Pablo Henrique
code for read VL53l0x sensor with CAN
Revision 1:7bbfe329c62b, committed 2019-03-18
- Comitter:
- pablo_bmxrp
- Date:
- Mon Mar 18 22:45:39 2019 +0000
- Parent:
- 0:44429c0a71d4
- Commit message:
- V1.0
Changed in this revision
--- a/STM32F103C8T6_MPA/.mbed Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1 +0,0 @@ -ROOT=.
--- a/STM32F103C8T6_MPA/GettingStarted.html Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,16 +0,0 @@ -<!DOCTYPE HTML> -<html lang="en-US"> - <head> - <meta charset="UTF-8"> - <meta http-equiv="refresh" - content="1;url="https://os.mbed.com/docs/latest/tools/exporting.html> - <script type="text/javascript"> - window.location.href = "https://os.mbed.com/docs/latest/tools/exporting.html" - </script> - <title>Page Redirection</title> - </head> - <body> - If you are not redirected automatically, please follow the - <a href='https://os.mbed.com/docs/v5.6/tools/exporting.html/'>link to the online exporter documentation</a> - </body> -</html>
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X.cpp Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,5554 +0,0 @@
-/**
- ******************************************************************************
- * @file VL53L0X_class.cpp
- * @author IMG
- * @version V0.0.1
- * @date 28-June-2016
- * @brief Implementation file for the VL53L0X driver class
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
-*/
-
-/* Includes */
-#include <stdlib.h>
-
-#include "VL53L0X.h"
-
-//#include "VL53L0X_api_core.h"
-//#include "VL53L0X_api_calibration.h"
-//#include "VL53L0X_api_strings.h"
-#include "VL53L0X_interrupt_threshold_settings.h"
-#include "VL53L0X_tuning.h"
-#include "VL53L0X_types.h"
-
-
-/****************** define for i2c configuration *******************************/
-
-#define TEMP_BUF_SIZE 64
-
-/** Maximum buffer size to be used in i2c */
-#define VL53L0X_MAX_I2C_XFER_SIZE 64 /* Maximum buffer size to be used in i2c */
-#define VL53L0X_I2C_USER_VAR /* none but could be for a flag var to get/pass to mutex interruptible return flags and try again */
-
-
-#define LOG_FUNCTION_START(fmt, ...) \
- _LOG_FUNCTION_START(TRACE_MODULE_API, fmt, ##__VA_ARGS__)
-#define LOG_FUNCTION_END(status, ...) \
- _LOG_FUNCTION_END(TRACE_MODULE_API, status, ##__VA_ARGS__)
-#define LOG_FUNCTION_END_FMT(status, fmt, ...) \
- _LOG_FUNCTION_END_FMT(TRACE_MODULE_API, status, fmt, ##__VA_ARGS__)
-
-#ifdef VL53L0X_LOG_ENABLE
-#define trace_print(level, ...) trace_print_module_function(TRACE_MODULE_API, \
- level, TRACE_FUNCTION_NONE, ##__VA_ARGS__)
-#endif
-
-#define REF_ARRAY_SPAD_0 0
-#define REF_ARRAY_SPAD_5 5
-#define REF_ARRAY_SPAD_10 10
-
-uint32_t refArrayQuadrants[4] = {REF_ARRAY_SPAD_10, REF_ARRAY_SPAD_5,
- REF_ARRAY_SPAD_0, REF_ARRAY_SPAD_5
- };
-
-
-
-
-VL53L0X_Error VL53L0X::VL53L0X_device_read_strobe(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t strobe;
- uint32_t loop_nb;
- LOG_FUNCTION_START("");
-
- status |= VL53L0X_write_byte(dev, 0x83, 0x00);
-
- /* polling
- * use timeout to avoid deadlock*/
- if (status == VL53L0X_ERROR_NONE) {
- loop_nb = 0;
- do {
- status = VL53L0X_read_byte(dev, 0x83, &strobe);
- if ((strobe != 0x00) || status != VL53L0X_ERROR_NONE) {
- break;
- }
-
- loop_nb = loop_nb + 1;
- } while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
-
- if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
- status = VL53L0X_ERROR_TIME_OUT;
- }
- }
-
- status |= VL53L0X_write_byte(dev, 0x83, 0x01);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_info_from_device(VL53L0X_DEV dev, uint8_t option)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t byte;
- uint32_t tmp_dword;
- uint8_t module_id;
- uint8_t revision;
- uint8_t reference_spad_count = 0;
- uint8_t reference_spad_type = 0;
- uint32_t part_uid_upper = 0;
- uint32_t part_uid_lower = 0;
- uint32_t offset_fixed1104_mm = 0;
- int16_t offset_micro_meters = 0;
- uint32_t dist_meas_tgt_fixed1104_mm = 400 << 4;
- uint32_t dist_meas_fixed1104_400_mm = 0;
- uint32_t signal_rate_meas_fixed1104_400_mm = 0;
- char product_id[19];
- char *product_id_tmp;
- uint8_t read_data_from_device_done;
- FixPoint1616_t signal_rate_meas_fixed400_mm_fix = 0;
- uint8_t nvm_ref_good_spad_map[VL53L0X_REF_SPAD_BUFFER_SIZE];
- int i;
-
-
- LOG_FUNCTION_START("");
-
- read_data_from_device_done = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
- ReadDataFromDeviceDone);
-
- /* This access is done only once after that a GetDeviceInfo or
- * datainit is done*/
- if (read_data_from_device_done != 7) {
-
- status |= VL53L0X_write_byte(dev, 0x80, 0x01);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
- status |= VL53L0X_write_byte(dev, 0x00, 0x00);
-
- status |= VL53L0X_write_byte(dev, 0xFF, 0x06);
- status |= VL53L0X_read_byte(dev, 0x83, &byte);
- status |= VL53L0X_write_byte(dev, 0x83, byte | 4);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x07);
- status |= VL53L0X_write_byte(dev, 0x81, 0x01);
-
- status |= VL53L0X_polling_delay(dev);
-
- status |= VL53L0X_write_byte(dev, 0x80, 0x01);
-
- if (((option & 1) == 1) &&
- ((read_data_from_device_done & 1) == 0)) {
- status |= VL53L0X_write_byte(dev, 0x94, 0x6b);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- reference_spad_count = (uint8_t)((tmp_dword >> 8) & 0x07f);
- reference_spad_type = (uint8_t)((tmp_dword >> 15) & 0x01);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x24);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
-
- nvm_ref_good_spad_map[0] = (uint8_t)((tmp_dword >> 24)
- & 0xff);
- nvm_ref_good_spad_map[1] = (uint8_t)((tmp_dword >> 16)
- & 0xff);
- nvm_ref_good_spad_map[2] = (uint8_t)((tmp_dword >> 8)
- & 0xff);
- nvm_ref_good_spad_map[3] = (uint8_t)(tmp_dword & 0xff);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x25);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- nvm_ref_good_spad_map[4] = (uint8_t)((tmp_dword >> 24)
- & 0xff);
- nvm_ref_good_spad_map[5] = (uint8_t)((tmp_dword >> 16)
- & 0xff);
- }
-
- if (((option & 2) == 2) &&
- ((read_data_from_device_done & 2) == 0)) {
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x02);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_byte(dev, 0x90, &module_id);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x7B);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_byte(dev, 0x90, &revision);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x77);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- product_id[0] = (char)((tmp_dword >> 25) & 0x07f);
- product_id[1] = (char)((tmp_dword >> 18) & 0x07f);
- product_id[2] = (char)((tmp_dword >> 11) & 0x07f);
- product_id[3] = (char)((tmp_dword >> 4) & 0x07f);
-
- byte = (uint8_t)((tmp_dword & 0x00f) << 3);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x78);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- product_id[4] = (char)(byte +
- ((tmp_dword >> 29) & 0x07f));
- product_id[5] = (char)((tmp_dword >> 22) & 0x07f);
- product_id[6] = (char)((tmp_dword >> 15) & 0x07f);
- product_id[7] = (char)((tmp_dword >> 8) & 0x07f);
- product_id[8] = (char)((tmp_dword >> 1) & 0x07f);
-
- byte = (uint8_t)((tmp_dword & 0x001) << 6);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x79);
-
- status |= VL53L0X_device_read_strobe(dev);
-
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- product_id[9] = (char)(byte +
- ((tmp_dword >> 26) & 0x07f));
- product_id[10] = (char)((tmp_dword >> 19) & 0x07f);
- product_id[11] = (char)((tmp_dword >> 12) & 0x07f);
- product_id[12] = (char)((tmp_dword >> 5) & 0x07f);
-
- byte = (uint8_t)((tmp_dword & 0x01f) << 2);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x7A);
-
- status |= VL53L0X_device_read_strobe(dev);
-
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- product_id[13] = (char)(byte +
- ((tmp_dword >> 30) & 0x07f));
- product_id[14] = (char)((tmp_dword >> 23) & 0x07f);
- product_id[15] = (char)((tmp_dword >> 16) & 0x07f);
- product_id[16] = (char)((tmp_dword >> 9) & 0x07f);
- product_id[17] = (char)((tmp_dword >> 2) & 0x07f);
- product_id[18] = '\0';
-
- }
-
- if (((option & 4) == 4) &&
- ((read_data_from_device_done & 4) == 0)) {
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x7B);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &part_uid_upper);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x7C);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &part_uid_lower);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x73);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- signal_rate_meas_fixed1104_400_mm = (tmp_dword &
- 0x0000000ff) << 8;
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x74);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- signal_rate_meas_fixed1104_400_mm |= ((tmp_dword &
- 0xff000000) >> 24);
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x75);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- dist_meas_fixed1104_400_mm = (tmp_dword & 0x0000000ff)
- << 8;
-
- status |= VL53L0X_write_byte(dev, 0x94, 0x76);
- status |= VL53L0X_device_read_strobe(dev);
- status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
-
- dist_meas_fixed1104_400_mm |= ((tmp_dword & 0xff000000)
- >> 24);
- }
-
- status |= VL53L0X_write_byte(dev, 0x81, 0x00);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x06);
- status |= VL53L0X_read_byte(dev, 0x83, &byte);
- status |= VL53L0X_write_byte(dev, 0x83, byte & 0xfb);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
- status |= VL53L0X_write_byte(dev, 0x00, 0x01);
-
- status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
- status |= VL53L0X_write_byte(dev, 0x80, 0x00);
- }
-
- if ((status == VL53L0X_ERROR_NONE) &&
- (read_data_from_device_done != 7)) {
- /* Assign to variable if status is ok */
- if (((option & 1) == 1) &&
- ((read_data_from_device_done & 1) == 0)) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadCount, reference_spad_count);
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadType, reference_spad_type);
-
- for (i = 0; i < VL53L0X_REF_SPAD_BUFFER_SIZE; i++) {
- dev->Data.SpadData.RefGoodSpadMap[i] =
- nvm_ref_good_spad_map[i];
- }
- }
-
- if (((option & 2) == 2) &&
- ((read_data_from_device_done & 2) == 0)) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- ModuleId, module_id);
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- Revision, revision);
-
- product_id_tmp = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
- ProductId);
- VL53L0X_COPYSTRING(product_id_tmp, product_id);
-
- }
-
- if (((option & 4) == 4) &&
- ((read_data_from_device_done & 4) == 0)) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- PartUIDUpper, part_uid_upper);
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- PartUIDLower, part_uid_lower);
-
- signal_rate_meas_fixed400_mm_fix =
- VL53L0X_FIXPOINT97TOFIXPOINT1616(
- signal_rate_meas_fixed1104_400_mm);
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- SignalRateMeasFixed400mm,
- signal_rate_meas_fixed400_mm_fix);
-
- offset_micro_meters = 0;
- if (dist_meas_fixed1104_400_mm != 0) {
- offset_fixed1104_mm =
- dist_meas_fixed1104_400_mm -
- dist_meas_tgt_fixed1104_mm;
- offset_micro_meters = (offset_fixed1104_mm
- * 1000) >> 4;
- offset_micro_meters *= -1;
- }
-
- PALDevDataSet(dev,
- Part2PartOffsetAdjustmentNVMMicroMeter,
- offset_micro_meters);
- }
- byte = (uint8_t)(read_data_from_device_done | option);
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev, ReadDataFromDeviceDone,
- byte);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t *p_offset_calibration_data_micro_meter)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint16_t range_offset_register;
- int16_t c_max_offset = 2047;
- int16_t c_offset_range = 4096;
-
- /* Note that offset has 10.2 format */
-
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
- &range_offset_register);
-
- if (status == VL53L0X_ERROR_NONE) {
- range_offset_register = (range_offset_register & 0x0fff);
-
- /* Apply 12 bit 2's compliment conversion */
- if (range_offset_register > c_max_offset) {
- *p_offset_calibration_data_micro_meter =
- (int16_t)(range_offset_register - c_offset_range)
- * 250;
- } else {
- *p_offset_calibration_data_micro_meter =
- (int16_t)range_offset_register * 250;
- }
-
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t *p_offset_calibration_data_micro_meter)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_get_offset_calibration_data_micro_meter(dev,
- p_offset_calibration_data_micro_meter);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t offset_calibration_data_micro_meter)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- int32_t c_max_offset_micro_meter = 511000;
- int32_t c_min_offset_micro_meter = -512000;
- int16_t c_offset_range = 4096;
- uint32_t encoded_offset_val;
-
- LOG_FUNCTION_START("");
-
- if (offset_calibration_data_micro_meter > c_max_offset_micro_meter) {
- offset_calibration_data_micro_meter = c_max_offset_micro_meter;
- } else {
- if (offset_calibration_data_micro_meter < c_min_offset_micro_meter) {
- offset_calibration_data_micro_meter = c_min_offset_micro_meter;
- }
- }
-
- /* The offset register is 10.2 format and units are mm
- * therefore conversion is applied by a division of
- * 250.
- */
- if (offset_calibration_data_micro_meter >= 0) {
- encoded_offset_val =
- offset_calibration_data_micro_meter / 250;
- } else {
- encoded_offset_val =
- c_offset_range +
- offset_calibration_data_micro_meter / 250;
- }
-
- status = VL53L0X_write_word(dev,
- VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
- encoded_offset_val);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t offset_calibration_data_micro_meter)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_set_offset_calibration_data_micro_meter(dev,
- offset_calibration_data_micro_meter);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_apply_offset_adjustment(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- int32_t corrected_offset_micro_meters;
- int32_t current_offset_micro_meters;
-
- /* if we run on this function we can read all the NVM info
- * used by the API */
- status = VL53L0X_get_info_from_device(dev, 7);
-
- /* Read back current device offset */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_offset_calibration_data_micro_meter(dev,
- ¤t_offset_micro_meters);
- }
-
- /* Apply Offset Adjustment derived from 400mm measurements */
- if (status == VL53L0X_ERROR_NONE) {
-
- /* Store initial device offset */
- PALDevDataSet(dev, Part2PartOffsetNVMMicroMeter,
- current_offset_micro_meters);
-
- corrected_offset_micro_meters = current_offset_micro_meters +
- (int32_t)PALDevDataGet(dev,
- Part2PartOffsetAdjustmentNVMMicroMeter);
-
- status = VL53L0X_set_offset_calibration_data_micro_meter(dev,
- corrected_offset_micro_meters);
-
- /* store current, adjusted offset */
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETPARAMETERFIELD(dev, RangeOffsetMicroMeters,
- corrected_offset_micro_meters);
- }
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_device_mode(VL53L0X_DEV dev,
- VL53L0X_DeviceModes *p_device_mode)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- VL53L0X_GETPARAMETERFIELD(dev, DeviceMode, *p_device_mode);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_inter_measurement_period_milli_seconds(VL53L0X_DEV dev,
- uint32_t *p_inter_measurement_period_milli_seconds)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint16_t osc_calibrate_val;
- uint32_t im_period_milli_seconds;
-
- LOG_FUNCTION_START("");
-
- status = VL53L0X_read_word(dev, VL53L0X_REG_OSC_CALIBRATE_VAL,
- &osc_calibrate_val);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_dword(dev,
- VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD,
- &im_period_milli_seconds);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- if (osc_calibrate_val != 0) {
- *p_inter_measurement_period_milli_seconds =
- im_period_milli_seconds / osc_calibrate_val;
- }
- VL53L0X_SETPARAMETERFIELD(dev,
- InterMeasurementPeriodMilliSeconds,
- *p_inter_measurement_period_milli_seconds);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_x_talk_compensation_rate_mega_cps(VL53L0X_DEV dev,
- FixPoint1616_t *p_xtalk_compensation_rate_mega_cps)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint16_t value;
- FixPoint1616_t temp_fix1616;
-
- LOG_FUNCTION_START("");
-
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS, (uint16_t *)&value);
- if (status == VL53L0X_ERROR_NONE) {
- if (value == 0) {
- /* the Xtalk is disabled return value from memory */
- VL53L0X_GETPARAMETERFIELD(dev,
- XTalkCompensationRateMegaCps, temp_fix1616);
- *p_xtalk_compensation_rate_mega_cps = temp_fix1616;
- VL53L0X_SETPARAMETERFIELD(dev, XTalkCompensationEnable,
- 0);
- } else {
- temp_fix1616 = VL53L0X_FIXPOINT313TOFIXPOINT1616(value);
- *p_xtalk_compensation_rate_mega_cps = temp_fix1616;
- VL53L0X_SETPARAMETERFIELD(dev,
- XTalkCompensationRateMegaCps, temp_fix1616);
- VL53L0X_SETPARAMETERFIELD(dev, XTalkCompensationEnable,
- 1);
- }
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
- FixPoint1616_t *p_limit_check_value)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t enable_zero_value = 0;
- uint16_t temp16;
- FixPoint1616_t temp_fix1616;
-
- LOG_FUNCTION_START("");
-
- switch (limit_check_id) {
-
- case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
- /* internal computation: */
- VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, temp_fix1616);
- enable_zero_value = 0;
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
- &temp16);
- if (status == VL53L0X_ERROR_NONE) {
- temp_fix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(temp16);
- }
-
-
- enable_zero_value = 1;
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
- /* internal computation: */
- VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, temp_fix1616);
- enable_zero_value = 0;
- break;
-
- case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
- /* internal computation: */
- VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, temp_fix1616);
- enable_zero_value = 0;
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
- &temp16);
- if (status == VL53L0X_ERROR_NONE) {
- temp_fix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(temp16);
- }
-
-
- enable_zero_value = 0;
- break;
-
- default:
- status = VL53L0X_ERROR_INVALID_PARAMS;
-
- }
-
- if (status == VL53L0X_ERROR_NONE) {
-
- if (enable_zero_value == 1) {
-
- if (temp_fix1616 == 0) {
- /* disabled: return value from memory */
- VL53L0X_GETARRAYPARAMETERFIELD(dev,
- LimitChecksValue, limit_check_id,
- temp_fix1616);
- *p_limit_check_value = temp_fix1616;
- VL53L0X_SETARRAYPARAMETERFIELD(dev,
- LimitChecksEnable, limit_check_id, 0);
- } else {
- *p_limit_check_value = temp_fix1616;
- VL53L0X_SETARRAYPARAMETERFIELD(dev,
- LimitChecksValue, limit_check_id,
- temp_fix1616);
- VL53L0X_SETARRAYPARAMETERFIELD(dev,
- LimitChecksEnable, limit_check_id, 1);
- }
- } else {
- *p_limit_check_value = temp_fix1616;
- }
- }
-
- LOG_FUNCTION_END(status);
- return status;
-
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
- uint8_t *p_limit_check_enable)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t temp8;
-
- LOG_FUNCTION_START("");
-
- if (limit_check_id >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
- status = VL53L0X_ERROR_INVALID_PARAMS;
- *p_limit_check_enable = 0;
- } else {
- VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
- limit_check_id, temp8);
- *p_limit_check_enable = temp8;
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_wrap_around_check_enable(VL53L0X_DEV dev,
- uint8_t *p_wrap_around_check_enable)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t data;
-
- LOG_FUNCTION_START("");
-
- status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, &data);
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, SequenceConfig, data);
- if (data & (0x01 << 7)) {
- *p_wrap_around_check_enable = 0x01;
- } else {
- *p_wrap_around_check_enable = 0x00;
- }
- }
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETPARAMETERFIELD(dev, WrapAroundCheckEnable,
- *p_wrap_around_check_enable);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::sequence_step_enabled(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_config,
- uint8_t *p_sequence_step_enabled)
-{
- VL53L0X_Error Status = VL53L0X_ERROR_NONE;
- *p_sequence_step_enabled = 0;
- LOG_FUNCTION_START("");
-
- switch (sequence_step_id) {
- case VL53L0X_SEQUENCESTEP_TCC:
- *p_sequence_step_enabled = (sequence_config & 0x10) >> 4;
- break;
- case VL53L0X_SEQUENCESTEP_DSS:
- *p_sequence_step_enabled = (sequence_config & 0x08) >> 3;
- break;
- case VL53L0X_SEQUENCESTEP_MSRC:
- *p_sequence_step_enabled = (sequence_config & 0x04) >> 2;
- break;
- case VL53L0X_SEQUENCESTEP_PRE_RANGE:
- *p_sequence_step_enabled = (sequence_config & 0x40) >> 6;
- break;
- case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
- *p_sequence_step_enabled = (sequence_config & 0x80) >> 7;
- break;
- default:
- Status = VL53L0X_ERROR_INVALID_PARAMS;
- }
-
- LOG_FUNCTION_END(status);
- return Status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_sequence_step_enables(VL53L0X_DEV dev,
- VL53L0X_SchedulerSequenceSteps_t *p_scheduler_sequence_steps)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t sequence_config = 0;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
- &sequence_config);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = sequence_step_enabled(dev,
- VL53L0X_SEQUENCESTEP_TCC, sequence_config,
- &p_scheduler_sequence_steps->TccOn);
- }
- if (status == VL53L0X_ERROR_NONE) {
- status = sequence_step_enabled(dev,
- VL53L0X_SEQUENCESTEP_DSS, sequence_config,
- &p_scheduler_sequence_steps->DssOn);
- }
- if (status == VL53L0X_ERROR_NONE) {
- status = sequence_step_enabled(dev,
- VL53L0X_SEQUENCESTEP_MSRC, sequence_config,
- &p_scheduler_sequence_steps->MsrcOn);
- }
- if (status == VL53L0X_ERROR_NONE) {
- status = sequence_step_enabled(dev,
- VL53L0X_SEQUENCESTEP_PRE_RANGE, sequence_config,
- &p_scheduler_sequence_steps->PreRangeOn);
- }
- if (status == VL53L0X_ERROR_NONE) {
- status = sequence_step_enabled(dev,
- VL53L0X_SEQUENCESTEP_FINAL_RANGE, sequence_config,
- &p_scheduler_sequence_steps->FinalRangeOn);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-uint8_t VL53L0X::VL53L0X_decode_vcsel_period(uint8_t vcsel_period_reg)
-{
- /*!
- * Converts the encoded VCSEL period register value into the real
- * period in PLL clocks
- */
-
- uint8_t vcsel_period_pclks = 0;
-
- vcsel_period_pclks = (vcsel_period_reg + 1) << 1;
-
- return vcsel_period_pclks;
-}
-
-uint8_t VL53L0X::lv53l0x_encode_vcsel_period(uint8_t vcsel_period_pclks)
-{
- /*!
- * Converts the encoded VCSEL period register value into the real period
- * in PLL clocks
- */
-
- uint8_t vcsel_period_reg = 0;
-
- vcsel_period_reg = (vcsel_period_pclks >> 1) - 1;
-
- return vcsel_period_reg;
-}
-
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period_pclk)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t vcsel_period_reg;
- uint8_t min_pre_vcsel_period_pclk = 12;
- uint8_t max_pre_vcsel_period_pclk = 18;
- uint8_t min_final_vcsel_period_pclk = 8;
- uint8_t max_final_vcsel_period_pclk = 14;
- uint32_t measurement_timing_budget_micro_seconds;
- uint32_t final_range_timeout_micro_seconds;
- uint32_t pre_range_timeout_micro_seconds;
- uint32_t msrc_timeout_micro_seconds;
- uint8_t phase_cal_int = 0;
-
- /* Check if valid clock period requested */
-
- if ((vcsel_pulse_period_pclk % 2) != 0) {
- /* Value must be an even number */
- status = VL53L0X_ERROR_INVALID_PARAMS;
- } else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_PRE_RANGE &&
- (vcsel_pulse_period_pclk < min_pre_vcsel_period_pclk ||
- vcsel_pulse_period_pclk > max_pre_vcsel_period_pclk)) {
- status = VL53L0X_ERROR_INVALID_PARAMS;
- } else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_FINAL_RANGE &&
- (vcsel_pulse_period_pclk < min_final_vcsel_period_pclk ||
- vcsel_pulse_period_pclk > max_final_vcsel_period_pclk)) {
-
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
-
- /* Apply specific settings for the requested clock period */
-
- if (status != VL53L0X_ERROR_NONE) {
- return status;
- }
-
-
- if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_PRE_RANGE) {
-
- /* Set phase check limits */
- if (vcsel_pulse_period_pclk == 12) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x18);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
- } else if (vcsel_pulse_period_pclk == 14) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x30);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
- } else if (vcsel_pulse_period_pclk == 16) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x40);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
- } else if (vcsel_pulse_period_pclk == 18) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x50);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
- }
- } else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_FINAL_RANGE) {
-
- if (vcsel_pulse_period_pclk == 8) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x10);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
-
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x02);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x0C);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x01);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_LIM,
- 0x30);
- status |= VL53L0X_write_byte(dev, 0xff, 0x00);
- } else if (vcsel_pulse_period_pclk == 10) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x28);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
-
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x09);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x01);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_LIM,
- 0x20);
- status |= VL53L0X_write_byte(dev, 0xff, 0x00);
- } else if (vcsel_pulse_period_pclk == 12) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x38);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
-
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x08);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x01);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_LIM,
- 0x20);
- status |= VL53L0X_write_byte(dev, 0xff, 0x00);
- } else if (vcsel_pulse_period_pclk == 14) {
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
- 0x048);
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
- 0x08);
-
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x07);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x01);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_ALGO_PHASECAL_LIM,
- 0x20);
- status |= VL53L0X_write_byte(dev, 0xff, 0x00);
- }
- }
-
-
- /* Re-calculate and apply timeouts, in macro periods */
-
- if (status == VL53L0X_ERROR_NONE) {
- vcsel_period_reg = lv53l0x_encode_vcsel_period((uint8_t)
- vcsel_pulse_period_pclk);
-
- /* When the VCSEL period for the pre or final range is changed,
- * the corresponding timeout must be read from the device using
- * the current VCSEL period, then the new VCSEL period can be
- * applied. The timeout then must be written back to the device
- * using the new VCSEL period.
- *
- * For the MSRC timeout, the same applies - this timeout being
- * dependant on the pre-range vcsel period.
- */
- switch (vcsel_period_type) {
- case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_PRE_RANGE,
- &pre_range_timeout_micro_seconds);
-
- if (status == VL53L0X_ERROR_NONE)
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_MSRC,
- &msrc_timeout_micro_seconds);
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
- vcsel_period_reg);
-
-
- if (status == VL53L0X_ERROR_NONE)
- status = set_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_PRE_RANGE,
- pre_range_timeout_micro_seconds);
-
-
- if (status == VL53L0X_ERROR_NONE)
- status = set_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_MSRC,
- msrc_timeout_micro_seconds);
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- PreRangeVcselPulsePeriod,
- vcsel_pulse_period_pclk);
- break;
- case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_FINAL_RANGE,
- &final_range_timeout_micro_seconds);
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
- vcsel_period_reg);
-
-
- if (status == VL53L0X_ERROR_NONE)
- status = set_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_FINAL_RANGE,
- final_range_timeout_micro_seconds);
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- FinalRangeVcselPulsePeriod,
- vcsel_pulse_period_pclk);
- break;
- default:
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- }
-
- /* Finally, the timing budget must be re-applied */
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_GETPARAMETERFIELD(dev,
- MeasurementTimingBudgetMicroSeconds,
- measurement_timing_budget_micro_seconds);
-
- status = VL53L0X_set_measurement_timing_budget_micro_seconds(dev,
- measurement_timing_budget_micro_seconds);
- }
-
- /* Perform the phase calibration. This is needed after changing on
- * vcsel period.
- * get_data_enable = 0, restore_config = 1 */
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_perform_phase_calibration(
- dev, &phase_cal_int, 0, 1);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_set_vcsel_pulse_period(dev, vcsel_period_type,
- vcsel_pulse_period);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t vcsel_period_reg;
-
- switch (vcsel_period_type) {
- case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
- status = VL53L0X_read_byte(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
- &vcsel_period_reg);
- break;
- case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
- status = VL53L0X_read_byte(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
- &vcsel_period_reg);
- break;
- default:
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
-
- if (status == VL53L0X_ERROR_NONE)
- *p_vcsel_pulse_period_pclk =
- VL53L0X_decode_vcsel_period(vcsel_period_reg);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_get_vcsel_pulse_period(dev, vcsel_period_type,
- p_vcsel_pulse_period_pclk);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-uint32_t VL53L0X::VL53L0X_decode_timeout(uint16_t encoded_timeout)
-{
- /*!
- * Decode 16-bit timeout register value - format (LSByte * 2^MSByte) + 1
- */
-
- uint32_t timeout_macro_clks = 0;
-
- timeout_macro_clks = ((uint32_t)(encoded_timeout & 0x00FF)
- << (uint32_t)((encoded_timeout & 0xFF00) >> 8)) + 1;
-
- return timeout_macro_clks;
-}
-
-uint32_t VL53L0X::VL53L0X_calc_macro_period_ps(VL53L0X_DEV dev, uint8_t vcsel_period_pclks)
-{
- uint64_t pll_period_ps;
- uint32_t macro_period_vclks;
- uint32_t macro_period_ps;
-
- LOG_FUNCTION_START("");
-
- /* The above calculation will produce rounding errors,
- therefore set fixed value
- */
- pll_period_ps = 1655;
-
- macro_period_vclks = 2304;
- macro_period_ps = (uint32_t)(macro_period_vclks
- * vcsel_period_pclks * pll_period_ps);
-
- LOG_FUNCTION_END("");
- return macro_period_ps;
-}
-
-/* To convert register value into us */
-uint32_t VL53L0X::VL53L0X_calc_timeout_us(VL53L0X_DEV dev,
- uint16_t timeout_period_mclks,
- uint8_t vcsel_period_pclks)
-{
- uint32_t macro_period_ps;
- uint32_t macro_period_ns;
- uint32_t actual_timeout_period_us = 0;
-
- macro_period_ps = VL53L0X_calc_macro_period_ps(dev, vcsel_period_pclks);
- macro_period_ns = (macro_period_ps + 500) / 1000;
-
- actual_timeout_period_us =
- ((timeout_period_mclks * macro_period_ns) + 500) / 1000;
-
- return actual_timeout_period_us;
-}
-
-VL53L0X_Error VL53L0X::get_sequence_step_timeout(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id,
- uint32_t *p_time_out_micro_secs)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t current_vcsel_pulse_period_p_clk;
- uint8_t encoded_time_out_byte = 0;
- uint32_t timeout_micro_seconds = 0;
- uint16_t pre_range_encoded_time_out = 0;
- uint16_t msrc_time_out_m_clks;
- uint16_t pre_range_time_out_m_clks;
- uint16_t final_range_time_out_m_clks = 0;
- uint16_t final_range_encoded_time_out;
- VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
-
- if ((sequence_step_id == VL53L0X_SEQUENCESTEP_TCC) ||
- (sequence_step_id == VL53L0X_SEQUENCESTEP_DSS) ||
- (sequence_step_id == VL53L0X_SEQUENCESTEP_MSRC)) {
-
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_byte(dev,
- VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
- &encoded_time_out_byte);
- }
- msrc_time_out_m_clks = VL53L0X_decode_timeout(encoded_time_out_byte);
-
- timeout_micro_seconds = VL53L0X_calc_timeout_us(dev,
- msrc_time_out_m_clks,
- current_vcsel_pulse_period_p_clk);
- } else if (sequence_step_id == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
- /* Retrieve PRE-RANGE VCSEL Period */
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
-
- /* Retrieve PRE-RANGE Timeout in Macro periods (MCLKS) */
- if (status == VL53L0X_ERROR_NONE) {
-
- /* Retrieve PRE-RANGE VCSEL Period */
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
- &pre_range_encoded_time_out);
- }
-
- pre_range_time_out_m_clks = VL53L0X_decode_timeout(
- pre_range_encoded_time_out);
-
- timeout_micro_seconds = VL53L0X_calc_timeout_us(dev,
- pre_range_time_out_m_clks,
- current_vcsel_pulse_period_p_clk);
- }
- } else if (sequence_step_id == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
-
- VL53L0X_get_sequence_step_enables(dev, &scheduler_sequence_steps);
- pre_range_time_out_m_clks = 0;
-
- if (scheduler_sequence_steps.PreRangeOn) {
- /* Retrieve PRE-RANGE VCSEL Period */
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
-
- /* Retrieve PRE-RANGE Timeout in Macro periods
- * (MCLKS) */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
- &pre_range_encoded_time_out);
- pre_range_time_out_m_clks = VL53L0X_decode_timeout(
- pre_range_encoded_time_out);
- }
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- /* Retrieve FINAL-RANGE VCSEL Period */
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
- }
-
- /* Retrieve FINAL-RANGE Timeout in Macro periods (MCLKS) */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
- &final_range_encoded_time_out);
- final_range_time_out_m_clks = VL53L0X_decode_timeout(
- final_range_encoded_time_out);
- }
-
- final_range_time_out_m_clks -= pre_range_time_out_m_clks;
- timeout_micro_seconds = VL53L0X_calc_timeout_us(dev,
- final_range_time_out_m_clks,
- current_vcsel_pulse_period_p_clk);
- }
-
- *p_time_out_micro_secs = timeout_micro_seconds;
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t *p_measurement_timing_budget_micro_seconds)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
- uint32_t final_range_timeout_micro_seconds;
- uint32_t msrc_dcc_tcc_timeout_micro_seconds = 2000;
- uint32_t start_overhead_micro_seconds = 1910;
- uint32_t end_overhead_micro_seconds = 960;
- uint32_t msrc_overhead_micro_seconds = 660;
- uint32_t tcc_overhead_micro_seconds = 590;
- uint32_t dss_overhead_micro_seconds = 690;
- uint32_t pre_range_overhead_micro_seconds = 660;
- uint32_t final_range_overhead_micro_seconds = 550;
- uint32_t pre_range_timeout_micro_seconds = 0;
-
- LOG_FUNCTION_START("");
-
- /* Start and end overhead times always present */
- *p_measurement_timing_budget_micro_seconds
- = start_overhead_micro_seconds + end_overhead_micro_seconds;
-
- status = VL53L0X_get_sequence_step_enables(dev, &scheduler_sequence_steps);
-
- if (status != VL53L0X_ERROR_NONE) {
- LOG_FUNCTION_END(status);
- return status;
- }
-
-
- if (scheduler_sequence_steps.TccOn ||
- scheduler_sequence_steps.MsrcOn ||
- scheduler_sequence_steps.DssOn) {
-
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_MSRC,
- &msrc_dcc_tcc_timeout_micro_seconds);
-
- if (status == VL53L0X_ERROR_NONE) {
- if (scheduler_sequence_steps.TccOn) {
- *p_measurement_timing_budget_micro_seconds +=
- msrc_dcc_tcc_timeout_micro_seconds +
- tcc_overhead_micro_seconds;
- }
-
- if (scheduler_sequence_steps.DssOn) {
- *p_measurement_timing_budget_micro_seconds +=
- 2 * (msrc_dcc_tcc_timeout_micro_seconds +
- dss_overhead_micro_seconds);
- } else if (scheduler_sequence_steps.MsrcOn) {
- *p_measurement_timing_budget_micro_seconds +=
- msrc_dcc_tcc_timeout_micro_seconds +
- msrc_overhead_micro_seconds;
- }
- }
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- if (scheduler_sequence_steps.PreRangeOn) {
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_PRE_RANGE,
- &pre_range_timeout_micro_seconds);
- *p_measurement_timing_budget_micro_seconds +=
- pre_range_timeout_micro_seconds +
- pre_range_overhead_micro_seconds;
- }
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- if (scheduler_sequence_steps.FinalRangeOn) {
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_FINAL_RANGE,
- &final_range_timeout_micro_seconds);
- *p_measurement_timing_budget_micro_seconds +=
- (final_range_timeout_micro_seconds +
- final_range_overhead_micro_seconds);
- }
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETPARAMETERFIELD(dev,
- MeasurementTimingBudgetMicroSeconds,
- *p_measurement_timing_budget_micro_seconds);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t *p_measurement_timing_budget_micro_seconds)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(dev,
- p_measurement_timing_budget_micro_seconds);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_device_parameters(VL53L0X_DEV dev,
- VL53L0X_DeviceParameters_t *p_device_parameters)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- int i;
-
- LOG_FUNCTION_START("");
-
- status = VL53L0X_get_device_mode(dev, &(p_device_parameters->DeviceMode));
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_get_inter_measurement_period_milli_seconds(dev,
- &(p_device_parameters->InterMeasurementPeriodMilliSeconds));
-
-
- if (status == VL53L0X_ERROR_NONE) {
- p_device_parameters->XTalkCompensationEnable = 0;
- }
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_get_x_talk_compensation_rate_mega_cps(dev,
- &(p_device_parameters->XTalkCompensationRateMegaCps));
-
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_get_offset_calibration_data_micro_meter(dev,
- &(p_device_parameters->RangeOffsetMicroMeters));
-
-
- if (status == VL53L0X_ERROR_NONE) {
- for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
- /* get first the values, then the enables.
- * VL53L0X_GetLimitCheckValue will modify the enable
- * flags
- */
- if (status == VL53L0X_ERROR_NONE) {
- status |= VL53L0X_get_limit_check_value(dev, i,
- &(p_device_parameters->LimitChecksValue[i]));
- } else {
- break;
- }
- if (status == VL53L0X_ERROR_NONE) {
- status |= VL53L0X_get_limit_check_enable(dev, i,
- &(p_device_parameters->LimitChecksEnable[i]));
- } else {
- break;
- }
- }
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_wrap_around_check_enable(dev,
- &(p_device_parameters->WrapAroundCheckEnable));
- }
-
- /* Need to be done at the end as it uses VCSELPulsePeriod */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_measurement_timing_budget_micro_seconds(dev,
- &(p_device_parameters->MeasurementTimingBudgetMicroSeconds));
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
- FixPoint1616_t limit_check_value)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t temp8;
-
- LOG_FUNCTION_START("");
-
- VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksEnable, limit_check_id,
- temp8);
-
- if (temp8 == 0) { /* disabled write only internal value */
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- limit_check_id, limit_check_value);
- } else {
-
- switch (limit_check_id) {
-
- case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
- /* internal computation: */
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
- limit_check_value);
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
-
- status = VL53L0X_write_word(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
- VL53L0X_FIXPOINT1616TOFIXPOINT97(
- limit_check_value));
-
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
-
- /* internal computation: */
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
- limit_check_value);
-
- break;
-
- case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
-
- /* internal computation: */
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
- limit_check_value);
-
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
-
- status = VL53L0X_write_word(dev,
- VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
- VL53L0X_FIXPOINT1616TOFIXPOINT97(
- limit_check_value));
-
- break;
-
- default:
- status = VL53L0X_ERROR_INVALID_PARAMS;
-
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- limit_check_id, limit_check_value);
- }
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_data_init(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- VL53L0X_DeviceParameters_t CurrentParameters;
- int i;
- uint8_t StopVariable;
-
- LOG_FUNCTION_START("");
-
- /* by default the I2C is running at 1V8 if you want to change it you
- * need to include this define at compilation level. */
-#ifdef USE_I2C_2V8
-#if ORIGINAL
- Status = VL53L0X_UpdateByte(Dev,
- VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
- 0xFE,
- 0x01);
-#else
- status = VL53L0X_update_byte(dev,
- VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
- 0xFE,
- 0x01);
-#endif
-#endif
-
- /* Set I2C standard mode */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0x88, 0x00);
- }
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev, ReadDataFromDeviceDone, 0);
-
-#ifdef USE_IQC_STATION
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_apply_offset_adjustment(Dev);
- }
-#endif
-
- /* Default value is 1000 for Linearity Corrective Gain */
- PALDevDataSet(dev, LinearityCorrectiveGain, 1000);
-
- /* Dmax default Parameter */
- PALDevDataSet(dev, DmaxCalRangeMilliMeter, 400);
- PALDevDataSet(dev, DmaxCalSignalRateRtnMegaCps,
- (FixPoint1616_t)((0x00016B85))); /* 1.42 No Cover Glass*/
-
- /* Set Default static parameters
- *set first temporary values 9.44MHz * 65536 = 618660 */
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev, OscFrequencyMHz, 618660);
-
- /* Set Default XTalkCompensationRateMegaCps to 0 */
- VL53L0X_SETPARAMETERFIELD(dev, XTalkCompensationRateMegaCps, 0);
-
- /* Get default parameters */
- status = VL53L0X_get_device_parameters(dev, &CurrentParameters);
- if (status == VL53L0X_ERROR_NONE) {
- /* initialize PAL values */
- CurrentParameters.DeviceMode = VL53L0X_DEVICEMODE_SINGLE_RANGING;
- CurrentParameters.HistogramMode = VL53L0X_HISTOGRAMMODE_DISABLED;
- PALDevDataSet(dev, CurrentParameters, CurrentParameters);
- }
-
- /* Sigma estimator variable */
- PALDevDataSet(dev, SigmaEstRefArray, 100);
- PALDevDataSet(dev, SigmaEstEffPulseWidth, 900);
- PALDevDataSet(dev, SigmaEstEffAmbWidth, 500);
- PALDevDataSet(dev, targetRefRate, 0x0A00); /* 20 MCPS in 9:7 format */
-
- /* Use internal default settings */
- PALDevDataSet(dev, UseInternalTuningSettings, 1);
-
- status |= VL53L0X_write_byte(dev, 0x80, 0x01);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
- status |= VL53L0X_write_byte(dev, 0x00, 0x00);
- status |= VL53L0X_read_byte(dev, 0x91, &StopVariable);
- PALDevDataSet(dev, StopVariable, StopVariable);
- status |= VL53L0X_write_byte(dev, 0x00, 0x01);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
- status |= VL53L0X_write_byte(dev, 0x80, 0x00);
-
- /* Enable all check */
- for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
- if (status == VL53L0X_ERROR_NONE) {
- status |= VL53L0X_set_limit_check_enable(dev, i, 1);
- } else {
- break;
- }
-
- }
-
- /* Disable the following checks */
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_set_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, 0);
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_set_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, 0);
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_set_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC, 0);
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_set_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE, 0);
-
- /* Limit default values */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_set_limit_check_value(dev,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
- (FixPoint1616_t)(18 * 65536));
- }
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_set_limit_check_value(dev,
- VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
- (FixPoint1616_t)(25 * 65536 / 100));
- /* 0.25 * 65536 */
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_set_limit_check_value(dev,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
- (FixPoint1616_t)(35 * 65536));
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_set_limit_check_value(dev,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
- (FixPoint1616_t)(0 * 65536));
- }
-
- if (status == VL53L0X_ERROR_NONE) {
-
- PALDevDataSet(dev, SequenceConfig, 0xFF);
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
- 0xFF);
-
- /* Set PAL state to tell that we are waiting for call to
- * VL53L0X_StaticInit */
- PALDevDataSet(dev, PalState, VL53L0X_STATE_WAIT_STATICINIT);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev, RefSpadsInitialised, 0);
- }
-
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_check_part_used(VL53L0X_DEV dev,
- uint8_t *revision,
- VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t module_id_int;
- char *product_id_tmp;
-
- LOG_FUNCTION_START("");
-
- status = VL53L0X_get_info_from_device(dev, 2);
-
- if (status == VL53L0X_ERROR_NONE) {
- module_id_int = VL53L0X_GETDEVICESPECIFICPARAMETER(dev, ModuleId);
-
- if (module_id_int == 0) {
- *revision = 0;
- VL53L0X_COPYSTRING(p_VL53L0X_device_info->ProductId, "");
- } else {
- *revision = VL53L0X_GETDEVICESPECIFICPARAMETER(dev, Revision);
- product_id_tmp = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
- ProductId);
- VL53L0X_COPYSTRING(p_VL53L0X_device_info->ProductId, product_id_tmp);
- }
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_device_info(VL53L0X_DEV dev,
- VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t revision_id;
- uint8_t revision;
-
- status = VL53L0X_check_part_used(dev, &revision, p_VL53L0X_device_info);
-
- if (status == VL53L0X_ERROR_NONE) {
- if (revision == 0) {
- VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
- VL53L0X_STRING_DEVICE_INFO_NAME_TS0);
- } else if ((revision <= 34) && (revision != 32)) {
- VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
- VL53L0X_STRING_DEVICE_INFO_NAME_TS1);
- } else if (revision < 39) {
- VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
- VL53L0X_STRING_DEVICE_INFO_NAME_TS2);
- } else {
- VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
- VL53L0X_STRING_DEVICE_INFO_NAME_ES1);
- }
-
- VL53L0X_COPYSTRING(p_VL53L0X_device_info->Type,
- VL53L0X_STRING_DEVICE_INFO_TYPE);
-
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_byte(dev, VL53L0X_REG_IDENTIFICATION_MODEL_ID,
- &p_VL53L0X_device_info->ProductType);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_byte(dev,
- VL53L0X_REG_IDENTIFICATION_REVISION_ID,
- &revision_id);
- p_VL53L0X_device_info->ProductRevisionMajor = 1;
- p_VL53L0X_device_info->ProductRevisionMinor =
- (revision_id & 0xF0) >> 4;
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_device_info(VL53L0X_DEV dev,
- VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_get_device_info(dev, p_VL53L0X_device_info);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_interrupt_mask_status(VL53L0X_DEV dev,
- uint32_t *p_interrupt_mask_status)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t byte;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_read_byte(dev, VL53L0X_REG_RESULT_INTERRUPT_STATUS, &byte);
- *p_interrupt_mask_status = byte & 0x07;
-
- if (byte & 0x18) {
- status = VL53L0X_ERROR_RANGE_ERROR;
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_measurement_data_ready(VL53L0X_DEV dev,
- uint8_t *p_measurement_data_ready)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t sys_range_status_register;
- uint8_t interrupt_config;
- uint32_t interrupt_mask;
- LOG_FUNCTION_START("");
-
- interrupt_config = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
- Pin0GpioFunctionality);
-
- if (interrupt_config ==
- VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY) {
- status = VL53L0X_get_interrupt_mask_status(dev, &interrupt_mask);
- if (interrupt_mask ==
- VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY) {
- *p_measurement_data_ready = 1;
- } else {
- *p_measurement_data_ready = 0;
- }
- } else {
- status = VL53L0X_read_byte(dev, VL53L0X_REG_RESULT_RANGE_STATUS,
- &sys_range_status_register);
- if (status == VL53L0X_ERROR_NONE) {
- if (sys_range_status_register & 0x01) {
- *p_measurement_data_ready = 1;
- } else {
- *p_measurement_data_ready = 0;
- }
- }
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_polling_delay(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
-
- // do nothing
- VL53L0X_OsDelay();
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_measurement_poll_for_completion(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t new_data_ready = 0;
- uint32_t loop_nb;
-
- LOG_FUNCTION_START("");
-
- loop_nb = 0;
-
- do {
- status = VL53L0X_get_measurement_data_ready(dev, &new_data_ready);
- if (status != 0) {
- break; /* the error is set */
- }
-
- if (new_data_ready == 1) {
- break; /* done note that status == 0 */
- }
-
- loop_nb++;
- if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
- status = VL53L0X_ERROR_TIME_OUT;
- break;
- }
-
- VL53L0X_polling_delay(dev);
- } while (1);
-
- LOG_FUNCTION_END(status);
-
- return status;
-}
-
-/* Group PAL Interrupt Functions */
-VL53L0X_Error VL53L0X::VL53L0X_clear_interrupt_mask(VL53L0X_DEV dev, uint32_t interrupt_mask)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t loop_count;
- uint8_t byte;
- LOG_FUNCTION_START("");
-
- /* clear bit 0 range interrupt, bit 1 error interrupt */
- loop_count = 0;
- do {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR, 0x01);
- status |= VL53L0X_write_byte(dev,
- VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR, 0x00);
- status |= VL53L0X_read_byte(dev,
- VL53L0X_REG_RESULT_INTERRUPT_STATUS, &byte);
- loop_count++;
- } while (((byte & 0x07) != 0x00)
- && (loop_count < 3)
- && (status == VL53L0X_ERROR_NONE));
-
-
- if (loop_count >= 3) {
- status = VL53L0X_ERROR_INTERRUPT_NOT_CLEARED;
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_perform_single_ref_calibration(VL53L0X_DEV dev,
- uint8_t vhv_init_byte)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START,
- VL53L0X_REG_SYSRANGE_MODE_START_STOP |
- vhv_init_byte);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_measurement_poll_for_completion(dev);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_clear_interrupt_mask(dev, 0);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START, 0x00);
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_ref_calibration_io(VL53L0X_DEV dev, uint8_t read_not_write,
- uint8_t vhv_settings, uint8_t phase_cal,
- uint8_t *p_vhv_settings, uint8_t *p_phase_cal,
- const uint8_t vhv_enable, const uint8_t phase_enable)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t phase_calint = 0;
-
- /* Read VHV from device */
- status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
- status |= VL53L0X_write_byte(dev, 0x00, 0x00);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
-
- if (read_not_write) {
- if (vhv_enable) {
- status |= VL53L0X_read_byte(dev, 0xCB, p_vhv_settings);
- }
- if (phase_enable) {
- status |= VL53L0X_read_byte(dev, 0xEE, &phase_calint);
- }
- } else {
- if (vhv_enable) {
- status |= VL53L0X_write_byte(dev, 0xCB, vhv_settings);
- }
- if (phase_enable) {
- status |= VL53L0X_update_byte(dev, 0xEE, 0x80, phase_cal);
- }
- }
-
- status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
- status |= VL53L0X_write_byte(dev, 0x00, 0x01);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
-
- *p_phase_cal = (uint8_t)(phase_calint & 0xEF);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_perform_vhv_calibration(VL53L0X_DEV dev,
- uint8_t *p_vhv_settings, const uint8_t get_data_enable,
- const uint8_t restore_config)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t sequence_config = 0;
- uint8_t vhv_settings = 0;
- uint8_t phase_cal = 0;
- uint8_t phase_cal_int = 0;
-
- /* store the value of the sequence config,
- * this will be reset before the end of the function
- */
-
- if (restore_config) {
- sequence_config = PALDevDataGet(dev, SequenceConfig);
- }
-
- /* Run VHV */
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0x01);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_perform_single_ref_calibration(dev, 0x40);
- }
-
- /* Read VHV from device */
- if ((status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
- status = VL53L0X_ref_calibration_io(dev, 1,
- vhv_settings, phase_cal, /* Not used here */
- p_vhv_settings, &phase_cal_int,
- 1, 0);
- } else {
- *p_vhv_settings = 0;
- }
-
-
- if ((status == VL53L0X_ERROR_NONE) && restore_config) {
- /* restore the previous Sequence Config */
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
- sequence_config);
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, SequenceConfig, sequence_config);
- }
-
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_perform_phase_calibration(VL53L0X_DEV dev,
- uint8_t *p_phase_cal, const uint8_t get_data_enable,
- const uint8_t restore_config)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t sequence_config = 0;
- uint8_t vhv_settings = 0;
- uint8_t phase_cal = 0;
- uint8_t vhv_settingsint;
-
- /* store the value of the sequence config,
- * this will be reset before the end of the function
- */
-
- if (restore_config) {
- sequence_config = PALDevDataGet(dev, SequenceConfig);
- }
-
- /* Run PhaseCal */
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0x02);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_perform_single_ref_calibration(dev, 0x0);
- }
-
- /* Read PhaseCal from device */
- if ((status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
- status = VL53L0X_ref_calibration_io(dev, 1,
- vhv_settings, phase_cal, /* Not used here */
- &vhv_settingsint, p_phase_cal,
- 0, 1);
- } else {
- *p_phase_cal = 0;
- }
-
-
- if ((status == VL53L0X_ERROR_NONE) && restore_config) {
- /* restore the previous Sequence Config */
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
- sequence_config);
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, SequenceConfig, sequence_config);
- }
-
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_perform_ref_calibration(VL53L0X_DEV dev,
- uint8_t *p_vhv_settings, uint8_t *p_phase_cal, uint8_t get_data_enable)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t sequence_config = 0;
-
- /* store the value of the sequence config,
- * this will be reset before the end of the function
- */
-
- sequence_config = PALDevDataGet(dev, SequenceConfig);
-
- /* In the following function we don't save the config to optimize
- * writes on device. Config is saved and restored only once. */
- status = VL53L0X_perform_vhv_calibration(
- dev, p_vhv_settings, get_data_enable, 0);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_perform_phase_calibration(
- dev, p_phase_cal, get_data_enable, 0);
- }
-
-
- if (status == VL53L0X_ERROR_NONE) {
- /* restore the previous Sequence Config */
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
- sequence_config);
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, SequenceConfig, sequence_config);
- }
-
- }
-
- return status;
-}
-
-void VL53L0X::get_next_good_spad(uint8_t good_spad_array[], uint32_t size,
- uint32_t curr, int32_t *p_next)
-{
- uint32_t start_index;
- uint32_t fine_offset;
- uint32_t c_spads_per_byte = 8;
- uint32_t coarse_index;
- uint32_t fine_index;
- uint8_t data_byte;
- uint8_t success = 0;
-
- /*
- * Starting with the current good spad, loop through the array to find
- * the next. i.e. the next bit set in the sequence.
- *
- * The coarse index is the byte index of the array and the fine index is
- * the index of the bit within each byte.
- */
-
- *p_next = -1;
-
- start_index = curr / c_spads_per_byte;
- fine_offset = curr % c_spads_per_byte;
-
- for (coarse_index = start_index; ((coarse_index < size) && !success);
- coarse_index++) {
- fine_index = 0;
- data_byte = good_spad_array[coarse_index];
-
- if (coarse_index == start_index) {
- /* locate the bit position of the provided current
- * spad bit before iterating */
- data_byte >>= fine_offset;
- fine_index = fine_offset;
- }
-
- while (fine_index < c_spads_per_byte) {
- if ((data_byte & 0x1) == 1) {
- success = 1;
- *p_next = coarse_index * c_spads_per_byte + fine_index;
- break;
- }
- data_byte >>= 1;
- fine_index++;
- }
- }
-}
-
-uint8_t VL53L0X::is_aperture(uint32_t spad_index)
-{
- /*
- * This function reports if a given spad index is an aperture SPAD by
- * deriving the quadrant.
- */
- uint32_t quadrant;
- uint8_t is_aperture = 1;
- quadrant = spad_index >> 6;
- if (refArrayQuadrants[quadrant] == REF_ARRAY_SPAD_0) {
- is_aperture = 0;
- }
-
- return is_aperture;
-}
-
-VL53L0X_Error VL53L0X::enable_spad_bit(uint8_t spad_array[], uint32_t size,
- uint32_t spad_index)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint32_t c_spads_per_byte = 8;
- uint32_t coarse_index;
- uint32_t fine_index;
-
- coarse_index = spad_index / c_spads_per_byte;
- fine_index = spad_index % c_spads_per_byte;
- if (coarse_index >= size) {
- status = VL53L0X_ERROR_REF_SPAD_INIT;
- } else {
- spad_array[coarse_index] |= (1 << fine_index);
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::set_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array)
-{
- VL53L0X_Error status = VL53L0X_write_multi(dev,
- VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
- p_ref_spad_array, 6);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::get_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array)
-{
- VL53L0X_Error status = VL53L0X_read_multi(dev,
- VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
- p_ref_spad_array,
- 6);
-// VL53L0X_Error status = VL53L0X_ERROR_NONE;
-// uint8_t count=0;
-
-// for (count = 0; count < 6; count++)
-// status = VL53L0X_RdByte(Dev, (VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 + count), &refSpadArray[count]);
- return status;
-}
-
-VL53L0X_Error VL53L0X::enable_ref_spads(VL53L0X_DEV dev,
- uint8_t aperture_spads,
- uint8_t good_spad_array[],
- uint8_t spad_array[],
- uint32_t size,
- uint32_t start,
- uint32_t offset,
- uint32_t spad_count,
- uint32_t *p_last_spad)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint32_t index;
- uint32_t i;
- int32_t next_good_spad = offset;
- uint32_t current_spad;
- uint8_t check_spad_array[6];
-
- /*
- * This function takes in a spad array which may or may not have SPADS
- * already enabled and appends from a given offset a requested number
- * of new SPAD enables. The 'good spad map' is applied to
- * determine the next SPADs to enable.
- *
- * This function applies to only aperture or only non-aperture spads.
- * Checks are performed to ensure this.
- */
-
- current_spad = offset;
- for (index = 0; index < spad_count; index++) {
- get_next_good_spad(good_spad_array, size, current_spad,
- &next_good_spad);
-
- if (next_good_spad == -1) {
- status = VL53L0X_ERROR_REF_SPAD_INIT;
- break;
- }
-
- /* Confirm that the next good SPAD is non-aperture */
- if (is_aperture(start + next_good_spad) != aperture_spads) {
- /* if we can't get the required number of good aperture
- * spads from the current quadrant then this is an error
- */
- status = VL53L0X_ERROR_REF_SPAD_INIT;
- break;
- }
- current_spad = (uint32_t)next_good_spad;
- enable_spad_bit(spad_array, size, current_spad);
- current_spad++;
- }
- *p_last_spad = current_spad;
-
- if (status == VL53L0X_ERROR_NONE) {
- status = set_ref_spad_map(dev, spad_array);
- }
-
-
- if (status == VL53L0X_ERROR_NONE) {
- status = get_ref_spad_map(dev, check_spad_array);
-
- i = 0;
-
- /* Compare spad maps. If not equal report error. */
- while (i < size) {
- if (spad_array[i] != check_spad_array[i]) {
- status = VL53L0X_ERROR_REF_SPAD_INIT;
- break;
- }
- i++;
- }
- }
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_device_mode(VL53L0X_DEV dev, VL53L0X_DeviceModes device_mode)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
-
- LOG_FUNCTION_START("%d", (int)DeviceMode);
-
- switch (device_mode) {
- case VL53L0X_DEVICEMODE_SINGLE_RANGING:
- case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
- case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
- case VL53L0X_DEVICEMODE_GPIO_DRIVE:
- case VL53L0X_DEVICEMODE_GPIO_OSC:
- /* Supported modes */
- VL53L0X_SETPARAMETERFIELD(dev, DeviceMode, device_mode);
- break;
- default:
- /* Unsupported mode */
- status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_interrupt_thresholds(VL53L0X_DEV dev,
- VL53L0X_DeviceModes device_mode, FixPoint1616_t threshold_low,
- FixPoint1616_t threshold_high)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint16_t threshold16;
- LOG_FUNCTION_START("");
-
- /* no dependency on DeviceMode for Ewok */
- /* Need to divide by 2 because the FW will apply a x2 */
- threshold16 = (uint16_t)((threshold_low >> 17) & 0x00fff);
- status = VL53L0X_write_word(dev, VL53L0X_REG_SYSTEM_THRESH_LOW, threshold16);
-
- if (status == VL53L0X_ERROR_NONE) {
- /* Need to divide by 2 because the FW will apply a x2 */
- threshold16 = (uint16_t)((threshold_high >> 17) & 0x00fff);
- status = VL53L0X_write_word(dev, VL53L0X_REG_SYSTEM_THRESH_HIGH,
- threshold16);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_interrupt_thresholds(VL53L0X_DEV dev,
- VL53L0X_DeviceModes device_mode, FixPoint1616_t *p_threshold_low,
- FixPoint1616_t *p_threshold_high)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint16_t threshold16;
- LOG_FUNCTION_START("");
-
- /* no dependency on DeviceMode for Ewok */
-
- status = VL53L0X_read_word(dev, VL53L0X_REG_SYSTEM_THRESH_LOW, &threshold16);
- /* Need to multiply by 2 because the FW will apply a x2 */
- *p_threshold_low = (FixPoint1616_t)((0x00fff & threshold16) << 17);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_word(dev, VL53L0X_REG_SYSTEM_THRESH_HIGH,
- &threshold16);
- /* Need to multiply by 2 because the FW will apply a x2 */
- *p_threshold_high =
- (FixPoint1616_t)((0x00fff & threshold16) << 17);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_load_tuning_settings(VL53L0X_DEV dev,
- uint8_t *p_tuning_setting_buffer)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- int i;
- int index;
- uint8_t msb;
- uint8_t lsb;
- uint8_t select_param;
- uint8_t number_of_writes;
- uint8_t address;
- uint8_t local_buffer[4]; /* max */
- uint16_t temp16;
-
- LOG_FUNCTION_START("");
-
- index = 0;
-
- while ((*(p_tuning_setting_buffer + index) != 0) &&
- (status == VL53L0X_ERROR_NONE)) {
- number_of_writes = *(p_tuning_setting_buffer + index);
- index++;
- if (number_of_writes == 0xFF) {
- /* internal parameters */
- select_param = *(p_tuning_setting_buffer + index);
- index++;
- switch (select_param) {
- case 0: /* uint16_t SigmaEstRefArray -> 2 bytes */
- msb = *(p_tuning_setting_buffer + index);
- index++;
- lsb = *(p_tuning_setting_buffer + index);
- index++;
- temp16 = VL53L0X_MAKEUINT16(lsb, msb);
- PALDevDataSet(dev, SigmaEstRefArray, temp16);
- break;
- case 1: /* uint16_t SigmaEstEffPulseWidth -> 2 bytes */
- msb = *(p_tuning_setting_buffer + index);
- index++;
- lsb = *(p_tuning_setting_buffer + index);
- index++;
- temp16 = VL53L0X_MAKEUINT16(lsb, msb);
- PALDevDataSet(dev, SigmaEstEffPulseWidth,
- temp16);
- break;
- case 2: /* uint16_t SigmaEstEffAmbWidth -> 2 bytes */
- msb = *(p_tuning_setting_buffer + index);
- index++;
- lsb = *(p_tuning_setting_buffer + index);
- index++;
- temp16 = VL53L0X_MAKEUINT16(lsb, msb);
- PALDevDataSet(dev, SigmaEstEffAmbWidth, temp16);
- break;
- case 3: /* uint16_t targetRefRate -> 2 bytes */
- msb = *(p_tuning_setting_buffer + index);
- index++;
- lsb = *(p_tuning_setting_buffer + index);
- index++;
- temp16 = VL53L0X_MAKEUINT16(lsb, msb);
- PALDevDataSet(dev, targetRefRate, temp16);
- break;
- default: /* invalid parameter */
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
-
- } else if (number_of_writes <= 4) {
- address = *(p_tuning_setting_buffer + index);
- index++;
-
- for (i = 0; i < number_of_writes; i++) {
- local_buffer[i] = *(p_tuning_setting_buffer +
- index);
- index++;
- }
-
- status = VL53L0X_write_multi(dev, address, local_buffer,
- number_of_writes);
-
- } else {
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_check_and_load_interrupt_settings(VL53L0X_DEV dev,
- uint8_t start_not_stopflag)
-{
- uint8_t interrupt_config;
- FixPoint1616_t threshold_low;
- FixPoint1616_t threshold_high;
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
-
- interrupt_config = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
- Pin0GpioFunctionality);
-
- if ((interrupt_config ==
- VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW) ||
- (interrupt_config ==
- VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH) ||
- (interrupt_config ==
- VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT)) {
-
- status = VL53L0X_get_interrupt_thresholds(dev,
- VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
- &threshold_low, &threshold_high);
-
- if (((threshold_low > 255 * 65536) ||
- (threshold_high > 255 * 65536)) &&
- (status == VL53L0X_ERROR_NONE)) {
-
- if (start_not_stopflag != 0) {
- status = VL53L0X_load_tuning_settings(dev,
- InterruptThresholdSettings);
- } else {
- status |= VL53L0X_write_byte(dev, 0xFF, 0x04);
- status |= VL53L0X_write_byte(dev, 0x70, 0x00);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
- status |= VL53L0X_write_byte(dev, 0x80, 0x00);
- }
-
- }
-
-
- }
-
- return status;
-
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_start_measurement(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- VL53L0X_DeviceModes device_mode;
- uint8_t byte;
- uint8_t start_stop_byte = VL53L0X_REG_SYSRANGE_MODE_START_STOP;
- uint32_t loop_nb;
- LOG_FUNCTION_START("");
-
- /* Get Current DeviceMode */
- VL53L0X_get_device_mode(dev, &device_mode);
-
- status = VL53L0X_write_byte(dev, 0x80, 0x01);
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
- status = VL53L0X_write_byte(dev, 0x00, 0x00);
- status = VL53L0X_write_byte(dev, 0x91, PALDevDataGet(dev, StopVariable));
- status = VL53L0X_write_byte(dev, 0x00, 0x01);
- status = VL53L0X_write_byte(dev, 0xFF, 0x00);
- status = VL53L0X_write_byte(dev, 0x80, 0x00);
-
- switch (device_mode) {
- case VL53L0X_DEVICEMODE_SINGLE_RANGING:
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START, 0x01);
-
- byte = start_stop_byte;
- if (status == VL53L0X_ERROR_NONE) {
- /* Wait until start bit has been cleared */
- loop_nb = 0;
- do {
- if (loop_nb > 0)
- status = VL53L0X_read_byte(dev,
- VL53L0X_REG_SYSRANGE_START, &byte);
- loop_nb = loop_nb + 1;
- } while (((byte & start_stop_byte) == start_stop_byte)
- && (status == VL53L0X_ERROR_NONE)
- && (loop_nb < VL53L0X_DEFAULT_MAX_LOOP));
-
- if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
- status = VL53L0X_ERROR_TIME_OUT;
- }
-
- }
-
- break;
- case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
- /* Back-to-back mode */
-
- /* Check if need to apply interrupt settings */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_check_and_load_interrupt_settings(dev, 1);
- }
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_SYSRANGE_START,
- VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK);
- if (status == VL53L0X_ERROR_NONE) {
- /* Set PAL State to Running */
- PALDevDataSet(dev, PalState, VL53L0X_STATE_RUNNING);
- }
- break;
- case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
- /* Continuous mode */
- /* Check if need to apply interrupt settings */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_check_and_load_interrupt_settings(dev, 1);
- }
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_SYSRANGE_START,
- VL53L0X_REG_SYSRANGE_MODE_TIMED);
-
- if (status == VL53L0X_ERROR_NONE) {
- /* Set PAL State to Running */
- PALDevDataSet(dev, PalState, VL53L0X_STATE_RUNNING);
- }
- break;
- default:
- /* Selected mode not supported */
- status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
- }
-
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-/* Group PAL Measurement Functions */
-VL53L0X_Error VL53L0X::VL53L0X_perform_single_measurement(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- VL53L0X_DeviceModes device_mode;
-
- LOG_FUNCTION_START("");
-
- /* Get Current DeviceMode */
- status = VL53L0X_get_device_mode(dev, &device_mode);
-
- /* Start immediately to run a single ranging measurement in case of
- * single ranging or single histogram */
- if (status == VL53L0X_ERROR_NONE
- && device_mode == VL53L0X_DEVICEMODE_SINGLE_RANGING) {
- status = VL53L0X_start_measurement(dev);
- }
-
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_measurement_poll_for_completion(dev);
- }
-
-
- /* Change PAL State in case of single ranging or single histogram */
- if (status == VL53L0X_ERROR_NONE
- && device_mode == VL53L0X_DEVICEMODE_SINGLE_RANGING) {
- PALDevDataSet(dev, PalState, VL53L0X_STATE_IDLE);
- }
-
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_x_talk_compensation_enable(VL53L0X_DEV dev,
- uint8_t *p_x_talk_compensation_enable)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t temp8;
- LOG_FUNCTION_START("");
-
- VL53L0X_GETPARAMETERFIELD(dev, XTalkCompensationEnable, temp8);
- *p_x_talk_compensation_enable = temp8;
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_total_xtalk_rate(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- FixPoint1616_t *p_total_xtalk_rate_mcps)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
-
- uint8_t xtalk_comp_enable;
- FixPoint1616_t total_xtalk_mega_cps;
- FixPoint1616_t xtalk_per_spad_mega_cps;
-
- *p_total_xtalk_rate_mcps = 0;
-
- status = VL53L0X_get_x_talk_compensation_enable(dev, &xtalk_comp_enable);
- if (status == VL53L0X_ERROR_NONE) {
-
- if (xtalk_comp_enable) {
-
- VL53L0X_GETPARAMETERFIELD(
- dev,
- XTalkCompensationRateMegaCps,
- xtalk_per_spad_mega_cps);
-
- /* FixPoint1616 * FixPoint 8:8 = FixPoint0824 */
- total_xtalk_mega_cps =
- p_ranging_measurement_data->EffectiveSpadRtnCount *
- xtalk_per_spad_mega_cps;
-
- /* FixPoint0824 >> 8 = FixPoint1616 */
- *p_total_xtalk_rate_mcps =
- (total_xtalk_mega_cps + 0x80) >> 8;
- }
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_total_signal_rate(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- FixPoint1616_t *p_total_signal_rate_mcps)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- FixPoint1616_t total_xtalk_mega_cps;
-
- LOG_FUNCTION_START("");
-
- *p_total_signal_rate_mcps =
- p_ranging_measurement_data->SignalRateRtnMegaCps;
-
- status = VL53L0X_get_total_xtalk_rate(
- dev, p_ranging_measurement_data, &total_xtalk_mega_cps);
-
- if (status == VL53L0X_ERROR_NONE) {
- *p_total_signal_rate_mcps += total_xtalk_mega_cps;
- }
-
- return status;
-}
-
-/* To convert ms into register value */
-uint32_t VL53L0X::VL53L0X_calc_timeout_mclks(VL53L0X_DEV dev,
- uint32_t timeout_period_us,
- uint8_t vcsel_period_pclks)
-{
- uint32_t macro_period_ps;
- uint32_t macro_period_ns;
- uint32_t timeout_period_mclks = 0;
-
- macro_period_ps = VL53L0X_calc_macro_period_ps(dev, vcsel_period_pclks);
- macro_period_ns = (macro_period_ps + 500) / 1000;
-
- timeout_period_mclks =
- (uint32_t)(((timeout_period_us * 1000)
- + (macro_period_ns / 2)) / macro_period_ns);
-
- return timeout_period_mclks;
-}
-
-uint32_t VL53L0X::VL53L0X_isqrt(uint32_t num)
-{
- /*
- * Implements an integer square root
- *
- * From: http://en.wikipedia.org/wiki/Methods_of_computing_square_roots
- */
-
- uint32_t res = 0;
- uint32_t bit = 1 << 30;
- /* The second-to-top bit is set:
- * 1 << 14 for 16-bits, 1 << 30 for 32 bits */
-
- /* "bit" starts at the highest power of four <= the argument. */
- while (bit > num) {
- bit >>= 2;
- }
-
-
- while (bit != 0) {
- if (num >= res + bit) {
- num -= res + bit;
- res = (res >> 1) + bit;
- } else {
- res >>= 1;
- }
-
- bit >>= 2;
- }
-
- return res;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_calc_dmax(
- VL53L0X_DEV dev,
- FixPoint1616_t total_signal_rate_mcps,
- FixPoint1616_t total_corr_signal_rate_mcps,
- FixPoint1616_t pw_mult,
- uint32_t sigma_estimate_p1,
- FixPoint1616_t sigma_estimate_p2,
- uint32_t peak_vcsel_duration_us,
- uint32_t *pd_max_mm)
-{
- const uint32_t c_sigma_limit = 18;
- const FixPoint1616_t c_signal_limit = 0x4000; /* 0.25 */
- const FixPoint1616_t c_sigma_est_ref = 0x00000042; /* 0.001 */
- const uint32_t c_amb_eff_width_sigma_est_ns = 6;
- const uint32_t c_amb_eff_width_d_max_ns = 7;
- uint32_t dmax_cal_range_mm;
- FixPoint1616_t dmax_cal_signal_rate_rtn_mcps;
- FixPoint1616_t min_signal_needed;
- FixPoint1616_t min_signal_needed_p1;
- FixPoint1616_t min_signal_needed_p2;
- FixPoint1616_t min_signal_needed_p3;
- FixPoint1616_t min_signal_needed_p4;
- FixPoint1616_t sigma_limit_tmp;
- FixPoint1616_t sigma_est_sq_tmp;
- FixPoint1616_t signal_limit_tmp;
- FixPoint1616_t signal_at0_mm;
- FixPoint1616_t dmax_dark;
- FixPoint1616_t dmax_ambient;
- FixPoint1616_t dmax_dark_tmp;
- FixPoint1616_t sigma_est_p2_tmp;
- uint32_t signal_rate_temp_mcps;
-
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
-
- LOG_FUNCTION_START("");
-
- dmax_cal_range_mm =
- PALDevDataGet(dev, DmaxCalRangeMilliMeter);
-
- dmax_cal_signal_rate_rtn_mcps =
- PALDevDataGet(dev, DmaxCalSignalRateRtnMegaCps);
-
- /* uint32 * FixPoint1616 = FixPoint1616 */
- signal_at0_mm = dmax_cal_range_mm * dmax_cal_signal_rate_rtn_mcps;
-
- /* FixPoint1616 >> 8 = FixPoint2408 */
- signal_at0_mm = (signal_at0_mm + 0x80) >> 8;
- signal_at0_mm *= dmax_cal_range_mm;
-
- min_signal_needed_p1 = 0;
- if (total_corr_signal_rate_mcps > 0) {
-
- /* Shift by 10 bits to increase resolution prior to the
- * division */
- signal_rate_temp_mcps = total_signal_rate_mcps << 10;
-
- /* Add rounding value prior to division */
- min_signal_needed_p1 = signal_rate_temp_mcps +
- (total_corr_signal_rate_mcps / 2);
-
- /* FixPoint0626/FixPoint1616 = FixPoint2210 */
- min_signal_needed_p1 /= total_corr_signal_rate_mcps;
-
- /* Apply a factored version of the speed of light.
- Correction to be applied at the end */
- min_signal_needed_p1 *= 3;
-
- /* FixPoint2210 * FixPoint2210 = FixPoint1220 */
- min_signal_needed_p1 *= min_signal_needed_p1;
-
- /* FixPoint1220 >> 16 = FixPoint2804 */
- min_signal_needed_p1 = (min_signal_needed_p1 + 0x8000) >> 16;
- }
-
- min_signal_needed_p2 = pw_mult * sigma_estimate_p1;
-
- /* FixPoint1616 >> 16 = uint32 */
- min_signal_needed_p2 = (min_signal_needed_p2 + 0x8000) >> 16;
-
- /* uint32 * uint32 = uint32 */
- min_signal_needed_p2 *= min_signal_needed_p2;
-
- /* Check sigmaEstimateP2
- * If this value is too high there is not enough signal rate
- * to calculate dmax value so set a suitable value to ensure
- * a very small dmax.
- */
- sigma_est_p2_tmp = (sigma_estimate_p2 + 0x8000) >> 16;
- sigma_est_p2_tmp = (sigma_est_p2_tmp + c_amb_eff_width_sigma_est_ns / 2) /
- c_amb_eff_width_sigma_est_ns;
- sigma_est_p2_tmp *= c_amb_eff_width_d_max_ns;
-
- if (sigma_est_p2_tmp > 0xffff) {
- min_signal_needed_p3 = 0xfff00000;
- } else {
-
- /* DMAX uses a different ambient width from sigma, so apply
- * correction.
- * Perform division before multiplication to prevent overflow.
- */
- sigma_estimate_p2 = (sigma_estimate_p2 + c_amb_eff_width_sigma_est_ns / 2) /
- c_amb_eff_width_sigma_est_ns;
- sigma_estimate_p2 *= c_amb_eff_width_d_max_ns;
-
- /* FixPoint1616 >> 16 = uint32 */
- min_signal_needed_p3 = (sigma_estimate_p2 + 0x8000) >> 16;
-
- min_signal_needed_p3 *= min_signal_needed_p3;
-
- }
-
- /* FixPoint1814 / uint32 = FixPoint1814 */
- sigma_limit_tmp = ((c_sigma_limit << 14) + 500) / 1000;
-
- /* FixPoint1814 * FixPoint1814 = FixPoint3628 := FixPoint0428 */
- sigma_limit_tmp *= sigma_limit_tmp;
-
- /* FixPoint1616 * FixPoint1616 = FixPoint3232 */
- sigma_est_sq_tmp = c_sigma_est_ref * c_sigma_est_ref;
-
- /* FixPoint3232 >> 4 = FixPoint0428 */
- sigma_est_sq_tmp = (sigma_est_sq_tmp + 0x08) >> 4;
-
- /* FixPoint0428 - FixPoint0428 = FixPoint0428 */
- sigma_limit_tmp -= sigma_est_sq_tmp;
-
- /* uint32_t * FixPoint0428 = FixPoint0428 */
- min_signal_needed_p4 = 4 * 12 * sigma_limit_tmp;
-
- /* FixPoint0428 >> 14 = FixPoint1814 */
- min_signal_needed_p4 = (min_signal_needed_p4 + 0x2000) >> 14;
-
- /* uint32 + uint32 = uint32 */
- min_signal_needed = (min_signal_needed_p2 + min_signal_needed_p3);
-
- /* uint32 / uint32 = uint32 */
- min_signal_needed += (peak_vcsel_duration_us / 2);
- min_signal_needed /= peak_vcsel_duration_us;
-
- /* uint32 << 14 = FixPoint1814 */
- min_signal_needed <<= 14;
-
- /* FixPoint1814 / FixPoint1814 = uint32 */
- min_signal_needed += (min_signal_needed_p4 / 2);
- min_signal_needed /= min_signal_needed_p4;
-
- /* FixPoint3200 * FixPoint2804 := FixPoint2804*/
- min_signal_needed *= min_signal_needed_p1;
-
- /* Apply correction by dividing by 1000000.
- * This assumes 10E16 on the numerator of the equation
- * and 10E-22 on the denominator.
- * We do this because 32bit fix point calculation can't
- * handle the larger and smaller elements of this equation,
- * i.e. speed of light and pulse widths.
- */
- min_signal_needed = (min_signal_needed + 500) / 1000;
- min_signal_needed <<= 4;
-
- min_signal_needed = (min_signal_needed + 500) / 1000;
-
- /* FixPoint1616 >> 8 = FixPoint2408 */
- signal_limit_tmp = (c_signal_limit + 0x80) >> 8;
-
- /* FixPoint2408/FixPoint2408 = uint32 */
- if (signal_limit_tmp != 0) {
- dmax_dark_tmp = (signal_at0_mm + (signal_limit_tmp / 2))
- / signal_limit_tmp;
- } else {
- dmax_dark_tmp = 0;
- }
-
- dmax_dark = VL53L0X_isqrt(dmax_dark_tmp);
-
- /* FixPoint2408/FixPoint2408 = uint32 */
- if (min_signal_needed != 0) {
- dmax_ambient = (signal_at0_mm + min_signal_needed / 2)
- / min_signal_needed;
- } else {
- dmax_ambient = 0;
- }
-
- dmax_ambient = VL53L0X_isqrt(dmax_ambient);
-
- *pd_max_mm = dmax_dark;
- if (dmax_dark > dmax_ambient) {
- *pd_max_mm = dmax_ambient;
- }
-
- LOG_FUNCTION_END(status);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_calc_sigma_estimate(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- FixPoint1616_t *p_sigma_estimate,
- uint32_t *p_dmax_mm)
-{
- /* Expressed in 100ths of a ns, i.e. centi-ns */
- const uint32_t c_pulse_effective_width_centi_ns = 800;
- /* Expressed in 100ths of a ns, i.e. centi-ns */
- const uint32_t c_ambient_effective_width_centi_ns = 600;
- const FixPoint1616_t c_dflt_final_range_integration_time_milli_secs = 0x00190000; /* 25ms */
- const uint32_t c_vcsel_pulse_width_ps = 4700; /* pico secs */
- const FixPoint1616_t c_sigma_est_max = 0x028F87AE;
- const FixPoint1616_t c_sigma_est_rtn_max = 0xF000;
- const FixPoint1616_t c_amb_to_signal_ratio_max = 0xF0000000 /
- c_ambient_effective_width_centi_ns;
- /* Time Of Flight per mm (6.6 pico secs) */
- const FixPoint1616_t c_tof_per_mm_ps = 0x0006999A;
- const uint32_t c_16bit_rounding_param = 0x00008000;
- const FixPoint1616_t c_max_x_talk_kcps = 0x00320000;
- const uint32_t c_pll_period_ps = 1655;
-
- uint32_t vcsel_total_events_rtn;
- uint32_t final_range_timeout_micro_secs;
- uint32_t pre_range_timeout_micro_secs;
- uint32_t final_range_integration_time_milli_secs;
- FixPoint1616_t sigma_estimate_p1;
- FixPoint1616_t sigma_estimate_p2;
- FixPoint1616_t sigma_estimate_p3;
- FixPoint1616_t delta_t_ps;
- FixPoint1616_t pw_mult;
- FixPoint1616_t sigma_est_rtn;
- FixPoint1616_t sigma_estimate;
- FixPoint1616_t x_talk_correction;
- FixPoint1616_t ambient_rate_kcps;
- FixPoint1616_t peak_signal_rate_kcps;
- FixPoint1616_t x_talk_comp_rate_mcps;
- uint32_t x_talk_comp_rate_kcps;
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- FixPoint1616_t diff1_mcps;
- FixPoint1616_t diff2_mcps;
- FixPoint1616_t sqr1;
- FixPoint1616_t sqr2;
- FixPoint1616_t sqr_sum;
- FixPoint1616_t sqrt_result_centi_ns;
- FixPoint1616_t sqrt_result;
- FixPoint1616_t total_signal_rate_mcps;
- FixPoint1616_t corrected_signal_rate_mcps;
- FixPoint1616_t sigma_est_ref;
- uint32_t vcsel_width;
- uint32_t final_range_macro_pclks;
- uint32_t pre_range_macro_pclks;
- uint32_t peak_vcsel_duration_us;
- uint8_t final_range_vcsel_pclks;
- uint8_t pre_range_vcsel_pclks;
- /*! \addtogroup calc_sigma_estimate
- * @{
- *
- * Estimates the range sigma
- */
-
- LOG_FUNCTION_START("");
-
- VL53L0X_GETPARAMETERFIELD(dev, XTalkCompensationRateMegaCps,
- x_talk_comp_rate_mcps);
-
- /*
- * We work in kcps rather than mcps as this helps keep within the
- * confines of the 32 Fix1616 type.
- */
-
- ambient_rate_kcps =
- (p_ranging_measurement_data->AmbientRateRtnMegaCps * 1000) >> 16;
-
- corrected_signal_rate_mcps =
- p_ranging_measurement_data->SignalRateRtnMegaCps;
-
-
- status = VL53L0X_get_total_signal_rate(
- dev, p_ranging_measurement_data, &total_signal_rate_mcps);
- status = VL53L0X_get_total_xtalk_rate(
- dev, p_ranging_measurement_data, &x_talk_comp_rate_mcps);
-
-
- /* Signal rate measurement provided by device is the
- * peak signal rate, not average.
- */
- peak_signal_rate_kcps = (total_signal_rate_mcps * 1000);
- peak_signal_rate_kcps = (peak_signal_rate_kcps + 0x8000) >> 16;
-
- x_talk_comp_rate_kcps = x_talk_comp_rate_mcps * 1000;
-
- if (x_talk_comp_rate_kcps > c_max_x_talk_kcps) {
- x_talk_comp_rate_kcps = c_max_x_talk_kcps;
- }
-
- if (status == VL53L0X_ERROR_NONE) {
-
- /* Calculate final range macro periods */
- final_range_timeout_micro_secs = VL53L0X_GETDEVICESPECIFICPARAMETER(
- dev, FinalRangeTimeoutMicroSecs);
-
- final_range_vcsel_pclks = VL53L0X_GETDEVICESPECIFICPARAMETER(
- dev, FinalRangeVcselPulsePeriod);
-
- final_range_macro_pclks = VL53L0X_calc_timeout_mclks(
- dev, final_range_timeout_micro_secs, final_range_vcsel_pclks);
-
- /* Calculate pre-range macro periods */
- pre_range_timeout_micro_secs = VL53L0X_GETDEVICESPECIFICPARAMETER(
- dev, PreRangeTimeoutMicroSecs);
-
- pre_range_vcsel_pclks = VL53L0X_GETDEVICESPECIFICPARAMETER(
- dev, PreRangeVcselPulsePeriod);
-
- pre_range_macro_pclks = VL53L0X_calc_timeout_mclks(
- dev, pre_range_timeout_micro_secs, pre_range_vcsel_pclks);
-
- vcsel_width = 3;
- if (final_range_vcsel_pclks == 8) {
- vcsel_width = 2;
- }
-
-
- peak_vcsel_duration_us = vcsel_width * 2048 *
- (pre_range_macro_pclks + final_range_macro_pclks);
- peak_vcsel_duration_us = (peak_vcsel_duration_us + 500) / 1000;
- peak_vcsel_duration_us *= c_pll_period_ps;
- peak_vcsel_duration_us = (peak_vcsel_duration_us + 500) / 1000;
-
- /* Fix1616 >> 8 = Fix2408 */
- total_signal_rate_mcps = (total_signal_rate_mcps + 0x80) >> 8;
-
- /* Fix2408 * uint32 = Fix2408 */
- vcsel_total_events_rtn = total_signal_rate_mcps *
- peak_vcsel_duration_us;
-
- /* Fix2408 >> 8 = uint32 */
- vcsel_total_events_rtn = (vcsel_total_events_rtn + 0x80) >> 8;
-
- /* Fix2408 << 8 = Fix1616 = */
- total_signal_rate_mcps <<= 8;
- }
-
- if (status != VL53L0X_ERROR_NONE) {
- LOG_FUNCTION_END(status);
- return status;
- }
-
- if (peak_signal_rate_kcps == 0) {
- *p_sigma_estimate = c_sigma_est_max;
- PALDevDataSet(dev, SigmaEstimate, c_sigma_est_max);
- *p_dmax_mm = 0;
- } else {
- if (vcsel_total_events_rtn < 1) {
- vcsel_total_events_rtn = 1;
- }
-
- sigma_estimate_p1 = c_pulse_effective_width_centi_ns;
-
- /* ((FixPoint1616 << 16)* uint32)/uint32 = FixPoint1616 */
- sigma_estimate_p2 = (ambient_rate_kcps << 16) / peak_signal_rate_kcps;
- if (sigma_estimate_p2 > c_amb_to_signal_ratio_max) {
- /* Clip to prevent overflow. Will ensure safe
- * max result. */
- sigma_estimate_p2 = c_amb_to_signal_ratio_max;
- }
- sigma_estimate_p2 *= c_ambient_effective_width_centi_ns;
-
- sigma_estimate_p3 = 2 * VL53L0X_isqrt(vcsel_total_events_rtn * 12);
-
- /* uint32 * FixPoint1616 = FixPoint1616 */
- delta_t_ps = p_ranging_measurement_data->RangeMilliMeter *
- c_tof_per_mm_ps;
-
- /*
- * vcselRate - xtalkCompRate
- * (uint32 << 16) - FixPoint1616 = FixPoint1616.
- * Divide result by 1000 to convert to mcps.
- * 500 is added to ensure rounding when integer division
- * truncates.
- */
- diff1_mcps = (((peak_signal_rate_kcps << 16) -
- 2 * x_talk_comp_rate_kcps) + 500) / 1000;
-
- /* vcselRate + xtalkCompRate */
- diff2_mcps = ((peak_signal_rate_kcps << 16) + 500) / 1000;
-
- /* Shift by 8 bits to increase resolution prior to the
- * division */
- diff1_mcps <<= 8;
-
- /* FixPoint0824/FixPoint1616 = FixPoint2408 */
-// xTalkCorrection = abs(diff1_mcps/diff2_mcps);
-// abs is causing compiler overloading isue in C++, but unsigned types. So, redundant call anyway!
- x_talk_correction = diff1_mcps / diff2_mcps;
-
- /* FixPoint2408 << 8 = FixPoint1616 */
- x_talk_correction <<= 8;
-
- if (p_ranging_measurement_data->RangeStatus != 0) {
- pw_mult = 1 << 16;
- } else {
- /* FixPoint1616/uint32 = FixPoint1616 */
- pw_mult = delta_t_ps / c_vcsel_pulse_width_ps; /* smaller than 1.0f */
-
- /*
- * FixPoint1616 * FixPoint1616 = FixPoint3232, however both
- * values are small enough such that32 bits will not be
- * exceeded.
- */
- pw_mult *= ((1 << 16) - x_talk_correction);
-
- /* (FixPoint3232 >> 16) = FixPoint1616 */
- pw_mult = (pw_mult + c_16bit_rounding_param) >> 16;
-
- /* FixPoint1616 + FixPoint1616 = FixPoint1616 */
- pw_mult += (1 << 16);
-
- /*
- * At this point the value will be 1.xx, therefore if we square
- * the value this will exceed 32 bits. To address this perform
- * a single shift to the right before the multiplication.
- */
- pw_mult >>= 1;
- /* FixPoint1715 * FixPoint1715 = FixPoint3430 */
- pw_mult = pw_mult * pw_mult;
-
- /* (FixPoint3430 >> 14) = Fix1616 */
- pw_mult >>= 14;
- }
-
- /* FixPoint1616 * uint32 = FixPoint1616 */
- sqr1 = pw_mult * sigma_estimate_p1;
-
- /* (FixPoint1616 >> 16) = FixPoint3200 */
- sqr1 = (sqr1 + 0x8000) >> 16;
-
- /* FixPoint3200 * FixPoint3200 = FixPoint6400 */
- sqr1 *= sqr1;
-
- sqr2 = sigma_estimate_p2;
-
- /* (FixPoint1616 >> 16) = FixPoint3200 */
- sqr2 = (sqr2 + 0x8000) >> 16;
-
- /* FixPoint3200 * FixPoint3200 = FixPoint6400 */
- sqr2 *= sqr2;
-
- /* FixPoint64000 + FixPoint6400 = FixPoint6400 */
- sqr_sum = sqr1 + sqr2;
-
- /* SQRT(FixPoin6400) = FixPoint3200 */
- sqrt_result_centi_ns = VL53L0X_isqrt(sqr_sum);
-
- /* (FixPoint3200 << 16) = FixPoint1616 */
- sqrt_result_centi_ns <<= 16;
-
- /*
- * Note that the Speed Of Light is expressed in um per 1E-10
- * seconds (2997) Therefore to get mm/ns we have to divide by
- * 10000
- */
- sigma_est_rtn = (((sqrt_result_centi_ns + 50) / 100) /
- sigma_estimate_p3);
- sigma_est_rtn *= VL53L0X_SPEED_OF_LIGHT_IN_AIR;
-
- /* Add 5000 before dividing by 10000 to ensure rounding. */
- sigma_est_rtn += 5000;
- sigma_est_rtn /= 10000;
-
- if (sigma_est_rtn > c_sigma_est_rtn_max) {
- /* Clip to prevent overflow. Will ensure safe
- * max result. */
- sigma_est_rtn = c_sigma_est_rtn_max;
- }
- final_range_integration_time_milli_secs =
- (final_range_timeout_micro_secs + pre_range_timeout_micro_secs + 500) / 1000;
-
- /* sigmaEstRef = 1mm * 25ms/final range integration time (inc pre-range)
- * sqrt(FixPoint1616/int) = FixPoint2408)
- */
- sigma_est_ref =
- VL53L0X_isqrt((c_dflt_final_range_integration_time_milli_secs +
- final_range_integration_time_milli_secs / 2) /
- final_range_integration_time_milli_secs);
-
- /* FixPoint2408 << 8 = FixPoint1616 */
- sigma_est_ref <<= 8;
- sigma_est_ref = (sigma_est_ref + 500) / 1000;
-
- /* FixPoint1616 * FixPoint1616 = FixPoint3232 */
- sqr1 = sigma_est_rtn * sigma_est_rtn;
- /* FixPoint1616 * FixPoint1616 = FixPoint3232 */
- sqr2 = sigma_est_ref * sigma_est_ref;
-
- /* sqrt(FixPoint3232) = FixPoint1616 */
- sqrt_result = VL53L0X_isqrt((sqr1 + sqr2));
- /*
- * Note that the Shift by 4 bits increases resolution prior to
- * the sqrt, therefore the result must be shifted by 2 bits to
- * the right to revert back to the FixPoint1616 format.
- */
-
- sigma_estimate = 1000 * sqrt_result;
-
- if ((peak_signal_rate_kcps < 1) || (vcsel_total_events_rtn < 1) ||
- (sigma_estimate > c_sigma_est_max)) {
- sigma_estimate = c_sigma_est_max;
- }
-
- *p_sigma_estimate = (uint32_t)(sigma_estimate);
- PALDevDataSet(dev, SigmaEstimate, *p_sigma_estimate);
- status = VL53L0X_calc_dmax(
- dev,
- total_signal_rate_mcps,
- corrected_signal_rate_mcps,
- pw_mult,
- sigma_estimate_p1,
- sigma_estimate_p2,
- peak_vcsel_duration_us,
- p_dmax_mm);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_pal_range_status(VL53L0X_DEV dev,
- uint8_t device_range_status,
- FixPoint1616_t signal_rate,
- uint16_t effective_spad_rtn_count,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- uint8_t *p_pal_range_status)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t none_flag;
- uint8_t sigma_limitflag = 0;
- uint8_t signal_ref_clipflag = 0;
- uint8_t range_ignore_thresholdflag = 0;
- uint8_t sigma_limit_check_enable = 0;
- uint8_t signal_rate_final_range_limit_check_enable = 0;
- uint8_t signal_ref_clip_limit_check_enable = 0;
- uint8_t range_ignore_threshold_limit_check_enable = 0;
- FixPoint1616_t sigma_estimate;
- FixPoint1616_t sigma_limit_value;
- FixPoint1616_t signal_ref_clip_value;
- FixPoint1616_t range_ignore_threshold_value;
- FixPoint1616_t signal_rate_per_spad;
- uint8_t device_range_status_internal = 0;
- uint16_t tmp_word = 0;
- uint8_t temp8;
- uint32_t dmax_mm = 0;
- FixPoint1616_t last_signal_ref_mcps;
-
- LOG_FUNCTION_START("");
-
-
- /*
- * VL53L0X has a good ranging when the value of the
- * DeviceRangeStatus = 11. This function will replace the value 0 with
- * the value 11 in the DeviceRangeStatus.
- * In addition, the SigmaEstimator is not included in the VL53L0X
- * DeviceRangeStatus, this will be added in the PalRangeStatus.
- */
-
- device_range_status_internal = ((device_range_status & 0x78) >> 3);
-
- if (device_range_status_internal == 0 ||
- device_range_status_internal == 5 ||
- device_range_status_internal == 7 ||
- device_range_status_internal == 12 ||
- device_range_status_internal == 13 ||
- device_range_status_internal == 14 ||
- device_range_status_internal == 15
- ) {
- none_flag = 1;
- } else {
- none_flag = 0;
- }
-
- /*
- * Check if Sigma limit is enabled, if yes then do comparison with limit
- * value and put the result back into pPalRangeStatus.
- */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
- &sigma_limit_check_enable);
- }
-
- if ((sigma_limit_check_enable != 0) && (status == VL53L0X_ERROR_NONE)) {
- /*
- * compute the Sigma and check with limit
- */
- status = VL53L0X_calc_sigma_estimate(
- dev,
- p_ranging_measurement_data,
- &sigma_estimate,
- &dmax_mm);
- if (status == VL53L0X_ERROR_NONE) {
- p_ranging_measurement_data->RangeDMaxMilliMeter = dmax_mm;
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_limit_check_value(dev,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
- &sigma_limit_value);
-
- if ((sigma_limit_value > 0) &&
- (sigma_estimate > sigma_limit_value)) {
- /* Limit Fail */
- sigma_limitflag = 1;
- }
- }
- }
-
- /*
- * Check if Signal ref clip limit is enabled, if yes then do comparison
- * with limit value and put the result back into pPalRangeStatus.
- */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
- &signal_ref_clip_limit_check_enable);
- }
-
- if ((signal_ref_clip_limit_check_enable != 0) &&
- (status == VL53L0X_ERROR_NONE)) {
-
- status = VL53L0X_get_limit_check_value(dev,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
- &signal_ref_clip_value);
-
- /* Read LastSignalRefMcps from device */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
- &tmp_word);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x00);
- }
-
- last_signal_ref_mcps = VL53L0X_FIXPOINT97TOFIXPOINT1616(tmp_word);
- PALDevDataSet(dev, LastSignalRefMcps, last_signal_ref_mcps);
-
- if ((signal_ref_clip_value > 0) &&
- (last_signal_ref_mcps > signal_ref_clip_value)) {
- /* Limit Fail */
- signal_ref_clipflag = 1;
- }
- }
-
- /*
- * Check if Signal ref clip limit is enabled, if yes then do comparison
- * with limit value and put the result back into pPalRangeStatus.
- * EffectiveSpadRtnCount has a format 8.8
- * If (Return signal rate < (1.5 x Xtalk x number of Spads)) : FAIL
- */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
- &range_ignore_threshold_limit_check_enable);
- }
-
- if ((range_ignore_threshold_limit_check_enable != 0) &&
- (status == VL53L0X_ERROR_NONE)) {
-
- /* Compute the signal rate per spad */
- if (effective_spad_rtn_count == 0) {
- signal_rate_per_spad = 0;
- } else {
- signal_rate_per_spad = (FixPoint1616_t)((256 * signal_rate)
- / effective_spad_rtn_count);
- }
-
- status = VL53L0X_get_limit_check_value(dev,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
- &range_ignore_threshold_value);
-
- if ((range_ignore_threshold_value > 0) &&
- (signal_rate_per_spad < range_ignore_threshold_value)) {
- /* Limit Fail add 2^6 to range status */
- range_ignore_thresholdflag = 1;
- }
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- if (none_flag == 1) {
- *p_pal_range_status = 255; /* NONE */
- } else if (device_range_status_internal == 1 ||
- device_range_status_internal == 2 ||
- device_range_status_internal == 3) {
- *p_pal_range_status = 5; /* HW fail */
- } else if (device_range_status_internal == 6 ||
- device_range_status_internal == 9) {
- *p_pal_range_status = 4; /* Phase fail */
- } else if (device_range_status_internal == 8 ||
- device_range_status_internal == 10 ||
- signal_ref_clipflag == 1) {
- *p_pal_range_status = 3; /* Min range */
- } else if (device_range_status_internal == 4 ||
- range_ignore_thresholdflag == 1) {
- *p_pal_range_status = 2; /* Signal Fail */
- } else if (sigma_limitflag == 1) {
- *p_pal_range_status = 1; /* Sigma Fail */
- } else {
- *p_pal_range_status = 0; /* Range Valid */
- }
- }
-
- /* DMAX only relevant during range error */
- if (*p_pal_range_status == 0) {
- p_ranging_measurement_data->RangeDMaxMilliMeter = 0;
- }
-
- /* fill the Limit Check Status */
-
- status = VL53L0X_get_limit_check_enable(dev,
- VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
- &signal_rate_final_range_limit_check_enable);
-
- if (status == VL53L0X_ERROR_NONE) {
- if ((sigma_limit_check_enable == 0) || (sigma_limitflag == 1)) {
- temp8 = 1;
- } else {
- temp8 = 0;
- }
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, temp8);
-
- if ((device_range_status_internal == 4) ||
- (signal_rate_final_range_limit_check_enable == 0)) {
- temp8 = 1;
- } else {
- temp8 = 0;
- }
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
- VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
- temp8);
-
- if ((signal_ref_clip_limit_check_enable == 0) ||
- (signal_ref_clipflag == 1)) {
- temp8 = 1;
- } else {
- temp8 = 0;
- }
-
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, temp8);
-
- if ((range_ignore_threshold_limit_check_enable == 0) ||
- (range_ignore_thresholdflag == 1)) {
- temp8 = 1;
- } else {
- temp8 = 0;
- }
-
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
- temp8);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_ranging_measurement_data(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t device_range_status;
- uint8_t range_fractional_enable;
- uint8_t pal_range_status;
- uint8_t x_talk_compensation_enable;
- uint16_t ambient_rate;
- FixPoint1616_t signal_rate;
- uint16_t x_talk_compensation_rate_mega_cps;
- uint16_t effective_spad_rtn_count;
- uint16_t tmpuint16;
- uint16_t xtalk_range_milli_meter;
- uint16_t linearity_corrective_gain;
- uint8_t localBuffer[12];
- VL53L0X_RangingMeasurementData_t last_range_data_buffer;
-
- LOG_FUNCTION_START("");
-
- /*
- * use multi read even if some registers are not useful, result will
- * be more efficient
- * start reading at 0x14 dec20
- * end reading at 0x21 dec33 total 14 bytes to read
- */
- status = VL53L0X_read_multi(dev, 0x14, localBuffer, 12);
-
- if (status == VL53L0X_ERROR_NONE) {
-
- p_ranging_measurement_data->ZoneId = 0; /* Only one zone */
- p_ranging_measurement_data->TimeStamp = 0; /* Not Implemented */
-
- tmpuint16 = VL53L0X_MAKEUINT16(localBuffer[11], localBuffer[10]);
- /* cut1.1 if SYSTEM__RANGE_CONFIG if 1 range is 2bits fractional
- *(format 11.2) else no fractional
- */
-
- p_ranging_measurement_data->MeasurementTimeUsec = 0;
-
- signal_rate = VL53L0X_FIXPOINT97TOFIXPOINT1616(
- VL53L0X_MAKEUINT16(localBuffer[7], localBuffer[6]));
- /* peak_signal_count_rate_rtn_mcps */
- p_ranging_measurement_data->SignalRateRtnMegaCps = signal_rate;
-
- ambient_rate = VL53L0X_MAKEUINT16(localBuffer[9], localBuffer[8]);
- p_ranging_measurement_data->AmbientRateRtnMegaCps =
- VL53L0X_FIXPOINT97TOFIXPOINT1616(ambient_rate);
-
- effective_spad_rtn_count = VL53L0X_MAKEUINT16(localBuffer[3],
- localBuffer[2]);
- /* EffectiveSpadRtnCount is 8.8 format */
- p_ranging_measurement_data->EffectiveSpadRtnCount =
- effective_spad_rtn_count;
-
- device_range_status = localBuffer[0];
-
- /* Get Linearity Corrective Gain */
- linearity_corrective_gain = PALDevDataGet(dev,
- LinearityCorrectiveGain);
-
- /* Get ranging configuration */
- range_fractional_enable = PALDevDataGet(dev,
- RangeFractionalEnable);
-
- if (linearity_corrective_gain != 1000) {
-
- tmpuint16 = (uint16_t)((linearity_corrective_gain
- * tmpuint16 + 500) / 1000);
-
- /* Implement Xtalk */
- VL53L0X_GETPARAMETERFIELD(dev,
- XTalkCompensationRateMegaCps,
- x_talk_compensation_rate_mega_cps);
- VL53L0X_GETPARAMETERFIELD(dev, XTalkCompensationEnable,
- x_talk_compensation_enable);
-
- if (x_talk_compensation_enable) {
-
- if ((signal_rate
- - ((x_talk_compensation_rate_mega_cps
- * effective_spad_rtn_count) >> 8))
- <= 0) {
- if (range_fractional_enable) {
- xtalk_range_milli_meter = 8888;
- } else {
- xtalk_range_milli_meter = 8888 << 2;
- }
- } else {
- xtalk_range_milli_meter =
- (tmpuint16 * signal_rate)
- / (signal_rate
- - ((x_talk_compensation_rate_mega_cps
- * effective_spad_rtn_count)
- >> 8));
- }
-
- tmpuint16 = xtalk_range_milli_meter;
- }
-
- }
-
- if (range_fractional_enable) {
- p_ranging_measurement_data->RangeMilliMeter =
- (uint16_t)((tmpuint16) >> 2);
- p_ranging_measurement_data->RangeFractionalPart =
- (uint8_t)((tmpuint16 & 0x03) << 6);
- } else {
- p_ranging_measurement_data->RangeMilliMeter = tmpuint16;
- p_ranging_measurement_data->RangeFractionalPart = 0;
- }
-
- /*
- * For a standard definition of RangeStatus, this should
- * return 0 in case of good result after a ranging
- * The range status depends on the device so call a device
- * specific function to obtain the right Status.
- */
- status |= VL53L0X_get_pal_range_status(dev, device_range_status,
- signal_rate, effective_spad_rtn_count,
- p_ranging_measurement_data, &pal_range_status);
-
- if (status == VL53L0X_ERROR_NONE) {
- p_ranging_measurement_data->RangeStatus = pal_range_status;
- }
-
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- /* Copy last read data into Dev buffer */
- last_range_data_buffer = PALDevDataGet(dev, LastRangeMeasure);
-
- last_range_data_buffer.RangeMilliMeter =
- p_ranging_measurement_data->RangeMilliMeter;
- last_range_data_buffer.RangeFractionalPart =
- p_ranging_measurement_data->RangeFractionalPart;
- last_range_data_buffer.RangeDMaxMilliMeter =
- p_ranging_measurement_data->RangeDMaxMilliMeter;
- last_range_data_buffer.MeasurementTimeUsec =
- p_ranging_measurement_data->MeasurementTimeUsec;
- last_range_data_buffer.SignalRateRtnMegaCps =
- p_ranging_measurement_data->SignalRateRtnMegaCps;
- last_range_data_buffer.AmbientRateRtnMegaCps =
- p_ranging_measurement_data->AmbientRateRtnMegaCps;
- last_range_data_buffer.EffectiveSpadRtnCount =
- p_ranging_measurement_data->EffectiveSpadRtnCount;
- last_range_data_buffer.RangeStatus =
- p_ranging_measurement_data->RangeStatus;
-
- PALDevDataSet(dev, LastRangeMeasure, last_range_data_buffer);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_perform_single_ranging_measurement(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
-
- LOG_FUNCTION_START("");
-
- /* This function will do a complete single ranging
- * Here we fix the mode! */
- status = VL53L0X_set_device_mode(dev, VL53L0X_DEVICEMODE_SINGLE_RANGING);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_perform_single_measurement(dev);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_ranging_measurement_data(dev,
- p_ranging_measurement_data);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_clear_interrupt_mask(dev, 0);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::perform_ref_signal_measurement(VL53L0X_DEV dev,
- uint16_t *p_ref_signal_rate)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- VL53L0X_RangingMeasurementData_t ranging_measurement_data;
-
- uint8_t sequence_config = 0;
-
- /* store the value of the sequence config,
- * this will be reset before the end of the function
- */
-
- sequence_config = PALDevDataGet(dev, SequenceConfig);
-
- /*
- * This function performs a reference signal rate measurement.
- */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0xC0);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_perform_single_ranging_measurement(dev,
- &ranging_measurement_data);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_word(dev,
- VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
- p_ref_signal_rate);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x00);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- /* restore the previous Sequence Config */
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
- sequence_config);
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, SequenceConfig, sequence_config);
- }
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
- uint32_t *ref_spad_count,
- uint8_t *is_aperture_spads)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t last_spad_array[6];
- uint8_t start_select = 0xB4;
- uint32_t minimum_spad_count = 3;
- uint32_t max_spad_count = 44;
- uint32_t current_spad_index = 0;
- uint32_t last_spad_index = 0;
- int32_t next_good_spad = 0;
- uint16_t target_ref_rate = 0x0A00; /* 20 MCPS in 9:7 format */
- uint16_t peak_signal_rate_ref;
- uint32_t need_apt_spads = 0;
- uint32_t index = 0;
- uint32_t spad_array_size = 6;
- uint32_t signal_rate_diff = 0;
- uint32_t last_signal_rate_diff = 0;
- uint8_t complete = 0;
- uint8_t vhv_settings = 0;
- uint8_t phase_cal = 0;
- uint32_t ref_spad_count_int = 0;
- uint8_t is_aperture_spads_int = 0;
-
- /*
- * The reference SPAD initialization procedure determines the minimum
- * amount of reference spads to be enables to achieve a target reference
- * signal rate and should be performed once during initialization.
- *
- * Either aperture or non-aperture spads are applied but never both.
- * Firstly non-aperture spads are set, begining with 5 spads, and
- * increased one spad at a time until the closest measurement to the
- * target rate is achieved.
- *
- * If the target rate is exceeded when 5 non-aperture spads are enabled,
- * initialization is performed instead with aperture spads.
- *
- * When setting spads, a 'Good Spad Map' is applied.
- *
- * This procedure operates within a SPAD window of interest of a maximum
- * 44 spads.
- * The start point is currently fixed to 180, which lies towards the end
- * of the non-aperture quadrant and runs in to the adjacent aperture
- * quadrant.
- */
- target_ref_rate = PALDevDataGet(dev, targetRefRate);
-
- /*
- * Initialize Spad arrays.
- * Currently the good spad map is initialised to 'All good'.
- * This is a short term implementation. The good spad map will be
- * provided as an input.
- * Note that there are 6 bytes. Only the first 44 bits will be used to
- * represent spads.
- */
- for (index = 0; index < spad_array_size; index++) {
- dev->Data.SpadData.RefSpadEnables[index] = 0;
- }
-
-
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x00);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
- start_select);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE, 0);
- }
-
- /* Perform ref calibration */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_perform_ref_calibration(dev, &vhv_settings,
- &phase_cal, 0);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- /* Enable Minimum NON-APERTURE Spads */
- current_spad_index = 0;
- last_spad_index = current_spad_index;
- need_apt_spads = 0;
- status = enable_ref_spads(dev,
- need_apt_spads,
- dev->Data.SpadData.RefGoodSpadMap,
- dev->Data.SpadData.RefSpadEnables,
- spad_array_size,
- start_select,
- current_spad_index,
- minimum_spad_count,
- &last_spad_index);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- current_spad_index = last_spad_index;
-
- status = perform_ref_signal_measurement(dev,
- &peak_signal_rate_ref);
- if ((status == VL53L0X_ERROR_NONE) &&
- (peak_signal_rate_ref > target_ref_rate)) {
- /* Signal rate measurement too high,
- * switch to APERTURE SPADs */
-
- for (index = 0; index < spad_array_size; index++) {
- dev->Data.SpadData.RefSpadEnables[index] = 0;
- }
-
-
- /* Increment to the first APERTURE spad */
- while ((is_aperture(start_select + current_spad_index)
- == 0) && (current_spad_index < max_spad_count)) {
- current_spad_index++;
- }
-
- need_apt_spads = 1;
-
- status = enable_ref_spads(dev,
- need_apt_spads,
- dev->Data.SpadData.RefGoodSpadMap,
- dev->Data.SpadData.RefSpadEnables,
- spad_array_size,
- start_select,
- current_spad_index,
- minimum_spad_count,
- &last_spad_index);
-
- if (status == VL53L0X_ERROR_NONE) {
- current_spad_index = last_spad_index;
- status = perform_ref_signal_measurement(dev,
- &peak_signal_rate_ref);
-
- if ((status == VL53L0X_ERROR_NONE) &&
- (peak_signal_rate_ref > target_ref_rate)) {
- /* Signal rate still too high after
- * setting the minimum number of
- * APERTURE spads. Can do no more
- * therefore set the min number of
- * aperture spads as the result.
- */
- is_aperture_spads_int = 1;
- ref_spad_count_int = minimum_spad_count;
- }
- }
- } else {
- need_apt_spads = 0;
- }
- }
-
- if ((status == VL53L0X_ERROR_NONE) &&
- (peak_signal_rate_ref < target_ref_rate)) {
- /* At this point, the minimum number of either aperture
- * or non-aperture spads have been set. Proceed to add
- * spads and perform measurements until the target
- * reference is reached.
- */
- is_aperture_spads_int = need_apt_spads;
- ref_spad_count_int = minimum_spad_count;
-
- memcpy(last_spad_array, dev->Data.SpadData.RefSpadEnables,
- spad_array_size);
- last_signal_rate_diff = abs(peak_signal_rate_ref -
- target_ref_rate);
- complete = 0;
-
- while (!complete) {
- get_next_good_spad(
- dev->Data.SpadData.RefGoodSpadMap,
- spad_array_size, current_spad_index,
- &next_good_spad);
-
- if (next_good_spad == -1) {
- status = VL53L0X_ERROR_REF_SPAD_INIT;
- break;
- }
-
- /* Cannot combine Aperture and Non-Aperture spads, so
- * ensure the current spad is of the correct type.
- */
- if (is_aperture((uint32_t)start_select + next_good_spad) !=
- need_apt_spads) {
- /* At this point we have enabled the maximum
- * number of Aperture spads.
- */
- complete = 1;
- break;
- }
-
- (ref_spad_count_int)++;
-
- current_spad_index = next_good_spad;
- status = enable_spad_bit(
- dev->Data.SpadData.RefSpadEnables,
- spad_array_size, current_spad_index);
-
- if (status == VL53L0X_ERROR_NONE) {
- current_spad_index++;
- /* Proceed to apply the additional spad and
- * perform measurement. */
- status = set_ref_spad_map(dev,
- dev->Data.SpadData.RefSpadEnables);
- }
-
- if (status != VL53L0X_ERROR_NONE) {
- break;
- }
-
- status = perform_ref_signal_measurement(dev,
- &peak_signal_rate_ref);
-
- if (status != VL53L0X_ERROR_NONE) {
- break;
- }
-
- signal_rate_diff = abs(peak_signal_rate_ref - target_ref_rate);
-
- if (peak_signal_rate_ref > target_ref_rate) {
- /* Select the spad map that provides the
- * measurement closest to the target rate,
- * either above or below it.
- */
- if (signal_rate_diff > last_signal_rate_diff) {
- /* Previous spad map produced a closer
- * measurement, so choose this. */
- status = set_ref_spad_map(dev,
- last_spad_array);
- memcpy(
- dev->Data.SpadData.RefSpadEnables,
- last_spad_array, spad_array_size);
-
- (ref_spad_count_int)--;
- }
- complete = 1;
- } else {
- /* Continue to add spads */
- last_signal_rate_diff = signal_rate_diff;
- memcpy(last_spad_array,
- dev->Data.SpadData.RefSpadEnables,
- spad_array_size);
- }
-
- } /* while */
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- *ref_spad_count = ref_spad_count_int;
- *is_aperture_spads = is_aperture_spads_int;
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev, RefSpadsInitialised, 1);
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadCount, (uint8_t)(*ref_spad_count));
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadType, *is_aperture_spads);
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_reference_spads(VL53L0X_DEV dev,
- uint32_t count, uint8_t is_aperture_spads)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint32_t current_spad_index = 0;
- uint8_t start_select = 0xB4;
- uint32_t spad_array_size = 6;
- uint32_t max_spad_count = 44;
- uint32_t last_spad_index;
- uint32_t index;
-
- /*
- * This function applies a requested number of reference spads, either
- * aperture or
- * non-aperture, as requested.
- * The good spad map will be applied.
- */
-
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x00);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
- start_select);
- }
-
- for (index = 0; index < spad_array_size; index++) {
- dev->Data.SpadData.RefSpadEnables[index] = 0;
- }
-
- if (is_aperture_spads) {
- /* Increment to the first APERTURE spad */
- while ((is_aperture(start_select + current_spad_index) == 0) &&
- (current_spad_index < max_spad_count)) {
- current_spad_index++;
- }
- }
- status = enable_ref_spads(dev,
- is_aperture_spads,
- dev->Data.SpadData.RefGoodSpadMap,
- dev->Data.SpadData.RefSpadEnables,
- spad_array_size,
- start_select,
- current_spad_index,
- count,
- &last_spad_index);
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev, RefSpadsInitialised, 1);
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadCount, (uint8_t)(count));
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadType, is_aperture_spads);
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_wait_device_booted(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NOT_IMPLEMENTED;
- LOG_FUNCTION_START("");
-
- /* not implemented on VL53L0X */
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_perform_ref_calibration(VL53L0X_DEV dev, uint8_t *p_vhv_settings,
- uint8_t *p_phase_cal)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_perform_ref_calibration(dev, p_vhv_settings,
- p_phase_cal, 1);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
- uint32_t *ref_spad_count, uint8_t *is_aperture_spads)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_perform_ref_spad_management(dev, ref_spad_count,
- is_aperture_spads);
-
- LOG_FUNCTION_END(status);
-
- return status;
-}
-
-/* Group PAL Init Functions */
-VL53L0X_Error VL53L0X::VL53L0X_set_device_address(VL53L0X_DEV dev, uint8_t device_address)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_write_byte(dev, VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS,
- device_address / 2);
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_gpio_config(VL53L0X_DEV dev, uint8_t pin,
- VL53L0X_DeviceModes device_mode, VL53L0X_GpioFunctionality functionality,
- VL53L0X_InterruptPolarity polarity)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t data;
-
- LOG_FUNCTION_START("");
-
- if (pin != 0) {
- status = VL53L0X_ERROR_GPIO_NOT_EXISTING;
- } else if (device_mode == VL53L0X_DEVICEMODE_GPIO_DRIVE) {
- if (polarity == VL53L0X_INTERRUPTPOLARITY_LOW) {
- data = 0x10;
- } else {
- data = 1;
- }
-
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH, data);
-
- } else {
- if (device_mode == VL53L0X_DEVICEMODE_GPIO_OSC) {
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x01);
- status |= VL53L0X_write_byte(dev, 0x00, 0x00);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x00);
- status |= VL53L0X_write_byte(dev, 0x80, 0x01);
- status |= VL53L0X_write_byte(dev, 0x85, 0x02);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x04);
- status |= VL53L0X_write_byte(dev, 0xcd, 0x00);
- status |= VL53L0X_write_byte(dev, 0xcc, 0x11);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x07);
- status |= VL53L0X_write_byte(dev, 0xbe, 0x00);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x06);
- status |= VL53L0X_write_byte(dev, 0xcc, 0x09);
-
- status |= VL53L0X_write_byte(dev, 0xff, 0x00);
- status |= VL53L0X_write_byte(dev, 0xff, 0x01);
- status |= VL53L0X_write_byte(dev, 0x00, 0x00);
-
- } else {
-
- if (status == VL53L0X_ERROR_NONE) {
- switch (functionality) {
- case VL53L0X_GPIOFUNCTIONALITY_OFF:
- data = 0x00;
- break;
- case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW:
- data = 0x01;
- break;
- case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH:
- data = 0x02;
- break;
- case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT:
- data = 0x03;
- break;
- case VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY:
- data = 0x04;
- break;
- default:
- status =
- VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED;
- }
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO, data);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- if (polarity == VL53L0X_INTERRUPTPOLARITY_LOW) {
- data = 0;
- } else {
- data = (uint8_t)(1 << 4);
- }
- status = VL53L0X_update_byte(dev,
- VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH, 0xEF, data);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- Pin0GpioFunctionality, functionality);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_clear_interrupt_mask(dev, 0);
- }
- }
- }
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_fraction_enable(VL53L0X_DEV dev, uint8_t *p_enabled)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_RANGE_CONFIG, p_enabled);
-
- if (status == VL53L0X_ERROR_NONE) {
- *p_enabled = (*p_enabled & 1);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-uint16_t VL53L0X::VL53L0X_encode_timeout(uint32_t timeout_macro_clks)
-{
- /*!
- * Encode timeout in macro periods in (LSByte * 2^MSByte) + 1 format
- */
-
- uint16_t encoded_timeout = 0;
- uint32_t ls_byte = 0;
- uint16_t ms_byte = 0;
-
- if (timeout_macro_clks > 0) {
- ls_byte = timeout_macro_clks - 1;
-
- while ((ls_byte & 0xFFFFFF00) > 0) {
- ls_byte = ls_byte >> 1;
- ms_byte++;
- }
-
- encoded_timeout = (ms_byte << 8)
- + (uint16_t)(ls_byte & 0x000000FF);
- }
-
- return encoded_timeout;
-
-}
-
-VL53L0X_Error VL53L0X::set_sequence_step_timeout(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id,
- uint32_t timeout_micro_secs)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t current_vcsel_pulse_period_p_clk;
- uint8_t msrc_encoded_time_out;
- uint16_t pre_range_encoded_time_out;
- uint16_t pre_range_time_out_m_clks;
- uint16_t msrc_range_time_out_m_clks;
- uint32_t final_range_time_out_m_clks;
- uint16_t final_range_encoded_time_out;
- VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
-
- if ((sequence_step_id == VL53L0X_SEQUENCESTEP_TCC) ||
- (sequence_step_id == VL53L0X_SEQUENCESTEP_DSS) ||
- (sequence_step_id == VL53L0X_SEQUENCESTEP_MSRC)) {
-
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
-
- if (status == VL53L0X_ERROR_NONE) {
- msrc_range_time_out_m_clks = VL53L0X_calc_timeout_mclks(dev,
- timeout_micro_secs,
- (uint8_t)current_vcsel_pulse_period_p_clk);
-
- if (msrc_range_time_out_m_clks > 256) {
- msrc_encoded_time_out = 255;
- } else {
- msrc_encoded_time_out =
- (uint8_t)msrc_range_time_out_m_clks - 1;
- }
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- LastEncodedTimeout,
- msrc_encoded_time_out);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
- msrc_encoded_time_out);
- }
- } else {
-
- if (sequence_step_id == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
- pre_range_time_out_m_clks =
- VL53L0X_calc_timeout_mclks(dev,
- timeout_micro_secs,
- (uint8_t)current_vcsel_pulse_period_p_clk);
- pre_range_encoded_time_out = VL53L0X_encode_timeout(
- pre_range_time_out_m_clks);
-
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
- LastEncodedTimeout,
- pre_range_encoded_time_out);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_word(dev,
- VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
- pre_range_encoded_time_out);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- PreRangeTimeoutMicroSecs,
- timeout_micro_secs);
- }
- } else if (sequence_step_id == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
-
- /* For the final range timeout, the pre-range timeout
- * must be added. To do this both final and pre-range
- * timeouts must be expressed in macro periods MClks
- * because they have different vcsel periods.
- */
-
- VL53L0X_get_sequence_step_enables(dev,
- &scheduler_sequence_steps);
- pre_range_time_out_m_clks = 0;
- if (scheduler_sequence_steps.PreRangeOn) {
-
- /* Retrieve PRE-RANGE VCSEL Period */
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
-
- /* Retrieve PRE-RANGE Timeout in Macro periods
- * (MCLKS) */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_word(dev, 0x51,
- &pre_range_encoded_time_out);
- pre_range_time_out_m_clks =
- VL53L0X_decode_timeout(
- pre_range_encoded_time_out);
- }
- }
-
- /* Calculate FINAL RANGE Timeout in Macro Periods
- * (MCLKS) and add PRE-RANGE value
- */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_vcsel_pulse_period(dev,
- VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
- ¤t_vcsel_pulse_period_p_clk);
- }
- if (status == VL53L0X_ERROR_NONE) {
- final_range_time_out_m_clks =
- VL53L0X_calc_timeout_mclks(dev,
- timeout_micro_secs,
- (uint8_t) current_vcsel_pulse_period_p_clk);
-
- final_range_time_out_m_clks += pre_range_time_out_m_clks;
-
- final_range_encoded_time_out =
- VL53L0X_encode_timeout(final_range_time_out_m_clks);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_word(dev, 0x71,
- final_range_encoded_time_out);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- FinalRangeTimeoutMicroSecs,
- timeout_micro_secs);
- }
- }
- } else {
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
-
- }
- return status;
-}
-
-VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t measurement_timing_budget_micro_seconds)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint32_t final_range_timing_budget_micro_seconds;
- VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
- uint32_t msrc_dcc_tcc_timeout_micro_seconds = 2000;
- uint32_t start_overhead_micro_seconds = 1910;
- uint32_t end_overhead_micro_seconds = 960;
- uint32_t msrc_overhead_micro_seconds = 660;
- uint32_t tcc_overhead_micro_seconds = 590;
- uint32_t dss_overhead_micro_seconds = 690;
- uint32_t pre_range_overhead_micro_seconds = 660;
- uint32_t final_range_overhead_micro_seconds = 550;
- uint32_t pre_range_timeout_micro_seconds = 0;
- uint32_t c_min_timing_budget_micro_seconds = 20000;
- uint32_t sub_timeout = 0;
-
- LOG_FUNCTION_START("");
-
- if (measurement_timing_budget_micro_seconds
- < c_min_timing_budget_micro_seconds) {
- status = VL53L0X_ERROR_INVALID_PARAMS;
- return status;
- }
-
- final_range_timing_budget_micro_seconds =
- measurement_timing_budget_micro_seconds -
- (start_overhead_micro_seconds + end_overhead_micro_seconds);
-
- status = VL53L0X_get_sequence_step_enables(dev, &scheduler_sequence_steps);
-
- if (status == VL53L0X_ERROR_NONE &&
- (scheduler_sequence_steps.TccOn ||
- scheduler_sequence_steps.MsrcOn ||
- scheduler_sequence_steps.DssOn)) {
-
- /* TCC, MSRC and DSS all share the same timeout */
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_MSRC,
- &msrc_dcc_tcc_timeout_micro_seconds);
-
- /* Subtract the TCC, MSRC and DSS timeouts if they are
- * enabled. */
-
- if (status != VL53L0X_ERROR_NONE) {
- return status;
- }
-
- /* TCC */
- if (scheduler_sequence_steps.TccOn) {
-
- sub_timeout = msrc_dcc_tcc_timeout_micro_seconds
- + tcc_overhead_micro_seconds;
-
- if (sub_timeout <
- final_range_timing_budget_micro_seconds) {
- final_range_timing_budget_micro_seconds -=
- sub_timeout;
- } else {
- /* Requested timeout too big. */
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- }
-
- if (status != VL53L0X_ERROR_NONE) {
- LOG_FUNCTION_END(status);
- return status;
- }
-
- /* DSS */
- if (scheduler_sequence_steps.DssOn) {
-
- sub_timeout = 2 * (msrc_dcc_tcc_timeout_micro_seconds +
- dss_overhead_micro_seconds);
-
- if (sub_timeout < final_range_timing_budget_micro_seconds) {
- final_range_timing_budget_micro_seconds
- -= sub_timeout;
- } else {
- /* Requested timeout too big. */
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- } else if (scheduler_sequence_steps.MsrcOn) {
- /* MSRC */
- sub_timeout = msrc_dcc_tcc_timeout_micro_seconds +
- msrc_overhead_micro_seconds;
-
- if (sub_timeout < final_range_timing_budget_micro_seconds) {
- final_range_timing_budget_micro_seconds
- -= sub_timeout;
- } else {
- /* Requested timeout too big. */
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- }
-
- }
-
- if (status != VL53L0X_ERROR_NONE) {
- LOG_FUNCTION_END(status);
- return status;
- }
-
- if (scheduler_sequence_steps.PreRangeOn) {
-
- /* Subtract the Pre-range timeout if enabled. */
-
- status = get_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_PRE_RANGE,
- &pre_range_timeout_micro_seconds);
-
- sub_timeout = pre_range_timeout_micro_seconds +
- pre_range_overhead_micro_seconds;
-
- if (sub_timeout < final_range_timing_budget_micro_seconds) {
- final_range_timing_budget_micro_seconds -= sub_timeout;
- } else {
- /* Requested timeout too big. */
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- }
-
-
- if (status == VL53L0X_ERROR_NONE &&
- scheduler_sequence_steps.FinalRangeOn) {
-
- final_range_timing_budget_micro_seconds -=
- final_range_overhead_micro_seconds;
-
- /* Final Range Timeout
- * Note that the final range timeout is determined by the timing
- * budget and the sum of all other timeouts within the sequence.
- * If there is no room for the final range timeout, then an error
- * will be set. Otherwise the remaining time will be applied to
- * the final range.
- */
- status = set_sequence_step_timeout(dev,
- VL53L0X_SEQUENCESTEP_FINAL_RANGE,
- final_range_timing_budget_micro_seconds);
-
- VL53L0X_SETPARAMETERFIELD(dev,
- MeasurementTimingBudgetMicroSeconds,
- measurement_timing_budget_micro_seconds);
- }
-
- LOG_FUNCTION_END(status);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t measurement_timing_budget_micro_seconds)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(dev,
- measurement_timing_budget_micro_seconds);
-
- LOG_FUNCTION_END(status);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_sequence_step_enable(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_step_enabled)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t sequence_config = 0;
- uint8_t sequence_config_new = 0;
- uint32_t measurement_timing_budget_micro_seconds;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
- &sequence_config);
-
- sequence_config_new = sequence_config;
-
- if (status == VL53L0X_ERROR_NONE) {
- if (sequence_step_enabled == 1) {
-
- /* Enable requested sequence step
- */
- switch (sequence_step_id) {
- case VL53L0X_SEQUENCESTEP_TCC:
- sequence_config_new |= 0x10;
- break;
- case VL53L0X_SEQUENCESTEP_DSS:
- sequence_config_new |= 0x28;
- break;
- case VL53L0X_SEQUENCESTEP_MSRC:
- sequence_config_new |= 0x04;
- break;
- case VL53L0X_SEQUENCESTEP_PRE_RANGE:
- sequence_config_new |= 0x40;
- break;
- case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
- sequence_config_new |= 0x80;
- break;
- default:
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- } else {
- /* Disable requested sequence step
- */
- switch (sequence_step_id) {
- case VL53L0X_SEQUENCESTEP_TCC:
- sequence_config_new &= 0xef;
- break;
- case VL53L0X_SEQUENCESTEP_DSS:
- sequence_config_new &= 0xd7;
- break;
- case VL53L0X_SEQUENCESTEP_MSRC:
- sequence_config_new &= 0xfb;
- break;
- case VL53L0X_SEQUENCESTEP_PRE_RANGE:
- sequence_config_new &= 0xbf;
- break;
- case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
- sequence_config_new &= 0x7f;
- break;
- default:
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
- }
- }
-
- if (sequence_config_new != sequence_config) {
- /* Apply New Setting */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev,
- VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, sequence_config_new);
- }
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, SequenceConfig, sequence_config_new);
- }
-
-
- /* Recalculate timing budget */
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_GETPARAMETERFIELD(dev,
- MeasurementTimingBudgetMicroSeconds,
- measurement_timing_budget_micro_seconds);
-
- VL53L0X_set_measurement_timing_budget_micro_seconds(dev,
- measurement_timing_budget_micro_seconds);
- }
- }
-
- LOG_FUNCTION_END(status);
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_set_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
- uint8_t limit_check_enable)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- FixPoint1616_t temp_fix1616 = 0;
- uint8_t limit_check_enable_int = 0;
- uint8_t limit_check_disable = 0;
- uint8_t temp8;
-
- LOG_FUNCTION_START("");
-
- if (limit_check_id >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
- status = VL53L0X_ERROR_INVALID_PARAMS;
- } else {
- if (limit_check_enable == 0) {
- temp_fix1616 = 0;
- limit_check_enable_int = 0;
- limit_check_disable = 1;
-
- } else {
- VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
- limit_check_id, temp_fix1616);
- limit_check_disable = 0;
- /* this to be sure to have either 0 or 1 */
- limit_check_enable_int = 1;
- }
-
- switch (limit_check_id) {
-
- case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
- /* internal computation: */
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
- limit_check_enable_int);
-
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
-
- status = VL53L0X_write_word(dev,
- VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
- VL53L0X_FIXPOINT1616TOFIXPOINT97(temp_fix1616));
-
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
-
- /* internal computation: */
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
- VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
- limit_check_enable_int);
-
- break;
-
- case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
-
- /* internal computation: */
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
- VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
- limit_check_enable_int);
-
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
-
- temp8 = (uint8_t)(limit_check_disable << 1);
- status = VL53L0X_update_byte(dev,
- VL53L0X_REG_MSRC_CONFIG_CONTROL,
- 0xFE, temp8);
-
- break;
-
- case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
-
- temp8 = (uint8_t)(limit_check_disable << 4);
- status = VL53L0X_update_byte(dev,
- VL53L0X_REG_MSRC_CONFIG_CONTROL,
- 0xEF, temp8);
-
- break;
-
-
- default:
- status = VL53L0X_ERROR_INVALID_PARAMS;
-
- }
-
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- if (limit_check_enable == 0) {
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
- limit_check_id, 0);
- } else {
- VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
- limit_check_id, 1);
- }
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_static_init(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- VL53L0X_DeviceParameters_t current_parameters = {0};
- uint8_t *p_tuning_setting_buffer;
- uint16_t tempword = 0;
- uint8_t tempbyte = 0;
- uint8_t use_internal_tuning_settings = 0;
- uint32_t count = 0;
- uint8_t is_aperture_spads = 0;
- uint32_t ref_spad_count = 0;
- uint8_t aperture_spads = 0;
- uint8_t vcsel_pulse_period_pclk;
- uint32_t seq_timeout_micro_secs;
-
- LOG_FUNCTION_START("");
-
- status = VL53L0X_get_info_from_device(dev, 1);
-
- /* set the ref spad from NVM */
- count = (uint32_t)VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadCount);
- aperture_spads = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
- ReferenceSpadType);
-
- /* NVM value invalid */
- if ((aperture_spads > 1) ||
- ((aperture_spads == 1) && (count > 32)) ||
- ((aperture_spads == 0) && (count > 12))) {
- status = wrapped_VL53L0X_perform_ref_spad_management(dev, &ref_spad_count,
- &is_aperture_spads);
- } else {
- status = VL53L0X_set_reference_spads(dev, count, aperture_spads);
- }
-
-
- /* Initialize tuning settings buffer to prevent compiler warning. */
- p_tuning_setting_buffer = DefaultTuningSettings;
-
- if (status == VL53L0X_ERROR_NONE) {
- use_internal_tuning_settings = PALDevDataGet(dev,
- UseInternalTuningSettings);
-
- if (use_internal_tuning_settings == 0) {
- p_tuning_setting_buffer = PALDevDataGet(dev,
- pTuningSettingsPointer);
- } else {
- p_tuning_setting_buffer = DefaultTuningSettings;
- }
-
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_load_tuning_settings(dev, p_tuning_setting_buffer);
- }
-
-
- /* Set interrupt config to new sample ready */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_set_gpio_config(dev, 0, 0,
- VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
- VL53L0X_INTERRUPTPOLARITY_LOW);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
- status |= VL53L0X_read_word(dev, 0x84, &tempword);
- status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(dev, OscFrequencyMHz,
- VL53L0X_FIXPOINT412TOFIXPOINT1616(tempword));
- }
-
- /* After static init, some device parameters may be changed,
- * so update them */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_device_parameters(dev, ¤t_parameters);
- }
-
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_fraction_enable(dev, &tempbyte);
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, RangeFractionalEnable, tempbyte);
- }
-
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, CurrentParameters, current_parameters);
- }
-
-
- /* read the sequence config and save it */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_byte(dev,
- VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, &tempbyte);
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, SequenceConfig, tempbyte);
- }
- }
-
- /* Disable MSRC and TCC by default */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_set_sequence_step_enable(dev,
- VL53L0X_SEQUENCESTEP_TCC, 0);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_set_sequence_step_enable(dev,
- VL53L0X_SEQUENCESTEP_MSRC, 0);
- }
-
- /* Set PAL State to standby */
- if (status == VL53L0X_ERROR_NONE) {
- PALDevDataSet(dev, PalState, VL53L0X_STATE_IDLE);
- }
-
- /* Store pre-range vcsel period */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_vcsel_pulse_period(
- dev,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE,
- &vcsel_pulse_period_pclk);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- PreRangeVcselPulsePeriod,
- vcsel_pulse_period_pclk);
- }
-
- /* Store final-range vcsel period */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_get_vcsel_pulse_period(
- dev,
- VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
- &vcsel_pulse_period_pclk);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- FinalRangeVcselPulsePeriod,
- vcsel_pulse_period_pclk);
- }
-
- /* Store pre-range timeout */
- if (status == VL53L0X_ERROR_NONE) {
- status = get_sequence_step_timeout(
- dev,
- VL53L0X_SEQUENCESTEP_PRE_RANGE,
- &seq_timeout_micro_secs);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- PreRangeTimeoutMicroSecs,
- seq_timeout_micro_secs);
- }
-
- /* Store final-range timeout */
- if (status == VL53L0X_ERROR_NONE) {
- status = get_sequence_step_timeout(
- dev,
- VL53L0X_SEQUENCESTEP_FINAL_RANGE,
- &seq_timeout_micro_secs);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- VL53L0X_SETDEVICESPECIFICPARAMETER(
- dev,
- FinalRangeTimeoutMicroSecs,
- seq_timeout_micro_secs);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-
-VL53L0X_Error VL53L0X::VL53L0X_stop_measurement(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START,
- VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT);
-
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
- status = VL53L0X_write_byte(dev, 0x00, 0x00);
- status = VL53L0X_write_byte(dev, 0x91, 0x00);
- status = VL53L0X_write_byte(dev, 0x00, 0x01);
- status = VL53L0X_write_byte(dev, 0xFF, 0x00);
-
- if (status == VL53L0X_ERROR_NONE) {
- /* Set PAL State to Idle */
- PALDevDataSet(dev, PalState, VL53L0X_STATE_IDLE);
- }
-
- /* Check if need to apply interrupt settings */
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_check_and_load_interrupt_settings(dev, 0);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_get_stop_completed_status(VL53L0X_DEV dev,
- uint32_t *p_stop_status)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t byte = 0;
- LOG_FUNCTION_START("");
-
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_read_byte(dev, 0x04, &byte);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- status = VL53L0X_write_byte(dev, 0xFF, 0x0);
- }
-
- *p_stop_status = byte;
-
- if (byte == 0) {
- status = VL53L0X_write_byte(dev, 0x80, 0x01);
- status = VL53L0X_write_byte(dev, 0xFF, 0x01);
- status = VL53L0X_write_byte(dev, 0x00, 0x00);
- status = VL53L0X_write_byte(dev, 0x91,
- PALDevDataGet(dev, StopVariable));
- status = VL53L0X_write_byte(dev, 0x00, 0x01);
- status = VL53L0X_write_byte(dev, 0xFF, 0x00);
- status = VL53L0X_write_byte(dev, 0x80, 0x00);
- }
-
- LOG_FUNCTION_END(status);
- return status;
-}
-
-/****************** Write and read functions from I2C *************************/
-
-VL53L0X_Error VL53L0X::VL53L0X_write_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count)
-{
- int status;
-
- status = VL53L0X_i2c_write(dev->I2cDevAddr, index, p_data, (uint16_t)count);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_read_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count)
-{
- int status;
-
- if (count >= VL53L0X_MAX_I2C_XFER_SIZE) {
- status = VL53L0X_ERROR_INVALID_PARAMS;
- }
-
- status = VL53L0X_i2c_read(dev->I2cDevAddr, index, p_data, (uint16_t)count);
-
- return status;
-}
-
-
-VL53L0X_Error VL53L0X::VL53L0X_write_byte(VL53L0X_DEV Dev, uint8_t index, uint8_t data)
-{
- int status;
-
- status = VL53L0X_i2c_write(Dev->I2cDevAddr, index, &data, 1);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_write_word(VL53L0X_DEV dev, uint8_t index, uint16_t data)
-{
- int status;
- uint8_t buffer[2];
-
- buffer[0] = data >> 8;
- buffer[1] = data & 0x00FF;
- status = VL53L0X_i2c_write(dev->I2cDevAddr, index, (uint8_t *)buffer, 2);
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_write_dword(VL53L0X_DEV Dev, uint8_t index, uint32_t data)
-{
- int status;
- uint8_t buffer[4];
-
- buffer[0] = (data >> 24) & 0xFF;
- buffer[1] = (data >> 16) & 0xFF;
- buffer[2] = (data >> 8) & 0xFF;
- buffer[3] = (data >> 0) & 0xFF;
- status = VL53L0X_i2c_write(Dev->I2cDevAddr, index, (uint8_t *)buffer, 4);
- return status;
-}
-
-
-VL53L0X_Error VL53L0X::VL53L0X_read_byte(VL53L0X_DEV Dev, uint8_t index, uint8_t *p_data)
-{
- int status;
-
- status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, p_data, 1);
-
- if (status) {
- return -1;
- }
-
- return 0;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_read_word(VL53L0X_DEV Dev, uint8_t index, uint16_t *p_data)
-{
- int status;
- uint8_t buffer[2] = {0, 0};
-
- status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, buffer, 2);
- if (!status) {
- *p_data = (buffer[0] << 8) + buffer[1];
- }
- return status;
-
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_read_dword(VL53L0X_DEV Dev, uint8_t index, uint32_t *p_data)
-{
- int status;
- uint8_t buffer[4] = {0, 0, 0, 0};
-
- status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, buffer, 4);
- if (!status) {
- *p_data = (buffer[0] << 24) + (buffer[1] << 16) + (buffer[2] << 8) + buffer[3];
- }
- return status;
-
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_update_byte(VL53L0X_DEV Dev, uint8_t index, uint8_t and_data, uint8_t or_data)
-{
- int status;
- uint8_t buffer = 0;
-
- /* read data direct onto buffer */
- status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, &buffer, 1);
- if (!status) {
- buffer = (buffer & and_data) | or_data;
- status = VL53L0X_i2c_write(Dev->I2cDevAddr, index, &buffer, (uint8_t)1);
- }
- return status;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_i2c_write(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t *p_data,
- uint16_t NumByteToWrite)
-{
- int ret;
-#if ORIGINAL
- ret = _dev_i2c->i2c_write(p_data, DeviceAddr, RegisterAddr, NumByteToWrite);
-#else
- ret = i2c_write(p_data, DeviceAddr, RegisterAddr, NumByteToWrite);
-#endif
-
- if (ret) {
- return -1;
- }
- return 0;
-}
-
-VL53L0X_Error VL53L0X::VL53L0X_i2c_read(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t *p_data,
- uint16_t NumByteToRead)
-{
- int ret;
-
-#if ORIGINAL
- ret = _dev_i2c->i2c_read(p_data, DeviceAddr, RegisterAddr, NumByteToRead);
-#else
- ret = i2c_read(p_data, DeviceAddr, RegisterAddr, NumByteToRead);
-#endif
-
- if (ret) {
- return -1;
- }
- return 0;
-}
-
-int VL53L0X::read_id(uint8_t *id)
-{
- int status = 0;
- uint16_t rl_id = 0;
-
- status = VL53L0X_read_word(_device, VL53L0X_REG_IDENTIFICATION_MODEL_ID, &rl_id);
- if (rl_id == 0xEEAA) {
- return status;
- }
-
- return -1;
-}
-
-
-VL53L0X_Error VL53L0X::wait_measurement_data_ready(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint8_t new_dat_ready = 0;
- uint32_t loop_nb;
-
- // Wait until it finished
- // use timeout to avoid deadlock
- if (status == VL53L0X_ERROR_NONE) {
- loop_nb = 0;
- do {
- status = VL53L0X_get_measurement_data_ready(dev, &new_dat_ready);
- if ((new_dat_ready == 0x01) || status != VL53L0X_ERROR_NONE) {
- break;
- }
- loop_nb = loop_nb + 1;
- VL53L0X_polling_delay(dev);
- } while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
-
- if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
- status = VL53L0X_ERROR_TIME_OUT;
- }
- }
-
- return status;
-}
-
-VL53L0X_Error VL53L0X::wait_stop_completed(VL53L0X_DEV dev)
-{
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint32_t stop_completed = 0;
- uint32_t loop_nb;
-
- // Wait until it finished
- // use timeout to avoid deadlock
- if (status == VL53L0X_ERROR_NONE) {
- loop_nb = 0;
- do {
- status = VL53L0X_get_stop_completed_status(dev, &stop_completed);
- if ((stop_completed == 0x00) || status != VL53L0X_ERROR_NONE) {
- break;
- }
- loop_nb = loop_nb + 1;
- VL53L0X_polling_delay(dev);
- } while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
-
- if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
- status = VL53L0X_ERROR_TIME_OUT;
- }
-
- }
-
- return status;
-}
-
-
-int VL53L0X::init_sensor(uint8_t new_addr)
-{
- int status;
-
- VL53L0X_off();
- VL53L0X_on();
-
-// status=VL53L0X_WaitDeviceBooted(Device);
-// if(status)
-// printf("WaitDeviceBooted fail\n\r");
- status = is_present();
- if (!status) {
- status = init(&_my_device);
- if (status != VL53L0X_ERROR_NONE) {
- printf("Failed to init VL53L0X sensor!\n\r");
- return status;
- }
-
- // deduce silicon version
- status = VL53L0X_get_device_info(&_my_device, &_device_info);
-
- status = prepare();
- if (status != VL53L0X_ERROR_NONE) {
- printf("Failed to prepare VL53L0X!\n\r");
- return status;
- }
-
- if (new_addr != VL53L0X_DEFAULT_ADDRESS) {
- status = set_device_address(new_addr);
- if (status) {
- printf("Failed to change I2C address!\n\r");
- return status;
- }
- } else {
-#if ORIGINAL
- printf("Invalid new address!\n\r");
-#endif
- return VL53L0X_ERROR_INVALID_PARAMS;
- }
- }
- return status;
-}
-
-int VL53L0X::range_meas_int_continuous_mode(void (*fptr)(void))
-{
- int status, clr_status;
-
- status = VL53L0X_stop_measurement(_device); // it is safer to do this while sensor is stopped
-
-// status = VL53L0X_SetInterruptThresholds(Device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING, 0, 300);
-
- status = VL53L0X_set_gpio_config(_device, 0, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
- VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
- VL53L0X_INTERRUPTPOLARITY_HIGH);
-
- if (!status) {
- attach_interrupt_measure_detection_irq(fptr);
- enable_interrupt_measure_detection_irq();
- }
-
- clr_status = clear_interrupt(VL53L0X_REG_RESULT_INTERRUPT_STATUS | VL53L0X_REG_RESULT_RANGE_STATUS);
- if (clr_status) {
- VL53L0X_ErrLog("VL53L0X_ClearErrorInterrupt fail\r\n");
- }
-
- if (!status) {
- status = range_start_continuous_mode();
- }
- return status;
-}
-
-
-int VL53L0X::start_measurement(OperatingMode operating_mode, void (*fptr)(void))
-{
- int Status = VL53L0X_ERROR_NONE;
- int ClrStatus;
-
- uint8_t VhvSettings;
- uint8_t PhaseCal;
- // *** from mass market cube expansion v1.1, ranging with satellites.
- // default settings, for normal range.
- FixPoint1616_t signalLimit = (FixPoint1616_t)(0.25 * 65536);
- FixPoint1616_t sigmaLimit = (FixPoint1616_t)(18 * 65536);
- uint32_t timingBudget = 33000;
- uint8_t preRangeVcselPeriod = 14;
- uint8_t finalRangeVcselPeriod = 10;
-
- if (operating_mode == range_continuous_interrupt) {
- if (_gpio1Int == NULL) {
- printf("GPIO1 Error\r\n");
- return 1;
- }
-
- Status = VL53L0X_stop_measurement(_device); // it is safer to do this while sensor is stopped
-
-// Status = VL53L0X_SetInterruptThresholds(Device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING, 0, 300);
-
- Status = VL53L0X_set_gpio_config(_device, 0, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
- VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
- VL53L0X_INTERRUPTPOLARITY_HIGH);
-
- if (Status == VL53L0X_ERROR_NONE) {
- attach_interrupt_measure_detection_irq(fptr);
- enable_interrupt_measure_detection_irq();
- }
-
- ClrStatus = clear_interrupt(VL53L0X_REG_RESULT_INTERRUPT_STATUS | VL53L0X_REG_RESULT_RANGE_STATUS);
- if (ClrStatus) {
- VL53L0X_ErrLog("VL53L0X_ClearErrorInterrupt fail\r\n");
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING); // Setup in continuous ranging mode
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_start_measurement(_device);
- }
- }
-
- if (operating_mode == range_single_shot_polling) {
- // singelshot, polled ranging
- if (Status == VL53L0X_ERROR_NONE) {
- // no need to do this when we use VL53L0X_PerformSingleRangingMeasurement
- Status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_SINGLE_RANGING); // Setup in single ranging mode
- }
-
- // Enable/Disable Sigma and Signal check
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_limit_check_enable(_device,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, 1);
- }
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_limit_check_enable(_device,
- VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE, 1);
- }
-
-// *** from mass market cube expansion v1.1, ranging with satellites.
-#if ORIGINAL
- /* Ranging configuration */
-//*
-// switch(rangingConfig) {
-// case LONG_RANGE:
- signalLimit = (FixPoint1616_t)(0.1 * 65536);
- sigmaLimit = (FixPoint1616_t)(60 * 65536);
- timingBudget = 33000;
- preRangeVcselPeriod = 18;
- finalRangeVcselPeriod = 14;
- /* break;
- case HIGH_ACCURACY:
- signalLimit = (FixPoint1616_t)(0.25*65536);
- sigmaLimit = (FixPoint1616_t)(18*65536);
- timingBudget = 200000;
- preRangeVcselPeriod = 14;
- finalRangeVcselPeriod = 10;
- break;
- case HIGH_SPEED:
- signalLimit = (FixPoint1616_t)(0.25*65536);
- sigmaLimit = (FixPoint1616_t)(32*65536);
- timingBudget = 20000;
- preRangeVcselPeriod = 14;
- finalRangeVcselPeriod = 10;
- break;
- default:
- debug_printf("Not Supported");
- }
- */
-#else
- /* Ranging configuration */
- switch(_range_mode) {
- case range_hi_accurate_200ms_120cm:
- signalLimit = (FixPoint1616_t)(0.25*65536);
- sigmaLimit = (FixPoint1616_t)(18*65536);
- timingBudget = 200000;
- preRangeVcselPeriod = 14;
- finalRangeVcselPeriod = 10;
- break;
- case range_hi_speed_20ms_120cm:
- signalLimit = (FixPoint1616_t)(0.25*65536);
- sigmaLimit = (FixPoint1616_t)(32*65536);
- timingBudget = 20000;
- preRangeVcselPeriod = 14;
- finalRangeVcselPeriod = 10;
- break;
- case range_long_distance_33ms_200cm:
- default:
- signalLimit = (FixPoint1616_t)(0.1 * 65536);
- sigmaLimit = (FixPoint1616_t)(60 * 65536);
- timingBudget = 33000;
- preRangeVcselPeriod = 18;
- finalRangeVcselPeriod = 14;
- }
-#endif
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_limit_check_value(_device,
- VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE, signalLimit);
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_limit_check_value(_device,
- VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, sigmaLimit);
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_measurement_timing_budget_micro_seconds(_device, timingBudget);
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_vcsel_pulse_period(_device,
- VL53L0X_VCSEL_PERIOD_PRE_RANGE, preRangeVcselPeriod);
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_set_vcsel_pulse_period(_device,
- VL53L0X_VCSEL_PERIOD_FINAL_RANGE, finalRangeVcselPeriod);
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_perform_ref_calibration(_device, &VhvSettings, &PhaseCal);
- }
-
- }
-
- if (operating_mode == range_continuous_polling) {
- if (Status == VL53L0X_ERROR_NONE) {
- //printf("Call of VL53L0X_SetDeviceMode\n");
- Status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING); // Setup in continuous ranging mode
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- //printf("Call of VL53L0X_StartMeasurement\n");
- Status = VL53L0X_start_measurement(_device);
- }
- }
-
- return Status;
-}
-
-
-int VL53L0X::get_measurement(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *p_data)
-{
- int Status = VL53L0X_ERROR_NONE;
-
- if (operating_mode == range_single_shot_polling) {
- Status = VL53L0X_perform_single_ranging_measurement(_device, p_data);
- }
-
- if (operating_mode == range_continuous_polling) {
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_measurement_poll_for_completion(_device);
- }
-
- if (Status == VL53L0X_ERROR_NONE) {
- Status = VL53L0X_get_ranging_measurement_data(_device, p_data);
-
- // Clear the interrupt
- VL53L0X_clear_interrupt_mask(_device, VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY);
- VL53L0X_polling_delay(_device);
- }
- }
-
- if (operating_mode == range_continuous_interrupt) {
- Status = VL53L0X_get_ranging_measurement_data(_device, p_data);
- VL53L0X_clear_interrupt_mask(_device, VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR | VL53L0X_REG_RESULT_INTERRUPT_STATUS);
- }
-
- return Status;
-}
-
-
-int VL53L0X::stop_measurement(OperatingMode operating_mode)
-{
- int status = VL53L0X_ERROR_NONE;
-
-
- // don't need to stop for a singleshot range!
- if (operating_mode == range_single_shot_polling) {
- }
-
- if (operating_mode == range_continuous_interrupt || operating_mode == range_continuous_polling) {
- // continuous mode
- if (status == VL53L0X_ERROR_NONE) {
- //printf("Call of VL53L0X_StopMeasurement\n");
- status = VL53L0X_stop_measurement(_device);
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- //printf("Wait Stop to be competed\n");
- status = wait_stop_completed(_device);
- }
-
- if (status == VL53L0X_ERROR_NONE)
- status = VL53L0X_clear_interrupt_mask(_device,
- VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY);
- }
-
- return status;
-}
-
-
-int VL53L0X::handle_irq(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *data)
-{
- int status;
- status = get_measurement(operating_mode, data);
- enable_interrupt_measure_detection_irq();
- return status;
-}
-
-
-/******************************************************************************/
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,414 +0,0 @@
-/*******************************************************************************
- Copyright © 2016, STMicroelectronics International N.V.
- All rights reserved.
-
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
- IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *****************************************************************************/
-
-#ifndef __VL53L0X_CLASS_H
-#define __VL53L0X_CLASS_H
-
-//------- Feburary 6th, 2018 by JH1PJL / K.Arai --------------------------------
-//ORIGINAL=1 does NOT mean anything but just keep original source code as it is!
-//You can NOT compile with ORIGINAL=1 !!
-#define ORIGINAL 0 // Just keep = 0
-#define USE_I2C_2V8
-//------------------------------------------------------------------------------
-
-#if ORIGINAL
-#ifdef _MSC_VER
-# ifdef VL53L0X_API_EXPORTS
-# define VL53L0X_API __declspec(dllexport)
-# else
-# define VL53L0X_API
-# endif
-#else
-# define VL53L0X_API
-#endif
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "mbed.h"
-#if ORIGINAL
-#include "RangeSensor.h"
-#include "DevI2C.h"
-#include "PinNames.h"
-#endif
-#include "VL53L0X_def.h"
-#include "VL53L0X_platform.h"
-#if ORIGINAL
-#include "Stmpe1600.h"
-#endif
-
-#if !ORIGINAL
-//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
-// moved to following header file
-#include "VL53L0X_1st.h"
-//------------------------------------------------------------------------------
-#endif
-
-/* sensor operating modes */
-typedef enum {
- range_single_shot_polling = 1,
- range_continuous_polling,
- range_continuous_interrupt,
- range_continuous_polling_low_threshold,
- range_continuous_polling_high_threshold,
- range_continuous_polling_out_of_window,
- range_continuous_interrupt_low_threshold,
- range_continuous_interrupt_high_threshold,
- range_continuous_interrupt_out_of_window,
-} OperatingMode;
-
-#if !ORIGINAL
-/* sensor range profiles */
-typedef enum {
- range_long_distance_33ms_200cm = 1,
- range_hi_accurate_200ms_120cm,
- range_hi_speed_20ms_120cm,
-} RangeProfile;
-#endif
-
-/** default device address */
-#if ORIGINAL
-#define VL53L0X_DEFAULT_ADDRESS 0x52 /* (8-bit) */
-#else
-// No other choice
-#define VL53L0X_DEFAULT_ADDRESS 0x52 // 8-bit(0x53/Read & 0x52?Write) 0x29(7bit)
-#endif
-
-#if !ORIGINAL
-#if (MBED_MAJOR_VERSION == 2)
-#define WAIT_MS(x) wait_ms(x)
-#define VL53L0X_OsDelay(...) wait_ms(2)
-#elif (MBED_MAJOR_VERSION == 5)
-#define WAIT_MS(x) Thread::wait(x)
-#define VL53L0X_OsDelay(...) Thread::wait(2)
-#else
-#warning "I cannot control wait_ms()!!"
-#endif
-#endif // !ORIGINAL
-
-#if !ORIGINAL
-
-//--------------- Simple debug -------------------------------------------------
-//extern DigitalOut myled;
-//------------------------------------------------------------------------------
-
-/** Interface for STMicronics VL53L0X
- * World smallest Time-of-Flight (ToF) ranging sensor
- *
- * @code
- * #include "mbed.h"
- *
- * // I2C Communication
- * VL53L0X sensor(I2C_SDA, I2C_SCL, D8); // SDA, SCL & XSHUT
- * // If you connected I2C line not only this device but also other devices,
- * // you need to declare following method.
- * I2C i2c(I2C_SDA, I2C_SCL);
- * VL53L0X sensor(i2c, D8); // I2C, XSHUT
- *
- * int main()
- * {
- * int status = VL53L0X_ERROR_NONE;
- * uint32_t data;
- *
- * status = sensor.init_sensor(0x33<<1U); //new addres(not equal others)
- * status = sensor.set_mode(range_long_distance_33ms_200cm);
- * //status = sensor.set_mode(range_hi_accurate_200ms_120cm);
- * //status = sensor.set_mode(range_hi_speed_20ms_120cm);
- * while (true) {
- * status = sensor.get_distance(&data);
- * if (status == VL53L0X_ERROR_NONE) {
- * printf("%5d\r\n", data);
- * } else {
- * printf("error\r\n");
- * }
- * }
- * }
- * @endcode
- */
-
-
-/* Classes -------------------------------------------------------------------*/
-/** Class representing a VL53L0 sensor component
- */
-class VL53L0X
-{
-public:
- /** Constructor
- * @param[in] &i2c device I2C to be used for communication
- * @param[in] pin Mbed DigitalInOut PinName to be used for XSHUT
- * @param[in] &pin_gpio1 pin Mbed InterruptIn PinName
- * to be used as component GPIO_1 INT
- */
- VL53L0X(I2C& i2c, PinName xshut, PinName pin_gpio1) : _i2c(i2c),
- _gpio0(xshut)
- {
- if (pin_gpio1 != NC) {
- _gpio1Int = new InterruptIn(pin_gpio1);
- } else {
- _gpio1Int = NULL;
- }
- preparation();
- }
-
- /** Constructor 2 (another simple way)
- * @param[in] Pin for I2C SDA & SDL
- * @param[in] pin Mbed DigitalInOut PinName to be used for XSHUT
- */
- VL53L0X(PinName p_sda, PinName p_scl, PinName xshut)
- : _i2c_p(new I2C(p_sda, p_scl)), _i2c(*_i2c_p), _gpio0(xshut) {
- _gpio1Int = NULL;
- preparation();
- }
-
- /** Constructor 3 (another simple way)
- * @param[in] &i2c device I2C to be used for communication
- * @param[in] pin Mbed DigitalInOut PinName to be used for XSHUT
- */
- VL53L0X(I2C& p_i2c, PinName xshut) : _i2c(p_i2c), _gpio0(xshut) {
- _gpio1Int = NULL;
- preparation();
- }
-
- /** Destructor
- */
- virtual ~VL53L0X()
- {
- if (_gpio1Int != NULL) {
- delete _gpio1Int;
- }
- }
-#else
-#warning "please recover original constractor form VL53L0X_header_original.txt"
-#endif
-
- /*** Interface Methods ***/
- /*** High level API ***/
-#if !ORIGINAL
- /**
- * @brief initialize
- * @return void
- */
- /* turns on the sensor */
- void preparation(void)
- {
- _my_device.I2cDevAddr = VL53L0X_DEFAULT_ADDRESS;
- _my_device.comms_type = 1; // VL53L0X_COMMS_I2C
- _my_device.comms_speed_khz = 400;
- _device = &_my_device;
- _range_mode = range_long_distance_33ms_200cm;
- VL53L0X_off();
- }
-#endif
-
- /**
- * @brief PowerOn the sensor
- * @return void
- */
- /* turns on the sensor */
- void VL53L0X_on(void)
- {
-#if ORIGINAL
- if (_gpio0) {
- *_gpio0 = 1;
- } else {
- if (_expgpio0) {
- *_expgpio0 = 1;
- }
- }
- wait_ms(10);
-#else
- _gpio0.output();
- _gpio0 = 1;
- _gpio0.input();
- WAIT_MS(1);
-#endif
- }
-
- /**
- * @brief PowerOff the sensor
- * @return void
- */
- /* turns off the sensor */
- void VL53L0X_off(void)
- {
-#if ORIGINAL
- if (_gpio0) {
- *_gpio0 = 0;
- } else {
- if (_expgpio0) {
- *_expgpio0 = 0;
- }
- }
- wait_ms(10);
-#else
- _gpio0 = 0;
- _gpio0.output();
- WAIT_MS(10);
-#endif
- }
-
- /**
- * @brief Initialize the sensor with default values
- * @param[in] new I2C address
- * @return "0" on success
- */
- int init_sensor(uint8_t new_addr);
-
-#if !ORIGINAL
- /**
- * @brief Start the measure by single shot operating mode
- * @param[in] operating mode
- * @return "0" on success
- */
- int set_mode(RangeProfile range_mode) {
- _range_mode = range_mode;
- return start_measurement(range_single_shot_polling, NULL);
- }
-
- /**
- * @brief Get ranging result and only that
- *
- * @par Function Description
- * Unlike @a VL53L0X_get_ranging_measurement_data()
- * this function only retrieves the range in millimeter \n
- * It does any required up-scale translation\n
- * It can be called after success status polling or in interrupt mode \n
- * @warning these function is not doing wrap around filtering \n
- * This function doesn't perform any data ready check!
- *
- * @param p_data Pointer to range distance
- * @return "0" on success
- */
- virtual int get_distance(uint32_t *p_data)
- {
- int status = 0;
- VL53L0X_RangingMeasurementData_t p_ranging_measurement_data;
-
-#if ORIGINAL
- status = start_measurement(range_single_shot_polling, NULL);
-#else
- status = VL53L0X_start_measurement(_device);
-#endif
- if (!status) {
- status = get_measurement(range_single_shot_polling,
- &p_ranging_measurement_data);
- }
- if (p_ranging_measurement_data.RangeStatus == 0) {
- // we have a valid range.
- *p_data = p_ranging_measurement_data.RangeMilliMeter;
- } else {
- *p_data = 0;
- status = VL53L0X_ERROR_RANGE_ERROR;
- }
- stop_measurement(range_single_shot_polling);
- return status;
- }
-#endif
-
-#if !ORIGINAL
-//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
-// moved to following header file
-#include "VL53L0X_2nd.h"
-//------------------------------------------------------------------------------
-#else
-#warning "please recover original functions form VL53L0X_2nd.h"
-#endif
-
-private:
-
-#if !ORIGINAL
-//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
-// moved to following header file
-#include "VL53L0X_3rd.h"
-//------------------------------------------------------------------------------
-#else
-#warning "please recover original functions form VL53L0X_3rd.h"
-#endif
-#if !ORIGINAL
- static const unsigned int TEMP_BUF_SIZE = 32;
-
- int i2c_write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr,
- uint16_t NumByteToWrite) {
- int ret;
- uint8_t tmp[TEMP_BUF_SIZE];
-
- if(NumByteToWrite >= TEMP_BUF_SIZE) return -2;
- /* First, send device address. Then, send data and STOP condition */
- tmp[0] = RegisterAddr;
- memcpy(tmp+1, pBuffer, NumByteToWrite);
- ret = _i2c.write(DeviceAddr, (const char*)tmp, NumByteToWrite+1, false);
- if(ret) return -1;
- return 0;
- }
-
- int i2c_read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr,
- uint16_t NumByteToRead) {
- int ret;
-
- //--debug--
- //myled = 1;
- /* Send device address, with no STOP condition */
- ret = _i2c.write(DeviceAddr, (const char*)&RegisterAddr, 1, true);
- //--debug--
- //myled = 0;
- if(!ret) {
- /* Read data, with STOP condition */
- ret = _i2c.read(DeviceAddr, (char*)pBuffer, NumByteToRead, false);
- }
- if(ret) return -1;
- return 0;
- }
-#endif
-
- VL53L0X_DeviceInfo_t _device_info;
-
-#if !ORIGINAL
- RangeProfile _range_mode;
-#endif
-
-#if ORIGINAL
- /* IO Device */
- DevI2C *_dev_i2c;
- /* Digital out pin */
- DigitalOut *_gpio0;
- /* GPIO expander */
- Stmpe1600DigiOut *_expgpio0;
-#else
- /* IO Device */
- I2C *_i2c_p;
- I2C &_i2c;
- /* Digital in and out pin */
- DigitalInOut _gpio0;
-#endif
- /* Measure detection IRQ */
- InterruptIn *_gpio1Int;
- /* Device data */
- VL53L0X_Dev_t _my_device;
- VL53L0X_DEV _device;
-};
-
-#endif /* _VL53L0X_CLASS_H_ */
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_1st.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,221 +0,0 @@ - -/** - * The device model ID - */ -#define IDENTIFICATION_MODEL_ID 0x000 - - -#define STATUS_OK 0x00 -#define STATUS_FAIL 0x01 - -#if ORIGINAL -#define VL53L0X_OsDelay(...) wait_ms(2) // 2 msec delay. can also use wait(float secs)/wait_us(int) -#endif - -#ifdef USE_EMPTY_STRING -#define VL53L0X_STRING_DEVICE_INFO_NAME "" -#define VL53L0X_STRING_DEVICE_INFO_NAME_TS0 "" -#define VL53L0X_STRING_DEVICE_INFO_NAME_TS1 "" -#define VL53L0X_STRING_DEVICE_INFO_NAME_TS2 "" -#define VL53L0X_STRING_DEVICE_INFO_NAME_ES1 "" -#define VL53L0X_STRING_DEVICE_INFO_TYPE "" - -/* PAL ERROR strings */ -#define VL53L0X_STRING_ERROR_NONE "" -#define VL53L0X_STRING_ERROR_CALIBRATION_WARNING "" -#define VL53L0X_STRING_ERROR_MIN_CLIPPED "" -#define VL53L0X_STRING_ERROR_UNDEFINED "" -#define VL53L0X_STRING_ERROR_INVALID_PARAMS "" -#define VL53L0X_STRING_ERROR_NOT_SUPPORTED "" -#define VL53L0X_STRING_ERROR_RANGE_ERROR "" -#define VL53L0X_STRING_ERROR_TIME_OUT "" -#define VL53L0X_STRING_ERROR_MODE_NOT_SUPPORTED "" -#define VL53L0X_STRING_ERROR_BUFFER_TOO_SMALL "" -#define VL53L0X_STRING_ERROR_GPIO_NOT_EXISTING "" -#define VL53L0X_STRING_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED "" -#define VL53L0X_STRING_ERROR_CONTROL_INTERFACE "" -#define VL53L0X_STRING_ERROR_INVALID_COMMAND "" -#define VL53L0X_STRING_ERROR_DIVISION_BY_ZERO "" -#define VL53L0X_STRING_ERROR_REF_SPAD_INIT "" -#define VL53L0X_STRING_ERROR_NOT_IMPLEMENTED "" - -#define VL53L0X_STRING_UNKNOW_ERROR_CODE "" - - - -/* Range Status */ -#define VL53L0X_STRING_RANGESTATUS_NONE "" -#define VL53L0X_STRING_RANGESTATUS_RANGEVALID "" -#define VL53L0X_STRING_RANGESTATUS_SIGMA "" -#define VL53L0X_STRING_RANGESTATUS_SIGNAL "" -#define VL53L0X_STRING_RANGESTATUS_MINRANGE "" -#define VL53L0X_STRING_RANGESTATUS_PHASE "" -#define VL53L0X_STRING_RANGESTATUS_HW "" - - -/* Range Status */ -#define VL53L0X_STRING_STATE_POWERDOWN "" -#define VL53L0X_STRING_STATE_WAIT_STATICINIT "" -#define VL53L0X_STRING_STATE_STANDBY "" -#define VL53L0X_STRING_STATE_IDLE "" -#define VL53L0X_STRING_STATE_RUNNING "" -#define VL53L0X_STRING_STATE_UNKNOWN "" -#define VL53L0X_STRING_STATE_ERROR "" - - -/* Device Specific */ -#define VL53L0X_STRING_DEVICEERROR_NONE "" -#define VL53L0X_STRING_DEVICEERROR_VCSELCONTINUITYTESTFAILURE "" -#define VL53L0X_STRING_DEVICEERROR_VCSELWATCHDOGTESTFAILURE "" -#define VL53L0X_STRING_DEVICEERROR_NOVHVVALUEFOUND "" -#define VL53L0X_STRING_DEVICEERROR_MSRCNOTARGET "" -#define VL53L0X_STRING_DEVICEERROR_SNRCHECK "" -#define VL53L0X_STRING_DEVICEERROR_RANGEPHASECHECK "" -#define VL53L0X_STRING_DEVICEERROR_SIGMATHRESHOLDCHECK "" -#define VL53L0X_STRING_DEVICEERROR_TCC "" -#define VL53L0X_STRING_DEVICEERROR_PHASECONSISTENCY "" -#define VL53L0X_STRING_DEVICEERROR_MINCLIP "" -#define VL53L0X_STRING_DEVICEERROR_RANGECOMPLETE "" -#define VL53L0X_STRING_DEVICEERROR_ALGOUNDERFLOW "" -#define VL53L0X_STRING_DEVICEERROR_ALGOOVERFLOW "" -#define VL53L0X_STRING_DEVICEERROR_RANGEIGNORETHRESHOLD "" -#define VL53L0X_STRING_DEVICEERROR_UNKNOWN "" - -/* Check Enable */ -#define VL53L0X_STRING_CHECKENABLE_SIGMA_FINAL_RANGE "" -#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE "" -#define VL53L0X_STRING_CHECKENABLE_SIGNAL_REF_CLIP "" -#define VL53L0X_STRING_CHECKENABLE_RANGE_IGNORE_THRESHOLD "" - -/* Sequence Step */ -#define VL53L0X_STRING_SEQUENCESTEP_TCC "" -#define VL53L0X_STRING_SEQUENCESTEP_DSS "" -#define VL53L0X_STRING_SEQUENCESTEP_MSRC "" -#define VL53L0X_STRING_SEQUENCESTEP_PRE_RANGE "" -#define VL53L0X_STRING_SEQUENCESTEP_FINAL_RANGE "" -#else -#define VL53L0X_STRING_DEVICE_INFO_NAME "VL53L0X cut1.0" -#define VL53L0X_STRING_DEVICE_INFO_NAME_TS0 "VL53L0X TS0" -#define VL53L0X_STRING_DEVICE_INFO_NAME_TS1 "VL53L0X TS1" -#define VL53L0X_STRING_DEVICE_INFO_NAME_TS2 "VL53L0X TS2" -#define VL53L0X_STRING_DEVICE_INFO_NAME_ES1 "VL53L0X ES1 or later" -#define VL53L0X_STRING_DEVICE_INFO_TYPE "VL53L0X" - -/* PAL ERROR strings */ -#define VL53L0X_STRING_ERROR_NONE \ - "No Error" -#define VL53L0X_STRING_ERROR_CALIBRATION_WARNING \ - "Calibration Warning Error" -#define VL53L0X_STRING_ERROR_MIN_CLIPPED \ - "Min clipped error" -#define VL53L0X_STRING_ERROR_UNDEFINED \ - "Undefined error" -#define VL53L0X_STRING_ERROR_INVALID_PARAMS \ - "Invalid parameters error" -#define VL53L0X_STRING_ERROR_NOT_SUPPORTED \ - "Not supported error" -#define VL53L0X_STRING_ERROR_RANGE_ERROR \ - "Range error" -#define VL53L0X_STRING_ERROR_TIME_OUT \ - "Time out error" -#define VL53L0X_STRING_ERROR_MODE_NOT_SUPPORTED \ - "Mode not supported error" -#define VL53L0X_STRING_ERROR_BUFFER_TOO_SMALL \ - "Buffer too small" -#define VL53L0X_STRING_ERROR_GPIO_NOT_EXISTING \ - "GPIO not existing" -#define VL53L0X_STRING_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED \ - "GPIO funct not supported" -#define VL53L0X_STRING_ERROR_INTERRUPT_NOT_CLEARED \ - "Interrupt not Cleared" -#define VL53L0X_STRING_ERROR_CONTROL_INTERFACE \ - "Control Interface Error" -#define VL53L0X_STRING_ERROR_INVALID_COMMAND \ - "Invalid Command Error" -#define VL53L0X_STRING_ERROR_DIVISION_BY_ZERO \ - "Division by zero Error" -#define VL53L0X_STRING_ERROR_REF_SPAD_INIT \ - "Reference Spad Init Error" -#define VL53L0X_STRING_ERROR_NOT_IMPLEMENTED \ - "Not implemented error" - -#define VL53L0X_STRING_UNKNOW_ERROR_CODE \ - "Unknown Error Code" - - - -/* Range Status */ -#define VL53L0X_STRING_RANGESTATUS_NONE "No Update" -#define VL53L0X_STRING_RANGESTATUS_RANGEVALID "Range Valid" -#define VL53L0X_STRING_RANGESTATUS_SIGMA "Sigma Fail" -#define VL53L0X_STRING_RANGESTATUS_SIGNAL "Signal Fail" -#define VL53L0X_STRING_RANGESTATUS_MINRANGE "Min Range Fail" -#define VL53L0X_STRING_RANGESTATUS_PHASE "Phase Fail" -#define VL53L0X_STRING_RANGESTATUS_HW "Hardware Fail" - - -/* Range Status */ -#define VL53L0X_STRING_STATE_POWERDOWN "POWERDOWN State" -#define VL53L0X_STRING_STATE_WAIT_STATICINIT \ - "Wait for staticinit State" -#define VL53L0X_STRING_STATE_STANDBY "STANDBY State" -#define VL53L0X_STRING_STATE_IDLE "IDLE State" -#define VL53L0X_STRING_STATE_RUNNING "RUNNING State" -#define VL53L0X_STRING_STATE_UNKNOWN "UNKNOWN State" -#define VL53L0X_STRING_STATE_ERROR "ERROR State" - - -/* Device Specific */ -#define VL53L0X_STRING_DEVICEERROR_NONE "No Update" -#define VL53L0X_STRING_DEVICEERROR_VCSELCONTINUITYTESTFAILURE \ - "VCSEL Continuity Test Failure" -#define VL53L0X_STRING_DEVICEERROR_VCSELWATCHDOGTESTFAILURE \ - "VCSEL Watchdog Test Failure" -#define VL53L0X_STRING_DEVICEERROR_NOVHVVALUEFOUND \ - "No VHV Value found" -#define VL53L0X_STRING_DEVICEERROR_MSRCNOTARGET \ - "MSRC No Target Error" -#define VL53L0X_STRING_DEVICEERROR_SNRCHECK \ - "SNR Check Exit" -#define VL53L0X_STRING_DEVICEERROR_RANGEPHASECHECK \ - "Range Phase Check Error" -#define VL53L0X_STRING_DEVICEERROR_SIGMATHRESHOLDCHECK \ - "Sigma Threshold Check Error" -#define VL53L0X_STRING_DEVICEERROR_TCC \ - "TCC Error" -#define VL53L0X_STRING_DEVICEERROR_PHASECONSISTENCY \ - "Phase Consistency Error" -#define VL53L0X_STRING_DEVICEERROR_MINCLIP \ - "Min Clip Error" -#define VL53L0X_STRING_DEVICEERROR_RANGECOMPLETE \ - "Range Complete" -#define VL53L0X_STRING_DEVICEERROR_ALGOUNDERFLOW \ - "Range Algo Underflow Error" -#define VL53L0X_STRING_DEVICEERROR_ALGOOVERFLOW \ - "Range Algo Overlow Error" -#define VL53L0X_STRING_DEVICEERROR_RANGEIGNORETHRESHOLD \ - "Range Ignore Threshold Error" -#define VL53L0X_STRING_DEVICEERROR_UNKNOWN \ - "Unknown error code" - -/* Check Enable */ -#define VL53L0X_STRING_CHECKENABLE_SIGMA_FINAL_RANGE \ - "SIGMA FINAL RANGE" -#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE \ - "SIGNAL RATE FINAL RANGE" -#define VL53L0X_STRING_CHECKENABLE_SIGNAL_REF_CLIP \ - "SIGNAL REF CLIP" -#define VL53L0X_STRING_CHECKENABLE_RANGE_IGNORE_THRESHOLD \ - "RANGE IGNORE THRESHOLD" -#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_MSRC \ - "SIGNAL RATE MSRC" -#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_PRE_RANGE \ - "SIGNAL RATE PRE RANGE" - -/* Sequence Step */ -#define VL53L0X_STRING_SEQUENCESTEP_TCC "TCC" -#define VL53L0X_STRING_SEQUENCESTEP_DSS "DSS" -#define VL53L0X_STRING_SEQUENCESTEP_MSRC "MSRC" -#define VL53L0X_STRING_SEQUENCESTEP_PRE_RANGE "PRE RANGE" -#define VL53L0X_STRING_SEQUENCESTEP_FINAL_RANGE "FINAL RANGE" -#endif /* USE_EMPTY_STRING */
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_2nd.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1446 +0,0 @@
-
- /**
- * @brief Start the measure indicated by operating mode
- * @param[in] operating_mode specifies requested measure
- * @param[in] fptr specifies call back function must be !NULL in case of interrupt measure
- * @return "0" on success
- */
- int start_measurement(OperatingMode operating_mode, void (*fptr)(void));
-
- /**
- * @brief Get results for the measure indicated by operating mode
- * @param[in] operating_mode specifies requested measure results
- * @param[out] p_data pointer to the MeasureData_t structure to read data in to
- * @return "0" on success
- */
- int get_measurement(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *p_data);
-
- /**
- * @brief Stop the currently running measure indicate by operating_mode
- * @param[in] operating_mode specifies requested measure to stop
- * @return "0" on success
- */
- int stop_measurement(OperatingMode operating_mode);
-
- /**
- * @brief Interrupt handling func to be called by user after an INT is occourred
- * @param[in] opeating_mode indicating the in progress measure
- * @param[out] Data pointer to the MeasureData_t structure to read data in to
- * @return "0" on success
- */
- int handle_irq(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *data);
-
- /**
- * @brief Enable interrupt measure IRQ
- * @return "0" on success
- */
- void enable_interrupt_measure_detection_irq(void)
- {
- if (_gpio1Int != NULL) {
- _gpio1Int->enable_irq();
- }
- }
-
- /**
- * @brief Disable interrupt measure IRQ
- * @return "0" on success
- */
- void disable_interrupt_measure_detection_irq(void)
- {
- if (_gpio1Int != NULL) {
- _gpio1Int->disable_irq();
- }
- }
-
- /**
- * @brief Attach a function to call when an interrupt is detected, i.e. measurement is ready
- * @param[in] fptr pointer to call back function to be called whenever an interrupt occours
- * @return "0" on success
- */
- void attach_interrupt_measure_detection_irq(void (*fptr)(void))
- {
- if (_gpio1Int != NULL) {
- _gpio1Int->rise(fptr);
- }
- }
-
-
- /** Wrapper functions */
- /** @defgroup api_init Init functions
- * @brief API init functions
- * @ingroup api_hl
- * @{
- */
-
- /**
- *
- * @brief One time device initialization
- *
- * To be called once and only once after device is brought out of reset (Chip enable) and booted.
- *
- * @par Function Description
- * When not used after a fresh device "power up" or reset, it may return @a #CALIBRATION_WARNING
- * meaning wrong calibration data may have been fetched from device that can result in ranging offset error\n
- * If application cannot execute device reset or need to run VL53L0X_data_init multiple time
- * then it must ensure proper offset calibration saving and restore on its own
- * by using @a VL53L0X_get_offset_calibration_data_micro_meter() on first power up and then @a VL53L0X_set_offset_calibration_data_micro_meter() all all subsequent init
- *
- * @param void
- * @return "0" on success, @a #CALIBRATION_WARNING if failed
- */
- virtual int init(void *init)
- {
- return VL53L0X_data_init(_device);
- }
-
- /**
- * @brief Prepare device for operation
- * @par Function Description
- * Does static initialization and reprogram common default settings \n
- * Device is prepared for new measure, ready single shot ranging or ALS typical polling operation\n
- * After prepare user can : \n
- * @li Call other API function to set other settings\n
- * @li Configure the interrupt pins, etc... \n
- * @li Then start ranging or ALS operations in single shot or continuous mode
- *
- * @param void
- * @return "0" on success
- */
- int prepare()
- {
- VL53L0X_Error status = VL53L0X_ERROR_NONE;
- uint32_t ref_spad_count;
- uint8_t is_aperture_spads;
- uint8_t vhv_settings;
- uint8_t phase_cal;
-
- if (status == VL53L0X_ERROR_NONE) {
- //printf("Call of VL53L0X_StaticInit\r\n");
- status = VL53L0X_static_init(_device); // Device Initialization
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- //printf("Call of VL53L0X_PerformRefCalibration\r\n");
- status = VL53L0X_perform_ref_calibration(_device,
- &vhv_settings, &phase_cal); // Device Initialization
- }
-
- if (status == VL53L0X_ERROR_NONE) {
- //printf("Call of VL53L0X_PerformRefSpadManagement\r\n");
- status = VL53L0X_perform_ref_spad_management(_device,
- &ref_spad_count, &is_aperture_spads); // Device Initialization
-// printf ("refSpadCount = %d, isApertureSpads = %d\r\n", refSpadCount, isApertureSpads);
- }
-
- return status;
- }
-
- /**
- * @brief Start continuous ranging mode
- *
- * @details End user should ensure device is in idle state and not already running
- * @return "0" on success
- */
- int range_start_continuous_mode()
- {
- int status;
- status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING);
-
- if (status == VL53L0X_ERROR_NONE) {
- //printf ("Call of VL53L0X_StartMeasurement\r\n");
- status = VL53L0X_start_measurement(_device);
- }
-
- return status;
- }
-
-//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
-#if ORIGINAL
- /**
- * @brief Get ranging result and only that
- *
- * @par Function Description
- * Unlike @a VL53L0X_get_ranging_measurement_data() this function only retrieves the range in millimeter \n
- * It does any required up-scale translation\n
- * It can be called after success status polling or in interrupt mode \n
- * @warning these function is not doing wrap around filtering \n
- * This function doesn't perform any data ready check!
- *
- * @param p_data Pointer to range distance
- * @return "0" on success
- */
- virtual int get_distance(uint32_t *p_data)
- {
- int status = 0;
- VL53L0X_RangingMeasurementData_t p_ranging_measurement_data;
-
- status = start_measurement(range_single_shot_polling, NULL);
- if (!status) {
- status = get_measurement(range_single_shot_polling, &p_ranging_measurement_data);
- }
- if (p_ranging_measurement_data.RangeStatus == 0) {
- // we have a valid range.
- *p_data = p_ranging_measurement_data.RangeMilliMeter;
- } else {
- *p_data = 0;
- status = VL53L0X_ERROR_RANGE_ERROR;
- }
- stop_measurement(range_single_shot_polling);
- return status;
- }
-#endif
-
- /** @} */
-
- /**
- * @brief Set new device i2c address
- *
- * After completion the device will answer to the new address programmed.
- *
- * @param new_addr The new i2c address (7bit)
- * @return "0" on success
- */
- int set_device_address(int new_addr)
- {
- int status;
-
- status = VL53L0X_set_device_address(_device, new_addr);
- if (!status) {
- _device->I2cDevAddr = new_addr;
- }
- return status;
-
- }
-
- /**
- * @brief Clear given system interrupt condition
- *
- * @par Function Description
- * Clear given interrupt cause by writing into register #SYSTEM_INTERRUPT_CLEAR register.
- * @param dev The device
- * @param int_clear Which interrupt source to clear. Use any combinations of #INTERRUPT_CLEAR_RANGING , #INTERRUPT_CLEAR_ALS , #INTERRUPT_CLEAR_ERROR.
- * @return "0" on success
- */
- int clear_interrupt(uint8_t int_clear)
- {
- return VL53L0X_clear_interrupt_mask(_device, int_clear);
- }
-
- /**
- *
- * @brief Get the 53L0 device
- *
- * To be called to retrive the internal device descriptor to allow usage of
- * low level API having device as parameter. To be called after set_device_address()
- * (if any).
- *
- * @par Function Description
- * To be called if low level API usage is needed as those functions requires
- * device as a parameter.TICINIT.
- *
- * @note This function return a pointer to an object internal structure
- *
- * @param dev ptr to ptr to Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error vl53l0x_get_device(VL53L0X_DEV *dev)
-{
- *dev = _device;
- return VL53L0X_ERROR_NONE;
-}
-
- /**
- *
- * @brief One time device initialization
- *
- * To be called once and only once after device is brought out of reset
- * (Chip enable) and booted see @a VL53L0X_WaitDeviceBooted()
- *
- * @par Function Description
- * When not used after a fresh device "power up" or reset, it may return
- * @a #VL53L0X_ERROR_CALIBRATION_WARNING meaning wrong calibration data
- * may have been fetched from device that can result in ranging offset error\n
- * If application cannot execute device reset or need to run VL53L0X_DataInit
- * multiple time then it must ensure proper offset calibration saving and
- * restore on its own by using @a VL53L0X_GetOffsetCalibrationData() on first
- * power up and then @a VL53L0X_SetOffsetCalibrationData() in all subsequent init
- * This function will change the VL53L0X_State from VL53L0X_STATE_POWERDOWN to
- * VL53L0X_STATE_WAIT_STATICINIT.
- *
- * @note This function accesses to the device
- *
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_data_init(VL53L0X_DEV dev);
-
- /**
- * @brief Do basic device init (and eventually patch loading)
- * This function will change the VL53L0X_State from
- * VL53L0X_STATE_WAIT_STATICINIT to VL53L0X_STATE_IDLE.
- * In this stage all default setting will be applied.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_static_init(VL53L0X_DEV dev);
-
- /**
- * @brief Perform Reference Calibration
- *
- * @details Perform a reference calibration of the Device.
- * This function should be run from time to time before doing
- * a ranging measurement.
- * This function will launch a special ranging measurement, so
- * if interrupt are enable an interrupt will be done.
- * This function will clear the interrupt generated automatically.
- *
- * @warning This function is a blocking function
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_vhv_settings Pointer to vhv settings parameter.
- * @param p_phase_cal Pointer to PhaseCal parameter.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_perform_ref_calibration(VL53L0X_DEV dev, uint8_t *p_vhv_settings,
- uint8_t *p_phase_cal);
-
- /**
- * @brief Get Reference Calibration Parameters
- *
- * @par Function Description
- * Get Reference Calibration Parameters.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_vhv_settings Pointer to VHV parameter
- * @param p_phase_cal Pointer to PhaseCal Parameter
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_ref_calibration(VL53L0X_DEV dev,
- uint8_t *p_vhv_settings, uint8_t *p_phase_cal);
-
- VL53L0X_Error VL53L0X_set_ref_calibration(VL53L0X_DEV dev,
- uint8_t vhv_settings, uint8_t phase_cal);
-
- /**
- * @brief Performs Reference Spad Management
- *
- * @par Function Description
- * The reference SPAD initialization procedure determines the minimum amount
- * of reference spads to be enables to achieve a target reference signal rate
- * and should be performed once during initialization.
- *
- * @note This function Access to the device
- *
- * @note This function change the device mode to
- * VL53L0X_DEVICEMODE_SINGLE_RANGING
- *
- * @param dev Device Handle
- * @param ref_spad_count Reports ref Spad Count
- * @param is_aperture_spads Reports if spads are of type
- * aperture or non-aperture.
- * 1:=aperture, 0:=Non-Aperture
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the Ref Spad procedure.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
- uint32_t *ref_spad_count, uint8_t *is_aperture_spads);
-
- /**
- * @brief Applies Reference SPAD configuration
- *
- * @par Function Description
- * This function applies a given number of reference spads, identified as
- * either Aperture or Non-Aperture.
- * The requested spad count and type are stored within the device specific
- * parameters data for access by the host.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param refSpadCount Number of ref spads.
- * @param is_aperture_spads Defines if spads are of type
- * aperture or non-aperture.
- * 1:=aperture, 0:=Non-Aperture
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the in the reference
- * spad configuration.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_reference_spads(VL53L0X_DEV dev,
- uint32_t refSpadCount, uint8_t is_aperture_spads);
-
- /**
- * @brief Retrieves SPAD configuration
- *
- * @par Function Description
- * This function retrieves the current number of applied reference spads
- * and also their type : Aperture or Non-Aperture.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_spad_count Number ref Spad Count
- * @param p_is_aperture_spads Reports if spads are of type
- * aperture or non-aperture.
- * 1:=aperture, 0:=Non-Aperture
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the in the reference
- * spad configuration.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_reference_spads(VL53L0X_DEV dev,
- uint32_t *p_spad_count, uint8_t *p_is_aperture_spads);
-
- /**
- * @brief Get part to part calibration offset
- *
- * @par Function Description
- * Should only be used after a successful call to @a VL53L0X_DataInit to backup
- * device NVM value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_offset_calibration_data_micro_meter Return part to part
- * calibration offset from device (microns)
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t *p_offset_calibration_data_micro_meter);
- /**
- * Set or over-hide part to part calibration offset
- * \sa VL53L0X_DataInit() VL53L0X_GetOffsetCalibrationDataMicroMeter()
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_offset_calibration_data_micro_meter Offset (microns)
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t offset_calibration_data_micro_meter);
-
- VL53L0X_Error VL53L0X_perform_offset_calibration(VL53L0X_DEV dev,
- FixPoint1616_t cal_distance_milli_meter,
- int32_t *p_offset_micro_meter);
-
- VL53L0X_Error VL53L0X_perform_xtalk_calibration(VL53L0X_DEV dev,
- FixPoint1616_t xtalk_cal_distance,
- FixPoint1616_t *p_xtalk_compensation_rate_mega_cps);
-
- /**
- * @brief Perform XTalk Measurement
- *
- * @details Measures the current cross talk from glass in front
- * of the sensor.
- * This functions performs a histogram measurement and uses the results
- * to measure the crosstalk. For the function to be successful, there
- * must be no target in front of the sensor.
- *
- * @warning This function is a blocking function
- *
- * @warning This function is not supported when the final range
- * vcsel clock period is set below 10 PCLKS.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param timeout_ms Histogram measurement duration.
- * @param p_xtalk_per_spad Output parameter containing the crosstalk
- * measurement result, in MCPS/Spad.
- * Format fixpoint 16:16.
- * @param p_ambient_too_high Output parameter which indicate that
- * pXtalkPerSpad is not good if the Ambient
- * is too high.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS vcsel clock period not supported
- * for this operation.
- * Must not be less than 10PCLKS.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_perform_xtalk_measurement(VL53L0X_DEV dev,
- uint32_t timeout_ms, FixPoint1616_t *p_xtalk_per_spad,
- uint8_t *p_ambient_too_high);
-
- /**
- * @brief Enable/Disable Cross talk compensation feature
- *
- * @note This function is not Implemented.
- * Enable/Disable Cross Talk by set to zero the Cross Talk value
- * by using @a VL53L0X_SetXTalkCompensationRateMegaCps().
- *
- * @param dev Device Handle
- * @param x_talk_compensation_enable Cross talk compensation
- * to be set 0=disabled else = enabled
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- */
- VL53L0X_Error VL53L0X_set_x_talk_compensation_enable(VL53L0X_DEV dev,
- uint8_t x_talk_compensation_enable);
-
- /**
- * @brief Get Cross talk compensation rate
- *
- * @note This function is not Implemented.
- * Enable/Disable Cross Talk by set to zero the Cross Talk value by
- * using @a VL53L0X_SetXTalkCompensationRateMegaCps().
- *
- * @param dev Device Handle
- * @param p_x_talk_compensation_enable Pointer to the Cross talk compensation
- * state 0=disabled or 1 = enabled
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- */
- VL53L0X_Error VL53L0X_get_x_talk_compensation_enable(VL53L0X_DEV dev,
- uint8_t *p_x_talk_compensation_enable);
- /**
- * @brief Set Cross talk compensation rate
- *
- * @par Function Description
- * Set Cross talk compensation rate.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param x_talk_compensation_rate_mega_cps Compensation rate in
- * Mega counts per second
- * (16.16 fix point) see
- * datasheet for details
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_x_talk_compensation_rate_mega_cps(VL53L0X_DEV dev,
- FixPoint1616_t x_talk_compensation_rate_mega_cps);
-
- /**
- * @brief Get Cross talk compensation rate
- *
- * @par Function Description
- * Get Cross talk compensation rate.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_xtalk_compensation_rate_mega_cps Pointer to Compensation rate
- * in Mega counts per second
- * (16.16 fix point) see
- * datasheet for details
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_x_talk_compensation_rate_mega_cps(VL53L0X_DEV dev,
- FixPoint1616_t *p_xtalk_compensation_rate_mega_cps);
-
- /**
- * @brief Set a new device mode
- * @par Function Description
- * Set device to a new mode (ranging, histogram ...)
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param device_mode New device mode to apply
- * Valid values are:
- * VL53L0X_DEVICEMODE_SINGLE_RANGING
- * VL53L0X_DEVICEMODE_CONTINUOUS_RANGING
- * VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING
- * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
- * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
- * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
- * VL53L0X_HISTOGRAMMODE_BOTH
- *
- *
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
- * DeviceMode is not in the
- * supported list
- */
- VL53L0X_Error VL53L0X_set_device_mode(VL53L0X_DEV dev, VL53L0X_DeviceModes device_mode);
-
- /**
- * @brief Get current new device mode
- * @par Function Description
- * Get actual mode of the device(ranging, histogram ...)
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param p_device_mode Pointer to current apply mode value
- * Valid values are:
- * VL53L0X_DEVICEMODE_SINGLE_RANGING
- * VL53L0X_DEVICEMODE_CONTINUOUS_RANGING
- * VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING
- * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
- * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
- * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
- * VL53L0X_HISTOGRAMMODE_BOTH
- *
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
- * DeviceMode is not in the
- * supported list
- */
- VL53L0X_Error VL53L0X_get_device_mode(VL53L0X_DEV dev,
- VL53L0X_DeviceModes *p_device_mode);
-
- /**
- * @brief Get current configuration for GPIO pin for a given device
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param pin ID of the GPIO Pin
- * @param p_device_mode Pointer to Device Mode associated to the Gpio.
- * @param p_functionality Pointer to Pin functionality.
- * Refer to ::VL53L0X_GpioFunctionality
- * @param p_polarity Pointer to interrupt polarity.
- * Active high or active low see
- * ::VL53L0X_InterruptPolarity
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_GPIO_NOT_EXISTING Only Pin=0 is accepted.
- * @return VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED
- * This error occurs
- * when Funcionality programmed is not in the supported list:
- * Supported value are:
- * VL53L0X_GPIOFUNCTIONALITY_OFF,
- * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW,
- * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH,
- * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT,
- * VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_gpio_config(VL53L0X_DEV dev, uint8_t pin,
- VL53L0X_DeviceModes *p_device_mode,
- VL53L0X_GpioFunctionality *p_functionality,
- VL53L0X_InterruptPolarity *p_polarity);
-
- /**
- * @brief Set the configuration of GPIO pin for a given device
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param pin ID of the GPIO Pin
- * @param functionality Select Pin functionality.
- * Refer to ::VL53L0X_GpioFunctionality
- * @param device_mode Device Mode associated to the Gpio.
- * @param polarity Set interrupt polarity. Active high
- * or active low see ::VL53L0X_InterruptPolarity
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_GPIO_NOT_EXISTING Only Pin=0 is accepted.
- * @return VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED This error occurs
- * when Functionality programmed is not in the supported list:
- * Supported value are:
- * VL53L0X_GPIOFUNCTIONALITY_OFF,
- * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW,
- * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH,
- VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT,
- * VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_gpio_config(VL53L0X_DEV dev, uint8_t pin,
- VL53L0X_DeviceModes device_mode, VL53L0X_GpioFunctionality functionality,
- VL53L0X_InterruptPolarity polarity);
-
- /**
- * @brief Start device measurement
- *
- * @details Started measurement will depend on device parameters set through
- * @a VL53L0X_SetParameters()
- * This is a non-blocking function.
- * This function will change the VL53L0X_State from VL53L0X_STATE_IDLE to
- * VL53L0X_STATE_RUNNING.
- *
- * @note This function Access to the device
- *
-
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
- * DeviceMode programmed with @a VL53L0X_SetDeviceMode is not in the supported
- * list:
- * Supported mode are:
- * VL53L0X_DEVICEMODE_SINGLE_RANGING,
- * VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
- * VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING
- * @return VL53L0X_ERROR_TIME_OUT Time out on start measurement
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_start_measurement(VL53L0X_DEV dev);
-
- /**
- * @brief Stop device measurement
- *
- * @details Will set the device in standby mode at end of current measurement\n
- * Not necessary in single mode as device shall return automatically
- * in standby mode at end of measurement.
- * This function will change the VL53L0X_State from VL53L0X_STATE_RUNNING
- * to VL53L0X_STATE_IDLE.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_stop_measurement(VL53L0X_DEV dev);
-
- /**
- * @brief Return device stop completion status
- *
- * @par Function Description
- * Returns stop completiob status.
- * User shall call this function after a stop command
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_stop_status Pointer to status variable to update
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_stop_completed_status(VL53L0X_DEV dev,
- uint32_t *p_stop_status);
-
- /**
- * @brief Return Measurement Data Ready
- *
- * @par Function Description
- * This function indicate that a measurement data is ready.
- * This function check if interrupt mode is used then check is done accordingly.
- * If perform function clear the interrupt, this function will not work,
- * like in case of @a VL53L0X_PerformSingleRangingMeasurement().
- * The previous function is blocking function, VL53L0X_GetMeasurementDataReady
- * is used for non-blocking capture.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_measurement_data_ready Pointer to Measurement Data Ready.
- * 0=data not ready, 1 = data ready
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_measurement_data_ready(VL53L0X_DEV dev,
- uint8_t *p_measurement_data_ready);
-
- /**
- * @brief Retrieve the measurements from device for a given setup
- *
- * @par Function Description
- * Get data from last successful Ranging measurement
- * @warning USER should take care about @a VL53L0X_GetNumberOfROIZones()
- * before get data.
- * PAL will fill a NumberOfROIZones times the corresponding data
- * structure used in the measurement function.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_ranging_measurement_data Pointer to the data structure to fill up.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_ranging_measurement_data(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data);
-
- /**
- * @brief Clear given system interrupt condition
- *
- * @par Function Description
- * Clear given interrupt(s).
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param interrupt_mask Mask of interrupts to clear
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INTERRUPT_NOT_CLEARED Cannot clear interrupts
- *
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_clear_interrupt_mask(VL53L0X_DEV dev, uint32_t interrupt_mask);
-
- /**
- * @brief Return device interrupt status
- *
- * @par Function Description
- * Returns currently raised interrupts by the device.
- * User shall be able to activate/deactivate interrupts through
- * @a VL53L0X_SetGpioConfig()
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_interrupt_mask_status Pointer to status variable to update
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_interrupt_mask_status(VL53L0X_DEV dev,
- uint32_t *p_interrupt_mask_status);
-
- /**
- * @brief Performs a single ranging measurement and retrieve the ranging
- * measurement data
- *
- * @par Function Description
- * This function will change the device mode to VL53L0X_DEVICEMODE_SINGLE_RANGING
- * with @a VL53L0X_SetDeviceMode(),
- * It performs measurement with @a VL53L0X_PerformSingleMeasurement()
- * It get data from last successful Ranging measurement with
- * @a VL53L0X_GetRangingMeasurementData.
- * Finally it clear the interrupt with @a VL53L0X_ClearInterruptMask().
- *
- * @note This function Access to the device
- *
- * @note This function change the device mode to
- * VL53L0X_DEVICEMODE_SINGLE_RANGING
- *
- * @param dev Device Handle
- * @param p_ranging_measurement_data Pointer to the data structure to fill up.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_perform_single_ranging_measurement(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data);
-
- /**
- * @brief Single shot measurement.
- *
- * @par Function Description
- * Perform simple measurement sequence (Start measure, Wait measure to end,
- * and returns when measurement is done).
- * Once function returns, user can get valid data by calling
- * VL53L0X_GetRangingMeasurement or VL53L0X_GetHistogramMeasurement
- * depending on defined measurement mode
- * User should Clear the interrupt in case this are enabled by using the
- * function VL53L0X_ClearInterruptMask().
- *
- * @warning This function is a blocking function
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_perform_single_measurement(VL53L0X_DEV dev);
-
- /**
- * @brief Read current status of the error register for the selected device
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_device_error_status Pointer to current error code of the device
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_device_error_status(VL53L0X_DEV dev,
- VL53L0X_DeviceError *p_device_error_status);
-
- /**
- * @brief Human readable error string for a given Error Code
- *
- * @note This function doesn't access to the device
- *
- * @param error_code The error code as stored on ::VL53L0X_DeviceError
- * @param p_device_error_string The error string corresponding to the ErrorCode
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_device_error_string(
- VL53L0X_DeviceError error_code, char *p_device_error_string);
-
- /**
- * @brief Human readable Range Status string for a given RangeStatus
- *
- * @note This function doesn't access to the device
- *
- * @param range_status The RangeStatus code as stored on
- * @a VL53L0X_RangingMeasurementData_t
- * @param p_range_status_string The returned RangeStatus string.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_range_status_string(uint8_t range_status,
- char *p_range_status_string);
-
- VL53L0X_Error VL53L0X_get_total_signal_rate(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- FixPoint1616_t *p_total_signal_rate_mcps);
-
- VL53L0X_Error VL53L0X_get_total_xtalk_rate(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- FixPoint1616_t *p_total_xtalk_rate_mcps);
-
- /**
- * @brief Get Ranging Timing Budget in microseconds
- *
- * @par Function Description
- * Returns the programmed the maximum time allowed by the user to the
- * device to run a full ranging sequence for the current mode
- * (ranging, histogram, ASL ...)
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_measurement_timing_budget_micro_seconds Max measurement time in
- * microseconds.
- * Valid values are:
- * >= 17000 microsecs when wraparound enabled
- * >= 12000 microsecs when wraparound disabled
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t *p_measurement_timing_budget_micro_seconds);
-
- /**
- * @brief Set Ranging Timing Budget in microseconds
- *
- * @par Function Description
- * Defines the maximum time allowed by the user to the device to run a
- * full ranging sequence for the current mode (ranging, histogram, ASL ...)
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param measurement_timing_budget_micro_seconds Max measurement time in
- * microseconds.
- * Valid values are:
- * >= 17000 microsecs when wraparound enabled
- * >= 12000 microsecs when wraparound disabled
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned if
- MeasurementTimingBudgetMicroSeconds out of range
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t measurement_timing_budget_micro_seconds);
-
- /**
- * @brief Get specific limit check enable state
- *
- * @par Function Description
- * This function get the enable state of a specific limit check.
- * The limit check is identified with the LimitCheckId.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param limit_check_id Limit Check ID
- * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
- * @param p_limit_check_enable Pointer to the check limit enable
- * value.
- * if 1 the check limit
- * corresponding to LimitCheckId is Enabled
- * if 0 the check limit
- * corresponding to LimitCheckId is disabled
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned
- * when LimitCheckId value is out of range.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
- uint8_t *p_limit_check_enable);
-
- /**
- * @brief Enable/Disable a specific limit check
- *
- * @par Function Description
- * This function Enable/Disable a specific limit check.
- * The limit check is identified with the LimitCheckId.
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param limit_check_id Limit Check ID
- * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
- * @param limit_check_enable if 1 the check limit
- * corresponding to LimitCheckId is Enabled
- * if 0 the check limit
- * corresponding to LimitCheckId is disabled
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned
- * when LimitCheckId value is out of range.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
- uint8_t limit_check_enable);
-
- /**
- * @brief Get a specific limit check value
- *
- * @par Function Description
- * This function get a specific limit check value from device then it updates
- * internal values and check enables.
- * The limit check is identified with the LimitCheckId.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param limit_check_id Limit Check ID
- * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
- * @param p_limit_check_value Pointer to Limit
- * check Value for a given LimitCheckId.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned
- * when LimitCheckId value is out of range.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
- FixPoint1616_t *p_limit_check_value);
-
- /**
- * @brief Set a specific limit check value
- *
- * @par Function Description
- * This function set a specific limit check value.
- * The limit check is identified with the LimitCheckId.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param limit_check_id Limit Check ID
- * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
- * @param limit_check_value Limit check Value for a given
- * LimitCheckId
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned when either
- * LimitCheckId or LimitCheckValue value is out of range.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
- FixPoint1616_t limit_check_value);
-
- /**
- * @brief Get the current value of the signal used for the limit check
- *
- * @par Function Description
- * This function get a the current value of the signal used for the limit check.
- * To obtain the latest value you should run a ranging before.
- * The value reported is linked to the limit check identified with the
- * LimitCheckId.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param limit_check_id Limit Check ID
- * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
- * @param p_limit_check_current Pointer to current Value for a
- * given LimitCheckId.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned when
- * LimitCheckId value is out of range.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_limit_check_current(VL53L0X_DEV dev, uint16_t limit_check_id,
- FixPoint1616_t *p_limit_check_current);
-
- /**
- * @brief Return a the Status of the specified check limit
- *
- * @par Function Description
- * This function returns the Status of the specified check limit.
- * The value indicate if the check is fail or not.
- * The limit check is identified with the LimitCheckId.
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param limit_check_id Limit Check ID
- (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
- * @param p_limit_check_status Pointer to the
- Limit Check Status of the given check limit.
- * LimitCheckStatus :
- * 0 the check is not fail
- * 1 the check if fail or not enabled
- *
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is
- returned when LimitCheckId value is out of range.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_limit_check_status(VL53L0X_DEV dev,
- uint16_t limit_check_id, uint8_t *p_limit_check_status);
-
- /**
- * Get continuous mode Inter-Measurement period in milliseconds
- *
- * @par Function Description
- * When trying to set too short time return INVALID_PARAMS minimal value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_inter_measurement_period_milli_seconds Pointer to programmed
- * Inter-Measurement Period in milliseconds.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_inter_measurement_period_milli_seconds(VL53L0X_DEV dev,
- uint32_t *p_inter_measurement_period_milli_seconds);
-
- /**
- * Program continuous mode Inter-Measurement period in milliseconds
- *
- * @par Function Description
- * When trying to set too short time return INVALID_PARAMS minimal value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param inter_measurement_period_milli_seconds Inter-Measurement Period in ms.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_inter_measurement_period_milli_seconds(
- VL53L0X_DEV dev, uint32_t inter_measurement_period_milli_seconds);
-
- /**
- * @brief Set new device address
- *
- * After completion the device will answer to the new address programmed.
- * This function should be called when several devices are used in parallel
- * before start programming the sensor.
- * When a single device us used, there is no need to call this function.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param device_address The new Device address
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_device_address(VL53L0X_DEV dev, uint8_t device_address);
-
- /**
- * @brief Do an hard reset or soft reset (depending on implementation) of the
- * device \nAfter call of this function, device must be in same state as right
- * after a power-up sequence.This function will change the VL53L0X_State to
- * VL53L0X_STATE_POWERDOWN.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_reset_device(VL53L0X_DEV dev);
-
- /**
- * @brief Get setup of Wrap around Check
- *
- * @par Function Description
- * This function get the wrapAround check enable parameters
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_wrap_around_check_enable Pointer to the Wrap around Check state
- * 0=disabled or 1 = enabled
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_wrap_around_check_enable(VL53L0X_DEV dev,
- uint8_t *p_wrap_around_check_enable);
-
- /**
- * @brief Enable (or disable) Wrap around Check
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param wrap_around_check_enable Wrap around Check to be set
- * 0=disabled, other = enabled
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_wrap_around_check_enable(VL53L0X_DEV dev,
- uint8_t wrap_around_check_enable);
-
- /**
- * @brief Gets the VCSEL pulse period.
- *
- * @par Function Description
- * This function retrieves the VCSEL pulse period for the given period type.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param vcsel_period_type VCSEL period identifier (pre-range|final).
- * @param p_vcsel_pulse_period_pclk Pointer to VCSEL period value.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS Error VcselPeriodType parameter not
- * supported.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk);
-
- /**
- * @brief Sets the VCSEL pulse period.
- *
- * @par Function Description
- * This function retrieves the VCSEL pulse period for the given period type.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param vcsel_period_type VCSEL period identifier (pre-range|final).
- * @param vcsel_pulse_period VCSEL period value
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS Error VcselPeriodType parameter not
- * supported.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period);
-
- /**
- * @brief Set low and high Interrupt thresholds for a given mode
- * (ranging, ALS, ...) for a given device
- *
- * @par Function Description
- * Set low and high Interrupt thresholds for a given mode (ranging, ALS, ...)
- * for a given device
- *
- * @note This function Access to the device
- *
- * @note DeviceMode is ignored for the current device
- *
- * @param dev Device Handle
- * @param device_mode Device Mode for which change thresholds
- * @param threshold_low Low threshold (mm, lux ..., depending on the mode)
- * @param threshold_high High threshold (mm, lux ..., depending on the mode)
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_interrupt_thresholds(VL53L0X_DEV dev,
- VL53L0X_DeviceModes device_mode, FixPoint1616_t threshold_low,
- FixPoint1616_t threshold_high);
-
- /**
- * @brief Get high and low Interrupt thresholds for a given mode
- * (ranging, ALS, ...) for a given device
- *
- * @par Function Description
- * Get high and low Interrupt thresholds for a given mode (ranging, ALS, ...)
- * for a given device
- *
- * @note This function Access to the device
- *
- * @note DeviceMode is ignored for the current device
- *
- * @param dev Device Handle
- * @param device_mode Device Mode from which read thresholds
- * @param p_threshold_low Low threshold (mm, lux ..., depending on the mode)
- * @param p_threshold_high High threshold (mm, lux ..., depending on the mode)
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_interrupt_thresholds(VL53L0X_DEV dev,
- VL53L0X_DeviceModes device_mode, FixPoint1616_t *p_threshold_low,
- FixPoint1616_t *p_threshold_high);
-
- /**
- * @brief Reads the Device information for given Device
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_VL53L0X_device_info Pointer to current device info for a given
- * Device
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_device_info(VL53L0X_DEV dev,
- VL53L0X_DeviceInfo_t *p_VL53L0X_device_info);
-
- /**
- * @brief Gets the (on/off) state of all sequence steps.
- *
- * @par Function Description
- * This function retrieves the state of all sequence step in the scheduler.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param p_scheduler_sequence_steps Pointer to struct containing result.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_sequence_step_enables(VL53L0X_DEV dev,
- VL53L0X_SchedulerSequenceSteps_t *p_scheduler_sequence_steps);
-
- /**
- * @brief Sets the (on/off) state of a requested sequence step.
- *
- * @par Function Description
- * This function enables/disables a requested sequence step.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param sequence_step_id Sequence step identifier.
- * @param sequence_step_enabled Demanded state {0=Off,1=On}
- * is enabled.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
- * supported.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_sequence_step_enable(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_step_enabled);
-
- /**
- * @brief Gets the fraction enable parameter indicating the resolution of
- * range measurements.
- *
- * @par Function Description
- * Gets the fraction enable state, which translates to the resolution of
- * range measurements as follows :Enabled:=0.25mm resolution,
- * Not Enabled:=1mm resolution.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param p_enabled Output Parameter reporting the fraction enable state.
- *
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_fraction_enable(VL53L0X_DEV dev, uint8_t *p_enabled);
-
- /**
- * @brief Sets the resolution of range measurements.
- * @par Function Description
- * Set resolution of range measurements to either 0.25mm if
- * fraction enabled or 1mm if not enabled.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param enable Enable high resolution
- *
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_range_fraction_enable(VL53L0X_DEV dev,
- uint8_t enable);
-
- /**
- * @brief Return the VL53L0X PAL Implementation Version
- *
- * @note This function doesn't access to the device
- *
- * @param p_version Pointer to current PAL Implementation Version
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_version(VL53L0X_Version_t *p_version);
-
- /**
- * @brief Reads the Product Revision for a for given Device
- * This function can be used to distinguish cut1.0 from cut1.1.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_product_revision_major Pointer to Product Revision Major
- * for a given Device
- * @param p_product_revision_minor Pointer to Product Revision Minor
- * for a given Device
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_product_revision(VL53L0X_DEV dev,
- uint8_t *p_product_revision_major, uint8_t *p_product_revision_minor);
-
- /**
- * @brief Retrieve current device parameters
- * @par Function Description
- * Get actual parameters of the device
- * @li Then start ranging operation.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_device_parameters Pointer to store current device parameters.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_device_parameters(VL53L0X_DEV dev,
- VL53L0X_DeviceParameters_t *p_device_parameters);
-
- /**
- * @brief Human readable error string for current PAL error status
- *
- * @note This function doesn't access to the device
- *
- * @param pal_error_code The error code as stored on @a VL53L0X_Error
- * @param p_pal_error_string The error string corresponding to the
- * PalErrorCode
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_pal_error_string(VL53L0X_Error pal_error_code,
- char *p_pal_error_string);
-
- /**
- * @brief Return the PAL Specification Version used for the current
- * implementation.
- *
- * @note This function doesn't access to the device
- *
- * @param p_pal_spec_version Pointer to current PAL Specification Version
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_pal_spec_version(
- VL53L0X_Version_t *p_pal_spec_version);
-
- /**
- * @brief Reads the internal state of the PAL for a given Device
- *
- * @note This function doesn't access to the device
- *
- * @param dev Device Handle
- * @param p_pal_state Pointer to current state of the PAL for a
- * given Device
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_pal_state(VL53L0X_DEV dev,
- VL53L0X_State *p_pal_state);
-
- /**
- * @brief Human readable PAL State string
- *
- * @note This function doesn't access to the device
- *
- * @param pal_state_code The State code as stored on @a VL53L0X_State
- * @param p_pal_state_string The State string corresponding to the
- * PalStateCode
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_pal_state_string(VL53L0X_State pal_state_code,
- char *p_pal_state_string);
-
- /*** End High level API ***/
-
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_3rd.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,952 +0,0 @@
-
- /* api.h functions */
-
- /**
- * @brief Wait for device booted after chip enable (hardware standby)
- * This function can be run only when VL53L0X_State is VL53L0X_STATE_POWERDOWN.
- *
- * @note This function is not Implemented
- *
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- *
- */
- VL53L0X_Error VL53L0X_wait_device_booted(VL53L0X_DEV dev);
-
-
- VL53L0X_Error sequence_step_enabled(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_config,
- uint8_t *p_sequence_step_enabled);
-
- VL53L0X_Error VL53L0X_check_and_load_interrupt_settings(VL53L0X_DEV dev,
- uint8_t start_not_stopflag);
-
-
- /* api_core.h functions */
-
- VL53L0X_Error VL53L0X_get_info_from_device(VL53L0X_DEV dev, uint8_t option);
-
- VL53L0X_Error VL53L0X_device_read_strobe(VL53L0X_DEV dev);
-
- VL53L0X_Error wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t *p_measurement_timing_budget_micro_seconds);
-
- VL53L0X_Error wrapped_VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk);
-
- uint8_t VL53L0X_decode_vcsel_period(uint8_t vcsel_period_reg);
-
- uint32_t VL53L0X_decode_timeout(uint16_t encoded_timeout);
-
- uint32_t VL53L0X_calc_timeout_us(VL53L0X_DEV dev,
- uint16_t timeout_period_mclks,
- uint8_t vcsel_period_pclks);
-
- uint32_t VL53L0X_calc_macro_period_ps(VL53L0X_DEV dev, uint8_t vcsel_period_pclks);
-
- VL53L0X_Error VL53L0X_measurement_poll_for_completion(VL53L0X_DEV dev);
-
- VL53L0X_Error VL53L0X_load_tuning_settings(VL53L0X_DEV dev,
- uint8_t *p_tuning_setting_buffer);
-
- VL53L0X_Error VL53L0X_get_pal_range_status(VL53L0X_DEV dev,
- uint8_t device_range_status,
- FixPoint1616_t signal_rate,
- uint16_t effective_spad_rtn_count,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- uint8_t *p_pal_range_status);
- VL53L0X_Error VL53L0X_calc_sigma_estimate(VL53L0X_DEV dev,
- VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
- FixPoint1616_t *p_sigma_estimate,
- uint32_t *p_dmax_mm);
- uint32_t VL53L0X_calc_timeout_mclks(VL53L0X_DEV dev,
- uint32_t timeout_period_us,
- uint8_t vcsel_period_pclks);
- uint32_t VL53L0X_isqrt(uint32_t num);
-
- uint32_t VL53L0X_quadrature_sum(uint32_t a, uint32_t b);
-
- VL53L0X_Error VL53L0X_calc_dmax(
- VL53L0X_DEV dev,
- FixPoint1616_t total_signal_rate_mcps,
- FixPoint1616_t total_corr_signal_rate_mcps,
- FixPoint1616_t pw_mult,
- uint32_t sigma_estimate_p1,
- FixPoint1616_t sigma_estimate_p2,
- uint32_t peak_vcsel_duration_us,
- uint32_t *pd_max_mm);
- VL53L0X_Error wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
- uint32_t measurement_timing_budget_micro_seconds);
- VL53L0X_Error get_sequence_step_timeout(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id,
- uint32_t *p_time_out_micro_secs);
- VL53L0X_Error set_sequence_step_timeout(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id,
- uint32_t timeout_micro_secs);
- uint16_t VL53L0X_encode_timeout(uint32_t timeout_macro_clks);
- VL53L0X_Error wrapped_VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
- VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period_pclk);
- uint8_t lv53l0x_encode_vcsel_period(uint8_t vcsel_period_pclks);
-
- /* api_calibration.h functions */
- VL53L0X_Error VL53L0X_apply_offset_adjustment(VL53L0X_DEV dev);
- VL53L0X_Error wrapped_VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t *p_offset_calibration_data_micro_meter);
- VL53L0X_Error wrapped_VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
- int32_t offset_calibration_data_micro_meter);
- VL53L0X_Error wrapped_VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
- uint32_t *ref_spad_count,
- uint8_t *is_aperture_spads);
- VL53L0X_Error VL53L0X_perform_ref_calibration(VL53L0X_DEV dev,
- uint8_t *p_vhv_settings, uint8_t *p_phase_cal, uint8_t get_data_enable);
- VL53L0X_Error VL53L0X_perform_vhv_calibration(VL53L0X_DEV dev,
- uint8_t *p_vhv_settings, const uint8_t get_data_enable,
- const uint8_t restore_config);
- VL53L0X_Error VL53L0X_perform_single_ref_calibration(VL53L0X_DEV dev,
- uint8_t vhv_init_byte);
- VL53L0X_Error VL53L0X_ref_calibration_io(VL53L0X_DEV dev, uint8_t read_not_write,
- uint8_t vhv_settings, uint8_t phase_cal,
- uint8_t *p_vhv_settings, uint8_t *p_phase_cal,
- const uint8_t vhv_enable, const uint8_t phase_enable);
- VL53L0X_Error VL53L0X_perform_phase_calibration(VL53L0X_DEV dev,
- uint8_t *p_phase_cal, const uint8_t get_data_enable,
- const uint8_t restore_config);
- VL53L0X_Error enable_ref_spads(VL53L0X_DEV dev,
- uint8_t aperture_spads,
- uint8_t good_spad_array[],
- uint8_t spad_array[],
- uint32_t size,
- uint32_t start,
- uint32_t offset,
- uint32_t spad_count,
- uint32_t *p_last_spad);
- void get_next_good_spad(uint8_t good_spad_array[], uint32_t size,
- uint32_t curr, int32_t *p_next);
- uint8_t is_aperture(uint32_t spad_index);
- VL53L0X_Error enable_spad_bit(uint8_t spad_array[], uint32_t size,
- uint32_t spad_index);
- VL53L0X_Error set_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array);
- VL53L0X_Error get_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array);
- VL53L0X_Error perform_ref_signal_measurement(VL53L0X_DEV dev,
- uint16_t *p_ref_signal_rate);
- VL53L0X_Error wrapped_VL53L0X_set_reference_spads(VL53L0X_DEV dev,
- uint32_t count, uint8_t is_aperture_spads);
-
- /* api_strings.h functions */
- VL53L0X_Error wrapped_VL53L0X_get_device_info(VL53L0X_DEV dev,
- VL53L0X_DeviceInfo_t *p_VL53L0X_device_info);
- VL53L0X_Error VL53L0X_check_part_used(VL53L0X_DEV dev,
- uint8_t *revision,
- VL53L0X_DeviceInfo_t *p_VL53L0X_device_info);
-
- /* Read function of the ID device */
- // virtual int read_id();
- virtual int read_id(uint8_t *id);
-
- VL53L0X_Error wait_measurement_data_ready(VL53L0X_DEV dev);
-
- VL53L0X_Error wait_stop_completed(VL53L0X_DEV dev);
-
- /* Write and read functions from I2C */
- /**
- * Write single byte register
- * @param dev Device Handle
- * @param index The register index
- * @param data 8 bit register data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_write_byte(VL53L0X_DEV dev, uint8_t index, uint8_t data);
- /**
- * Write word register
- * @param dev Device Handle
- * @param index The register index
- * @param data 16 bit register data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_write_word(VL53L0X_DEV dev, uint8_t index, uint16_t data);
- /**
- * Write double word (4 byte) register
- * @param dev Device Handle
- * @param index The register index
- * @param data 32 bit register data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_write_dword(VL53L0X_DEV dev, uint8_t index, uint32_t data);
- /**
- * Read single byte register
- * @param dev Device Handle
- * @param index The register index
- * @param data pointer to 8 bit data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_read_byte(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data);
- /**
- * Read word (2byte) register
- * @param dev Device Handle
- * @param index The register index
- * @param data pointer to 16 bit data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_read_word(VL53L0X_DEV dev, uint8_t index, uint16_t *p_data);
- /**
- * Read dword (4byte) register
- * @param dev Device Handle
- * @param index The register index
- * @param data pointer to 32 bit data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_read_dword(VL53L0X_DEV dev, uint8_t index, uint32_t *p_data);
- /**
- * Threat safe Update (read/modify/write) single byte register
- *
- * Final_reg = (Initial_reg & and_data) |or_data
- *
- * @param dev Device Handle
- * @param index The register index
- * @param and_data 8 bit and data
- * @param or_data 8 bit or data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_update_byte(VL53L0X_DEV dev, uint8_t index, uint8_t and_data, uint8_t or_data);
- /**
- * Writes the supplied byte buffer to the device
- * @param dev Device Handle
- * @param index The register index
- * @param p_data Pointer to uint8_t buffer containing the data to be written
- * @param count Number of bytes in the supplied byte buffer
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_write_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count);
- /**
- * Reads the requested number of bytes from the device
- * @param dev Device Handle
- * @param index The register index
- * @param p_data Pointer to the uint8_t buffer to store read data
- * @param count Number of uint8_t's to read
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_read_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count);
-
- /**
- * @brief Writes a buffer towards the I2C peripheral device.
- * @param dev Device Handle
- * @param p_data pointer to the byte-array data to send
- * @param number_of_bytes number of bytes to be written.
- * @retval 0 if ok,
- * @retval -1 if an I2C error has occured
- * @note On some devices if NumByteToWrite is greater
- * than one, the RegisterAddr must be masked correctly!
- */
- VL53L0X_Error VL53L0X_i2c_write(uint8_t dev, uint8_t index, uint8_t *p_data, uint16_t number_of_bytes);
-
- /**
- * @brief Reads a buffer from the I2C peripheral device.
- * @param dev Device Handle
- * @param p_data pointer to the byte-array to read data in to
- * @param number_of_bytes number of bytes to be read.
- * @retval 0 if ok,
- * @retval -1 if an I2C error has occured
- * @note On some devices if NumByteToWrite is greater
- * than one, the RegisterAddr must be masked correctly!
- */
- VL53L0X_Error VL53L0X_i2c_read(uint8_t dev, uint8_t index, uint8_t *p_data, uint16_t number_of_bytes);
-
- /**
- * @brief execute delay in all polling API call
- *
- * A typical multi-thread or RTOs implementation is to sleep the task for some 5ms (with 100Hz max rate faster polling is not needed)
- * if nothing specific is need you can define it as an empty/void macro
- * @code
- * #define VL53L0X_PollingDelay(...) (void)0
- * @endcode
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_polling_delay(VL53L0X_DEV dev); /* usually best implemented as a real function */
-
- int is_present()
- {
- int status;
- uint8_t id = 0;
-
- status = read_id(&id);
- if (status) {
- VL53L0X_ErrLog("Failed to read ID device. Device not present!\n\r");
- }
- return status;
- }
-
- ///////////////////////////////////////////////////////////////////////////////////////////////////////
- //Added functions //
- ///////////////////////////////////////////////////////////////////////////////////////////////////////
-
- /**
- * @brief Cycle Power to Device
- *
- * @return status - status 0 = ok, 1 = error
- *
- */
- int32_t VL53L0X_cycle_power(void);
-
- uint8_t VL53L0X_encode_vcsel_period(uint8_t vcsel_period_pclks);
-
- VL53L0X_Error wrapped_VL53L0X_get_device_error_string(VL53L0X_DeviceError error_code,
- char *p_device_error_string);
-
- VL53L0X_Error wrapped_VL53L0X_get_limit_check_info(VL53L0X_DEV dev, uint16_t limit_check_id,
- char *p_limit_check_string);
-
- VL53L0X_Error wrapped_VL53L0X_get_pal_error_string(VL53L0X_Error pal_error_code,
- char *p_pal_error_string);
-
- VL53L0X_Error wrapped_VL53L0X_get_pal_state_string(VL53L0X_State pal_state_code,
- char *p_pal_state_string);
-
- VL53L0X_Error wrapped_VL53L0X_get_range_status_string(uint8_t range_status,
- char *p_range_status_string);
-
- VL53L0X_Error wrapped_VL53L0X_get_ref_calibration(VL53L0X_DEV dev,
- uint8_t *p_vhv_settings, uint8_t *p_phase_cal);
-
-
- VL53L0X_Error count_enabled_spads(uint8_t spad_array[],
- uint32_t byte_count, uint32_t max_spads,
- uint32_t *p_total_spads_enabled, uint8_t *p_is_aperture);
-
- VL53L0X_Error wrapped_VL53L0X_get_sequence_steps_info(VL53L0X_SequenceStepId sequence_step_id,
- char *p_sequence_steps_string);
-
-
- /**
- * @brief Gets the name of a given sequence step.
- *
- * @par Function Description
- * This function retrieves the name of sequence steps corresponding to
- * SequenceStepId.
- *
- * @note This function doesn't Accesses the device
- *
- * @param sequence_step_id Sequence step identifier.
- * @param p_sequence_steps_string Pointer to Info string
- *
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_sequence_steps_info(VL53L0X_SequenceStepId sequence_step_id,
- char *p_sequence_steps_string);
-
- /**
- * @brief Get the frequency of the timer used for ranging results time stamps
- *
- * @param[out] p_timer_freq_hz : pointer for timer frequency
- *
- * @return status : 0 = ok, 1 = error
- *
- */
- int32_t VL53L0X_get_timer_frequency(int32_t *p_timer_freq_hz);
-
- /**
- * @brief Get the timer value in units of timer_freq_hz (see VL53L0X_get_timestamp_frequency())
- *
- * @param[out] p_timer_count : pointer for timer count value
- *
- * @return status : 0 = ok, 1 = error
- *
- */
- int32_t VL53L0X_get_timer_value(int32_t *p_timer_count);
-
- /**
- * @brief Configure ranging interrupt reported to system
- *
- * @note This function is not Implemented
- *
- * @param dev Device Handle
- * @param interrupt_mask Mask of interrupt to Enable/disable
- * (0:interrupt disabled or 1: interrupt enabled)
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- */
- VL53L0X_Error VL53L0X_enable_interrupt_mask(VL53L0X_DEV dev,
- uint32_t interrupt_mask);
-
- /**
- * @brief Get Dmax Calibration Parameters for a given device
- *
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_range_milli_meter Pointer to Calibration Distance
- * @param p_signal_rate_rtn_mega_cps Pointer to Signal rate return
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_dmax_cal_parameters(VL53L0X_DEV dev,
- uint16_t *p_range_milli_meter, FixPoint1616_t *p_signal_rate_rtn_mega_cps);
-
- /**
- * @brief Set Dmax Calibration Parameters for a given device
- * When one of the parameter is zero, this function will get parameter
- * from NVM.
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param range_milli_meter Calibration Distance
- * @param signal_rate_rtn_mega_cps Signal rate return read at CalDistance
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_dmax_cal_parameters(VL53L0X_DEV dev,
- uint16_t range_milli_meter, FixPoint1616_t signal_rate_rtn_mega_cps);
-
- /**
- * @brief Retrieve the measurements from device for a given setup
- *
- * @par Function Description
- * Get data from last successful Histogram measurement
- * @warning USER should take care about @a VL53L0X_GetNumberOfROIZones()
- * before get data.
- * PAL will fill a NumberOfROIZones times the corresponding data structure
- * used in the measurement function.
- *
- * @note This function is not Implemented
- *
- * @param dev Device Handle
- * @param p_histogram_measurement_data Pointer to the histogram data structure.
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- */
- VL53L0X_Error VL53L0X_get_histogram_measurement_data(VL53L0X_DEV dev,
- VL53L0X_HistogramMeasurementData_t *p_histogram_measurement_data);
-
- /**
- * @brief Get current new device mode
- * @par Function Description
- * Get current Histogram mode of a Device
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param p_histogram_mode Pointer to current Histogram Mode value
- * Valid values are:
- * VL53L0X_HISTOGRAMMODE_DISABLED
- * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
- * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
- * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
- * VL53L0X_HISTOGRAMMODE_BOTH
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_histogram_mode(VL53L0X_DEV dev,
- VL53L0X_HistogramModes *p_histogram_mode);
-
- /**
- * @brief Set a new Histogram mode
- * @par Function Description
- * Set device to a new Histogram mode
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param histogram_mode New device mode to apply
- * Valid values are:
- * VL53L0X_HISTOGRAMMODE_DISABLED
- * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
- * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
- * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
- * VL53L0X_HISTOGRAMMODE_BOTH
- *
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
- * HistogramMode is not in the supported list
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_histogram_mode(VL53L0X_DEV dev,
- VL53L0X_HistogramModes histogram_mode);
-
- /**
- * @brief Return a description string for a given limit check number
- *
- * @par Function Description
- * This function returns a description string for a given limit check number.
- * The limit check is identified with the LimitCheckId.
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param limit_check_id Limit Check ID
- (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
- * @param p_limit_check_string Pointer to the
- description string of the given check limit.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is
- returned when LimitCheckId value is out of range.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_limit_check_info(VL53L0X_DEV dev,
- uint16_t limit_check_id, char *p_limit_check_string);
-
- /**
- * @brief Get the linearity corrective gain
- *
- * @par Function Description
- * Should only be used after a successful call to @a VL53L0X_DataInit to backup
- * device NVM value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_linearity_corrective_gain Pointer to the linearity
- * corrective gain in x1000
- * if value is 1000 then no modification is applied.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_linearity_corrective_gain(VL53L0X_DEV dev,
- uint16_t *p_linearity_corrective_gain);
-
- /**
- * Set the linearity corrective gain
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param linearity_corrective_gain Linearity corrective
- * gain in x1000
- * if value is 1000 then no modification is applied.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_linearity_corrective_gain(VL53L0X_DEV dev,
- int16_t linearity_corrective_gain);
-
- /**
- * @brief Get the Maximum number of ROI Zones managed by the Device
- *
- * @par Function Description
- * Get Maximum number of ROI Zones managed by the Device.
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param p_max_number_of_roi_zones Pointer to the Maximum Number
- * of ROI Zones value.
- * @return VL53L0X_ERROR_NONE Success
- */
- VL53L0X_Error VL53L0X_get_max_number_of_roi_zones(VL53L0X_DEV dev,
- uint8_t *p_max_number_of_roi_zones);
-
- /**
- * @brief Retrieve the Reference Signal after a measurements
- *
- * @par Function Description
- * Get Reference Signal from last successful Ranging measurement
- * This function return a valid value after that you call the
- * @a VL53L0X_GetRangingMeasurementData().
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_measurement_ref_signal Pointer to the Ref Signal to fill up.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_measurement_ref_signal(VL53L0X_DEV dev,
- FixPoint1616_t *p_measurement_ref_signal);
-
- /**
- * @brief Get the number of the check limit managed by a given Device
- *
- * @par Function Description
- * This function give the number of the check limit managed by the Device
- *
- * @note This function doesn't Access to the device
- *
- * @param p_number_of_limit_check Pointer to the number of check limit.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_number_of_limit_check(
- uint16_t *p_number_of_limit_check);
-
- /**
- * @brief Get the number of ROI Zones managed by the Device
- *
- * @par Function Description
- * Get number of ROI Zones managed by the Device
- * USER should take care about @a VL53L0X_GetNumberOfROIZones()
- * before get data after a perform measurement.
- * PAL will fill a NumberOfROIZones times the corresponding data
- * structure used in the measurement function.
- *
- * @note This function doesn't Access to the device
- *
- * @param dev Device Handle
- * @param p_number_of_roi_zones Pointer to the Number of ROI Zones value.
- * @return VL53L0X_ERROR_NONE Success
- */
- VL53L0X_Error VL53L0X_get_number_of_roi_zones(VL53L0X_DEV dev,
- uint8_t *p_number_of_roi_zones);
-
- /**
- * @brief Set the number of ROI Zones to be used for a specific Device
- *
- * @par Function Description
- * Set the number of ROI Zones to be used for a specific Device.
- * The programmed value should be less than the max number of ROI Zones given
- * with @a VL53L0X_GetMaxNumberOfROIZones().
- * This version of API manage only one zone.
- *
- * @param dev Device Handle
- * @param number_of_roi_zones Number of ROI Zones to be used for a
- * specific Device.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned if
- * NumberOfROIZones != 1
- */
- VL53L0X_Error VL53L0X_set_number_of_roi_zones(VL53L0X_DEV dev,
- uint8_t number_of_roi_zones);
-
- /**
- * @brief Gets number of sequence steps managed by the API.
- *
- * @par Function Description
- * This function retrieves the number of sequence steps currently managed
- * by the API
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param p_number_of_sequence_steps Out parameter reporting the number of
- * sequence steps.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_number_of_sequence_steps(VL53L0X_DEV dev,
- uint8_t *p_number_of_sequence_steps);
- /**
- * @brief Get the power mode for a given Device
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_power_mode Pointer to the current value of the power
- * mode. see ::VL53L0X_PowerModes
- * Valid values are:
- * VL53L0X_POWERMODE_STANDBY_LEVEL1,
- * VL53L0X_POWERMODE_IDLE_LEVEL1
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_power_mode(VL53L0X_DEV dev,
- VL53L0X_PowerModes *p_power_mode);
-
- /**
- * @brief Set the power mode for a given Device
- * The power mode can be Standby or Idle. Different level of both Standby and
- * Idle can exists.
- * This function should not be used when device is in Ranging state.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param power_mode The value of the power mode to set.
- * see ::VL53L0X_PowerModes
- * Valid values are:
- * VL53L0X_POWERMODE_STANDBY_LEVEL1,
- * VL53L0X_POWERMODE_IDLE_LEVEL1
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when PowerMode
- * is not in the supported list
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_power_mode(VL53L0X_DEV dev,
- VL53L0X_PowerModes power_mode);
-
- /**
- * @brief Retrieves SPAD configuration
- *
- * @par Function Description
- * This function retrieves the current number of applied reference spads
- * and also their type : Aperture or Non-Aperture.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_spad_count Number ref Spad Count
- * @param p_is_aperture_spads Reports if spads are of type
- * aperture or non-aperture.
- * 1:=aperture, 0:=Non-Aperture
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the in the reference
- * spad configuration.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error wrapped_VL53L0X_get_reference_spads(VL53L0X_DEV dev,
- uint32_t *p_spad_count, uint8_t *p_is_aperture_spads);
-
- /**
- * @brief Gets the (on/off) state of a requested sequence step.
- *
- * @par Function Description
- * This function retrieves the state of a requested sequence step, i.e. on/off.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param sequence_step_id Sequence step identifier.
- * @param p_sequence_step_enabled Out parameter reporting if the sequence step
- * is enabled {0=Off,1=On}.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
- * supported.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_sequence_step_enable(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id, uint8_t *p_sequence_step_enabled);
-
-
- /**
- * @brief Gets the timeout of a requested sequence step.
- *
- * @par Function Description
- * This function retrieves the timeout of a requested sequence step.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param sequence_step_id Sequence step identifier.
- * @param p_time_out_milli_secs Timeout value.
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
- * supported.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_sequence_step_timeout(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id,
- FixPoint1616_t *p_time_out_milli_secs);
-
- /**
- * @brief Sets the timeout of a requested sequence step.
- *
- * @par Function Description
- * This function sets the timeout of a requested sequence step.
- *
- * @note This function Accesses the device
- *
- * @param dev Device Handle
- * @param sequence_step_id Sequence step identifier.
- * @param time_out_milli_secs Demanded timeout
- * @return VL53L0X_ERROR_NONE Success
- * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
- * supported.
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_sequence_step_timeout(VL53L0X_DEV dev,
- VL53L0X_SequenceStepId sequence_step_id, FixPoint1616_t time_out_milli_secs);
-
- /**
- * @brief Get the current SPAD Ambient Damper Factor value
- *
- * @par Function Description
- * This function get the SPAD Ambient Damper Factor value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_spad_ambient_damper_factor Pointer to programmed SPAD Ambient
- * Damper Factor value
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_spad_ambient_damper_factor(VL53L0X_DEV dev,
- uint16_t *p_spad_ambient_damper_factor);
- /**
- * @brief Set the SPAD Ambient Damper Factor value
- *
- * @par Function Description
- * This function set the SPAD Ambient Damper Factor value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param spad_ambient_damper_factor SPAD Ambient Damper Factor value
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_spad_ambient_damper_factor(VL53L0X_DEV dev,
- uint16_t spad_ambient_damper_factor);
-
- /**
- * @brief Get the current SPAD Ambient Damper Threshold value
- *
- * @par Function Description
- * This function get the SPAD Ambient Damper Threshold value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_spad_ambient_damper_threshold Pointer to programmed
- * SPAD Ambient Damper Threshold value
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_spad_ambient_damper_threshold(VL53L0X_DEV dev,
- uint16_t *p_spad_ambient_damper_threshold);
-
- /**
- * @brief Set the SPAD Ambient Damper Threshold value
- *
- * @par Function Description
- * This function set the SPAD Ambient Damper Threshold value
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param spad_ambient_damper_threshold SPAD Ambient Damper Threshold value
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_spad_ambient_damper_threshold(VL53L0X_DEV dev,
- uint16_t spad_ambient_damper_threshold);
-
- /**
- * @brief Get the maximal distance for actual setup
- * @par Function Description
- * Device must be initialized through @a VL53L0X_SetParameters() prior calling
- * this function.
- *
- * Any range value more than the value returned is to be considered as
- * "no target detected" or
- * "no target in detectable range"\n
- * @warning The maximal distance depends on the setup
- *
- * @note This function is not Implemented
- *
- * @param dev Device Handle
- * @param p_upper_limit_milli_meter The maximal range limit for actual setup
- * (in millimeter)
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- */
- VL53L0X_Error VL53L0X_get_upper_limit_milli_meter(VL53L0X_DEV dev,
- uint16_t *p_upper_limit_milli_meter);
-
- /**
- * @brief Get the tuning settings pointer and the internal external switch
- * value.
- *
- * This function is used to get the Tuning settings buffer pointer and the
- * value.
- * of the switch to select either external or internal tuning settings.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param pp_tuning_setting_buffer Pointer to tuning settings buffer.
- * @param p_use_internal_tuning_settings Pointer to store Use internal tuning
- * settings value.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_get_tuning_setting_buffer(VL53L0X_DEV dev,
- uint8_t **pp_tuning_setting_buffer, uint8_t *p_use_internal_tuning_settings);
-
- /**
- * @brief Set the tuning settings pointer
- *
- * This function is used to specify the Tuning settings buffer to be used
- * for a given device. The buffer contains all the necessary data to permit
- * the API to write tuning settings.
- * This function permit to force the usage of either external or internal
- * tuning settings.
- *
- * @note This function Access to the device
- *
- * @param dev Device Handle
- * @param p_tuning_setting_buffer Pointer to tuning settings buffer.
- * @param use_internal_tuning_settings Use internal tuning settings value.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_set_tuning_setting_buffer(VL53L0X_DEV dev,
- uint8_t *p_tuning_setting_buffer, uint8_t use_internal_tuning_settings);
-
- /**
- * @defgroup VL53L0X_registerAccess_group PAL Register Access Functions
- * @brief PAL Register Access Functions
- * @{
- */
-
- /**
- * Lock comms interface to serialize all commands to a shared I2C interface for a specific device
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_lock_sequence_access(VL53L0X_DEV dev);
-
- /**
- * Unlock comms interface to serialize all commands to a shared I2C interface for a specific device
- * @param dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error VL53L0X_unlock_sequence_access(VL53L0X_DEV dev);
-
- /**
- * @brief Prepare device for operation
- * @par Function Description
- * Update device with provided parameters
- * @li Then start ranging operation.
- *
- * @note This function Access to the device
- *
- * @param Dev Device Handle
- * @param pDeviceParameters Pointer to store current device parameters.
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
- VL53L0X_Error vl53L0x_set_device_parameters(VL53L0X_DEV Dev,
- const VL53L0X_DeviceParameters_t *pDeviceParameters);
-
- /**
- * Set Group parameter Hold state
- *
- * @par Function Description
- * Set or remove device internal group parameter hold
- *
- * @note This function is not Implemented
- *
- * @param dev Device Handle
- * @param group_param_hold Group parameter Hold state to be set (on/off)
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- */
- VL53L0X_Error VL53L0X_set_group_param_hold(VL53L0X_DEV dev,
- uint8_t group_param_hold);
-
-
- /**
- * @brief Wait for device ready for a new measurement command.
- * Blocking function.
- *
- * @note This function is not Implemented
- *
- * @param dev Device Handle
- * @param max_loop Max Number of polling loop (timeout).
- * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
- */
- VL53L0X_Error VL53L0X_wait_device_ready_for_new_measurement(VL53L0X_DEV dev,
- uint32_t max_loop);
-
- VL53L0X_Error VL53L0X_reverse_bytes(uint8_t *data, uint32_t size);
-
- int range_meas_int_continuous_mode(void (*fptr)(void));
-
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_def.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,640 +0,0 @@
-/*******************************************************************************
-Copyright © 2016, STMicroelectronics International N.V.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
-IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************/
-
-/**
- * @file VL53L0X_def.h
- *
- * @brief Type definitions for VL53L0X API.
- *
- */
-
-
-#ifndef _VL53L0X_DEF_H_
-#define _VL53L0X_DEF_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @defgroup VL53L0X_globaldefine_group VL53L0X Defines
- * @brief VL53L0X Defines
- * @{
- */
-
-
-/** PAL SPECIFICATION major version */
-#define VL53L0X10_SPECIFICATION_VER_MAJOR 1
-/** PAL SPECIFICATION minor version */
-#define VL53L0X10_SPECIFICATION_VER_MINOR 2
-/** PAL SPECIFICATION sub version */
-#define VL53L0X10_SPECIFICATION_VER_SUB 7
-/** PAL SPECIFICATION sub version */
-#define VL53L0X10_SPECIFICATION_VER_REVISION 1440
-
-/** VL53L0X PAL IMPLEMENTATION major version */
-#define VL53L0X10_IMPLEMENTATION_VER_MAJOR 1
-/** VL53L0X PAL IMPLEMENTATION minor version */
-#define VL53L0X10_IMPLEMENTATION_VER_MINOR 0
-/** VL53L0X PAL IMPLEMENTATION sub version */
-#define VL53L0X10_IMPLEMENTATION_VER_SUB 9
-/** VL53L0X PAL IMPLEMENTATION sub version */
-#define VL53L0X10_IMPLEMENTATION_VER_REVISION 3673
-
-/** PAL SPECIFICATION major version */
-#define VL53L0X_SPECIFICATION_VER_MAJOR 1
-/** PAL SPECIFICATION minor version */
-#define VL53L0X_SPECIFICATION_VER_MINOR 2
-/** PAL SPECIFICATION sub version */
-#define VL53L0X_SPECIFICATION_VER_SUB 7
-/** PAL SPECIFICATION sub version */
-#define VL53L0X_SPECIFICATION_VER_REVISION 1440
-
-/** VL53L0X PAL IMPLEMENTATION major version */
-#define VL53L0X_IMPLEMENTATION_VER_MAJOR 1
-/** VL53L0X PAL IMPLEMENTATION minor version */
-#define VL53L0X_IMPLEMENTATION_VER_MINOR 1
-/** VL53L0X PAL IMPLEMENTATION sub version */
-#define VL53L0X_IMPLEMENTATION_VER_SUB 21
-/** VL53L0X PAL IMPLEMENTATION sub version */
-#define VL53L0X_IMPLEMENTATION_VER_REVISION 4823
-#define VL53L0X_DEFAULT_MAX_LOOP 2000
-#define VL53L0X_MAX_STRING_LENGTH 32
-
-
-#include "VL53L0X_device.h"
-#include "VL53L0X_types.h"
-
-
-/****************************************
- * PRIVATE define do not edit
- ****************************************/
-
-/** @brief Defines the parameters of the Get Version Functions
- */
-typedef struct {
- uint32_t revision; /*!< revision number */
- uint8_t major; /*!< major number */
- uint8_t minor; /*!< minor number */
- uint8_t build; /*!< build number */
-} VL53L0X_Version_t;
-
-
-/** @brief Defines the parameters of the Get Device Info Functions
- */
-typedef struct {
- char Name[VL53L0X_MAX_STRING_LENGTH];
- /*!< Name of the Device e.g. Left_Distance */
- char Type[VL53L0X_MAX_STRING_LENGTH];
- /*!< Type of the Device e.g VL53L0X */
- char ProductId[VL53L0X_MAX_STRING_LENGTH];
- /*!< Product Identifier String */
- uint8_t ProductType;
- /*!< Product Type, VL53L0X = 1, VL53L1 = 2 */
- uint8_t ProductRevisionMajor;
- /*!< Product revision major */
- uint8_t ProductRevisionMinor;
- /*!< Product revision minor */
-} VL53L0X_DeviceInfo_t;
-
-
-/** @defgroup VL53L0X_define_Error_group Error and Warning code returned by API
- * The following DEFINE are used to identify the PAL ERROR
- * @{
- */
-
-typedef int8_t VL53L0X_Error;
-
-#define VL53L0X_ERROR_NONE ((VL53L0X_Error) 0)
-#define VL53L0X_ERROR_CALIBRATION_WARNING ((VL53L0X_Error) -1)
-/*!< Warning invalid calibration data may be in used
- \a VL53L0X_InitData()
- \a VL53L0X_GetOffsetCalibrationData
- \a VL53L0X_SetOffsetCalibrationData */
-#define VL53L0X_ERROR_MIN_CLIPPED ((VL53L0X_Error) -2)
-/*!< Warning parameter passed was clipped to min before to be applied */
-
-#define VL53L0X_ERROR_UNDEFINED ((VL53L0X_Error) -3)
-/*!< Unqualified error */
-#define VL53L0X_ERROR_INVALID_PARAMS ((VL53L0X_Error) -4)
-/*!< Parameter passed is invalid or out of range */
-#define VL53L0X_ERROR_NOT_SUPPORTED ((VL53L0X_Error) -5)
-/*!< Function is not supported in current mode or configuration */
-#define VL53L0X_ERROR_RANGE_ERROR ((VL53L0X_Error) -6)
-/*!< Device report a ranging error interrupt status */
-#define VL53L0X_ERROR_TIME_OUT ((VL53L0X_Error) -7)
-/*!< Aborted due to time out */
-#define VL53L0X_ERROR_MODE_NOT_SUPPORTED ((VL53L0X_Error) -8)
-/*!< Asked mode is not supported by the device */
-#define VL53L0X_ERROR_BUFFER_TOO_SMALL ((VL53L0X_Error) -9)
-/*!< ... */
-#define VL53L0X_ERROR_GPIO_NOT_EXISTING ((VL53L0X_Error) -10)
-/*!< User tried to setup a non-existing GPIO pin */
-#define VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED ((VL53L0X_Error) -11)
-/*!< unsupported GPIO functionality */
-#define VL53L0X_ERROR_INTERRUPT_NOT_CLEARED ((VL53L0X_Error) -12)
-/*!< Error during interrupt clear */
-#define VL53L0X_ERROR_CONTROL_INTERFACE ((VL53L0X_Error) -20)
-/*!< error reported from IO functions */
-#define VL53L0X_ERROR_INVALID_COMMAND ((VL53L0X_Error) -30)
-/*!< The command is not allowed in the current device state
- * (power down) */
-#define VL53L0X_ERROR_DIVISION_BY_ZERO ((VL53L0X_Error) -40)
-/*!< In the function a division by zero occurs */
-#define VL53L0X_ERROR_REF_SPAD_INIT ((VL53L0X_Error) -50)
-/*!< Error during reference SPAD initialization */
-#define VL53L0X_ERROR_NOT_IMPLEMENTED ((VL53L0X_Error) -99)
-/*!< Tells requested functionality has not been implemented yet or
- * not compatible with the device */
-/** @} VL53L0X_define_Error_group */
-
-
-/** @defgroup VL53L0X_define_DeviceModes_group Defines Device modes
- * Defines all possible modes for the device
- * @{
- */
-typedef uint8_t VL53L0X_DeviceModes;
-
-#define VL53L0X_DEVICEMODE_SINGLE_RANGING ((VL53L0X_DeviceModes) 0)
-#define VL53L0X_DEVICEMODE_CONTINUOUS_RANGING ((VL53L0X_DeviceModes) 1)
-#define VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM ((VL53L0X_DeviceModes) 2)
-#define VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING ((VL53L0X_DeviceModes) 3)
-#define VL53L0X_DEVICEMODE_SINGLE_ALS ((VL53L0X_DeviceModes) 10)
-#define VL53L0X_DEVICEMODE_GPIO_DRIVE ((VL53L0X_DeviceModes) 20)
-#define VL53L0X_DEVICEMODE_GPIO_OSC ((VL53L0X_DeviceModes) 21)
-/* ... Modes to be added depending on device */
-/** @} VL53L0X_define_DeviceModes_group */
-
-
-
-/** @defgroup VL53L0X_define_HistogramModes_group Defines Histogram modes
- * Defines all possible Histogram modes for the device
- * @{
- */
-typedef uint8_t VL53L0X_HistogramModes;
-
-#define VL53L0X_HISTOGRAMMODE_DISABLED ((VL53L0X_HistogramModes) 0)
-/*!< Histogram Disabled */
-#define VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY ((VL53L0X_HistogramModes) 1)
-/*!< Histogram Reference array only */
-#define VL53L0X_HISTOGRAMMODE_RETURN_ONLY ((VL53L0X_HistogramModes) 2)
-/*!< Histogram Return array only */
-#define VL53L0X_HISTOGRAMMODE_BOTH ((VL53L0X_HistogramModes) 3)
-/*!< Histogram both Reference and Return Arrays */
-/* ... Modes to be added depending on device */
-/** @} VL53L0X_define_HistogramModes_group */
-
-
-/** @defgroup VL53L0X_define_PowerModes_group List of available Power Modes
- * List of available Power Modes
- * @{
- */
-
-typedef uint8_t VL53L0X_PowerModes;
-
-#define VL53L0X_POWERMODE_STANDBY_LEVEL1 ((VL53L0X_PowerModes) 0)
-/*!< Standby level 1 */
-#define VL53L0X_POWERMODE_STANDBY_LEVEL2 ((VL53L0X_PowerModes) 1)
-/*!< Standby level 2 */
-#define VL53L0X_POWERMODE_IDLE_LEVEL1 ((VL53L0X_PowerModes) 2)
-/*!< Idle level 1 */
-#define VL53L0X_POWERMODE_IDLE_LEVEL2 ((VL53L0X_PowerModes) 3)
-/*!< Idle level 2 */
-
-/** @} VL53L0X_define_PowerModes_group */
-
-
-/** @brief Defines all parameters for the device
- */
-typedef struct {
- VL53L0X_DeviceModes DeviceMode;
- /*!< Defines type of measurement to be done for the next measure */
- VL53L0X_HistogramModes HistogramMode;
- /*!< Defines type of histogram measurement to be done for the next
- * measure */
- uint32_t MeasurementTimingBudgetMicroSeconds;
- /*!< Defines the allowed total time for a single measurement */
- uint32_t InterMeasurementPeriodMilliSeconds;
- /*!< Defines time between two consecutive measurements (between two
- * measurement starts). If set to 0 means back-to-back mode */
- uint8_t XTalkCompensationEnable;
- /*!< Tells if Crosstalk compensation shall be enable or not */
- uint16_t XTalkCompensationRangeMilliMeter;
- /*!< CrossTalk compensation range in millimeter */
- FixPoint1616_t XTalkCompensationRateMegaCps;
- /*!< CrossTalk compensation rate in Mega counts per seconds.
- * Expressed in 16.16 fixed point format. */
- int32_t RangeOffsetMicroMeters;
- /*!< Range offset adjustment (mm). */
-
- uint8_t LimitChecksEnable[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
- /*!< This Array store all the Limit Check enable for this device. */
- uint8_t LimitChecksStatus[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
- /*!< This Array store all the Status of the check linked to last
- * measurement. */
- FixPoint1616_t LimitChecksValue[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
- /*!< This Array store all the Limit Check value for this device */
-
- uint8_t WrapAroundCheckEnable;
- /*!< Tells if Wrap Around Check shall be enable or not */
-} VL53L0X_DeviceParameters_t;
-
-
-/** @defgroup VL53L0X_define_State_group Defines the current status of the device
- * Defines the current status of the device
- * @{
- */
-
-typedef uint8_t VL53L0X_State;
-
-#define VL53L0X_STATE_POWERDOWN ((VL53L0X_State) 0)
-/*!< Device is in HW reset */
-#define VL53L0X_STATE_WAIT_STATICINIT ((VL53L0X_State) 1)
-/*!< Device is initialized and wait for static initialization */
-#define VL53L0X_STATE_STANDBY ((VL53L0X_State) 2)
-/*!< Device is in Low power Standby mode */
-#define VL53L0X_STATE_IDLE ((VL53L0X_State) 3)
-/*!< Device has been initialized and ready to do measurements */
-#define VL53L0X_STATE_RUNNING ((VL53L0X_State) 4)
-/*!< Device is performing measurement */
-#define VL53L0X_STATE_UNKNOWN ((VL53L0X_State) 98)
-/*!< Device is in unknown state and need to be rebooted */
-#define VL53L0X_STATE_ERROR ((VL53L0X_State) 99)
-/*!< Device is in error state and need to be rebooted */
-
-/** @} VL53L0X_define_State_group */
-
-
-/** @brief Structure containing the Dmax computation parameters and data
- */
-typedef struct {
- int32_t AmbTuningWindowFactor_K;
- /*!< internal algo tuning (*1000) */
- int32_t RetSignalAt0mm;
- /*!< intermediate dmax computation value caching */
-} VL53L0X_DMaxData_t;
-
-/**
- * @struct VL53L0X_RangeData_t
- * @brief Range measurement data.
- */
-typedef struct {
- uint32_t TimeStamp; /*!< 32-bit time stamp. */
- uint32_t MeasurementTimeUsec;
- /*!< Give the Measurement time needed by the device to do the
- * measurement.*/
-
-
- uint16_t RangeMilliMeter; /*!< range distance in millimeter. */
-
- uint16_t RangeDMaxMilliMeter;
- /*!< Tells what is the maximum detection distance of the device
- * in current setup and environment conditions (Filled when
- * applicable) */
-
- FixPoint1616_t SignalRateRtnMegaCps;
- /*!< Return signal rate (MCPS)\n these is a 16.16 fix point
- * value, which is effectively a measure of target
- * reflectance.*/
- FixPoint1616_t AmbientRateRtnMegaCps;
- /*!< Return ambient rate (MCPS)\n these is a 16.16 fix point
- * value, which is effectively a measure of the ambien
- * t light.*/
-
- uint16_t EffectiveSpadRtnCount;
- /*!< Return the effective SPAD count for the return signal.
- * To obtain Real value it should be divided by 256 */
-
- uint8_t ZoneId;
- /*!< Denotes which zone and range scheduler stage the range
- * data relates to. */
- uint8_t RangeFractionalPart;
- /*!< Fractional part of range distance. Final value is a
- * FixPoint168 value. */
- uint8_t RangeStatus;
- /*!< Range Status for the current measurement. This is device
- * dependent. Value = 0 means value is valid.
- * See \ref RangeStatusPage */
-} VL53L0X_RangingMeasurementData_t;
-
-
-#define VL53L0X_HISTOGRAM_BUFFER_SIZE 24
-
-/**
- * @struct VL53L0X_HistogramData_t
- * @brief Histogram measurement data.
- */
-typedef struct {
- /* Histogram Measurement data */
- uint32_t HistogramData[VL53L0X_HISTOGRAM_BUFFER_SIZE];
- /*!< Histogram data */
- uint8_t HistogramType; /*!< Indicate the types of histogram data :
- Return only, Reference only, both Return and Reference */
- uint8_t FirstBin; /*!< First Bin value */
- uint8_t BufferSize; /*!< Buffer Size - Set by the user.*/
- uint8_t NumberOfBins;
- /*!< Number of bins filled by the histogram measurement */
-
- VL53L0X_DeviceError ErrorStatus;
- /*!< Error status of the current measurement. \n
- see @a ::VL53L0X_DeviceError @a VL53L0X_GetStatusErrorString() */
-} VL53L0X_HistogramMeasurementData_t;
-
-#define VL53L0X_REF_SPAD_BUFFER_SIZE 6
-
-/**
- * @struct VL53L0X_SpadData_t
- * @brief Spad Configuration Data.
- */
-typedef struct {
- uint8_t RefSpadEnables[VL53L0X_REF_SPAD_BUFFER_SIZE];
- /*!< Reference Spad Enables */
- uint8_t RefGoodSpadMap[VL53L0X_REF_SPAD_BUFFER_SIZE];
- /*!< Reference Spad Good Spad Map */
-} VL53L0X_SpadData_t;
-
-typedef struct {
- FixPoint1616_t OscFrequencyMHz; /* Frequency used */
-
- uint16_t LastEncodedTimeout;
- /* last encoded Time out used for timing budget*/
-
- VL53L0X_GpioFunctionality Pin0GpioFunctionality;
- /* store the functionality of the GPIO: pin0 */
-
- uint32_t FinalRangeTimeoutMicroSecs;
- /*!< Execution time of the final range*/
- uint8_t FinalRangeVcselPulsePeriod;
- /*!< Vcsel pulse period (pll clocks) for the final range measurement*/
- uint32_t PreRangeTimeoutMicroSecs;
- /*!< Execution time of the final range*/
- uint8_t PreRangeVcselPulsePeriod;
- /*!< Vcsel pulse period (pll clocks) for the pre-range measurement*/
-
- uint16_t SigmaEstRefArray;
- /*!< Reference array sigma value in 1/100th of [mm] e.g. 100 = 1mm */
- uint16_t SigmaEstEffPulseWidth;
- /*!< Effective Pulse width for sigma estimate in 1/100th
- * of ns e.g. 900 = 9.0ns */
- uint16_t SigmaEstEffAmbWidth;
- /*!< Effective Ambient width for sigma estimate in 1/100th of ns
- * e.g. 500 = 5.0ns */
-
-
- uint8_t ReadDataFromDeviceDone; /* Indicate if read from device has
- been done (==1) or not (==0) */
- uint8_t ModuleId; /* Module ID */
- uint8_t Revision; /* test Revision */
- char ProductId[VL53L0X_MAX_STRING_LENGTH];
- /* Product Identifier String */
- uint8_t ReferenceSpadCount; /* used for ref spad management */
- uint8_t ReferenceSpadType; /* used for ref spad management */
- uint8_t RefSpadsInitialised; /* reports if ref spads are initialised. */
- uint32_t PartUIDUpper; /*!< Unique Part ID Upper */
- uint32_t PartUIDLower; /*!< Unique Part ID Lower */
- FixPoint1616_t SignalRateMeasFixed400mm; /*!< Peek Signal rate
- at 400 mm*/
-
-} VL53L0X_DeviceSpecificParameters_t;
-
-/**
- * @struct VL53L0X_DevData_t
- *
- * @brief VL53L0X PAL device ST private data structure \n
- * End user should never access any of these field directly
- *
- * These must never access directly but only via macro
- */
-typedef struct {
- VL53L0X_DMaxData_t DMaxData;
- /*!< Dmax Data */
- int32_t Part2PartOffsetNVMMicroMeter;
- /*!< backed up NVM value */
- int32_t Part2PartOffsetAdjustmentNVMMicroMeter;
- /*!< backed up NVM value representing additional offset adjustment */
- VL53L0X_DeviceParameters_t CurrentParameters;
- /*!< Current Device Parameter */
- VL53L0X_RangingMeasurementData_t LastRangeMeasure;
- /*!< Ranging Data */
- VL53L0X_HistogramMeasurementData_t LastHistogramMeasure;
- /*!< Histogram Data */
- VL53L0X_DeviceSpecificParameters_t DeviceSpecificParameters;
- /*!< Parameters specific to the device */
- VL53L0X_SpadData_t SpadData;
- /*!< Spad Data */
- uint8_t SequenceConfig;
- /*!< Internal value for the sequence config */
- uint8_t RangeFractionalEnable;
- /*!< Enable/Disable fractional part of ranging data */
- VL53L0X_State PalState;
- /*!< Current state of the PAL for this device */
- VL53L0X_PowerModes PowerMode;
- /*!< Current Power Mode */
- uint16_t SigmaEstRefArray;
- /*!< Reference array sigma value in 1/100th of [mm] e.g. 100 = 1mm */
- uint16_t SigmaEstEffPulseWidth;
- /*!< Effective Pulse width for sigma estimate in 1/100th
- * of ns e.g. 900 = 9.0ns */
- uint16_t SigmaEstEffAmbWidth;
- /*!< Effective Ambient width for sigma estimate in 1/100th of ns
- * e.g. 500 = 5.0ns */
- uint8_t StopVariable;
- /*!< StopVariable used during the stop sequence */
- uint16_t targetRefRate;
- /*!< Target Ambient Rate for Ref spad management */
- FixPoint1616_t SigmaEstimate;
- /*!< Sigma Estimate - based on ambient & VCSEL rates and
- * signal_total_events */
- FixPoint1616_t SignalEstimate;
- /*!< Signal Estimate - based on ambient & VCSEL rates and cross talk */
- FixPoint1616_t LastSignalRefMcps;
- /*!< Latest Signal ref in Mcps */
- uint8_t *pTuningSettingsPointer;
- /*!< Pointer for Tuning Settings table */
- uint8_t UseInternalTuningSettings;
- /*!< Indicate if we use Tuning Settings table */
- uint16_t LinearityCorrectiveGain;
- /*!< Linearity Corrective Gain value in x1000 */
- uint16_t DmaxCalRangeMilliMeter;
- /*!< Dmax Calibration Range millimeter */
- FixPoint1616_t DmaxCalSignalRateRtnMegaCps;
- /*!< Dmax Calibration Signal Rate Return MegaCps */
-
-} VL53L0X_DevData_t;
-
-
-/** @defgroup VL53L0X_define_InterruptPolarity_group Defines the Polarity
- * of the Interrupt
- * Defines the Polarity of the Interrupt
- * @{
- */
-typedef uint8_t VL53L0X_InterruptPolarity;
-
-#define VL53L0X_INTERRUPTPOLARITY_LOW ((VL53L0X_InterruptPolarity) 0)
-/*!< Set active low polarity best setup for falling edge. */
-#define VL53L0X_INTERRUPTPOLARITY_HIGH ((VL53L0X_InterruptPolarity) 1)
-/*!< Set active high polarity best setup for rising edge. */
-
-/** @} VL53L0X_define_InterruptPolarity_group */
-
-
-/** @defgroup VL53L0X_define_VcselPeriod_group Vcsel Period Defines
- * Defines the range measurement for which to access the vcsel period.
- * @{
- */
-typedef uint8_t VL53L0X_VcselPeriod;
-
-#define VL53L0X_VCSEL_PERIOD_PRE_RANGE ((VL53L0X_VcselPeriod) 0)
-/*!<Identifies the pre-range vcsel period. */
-#define VL53L0X_VCSEL_PERIOD_FINAL_RANGE ((VL53L0X_VcselPeriod) 1)
-/*!<Identifies the final range vcsel period. */
-
-/** @} VL53L0X_define_VcselPeriod_group */
-
-/** @defgroup VL53L0X_define_SchedulerSequence_group Defines the steps
- * carried out by the scheduler during a range measurement.
- * @{
- * Defines the states of all the steps in the scheduler
- * i.e. enabled/disabled.
- */
-typedef struct {
- uint8_t TccOn; /*!<Reports if Target Centre Check On */
- uint8_t MsrcOn; /*!<Reports if MSRC On */
- uint8_t DssOn; /*!<Reports if DSS On */
- uint8_t PreRangeOn; /*!<Reports if Pre-Range On */
- uint8_t FinalRangeOn; /*!<Reports if Final-Range On */
-} VL53L0X_SchedulerSequenceSteps_t;
-
-/** @} VL53L0X_define_SchedulerSequence_group */
-
-/** @defgroup VL53L0X_define_SequenceStepId_group Defines the Polarity
- * of the Interrupt
- * Defines the the sequence steps performed during ranging..
- * @{
- */
-typedef uint8_t VL53L0X_SequenceStepId;
-
-#define VL53L0X_SEQUENCESTEP_TCC ((VL53L0X_VcselPeriod) 0)
-/*!<Target CentreCheck identifier. */
-#define VL53L0X_SEQUENCESTEP_DSS ((VL53L0X_VcselPeriod) 1)
-/*!<Dynamic Spad Selection function Identifier. */
-#define VL53L0X_SEQUENCESTEP_MSRC ((VL53L0X_VcselPeriod) 2)
-/*!<Minimum Signal Rate Check function Identifier. */
-#define VL53L0X_SEQUENCESTEP_PRE_RANGE ((VL53L0X_VcselPeriod) 3)
-/*!<Pre-Range check Identifier. */
-#define VL53L0X_SEQUENCESTEP_FINAL_RANGE ((VL53L0X_VcselPeriod) 4)
-/*!<Final Range Check Identifier. */
-
-#define VL53L0X_SEQUENCESTEP_NUMBER_OF_CHECKS 5
-/*!<Number of Sequence Step Managed by the API. */
-
-/** @} VL53L0X_define_SequenceStepId_group */
-
-
-/* MACRO Definitions */
-/** @defgroup VL53L0X_define_GeneralMacro_group General Macro Defines
- * General Macro Defines
- * @{
- */
-
-/* Defines */
-#define VL53L0X_SETPARAMETERFIELD(Dev, field, value) \
- PALDevDataSet(Dev, CurrentParameters.field, value)
-
-#define VL53L0X_GETPARAMETERFIELD(Dev, field, variable) \
- variable = PALDevDataGet(Dev, CurrentParameters).field
-
-
-#define VL53L0X_SETARRAYPARAMETERFIELD(Dev, field, index, value) \
- PALDevDataSet(Dev, CurrentParameters.field[index], value)
-
-#define VL53L0X_GETARRAYPARAMETERFIELD(Dev, field, index, variable) \
- variable = PALDevDataGet(Dev, CurrentParameters).field[index]
-
-
-#define VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, field, value) \
- PALDevDataSet(Dev, DeviceSpecificParameters.field, value)
-
-#define VL53L0X_GETDEVICESPECIFICPARAMETER(Dev, field) \
- PALDevDataGet(Dev, DeviceSpecificParameters).field
-
-
-#define VL53L0X_FIXPOINT1616TOFIXPOINT97(Value) \
- (uint16_t)((Value>>9)&0xFFFF)
-#define VL53L0X_FIXPOINT97TOFIXPOINT1616(Value) \
- (FixPoint1616_t)(Value<<9)
-
-#define VL53L0X_FIXPOINT1616TOFIXPOINT88(Value) \
- (uint16_t)((Value>>8)&0xFFFF)
-#define VL53L0X_FIXPOINT88TOFIXPOINT1616(Value) \
- (FixPoint1616_t)(Value<<8)
-
-#define VL53L0X_FIXPOINT1616TOFIXPOINT412(Value) \
- (uint16_t)((Value>>4)&0xFFFF)
-#define VL53L0X_FIXPOINT412TOFIXPOINT1616(Value) \
- (FixPoint1616_t)(Value<<4)
-
-#define VL53L0X_FIXPOINT1616TOFIXPOINT313(Value) \
- (uint16_t)((Value>>3)&0xFFFF)
-#define VL53L0X_FIXPOINT313TOFIXPOINT1616(Value) \
- (FixPoint1616_t)(Value<<3)
-
-#define VL53L0X_FIXPOINT1616TOFIXPOINT08(Value) \
- (uint8_t)((Value>>8)&0x00FF)
-#define VL53L0X_FIXPOINT08TOFIXPOINT1616(Value) \
- (FixPoint1616_t)(Value<<8)
-
-#define VL53L0X_FIXPOINT1616TOFIXPOINT53(Value) \
- (uint8_t)((Value>>13)&0x00FF)
-#define VL53L0X_FIXPOINT53TOFIXPOINT1616(Value) \
- (FixPoint1616_t)(Value<<13)
-
-#define VL53L0X_FIXPOINT1616TOFIXPOINT102(Value) \
- (uint16_t)((Value>>14)&0x0FFF)
-#define VL53L0X_FIXPOINT102TOFIXPOINT1616(Value) \
- (FixPoint1616_t)(Value<<12)
-
-#define VL53L0X_MAKEUINT16(lsb, msb) (uint16_t)((((uint16_t)msb)<<8) + \
- (uint16_t)lsb)
-
-/** @} VL53L0X_define_GeneralMacro_group */
-
-/** @} VL53L0X_globaldefine_group */
-
-
-
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* _VL53L0X_DEF_H_ */
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_device.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,257 +0,0 @@
-/*******************************************************************************
-Copyright © 2016, STMicroelectronics International N.V.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
-IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************/
-
-/**
- * Device specific defines. To be adapted by implementer for the targeted
- * device.
- */
-
-#ifndef _VL53L0X_DEVICE_H_
-#define _VL53L0X_DEVICE_H_
-
-#include "VL53L0X_types.h"
-
-
-/** @defgroup VL53L0X_DevSpecDefines_group VL53L0X cut1.1 Device Specific Defines
- * @brief VL53L0X cut1.1 Device Specific Defines
- * @{
- */
-
-
-/** @defgroup VL53L0X_DeviceError_group Device Error
- * @brief Device Error code
- *
- * This enum is Device specific it should be updated in the implementation
- * Use @a VL53L0X_GetStatusErrorString() to get the string.
- * It is related to Status Register of the Device.
- * @{
- */
-typedef uint8_t VL53L0X_DeviceError;
-
-#define VL53L0X_DEVICEERROR_NONE ((VL53L0X_DeviceError) 0)
-/*!< 0 NoError */
-#define VL53L0X_DEVICEERROR_VCSELCONTINUITYTESTFAILURE ((VL53L0X_DeviceError) 1)
-#define VL53L0X_DEVICEERROR_VCSELWATCHDOGTESTFAILURE ((VL53L0X_DeviceError) 2)
-#define VL53L0X_DEVICEERROR_NOVHVVALUEFOUND ((VL53L0X_DeviceError) 3)
-#define VL53L0X_DEVICEERROR_MSRCNOTARGET ((VL53L0X_DeviceError) 4)
-#define VL53L0X_DEVICEERROR_SNRCHECK ((VL53L0X_DeviceError) 5)
-#define VL53L0X_DEVICEERROR_RANGEPHASECHECK ((VL53L0X_DeviceError) 6)
-#define VL53L0X_DEVICEERROR_SIGMATHRESHOLDCHECK ((VL53L0X_DeviceError) 7)
-#define VL53L0X_DEVICEERROR_TCC ((VL53L0X_DeviceError) 8)
-#define VL53L0X_DEVICEERROR_PHASECONSISTENCY ((VL53L0X_DeviceError) 9)
-#define VL53L0X_DEVICEERROR_MINCLIP ((VL53L0X_DeviceError) 10)
-#define VL53L0X_DEVICEERROR_RANGECOMPLETE ((VL53L0X_DeviceError) 11)
-#define VL53L0X_DEVICEERROR_ALGOUNDERFLOW ((VL53L0X_DeviceError) 12)
-#define VL53L0X_DEVICEERROR_ALGOOVERFLOW ((VL53L0X_DeviceError) 13)
-#define VL53L0X_DEVICEERROR_RANGEIGNORETHRESHOLD ((VL53L0X_DeviceError) 14)
-
-/** @} end of VL53L0X_DeviceError_group */
-
-
-/** @defgroup VL53L0X_CheckEnable_group Check Enable list
- * @brief Check Enable code
- *
- * Define used to specify the LimitCheckId.
- * Use @a VL53L0X_GetLimitCheckInfo() to get the string.
- * @{
- */
-
-#define VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE 0
-#define VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE 1
-#define VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP 2
-#define VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD 3
-#define VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC 4
-#define VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE 5
-
-#define VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS 6
-
-/** @} end of VL53L0X_CheckEnable_group */
-
-
-/** @defgroup VL53L0X_GpioFunctionality_group Gpio Functionality
- * @brief Defines the different functionalities for the device GPIO(s)
- * @{
- */
-typedef uint8_t VL53L0X_GpioFunctionality;
-
-#define VL53L0X_GPIOFUNCTIONALITY_OFF \
- ((VL53L0X_GpioFunctionality) 0) /*!< NO Interrupt */
-#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW \
- ((VL53L0X_GpioFunctionality) 1) /*!< Level Low (value < thresh_low) */
-#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH \
- ((VL53L0X_GpioFunctionality) 2) /*!< Level High (value > thresh_high) */
-#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT \
- ((VL53L0X_GpioFunctionality) 3)
-/*!< Out Of Window (value < thresh_low OR value > thresh_high) */
-#define VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY \
- ((VL53L0X_GpioFunctionality) 4) /*!< New Sample Ready */
-
-/** @} end of VL53L0X_GpioFunctionality_group */
-
-
-/* Device register map */
-
-/** @defgroup VL53L0X_DefineRegisters_group Define Registers
- * @brief List of all the defined registers
- * @{
- */
-#define VL53L0X_REG_SYSRANGE_START 0x000
-/** mask existing bit in #VL53L0X_REG_SYSRANGE_START*/
-#define VL53L0X_REG_SYSRANGE_MODE_MASK 0x0F
-/** bit 0 in #VL53L0X_REG_SYSRANGE_START write 1 toggle state in
- * continuous mode and arm next shot in single shot mode */
-#define VL53L0X_REG_SYSRANGE_MODE_START_STOP 0x01
-/** bit 1 write 0 in #VL53L0X_REG_SYSRANGE_START set single shot mode */
-#define VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT 0x00
-/** bit 1 write 1 in #VL53L0X_REG_SYSRANGE_START set back-to-back
- * operation mode */
-#define VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK 0x02
-/** bit 2 write 1 in #VL53L0X_REG_SYSRANGE_START set timed operation
- * mode */
-#define VL53L0X_REG_SYSRANGE_MODE_TIMED 0x04
-/** bit 3 write 1 in #VL53L0X_REG_SYSRANGE_START set histogram operation
- * mode */
-#define VL53L0X_REG_SYSRANGE_MODE_HISTOGRAM 0x08
-
-
-#define VL53L0X_REG_SYSTEM_THRESH_HIGH 0x000C
-#define VL53L0X_REG_SYSTEM_THRESH_LOW 0x000E
-
-
-#define VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG 0x0001
-#define VL53L0X_REG_SYSTEM_RANGE_CONFIG 0x0009
-#define VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD 0x0004
-
-
-#define VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO 0x000A
-#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_DISABLED 0x00
-#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_LOW 0x01
-#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_HIGH 0x02
-#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_OUT_OF_WINDOW 0x03
-#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY 0x04
-
-#define VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH 0x0084
-
-
-#define VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR 0x000B
-
-/* Result registers */
-#define VL53L0X_REG_RESULT_INTERRUPT_STATUS 0x0013
-#define VL53L0X_REG_RESULT_RANGE_STATUS 0x0014
-
-#define VL53L0X_REG_RESULT_CORE_PAGE 1
-#define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN 0x00BC
-#define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN 0x00C0
-#define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF 0x00D0
-#define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_REF 0x00D4
-#define VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF 0x00B6
-
-/* Algo register */
-
-#define VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM 0x0028
-
-#define VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS 0x008a
-
-/* Check Limit registers */
-#define VL53L0X_REG_MSRC_CONFIG_CONTROL 0x0060
-
-#define VL53L0X_REG_PRE_RANGE_CONFIG_MIN_SNR 0X0027
-#define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW 0x0056
-#define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH 0x0057
-#define VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT 0x0064
-
-#define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_SNR 0X0067
-#define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW 0x0047
-#define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH 0x0048
-#define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT 0x0044
-
-
-#define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_HI 0X0061
-#define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_LO 0X0062
-
-/* PRE RANGE registers */
-#define VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD 0x0050
-#define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0051
-#define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0052
-
-#define VL53L0X_REG_SYSTEM_HISTOGRAM_BIN 0x0081
-#define VL53L0X_REG_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT 0x0033
-#define VL53L0X_REG_HISTOGRAM_CONFIG_READOUT_CTRL 0x0055
-
-#define VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD 0x0070
-#define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0071
-#define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0072
-#define VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS 0x0020
-
-#define VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP 0x0046
-
-
-#define VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N 0x00bf
-#define VL53L0X_REG_IDENTIFICATION_MODEL_ID 0x00c0
-#define VL53L0X_REG_IDENTIFICATION_REVISION_ID 0x00c2
-
-#define VL53L0X_REG_OSC_CALIBRATE_VAL 0x00f8
-
-
-#define VL53L0X_SIGMA_ESTIMATE_MAX_VALUE 65535
-/* equivalent to a range sigma of 655.35mm */
-
-#define VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH 0x032
-#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 0x0B0
-#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_1 0x0B1
-#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_2 0x0B2
-#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_3 0x0B3
-#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_4 0x0B4
-#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_5 0x0B5
-
-#define VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT 0xB6
-#define VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD 0x4E /* 0x14E */
-#define VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET 0x4F /* 0x14F */
-#define VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE 0x80
-
-/*
- * Speed of light in um per 1E-10 Seconds
- */
-
-#define VL53L0X_SPEED_OF_LIGHT_IN_AIR 2997
-
-#define VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV 0x0089
-
-#define VL53L0X_REG_ALGO_PHASECAL_LIM 0x0030 /* 0x130 */
-#define VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT 0x0030
-
-/** @} VL53L0X_DefineRegisters_group */
-
-/** @} VL53L0X_DevSpecDefines_group */
-
-
-#endif
-
-/* _VL53L0X_DEVICE_H_ */
-
-
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_interrupt_threshold_settings.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,195 +0,0 @@
-/*******************************************************************************
-Copyright © 2016, STMicroelectronics International N.V.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
-IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************/
-
-
-#ifndef _VL53L0X_INTERRUPT_THRESHOLD_SETTINGS_H_
-#define _VL53L0X_INTERRUPT_THRESHOLD_SETTINGS_H_
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-uint8_t InterruptThresholdSettings[] = {
-
- /* Start of Interrupt Threshold Settings */
- 0x1, 0xff, 0x00,
- 0x1, 0x80, 0x01,
- 0x1, 0xff, 0x01,
- 0x1, 0x00, 0x00,
- 0x1, 0xff, 0x01,
- 0x1, 0x4f, 0x02,
- 0x1, 0xFF, 0x0E,
- 0x1, 0x00, 0x03,
- 0x1, 0x01, 0x84,
- 0x1, 0x02, 0x0A,
- 0x1, 0x03, 0x03,
- 0x1, 0x04, 0x08,
- 0x1, 0x05, 0xC8,
- 0x1, 0x06, 0x03,
- 0x1, 0x07, 0x8D,
- 0x1, 0x08, 0x08,
- 0x1, 0x09, 0xC6,
- 0x1, 0x0A, 0x01,
- 0x1, 0x0B, 0x02,
- 0x1, 0x0C, 0x00,
- 0x1, 0x0D, 0xD5,
- 0x1, 0x0E, 0x18,
- 0x1, 0x0F, 0x12,
- 0x1, 0x10, 0x01,
- 0x1, 0x11, 0x82,
- 0x1, 0x12, 0x00,
- 0x1, 0x13, 0xD5,
- 0x1, 0x14, 0x18,
- 0x1, 0x15, 0x13,
- 0x1, 0x16, 0x03,
- 0x1, 0x17, 0x86,
- 0x1, 0x18, 0x0A,
- 0x1, 0x19, 0x09,
- 0x1, 0x1A, 0x08,
- 0x1, 0x1B, 0xC2,
- 0x1, 0x1C, 0x03,
- 0x1, 0x1D, 0x8F,
- 0x1, 0x1E, 0x0A,
- 0x1, 0x1F, 0x06,
- 0x1, 0x20, 0x01,
- 0x1, 0x21, 0x02,
- 0x1, 0x22, 0x00,
- 0x1, 0x23, 0xD5,
- 0x1, 0x24, 0x18,
- 0x1, 0x25, 0x22,
- 0x1, 0x26, 0x01,
- 0x1, 0x27, 0x82,
- 0x1, 0x28, 0x00,
- 0x1, 0x29, 0xD5,
- 0x1, 0x2A, 0x18,
- 0x1, 0x2B, 0x0B,
- 0x1, 0x2C, 0x28,
- 0x1, 0x2D, 0x78,
- 0x1, 0x2E, 0x28,
- 0x1, 0x2F, 0x91,
- 0x1, 0x30, 0x00,
- 0x1, 0x31, 0x0B,
- 0x1, 0x32, 0x00,
- 0x1, 0x33, 0x0B,
- 0x1, 0x34, 0x00,
- 0x1, 0x35, 0xA1,
- 0x1, 0x36, 0x00,
- 0x1, 0x37, 0xA0,
- 0x1, 0x38, 0x00,
- 0x1, 0x39, 0x04,
- 0x1, 0x3A, 0x28,
- 0x1, 0x3B, 0x30,
- 0x1, 0x3C, 0x0C,
- 0x1, 0x3D, 0x04,
- 0x1, 0x3E, 0x0F,
- 0x1, 0x3F, 0x79,
- 0x1, 0x40, 0x28,
- 0x1, 0x41, 0x1E,
- 0x1, 0x42, 0x2F,
- 0x1, 0x43, 0x87,
- 0x1, 0x44, 0x00,
- 0x1, 0x45, 0x0B,
- 0x1, 0x46, 0x00,
- 0x1, 0x47, 0x0B,
- 0x1, 0x48, 0x00,
- 0x1, 0x49, 0xA7,
- 0x1, 0x4A, 0x00,
- 0x1, 0x4B, 0xA6,
- 0x1, 0x4C, 0x00,
- 0x1, 0x4D, 0x04,
- 0x1, 0x4E, 0x01,
- 0x1, 0x4F, 0x00,
- 0x1, 0x50, 0x00,
- 0x1, 0x51, 0x80,
- 0x1, 0x52, 0x09,
- 0x1, 0x53, 0x08,
- 0x1, 0x54, 0x01,
- 0x1, 0x55, 0x00,
- 0x1, 0x56, 0x0F,
- 0x1, 0x57, 0x79,
- 0x1, 0x58, 0x09,
- 0x1, 0x59, 0x05,
- 0x1, 0x5A, 0x00,
- 0x1, 0x5B, 0x60,
- 0x1, 0x5C, 0x05,
- 0x1, 0x5D, 0xD1,
- 0x1, 0x5E, 0x0C,
- 0x1, 0x5F, 0x3C,
- 0x1, 0x60, 0x00,
- 0x1, 0x61, 0xD0,
- 0x1, 0x62, 0x0B,
- 0x1, 0x63, 0x03,
- 0x1, 0x64, 0x28,
- 0x1, 0x65, 0x10,
- 0x1, 0x66, 0x2A,
- 0x1, 0x67, 0x39,
- 0x1, 0x68, 0x0B,
- 0x1, 0x69, 0x02,
- 0x1, 0x6A, 0x28,
- 0x1, 0x6B, 0x10,
- 0x1, 0x6C, 0x2A,
- 0x1, 0x6D, 0x61,
- 0x1, 0x6E, 0x0C,
- 0x1, 0x6F, 0x00,
- 0x1, 0x70, 0x0F,
- 0x1, 0x71, 0x79,
- 0x1, 0x72, 0x00,
- 0x1, 0x73, 0x0B,
- 0x1, 0x74, 0x00,
- 0x1, 0x75, 0x0B,
- 0x1, 0x76, 0x00,
- 0x1, 0x77, 0xA1,
- 0x1, 0x78, 0x00,
- 0x1, 0x79, 0xA0,
- 0x1, 0x7A, 0x00,
- 0x1, 0x7B, 0x04,
- 0x1, 0xFF, 0x04,
- 0x1, 0x79, 0x1D,
- 0x1, 0x7B, 0x27,
- 0x1, 0x96, 0x0E,
- 0x1, 0x97, 0xFE,
- 0x1, 0x98, 0x03,
- 0x1, 0x99, 0xEF,
- 0x1, 0x9A, 0x02,
- 0x1, 0x9B, 0x44,
- 0x1, 0x73, 0x07,
- 0x1, 0x70, 0x01,
- 0x1, 0xff, 0x01,
- 0x1, 0x00, 0x01,
- 0x1, 0xff, 0x00,
- 0x00, 0x00, 0x00
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _VL53L0X_INTERRUPT_THRESHOLD_SETTINGS_H_ */
-
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_platform.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,242 +0,0 @@
-/*******************************************************************************
-Copyright © 2015, STMicroelectronics International N.V.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
-IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-********************************************************************************/
-
-
-#ifndef _VL53L0X_PLATFORM_H_
-#define _VL53L0X_PLATFORM_H_
-
-#include "VL53L0X_def.h"
-#include "VL53L0X_platform_log.h"
-//#include "VL53L0X_i2c_platform.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @file vl53l0_platform.h
- *
- * @brief All end user OS/platform/application porting
- */
-
-/**
- * @defgroup VL53L0X_platform_group VL53L0 Platform Functions
- * @brief VL53L0 Platform Functions
- * @{
- */
-
-/**
- * @struct VL53L0X_Dev_t
- * @brief Generic PAL device type that does link between API and platform abstraction layer
- *
- */
-typedef struct {
- VL53L0X_DevData_t Data; /*!< embed ST Ewok Dev data as "Data"*/
-
- /*!< user specific field */
- uint8_t I2cDevAddr; /*!< i2c device address user specific field */
- uint8_t comms_type; /*!< Type of comms : VL53L0X_COMMS_I2C or VL53L0X_COMMS_SPI */
- uint16_t comms_speed_khz; /*!< Comms speed [kHz] : typically 400kHz for I2C */
-
-} VL53L0X_Dev_t;
-
-
-/**
- * @brief Declare the device Handle as a pointer of the structure @a VL53L0X_Dev_t.
- *
- */
-typedef VL53L0X_Dev_t *VL53L0X_DEV;
-
-/**
- * @def PALDevDataGet
- * @brief Get ST private structure @a VL53L0X_DevData_t data access
- *
- * @param Dev Device Handle
- * @param field ST structure field name
- * It maybe used and as real data "ref" not just as "get" for sub-structure item
- * like PALDevDataGet(FilterData.field)[i] or PALDevDataGet(FilterData.MeasurementIndex)++
- */
-#define PALDevDataGet(Dev, field) (Dev->Data.field)
-
-/**
- * @def PALDevDataSet(Dev, field, data)
- * @brief Set ST private structure @a VL53L0X_DevData_t data field
- * @param Dev Device Handle
- * @param field ST structure field name
- * @param data Data to be set
- */
-#define PALDevDataSet(Dev, field, data) (Dev->Data.field)=(data)
-
-
-/**
- * @defgroup VL53L0X_registerAccess_group PAL Register Access Functions
- * @brief PAL Register Access Functions
- * @{
- */
-
-/**
- * Lock comms interface to serialize all commands to a shared I2C interface for a specific device
- * @param Dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_LockSequenceAccess(VL53L0X_DEV Dev);
-
-/**
- * Unlock comms interface to serialize all commands to a shared I2C interface for a specific device
- * @param Dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_UnlockSequenceAccess(VL53L0X_DEV Dev);
-
-
-/**
- * Writes the supplied byte buffer to the device
- * @param Dev Device Handle
- * @param index The register index
- * @param pdata Pointer to uint8_t buffer containing the data to be written
- * @param count Number of bytes in the supplied byte buffer
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_WriteMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count);
-
-/**
- * Reads the requested number of bytes from the device
- * @param Dev Device Handle
- * @param index The register index
- * @param pdata Pointer to the uint8_t buffer to store read data
- * @param count Number of uint8_t's to read
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_ReadMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count);
-
-/**
- * Write single byte register
- * @param Dev Device Handle
- * @param index The register index
- * @param data 8 bit register data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_WrByte(VL53L0X_DEV Dev, uint8_t index, uint8_t data);
-
-/**
- * Write word register
- * @param Dev Device Handle
- * @param index The register index
- * @param data 16 bit register data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_WrWord(VL53L0X_DEV Dev, uint8_t index, uint16_t data);
-
-/**
- * Write double word (4 byte) register
- * @param Dev Device Handle
- * @param index The register index
- * @param data 32 bit register data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_WrDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t data);
-
-/**
- * Read single byte register
- * @param Dev Device Handle
- * @param index The register index
- * @param data pointer to 8 bit data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_RdByte(VL53L0X_DEV Dev, uint8_t index, uint8_t *data);
-
-/**
- * Read word (2byte) register
- * @param Dev Device Handle
- * @param index The register index
- * @param data pointer to 16 bit data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_RdWord(VL53L0X_DEV Dev, uint8_t index, uint16_t *data);
-
-/**
- * Read dword (4byte) register
- * @param Dev Device Handle
- * @param index The register index
- * @param data pointer to 32 bit data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_RdDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t *data);
-
-/**
- * Threat safe Update (read/modify/write) single byte register
- *
- * Final_reg = (Initial_reg & and_data) |or_data
- *
- * @param Dev Device Handle
- * @param index The register index
- * @param AndData 8 bit and data
- * @param OrData 8 bit or data
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_UpdateByte(VL53L0X_DEV Dev, uint8_t index, uint8_t AndData, uint8_t OrData);
-
-/** @} end of VL53L0X_registerAccess_group */
-
-
-/**
- * @brief execute delay in all polling API call
- *
- * A typical multi-thread or RTOs implementation is to sleep the task for some 5ms (with 100Hz max rate faster polling is not needed)
- * if nothing specific is need you can define it as an empty/void macro
- * @code
- * #define VL53L0X_PollingDelay(...) (void)0
- * @endcode
- * @param Dev Device Handle
- * @return VL53L0X_ERROR_NONE Success
- * @return "Other error code" See ::VL53L0X_Error
- */
-VL53L0X_Error VL53L0X_PollingDelay(VL53L0X_DEV Dev); /* usually best implemented as a real function */
-
-/** @} end of VL53L0X_platform_group */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _VL53L0X_PLATFORM_H_ */
-
-
-
-
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_platform_log.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,119 +0,0 @@
-/*******************************************************************************
-Copyright © 2015, STMicroelectronics International N.V.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
-IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-********************************************************************************/
-
-
-#ifndef _VL53L0X_PLATFORM_LOG_H_
-#define _VL53L0X_PLATFORM_LOG_H_
-
-#include <stdio.h>
-#include <string.h>
-/* LOG Functions */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @file vl53l0_platform_log.h
- *
- * @brief platform log function definition
- */
-
-//#define VL53L0X_LOG_ENABLE 0
-
-enum {
- TRACE_LEVEL_NONE,
- TRACE_LEVEL_ERRORS,
- TRACE_LEVEL_WARNING,
- TRACE_LEVEL_INFO,
- TRACE_LEVEL_DEBUG,
- TRACE_LEVEL_ALL,
- TRACE_LEVEL_IGNORE
-};
-
-enum {
- TRACE_FUNCTION_NONE = 0,
- TRACE_FUNCTION_I2C = 1,
- TRACE_FUNCTION_ALL = 0x7fffffff //all bits except sign
-};
-
-enum {
- TRACE_MODULE_NONE = 0x0,
- TRACE_MODULE_API = 0x1,
- TRACE_MODULE_PLATFORM = 0x2,
- TRACE_MODULE_ALL = 0x7fffffff //all bits except sign
-};
-
-
-#ifdef VL53L0X_LOG_ENABLE
-
-#include <sys/time.h>
-
-extern uint32_t _trace_level;
-
-
-
-int32_t VL53L0X_trace_config(char *filename, uint32_t modules, uint32_t level, uint32_t functions);
-
-void trace_print_module_function(uint32_t module, uint32_t level, uint32_t function, const char *format, ...);
-
-
-//extern FILE * log_file;
-
-#define LOG_GET_TIME() (int)clock()
-
-#define _LOG_FUNCTION_START(module, fmt, ... ) \
- trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <START> %s "fmt"\n", LOG_GET_TIME(), __FUNCTION__, ##__VA_ARGS__);
-
-#define _LOG_FUNCTION_END(module, status, ... )\
- trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <END> %s %d\n", LOG_GET_TIME(), __FUNCTION__, (int)status, ##__VA_ARGS__)
-
-#define _LOG_FUNCTION_END_FMT(module, status, fmt, ... )\
- trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <END> %s %d "fmt"\n", LOG_GET_TIME(), __FUNCTION__, (int)status,##__VA_ARGS__)
-
-// __func__ is gcc only
-#define VL53L0X_ErrLog( fmt, ...) fprintf(stderr, "VL53L0X_ErrLog %s" fmt "\n", __func__, ##__VA_ARGS__)
-
-#else /* VL53L0X_LOG_ENABLE no logging */
-#define VL53L0X_ErrLog(...) (void)0
-#define _LOG_FUNCTION_START(module, fmt, ... ) (void)0
-#define _LOG_FUNCTION_END(module, status, ... ) (void)0
-#define _LOG_FUNCTION_END_FMT(module, status, fmt, ... ) (void)0
-#endif /* else */
-
-#define VL53L0X_COPYSTRING(str, ...) strcpy(str, ##__VA_ARGS__)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _VL53L0X_PLATFORM_LOG_H_ */
-
-
-
-
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_tuning.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,147 +0,0 @@
-/*******************************************************************************
-Copyright © 2016, STMicroelectronics International N.V.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
-IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************/
-
-
-#ifndef _VL53L0X_TUNING_H_
-#define _VL53L0X_TUNING_H_
-
-#include "VL53L0X_def.h"
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-uint8_t DefaultTuningSettings[] = {
-
- /* update 02/11/2015_v36 */
- 0x01, 0xFF, 0x01,
- 0x01, 0x00, 0x00,
-
- 0x01, 0xFF, 0x00,
- 0x01, 0x09, 0x00,
- 0x01, 0x10, 0x00,
- 0x01, 0x11, 0x00,
-
- 0x01, 0x24, 0x01,
- 0x01, 0x25, 0xff,
- 0x01, 0x75, 0x00,
-
- 0x01, 0xFF, 0x01,
- 0x01, 0x4e, 0x2c,
- 0x01, 0x48, 0x00,
- 0x01, 0x30, 0x20,
-
- 0x01, 0xFF, 0x00,
- 0x01, 0x30, 0x09, /* mja changed from 0x64. */
- 0x01, 0x54, 0x00,
- 0x01, 0x31, 0x04,
- 0x01, 0x32, 0x03,
- 0x01, 0x40, 0x83,
- 0x01, 0x46, 0x25,
- 0x01, 0x60, 0x00,
- 0x01, 0x27, 0x00,
- 0x01, 0x50, 0x06,
- 0x01, 0x51, 0x00,
- 0x01, 0x52, 0x96,
- 0x01, 0x56, 0x08,
- 0x01, 0x57, 0x30,
- 0x01, 0x61, 0x00,
- 0x01, 0x62, 0x00,
- 0x01, 0x64, 0x00,
- 0x01, 0x65, 0x00,
- 0x01, 0x66, 0xa0,
-
- 0x01, 0xFF, 0x01,
- 0x01, 0x22, 0x32,
- 0x01, 0x47, 0x14,
- 0x01, 0x49, 0xff,
- 0x01, 0x4a, 0x00,
-
- 0x01, 0xFF, 0x00,
- 0x01, 0x7a, 0x0a,
- 0x01, 0x7b, 0x00,
- 0x01, 0x78, 0x21,
-
- 0x01, 0xFF, 0x01,
- 0x01, 0x23, 0x34,
- 0x01, 0x42, 0x00,
- 0x01, 0x44, 0xff,
- 0x01, 0x45, 0x26,
- 0x01, 0x46, 0x05,
- 0x01, 0x40, 0x40,
- 0x01, 0x0E, 0x06,
- 0x01, 0x20, 0x1a,
- 0x01, 0x43, 0x40,
-
- 0x01, 0xFF, 0x00,
- 0x01, 0x34, 0x03,
- 0x01, 0x35, 0x44,
-
- 0x01, 0xFF, 0x01,
- 0x01, 0x31, 0x04,
- 0x01, 0x4b, 0x09,
- 0x01, 0x4c, 0x05,
- 0x01, 0x4d, 0x04,
-
-
- 0x01, 0xFF, 0x00,
- 0x01, 0x44, 0x00,
- 0x01, 0x45, 0x20,
- 0x01, 0x47, 0x08,
- 0x01, 0x48, 0x28,
- 0x01, 0x67, 0x00,
- 0x01, 0x70, 0x04,
- 0x01, 0x71, 0x01,
- 0x01, 0x72, 0xfe,
- 0x01, 0x76, 0x00,
- 0x01, 0x77, 0x00,
-
- 0x01, 0xFF, 0x01,
- 0x01, 0x0d, 0x01,
-
- 0x01, 0xFF, 0x00,
- 0x01, 0x80, 0x01,
- 0x01, 0x01, 0xF8,
-
- 0x01, 0xFF, 0x01,
- 0x01, 0x8e, 0x01,
- 0x01, 0x00, 0x01,
- 0x01, 0xFF, 0x00,
- 0x01, 0x80, 0x00,
-
- 0x00, 0x00, 0x00
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _VL53L0X_TUNING_H_ */
-
--- a/STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_types.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,112 +0,0 @@
-/*******************************************************************************
-Copyright © 2015, STMicroelectronics International N.V.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of STMicroelectronics nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
-IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-********************************************************************************/
-/**
- * @file vl53l0_types.h
- * @brief VL53L0 types definition
- */
-
-#ifndef VL53L0X_TYPES_H_
-#define VL53L0X_TYPES_H_
-
-/** @defgroup porting_type Basic type definition
- * @ingroup VL53L0X_platform_group
- *
- * @brief file vl53l0_types.h files hold basic type definition that may requires porting
- *
- * contains type that must be defined for the platform\n
- * when target platform and compiler provide stdint.h and stddef.h it is enough to include it.\n
- * If stdint.h is not available review and adapt all signed and unsigned 8/16/32 bits basic types. \n
- * If stddef.h is not available review and adapt NULL definition .
- */
-#include <stdint.h>
-#include <stddef.h>
-
-#ifndef NULL
-#error "Error NULL definition should be done. Please add required include "
-#endif
-
-
-#if ! defined(STDINT_H) && !defined(_GCC_STDINT_H) &&!defined(__STDINT_DECLS) && !defined(_GCC_WRAP_STDINT_H)
-
-#pragma message("Please review type definition of STDINT define for your platform and add to list above ")
-
-/*
- * target platform do not provide stdint or use a different #define than above
- * to avoid seeing the message below addapt the #define list above or implement
- * all type and delete these pragma
- */
-
-/** \ingroup VL53L0X_portingType_group
- * @{
- */
-
-
-typedef unsigned long long uint64_t;
-
-
-/** @brief Typedef defining 32 bit unsigned int type.\n
- * The developer should modify this to suit the platform being deployed.
- */
-typedef unsigned int uint32_t;
-
-/** @brief Typedef defining 32 bit int type.\n
- * The developer should modify this to suit the platform being deployed.
- */
-typedef int int32_t;
-
-/** @brief Typedef defining 16 bit unsigned short type.\n
- * The developer should modify this to suit the platform being deployed.
- */
-typedef unsigned short uint16_t;
-
-/** @brief Typedef defining 16 bit short type.\n
- * The developer should modify this to suit the platform being deployed.
- */
-typedef short int16_t;
-
-/** @brief Typedef defining 8 bit unsigned char type.\n
- * The developer should modify this to suit the platform being deployed.
- */
-typedef unsigned char uint8_t;
-
-/** @brief Typedef defining 8 bit char type.\n
- * The developer should modify this to suit the platform being deployed.
- */
-typedef signed char int8_t;
-
-/** @} */
-#endif /* _STDINT_H */
-
-
-/** use where fractional values are expected
- *
- * Given a floating point value f it's .16 bit point is (int)(f*(1<<16))*/
-typedef uint32_t FixPoint1616_t;
-
-#endif /* VL53L0X_TYPES_H_ */
-
--- a/STM32F103C8T6_MPA/language.settings.xml Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,32 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
-
-
- <configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.615294631" name="Debug">
- <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
- <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
- <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
- <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
- <provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1025524915312781673" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
- <language-scope id="org.eclipse.cdt.core.gcc"/>
- <language-scope id="org.eclipse.cdt.core.g++"/>
- </provider>
- </extension>
- </configuration>
-
-
- <configuration id="fr.ac6.managedbuild.config.gnu.cross.exe.release.088596962" name="Release">
- <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
- <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
- <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
- <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
- <provider class="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" console="false" env-hash="-1025524915312781673" id="fr.ac6.mcu.ide.build.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="Ac6 SW4 STM32 MCU Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
- <language-scope id="org.eclipse.cdt.core.gcc"/>
- <language-scope id="org.eclipse.cdt.core.g++"/>
- </provider>
- </extension>
- </configuration>
-
-</project>
\ No newline at end of file
--- a/STM32F103C8T6_MPA/main.cpp Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,130 +0,0 @@
-#include "stm32f103c8t6.h"
-#include "mbed.h"
-/*
- * Mbed Application program
- * Time-of-Flight ranging and gesture detection sensor / STMicro VL53L0X
- * http://www.st.com/ja/imaging-and-photonics-solutions/vl53l0x.html
- *
- * 1) AKIZUKI AE-VL53L0X
- * http://akizukidenshi.com/catalog/g/gM-12590/
- * 2) SWITCH SCIENCE Pololu VL53L0X (POLOLU-2490)
- * https://www.switch-science.com/catalog/2869/
- * 3) SWITCH SCIENCE VL53L0X (SSCI-028943)
- * https://www.switch-science.com/catalog/2894/
- * 4) Strawberry Linux
- * https://strawberry-linux.com/catalog/items?code=15310
- *
- * ---- Tested AE-VL53L0X BOARD and handmade circuit ----
- * Tested on below Mbed boards and works fine on mbed 2.0
- * Nucleo-F303K8
- * Nucleo-F334R8, -F401RE, -F411RE, -F446RE
- * Nucleo-L053R8, -L073RZ, -L152RE, -L476RG
- * FRDM-K64F
- * TY51822r3
- * Run also on mbed-os5 (Tested on Nucleo-F446RE)
- *
- * Copyright (c) 2018 Kenji Arai / JH1PJL
- * http://www.page.sannet.ne.jp/kenjia/index.html
- * http://mbed.org/users/kenjiArai/
- * Created: January 21st, 2018
- * Revised: Feburary 6th, 2018 (with updated VL53L0X_simple library)
- */
-
-// Include --------------------------------------------------------------------
-#include "VL53L0X.h"
-
-// Definition -----------------------------------------------------------------
-#define USE_XSHUT 1
-
-// Constructor ----------------------------------------------------------------
-DigitalOut myled(PA_5);
-DigitalOut CAN_STB(PA_4);
-
-CAN can1(PA_11, PA_12);
-
-Serial pc(USBTX, USBRX, 9600);
-//I2C i2c(P0_30, P0_7); // only for TY51822r3
-I2C i2c(PB_9, PB_8); //placa hensys
-//I2C i2c(PB_11, PB_10); //bluepill
-
-#if USE_XSHUT
-VL53L0X sensor(i2c, PA_8); // XSHUT = D8
-#else
-VL53L0X sensor(i2c, NC); // XSHUT = NC
-#endif
-Timer t;
-
-// RAM ------------------------------------------------------------------------
-
-// ROM / Constant data --------------------------------------------------------
-char *const msg0 = "VL53L0X is running correctly!!\r\n";
-char *const msg1 = "VL53L0X -> something is wrong!!\r\n";
-char *const msg2 = "#,";
-char *const msg3 = "d[mm]=,";
-char *const msg4 = "d[mm]=,error,";
-char *const msg5 = "VL53[mS]=, ";
-char *const msg6 = "all[mS]=, ";
-
-// Function prototypes --------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Control Program
-//------------------------------------------------------------------------------
-int main()
-{
- char bosta = 1;
- can1.frequency(500000);
- CAN_STB = 0;
- int status = VL53L0X_ERROR_NONE;
- uint32_t data;
- uint32_t count = 0;
- uint32_t tm_sensor;
- uint32_t tm_all_work;
-
-#if USE_XSHUT
- status = sensor.init_sensor(0x53); // set new I2C address
-#else
- // no control XSHUT then set default address (no other way)
- status = sensor.init_sensor(VL53L0X_DEFAULT_ADDRESS);
-#endif
- if (status == VL53L0X_ERROR_NONE) {
- pc.printf(msg0);
- } else {
- pc.printf(msg1);
- }
- //status = sensor.set_mode(range_long_distance_33ms_200cm);
- //status = sensor.set_mode(range_hi_accurate_200ms_120cm);
- status = sensor.set_mode(range_hi_speed_20ms_120cm);
- if (status == VL53L0X_ERROR_NONE) {
- pc.printf(msg0);
- } else {
- pc.printf(msg1);
- }
- while(true) {
- //can1.write(CANMessage(1337,&bosta,1));
- //wait(0.2);
- t.reset();
- t.start();
- pc.printf("olar");
- //myled = !myled;
- status = sensor.get_distance(&data);
- tm_sensor = t.read_ms();
- if (status == VL53L0X_ERROR_NONE) {
- pc.printf("%s%5d,%s%5d,", msg2, count++, msg3, data);
- if(data >= 300){
- myled = 1;
- can1.write(CANMessage(1337,&bosta,1));
- wait(0.2);
- }
- else {
- myled = 0;}
- } else {
- pc.printf("%s%5d,%s", msg2, count++, msg4);
- }
- pc.printf("%s%d,%s%d\r\n", msg5, tm_sensor, msg6, tm_all_work);
- tm_all_work = t.read_ms();
- if (tm_all_work < 99){
- wait_ms(100 - tm_all_work);
- }
- }
-}
--- a/STM32F103C8T6_MPA/makefile.targets Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,18 +0,0 @@ -# DO NOT REMOVE! Generated by the SW4STM32 exporter from the mbed project. - -PREPROC_CMD ?= arm-none-eabi-cpp -E -P - -ldclean: - $(RM) linker-script-debug.ld - $(RM) linker-script-release.ld - -linker-script-debug.ld: ../mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld - $(PREPROC_CMD) -DMBED_DEBUG -DMBED_TRAP_ERRORS_ENABLED=1 -Wl,-n -Wl,--start-group -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys -Wl,--end-group $< -o $@ - -STM32F103C8T6_MPA-debug.elf: linker-script-debug.ld - -linker-script-release.ld: ../mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld - $(PREPROC_CMD) -DNDEBUG -Wl,-n -Wl,--start-group -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys -Wl,--end-group $< -o $@ - -STM32F103C8T6_MPA-release.elf: linker-script-release.ld -
--- a/STM32F103C8T6_MPA/mbed-STM32F103C8T6/PinNames.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,152 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- *
- * Modified by Zoltan Hudak 2017
- *
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-#include "PinNamesTypes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- // Not connected
- NC = (int)0xFFFFFFFF,
-
- // Ports
- PA_0 = 0x00,
- PA_1 = 0x01,
- PA_2 = 0x02,
- PA_3 = 0x03,
- PA_4 = 0x04,
- PA_5 = 0x05,
- PA_6 = 0x06,
- PA_7 = 0x07,
- PA_8 = 0x08,
- PA_9 = 0x09,
- PA_10 = 0x0A,
- PA_11 = 0x0B,
- PA_12 = 0x0C,
- PA_13 = NC,
- PA_14 = NC,
- PA_15 = 0x0F,
-
- PB_0 = 0x10,
- PB_1 = 0x11,
- PB_2 = NC,
- PB_3 = 0x13,
- PB_4 = 0x14,
- PB_5 = 0x15,
- PB_6 = 0x16,
- PB_7 = 0x17,
- PB_8 = 0x18,
- PB_9 = 0x19,
- PB_10 = 0x1A,
- PB_11 = 0x1B,
- PB_12 = 0x1C,
- PB_13 = 0x1D,
- PB_14 = 0x1E,
- PB_15 = 0x1F,
-
- PC_0 = NC,
- PC_1 = NC,
- PC_2 = NC,
- PC_3 = NC,
- PC_4 = NC,
- PC_5 = NC,
- PC_6 = NC,
- PC_7 = NC,
- PC_8 = NC,
- PC_9 = NC,
- PC_10 = NC,
- PC_11 = NC,
- PC_12 = NC,
- PC_13 = 0x2D,
- PC_14 = 0x2E,
- PC_15 = 0x2F,
-
- PD_2 = NC,
-
- // ADC internal channels
- ADC_TEMP = 0xF0,
- ADC_VREF = 0xF1,
-
- // Arduino connector namings
- A0 = PA_0,
- A1 = PA_1,
- A2 = PA_4,
- A3 = PB_0,
- A4 = NC,
- A5 = NC,
- D0 = PA_3,
- D1 = PA_2,
- D2 = PA_10,
- D3 = PB_3,
- D4 = PB_5,
- D5 = PB_4,
- D6 = PB_10,
- D7 = PA_8,
- D8 = PA_9,
- D9 = NC,
- D10 = PB_6,
- D11 = PA_7,
- D12 = PA_6,
- D13 = PA_5,
- D14 = PB_9,
- D15 = PB_8,
-
- // Generic signals namings
- LED1 = PC_13,
- LED2 = NC,
- LED3 = NC,
- LED4 = NC,
- USER_BUTTON = NC,
- SERIAL_TX = PA_2,
- SERIAL_RX = PA_3,
- USBTX = PA_2,
- USBRX = PA_3,
- I2C_SCL = PB_8,
- I2C_SDA = PB_9,
- SPI_MOSI = PA_7,
- SPI_MISO = PA_6,
- SPI_SCK = PA_5,
- SPI_CS = PB_6,
- PWM_OUT = PB_3
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
\ No newline at end of file
--- a/STM32F103C8T6_MPA/mbed-STM32F103C8T6/SysClockConf.cpp Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/*
- ******************************************************************************
- * @file SysClockConf.c
- * @author Zoltan Hudak
- * @version
- * @date 05-July-2016
- * @brief System Clock configuration for STM32F103C8T6
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 Zoltan Hudak <hudakz@outlook.com>
- *
- * All rights reserved.
-
- This program is free software: you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation, either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "SysClockConf.h"
-#include "mbed.h"
-
-void HSE_SystemClock_Config(void) {
- RCC_OscInitTypeDef RCC_OscInitStruct;
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_PeriphCLKInitTypeDef PeriphClkInit;
-
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSEState = RCC_HSE_ON;
- RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
- HAL_RCC_OscConfig(&RCC_OscInitStruct);
- RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
- PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB;
- PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
- PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
- HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
-}
-
-void confSysClock(void) {
- HAL_RCC_DeInit();
- HSE_SystemClock_Config();
- SystemCoreClockUpdate();
-}
--- a/STM32F103C8T6_MPA/mbed-STM32F103C8T6/SysClockConf.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -#pragma once -void confSysClock(void); \ No newline at end of file
--- a/STM32F103C8T6_MPA/mbed-STM32F103C8T6/stm32f103c8t6.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -#pragma once -#include "PinNames.h" -#include "SysClockConf.h"
--- a/STM32F103C8T6_MPA/mbed.bld Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1 +0,0 @@ -https://os.mbed.com/users/mbed_official/code/mbed/builds/65be27845400 \ No newline at end of file
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/PeripheralNames.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,74 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
- UART_1 = (int)USART1_BASE,
- UART_2 = (int)USART2_BASE,
- UART_3 = (int)USART3_BASE
-} UARTName;
-
-typedef enum {
- SPI_1 = (int)SPI1_BASE,
- SPI_2 = (int)SPI2_BASE
-} SPIName;
-
-typedef enum {
- I2C_1 = (int)I2C1_BASE,
- I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
- PWM_1 = (int)TIM1_BASE,
- PWM_2 = (int)TIM2_BASE,
- PWM_3 = (int)TIM3_BASE,
- PWM_4 = (int)TIM4_BASE
-} PWMName;
-
-typedef enum {
- CAN_1 = (int)CAN1_BASE
-} CANName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/PeripheralPins.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,89 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_PERIPHERALPINS_H -#define MBED_PERIPHERALPINS_H - -#include "pinmap.h" -#include "PeripheralNames.h" - -//*** ADC *** -#if DEVICE_ANALOGIN -extern const PinMap PinMap_ADC[]; -extern const PinMap PinMap_ADC_Internal[]; -#endif - -//*** DAC *** -#if DEVICE_ANALOGOUT -extern const PinMap PinMap_DAC[]; -#endif - -//*** I2C *** -#if DEVICE_I2C -extern const PinMap PinMap_I2C_SDA[]; -extern const PinMap PinMap_I2C_SCL[]; -#endif - -//*** PWM *** -#if DEVICE_PWMOUT -extern const PinMap PinMap_PWM[]; -#endif - -//*** SERIAL *** -#if DEVICE_SERIAL -extern const PinMap PinMap_UART_TX[]; -extern const PinMap PinMap_UART_RX[]; -#if DEVICE_SERIAL_FC -extern const PinMap PinMap_UART_RTS[]; -extern const PinMap PinMap_UART_CTS[]; -#endif -#endif - -//*** SPI *** -#if DEVICE_SPI -extern const PinMap PinMap_SPI_MOSI[]; -extern const PinMap PinMap_SPI_MISO[]; -extern const PinMap PinMap_SPI_SCLK[]; -extern const PinMap PinMap_SPI_SSEL[]; -#endif - -//*** CAN *** -#if DEVICE_CAN -extern const PinMap PinMap_CAN_RD[]; -extern const PinMap PinMap_CAN_TD[]; -#endif - -#if DEVICE_QSPI -extern const PinMap PinMap_QSPI_DATA[]; -extern const PinMap PinMap_QSPI_SCLK[]; -extern const PinMap PinMap_QSPI_SSEL[]; -#endif - -#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/PeripheralPins.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/PinNames.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2018, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-#include "PinNamesTypes.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PA_0 = 0x00,
- PA_1 = 0x01,
- PA_2 = 0x02,
- PA_3 = 0x03,
- PA_4 = 0x04,
- PA_5 = 0x05,
- PA_6 = 0x06,
- PA_7 = 0x07,
- PA_8 = 0x08,
- PA_9 = 0x09,
- PA_10 = 0x0A,
- PA_11 = 0x0B,
- PA_12 = 0x0C,
- PA_13 = 0x0D,
- PA_14 = 0x0E,
- PA_15 = 0x0F,
-
- PB_0 = 0x10,
- PB_1 = 0x11,
- PB_2 = 0x12,
- PB_3 = 0x13,
- PB_4 = 0x14,
- PB_5 = 0x15,
- PB_6 = 0x16,
- PB_7 = 0x17,
- PB_8 = 0x18,
- PB_9 = 0x19,
- PB_10 = 0x1A,
- PB_11 = 0x1B,
- PB_12 = 0x1C,
- PB_13 = 0x1D,
- PB_14 = 0x1E,
- PB_15 = 0x1F,
-
- PC_0 = 0x20,
- PC_1 = 0x21,
- PC_2 = 0x22,
- PC_3 = 0x23,
- PC_4 = 0x24,
- PC_5 = 0x25,
- PC_6 = 0x26,
- PC_7 = 0x27,
- PC_8 = 0x28,
- PC_9 = 0x29,
- PC_10 = 0x2A,
- PC_11 = 0x2B,
- PC_12 = 0x2C,
- PC_13 = 0x2D,
- PC_14 = 0x2E,
- PC_15 = 0x2F,
-
- PD_0 = 0x30,
- PD_1 = 0x31,
- PD_2 = 0x32,
-
- // ADC internal channels
- ADC_TEMP = 0xF0,
- ADC_VREF = 0xF1,
-
- // Arduino connector namings
- A0 = PA_0,
- A1 = PA_1,
- A2 = PA_4,
- A3 = PB_0,
- A4 = PC_1,
- A5 = PC_0,
- D0 = PA_3,
- D1 = PA_2,
- D2 = PA_10,
- D3 = PB_3,
- D4 = PB_5,
- D5 = PB_4,
- D6 = PB_10,
- D7 = PA_8,
- D8 = PA_9,
- D9 = PC_7,
- D10 = PB_6,
- D11 = PA_7,
- D12 = PA_6,
- D13 = PA_5,
- D14 = PB_9,
- D15 = PB_8,
-
- // STDIO for console print
-#ifdef MBED_CONF_TARGET_STDIO_UART_TX
- STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
-#else
- STDIO_UART_TX = PA_2,
-#endif
-#ifdef MBED_CONF_TARGET_STDIO_UART_RX
- STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
-#else
- STDIO_UART_RX = PA_3,
-#endif
-
- // Generic signals namings
- LED1 = PA_5,
- LED2 = PA_5,
- LED3 = PA_5,
- LED4 = PA_5,
- USER_BUTTON = PC_13,
- // Standardized button names
- BUTTON1 = USER_BUTTON,
- SERIAL_TX = STDIO_UART_TX,
- SERIAL_RX = STDIO_UART_RX,
- USBTX = STDIO_UART_TX,
- USBRX = STDIO_UART_RX,
- I2C_SCL = PB_8,
- I2C_SDA = PB_9,
- SPI_MOSI = PA_7,
- SPI_MISO = PA_6,
- SPI_SCK = PA_5,
- SPI_CS = PB_6,
- PWM_OUT = PB_3,
-
- /**** USB pins ****/
- USB_DM = PA_11,
- USB_DP = PA_12,
-
- /**** OSCILLATOR pins ****/
- RCC_OSC32_IN = PC_14,
- RCC_OSC32_OUT = PC_15,
- RCC_OSC_IN = PD_0,
- RCC_OSC_OUT = PD_1,
-
- /**** DEBUG pins ****/
- SYS_JTCK_SWCLK = PA_14,
- SYS_JTDI = PA_15,
- SYS_JTDO_TRACESWO = PB_3,
- SYS_JTMS_SWDIO = PA_13,
- SYS_NJTRST = PB_4,
- SYS_WKUP = PA_0,
-
- // Not connected
- NC = (int)0xFFFFFFFF
-} PinName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/PinNamesTypes.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,158 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMESTYPES_H
-#define MBED_PINNAMESTYPES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* STM PIN data as used in pin_function is coded on 32 bits as below
- * [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog
- * [3] Output Push-Pull / Open Drain (as in OTYPER reg)
- * [5:4] as in PUPDR reg: No Pull, Pull-up, Pull-Donc
- * [7:6] Reserved for speed config (as in OSPEEDR), but not used yet
- * [11:8] Alternate Num (as in AFRL/AFRG reg)
- * [16:12] Channel (Analog/Timer specific)
- * [17] Inverted (Analog/Timer specific)
- * [18] Analog ADC control - Only valid for specific families
- * [32:19] Reserved
- */
-
-#define STM_PIN_FUNCTION_MASK 0x07
-#define STM_PIN_FUNCTION_SHIFT 0
-#define STM_PIN_FUNCTION_BITS (STM_PIN_FUNCTION_MASK << STM_PIN_FUNCTION_SHIFT)
-
-#define STM_PIN_OD_MASK 0x01
-#define STM_PIN_OD_SHIFT 3
-#define STM_PIN_OD_BITS (STM_PIN_OD_MASK << STM_PIN_OD_SHIFT)
-
-#define STM_PIN_PUPD_MASK 0x03
-#define STM_PIN_PUPD_SHIFT 4
-#define STM_PIN_PUPD_BITS (STM_PIN_PUPD_MASK << STM_PIN_PUPD_SHIFT)
-
-#define STM_PIN_SPEED_MASK 0x03
-#define STM_PIN_SPEED_SHIFT 6
-#define STM_PIN_SPEED_BITS (STM_PIN_SPEED_MASK << STM_PIN_SPEED_SHIFT)
-
-#define STM_PIN_AFNUM_MASK 0x0F
-#define STM_PIN_AFNUM_SHIFT 8
-#define STM_PIN_AFNUM_BITS (STM_PIN_AFNUM_MASK << STM_PIN_AFNUM_SHIFT)
-
-#define STM_PIN_CHAN_MASK 0x1F
-#define STM_PIN_CHAN_SHIFT 12
-#define STM_PIN_CHANNEL_BIT (STM_PIN_CHAN_MASK << STM_PIN_CHAN_SHIFT)
-
-#define STM_PIN_INV_MASK 0x01
-#define STM_PIN_INV_SHIFT 17
-#define STM_PIN_INV_BIT (STM_PIN_INV_MASK << STM_PIN_INV_SHIFT)
-
-#define STM_PIN_AN_CTRL_MASK 0x01
-#define STM_PIN_AN_CTRL_SHIFT 18
-#define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT)
-
-#define STM_PIN_FUNCTION(X) (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK)
-#define STM_PIN_OD(X) (((X) >> STM_PIN_OD_SHIFT) & STM_PIN_OD_MASK)
-#define STM_PIN_PUPD(X) (((X) >> STM_PIN_PUPD_SHIFT) & STM_PIN_PUPD_MASK)
-#define STM_PIN_SPEED(X) (((X) >> STM_PIN_SPEED_SHIFT) & STM_PIN_SPEED_MASK)
-#define STM_PIN_AFNUM(X) (((X) >> STM_PIN_AFNUM_SHIFT) & STM_PIN_AFNUM_MASK)
-#define STM_PIN_CHANNEL(X) (((X) >> STM_PIN_CHAN_SHIFT) & STM_PIN_CHAN_MASK)
-#define STM_PIN_INVERTED(X) (((X) >> STM_PIN_INV_SHIFT) & STM_PIN_INV_MASK)
-#define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK)
-
-#define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\
- ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
- ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT))
-
-#define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \
- ((int)(FUNC_OD) |\
- ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\
- ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\
- ((CHAN & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\
- ((INV & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT))
-
-/*
- * MACROS to support the legacy definition of PIN formats
- * The STM_MODE_ defines contain the function and the Push-pull/OpenDrain
- * configuration (legacy inheritance).
- */
-#define STM_PIN_DATA(FUNC_OD, PUPD, AFNUM) \
- STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM)
-#define STM_PIN_DATA_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED) \
- STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED)
-
-typedef enum {
- STM_PIN_INPUT = 0,
- STM_PIN_OUTPUT = 1,
- STM_PIN_ALTERNATE = 2,
- STM_PIN_ANALOG = 3,
-} StmPinFunction;
-
-#define STM_MODE_INPUT (STM_PIN_INPUT)
-#define STM_MODE_OUTPUT_PP (STM_PIN_OUTPUT)
-#define STM_MODE_OUTPUT_OD (STM_PIN_OUTPUT | STM_PIN_OD_BITS)
-#define STM_MODE_AF_PP (STM_PIN_ALTERNATE)
-#define STM_MODE_AF_OD (STM_PIN_ALTERNATE | STM_PIN_OD_BITS)
-#define STM_MODE_ANALOG (STM_PIN_ANALOG)
-#define STM_MODE_ANALOG_ADC_CONTROL (STM_PIN_ANALOG | STM_PIN_ANALOG_CONTROL_BIT)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X) ((uint32_t)(X) & 0xF)
-
-/* Defines to be used by application */
-typedef enum {
- PIN_INPUT = 0,
- PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
- PullNone = 0,
- PullUp = 1,
- PullDown = 2,
- OpenDrainPullUp = 3,
- OpenDrainNoPull = 4,
- OpenDrainPullDown = 5,
- PushPullNoPull = PullNone,
- PushPullPullUp = PullUp,
- PushPullPullDown = PullDown,
- OpenDrain = OpenDrainPullUp,
- PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/PortNames.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- PortA = 0,
- PortB = 1,
- PortC = 2,
- PortD = 3,
- PortE = 4,
- PortF = 5,
- PortG = 6,
- PortH = 7,
- PortI = 8,
- PortJ = 9,
- PortK = 10
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/RTE_Components.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define CMSIS_device_header <cmsis.h> - -#if defined(MBED_CONF_RTOS_PRESENT) -#include "mbed_rtx_conf.h" -#endif -#include "mbed_cmsis_conf.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/STM32F103XB.ld Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,155 +0,0 @@
-/* Linker script to configure memory regions. */
-/* 0xEC reserved for vectors; 8-byte aligned = 0xF0 */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
- RAM (rwx) : ORIGIN = 0x200000F0, LENGTH = 20K - (0xEC+0x4)
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- * _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
- _sidata = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- _sdata = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(8);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(8);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(8);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- KEEP(*(.jcr*))
- . = ALIGN(8);
- /* All data end */
- __data_end__ = .;
- _edata = .;
-
- } > RAM
-
- .bss :
- {
- . = ALIGN(8);
- __bss_start__ = .;
- _sbss = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(8);
- __bss_end__ = .;
- _ebss = .;
- } > RAM
-
- .heap (COPY):
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
-
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/analogin_api.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/analogin_device.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/analogout_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/arm_math.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,7190 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project: CMSIS DSP Library
- * Title: arm_math.h
- * Description: Public header file for CMSIS DSP Library
- *
- * $Date: 27. January 2017
- * $Revision: V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/**
- \mainpage CMSIS DSP Software Library
- *
- * Introduction
- * ------------
- *
- * This user manual describes the CMSIS DSP software library,
- * a suite of common signal processing functions for use on Cortex-M processor based devices.
- *
- * The library is divided into a number of functions each covering a specific category:
- * - Basic math functions
- * - Fast math functions
- * - Complex math functions
- * - Filters
- * - Matrix functions
- * - Transforms
- * - Motor control functions
- * - Statistical functions
- * - Support functions
- * - Interpolation functions
- *
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,
- * 32-bit integer and 32-bit floating-point values.
- *
- * Using the Library
- * ------------
- *
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
- * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)
- * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)
- * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)
- * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)
- * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)
- * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)
- * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)
- * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)
- * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)
- * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)
- * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)
- * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)
- * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)
- * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)
- * - arm_ARMv8MBLl_math.lib (ARMv8M Baseline, Little endian)
- * - arm_ARMv8MMLl_math.lib (ARMv8M Mainline, Little endian)
- * - arm_ARMv8MMLlfsp_math.lib (ARMv8M Mainline, Little endian, Single Precision Floating Point Unit)
- * - arm_ARMv8MMLld_math.lib (ARMv8M Mainline, Little endian, DSP instructions)
- * - arm_ARMv8MMLldfsp_math.lib (ARMv8M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)
- *
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
- * For ARMv8M cores define pre processor MACRO ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.
- * Set Pre processor MACRO __DSP_PRESENT if ARMv8M Mainline core supports DSP instructions.
- *
- *
- * Examples
- * --------
- *
- * The library ships with a number of examples which demonstrate how to use the library functions.
- *
- * Toolchain Support
- * ------------
- *
- * The library has been developed and tested with MDK-ARM version 5.14.0.0
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
- *
- * Building the Library
- * ------------
- *
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
- * - arm_cortexM_math.uvprojx
- *
- *
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
- *
- * Pre-processor Macros
- * ------------
- *
- * Each library project have differant pre-processor macros.
- *
- * - UNALIGNED_SUPPORT_DISABLE:
- *
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
- *
- * - ARM_MATH_BIG_ENDIAN:
- *
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * - ARM_MATH_MATRIX_CHECK:
- *
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
- *
- * - ARM_MATH_ROUNDING:
- *
- * Define macro ARM_MATH_ROUNDING for rounding on support functions
- *
- * - ARM_MATH_CMx:
- *
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
- * ARM_MATH_CM7 for building the library on cortex-M7.
- *
- * - ARM_MATH_ARMV8MxL:
- *
- * Define macro ARM_MATH_ARMV8MBL for building the library on ARMv8M Baseline target, ARM_MATH_ARMV8MBL for building library
- * on ARMv8M Mainline target.
- *
- * - __FPU_PRESENT:
- *
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.
- *
- * - __DSP_PRESENT:
- *
- * Initialize macro __DSP_PRESENT = 1 when ARMv8M Mainline core supports DSP instructions.
- *
- * <hr>
- * CMSIS-DSP in ARM::CMSIS Pack
- * -----------------------------
- *
- * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
- * |File/Folder |Content |
- * |------------------------------|------------------------------------------------------------------------|
- * |\b CMSIS\\Documentation\\DSP | This documentation |
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
- *
- * <hr>
- * Revision History of CMSIS-DSP
- * ------------
- * Please refer to \ref ChangeLog_pg.
- *
- * Copyright Notice
- * ------------
- *
- * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
- */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures. For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows; // number of rows of the matrix.
- * uint16_t numCols; // number of columns of the matrix.
- * float32_t *pData; // points to the data of the matrix.
- * } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data. The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order. That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- * pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure. For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- * ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- * ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- * ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* Compiler specific diagnostic adjustment */
-#if defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
- #error Unknown compiler
-#endif
-
-
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
- #include "core_cm7.h"
- #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM4)
- #include "core_cm4.h"
- #define ARM_MATH_DSP
-#elif defined (ARM_MATH_CM3)
- #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
- #include "core_cm0.h"
- #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
- #include "core_cm0plus.h"
- #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MBL)
- #include "core_armv8mbl.h"
- #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_ARMV8MML)
- #include "core_armv8mml.h"
- #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))
- #define ARM_MATH_DSP
- #endif
-#else
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML"
-#endif
-
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
- /**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31 (0x100)
-#define DELTA_Q15 0x5
-#define INDEX_MASK 0x0000003F
-#ifndef PI
- #define PI 3.14159265358979f
-#endif
-
- /**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define FAST_MATH_TABLE_SIZE 512
-#define FAST_MATH_Q31_SHIFT (32 - 10)
-#define FAST_MATH_Q15_SHIFT (16 - 10)
-#define CONTROLLER_Q31_SHIFT (32 - 9)
-#define TABLE_SPACING_Q31 0x400000
-#define TABLE_SPACING_Q15 0x80
-
- /**
- * @brief Macros required for SINE and COSINE Controller functions
- */
- /* 1.31(q31) Fixed value of 2/360 */
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING 0xB60B61
-
- /**
- * @brief Macro for Unaligned Support
- */
-#ifndef UNALIGNED_SUPPORT_DISABLE
- #define ALIGN4
-#else
- #if defined (__GNUC__)
- #define ALIGN4 __attribute__((aligned(4)))
- #else
- #define ALIGN4 __align(4)
- #endif
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /**
- * @brief Error status returned by some functions in the library.
- */
-
- typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
-
- /**
- * @brief 8-bit fractional data type in 1.7 format.
- */
- typedef int8_t q7_t;
-
- /**
- * @brief 16-bit fractional data type in 1.15 format.
- */
- typedef int16_t q15_t;
-
- /**
- * @brief 32-bit fractional data type in 1.31 format.
- */
- typedef int32_t q31_t;
-
- /**
- * @brief 64-bit fractional data type in 1.63 format.
- */
- typedef int64_t q63_t;
-
- /**
- * @brief 32-bit floating-point type definition.
- */
- typedef float float32_t;
-
- /**
- * @brief 64-bit floating-point type definition.
- */
- typedef double float64_t;
-
- /**
- * @brief definition to read/write two 16 bit values.
- */
-#if defined ( __CC_ARM )
- #define __SIMD32_TYPE int32_t __packed
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __GNUC__ )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE __attribute__((always_inline))
-
-#elif defined ( __ICCARM__ )
- #define __SIMD32_TYPE int32_t __packed
- #define CMSIS_UNUSED
- #define CMSIS_INLINE
-
-#elif defined ( __TI_ARM__ )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
- #define CMSIS_INLINE
-
-#elif defined ( __CSMC__ )
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED
- #define CMSIS_INLINE
-
-#elif defined ( __TASKING__ )
- #define __SIMD32_TYPE __unaligned int32_t
- #define CMSIS_UNUSED
- #define CMSIS_INLINE
-
-#else
- #error Unknown compiler
-#endif
-
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
-#define __SIMD64(addr) (*(int64_t **) & (addr))
-
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
- /**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
- /**
- * @brief definition to pack four 8 bit values.
- */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-
-#endif
-
-
- /**
- * @brief Clips Q63 to Q31 values.
- */
- CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
- }
-
- /**
- * @brief Clips Q63 to Q15 values.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
- }
-
- /**
- * @brief Clips Q31 to Q7 values.
- */
- CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(
- q31_t x)
- {
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
- }
-
- /**
- * @brief Clips Q31 to Q15 values.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(
- q31_t x)
- {
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
- }
-
- /**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
- CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
- {
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
- (((q63_t) (x >> 32) * y)));
- }
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
-
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- q31_t * pRecipTable)
- {
- q31_t out;
- uint32_t tempVal;
- uint32_t index, i;
- uint32_t signBits;
-
- if (in > 0)
- {
- signBits = ((uint32_t) (__CLZ( in) - 1));
- }
- else
- {
- signBits = ((uint32_t) (__CLZ(-in) - 1));
- }
-
- /* Convert input sample to 1.31 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 24);
- index = (index & INDEX_MASK);
-
- /* 1.31 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (uint32_t) (((q63_t) in * out) >> 31);
- tempVal = 0x7FFFFFFFu - tempVal;
- /* 1.31 with exp 1 */
- /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
- out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1u);
- }
-
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- q15_t * pRecipTable)
- {
- q15_t out = 0;
- uint32_t tempVal = 0;
- uint32_t index = 0, i = 0;
- uint32_t signBits = 0;
-
- if (in > 0)
- {
- signBits = ((uint32_t)(__CLZ( in) - 17));
- }
- else
- {
- signBits = ((uint32_t)(__CLZ(-in) - 17));
- }
-
- /* Convert input sample to 1.15 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 8);
- index = (index & INDEX_MASK);
-
- /* 1.15 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (uint32_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFFu - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1);
- }
-
- /*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-/* #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#if !defined (ARM_MATH_DSP)
-
- /*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(
- uint32_t x,
- uint32_t y)
- {
-/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
- q31_t r = 0, s = 0;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QASX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
- /*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined QADD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE int32_t __QADD(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SXTB16 for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(
- uint32_t x)
- {
- return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
- ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
- }
-
- /*
- * @brief C custom defined SMMLA for M3 and M0 processors
- */
- CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(
- int32_t x,
- int32_t y,
- int32_t sum)
- {
- return (sum + (int32_t) (((int64_t) x * y) >> 32));
- }
-
-#if 0
- /*
- * @brief C custom defined PKHBT for unavailable DSP extension
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __PKHBT(
- uint32_t x,
- uint32_t y,
- uint32_t leftshift)
- {
- return ( ((x ) & 0x0000FFFFUL) |
- ((y << leftshift) & 0xFFFF0000UL) );
- }
-
- /*
- * @brief C custom defined PKHTB for unavailable DSP extension
- */
- CMSIS_INLINE __STATIC_INLINE uint32_t __PKHTB(
- uint32_t x,
- uint32_t y,
- uint32_t rightshift)
- {
- return ( ((x ) & 0xFFFF0000UL) |
- ((y >> rightshift) & 0x0000FFFFUL) );
- }
-#endif
-
-/* #endif // defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-#endif /* !defined (ARM_MATH_DSP) */
-
-
- /**
- * @brief Instance structure for the Q7 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q7;
-
- /**
- * @brief Instance structure for the Q15 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_f32;
-
-
- /**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in] S points to an instance of the Q7 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 FIR filter.
- * @param[in,out] S points to an instance of the Q7 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed.
- */
- void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] S points to an instance of the Q15 FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR filter.
- * @param[in,out] S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * <code>numTaps</code> is not a supported value.
- */
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in] S points to an instance of the Q31 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR filter.
- * @param[in,out] S points to an instance of the Q31 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in] S points to an instance of the floating-point FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR filter.
- * @param[in,out] S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
- typedef struct
- {
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q15;
-
- /**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q31;
-
- /**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_casd_df1_inst_f32;
-
-
- /**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float32_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f32;
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float64_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f64;
-
- /**
- * @brief Instance structure for the Q15 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q15_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q31_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q31;
-
-
- /**
- * @brief Floating-point matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Q31, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
-
- /**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
-
- /**
- * @brief Q31 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix scaling.
- * @param[in] pSrc points to the input matrix
- * @param[in] scale scale factor
- * @param[out] pDst points to the output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t * pData);
-
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t * pData);
-
-
- /**
- * @brief Floating-point matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t * pData);
-
-
-
- /**
- * @brief Instance structure for the Q15 PID Control.
- */
- typedef struct
- {
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
-#if !defined (ARM_MATH_DSP)
- q15_t A1;
- q15_t A2;
-#else
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
- q15_t state[3]; /**< The state array of length 3. */
- q15_t Kp; /**< The proportional gain. */
- q15_t Ki; /**< The integral gain. */
- q15_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 PID Control.
- */
- typedef struct
- {
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- q31_t A2; /**< The derived gain, A2 = Kd . */
- q31_t state[3]; /**< The state array of length 3. */
- q31_t Kp; /**< The proportional gain. */
- q31_t Ki; /**< The integral gain. */
- q31_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point PID Control.
- */
- typedef struct
- {
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- float32_t A2; /**< The derived gain, A2 = Kd . */
- float32_t state[3]; /**< The state array of length 3. */
- float32_t Kp; /**< The proportional gain. */
- float32_t Ki; /**< The integral gain. */
- float32_t Kd; /**< The derivative gain. */
- } arm_pid_instance_f32;
-
-
-
- /**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- */
- void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
-
-
- /**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q31 PID Control structure
- */
-
- void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
-
-
- /**
- * @brief Initialization function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the q15 PID Control structure
- */
- void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
-
-
- /**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
- typedef struct
- {
- uint32_t nValues; /**< nValues */
- float32_t x1; /**< x1 */
- float32_t xSpacing; /**< xSpacing */
- float32_t *pYData; /**< pointer to the table of Y values */
- } arm_linear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q15;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q7;
-
-
- /**
- * @brief Q7 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q15(
- arm_cfft_radix2_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q15(
- const arm_cfft_radix2_instance_q15 * S,
- q15_t * pSrc);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
-
- /**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q31(
- arm_cfft_radix2_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q31(
- const arm_cfft_radix2_instance_q31 * S,
- q31_t * pSrc);
-
- /**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
- void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_f32(
- arm_cfft_radix2_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_f32(
- const arm_cfft_radix2_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
- const arm_cfft_instance_q15 * S,
- q15_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
- const arm_cfft_instance_q31 * S,
- q31_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_f32;
-
- void arm_cfft_f32(
- const arm_cfft_instance_f32 * S,
- float32_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q15;
-
- arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
-
- /**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q31;
-
- arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_f32;
-
- arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct
- {
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
- uint16_t fftLenRFFT; /**< length of the real sequence */
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
- } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
- arm_rfft_fast_instance_f32 * S,
- uint16_t fftLen);
-
-void arm_rfft_fast_f32(
- arm_rfft_fast_instance_f32 * S,
- float32_t * p, float32_t * pOut,
- uint8_t ifftFlag);
-
- /**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- float32_t normalize; /**< normalizing factor. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- float32_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_f32;
-
-
- /**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
- */
- arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
-
-
- /**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q31_t normalize; /**< normalizing factor. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- q31_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q31;
-
-
- /**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
- arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
-
-
- /**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q31 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q15_t normalize; /**< normalizing factor. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- q15_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
- arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
-
-
- /**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q15 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
-
-
- /**
- * @brief Floating-point vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Dot product of floating-point vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
-
-
- /**
- * @brief Dot product of Q7 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
-
-
- /**
- * @brief Dot product of Q15 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Dot product of Q31 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q7 sequences
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Instance structure for the Q15 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in] S points to an instance of the floating-point FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR decimator.
- * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
- arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
- arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
- arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
- } arm_fir_interpolate_instance_f32;
-
-
- /**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
- arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
- arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
- arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
- } arm_biquad_cas_df1_32x64_ins_q31;
-
-
- /**
- * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_stereo_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f64;
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_stereo_df2T_f32(
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f64(
- const arm_biquad_cascade_df2T_instance_f64 * S,
- float64_t * pSrc,
- float64_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_stereo_df2T_init_f32(
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f64(
- arm_biquad_cascade_df2T_instance_f64 * S,
- uint8_t numStages,
- float64_t * pCoeffs,
- float64_t * pState);
-
-
- /**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_f32;
-
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState);
-
-
- /**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState);
-
-
- /**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pkCoeffs,
- float32_t * pvCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pkCoeffs,
- q31_t * pvCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the Q15 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- */
- void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pkCoeffs,
- q15_t * pvCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the floating-point LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that controls filter coefficient updates. */
- } arm_lms_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that control filter coefficient updates. */
- float32_t energy; /**< saves previous frame energy. */
- float32_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q31_t *recipTable; /**< points to the reciprocal initial value table. */
- q31_t energy; /**< saves previous frame energy. */
- q31_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< Number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */
- q15_t energy; /**< saves previous frame energy. */
- q15_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q15;
-
-
- /**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Correlation of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
- void arm_correlate_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
-
- void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
-
- void arm_correlate_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
- void arm_correlate_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_correlate_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q15;
-
- /**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q7;
-
-
- /**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cos output.
- */
- void arm_sin_cos_f32(
- float32_t theta,
- float32_t * pSinVal,
- float32_t * pCosVal);
-
-
- /**
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cosine output.
- */
- void arm_sin_cos_q31(
- q31_t theta,
- q31_t * pSinVal,
- q31_t * pCosVal);
-
-
- /**
- * @brief Floating-point complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- * <pre>
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- * A0 = Kp + Ki + Kd
- * A1 = (-Kp ) - (2 * Kd )
- * A2 = Kd </pre>
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup PID
- * @{
- */
-
- /**
- * @brief Process function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- */
- CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
- {
- float32_t out;
-
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
- out = (S->A0 * in) +
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q31 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
- CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
- {
- q63_t acc;
- q31_t out;
-
- /* acc = A0 * x[n] */
- acc = (q63_t) S->A0 * in;
-
- /* acc += A1 * x[n-1] */
- acc += (q63_t) S->A1 * S->state[0];
-
- /* acc += A2 * x[n-2] */
- acc += (q63_t) S->A2 * S->state[1];
-
- /* convert output to 1.31 format to add y[n-1] */
- out = (q31_t) (acc >> 31u);
-
- /* out += y[n-1] */
- out += S->state[2];
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
-
- /**
- * @brief Process function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
- {
- q63_t acc;
- q15_t out;
-
-#if defined (ARM_MATH_DSP)
- __SIMD32_TYPE *vstate;
-
- /* Implementation of PID controller */
-
- /* acc = A0 * x[n] */
- acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- vstate = __SIMD32_CONST(S->state);
- acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
-#else
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0) * in;
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0];
- acc += (q31_t) S->A2 * S->state[1];
-#endif
-
- /* acc += y[n-1] */
- acc += (q31_t) S->state[2] << 15;
-
- /* saturate the output */
- out = (q15_t) (__SSAT((acc >> 15), 16));
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
- /**
- * @} end of PID group
- */
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f64(
- const arm_matrix_instance_f64 * src,
- arm_matrix_instance_f64 * dst);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup clarke
- * @{
- */
-
- /**
- *
- * @brief Floating-point Clarke transform
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- */
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
- {
- /* Calculate pIalpha using the equation, pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
- }
-
-
- /**
- * @brief Clarke transform for Q31 version
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
- /* pIbeta is calculated by adding the intermediate products */
- *pIbeta = __QADD(product1, product2);
- }
-
- /**
- * @} end of clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_clarke
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Clarke transform
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] pIa points to output three-phase coordinate <code>a</code>
- * @param[out] pIb points to output three-phase coordinate <code>b</code>
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
- {
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
- *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
- }
-
-
- /**
- * @brief Inverse Clarke transform for Q31 version
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] pIa points to output three-phase coordinate <code>a</code>
- * @param[out] pIb points to output three-phase coordinate <code>b</code>
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
- /* pIb is calculated by subtracting the products */
- *pIb = __QSUB(product2, product1);
- }
-
- /**
- * @} end of inv_clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup park
- * @{
- */
-
- /**
- * @brief Floating-point Park transform
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] pId points to output rotor reference frame d
- * @param[out] pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * The function implements the forward Park transform.
- *
- */
- CMSIS_INLINE __STATIC_INLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
- *pId = Ialpha * cosVal + Ibeta * sinVal;
-
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;
- }
-
-
- /**
- * @brief Park transform for Q31 version
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] pId points to output rotor reference frame d
- * @param[out] pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Ialpha * cosVal) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * sinVal) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Ialpha * sinVal) */
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * cosVal) */
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
- /* Calculate pId by adding the two intermediate products 1 and 2 */
- *pId = __QADD(product1, product2);
-
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
- *pIq = __QSUB(product4, product3);
- }
-
- /**
- * @} end of park group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_park
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Park transform
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
- *pIalpha = Id * cosVal - Iq * sinVal;
-
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
- *pIbeta = Id * sinVal + Iq * cosVal;
- }
-
-
- /**
- * @brief Inverse Park transform for Q31 version
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Id * cosVal) */
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * sinVal) */
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Id * sinVal) */
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * cosVal) */
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */
- *pIalpha = __QSUB(product1, product2);
-
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */
- *pIbeta = __QADD(product4, product3);
- }
-
- /**
- * @} end of Inverse park group
- */
-
-
- /**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- * <pre>
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- * where x0, x1 are nearest values of input x
- * y0, y1 are nearest values to output y
- * </pre>
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.
- * <code>x</code> is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
- /**
- * @addtogroup LinearInterpolate
- * @{
- */
-
- /**
- * @brief Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
- * @param[in] x input sample to process
- * @return y processed output sample.
- *
- */
- CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
- {
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (int32_t) ((x - S->x1) / xSpacing);
-
- if (i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if ((uint32_t)i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues - 1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i + 1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
- }
-
- /* returns output value */
- return (y);
- }
-
-
- /**
- *
- * @brief Process function for the Q31 Linear Interpolation Function.
- * @param[in] pYData pointer to Q31 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(
- q31_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q31_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (q31_t)0xFFF00000) >> 20);
-
- if (index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if (index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1u);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q15 Linear Interpolation Function.
- * @param[in] pYData pointer to Q15 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(
- q15_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (int32_t)0xFFF00000) >> 20);
-
- if (index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if (index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (q15_t) (y >> 20);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q7 Linear Interpolation Function.
- * @param[in] pYData pointer to Q7 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
- CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(
- q7_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q7_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- uint32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- if (x < 0)
- {
- return (pYData[0]);
- }
- index = (x >> 20) & 0xfff;
-
- if (index >= (nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (q7_t) (y >> 20);
- }
- }
-
- /**
- * @} end of LinearInterpolate group
- */
-
- /**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
- float32_t arm_sin_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q31_t arm_sin_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q15_t arm_sin_q15(
- q15_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
- float32_t arm_cos_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q31_t arm_cos_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q15_t arm_cos_q15(
- q15_t x);
-
-
- /**
- * @ingroup groupFastMath
- */
-
-
- /**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- * <pre>
- * x1 = x0 - f(x0)/f'(x0)
- * </pre>
- * where <code>x1</code> is the current estimate,
- * <code>x0</code> is the previous estimate, and
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
- * For the square root function, the algorithm reduces to:
- * <pre>
- * x0 = in/2 [initial guess]
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]
- * </pre>
- */
-
-
- /**
- * @addtogroup SQRT
- * @{
- */
-
- /**
- * @brief Floating-point square root function.
- * @param[in] in input value.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(
- float32_t in,
- float32_t * pOut)
- {
- if (in >= 0.0f)
- {
-
-#if (__FPU_USED == 1) && defined ( __CC_ARM )
- *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
- *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
- *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
- __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
- *pOut = sqrtf(in);
-#endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
- }
-
-
- /**
- * @brief Q31 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q31(
- q31_t in,
- q31_t * pOut);
-
-
- /**
- * @brief Q15 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q15(
- q15_t in,
- q15_t * pOut);
-
- /**
- * @} end of SQRT group
- */
-
-
- /**
- * @brief floating-point Circular write function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
-
- /**
- * @brief floating-point Circular Read function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == (int32_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q15 Circular write function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q15 Circular Read function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == (q15_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q7 Circular write function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if (wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q7 Circular Read function.
- */
- CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while (i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if (dst == (q7_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if (rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
-
-
- /**
- * @brief Mean value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Mean value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Floating-point complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
-
-
- /**
- * @brief Q31 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
-
-
- /**
- * @brief Floating-point complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
-
-
- /**
- * @brief Q15 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Minimum value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] result is output pointer
- * @param[in] index is the array index of the minimum value in the input buffer.
- */
- void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
-
-
- /**
- * @brief Minimum value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[in] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * <b>Algorithm</b>
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows;
- * uint16_t numCols;
- * float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- * </pre>
- *
- * \par
- * where <code>numRows</code> specifies the number of rows in the table;
- * <code>numCols</code> specifies the number of columns in the table;
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
- *
- * \par
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
- * <pre>
- * XF = floor(x)
- * YF = floor(y)
- * </pre>
- * \par
- * The interpolated output point is computed as:
- * <pre>
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)
- * </pre>
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
- /**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
-
- /**
- *
- * @brief Floating-point bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate.
- * @param[in] Y interpolation coordinate.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
- {
- float32_t out;
- float32_t f00, f01, f10, f11;
- float32_t *pData = S->pData;
- int32_t xIndex, yIndex, index;
- float32_t xdiff, ydiff;
- float32_t b1, b2, b3, b4;
-
- xIndex = (int32_t) X;
- yIndex = (int32_t) Y;
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
- {
- return (0);
- }
-
- /* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
- /* Read two nearest points in X-direction */
- f00 = pData[index];
- f01 = pData[index + 1];
-
- /* Calculation of index for two nearest points in Y-direction */
- index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
- /* Read two nearest points in Y-direction */
- f10 = pData[index];
- f11 = pData[index + 1];
-
- /* Calculation of intermediate values */
- b1 = f00;
- b2 = f01 - f00;
- b3 = f10 - f00;
- b4 = f00 - f01 - f10 + f11;
-
- /* Calculation of fractional part in X */
- xdiff = X - xIndex;
-
- /* Calculation of fractional part in Y */
- ydiff = Y - yIndex;
-
- /* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
- /* return to application */
- return (out);
- }
-
-
- /**
- *
- * @brief Q31 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
- {
- q31_t out; /* Temporary output */
- q31_t acc = 0; /* output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q31_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* shift left xfract by 11 to keep 1.31 format */
- xfract = (X & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
- x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
- /* 20 bits for the fractional part */
- /* shift left yfract by 11 to keep 1.31 format */
- yfract = (Y & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
- y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* Convert acc to 1.31(q31) format */
- return ((q31_t)(acc << 2));
- }
-
-
- /**
- * @brief Q15 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q15_t x1, x2, y1, y2; /* Nearest output values */
- q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
- q15_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
- acc = ((q63_t) out * (0xFFFFF - yfract));
-
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
- acc += ((q63_t) out * (xfract));
-
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* acc is in 13.51 format and down shift acc by 36 times */
- /* Convert out to 1.15 format */
- return ((q15_t)(acc >> 36));
- }
-
-
- /**
- * @brief Q7 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q7_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
- out = ((x1 * (0xFFFFF - xfract)));
- acc = (((q63_t) out * (0xFFFFF - yfract)));
-
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
- out = ((x2 * (0xFFFFF - yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y1 * (0xFFFFF - xfract)));
- acc += (((q63_t) out * (yfract)));
-
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y2 * (yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
- return ((q7_t)(acc >> 40));
- }
-
- /**
- * @} end of BilinearInterpolate group
- */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if defined ( __CC_ARM )
- /* Enter low optimization region - place directly above function definition */
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("push") \
- _Pragma ("O1")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
- #define LOW_OPTIMIZATION_EXIT \
- _Pragma ("pop")
- #else
- #define LOW_OPTIMIZATION_EXIT
- #endif
-
- /* Enter low optimization region - place directly above function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __GNUC__ )
- #define LOW_OPTIMIZATION_ENTER \
- __attribute__(( optimize("-O1") ))
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __ICCARM__ )
- /* Enter low optimization region - place directly above function definition */
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define LOW_OPTIMIZATION_EXIT
-
- /* Enter low optimization region - place directly above function definition */
- #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TI_ARM__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __CSMC__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined ( __TASKING__ )
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/* Compiler specific diagnostic adjustment */
-#if defined ( __CC_ARM )
-
-#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
-
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-
-#elif defined ( __ICCARM__ )
-
-#elif defined ( __TI_ARM__ )
-
-#elif defined ( __CSMC__ )
-
-#elif defined ( __TASKING__ )
-
-#else
- #error Unknown compiler
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/can_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/can_device.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,43 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_DEVICE_H
-#define MBED_CAN_DEVICE_H
-
-#include "cmsis.h"
-#include "stm32f1xx.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_CAN
-
-#define CAN_NUM 1 // Number of CAN peripherals present in the STM32 serie
-
-#define CAN1_IRQ_RX_IRQN CAN1_RX0_IRQn
-#define CAN1_IRQ_RX_VECT CAN1_RX0_IRQHandler
-#define CAN1_IRQ_TX_IRQN CAN1_TX_IRQn
-#define CAN1_IRQ_TX_VECT CAN1_TX_IRQHandler
-#define CAN1_IRQ_ERROR_IRQN CAN1_SCE_IRQn
-#define CAN1_IRQ_ERROR_VECT CAN1_SCE_IRQHandler
-#define CAN1_IRQ_PASSIVE_IRQN CAN1_SCE_IRQn
-#define CAN1_IRQ_PASSIVE_VECT CAN1_SCE_IRQHandler
-#define CAN1_IRQ_BUS_IRQN CAN1_SCE_IRQn
-#define CAN1_IRQ_BUS_VECT CAN1_SCE_IRQHandler
-
-#endif // DEVICE_CAN
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/* mbed Microcontroller Library - * A generic CMSIS include header - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "stm32f1xx.h" -#include "cmsis_nvic.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis_armcc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,865 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_armcc.h
- * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version V5.0.4
- * @date 10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
- #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
- (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
- #define __ARM_ARCH_6M__ 1
-#endif
-
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
- #define __ARM_ARCH_7M__ 1
-#endif
-
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
- #define __ARM_ARCH_7EM__ 1
-#endif
-
- /* __ARM_ARCH_8M_BASE__ not applicable */
- /* __ARM_ARCH_8M_MAIN__ not applicable */
-
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE __inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static __inline
-#endif
-#ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE static __forceinline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __declspec(noreturn)
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT __packed struct
-#endif
-#ifndef __PACKED_UNION
- #define __PACKED_UNION __packed union
-#endif
-#ifndef __UNALIGNED_UINT32 /* deprecated */
- #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
-#endif
-#ifndef __UNALIGNED_UINT16_WRITE
- #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
-#endif
-#ifndef __UNALIGNED_UINT16_READ
- #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
-#endif
-#ifndef __UNALIGNED_UINT32_WRITE
- #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
-#endif
-#ifndef __UNALIGNED_UINT32_READ
- #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __RESTRICT
- #define __RESTRICT __restrict
-#endif
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); */
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); */
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- register uint32_t __regBasePriMax __ASM("basepri_max");
- __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#else
- (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-#define __ISB() do {\
- __schedule_barrier();\
- __isb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
- __schedule_barrier();\
- __dsb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
- __schedule_barrier();\
- __dmb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
- #define __RBIT __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
- uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value != 0U; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
- return result;
-}
-#endif
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-#else
- #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-#else
- #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-#else
- #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXB(value, ptr) __strex(value, ptr)
-#else
- #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXH(value, ptr) __strex(value, ptr)
-#else
- #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXW(value, ptr) __strex(value, ptr)
-#else
- #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX __clrex
-
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
- rrx r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRBT(value, ptr) __strt(value, ptr)
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRHT(value, ptr) __strt(value, ptr)
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRT(value, ptr) __strt(value, ptr)
-
-#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
- if ((sat >= 1U) && (sat <= 32U))
- {
- const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
- const int32_t min = -1 - max ;
- if (val > max)
- {
- return max;
- }
- else if (val < min)
- {
- return min;
- }
- }
- return val;
-}
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
- if (sat <= 31U)
- {
- const uint32_t max = ((1U << sat) - 1U);
- if (val > (int32_t)max)
- {
- return max;
- }
- else if (val < 0)
- {
- return 0U;
- }
- }
- return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
-
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32U) ) >> 32U))
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis_armclang.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1869 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_armclang.h
- * @brief CMSIS compiler armclang (Arm Compiler 6) header file
- * @version V5.0.4
- * @date 10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#pragma clang system_header /* treat file as system include file */
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE __inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static __inline
-#endif
-#ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((__noreturn__))
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_UNION
- #define __PACKED_UNION union __attribute__((packed, aligned(1)))
-#endif
-#ifndef __UNALIGNED_UINT32 /* deprecated */
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- #pragma clang diagnostic pop
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef __UNALIGNED_UINT16_WRITE
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
- __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
- #pragma clang diagnostic pop
- #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef __UNALIGNED_UINT16_READ
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
- __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
- #pragma clang diagnostic pop
- #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef __UNALIGNED_UINT32_WRITE
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
- __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
- #pragma clang diagnostic pop
- #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef __UNALIGNED_UINT32_READ
- #pragma clang diagnostic push
- #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
- __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
- #pragma clang diagnostic pop
- #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __RESTRICT
- #define __RESTRICT __restrict
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq(); see arm_compat.h */
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq(); see arm_compat.h */
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
- \return SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
- \param [in] topOfStack Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
- __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq /* see arm_compat.h */
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
- return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
-#else
-#define __get_FPSCR() ((uint32_t)0U)
-#endif
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#define __set_FPSCR __builtin_arm_set_fpscr
-#else
-#define __set_FPSCR(x) ((void)(x))
-#endif
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __builtin_arm_nop
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI __builtin_arm_wfi
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __builtin_arm_wfe
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __builtin_arm_sev
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-#define __ISB() __builtin_arm_isb(0xF);
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __builtin_arm_dsb(0xF);
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __builtin_arm_dmb(0xF);
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV(value) __builtin_bswap32(value)
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV16(value) __ROR(__REV(value), 16)
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REVSH(value) (int16_t)__builtin_bswap16(value)
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- op2 %= 32U;
- if (op2 == 0U)
- {
- return op1;
- }
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __RBIT __builtin_arm_rbit
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ (uint8_t)__builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB (uint8_t)__builtin_arm_ldrex
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH (uint16_t)__builtin_arm_ldrex
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW (uint32_t)__builtin_arm_ldrex
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __builtin_arm_ssat
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __builtin_arm_usat
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
- if ((sat >= 1U) && (sat <= 32U))
- {
- const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
- const int32_t min = -1 - max ;
- if (val > max)
- {
- return max;
- }
- else if (val < min)
- {
- return min;
- }
- }
- return val;
-}
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
- if (sat <= 31U)
- {
- const uint32_t max = ((1U << sat) - 1U);
- if (val > (int32_t)max)
- {
- return max;
- }
- else if (val < 0)
- {
- return 0U;
- }
- }
- return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief Load-Acquire (8 bit)
- \details Executes a LDAB instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire (16 bit)
- \details Executes a LDAH instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire (32 bit)
- \details Executes a LDA instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release (8 bit)
- \details Executes a STLB instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (16 bit)
- \details Executes a STLH instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (32 bit)
- \details Executes a STL instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Load-Acquire Exclusive (8 bit)
- \details Executes a LDAB exclusive instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDAEXB (uint8_t)__builtin_arm_ldaex
-
-
-/**
- \brief Load-Acquire Exclusive (16 bit)
- \details Executes a LDAH exclusive instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDAEXH (uint16_t)__builtin_arm_ldaex
-
-
-/**
- \brief Load-Acquire Exclusive (32 bit)
- \details Executes a LDA exclusive instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDAEX (uint32_t)__builtin_arm_ldaex
-
-
-/**
- \brief Store-Release Exclusive (8 bit)
- \details Executes a STLB exclusive instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEXB (uint32_t)__builtin_arm_stlex
-
-
-/**
- \brief Store-Release Exclusive (16 bit)
- \details Executes a STLH exclusive instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEXH (uint32_t)__builtin_arm_stlex
-
-
-/**
- \brief Store-Release Exclusive (32 bit)
- \details Executes a STL exclusive instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEX (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis_compiler.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,266 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_compiler.h
- * @brief CMSIS compiler generic header file
- * @version V5.0.4
- * @date 10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * Arm Compiler 4/5
- */
-#if defined ( __CC_ARM )
- #include "cmsis_armcc.h"
-
-
-/*
- * Arm Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
- #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
- #include <cmsis_iccarm.h>
-
-
-/*
- * TI Arm Compiler
- */
-#elif defined ( __TI_ARM__ )
- #include <cmsis_ccs.h>
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE __STATIC_INLINE
- #endif
- #ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
- #endif
- #ifndef __USED
- #define __USED __attribute__((used))
- #endif
- #ifndef __WEAK
- #define __WEAK __attribute__((weak))
- #endif
- #ifndef __PACKED
- #define __PACKED __attribute__((packed))
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed))
- #endif
- #ifndef __PACKED_UNION
- #define __PACKED_UNION union __attribute__((packed))
- #endif
- #ifndef __UNALIGNED_UINT32 /* deprecated */
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __UNALIGNED_UINT16_WRITE
- __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
- #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
- #endif
- #ifndef __UNALIGNED_UINT16_READ
- __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
- #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
- #endif
- #ifndef __UNALIGNED_UINT32_WRITE
- __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
- #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
- #endif
- #ifndef __UNALIGNED_UINT32_READ
- __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
- #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
- #endif
- #ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
- #endif
- #ifndef __RESTRICT
- #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
- #define __RESTRICT
- #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
- /*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
- #ifndef __ASM
- #define __ASM __asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE __STATIC_INLINE
- #endif
- #ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((noreturn))
- #endif
- #ifndef __USED
- #define __USED __attribute__((used))
- #endif
- #ifndef __WEAK
- #define __WEAK __attribute__((weak))
- #endif
- #ifndef __PACKED
- #define __PACKED __packed__
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __packed__
- #endif
- #ifndef __PACKED_UNION
- #define __PACKED_UNION union __packed__
- #endif
- #ifndef __UNALIGNED_UINT32 /* deprecated */
- struct __packed__ T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __UNALIGNED_UINT16_WRITE
- __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
- #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
- #endif
- #ifndef __UNALIGNED_UINT16_READ
- __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
- #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
- #endif
- #ifndef __UNALIGNED_UINT32_WRITE
- __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
- #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
- #endif
- #ifndef __UNALIGNED_UINT32_READ
- __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
- #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
- #endif
- #ifndef __ALIGNED
- #define __ALIGNED(x) __align(x)
- #endif
- #ifndef __RESTRICT
- #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
- #define __RESTRICT
- #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
- #include <cmsis_csm.h>
-
- #ifndef __ASM
- #define __ASM _asm
- #endif
- #ifndef __INLINE
- #define __INLINE inline
- #endif
- #ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
- #endif
- #ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE __STATIC_INLINE
- #endif
- #ifndef __NO_RETURN
- // NO RETURN is automatically detected hence no warning here
- #define __NO_RETURN
- #endif
- #ifndef __USED
- #warning No compiler specific solution for __USED. __USED is ignored.
- #define __USED
- #endif
- #ifndef __WEAK
- #define __WEAK __weak
- #endif
- #ifndef __PACKED
- #define __PACKED @packed
- #endif
- #ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT @packed struct
- #endif
- #ifndef __PACKED_UNION
- #define __PACKED_UNION @packed union
- #endif
- #ifndef __UNALIGNED_UINT32 /* deprecated */
- @packed struct T_UINT32 { uint32_t v; };
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
- #endif
- #ifndef __UNALIGNED_UINT16_WRITE
- __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
- #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
- #endif
- #ifndef __UNALIGNED_UINT16_READ
- __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
- #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
- #endif
- #ifndef __UNALIGNED_UINT32_WRITE
- __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
- #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
- #endif
- #ifndef __UNALIGNED_UINT32_READ
- __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
- #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
- #endif
- #ifndef __ALIGNED
- #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
- #define __ALIGNED(x)
- #endif
- #ifndef __RESTRICT
- #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
- #define __RESTRICT
- #endif
-
-
-#else
- #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis_gcc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2085 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_gcc.h
- * @brief CMSIS compiler GCC header file
- * @version V5.0.4
- * @date 09. April 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* Fallback for __has_builtin */
-#ifndef __has_builtin
- #define __has_builtin(x) (0)
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef __ASM
- #define __ASM __asm
-#endif
-#ifndef __INLINE
- #define __INLINE inline
-#endif
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
-#endif
-#ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
-#endif
-#ifndef __NO_RETURN
- #define __NO_RETURN __attribute__((__noreturn__))
-#endif
-#ifndef __USED
- #define __USED __attribute__((used))
-#endif
-#ifndef __WEAK
- #define __WEAK __attribute__((weak))
-#endif
-#ifndef __PACKED
- #define __PACKED __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_STRUCT
- #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef __PACKED_UNION
- #define __PACKED_UNION union __attribute__((packed, aligned(1)))
-#endif
-#ifndef __UNALIGNED_UINT32 /* deprecated */
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- struct __attribute__((packed)) T_UINT32 { uint32_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef __UNALIGNED_UINT16_WRITE
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef __UNALIGNED_UINT16_READ
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef __UNALIGNED_UINT32_WRITE
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef __UNALIGNED_UINT32_READ
- #pragma GCC diagnostic push
- #pragma GCC diagnostic ignored "-Wpacked"
- #pragma GCC diagnostic ignored "-Wattributes"
- __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
- #pragma GCC diagnostic pop
- #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef __ALIGNED
- #define __ALIGNED(x) __attribute__((aligned(x)))
-#endif
-#ifndef __RESTRICT
- #define __RESTRICT __restrict
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
- \return SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
- \param [in] topOfStack Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
- __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-/**
- \brief Get Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Process Stack Pointer (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)ProcStackPtrLimit;
-#else
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always in non-secure
- mode.
-
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
- return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence zero is returned always.
-
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- return 0U;
-#else
- uint32_t result;
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return result;
-#endif
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored in non-secure
- mode.
-
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
- Stack Pointer Limit register hence the write is silently ignored.
-
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)MainStackPtrLimit;
-#else
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_get_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- return __builtin_arm_get_fpscr();
-#else
- uint32_t result;
-
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- return(result);
-#endif
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
-#if __has_builtin(__builtin_arm_set_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
- /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
- __builtin_arm_set_fpscr(fpscr);
-#else
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#endif
-#else
- (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP() __ASM volatile ("nop")
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI() __ASM volatile ("wfi")
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE() __ASM volatile ("wfe")
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV() __ASM volatile ("sev")
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-__STATIC_FORCEINLINE void __ISB(void)
-{
- __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
- __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
- __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return result;
-#endif
-}
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return result;
-}
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (int16_t)__builtin_bswap16(value);
-#else
- int16_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return result;
-#endif
-}
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- op2 %= 32U;
- if (op2 == 0U)
- {
- return op1;
- }
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value != 0U; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return result;
-}
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ (uint8_t)__builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-__STATIC_FORCEINLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] ARG1 Value to be saturated
- \param [in] ARG2 Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-__extension__ \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] ARG1 Value to be saturated
- \param [in] ARG2 Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
- __extension__ \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
- if ((sat >= 1U) && (sat <= 32U))
- {
- const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
- const int32_t min = -1 - max ;
- if (val > max)
- {
- return max;
- }
- else if (val < min)
- {
- return min;
- }
- }
- return val;
-}
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
- if (sat <= 31U)
- {
- const uint32_t max = ((1U << sat) - 1U);
- if (val > (int32_t)max)
- {
- return max;
- }
- else if (val < 0)
- {
- return 0U;
- }
- }
- return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
- (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
- (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-/**
- \brief Load-Acquire (8 bit)
- \details Executes a LDAB instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire (16 bit)
- \details Executes a LDAH instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire (32 bit)
- \details Executes a LDA instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release (8 bit)
- \details Executes a STLB instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (16 bit)
- \details Executes a STLH instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (32 bit)
- \details Executes a STL instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Load-Acquire Exclusive (8 bit)
- \details Executes a LDAB exclusive instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (16 bit)
- \details Executes a LDAH exclusive instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire Exclusive (32 bit)
- \details Executes a LDA exclusive instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (8 bit)
- \details Executes a STLB exclusive instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (16 bit)
- \details Executes a STLH exclusive instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief Store-Release Exclusive (32 bit)
- \details Executes a STL exclusive instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis_iccarm.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,935 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_iccarm.h
- * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version V5.0.7
- * @date 19. June 2018
- ******************************************************************************/
-
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2017-2018 IAR Systems
-//
-// Licensed under the Apache License, Version 2.0 (the "License")
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-// http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-//------------------------------------------------------------------------------
-
-
-#ifndef __CMSIS_ICCARM_H__
-#define __CMSIS_ICCARM_H__
-
-#ifndef __ICCARM__
- #error This file should only be compiled by ICCARM
-#endif
-
-#pragma system_include
-
-#define __IAR_FT _Pragma("inline=forced") __intrinsic
-
-#if (__VER__ >= 8000000)
- #define __ICCARM_V8 1
-#else
- #define __ICCARM_V8 0
-#endif
-
-#ifndef __ALIGNED
- #if __ICCARM_V8
- #define __ALIGNED(x) __attribute__((aligned(x)))
- #elif (__VER__ >= 7080000)
- /* Needs IAR language extensions */
- #define __ALIGNED(x) __attribute__((aligned(x)))
- #else
- #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
- #define __ALIGNED(x)
- #endif
-#endif
-
-
-/* Define compiler macros for CPU architecture, used in CMSIS 5.
- */
-#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
-/* Macros already defined */
-#else
- #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
- #define __ARM_ARCH_8M_MAIN__ 1
- #elif defined(__ARM8M_BASELINE__)
- #define __ARM_ARCH_8M_BASE__ 1
- #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
- #if __ARM_ARCH == 6
- #define __ARM_ARCH_6M__ 1
- #elif __ARM_ARCH == 7
- #if __ARM_FEATURE_DSP
- #define __ARM_ARCH_7EM__ 1
- #else
- #define __ARM_ARCH_7M__ 1
- #endif
- #endif /* __ARM_ARCH */
- #endif /* __ARM_ARCH_PROFILE == 'M' */
-#endif
-
-/* Alternativ core deduction for older ICCARM's */
-#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
- !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
- #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
- #define __ARM_ARCH_6M__ 1
- #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
- #define __ARM_ARCH_7M__ 1
- #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
- #define __ARM_ARCH_7EM__ 1
- #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
- #define __ARM_ARCH_8M_BASE__ 1
- #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
- #define __ARM_ARCH_8M_MAIN__ 1
- #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
- #define __ARM_ARCH_8M_MAIN__ 1
- #else
- #error "Unknown target."
- #endif
-#endif
-
-
-
-#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
- #define __IAR_M0_FAMILY 1
-#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
- #define __IAR_M0_FAMILY 1
-#else
- #define __IAR_M0_FAMILY 0
-#endif
-
-
-#ifndef __ASM
- #define __ASM __asm
-#endif
-
-#ifndef __INLINE
- #define __INLINE inline
-#endif
-
-#ifndef __NO_RETURN
- #if __ICCARM_V8
- #define __NO_RETURN __attribute__((__noreturn__))
- #else
- #define __NO_RETURN _Pragma("object_attribute=__noreturn")
- #endif
-#endif
-
-#ifndef __PACKED
- #if __ICCARM_V8
- #define __PACKED __attribute__((packed, aligned(1)))
- #else
- /* Needs IAR language extensions */
- #define __PACKED __packed
- #endif
-#endif
-
-#ifndef __PACKED_STRUCT
- #if __ICCARM_V8
- #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
- #else
- /* Needs IAR language extensions */
- #define __PACKED_STRUCT __packed struct
- #endif
-#endif
-
-#ifndef __PACKED_UNION
- #if __ICCARM_V8
- #define __PACKED_UNION union __attribute__((packed, aligned(1)))
- #else
- /* Needs IAR language extensions */
- #define __PACKED_UNION __packed union
- #endif
-#endif
-
-#ifndef __RESTRICT
- #define __RESTRICT restrict
-#endif
-
-#ifndef __STATIC_INLINE
- #define __STATIC_INLINE static inline
-#endif
-
-#ifndef __FORCEINLINE
- #define __FORCEINLINE _Pragma("inline=forced")
-#endif
-
-#ifndef __STATIC_FORCEINLINE
- #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
-#endif
-
-#ifndef __UNALIGNED_UINT16_READ
-#pragma language=save
-#pragma language=extended
-__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
-{
- return *(__packed uint16_t*)(ptr);
-}
-#pragma language=restore
-#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
-#endif
-
-
-#ifndef __UNALIGNED_UINT16_WRITE
-#pragma language=save
-#pragma language=extended
-__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
-{
- *(__packed uint16_t*)(ptr) = val;;
-}
-#pragma language=restore
-#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
-#endif
-
-#ifndef __UNALIGNED_UINT32_READ
-#pragma language=save
-#pragma language=extended
-__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
-{
- return *(__packed uint32_t*)(ptr);
-}
-#pragma language=restore
-#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
-#endif
-
-#ifndef __UNALIGNED_UINT32_WRITE
-#pragma language=save
-#pragma language=extended
-__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
-{
- *(__packed uint32_t*)(ptr) = val;;
-}
-#pragma language=restore
-#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
-#endif
-
-#ifndef __UNALIGNED_UINT32 /* deprecated */
-#pragma language=save
-#pragma language=extended
-__packed struct __iar_u32 { uint32_t v; };
-#pragma language=restore
-#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
-#endif
-
-#ifndef __USED
- #if __ICCARM_V8
- #define __USED __attribute__((used))
- #else
- #define __USED _Pragma("__root")
- #endif
-#endif
-
-#ifndef __WEAK
- #if __ICCARM_V8
- #define __WEAK __attribute__((weak))
- #else
- #define __WEAK _Pragma("__weak")
- #endif
-#endif
-
-
-#ifndef __ICCARM_INTRINSICS_VERSION__
- #define __ICCARM_INTRINSICS_VERSION__ 0
-#endif
-
-#if __ICCARM_INTRINSICS_VERSION__ == 2
-
- #if defined(__CLZ)
- #undef __CLZ
- #endif
- #if defined(__REVSH)
- #undef __REVSH
- #endif
- #if defined(__RBIT)
- #undef __RBIT
- #endif
- #if defined(__SSAT)
- #undef __SSAT
- #endif
- #if defined(__USAT)
- #undef __USAT
- #endif
-
- #include "iccarm_builtin.h"
-
- #define __disable_fault_irq __iar_builtin_disable_fiq
- #define __disable_irq __iar_builtin_disable_interrupt
- #define __enable_fault_irq __iar_builtin_enable_fiq
- #define __enable_irq __iar_builtin_enable_interrupt
- #define __arm_rsr __iar_builtin_rsr
- #define __arm_wsr __iar_builtin_wsr
-
-
- #define __get_APSR() (__arm_rsr("APSR"))
- #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
- #define __get_CONTROL() (__arm_rsr("CONTROL"))
- #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
-
- #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
- #define __get_FPSCR() (__arm_rsr("FPSCR"))
- #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
- #else
- #define __get_FPSCR() ( 0 )
- #define __set_FPSCR(VALUE) ((void)VALUE)
- #endif
-
- #define __get_IPSR() (__arm_rsr("IPSR"))
- #define __get_MSP() (__arm_rsr("MSP"))
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- #define __get_MSPLIM() (0U)
- #else
- #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
- #endif
- #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
- #define __get_PSP() (__arm_rsr("PSP"))
-
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- #define __get_PSPLIM() (0U)
- #else
- #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
- #endif
-
- #define __get_xPSR() (__arm_rsr("xPSR"))
-
- #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
- #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
- #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
- #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
- #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
-
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- #define __set_MSPLIM(VALUE) ((void)(VALUE))
- #else
- #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
- #endif
- #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
- #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- #define __set_PSPLIM(VALUE) ((void)(VALUE))
- #else
- #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
- #endif
-
- #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
- #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
- #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
- #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
- #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
- #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
- #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
- #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
- #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
- #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
- #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
- #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
- #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
- #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- #define __TZ_get_PSPLIM_NS() (0U)
- #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
- #else
- #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
- #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
- #endif
-
- #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
- #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
-
- #define __NOP __iar_builtin_no_operation
-
- #define __CLZ __iar_builtin_CLZ
- #define __CLREX __iar_builtin_CLREX
-
- #define __DMB __iar_builtin_DMB
- #define __DSB __iar_builtin_DSB
- #define __ISB __iar_builtin_ISB
-
- #define __LDREXB __iar_builtin_LDREXB
- #define __LDREXH __iar_builtin_LDREXH
- #define __LDREXW __iar_builtin_LDREX
-
- #define __RBIT __iar_builtin_RBIT
- #define __REV __iar_builtin_REV
- #define __REV16 __iar_builtin_REV16
-
- __IAR_FT int16_t __REVSH(int16_t val)
- {
- return (int16_t) __iar_builtin_REVSH(val);
- }
-
- #define __ROR __iar_builtin_ROR
- #define __RRX __iar_builtin_RRX
-
- #define __SEV __iar_builtin_SEV
-
- #if !__IAR_M0_FAMILY
- #define __SSAT __iar_builtin_SSAT
- #endif
-
- #define __STREXB __iar_builtin_STREXB
- #define __STREXH __iar_builtin_STREXH
- #define __STREXW __iar_builtin_STREX
-
- #if !__IAR_M0_FAMILY
- #define __USAT __iar_builtin_USAT
- #endif
-
- #define __WFE __iar_builtin_WFE
- #define __WFI __iar_builtin_WFI
-
- #if __ARM_MEDIA__
- #define __SADD8 __iar_builtin_SADD8
- #define __QADD8 __iar_builtin_QADD8
- #define __SHADD8 __iar_builtin_SHADD8
- #define __UADD8 __iar_builtin_UADD8
- #define __UQADD8 __iar_builtin_UQADD8
- #define __UHADD8 __iar_builtin_UHADD8
- #define __SSUB8 __iar_builtin_SSUB8
- #define __QSUB8 __iar_builtin_QSUB8
- #define __SHSUB8 __iar_builtin_SHSUB8
- #define __USUB8 __iar_builtin_USUB8
- #define __UQSUB8 __iar_builtin_UQSUB8
- #define __UHSUB8 __iar_builtin_UHSUB8
- #define __SADD16 __iar_builtin_SADD16
- #define __QADD16 __iar_builtin_QADD16
- #define __SHADD16 __iar_builtin_SHADD16
- #define __UADD16 __iar_builtin_UADD16
- #define __UQADD16 __iar_builtin_UQADD16
- #define __UHADD16 __iar_builtin_UHADD16
- #define __SSUB16 __iar_builtin_SSUB16
- #define __QSUB16 __iar_builtin_QSUB16
- #define __SHSUB16 __iar_builtin_SHSUB16
- #define __USUB16 __iar_builtin_USUB16
- #define __UQSUB16 __iar_builtin_UQSUB16
- #define __UHSUB16 __iar_builtin_UHSUB16
- #define __SASX __iar_builtin_SASX
- #define __QASX __iar_builtin_QASX
- #define __SHASX __iar_builtin_SHASX
- #define __UASX __iar_builtin_UASX
- #define __UQASX __iar_builtin_UQASX
- #define __UHASX __iar_builtin_UHASX
- #define __SSAX __iar_builtin_SSAX
- #define __QSAX __iar_builtin_QSAX
- #define __SHSAX __iar_builtin_SHSAX
- #define __USAX __iar_builtin_USAX
- #define __UQSAX __iar_builtin_UQSAX
- #define __UHSAX __iar_builtin_UHSAX
- #define __USAD8 __iar_builtin_USAD8
- #define __USADA8 __iar_builtin_USADA8
- #define __SSAT16 __iar_builtin_SSAT16
- #define __USAT16 __iar_builtin_USAT16
- #define __UXTB16 __iar_builtin_UXTB16
- #define __UXTAB16 __iar_builtin_UXTAB16
- #define __SXTB16 __iar_builtin_SXTB16
- #define __SXTAB16 __iar_builtin_SXTAB16
- #define __SMUAD __iar_builtin_SMUAD
- #define __SMUADX __iar_builtin_SMUADX
- #define __SMMLA __iar_builtin_SMMLA
- #define __SMLAD __iar_builtin_SMLAD
- #define __SMLADX __iar_builtin_SMLADX
- #define __SMLALD __iar_builtin_SMLALD
- #define __SMLALDX __iar_builtin_SMLALDX
- #define __SMUSD __iar_builtin_SMUSD
- #define __SMUSDX __iar_builtin_SMUSDX
- #define __SMLSD __iar_builtin_SMLSD
- #define __SMLSDX __iar_builtin_SMLSDX
- #define __SMLSLD __iar_builtin_SMLSLD
- #define __SMLSLDX __iar_builtin_SMLSLDX
- #define __SEL __iar_builtin_SEL
- #define __QADD __iar_builtin_QADD
- #define __QSUB __iar_builtin_QSUB
- #define __PKHBT __iar_builtin_PKHBT
- #define __PKHTB __iar_builtin_PKHTB
- #endif
-
-#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
-
- #if __IAR_M0_FAMILY
- /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
- #define __CLZ __cmsis_iar_clz_not_active
- #define __SSAT __cmsis_iar_ssat_not_active
- #define __USAT __cmsis_iar_usat_not_active
- #define __RBIT __cmsis_iar_rbit_not_active
- #define __get_APSR __cmsis_iar_get_APSR_not_active
- #endif
-
-
- #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
- #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
- #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
- #endif
-
- #ifdef __INTRINSICS_INCLUDED
- #error intrinsics.h is already included previously!
- #endif
-
- #include <intrinsics.h>
-
- #if __IAR_M0_FAMILY
- /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
- #undef __CLZ
- #undef __SSAT
- #undef __USAT
- #undef __RBIT
- #undef __get_APSR
-
- __STATIC_INLINE uint8_t __CLZ(uint32_t data)
- {
- if (data == 0U) { return 32U; }
-
- uint32_t count = 0U;
- uint32_t mask = 0x80000000U;
-
- while ((data & mask) == 0U)
- {
- count += 1U;
- mask = mask >> 1U;
- }
- return count;
- }
-
- __STATIC_INLINE uint32_t __RBIT(uint32_t v)
- {
- uint8_t sc = 31U;
- uint32_t r = v;
- for (v >>= 1U; v; v >>= 1U)
- {
- r <<= 1U;
- r |= v & 1U;
- sc--;
- }
- return (r << sc);
- }
-
- __STATIC_INLINE uint32_t __get_APSR(void)
- {
- uint32_t res;
- __asm("MRS %0,APSR" : "=r" (res));
- return res;
- }
-
- #endif
-
- #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
- (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
- #undef __get_FPSCR
- #undef __set_FPSCR
- #define __get_FPSCR() (0)
- #define __set_FPSCR(VALUE) ((void)VALUE)
- #endif
-
- #pragma diag_suppress=Pe940
- #pragma diag_suppress=Pe177
-
- #define __enable_irq __enable_interrupt
- #define __disable_irq __disable_interrupt
- #define __NOP __no_operation
-
- #define __get_xPSR __get_PSR
-
- #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
-
- __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
- {
- return __LDREX((unsigned long *)ptr);
- }
-
- __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
- {
- return __STREX(value, (unsigned long *)ptr);
- }
- #endif
-
-
- /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
- #if (__CORTEX_M >= 0x03)
-
- __IAR_FT uint32_t __RRX(uint32_t value)
- {
- uint32_t result;
- __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
- return(result);
- }
-
- __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
- {
- __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
- }
-
-
- #define __enable_fault_irq __enable_fiq
- #define __disable_fault_irq __disable_fiq
-
-
- #endif /* (__CORTEX_M >= 0x03) */
-
- __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
- {
- return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
- }
-
- #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
- __IAR_FT uint32_t __get_MSPLIM(void)
- {
- uint32_t res;
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- res = 0U;
- #else
- __asm volatile("MRS %0,MSPLIM" : "=r" (res));
- #endif
- return res;
- }
-
- __IAR_FT void __set_MSPLIM(uint32_t value)
- {
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure MSPLIM is RAZ/WI
- (void)value;
- #else
- __asm volatile("MSR MSPLIM,%0" :: "r" (value));
- #endif
- }
-
- __IAR_FT uint32_t __get_PSPLIM(void)
- {
- uint32_t res;
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- res = 0U;
- #else
- __asm volatile("MRS %0,PSPLIM" : "=r" (res));
- #endif
- return res;
- }
-
- __IAR_FT void __set_PSPLIM(uint32_t value)
- {
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)value;
- #else
- __asm volatile("MSR PSPLIM,%0" :: "r" (value));
- #endif
- }
-
- __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
- return res;
- }
-
- __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
- {
- __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
- }
-
- __IAR_FT uint32_t __TZ_get_PSP_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,PSP_NS" : "=r" (res));
- return res;
- }
-
- __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
- {
- __asm volatile("MSR PSP_NS,%0" :: "r" (value));
- }
-
- __IAR_FT uint32_t __TZ_get_MSP_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,MSP_NS" : "=r" (res));
- return res;
- }
-
- __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
- {
- __asm volatile("MSR MSP_NS,%0" :: "r" (value));
- }
-
- __IAR_FT uint32_t __TZ_get_SP_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,SP_NS" : "=r" (res));
- return res;
- }
- __IAR_FT void __TZ_set_SP_NS(uint32_t value)
- {
- __asm volatile("MSR SP_NS,%0" :: "r" (value));
- }
-
- __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
- return res;
- }
-
- __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
- {
- __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
- }
-
- __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
- return res;
- }
-
- __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
- {
- __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
- }
-
- __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
- return res;
- }
-
- __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
- {
- __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
- }
-
- __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
- {
- uint32_t res;
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- res = 0U;
- #else
- __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
- #endif
- return res;
- }
-
- __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
- {
- #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
- (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
- // without main extensions, the non-secure PSPLIM is RAZ/WI
- (void)value;
- #else
- __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
- #endif
- }
-
- __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
- {
- uint32_t res;
- __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
- return res;
- }
-
- __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
- {
- __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
- }
-
- #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
-
-#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
-
-#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
-
-#if __IAR_M0_FAMILY
- __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
- {
- if ((sat >= 1U) && (sat <= 32U))
- {
- const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
- const int32_t min = -1 - max ;
- if (val > max)
- {
- return max;
- }
- else if (val < min)
- {
- return min;
- }
- }
- return val;
- }
-
- __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
- {
- if (sat <= 31U)
- {
- const uint32_t max = ((1U << sat) - 1U);
- if (val > (int32_t)max)
- {
- return max;
- }
- else if (val < 0)
- {
- return 0U;
- }
- }
- return (uint32_t)val;
- }
-#endif
-
-#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
-
- __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
- {
- uint32_t res;
- __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
- return ((uint8_t)res);
- }
-
- __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
- {
- uint32_t res;
- __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
- return ((uint16_t)res);
- }
-
- __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
- {
- uint32_t res;
- __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
- return res;
- }
-
- __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
- {
- __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
- }
-
- __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
- {
- __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
- }
-
- __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
- {
- __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
- }
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
- (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
-
-
- __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
- return ((uint8_t)res);
- }
-
- __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
- return ((uint16_t)res);
- }
-
- __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
- return res;
- }
-
- __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
- {
- __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
- }
-
- __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
- {
- __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
- }
-
- __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
- {
- __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
- }
-
- __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
- return ((uint8_t)res);
- }
-
- __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
- return ((uint16_t)res);
- }
-
- __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
- return res;
- }
-
- __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
- return res;
- }
-
- __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
- return res;
- }
-
- __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
- {
- uint32_t res;
- __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
- return res;
- }
-
-#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
-
-#undef __IAR_FT
-#undef __IAR_M0_FAMILY
-#undef __ICCARM_V8
-
-#pragma diag_default=Pe940
-#pragma diag_default=Pe177
-
-#endif /* __CMSIS_ICCARM_H__ */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis_nvic.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,40 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2016, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -// CORE: 16 vectors (= 64 bytes from 0x00 to 0x3F) -// MCU Peripherals: 43 vectors (= 172 bytes from 0x40 to 0xEB) -// Total: 236 bytes to be reserved in RAM (see scatter file) -#define NVIC_NUM_VECTORS (16 + 43) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM - -#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/cmsis_version.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 - ******************************************************************************/ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/common_objects.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,140 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_COMMON_OBJECTS_H
-#define MBED_COMMON_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct pwmout_s {
- PWMName pwm;
- PinName pin;
- uint32_t prescaler;
- uint32_t period;
- uint32_t pulse;
- uint8_t channel;
- uint8_t inverted;
-};
-
-struct serial_s {
- UARTName uart;
- int index; // Used by irq
- uint32_t baudrate;
- uint32_t databits;
- uint32_t stopbits;
- uint32_t parity;
- PinName pin_tx;
- PinName pin_rx;
-#if DEVICE_SERIAL_ASYNCH
- uint32_t events;
-#endif
-#if DEVICE_SERIAL_FC
- uint32_t hw_flow_ctl;
- PinName pin_rts;
- PinName pin_cts;
-#endif
-};
-
-struct spi_s {
- SPI_HandleTypeDef handle;
- IRQn_Type spiIRQ;
- SPIName spi;
- PinName pin_miso;
- PinName pin_mosi;
- PinName pin_sclk;
- PinName pin_ssel;
-#if DEVICE_SPI_ASYNCH
- uint32_t event;
- uint8_t transfer_type;
-#endif
-};
-
-struct i2c_s {
- /* The 1st 2 members I2CName i2c
- * and I2C_HandleTypeDef handle should
- * be kept as the first members of this struct
- * to ensure i2c_get_obj to work as expected
- */
- I2CName i2c;
- I2C_HandleTypeDef handle;
- uint8_t index;
- int hz;
- PinName sda;
- PinName scl;
- IRQn_Type event_i2cIRQ;
- IRQn_Type error_i2cIRQ;
- uint32_t XferOperation;
- volatile uint8_t event;
-#if DEVICE_I2CSLAVE
- uint8_t slave;
- volatile uint8_t pending_slave_tx_master_rx;
- volatile uint8_t pending_slave_rx_maxter_tx;
-#endif
-#if DEVICE_I2C_ASYNCH
- uint32_t address;
- uint8_t stop;
- uint8_t available_events;
-#endif
-};
-
-struct analogin_s {
- ADC_HandleTypeDef handle;
- PinName pin;
- uint8_t channel;
-};
-
-#if DEVICE_CAN
-struct can_s {
- CAN_HandleTypeDef CanHandle;
- int index;
- int hz;
-};
-#endif
-
-#if DEVICE_FLASH
-struct flash_s {
- /* nothing to be stored for now */
- uint32_t dummy;
-};
-#endif
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_armv8mbl.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1918 +0,0 @@
-/**************************************************************************//**
- * @file core_armv8mbl.h
- * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
- * @version V5.0.7
- * @date 22. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MBL_H_GENERIC
-#define __CORE_ARMV8MBL_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_ARMv8MBL
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS definitions */
-#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
- __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M ( 2U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT
-#define __CORE_ARMV8MBL_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __ARMv8MBL_REV
- #define __ARMv8MBL_REV 0x0000U
- #warning "__ARMv8MBL_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0U
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-
- #ifndef __ETM_PRESENT
- #define __ETM_PRESENT 0U
- #warning "__ETM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MTB_PRESENT
- #define __MTB_PRESENT 0U
- #warning "__MTB_PRESENT not defined in device header file; using default!"
- #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- uint32_t RESERVED0[6U];
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
- uint32_t RESERVED3[809U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
- uint32_t RESERVED4[4U];
- __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI Periodic Synchronization Control Register Definitions */
-#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
-#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
-
-/* TPI Software Lock Status Register Definitions */
-#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
-#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
-
-#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
-#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
-
-#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
-#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
-#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- uint32_t RESERVED0[7U];
- union {
- __IOM uint32_t MAIR[2];
- struct {
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
- };
- };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
-#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
-#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
-#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
-#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
-#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
-#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
-#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
-#else
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
-#endif
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping() (0U)
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- If VTOR is not present address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_armv8mml.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2927 +0,0 @@
-/**************************************************************************//**
- * @file core_armv8mml.h
- * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
- * @version V5.0.7
- * @date 06. July 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MML_H_GENERIC
-#define __CORE_ARMV8MML_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_ARMv8MML
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS Armv8MML definitions */
-#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
- __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (81U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined(__ARM_FEATURE_DSP)
- #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined(__ARM_FEATURE_DSP)
- #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined(__ARM_FEATURE_DSP)
- #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined(__ARM_FEATURE_DSP)
- #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MML_H_DEPENDANT
-#define __CORE_ARMV8MML_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __ARMv8MML_REV
- #define __ARMv8MML_REV 0x0000U
- #warning "__ARMv8MML_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DSP_PRESENT
- #define __DSP_PRESENT 0U
- #warning "__DSP_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
- uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
- uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED6[580U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
- __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
- uint32_t RESERVED6[4U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
- uint32_t RESERVED32[934U];
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
- uint32_t RESERVED33[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
- uint32_t RESERVED3[809U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */
- uint32_t RESERVED4[4U];
- __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI Periodic Synchronization Control Register Definitions */
-#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */
-#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */
-
-/* TPI Software Lock Status Register Definitions */
-#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */
-#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */
-
-#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */
-#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */
-
-#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */
-#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */
-#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
- __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
- __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
- __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
- uint32_t RESERVED0[1];
- union {
- __IOM uint32_t MAIR[2];
- struct {
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
- };
- };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#else
- uint32_t RESERVED0[3];
-#endif
- __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
- __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
- #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
- #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
-#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
-#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
-#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
-#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
-#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
-#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
-#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
-#else
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
-#endif
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Priority Grouping (non-secure)
- \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB_NS->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB_NS->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping (non-secure)
- \details Reads the priority grouping field from the non-secure NVIC when in secure state.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
- return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm0.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,949 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V5.0.5
- * @date 28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M0
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
- __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (0U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000U
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping() (0U)
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- Address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)0x0U;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)0x0U;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm0plus.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1083 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0plus.h
- * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V5.0.6
- * @date 28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex-M0+
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
- __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (0U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0PLUS_REV
- #define __CM0PLUS_REV 0x0000U
- #warning "__CM0PLUS_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0U
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the Cortex-M0+ header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping() (0U)
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- If VTOR is not present address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm1.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,976 +0,0 @@
-/**************************************************************************//**
- * @file core_cm1.h
- * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
- * @version V1.0.0
- * @date 23. July 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM1_H_GENERIC
-#define __CORE_CM1_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M1
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM1 definitions */
-#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
- __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (1U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM1_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM1_H_DEPENDANT
-#define __CORE_CM1_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM1_REV
- #define __CM1_REV 0x0100U
- #warning "__CM1_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M1 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
-#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
-
-#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
-#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the Cortex-M1 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping() (0U)
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- Address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)0x0U;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)0x0U;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM1_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm23.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1993 +0,0 @@
-/**************************************************************************//**
- * @file core_cm23.h
- * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version V5.0.7
- * @date 22. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM23_H_GENERIC
-#define __CORE_CM23_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M23
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS definitions */
-#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
- __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (23U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM23_H_DEPENDANT
-#define __CORE_CM23_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM23_REV
- #define __CM23_REV 0x0000U
- #warning "__CM23_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0U
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-
- #ifndef __ETM_PRESENT
- #define __ETM_PRESENT 0U
- #warning "__ETM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MTB_PRESENT
- #define __MTB_PRESENT 0U
- #warning "__MTB_PRESENT not defined in device header file; using default!"
- #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M23 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- uint32_t RESERVED0[6U];
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
- __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
- __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
- __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 2 Register Definitions */
-#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
-#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
-#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
-#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
-
-#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
-#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
-
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 0 Definitions */
-#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
-#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
-#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
-#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
-
-#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
-#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
-#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- uint32_t RESERVED0[7U];
- union {
- __IOM uint32_t MAIR[2];
- struct {
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
- };
- };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
-#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
-#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
-#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
-#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
-#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
-#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
-#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
-#else
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
-#endif
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping() (0U)
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- If VTOR is not present address 0 must be mapped to SRAM.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
- uint32_t *vectors = (uint32_t *)0x0U;
-#endif
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm3.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1942 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V5.0.8
- * @date 04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M3
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
- __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (3U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM3_REV
- #define __CM3_REV 0x0200U
- #warning "__CM3_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-#else
- uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-#endif
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm33.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,3002 +0,0 @@
-/**************************************************************************//**
- * @file core_cm33.h
- * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version V5.0.9
- * @date 06. July 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM33_H_GENERIC
-#define __CORE_CM33_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M33
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
- __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (33U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined (__TARGET_FPU_VFP)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined (__ARM_FP)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined (__ARMVFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
- #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
- #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
- #define __DSP_USED 1U
- #else
- #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
- #define __DSP_USED 0U
- #endif
- #else
- #define __DSP_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined (__TI_VFP_SUPPORT__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined (__FPU_VFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM33_H_DEPENDANT
-#define __CORE_CM33_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM33_REV
- #define __CM33_REV 0x0000U
- #warning "__CM33_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __SAUREGION_PRESENT
- #define __SAUREGION_PRESENT 0U
- #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DSP_PRESENT
- #define __DSP_PRESENT 0U
- #warning "__DSP_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M33 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core SAU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
- uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
- uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
- uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[16U];
- __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[16U];
- __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[16U];
- __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[16U];
- __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[16U];
- __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
- uint32_t RESERVED5[16U];
- __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED6[580U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
- uint32_t RESERVED3[92U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
- __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
- uint32_t RESERVED6[4U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- uint32_t RESERVED3[1U];
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED4[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- uint32_t RESERVED5[1U];
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED6[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- uint32_t RESERVED7[1U];
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED8[1U];
- __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
- uint32_t RESERVED9[1U];
- __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
- uint32_t RESERVED10[1U];
- __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
- uint32_t RESERVED11[1U];
- __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
- uint32_t RESERVED12[1U];
- __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
- uint32_t RESERVED13[1U];
- __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
- uint32_t RESERVED14[1U];
- __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
- uint32_t RESERVED15[1U];
- __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
- uint32_t RESERVED16[1U];
- __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
- uint32_t RESERVED17[1U];
- __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
- uint32_t RESERVED18[1U];
- __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
- uint32_t RESERVED19[1U];
- __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
- uint32_t RESERVED20[1U];
- __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
- uint32_t RESERVED21[1U];
- __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
- uint32_t RESERVED22[1U];
- __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
- uint32_t RESERVED23[1U];
- __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
- uint32_t RESERVED24[1U];
- __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
- uint32_t RESERVED25[1U];
- __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
- uint32_t RESERVED26[1U];
- __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
- uint32_t RESERVED27[1U];
- __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
- uint32_t RESERVED28[1U];
- __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
- uint32_t RESERVED29[1U];
- __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
- uint32_t RESERVED30[1U];
- __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
- uint32_t RESERVED31[1U];
- __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
- uint32_t RESERVED32[934U];
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
- uint32_t RESERVED33[1U];
- __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
- __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
- __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
- __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 2 Register Definitions */
-#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
-#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
-#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
-#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
-
-#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
-#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
-
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 0 Definitions */
-#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
-#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
-#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
-#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
-
-#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
-#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
-#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
- __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
- __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
- __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
- uint32_t RESERVED0[1];
- union {
- __IOM uint32_t MAIR[2];
- struct {
- __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
- __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
- };
- };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SAU Security Attribution Unit (SAU)
- \brief Type definitions for the Security Attribution Unit (SAU)
- @{
- */
-
-/**
- \brief Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
- __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
- __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
-#else
- uint32_t RESERVED0[3];
-#endif
- __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
- __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
- uint32_t RESERVED4[1U];
- __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
- __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
- #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
- #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
- #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
- #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
- #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
- #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
- #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
- #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
- #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
- #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
- #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
- #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
- #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
- #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
- #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
- #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
- #endif
-
- #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
- #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
- #endif
-
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
- #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
- #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
- #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
- #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
- #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
-
- #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
- #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
- #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
- #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
- #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
-
- #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
- #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
- #endif
-
- #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
- #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
-#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
-#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
-#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
-#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
-#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
-#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
-#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
-#else
-#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
-#endif
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Interrupt Target State
- \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- \return 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Target State
- \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Clear Interrupt Target State
- \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 if interrupt is assigned to Secure
- 1 if interrupt is assigned to Non Secure
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
- return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Priority Grouping (non-secure)
- \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB_NS->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- SCB_NS->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping (non-secure)
- \details Reads the priority grouping field from the non-secure NVIC when in secure state.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
- return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt (non-secure)
- \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status (non-secure)
- \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt (non-secure)
- \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Pending Interrupt (non-secure)
- \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt (non-secure)
- \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt (non-secure)
- \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt (non-secure)
- \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority (non-secure)
- \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority (non-secure)
- \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## SAU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SAUFunctions SAU Functions
- \brief Functions that configure the SAU.
- @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
- \brief Enable SAU
- \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
- SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
- \brief Disable SAU
- \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
- SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief System Tick Configuration (non-secure)
- \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm4.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2129 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V5.0.8
- * @date 04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M4
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (4U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000U
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
-#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
-#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
-#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = FPU->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_cm7.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2671 +0,0 @@
-/**************************************************************************//**
- * @file core_cm7.h
- * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version V5.0.8
- * @date 04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M7
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
- __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M (7U) /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM7_REV
- #define __CM7_REV 0x0000U
- #warning "__CM7_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __ICACHE_PRESENT
- #define __ICACHE_PRESENT 0U
- #warning "__ICACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DCACHE_PRESENT
- #define __DCACHE_PRESENT 0U
- #warning "__DCACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DTCM_PRESENT
- #define __DTCM_PRESENT 0U
- #warning "__DTCM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[1U];
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- uint32_t RESERVED3[93U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED3[981U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES 4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
-#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
-#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
-#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ########################## MPU functions #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = SCB->MVFR0;
- if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
- {
- return 2U; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
- {
- return 1U; /* Single precision FPU */
- }
- else
- {
- return 0U; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## Cache functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_CacheFunctions Cache Functions
- \brief Functions that configure Instruction and Data cache.
- @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
-
-
-/**
- \brief Enable I-Cache
- \details Turns on I-Cache
- */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */
- __DSB();
- __ISB();
- SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Disable I-Cache
- \details Turns off I-Cache
- */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Invalidate I-Cache
- \details Invalidates I-Cache
- */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
- #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0UL;
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Enable D-Cache
- \details Turns on D-Cache
- */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
- __DSB();
-
- SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Disable D-Cache
- \details Turns off D-Cache
- */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean & invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Invalidate D-Cache
- \details Invalidates D-Cache
- */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Clean D-Cache
- \details Cleans D-Cache
- */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
- ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Clean & Invalidate D-Cache
- \details Cleans and Invalidates D-Cache
- */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean & invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways-- != 0U);
- } while(sets-- != 0U);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Invalidate by address
- \details Invalidates D-Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t)addr;
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCIMVAC = op_addr;
- op_addr += (uint32_t)linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Clean by address
- \details Cleans D-Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t) addr;
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCCMVAC = op_addr;
- op_addr += (uint32_t)linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Clean and Invalidate by address
- \details Cleans and invalidates D_Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t) addr;
- int32_t linesize = 32; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCCIMVAC = op_addr;
- op_addr += (uint32_t)linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_sc000.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1022 +0,0 @@
-/**************************************************************************//**
- * @file core_sc000.h
- * @brief CMSIS SC000 Core Peripheral Access Layer Header File
- * @version V5.0.5
- * @date 28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup SC000
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
- __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_SC (000U) /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC000_REV
- #define __SC000_REV 0x0000U
- #warning "__SC000_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- uint32_t RESERVED1[154U];
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the SC000 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
-/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/core_sc300.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1915 +0,0 @@
-/**************************************************************************//**
- * @file core_sc300.h
- * @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V5.0.6
- * @date 04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup SC3000
- @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
- __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_SC (300U) /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_FP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TI_ARM__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC300_REV
- #define __SC300_REV 0x0000U
- #warning "__SC300_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:1; /*!< bit: 9 Reserved */
- uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
- uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit */
- uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- uint32_t RESERVED1[129U];
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- uint32_t RESERVED1[1U];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
- #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
- #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
- #endif
- #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
- #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
- #define NVIC_EnableIRQ __NVIC_EnableIRQ
- #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
- #define NVIC_DisableIRQ __NVIC_DisableIRQ
- #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
- #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
- #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
- #define NVIC_GetActive __NVIC_GetActive
- #define NVIC_SetPriority __NVIC_SetPriority
- #define NVIC_GetPriority __NVIC_GetPriority
- #define NVIC_SystemReset __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
- #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
- #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
- #endif
- #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
- #define NVIC_SetVector __NVIC_SetVector
- #define NVIC_GetVector __NVIC_GetVector
-#endif /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET 16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
-#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
-#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
-
-
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable Interrupt
- \details Enables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Interrupt Enable status
- \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt is not enabled.
- \return 1 Interrupt is enabled.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Disable Interrupt
- \details Disables a device specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- __DSB();
- __ISB();
- }
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
- \param [in] IRQn Device specific interrupt number.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- }
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
- \param [in] IRQn Device specific interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- \note IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
- }
- else
- {
- return(0U);
- }
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- \note The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) >= 0)
- {
- NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of a device specific interrupt or a processor exception.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) >= 0)
- {
- return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief Set Interrupt Vector
- \details Sets an interrupt vector in SRAM based interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- VTOR must been relocated to SRAM before.
- \param [in] IRQn Interrupt number
- \param [in] vector Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
- \brief Get Interrupt Vector
- \details Reads an interrupt vector from interrupt vector table.
- The interrupt number can be positive to specify a device specific interrupt,
- or negative to specify a processor exception.
- \param [in] IRQn Interrupt number.
- \return Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- return 0U; /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/device.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,42 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2014, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -//======================================= -#define DEVICE_ID_LENGTH 24 - -#include "objects.h" -/* WORKAROUND waiting for mbed-os issue 4408 to be addressed */ -#include "stm32f1xx_ll_usart.h" - -#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/except.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/flash_api.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/gpio_api.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/gpio_irq_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/gpio_irq_device.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2017, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_IRQ_DEVICE_H
-#define MBED_GPIO_IRQ_DEVICE_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "stm32f1xx_ll_exti.h"
-
-// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
-#define CHANNEL_NUM (7)
-
-#define EXTI_IRQ0_NUM_LINES 1
-#define EXTI_IRQ1_NUM_LINES 1
-#define EXTI_IRQ2_NUM_LINES 1
-#define EXTI_IRQ3_NUM_LINES 1
-#define EXTI_IRQ4_NUM_LINES 1
-#define EXTI_IRQ5_NUM_LINES 5
-#define EXTI_IRQ6_NUM_LINES 6
-
-// Max pins for one line (max with EXTI10_15)
-#define MAX_PIN_LINE (EXTI_IRQ6_NUM_LINES)
-
-/* Structure to describe how the HW EXTI lines are defined in this HW */
-typedef struct exti_lines {
- uint32_t gpio_idx; // an index entry for each EXIT line
- uint32_t irq_index; // the IRQ index
- IRQn_Type irq_n; // the corresponding EXTI IRQn
-} exti_lines_t;
-
-// Used to return the index for channels array.
-extern const exti_lines_t pin_lines_desc[];
-
-/* In F1 family target, SYSCFG is named AFIO */
-#define SYSCFG AFIO
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/gpio_irq_device.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/gpio_object.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Note: reg_clr might actually be same as reg_set.
- * Depends on family whether BRR is available on top of BSRR
- * if BRR does not exist, family shall define GPIO_IP_WITHOUT_BRR
- */
-typedef struct {
- uint32_t mask;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_set;
- __IO uint32_t *reg_clr;
- PinName pin;
- GPIO_TypeDef *gpio;
- uint32_t ll_pin;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
- if (value) {
- *obj->reg_set = obj->mask;
- } else {
-#ifdef GPIO_IP_WITHOUT_BRR
- *obj->reg_clr = obj->mask << 16;
-#else
- *obj->reg_clr = obj->mask;
-#endif
- }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
- return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj)
-{
- return obj->pin != (PinName)NC;
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/hal_tick_overrides.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/i2c_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/i2c_device.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_I2C_DEVICE_H
-#define MBED_I2C_DEVICE_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_I2C
-
-/* Define IP version */
-#define I2C_IP_VERSION_V1
-
-#define I2C_IT_ALL (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR)
-
-#endif // DEVICE_I2C
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/libmbed.a has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/lp_ticker.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_board.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_cmsis_conf.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2012 ARM Limited - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE - * SOFTWARE. - */ -#ifndef MBED_CMSIS_CONF_H -#define MBED_CMSIS_CONF_H - -#ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE -#define MBED_CONF_TZ_PROCESS_STACK_SIZE 512 -#endif -#ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS -#define MBED_CONF_TZ_PROCESS_STACK_SLOTS 8 -#endif - -#define TZ_PROCESS_STACK_SLOTS MBED_CONF_TZ_PROCESS_STACK_SLOTS -#define TZ_PROCESS_STACK_SIZE MBED_CONF_TZ_PROCESS_STACK_SIZE - -#endif /* MBED_CMSIS_CONF_H */
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_crc_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_fault_handler.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_FAULT_HANDLER_H
-#define MBED_FAULT_HANDLER_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-//Fault context struct
-//WARNING: DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES in except.S files.
-//Offset of these registers are used by fault handler in except.S
-typedef struct {
- uint32_t R0_reg;
- uint32_t R1_reg;
- uint32_t R2_reg;
- uint32_t R3_reg;
- uint32_t R4_reg;
- uint32_t R5_reg;
- uint32_t R6_reg;
- uint32_t R7_reg;
- uint32_t R8_reg;
- uint32_t R9_reg;
- uint32_t R10_reg;
- uint32_t R11_reg;
- uint32_t R12_reg;
- uint32_t SP_reg;
- uint32_t LR_reg;
- uint32_t PC_reg;
- uint32_t xPSR;
- uint32_t PSP;
- uint32_t MSP;
- uint32_t EXC_RETURN;
- uint32_t CONTROL;
-} mbed_fault_context_t;
-
-//Fault type definitions
-//WARNING: DO NOT CHANGE THESE VALUES WITHOUT MAKING CORRESPONDING CHANGES in except.S files.
-#define HARD_FAULT_EXCEPTION (0x10) //Keep some gap between values for any future insertion/expansion
-#define MEMMANAGE_FAULT_EXCEPTION (0x20)
-#define BUS_FAULT_EXCEPTION (0x30)
-#define USAGE_FAULT_EXCEPTION (0x40)
-
-//This is a handler function called from Fault handler to print the error information out.
-//This runs in fault context and uses special functions(defined in mbed_fault_handler.c) to print the information without using C-lib support.
-void mbed_fault_handler (uint32_t fault_type, void *mbed_fault_context_in);
-
-/**
- * Call this function to retrieve the fault context after a fatal exception which triggered a system reboot. The function retrieves the fault context stored in crash-report ram area which is preserved over reboot.
- * @param fault_context Pointer to mbed_fault_context_t struct allocated by the caller. This is the mbed_fault_context_t info captured as part of the fatal exception which triggered the reboot.
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_INVALID_ARGUMENT in case of invalid error_info pointer
- * MBED_ERROR_ITEM_NOT_FOUND if no reboot context is currently captured by teh system
- *
- */
-mbed_error_status_t mbed_get_reboot_fault_context (mbed_fault_context_t *fault_context);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_fault_handler.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_lib.json Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,204 +0,0 @@
-{
- "name": "platform",
- "config": {
- "stdio-convert-newlines": {
- "help": "Enable conversion to standard newlines on stdin/stdout/stderr",
- "value": false
- },
-
- "stdio-convert-tty-newlines": {
- "help": "Enable conversion to standard newlines on any tty FILE stream",
- "value": false
- },
-
- "stdio-buffered-serial": {
- "help": "Use UARTSerial driver to obtain buffered serial I/O on stdin/stdout/stderr. If false, unbuffered serial_getc and serial_putc are used directly.",
- "value": false
- },
-
- "stdio-baud-rate": {
- "help": "Baud rate for stdio",
- "value": 9600
- },
-
- "stdio-flush-at-exit": {
- "help": "Enable or disable the flush of standard I/O's at exit.",
- "value": true
- },
-
- "default-serial-baud-rate": {
- "help": "Default baud rate for a Serial or RawSerial instance (if not specified in the constructor)",
- "value": 9600
- },
-
- "force-non-copyable-error": {
- "help": "Force compile time error when a NonCopyable object is copied",
- "value": false
- },
-
- "poll-use-lowpower-timer": {
- "help": "Enable use of low power timer class for poll(). May cause missing events.",
- "value": false
- },
-
- "error-hist-enabled": {
- "help": "Enable for error history tracking.",
- "value": false
- },
-
- "error-hist-size": {
- "help": "Set the number of most recent errors the system keeps in its history, needs error-hist-enabled set to true for this to work.",
- "value": 4
- },
-
- "error-filename-capture-enabled": {
- "help": "Enables capture of filename and line number as part of error context capture, this works only for debug and develop builds. On release builds, filename capture is always disabled",
- "value": false
- },
-
- "error-all-threads-info": {
- "help": "Reports all the threads in the system as part of error report.",
- "value": false
- },
-
- "max-error-filename-len": {
- "help": "Sets the maximum length of buffer used for capturing the filename in error context. This needs error-filename-capture-enabled feature.",
- "value": 16
- },
-
- "memory-tracing-enabled": {
- "macro_name": "MBED_MEM_TRACING_ENABLED",
- "help": "Enable tracing of each memory call by invoking a callback on each memory operation. See mbed_mem_trace.h in the HAL API for more information",
- "value": null
- },
-
- "all-stats-enabled": {
- "macro_name": "MBED_ALL_STATS_ENABLED",
- "help": "Set to 1 to enable all platform stats. When enabled the functions mbed_stats_*_get returns non-zero data. See mbed_stats.h for more information",
- "value": null
- },
-
- "sys-stats-enabled": {
- "macro_name": "MBED_SYS_STATS_ENABLED",
- "help": "Set to 1 to enable system stats. When enabled the function mbed_stats_sys_get returns non-zero data. See mbed_stats.h for more information",
- "value": null
- },
-
- "stack-stats-enabled": {
- "macro_name": "MBED_STACK_STATS_ENABLED",
- "help": "Set to 1 to enable stack stats. When enabled the functions mbed_stats_stack_get and mbed_stats_stack_get_each return non-zero data. See mbed_stats.h for more information",
- "value": null
- },
-
- "cpu-stats-enabled": {
- "macro_name": "MBED_CPU_STATS_ENABLED",
- "help": "Set to 1 to enable cpu stats. When enabled the function mbed_stats_cpu_get returns non-zero data. See mbed_stats.h for more information",
- "value": null
- },
-
- "heap-stats-enabled": {
- "macro_name": "MBED_HEAP_STATS_ENABLED",
- "help": "Set to 1 to enable heap stats. When enabled the function mbed_stats_heap_get returns non-zero data. See mbed_stats.h for more information",
- "value": null
- },
-
- "thread-stats-enabled": {
- "macro_name": "MBED_THREAD_STATS_ENABLED",
- "help": "Set to 1 to enable thread stats. When enabled the function mbed_stats_thread_get_each returns non-zero data. See mbed_stats.h for more information",
- "value": null
- },
-
- "error-decode-http-url-str": {
- "help": "HTTP URL string for ARM Mbed-OS Error Decode microsite",
- "value": "\"\\nFor more info, visit: https://armmbed.github.io/mbedos-error/?error=0x%08X\""
- },
-
- "cthunk_count_max": {
- "help": "The maximum CThunk objects used at the same time. This must be greater than 0 and less 256",
- "value": 8
- },
- "crash-capture-enabled": {
- "help": "Enables crash context capture when the system enters a fatal error/crash.",
- "value": false
- },
- "error-reboot-max": {
- "help": "Maximum number of auto reboots permitted when an error happens.",
- "value": 1
- },
- "fatal-error-auto-reboot-enabled": {
- "help": "Setting this to true enables auto-reboot on a fatal error.",
- "value": false
- },
- "use-mpu": {
- "help": "Use the MPU if available to fault execution from RAM and writes to ROM. Can be disabled to reduce image size.",
- "value": true
- }
- },
- "target_overrides": {
- "EFM32": {
- "stdio-baud-rate": 115200
- },
- "EFR32": {
- "stdio-baud-rate": 115200
- },
- "UNO_91H": {
- "stdio-baud-rate": 115200
- },
- "DISCO_L475VG_IOT01A": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "K64F": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "K66F": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUCLEO_F429ZI": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUCLEO_F746ZG": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUCLEO_F767ZI": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUCLEO_H743ZI": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUCLEO_F439ZI": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "UBLOX_EVK_ODIN_W2": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "UBLOX_C030_U201": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUMAKER_PFM_M487": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NRF52840_DK": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUCLEO_L476RG": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- },
- "NUCLEO_F411RE": {
- "crash-capture-enabled": true,
- "fatal-error-auto-reboot-enabled": true
- }
- }
-}
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_overrides.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_retarget.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_rtx.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,162 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_MBED_RTX_H -#define MBED_MBED_RTX_H - -#include <stdint.h> - -#ifndef INITIAL_SP - -#if (defined(TARGET_STM32L475VG) ||\ - defined(TARGET_STM32L476RG) ||\ - defined(TARGET_STM32L476JG) ||\ - defined(TARGET_STM32L476VG) ||\ - defined(TARGET_STM32L486RG) ||\ - defined(TARGET_STM32L471QG)) -/* only GCC_ARM and IAR toolchains have the stack on SRAM2 */ -#if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\ - defined(__IAR_SYSTEMS_ICC__ )) &&\ - defined(TWO_RAM_REGIONS)) -#define INITIAL_SP (0x10008000UL) -#else -#define INITIAL_SP (0x20018000UL) -#endif /* toolchains */ - -#elif (defined(TARGET_STM32F051R8) ||\ - defined(TARGET_STM32F100RB) ||\ - defined(TARGET_STM32L031K6) ||\ - defined(TARGET_STM32L053C8) ||\ - defined(TARGET_STM32L053R8)) -#define INITIAL_SP (0x20002000UL) - -#elif (defined(TARGET_STM32F303K8) ||\ - defined(TARGET_STM32F334C8) ||\ - defined(TARGET_STM32F334R8)) -#define INITIAL_SP (0x20003000UL) - -#elif (defined(TARGET_STM32F070RB) ||\ - defined(TARGET_STM32F072RB) ||\ - defined(TARGET_STM32F302R8)) -#define INITIAL_SP (0x20004000UL) - -#elif (defined(TARGET_STM32F103RB) ||\ - defined(TARGET_STM32F103C8) ||\ - defined(TARGET_STM32L072CZ) ||\ - defined(TARGET_STM32L073RZ) ||\ - defined(TARGET_STM32L0x2xZ)) -#define INITIAL_SP (0x20005000UL) - -#elif (defined(TARGET_STM32F091RC) ||\ - defined(TARGET_STM32F410RB) ||\ - defined(TARGET_STM32L151CBA)||\ - defined(TARGET_STM32L151CC) ||\ - defined(TARGET_STM32L151RC) ||\ - defined(TARGET_STM32L152RC)) -#define INITIAL_SP (0x20008000UL) - -#elif defined(TARGET_STM32F303VC) -#define INITIAL_SP (0x2000A000UL) - -#elif defined(TARGET_STM32L443RC) -#define INITIAL_SP (0x2000C000UL) - -#elif (defined(TARGET_STM32F303RE) ||\ - defined(TARGET_STM32F303ZE) ||\ - defined(TARGET_STM32F401VC) ||\ - defined(TARGET_STM32L432KC) ||\ - defined(TARGET_STM32L433RC)) -#define INITIAL_SP (0x20010000UL) - -#elif defined(TARGET_STM32L152RE) -#define INITIAL_SP (0x20014000UL) - -#elif (defined(TARGET_STM32F401RE) ||\ - defined(TARGET_STM32F401VE)) -#define INITIAL_SP (0x20018000UL) - -#elif (defined(TARGET_STM32F207ZG) ||\ - defined(TARGET_STM32F405RG) ||\ - defined(TARGET_STM32F407VG) ||\ - defined(TARGET_STM32F411RE) ||\ - defined(TARGET_STM32F446RE) ||\ - defined(TARGET_STM32F446VE) ||\ - defined(TARGET_STM32F446ZE) ||\ - defined(TARGET_STM32H743ZI) ||\ - defined(TARGET_STM32H753ZI)) -#define INITIAL_SP (0x20020000UL) - -#elif (defined(TARGET_STM32F429ZI) ||\ - defined(TARGET_STM32F437VG) ||\ - defined(TARGET_STM32F439VI) ||\ - defined(TARGET_STM32F439ZI)) -#define INITIAL_SP (0x20030000UL) - -#elif defined(TARGET_STM32F412ZG) -#define INITIAL_SP (0x20040000UL) - -#elif (defined(TARGET_STM32F413ZH) ||\ - defined(TARGET_STM32F469NI) ||\ - defined(TARGET_STM32F746NG) ||\ - defined(TARGET_STM32F746ZG) ||\ - defined(TARGET_STM32F756ZG) ||\ - defined(TARGET_STM32L496AG) ||\ - defined(TARGET_STM32L496ZG)) -#define INITIAL_SP (0x20050000UL) - -#elif (defined(TARGET_STM32F767ZI) ||\ - defined(TARGET_STM32F769NI)) -#define INITIAL_SP (0x20080000UL) - -#elif defined(TARGET_STM32L4R5ZI) -#define INITIAL_SP (0x200A0000UL) - -#else -#error "INITIAL_SP is not defined for this target in the mbed_rtx.h file" -#endif - -#endif // INITIAL_SP -#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS)) -extern uint32_t __StackLimit[]; -extern uint32_t __StackTop[]; -extern uint32_t __end__[]; -extern uint32_t __HeapLimit[]; -#define HEAP_START ((unsigned char*)__end__) -#define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) -#define ISR_STACK_START ((unsigned char*)__StackLimit) -#define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) -#endif - -#if (defined(TARGET_STM32F070RB) || defined(TARGET_STM32F072RB)) -#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION)) -extern uint32_t __StackLimit; -extern uint32_t __StackTop; -extern uint32_t __end__; -extern uint32_t __HeapLimit; -#define HEAP_START ((unsigned char*) &__end__) -#define HEAP_SIZE ((uint32_t)((uint32_t) &__HeapLimit - (uint32_t) HEAP_START)) -#define ISR_STACK_START ((unsigned char*) &__StackLimit) -#define ISR_STACK_SIZE ((uint32_t)((uint32_t) &__StackTop - (uint32_t) &__StackLimit)) -#endif - -#ifdef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE -#undef MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE -#endif -#define MBED_CONF_RTOS_MAIN_THREAD_STACK_SIZE 3072 - -#endif - -#endif // MBED_MBED_RTX_H
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_sdk_boot.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mbed_tz_context.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mpu_armv7.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,273 +0,0 @@
-/******************************************************************************
- * @file mpu_armv7.h
- * @brief CMSIS MPU API for Armv7-M MPU
- * @version V5.0.5
- * @date 06. September 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef ARM_MPU_ARMV7_H
-#define ARM_MPU_ARMV7_H
-
-#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
-#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
-#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
-#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
-#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
-#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
-#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
-#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
-#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
-#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
-#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
-#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
-#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
-#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
-#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
-#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
-#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
-#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
-#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
-#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
-#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
-#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
-#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
-#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
-#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
-#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
-#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
-#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
-
-#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
-#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
-#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
-#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
-#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
-#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
-
-/** MPU Region Base Address Register Value
-*
-* \param Region The region to be configured, number 0 to 15.
-* \param BaseAddress The base address for the region.
-*/
-#define ARM_MPU_RBAR(Region, BaseAddress) \
- (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
- ((Region) & MPU_RBAR_REGION_Msk) | \
- (MPU_RBAR_VALID_Msk))
-
-/**
-* MPU Memory Access Attributes
-*
-* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable Region is shareable between multiple bus masters.
-* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/
-#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
- ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
- (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
- (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
- (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
-
-/**
-* MPU Region Attribute and Size Register Value
-*
-* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
-* \param SubRegionDisable Sub-region disable field.
-* \param Size Region size of the region to be configured, for example 4K, 8K.
-*/
-#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
- ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
- (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
- (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
- (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
- (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
- (((MPU_RASR_ENABLE_Msk))))
-
-/**
-* MPU Region Attribute and Size Register Value
-*
-* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable Region is shareable between multiple bus masters.
-* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-* \param SubRegionDisable Sub-region disable field.
-* \param Size Region size of the region to be configured, for example 4K, 8K.
-*/
-#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
- ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
-
-/**
-* MPU Memory Access Attribute for strongly ordered memory.
-* - TEX: 000b
-* - Shareable
-* - Non-cacheable
-* - Non-bufferable
-*/
-#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
-
-/**
-* MPU Memory Access Attribute for device memory.
-* - TEX: 000b (if non-shareable) or 010b (if shareable)
-* - Shareable or non-shareable
-* - Non-cacheable
-* - Bufferable (if shareable) or non-bufferable (if non-shareable)
-*
-* \param IsShareable Configures the device memory as shareable or non-shareable.
-*/
-#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
-
-/**
-* MPU Memory Access Attribute for normal memory.
-* - TEX: 1BBb (reflecting outer cacheability rules)
-* - Shareable or non-shareable
-* - Cacheable or non-cacheable (reflecting inner cacheability rules)
-* - Bufferable or non-bufferable (reflecting inner cacheability rules)
-*
-* \param OuterCp Configures the outer cache policy.
-* \param InnerCp Configures the inner cache policy.
-* \param IsShareable Configures the memory as shareable or non-shareable.
-*/
-#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
-
-/**
-* MPU Memory Access Attribute non-cacheable policy.
-*/
-#define ARM_MPU_CACHEP_NOCACHE 0U
-
-/**
-* MPU Memory Access Attribute write-back, write and read allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_WRA 1U
-
-/**
-* MPU Memory Access Attribute write-through, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WT_NWA 2U
-
-/**
-* MPU Memory Access Attribute write-back, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_NWA 3U
-
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
- uint32_t RBAR; //!< The region base address register value (RBAR)
- uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
-} ARM_MPU_Region_t;
-
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
- __DSB();
- __ISB();
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
- __DSB();
- __ISB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
- MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
- MPU->RNR = rnr;
- MPU->RASR = 0U;
-}
-
-/** Configure an MPU region.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
-{
- MPU->RBAR = rbar;
- MPU->RASR = rasr;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
-{
- MPU->RNR = rnr;
- MPU->RBAR = rbar;
- MPU->RASR = rasr;
-}
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
- uint32_t i;
- for (i = 0U; i < len; ++i)
- {
- dst[i] = src[i];
- }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
-{
- const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
- while (cnt > MPU_TYPE_RALIASES) {
- orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
- table += MPU_TYPE_RALIASES;
- cnt -= MPU_TYPE_RALIASES;
- }
- orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
-}
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/mpu_armv8.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,333 +0,0 @@
-/******************************************************************************
- * @file mpu_armv8.h
- * @brief CMSIS MPU API for Armv8-M MPU
- * @version V5.0.4
- * @date 10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef ARM_MPU_ARMV8_H
-#define ARM_MPU_ARMV8_H
-
-/** \brief Attribute for device memory (outer only) */
-#define ARM_MPU_ATTR_DEVICE ( 0U )
-
-/** \brief Attribute for non-cacheable, normal memory */
-#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
-
-/** \brief Attribute for normal memory (outer and inner)
-* \param NT Non-Transient: Set to 1 for non-transient data.
-* \param WB Write-Back: Set to 1 to use write-back update policy.
-* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
-* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
-*/
-#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
- (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
-
-/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
-
-/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
-
-/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
-
-/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_GRE (3U)
-
-/** \brief Memory Attribute
-* \param O Outer memory attributes
-* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
-*/
-#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
-
-/** \brief Normal memory non-shareable */
-#define ARM_MPU_SH_NON (0U)
-
-/** \brief Normal memory outer shareable */
-#define ARM_MPU_SH_OUTER (2U)
-
-/** \brief Normal memory inner shareable */
-#define ARM_MPU_SH_INNER (3U)
-
-/** \brief Memory access permissions
-* \param RO Read-Only: Set to 1 for read-only memory.
-* \param NP Non-Privileged: Set to 1 for non-privileged memory.
-*/
-#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
-
-/** \brief Region Base Address Register value
-* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
-* \param SH Defines the Shareability domain for this memory region.
-* \param RO Read-Only: Set to 1 for a read-only memory region.
-* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
-* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
-*/
-#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
- ((BASE & MPU_RBAR_BASE_Msk) | \
- ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
- ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
- ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
-
-/** \brief Region Limit Address Register value
-* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
-* \param IDX The attribute index to be associated with this memory region.
-*/
-#define ARM_MPU_RLAR(LIMIT, IDX) \
- ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
- ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
- (MPU_RLAR_EN_Msk))
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
- uint32_t RBAR; /*!< Region Base Address Register value */
- uint32_t RLAR; /*!< Region Limit Address Register value */
-} ARM_MPU_Region_t;
-
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
- __DSB();
- __ISB();
- MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
- SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
- __DSB();
- __ISB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
- SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
- MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-#ifdef MPU_NS
-/** Enable the Non-secure MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
-{
- __DSB();
- __ISB();
- MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
- SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-}
-
-/** Disable the Non-secure MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable_NS(void)
-{
- __DSB();
- __ISB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
- SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
- MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
-}
-#endif
-
-/** Set the memory attribute encoding to the given MPU.
-* \param mpu Pointer to the MPU to be configured.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
-{
- const uint8_t reg = idx / 4U;
- const uint32_t pos = ((idx % 4U) * 8U);
- const uint32_t mask = 0xFFU << pos;
-
- if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
- return; // invalid index
- }
-
- mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
-}
-
-/** Set the memory attribute encoding.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
-{
- ARM_MPU_SetMemAttrEx(MPU, idx, attr);
-}
-
-#ifdef MPU_NS
-/** Set the memory attribute encoding to the Non-secure MPU.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
-{
- ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
-}
-#endif
-
-/** Clear and disable the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
-{
- mpu->RNR = rnr;
- mpu->RLAR = 0U;
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
- ARM_MPU_ClrRegionEx(MPU, rnr);
-}
-
-#ifdef MPU_NS
-/** Clear and disable the given Non-secure MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
-{
- ARM_MPU_ClrRegionEx(MPU_NS, rnr);
-}
-#endif
-
-/** Configure the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
- mpu->RNR = rnr;
- mpu->RBAR = rbar;
- mpu->RLAR = rlar;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
- ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
-}
-
-#ifdef MPU_NS
-/** Configure the given Non-secure MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/
-__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
- ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
-}
-#endif
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
- uint32_t i;
- for (i = 0U; i < len; ++i)
- {
- dst[i] = src[i];
- }
-}
-
-/** Load the given number of MPU regions from a table to the given MPU.
-* \param mpu Pointer to the MPU registers to be used.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
-{
- const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
- if (cnt == 1U) {
- mpu->RNR = rnr;
- orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
- } else {
- uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
- uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
-
- mpu->RNR = rnrBase;
- while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
- uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
- orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
- table += c;
- cnt -= c;
- rnrOffset = 0U;
- rnrBase += MPU_TYPE_RALIASES;
- mpu->RNR = rnrBase;
- }
-
- orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
- }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
-{
- ARM_MPU_LoadEx(MPU, rnr, table, cnt);
-}
-
-#ifdef MPU_NS
-/** Load the given number of MPU regions from a table to the Non-secure MPU.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
-{
- ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
-}
-#endif
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/nvic_addr.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef NVIC_ADDR_H
-#define NVIC_ADDR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(__ICCARM__)
-#pragma section=".intvec"
-#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
-#elif defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-extern uint32_t Load$$LR$$LR_IROM1$$Base[];
-#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
-#elif defined(__GNUC__)
-extern uint32_t g_pfnVectors[];
-#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors)
-#else
-#error "Flash vector address not set for this toolchain"
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/objects.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- IRQn_Type irq_n;
- uint32_t irq_index;
- uint32_t event;
- PinName pin;
-};
-
-struct port_s {
- PortName port;
- uint32_t mask;
- PinDirection direction;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_out;
-};
-
-#include "common_objects.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/pin_device.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,125 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2016, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PIN_DEVICE_H
-#define MBED_PIN_DEVICE_H
-
-#include "cmsis.h"
-#include "stm32f1xx_ll_gpio.h"
-
-extern const uint32_t ll_pin_defines[16];
-
-static inline void stm_pin_DisconnectDebug(PinName pin)
-{
- // Enable AFIO clock
- __HAL_RCC_AFIO_CLK_ENABLE();
-
- // Disconnect JTAG-DP + SW-DP signals.
- // Warning: Need to reconnect under reset
- if ((pin == PA_13) || (pin == PA_14)) {
- __HAL_AFIO_REMAP_SWJ_DISABLE(); // JTAG-DP Disabled and SW-DP Disabled
- }
- if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
- __HAL_AFIO_REMAP_SWJ_NOJTAG(); // JTAG-DP Disabled and SW-DP enabled
- }
-}
-
-/* The AF selection of F1 family is specific compared to others */
-static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t afnum)
-{
- // Enable AFIO clock
- __HAL_RCC_AFIO_CLK_ENABLE();
-
- if (afnum > 0) {
- switch (afnum) {
- case 1: // Remap SPI1
- __HAL_AFIO_REMAP_SPI1_ENABLE();
- break;
- case 2: // Remap I2C1
- __HAL_AFIO_REMAP_I2C1_ENABLE();
- break;
- case 3: // Remap USART1
- __HAL_AFIO_REMAP_USART1_ENABLE();
- break;
- case 4: // Remap USART2
- __HAL_AFIO_REMAP_USART2_ENABLE();
- break;
- case 5: // Partial Remap USART3
- __HAL_AFIO_REMAP_USART3_PARTIAL();
- break;
- case 6: // Partial Remap TIM1
- __HAL_AFIO_REMAP_TIM1_PARTIAL();
- break;
- case 7: // Partial Remap TIM3
- __HAL_AFIO_REMAP_TIM3_PARTIAL();
- break;
- case 8: // Full Remap TIM2
- __HAL_AFIO_REMAP_TIM2_ENABLE();
- break;
- case 9: // Full Remap TIM3
- __HAL_AFIO_REMAP_TIM3_ENABLE();
- break;
-#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
- case 10: // CAN_RX mapped to PB8, CAN_TX mapped to PB9
- __HAL_AFIO_REMAP_CAN1_2();
- break;
-#endif
- default:
- break;
- }
- }
-}
-
-static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
-{
- uint32_t function = LL_GPIO_GetPinMode(gpio, ll_pin);
-
- switch (pull_config) {
- case GPIO_PULLUP:
- if (function == LL_GPIO_MODE_FLOATING) {
- LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
- }
- LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_UP);
- break;
- case GPIO_PULLDOWN:
- if (function == LL_GPIO_MODE_FLOATING) {
- LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_INPUT);
- }
- LL_GPIO_SetPinPull(gpio, ll_pin, LL_GPIO_PULL_DOWN);
- break;
- default:
- /* Input+NoPull = Floating for F1 family */
- if (function == LL_GPIO_MODE_INPUT) {
- LL_GPIO_SetPinMode(gpio, ll_pin, LL_GPIO_MODE_FLOATING);
- }
- break;
- }
-}
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/pinmap.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/port_api.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/pwmout_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/pwmout_device.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2017, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PWMOUT_DEVICE_H
-#define MBED_PWMOUT_DEVICE_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_PWMOUT
-
-typedef enum {
- PWMOUT_ON_APB1 = 0,
- PWMOUT_ON_APB2 = 1,
- PWMOUT_UNKNOWN = 2
-} PwmoutApb;
-
-/* Structure to describe Timers to APB */
-typedef struct pwm_apb_map {
- PWMName pwm; // an index entry for each EXIT line
- PwmoutApb pwmoutApb;
-} pwm_apb_map_t;
-
-extern const pwm_apb_map_t pwm_apb_map_table[];
-
-#endif // DEVICE_PWMOUT
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/pwmout_device.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/qspi_api.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/rtc_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/rtc_api_hal.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,96 +0,0 @@
-/* mbed Microcontroller Library
-*******************************************************************************
-* Copyright (c) 2018, STMicroelectronics
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 3. Neither the name of STMicroelectronics nor the names of its contributors
-* may be used to endorse or promote products derived from this software
-* without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************
-*/
-
-#ifndef MBED_RTC_API_HAL_H
-#define MBED_RTC_API_HAL_H
-
-#include "rtc_api.h"
-#include "lp_ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if MBED_CONF_TARGET_LSE_AVAILABLE
-#define RTC_CLOCK LSE_VALUE
-#else
-#define RTC_CLOCK LSI_VALUE
-#endif
-
-#if DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM
-/* PREDIV_A : 7-bit asynchronous prescaler */
-/* PREDIV_A is set to set LPTICKER frequency to RTC_CLOCK/4 */
-#define PREDIV_A_VALUE 3
-
-/** Read RTC counter with sub second precision
- *
- * @return LP ticker counter
- */
-uint32_t rtc_read_lp(void);
-
-/** Program a wake up timer event
- *
- * @param timestamp: counter to set
- */
-void rtc_set_wake_up_timer(timestamp_t timestamp);
-
-/** Call RTC Wake Up IT
- */
-void rtc_fire_interrupt(void);
-
-/** Disable the wake up timer event.
- *
- * The wake up timer use auto reload, you have to deactivate it manually.
- */
-void rtc_deactivate_wake_up_timer(void);
-
-#else /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
-
-/* PREDIV_A : 7-bit asynchronous prescaler */
-/* PREDIV_A is set to the maximum value to improve the consumption */
-#define PREDIV_A_VALUE 127
-
-#endif /* DEVICE_LPTICKER && !MBED_CONF_TARGET_LPTICKER_LPTIM */
-
-/* PREDIV_S : 15-bit synchronous prescaler */
-/* PREDIV_S is set in order to get a 1 Hz clock */
-#define PREDIV_S_VALUE (RTC_CLOCK / (PREDIV_A_VALUE + 1) - 1)
-
-/** Synchronise the RTC shadow registers.
- *
- * Must be called after a deepsleep.
- */
-void rtc_synchronize(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/serial_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/serial_api_hal.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
-*******************************************************************************
-* Copyright (c) 2016, STMicroelectronics
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-*
-* 1. Redistributions of source code must retain the above copyright notice,
-* this list of conditions and the following disclaimer.
-* 2. Redistributions in binary form must reproduce the above copyright notice,
-* this list of conditions and the following disclaimer in the documentation
-* and/or other materials provided with the distribution.
-* 3. Neither the name of STMicroelectronics nor the names of its contributors
-* may be used to endorse or promote products derived from this software
-* without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*******************************************************************************
-*/
-
-#ifndef MBED_SERIAL_API_HAL_H
-#define MBED_SERIAL_API_HAL_H
-
-#include "serial_api.h"
-#include <string.h>
-#include "mbed_assert.h"
-#include "mbed_debug.h"
-#include "mbed_error.h"
-
-#include "PeripheralPins.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
- * Extend serial_api.h
- */
-
-#if DEVICE_SERIAL_ASYNCH
-#define SERIAL_S(obj) (&((obj)->serial))
-#else
-#define SERIAL_S(obj) (obj)
-#endif
-
-
-/** Initialize and configure the UART peripheral
- *
- * @param obj The serial object containing the configuration
- */
-HAL_StatusTypeDef init_uart(serial_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/serial_device.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/sleep.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/spi_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/spi_device.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,35 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef MBED_SPI_DEVICE_H -#define MBED_SPI_DEVICE_H - -#include "stm32f1xx_ll_spi.h" - -#endif
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/startup_stm32f103xb.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32_assert.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2017, STMicroelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#ifndef STM32_ASSERT_H -#define STM32_ASSERT_H -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ -#include "mbed_assert.h" -#define assert_param(expr) MBED_ASSERT(expr) - -#endif
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32_assert_template.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,73 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_assert.h
- * @author MCD Application Team
- * @brief STM32 assert template file.
- * This file should be copied to the application folder and renamed
- * to stm32_assert.h.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_ASSERT_H
-#define __STM32_ASSERT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_ASSERT_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32_hal_legacy.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,3219 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_hal_legacy.h
- * @author MCD Application Team
- * @version V1.1.1
- * @date 12-May-2017
- * @brief This file contains aliases definition for the STM32Cube HAL constants
- * macros and functions maintained for legacy purpose.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_HAL_LEGACY
-#define __STM32_HAL_LEGACY
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define AES_FLAG_RDERR CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP ADC_REGULAR_GROUP
-#define INJECTED_GROUP ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT ADC_AWD_EVENT
-#define AWD1_EVENT ADC_AWD1_EVENT
-#define AWD2_EVENT ADC_AWD2_EVENT
-#define AWD3_EVENT ADC_AWD3_EVENT
-#define OVR_EVENT ADC_OVR_EVENT
-#define JQOVF_EVENT ADC_JQOVF_EVENT
-#define ALL_CHANNELS ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
-/**
- * @}
- */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
- * @{
- */
-#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
-/* to the second dedicated IO (only for COMP2). */
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
-/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
- * @{
- */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
- * @}
- */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define DAC1_CHANNEL_1 DAC_CHANNEL_1
-#define DAC1_CHANNEL_2 DAC_CHANNEL_2
-#define DAC2_CHANNEL_1 DAC_CHANNEL_1
-#define DAC_WAVE_NONE 0x00000000U
-#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW OB_IWDG_SW
-#define OB_WDG_HW OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
-/**
- * @}
- */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
- * @{
- */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
-#else
-#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
- * @}
- */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
-/**
- * @}
- */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
- * @{
- */
-#define GET_GPIO_SOURCE GPIO_GET_INDEX
-#define GET_GPIO_INDEX GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
-#endif
-
-#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#if defined(STM32H7)
- #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
- #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
- #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
- #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
- #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
- #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
- * @{
- */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define KR_KEY_RELOAD IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE IWDG_KEY_ENABLE
-#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
-/**
- * @}
- */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
- * @{
- */
-#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE NOR_WRITE
-#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
-/**
- * @}
- */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
- * @{
- */
-#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-#if defined(STM32F7)
- #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
-#endif
-/**
- * @}
- */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define FORMAT_BIN RTC_FORMAT_BIN
-#define FORMAT_BCD RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1 TIM_DMABASE_CR1
-#define TIM_DMABase_CR2 TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER TIM_DMABASE_DIER
-#define TIM_DMABase_SR TIM_DMABASE_SR
-#define TIM_DMABase_EGR TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER TIM_DMABASE_CCER
-#define TIM_DMABase_CNT TIM_DMABASE_CNT
-#define TIM_DMABase_PSC TIM_DMABASE_PSC
-#define TIM_DMABase_ARR TIM_DMABASE_ARR
-#define TIM_DMABase_RCR TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1 TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2 TIM_DMABASE_OR2
-#define TIM_DMABase_OR3 TIM_DMABASE_OR3
-#define TIM_DMABase_OR TIM_DMABASE_OR
-
-#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
-
-/**
- * @}
- */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
- * @{
- */
-#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
- * @{
- */
-#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
-
-#define __DIV_LPUART UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED USART_NACK_ENABLE
-#define USARTNACK_DISABLED USART_NACK_DISABLE
-/**
- * @}
- */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CFR_BASE WWDG_CFR_BASE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
- * @{
- */
-#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
-#define CAN_TXSTATUS_OK ((uint8_t)0x01)
-#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
- * @{
- */
-
-#define VLAN_TAG ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR 0x00000100U
-#define ETH_MMCRIR 0x00000104U
-#define ETH_MMCTIR 0x00000108U
-#define ETH_MMCRIMR 0x0000010CU
-#define ETH_MMCTIMR 0x00000110U
-#define ETH_MMCTGFSCCR 0x0000014CU
-#define ETH_MMCTGFMSCCR 0x00000150U
-#define ETH_MMCTGFCR 0x00000168U
-#define ETH_MMCRFCECR 0x00000194U
-#define ETH_MMCRFAECR 0x00000198U
-#define ETH_MMCRGUFCR 0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
-#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
- * @{
- */
-#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
-
-/**
- * @}
- */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
- defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
- * @{
- */
-#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
-#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
-/**
- * @}
- */
-#endif /* STM32L4 || STM32F7*/
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
- * @{
- */
-#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
-
- /**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
- /**
- * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
- * @{
- */
-#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
-
-#define DBP_BitNumber DBP_BIT_NUMBER
-#define PVDE_BitNumber PVDE_BIT_NUMBER
-#define PMODE_BitNumber PMODE_BIT_NUMBER
-#define EWUP_BitNumber EWUP_BIT_NUMBER
-#define FPDS_BitNumber FPDS_BIT_NUMBER
-#define ODEN_BitNumber ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
-#define BRE_BitNumber BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
- /**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError TIM_DMAError
-#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define AES_IT_CC CRYP_IT_CC
-#define AES_IT_ERR CRYP_IT_ERR
-#define AES_FLAG_CCF CRYP_FLAG_CCF
-/**
- * @}
- */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __ADC_ENABLE __HAL_ADC_ENABLE
-#define __ADC_DISABLE __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
-#define __ADC_IS_ENABLED ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1 ADC_SQR1
-#define __HAL_ADC_SMPR1 ADC_SMPR1
-#define __HAL_ADC_SMPR2 ADC_SMPR2
-#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
- * @}
- */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#if defined(STM32F3)
-#define COMP_START __HAL_COMP_ENABLE
-#define COMP_STOP __HAL_COMP_DISABLE
-#define COMP_LOCK __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
- ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
- ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
- __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
- __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
- __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro */
-/* is COMP_FLAG_LOCK. */
-/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
-/* argument. */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
- * @}
- */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
- * @{
- */
-#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
- * @}
- */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
- ((WAVE) == DAC_WAVE_NOISE)|| \
- ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
- * @}
- */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_WRPAREA IS_OB_WRPAREA
-#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE IS_FLASH_TYPEERASE
-#define IS_NBSECTORS IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
-#define __HAL_I2C_SPEED I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
-/**
- * @}
- */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
-
-/**
- * @}
- */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __IRDA_DISABLE __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
- * @}
- */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
- * @}
- */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
- * @{
- */
-
-#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
-#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
-#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14 RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE RCC_IT_LSECSS
-#define RCC_IT_CSSHSE RCC_IT_CSS
-
-#define RCC_PLLMUL_3 RCC_PLL_MUL3
-#define RCC_PLLMUL_4 RCC_PLL_MUL4
-#define RCC_PLLMUL_6 RCC_PLL_MUL6
-#define RCC_PLLMUL_8 RCC_PLL_MUL8
-#define RCC_PLLMUL_12 RCC_PLL_MUL12
-#define RCC_PLLMUL_16 RCC_PLL_MUL16
-#define RCC_PLLMUL_24 RCC_PLL_MUL24
-#define RCC_PLLMUL_32 RCC_PLL_MUL32
-#define RCC_PLLMUL_48 RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2 RCC_PLL_DIV2
-#define RCC_PLLDIV_3 RCC_PLL_DIV3
-#define RCC_PLLDIV_4 RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV RCC_MCODIV_1
-#define RCC_MCO_DIV1 RCC_MCODIV_1
-#define RCC_MCO_DIV2 RCC_MCODIV_2
-#define RCC_MCO_DIV4 RCC_MCODIV_4
-#define RCC_MCO_DIV8 RCC_MCODIV_8
-#define RCC_MCO_DIV16 RCC_MCODIV_16
-#define RCC_MCO_DIV32 RCC_MCODIV_32
-#define RCC_MCO_DIV64 RCC_MCODIV_64
-#define RCC_MCO_DIV128 RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
-
-#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB RCC_CR_HSION_BB
-#define CR_CSSON_BB RCC_CR_CSSON_BB
-#define CR_PLLON_BB RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB RCC_CR_MSION_BB
-#define CSR_LSION_BB RCC_CSR_LSION_BB
-#define CSR_LSEON_BB RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB RCC_CR_HSEON_BB
-#define CSR_RMVF_BB RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
- * @{
- */
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
- * @}
- */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
-#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif /* STM32F1 */
-
-#define IS_ALARM IS_RTC_ALARM
-#define IS_ALARM_MASK IS_RTC_ALARM_MASK
-#define IS_TAMPER IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-
-#if defined(STM32F4) || defined(STM32F2)
-#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
-#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define SDMMC1_IRQn SDIO_IRQn
-#define SDMMC1_IRQHandler SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
-#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
-#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
-#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
-#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
-#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
-#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
-#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
-#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
-#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
-#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
-#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
-#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
-#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
-#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
-#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
-#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
-#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define SDIO_IRQn SDMMC1_IRQn
-#define SDIO_IRQHandler SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
-#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
-#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
-#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
-#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
-/**
- * @}
- */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
-
-/**
- * @}
- */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
-
-/**
- * @}
- */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
-#define __USART_ENABLE __HAL_USART_ENABLE
-#define __USART_DISABLE __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
-
-/**
- * @}
- */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
- * @{
- */
-#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
-/**
- * @}
- */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
-/**
- * @}
- */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
- * @{
- */
-
-#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
-/**
- * @}
- */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
- * @{
- */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
- * @}
- */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
- * @{
- */
-#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
- * @}
- */
-
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
- * @{
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f103xb.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,10642 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f103xb.h
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F1xx devices.
- *
- * This file contains:
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripherals registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f103xb
- * @{
- */
-
-#ifndef __STM32F103xB_H
-#define __STM32F103xB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
- */
-#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
- #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
-#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32F10x Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
-/****** STM32 specific Interrupt Numbers *********************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMPER_IRQn = 2, /*!< Tamper Interrupt */
- RTC_IRQn = 3, /*!< RTC global Interrupt */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h"
-#include "system_stm32f1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR;
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SMPR1;
- __IO uint32_t SMPR2;
- __IO uint32_t JOFR1;
- __IO uint32_t JOFR2;
- __IO uint32_t JOFR3;
- __IO uint32_t JOFR4;
- __IO uint32_t HTR;
- __IO uint32_t LTR;
- __IO uint32_t SQR1;
- __IO uint32_t SQR2;
- __IO uint32_t SQR3;
- __IO uint32_t JSQR;
- __IO uint32_t JDR1;
- __IO uint32_t JDR2;
- __IO uint32_t JDR3;
- __IO uint32_t JDR4;
- __IO uint32_t DR;
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
- __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
- uint32_t RESERVED[16];
- __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
-} ADC_Common_TypeDef;
-
-/**
- * @brief Backup Registers
- */
-
-typedef struct
-{
- uint32_t RESERVED0;
- __IO uint32_t DR1;
- __IO uint32_t DR2;
- __IO uint32_t DR3;
- __IO uint32_t DR4;
- __IO uint32_t DR5;
- __IO uint32_t DR6;
- __IO uint32_t DR7;
- __IO uint32_t DR8;
- __IO uint32_t DR9;
- __IO uint32_t DR10;
- __IO uint32_t RTCCR;
- __IO uint32_t CR;
- __IO uint32_t CSR;
-} BKP_TypeDef;
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR;
- __IO uint32_t TDTR;
- __IO uint32_t TDLR;
- __IO uint32_t TDHR;
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR;
- __IO uint32_t RDTR;
- __IO uint32_t RDLR;
- __IO uint32_t RDHR;
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1;
- __IO uint32_t FR2;
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR;
- __IO uint32_t MSR;
- __IO uint32_t TSR;
- __IO uint32_t RF0R;
- __IO uint32_t RF1R;
- __IO uint32_t IER;
- __IO uint32_t ESR;
- __IO uint32_t BTR;
- uint32_t RESERVED0[88];
- CAN_TxMailBox_TypeDef sTxMailBox[3];
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
- uint32_t RESERVED1[12];
- __IO uint32_t FMR;
- __IO uint32_t FM1R;
- uint32_t RESERVED2;
- __IO uint32_t FS1R;
- uint32_t RESERVED3;
- __IO uint32_t FFA1R;
- uint32_t RESERVED4;
- __IO uint32_t FA1R;
- uint32_t RESERVED5[8];
- CAN_FilterRegister_TypeDef sFilterRegister[14];
-} CAN_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
- uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE;
- __IO uint32_t CR;
-}DBGMCU_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CCR;
- __IO uint32_t CNDTR;
- __IO uint32_t CPAR;
- __IO uint32_t CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR;
- __IO uint32_t IFCR;
-} DMA_TypeDef;
-
-
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR;
- __IO uint32_t EMR;
- __IO uint32_t RTSR;
- __IO uint32_t FTSR;
- __IO uint32_t SWIER;
- __IO uint32_t PR;
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR;
- __IO uint32_t KEYR;
- __IO uint32_t OPTKEYR;
- __IO uint32_t SR;
- __IO uint32_t CR;
- __IO uint32_t AR;
- __IO uint32_t RESERVED;
- __IO uint32_t OBR;
- __IO uint32_t WRPR;
-} FLASH_TypeDef;
-
-/**
- * @brief Option Bytes Registers
- */
-
-typedef struct
-{
- __IO uint16_t RDP;
- __IO uint16_t USER;
- __IO uint16_t Data0;
- __IO uint16_t Data1;
- __IO uint16_t WRP0;
- __IO uint16_t WRP1;
- __IO uint16_t WRP2;
- __IO uint16_t WRP3;
-} OB_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t CRL;
- __IO uint32_t CRH;
- __IO uint32_t IDR;
- __IO uint32_t ODR;
- __IO uint32_t BSRR;
- __IO uint32_t BRR;
- __IO uint32_t LCKR;
-} GPIO_TypeDef;
-
-/**
- * @brief Alternate Function I/O
- */
-
-typedef struct
-{
- __IO uint32_t EVCR;
- __IO uint32_t MAPR;
- __IO uint32_t EXTICR[4];
- uint32_t RESERVED0;
- __IO uint32_t MAPR2;
-} AFIO_TypeDef;
-/**
- * @brief Inter Integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t OAR1;
- __IO uint32_t OAR2;
- __IO uint32_t DR;
- __IO uint32_t SR1;
- __IO uint32_t SR2;
- __IO uint32_t CCR;
- __IO uint32_t TRISE;
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CSR;
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CFGR;
- __IO uint32_t CIR;
- __IO uint32_t APB2RSTR;
- __IO uint32_t APB1RSTR;
- __IO uint32_t AHBENR;
- __IO uint32_t APB2ENR;
- __IO uint32_t APB1ENR;
- __IO uint32_t BDCR;
- __IO uint32_t CSR;
-
-
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t CRH;
- __IO uint32_t CRL;
- __IO uint32_t PRLH;
- __IO uint32_t PRLL;
- __IO uint32_t DIVH;
- __IO uint32_t DIVL;
- __IO uint32_t CNTH;
- __IO uint32_t CNTL;
- __IO uint32_t ALRH;
- __IO uint32_t ALRL;
-} RTC_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER;
- __IO uint32_t CLKCR;
- __IO uint32_t ARG;
- __IO uint32_t CMD;
- __I uint32_t RESPCMD;
- __I uint32_t RESP1;
- __I uint32_t RESP2;
- __I uint32_t RESP3;
- __I uint32_t RESP4;
- __IO uint32_t DTIMER;
- __IO uint32_t DLEN;
- __IO uint32_t DCTRL;
- __I uint32_t DCOUNT;
- __I uint32_t STA;
- __IO uint32_t ICR;
- __IO uint32_t MASK;
- uint32_t RESERVED0[2];
- __I uint32_t FIFOCNT;
- uint32_t RESERVED1[13];
- __IO uint32_t FIFO;
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SR;
- __IO uint32_t DR;
- __IO uint32_t CRCPR;
- __IO uint32_t RXCRCR;
- __IO uint32_t TXCRCR;
- __IO uint32_t I2SCFGR;
-} SPI_TypeDef;
-
-/**
- * @brief TIM Timers
- */
-typedef struct
-{
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
- __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
-}TIM_TypeDef;
-
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/**
- * @brief Universal Serial Bus Full Speed Device
- */
-
-typedef struct
-{
- __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
- __IO uint16_t RESERVED0; /*!< Reserved */
- __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
- __IO uint16_t RESERVED1; /*!< Reserved */
- __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
- __IO uint16_t RESERVED2; /*!< Reserved */
- __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
- __IO uint16_t RESERVED3; /*!< Reserved */
- __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
- __IO uint16_t RESERVED4; /*!< Reserved */
- __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
- __IO uint16_t RESERVED5; /*!< Reserved */
- __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
- __IO uint16_t RESERVED6; /*!< Reserved */
- __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
- __IO uint16_t RESERVED7[17]; /*!< Reserved */
- __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
- __IO uint16_t RESERVED8; /*!< Reserved */
- __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
- __IO uint16_t RESERVED9; /*!< Reserved */
- __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
- __IO uint16_t RESERVEDA; /*!< Reserved */
- __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
- __IO uint16_t RESERVEDB; /*!< Reserved */
- __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
- __IO uint16_t RESERVEDC; /*!< Reserved */
-} USB_TypeDef;
-
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-
-#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
-#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
-#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-
-#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
-#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
-#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
-#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
-#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
-#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
-#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-
-#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
-#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
-#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
-#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
-#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
-#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-
-
-
-#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
-
-/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-
-#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
-#define RTC ((RTC_TypeDef *)RTC_BASE)
-#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
-#define USART2 ((USART_TypeDef *)USART2_BASE)
-#define USART3 ((USART_TypeDef *)USART3_BASE)
-#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
-#define USB ((USB_TypeDef *)USB_BASE)
-#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
-#define BKP ((BKP_TypeDef *)BKP_BASE)
-#define PWR ((PWR_TypeDef *)PWR_BASE)
-#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
-#define USART1 ((USART_TypeDef *)USART1_BASE)
-#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *)RCC_BASE)
-#define CRC ((CRC_TypeDef *)CRC_BASE)
-#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
-#define OB ((OB_TypeDef *)OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
-
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit (CRC) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR_Pos (0U)
-#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
-#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR_Pos (0U)
-#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
-#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET_Pos (0U)
-#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
-#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
-
-/******************************************************************************/
-/* */
-/* Power Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS_Pos (0U)
-#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
-#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
-#define PWR_CR_PDDS_Pos (1U)
-#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
-#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos (2U)
-#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
-#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos (3U)
-#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
-#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos (4U)
-#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
-#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos (5U)
-#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
-#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
-#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
-#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
-#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
-#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
-#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
-#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
-#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
-#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
-#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
-
-/* Legacy defines */
-#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
-#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
-#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
-#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
-#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
-#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
-#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
-#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
-
-#define PWR_CR_DBP_Pos (8U)
-#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
-#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
-
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF_Pos (0U)
-#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
-#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos (1U)
-#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
-#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos (2U)
-#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
-#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
-#define PWR_CSR_EWUP_Pos (8U)
-#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
-#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
-
-/******************************************************************************/
-/* */
-/* Backup registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for BKP_DR1 register ********************/
-#define BKP_DR1_D_Pos (0U)
-#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR2 register ********************/
-#define BKP_DR2_D_Pos (0U)
-#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR3 register ********************/
-#define BKP_DR3_D_Pos (0U)
-#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR4 register ********************/
-#define BKP_DR4_D_Pos (0U)
-#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR5 register ********************/
-#define BKP_DR5_D_Pos (0U)
-#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR6 register ********************/
-#define BKP_DR6_D_Pos (0U)
-#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR7 register ********************/
-#define BKP_DR7_D_Pos (0U)
-#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR8 register ********************/
-#define BKP_DR8_D_Pos (0U)
-#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR9 register ********************/
-#define BKP_DR9_D_Pos (0U)
-#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR10 register *******************/
-#define BKP_DR10_D_Pos (0U)
-#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
-
-#define RTC_BKP_NUMBER 10
-
-/****************** Bit definition for BKP_RTCCR register *******************/
-#define BKP_RTCCR_CAL_Pos (0U)
-#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
-#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
-#define BKP_RTCCR_CCO_Pos (7U)
-#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
-#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
-#define BKP_RTCCR_ASOE_Pos (8U)
-#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
-#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
-#define BKP_RTCCR_ASOS_Pos (9U)
-#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
-#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
-
-/******************** Bit definition for BKP_CR register ********************/
-#define BKP_CR_TPE_Pos (0U)
-#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
-#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
-#define BKP_CR_TPAL_Pos (1U)
-#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
-#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
-
-/******************* Bit definition for BKP_CSR register ********************/
-#define BKP_CSR_CTE_Pos (0U)
-#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
-#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
-#define BKP_CSR_CTI_Pos (1U)
-#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
-#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
-#define BKP_CSR_TPIE_Pos (2U)
-#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
-#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
-#define BKP_CSR_TEF_Pos (8U)
-#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
-#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
-#define BKP_CSR_TIF_Pos (9U)
-#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
-#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
-
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION_Pos (0U)
-#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
-#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos (1U)
-#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
-#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSITRIM_Pos (3U)
-#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
-#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
-#define RCC_CR_HSICAL_Pos (8U)
-#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
-#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
-#define RCC_CR_HSEON_Pos (16U)
-#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
-#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos (17U)
-#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
-#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos (18U)
-#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
-#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSON_Pos (19U)
-#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
-#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
-#define RCC_CR_PLLON_Pos (24U)
-#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
-#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos (25U)
-#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
-#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
-
-
-/******************* Bit definition for RCC_CFGR register *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos (0U)
-#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
-#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
-#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos (2U)
-#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
-#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos (4U)
-#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos (8U)
-#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos (11U)
-#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define RCC_CFGR_ADCPRE_Pos (14U)
-#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
-#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
-#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
-#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-
-#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
-
-#define RCC_CFGR_PLLSRC_Pos (16U)
-#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLXTPRE_Pos (17U)
-#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
-#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMULL_Pos (18U)
-#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
-#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
-#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
-#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-
-#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
-#define RCC_CFGR_PLLMULL3_Pos (18U)
-#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
-#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
-#define RCC_CFGR_PLLMULL4_Pos (19U)
-#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
-#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
-#define RCC_CFGR_PLLMULL5_Pos (18U)
-#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
-#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
-#define RCC_CFGR_PLLMULL6_Pos (20U)
-#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
-#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
-#define RCC_CFGR_PLLMULL7_Pos (18U)
-#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
-#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
-#define RCC_CFGR_PLLMULL8_Pos (19U)
-#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
-#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
-#define RCC_CFGR_PLLMULL9_Pos (18U)
-#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
-#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
-#define RCC_CFGR_PLLMULL10_Pos (21U)
-#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
-#define RCC_CFGR_PLLMULL11_Pos (18U)
-#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
-#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
-#define RCC_CFGR_PLLMULL12_Pos (19U)
-#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
-#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
-#define RCC_CFGR_PLLMULL13_Pos (18U)
-#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
-#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
-#define RCC_CFGR_PLLMULL14_Pos (20U)
-#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
-#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
-#define RCC_CFGR_PLLMULL15_Pos (18U)
-#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
-#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
-#define RCC_CFGR_PLLMULL16_Pos (19U)
-#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
-#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
-#define RCC_CFGR_USBPRE_Pos (22U)
-#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
-#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCO_Pos (24U)
-#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-
-#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
-
- /* Reference defines */
- #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
- #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
- #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
- #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
- #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
- #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
- #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
- #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
- #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
-
-/*!<****************** Bit definition for RCC_CIR register ********************/
-#define RCC_CIR_LSIRDYF_Pos (0U)
-#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos (1U)
-#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos (2U)
-#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos (3U)
-#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos (4U)
-#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_CSSF_Pos (7U)
-#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
-#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
-#define RCC_CIR_LSIRDYIE_Pos (8U)
-#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos (9U)
-#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos (10U)
-#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos (11U)
-#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos (12U)
-#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_LSIRDYC_Pos (16U)
-#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos (17U)
-#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos (18U)
-#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos (19U)
-#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos (20U)
-#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_CSSC_Pos (23U)
-#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
-#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
-
-
-/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_AFIORST_Pos (0U)
-#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
-#define RCC_APB2RSTR_IOPARST_Pos (2U)
-#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
-#define RCC_APB2RSTR_IOPBRST_Pos (3U)
-#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
-#define RCC_APB2RSTR_IOPCRST_Pos (4U)
-#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
-#define RCC_APB2RSTR_IOPDRST_Pos (5U)
-#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
-#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
-#define RCC_APB2RSTR_ADC1RST_Pos (9U)
-#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
-
-#define RCC_APB2RSTR_ADC2RST_Pos (10U)
-#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
-#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
-
-#define RCC_APB2RSTR_TIM1RST_Pos (11U)
-#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
-#define RCC_APB2RSTR_SPI1RST_Pos (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos (14U)
-#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
-
-
-#define RCC_APB2RSTR_IOPERST_Pos (6U)
-#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
-#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
-
-
-
-
-/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos (17U)
-#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
-
-#define RCC_APB1RSTR_CAN1RST_Pos (25U)
-#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
-#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
-
-#define RCC_APB1RSTR_BKPRST_Pos (27U)
-#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
-#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
-#define RCC_APB1RSTR_PWRRST_Pos (28U)
-#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
-
-#define RCC_APB1RSTR_TIM4RST_Pos (2U)
-#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
-#define RCC_APB1RSTR_SPI2RST_Pos (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos (18U)
-#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
-
-#define RCC_APB1RSTR_USBRST_Pos (23U)
-#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
-
-
-
-
-
-
-/****************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMA1EN_Pos (0U)
-#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
-#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
-#define RCC_AHBENR_SRAMEN_Pos (2U)
-#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN_Pos (4U)
-#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
-#define RCC_AHBENR_CRCEN_Pos (6U)
-#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
-
-
-
-
-/****************** Bit definition for RCC_APB2ENR register *****************/
-#define RCC_APB2ENR_AFIOEN_Pos (0U)
-#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
-#define RCC_APB2ENR_IOPAEN_Pos (2U)
-#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
-#define RCC_APB2ENR_IOPBEN_Pos (3U)
-#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
-#define RCC_APB2ENR_IOPCEN_Pos (4U)
-#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
-#define RCC_APB2ENR_IOPDEN_Pos (5U)
-#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos (9U)
-#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
-
-#define RCC_APB2ENR_ADC2EN_Pos (10U)
-#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
-#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
-
-#define RCC_APB2ENR_TIM1EN_Pos (11U)
-#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
-#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos (12U)
-#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos (14U)
-#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
-
-
-#define RCC_APB2ENR_IOPEEN_Pos (6U)
-#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
-#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
-
-
-
-
-/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN_Pos (0U)
-#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos (1U)
-#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos (11U)
-#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos (17U)
-#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos (21U)
-#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
-
-#define RCC_APB1ENR_CAN1EN_Pos (25U)
-#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
-#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
-
-#define RCC_APB1ENR_BKPEN_Pos (27U)
-#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
-#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
-#define RCC_APB1ENR_PWREN_Pos (28U)
-#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
-
-#define RCC_APB1ENR_TIM4EN_Pos (2U)
-#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos (14U)
-#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos (18U)
-#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos (22U)
-#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
-
-#define RCC_APB1ENR_USBEN_Pos (23U)
-#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
-
-
-
-
-
-
-/******************* Bit definition for RCC_BDCR register *******************/
-#define RCC_BDCR_LSEON_Pos (0U)
-#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
-#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
-#define RCC_BDCR_LSERDY_Pos (1U)
-#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
-#define RCC_BDCR_LSEBYP_Pos (2U)
-#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
-
-#define RCC_BDCR_RTCSEL_Pos (8U)
-#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
-
-/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define RCC_BDCR_RTCEN_Pos (15U)
-#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
-#define RCC_BDCR_BDRST_Pos (16U)
-#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
-#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
-
-/******************* Bit definition for RCC_CSR register ********************/
-#define RCC_CSR_LSION_Pos (0U)
-#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
-#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos (1U)
-#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_RMVF_Pos (24U)
-#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
-#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
-#define RCC_CSR_PINRSTF_Pos (26U)
-#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos (27U)
-#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos (28U)
-#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos (29U)
-#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos (30U)
-#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos (31U)
-#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
-
-
-
-/******************************************************************************/
-/* */
-/* General Purpose and Alternate Function I/O */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for GPIO_CRL register *******************/
-#define GPIO_CRL_MODE_Pos (0U)
-#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
-#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
-
-#define GPIO_CRL_MODE0_Pos (0U)
-#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
-#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
-#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
-
-#define GPIO_CRL_MODE1_Pos (4U)
-#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
-#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
-#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
-
-#define GPIO_CRL_MODE2_Pos (8U)
-#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
-#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
-#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
-
-#define GPIO_CRL_MODE3_Pos (12U)
-#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
-#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
-#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
-
-#define GPIO_CRL_MODE4_Pos (16U)
-#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
-#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
-#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
-
-#define GPIO_CRL_MODE5_Pos (20U)
-#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
-#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
-#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
-
-#define GPIO_CRL_MODE6_Pos (24U)
-#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
-#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
-#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
-
-#define GPIO_CRL_MODE7_Pos (28U)
-#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
-#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
-#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
-
-#define GPIO_CRL_CNF_Pos (2U)
-#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
-#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
-
-#define GPIO_CRL_CNF0_Pos (2U)
-#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
-#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
-#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
-
-#define GPIO_CRL_CNF1_Pos (6U)
-#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
-#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
-#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
-
-#define GPIO_CRL_CNF2_Pos (10U)
-#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
-#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
-#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
-
-#define GPIO_CRL_CNF3_Pos (14U)
-#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
-#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
-#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
-
-#define GPIO_CRL_CNF4_Pos (18U)
-#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
-#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
-#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
-
-#define GPIO_CRL_CNF5_Pos (22U)
-#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
-#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
-#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
-
-#define GPIO_CRL_CNF6_Pos (26U)
-#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
-#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
-#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
-
-#define GPIO_CRL_CNF7_Pos (30U)
-#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
-#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
-#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
-
-/******************* Bit definition for GPIO_CRH register *******************/
-#define GPIO_CRH_MODE_Pos (0U)
-#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
-#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
-
-#define GPIO_CRH_MODE8_Pos (0U)
-#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
-#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
-#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
-
-#define GPIO_CRH_MODE9_Pos (4U)
-#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
-#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
-#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
-
-#define GPIO_CRH_MODE10_Pos (8U)
-#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
-#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
-#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
-
-#define GPIO_CRH_MODE11_Pos (12U)
-#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
-#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
-#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
-
-#define GPIO_CRH_MODE12_Pos (16U)
-#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
-#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
-#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
-
-#define GPIO_CRH_MODE13_Pos (20U)
-#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
-#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
-#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
-
-#define GPIO_CRH_MODE14_Pos (24U)
-#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
-#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
-#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
-
-#define GPIO_CRH_MODE15_Pos (28U)
-#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
-#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
-#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
-
-#define GPIO_CRH_CNF_Pos (2U)
-#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
-#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
-
-#define GPIO_CRH_CNF8_Pos (2U)
-#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
-#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
-#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
-
-#define GPIO_CRH_CNF9_Pos (6U)
-#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
-#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
-#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
-
-#define GPIO_CRH_CNF10_Pos (10U)
-#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
-#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
-#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
-
-#define GPIO_CRH_CNF11_Pos (14U)
-#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
-#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
-#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
-
-#define GPIO_CRH_CNF12_Pos (18U)
-#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
-#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
-#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
-
-#define GPIO_CRH_CNF13_Pos (22U)
-#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
-#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
-#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
-
-#define GPIO_CRH_CNF14_Pos (26U)
-#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
-#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
-#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
-
-#define GPIO_CRH_CNF15_Pos (30U)
-#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
-#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
-#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
-
-/*!<****************** Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_IDR0_Pos (0U)
-#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
-#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
-#define GPIO_IDR_IDR1_Pos (1U)
-#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
-#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
-#define GPIO_IDR_IDR2_Pos (2U)
-#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
-#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
-#define GPIO_IDR_IDR3_Pos (3U)
-#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
-#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
-#define GPIO_IDR_IDR4_Pos (4U)
-#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
-#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
-#define GPIO_IDR_IDR5_Pos (5U)
-#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
-#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
-#define GPIO_IDR_IDR6_Pos (6U)
-#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
-#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
-#define GPIO_IDR_IDR7_Pos (7U)
-#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
-#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
-#define GPIO_IDR_IDR8_Pos (8U)
-#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
-#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
-#define GPIO_IDR_IDR9_Pos (9U)
-#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
-#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
-#define GPIO_IDR_IDR10_Pos (10U)
-#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
-#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
-#define GPIO_IDR_IDR11_Pos (11U)
-#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
-#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
-#define GPIO_IDR_IDR12_Pos (12U)
-#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
-#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
-#define GPIO_IDR_IDR13_Pos (13U)
-#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
-#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
-#define GPIO_IDR_IDR14_Pos (14U)
-#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
-#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
-#define GPIO_IDR_IDR15_Pos (15U)
-#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
-#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
-
-/******************* Bit definition for GPIO_ODR register *******************/
-#define GPIO_ODR_ODR0_Pos (0U)
-#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
-#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
-#define GPIO_ODR_ODR1_Pos (1U)
-#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
-#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
-#define GPIO_ODR_ODR2_Pos (2U)
-#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
-#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
-#define GPIO_ODR_ODR3_Pos (3U)
-#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
-#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
-#define GPIO_ODR_ODR4_Pos (4U)
-#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
-#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
-#define GPIO_ODR_ODR5_Pos (5U)
-#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
-#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
-#define GPIO_ODR_ODR6_Pos (6U)
-#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
-#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
-#define GPIO_ODR_ODR7_Pos (7U)
-#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
-#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
-#define GPIO_ODR_ODR8_Pos (8U)
-#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
-#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
-#define GPIO_ODR_ODR9_Pos (9U)
-#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
-#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
-#define GPIO_ODR_ODR10_Pos (10U)
-#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
-#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
-#define GPIO_ODR_ODR11_Pos (11U)
-#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
-#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
-#define GPIO_ODR_ODR12_Pos (12U)
-#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
-#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
-#define GPIO_ODR_ODR13_Pos (13U)
-#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
-#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
-#define GPIO_ODR_ODR14_Pos (14U)
-#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
-#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
-#define GPIO_ODR_ODR15_Pos (15U)
-#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
-#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
-
-/****************** Bit definition for GPIO_BSRR register *******************/
-#define GPIO_BSRR_BS0_Pos (0U)
-#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
-#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
-#define GPIO_BSRR_BS1_Pos (1U)
-#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
-#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
-#define GPIO_BSRR_BS2_Pos (2U)
-#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
-#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
-#define GPIO_BSRR_BS3_Pos (3U)
-#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
-#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
-#define GPIO_BSRR_BS4_Pos (4U)
-#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
-#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
-#define GPIO_BSRR_BS5_Pos (5U)
-#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
-#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
-#define GPIO_BSRR_BS6_Pos (6U)
-#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
-#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
-#define GPIO_BSRR_BS7_Pos (7U)
-#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
-#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
-#define GPIO_BSRR_BS8_Pos (8U)
-#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
-#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
-#define GPIO_BSRR_BS9_Pos (9U)
-#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
-#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
-#define GPIO_BSRR_BS10_Pos (10U)
-#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
-#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
-#define GPIO_BSRR_BS11_Pos (11U)
-#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
-#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
-#define GPIO_BSRR_BS12_Pos (12U)
-#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
-#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
-#define GPIO_BSRR_BS13_Pos (13U)
-#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
-#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
-#define GPIO_BSRR_BS14_Pos (14U)
-#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
-#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
-#define GPIO_BSRR_BS15_Pos (15U)
-#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
-#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
-
-#define GPIO_BSRR_BR0_Pos (16U)
-#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
-#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
-#define GPIO_BSRR_BR1_Pos (17U)
-#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
-#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
-#define GPIO_BSRR_BR2_Pos (18U)
-#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
-#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
-#define GPIO_BSRR_BR3_Pos (19U)
-#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
-#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
-#define GPIO_BSRR_BR4_Pos (20U)
-#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
-#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
-#define GPIO_BSRR_BR5_Pos (21U)
-#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
-#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
-#define GPIO_BSRR_BR6_Pos (22U)
-#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
-#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
-#define GPIO_BSRR_BR7_Pos (23U)
-#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
-#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
-#define GPIO_BSRR_BR8_Pos (24U)
-#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
-#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
-#define GPIO_BSRR_BR9_Pos (25U)
-#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
-#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
-#define GPIO_BSRR_BR10_Pos (26U)
-#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
-#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
-#define GPIO_BSRR_BR11_Pos (27U)
-#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
-#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
-#define GPIO_BSRR_BR12_Pos (28U)
-#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
-#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
-#define GPIO_BSRR_BR13_Pos (29U)
-#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
-#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
-#define GPIO_BSRR_BR14_Pos (30U)
-#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
-#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
-#define GPIO_BSRR_BR15_Pos (31U)
-#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
-#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
-
-/******************* Bit definition for GPIO_BRR register *******************/
-#define GPIO_BRR_BR0_Pos (0U)
-#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
-#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
-#define GPIO_BRR_BR1_Pos (1U)
-#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
-#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
-#define GPIO_BRR_BR2_Pos (2U)
-#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
-#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
-#define GPIO_BRR_BR3_Pos (3U)
-#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
-#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
-#define GPIO_BRR_BR4_Pos (4U)
-#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
-#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
-#define GPIO_BRR_BR5_Pos (5U)
-#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
-#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
-#define GPIO_BRR_BR6_Pos (6U)
-#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
-#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
-#define GPIO_BRR_BR7_Pos (7U)
-#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
-#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
-#define GPIO_BRR_BR8_Pos (8U)
-#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
-#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
-#define GPIO_BRR_BR9_Pos (9U)
-#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
-#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
-#define GPIO_BRR_BR10_Pos (10U)
-#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
-#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
-#define GPIO_BRR_BR11_Pos (11U)
-#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
-#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
-#define GPIO_BRR_BR12_Pos (12U)
-#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
-#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
-#define GPIO_BRR_BR13_Pos (13U)
-#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
-#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
-#define GPIO_BRR_BR14_Pos (14U)
-#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
-#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
-#define GPIO_BRR_BR15_Pos (15U)
-#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
-#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
-
-/****************** Bit definition for GPIO_LCKR register *******************/
-#define GPIO_LCKR_LCK0_Pos (0U)
-#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
-#define GPIO_LCKR_LCK1_Pos (1U)
-#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
-#define GPIO_LCKR_LCK2_Pos (2U)
-#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
-#define GPIO_LCKR_LCK3_Pos (3U)
-#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
-#define GPIO_LCKR_LCK4_Pos (4U)
-#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
-#define GPIO_LCKR_LCK5_Pos (5U)
-#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
-#define GPIO_LCKR_LCK6_Pos (6U)
-#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
-#define GPIO_LCKR_LCK7_Pos (7U)
-#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
-#define GPIO_LCKR_LCK8_Pos (8U)
-#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
-#define GPIO_LCKR_LCK9_Pos (9U)
-#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
-#define GPIO_LCKR_LCK10_Pos (10U)
-#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
-#define GPIO_LCKR_LCK11_Pos (11U)
-#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
-#define GPIO_LCKR_LCK12_Pos (12U)
-#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
-#define GPIO_LCKR_LCK13_Pos (13U)
-#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
-#define GPIO_LCKR_LCK14_Pos (14U)
-#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
-#define GPIO_LCKR_LCK15_Pos (15U)
-#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
-#define GPIO_LCKR_LCKK_Pos (16U)
-#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for AFIO_EVCR register *******************/
-#define AFIO_EVCR_PIN_Pos (0U)
-#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
-#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
-#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
-#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
-#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
-#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
-
-/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
-#define AFIO_EVCR_PIN_PX1_Pos (0U)
-#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
-#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
-#define AFIO_EVCR_PIN_PX2_Pos (1U)
-#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
-#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
-#define AFIO_EVCR_PIN_PX3_Pos (0U)
-#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
-#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
-#define AFIO_EVCR_PIN_PX4_Pos (2U)
-#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
-#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
-#define AFIO_EVCR_PIN_PX5_Pos (0U)
-#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
-#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
-#define AFIO_EVCR_PIN_PX6_Pos (1U)
-#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
-#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
-#define AFIO_EVCR_PIN_PX7_Pos (0U)
-#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
-#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
-#define AFIO_EVCR_PIN_PX8_Pos (3U)
-#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
-#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
-#define AFIO_EVCR_PIN_PX9_Pos (0U)
-#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
-#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
-#define AFIO_EVCR_PIN_PX10_Pos (1U)
-#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
-#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
-#define AFIO_EVCR_PIN_PX11_Pos (0U)
-#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
-#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
-#define AFIO_EVCR_PIN_PX12_Pos (2U)
-#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
-#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
-#define AFIO_EVCR_PIN_PX13_Pos (0U)
-#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
-#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
-#define AFIO_EVCR_PIN_PX14_Pos (1U)
-#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
-#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
-#define AFIO_EVCR_PIN_PX15_Pos (0U)
-#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
-#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
-
-#define AFIO_EVCR_PORT_Pos (4U)
-#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
-#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
-#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
-#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
-#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
-
-/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
-#define AFIO_EVCR_PORT_PB_Pos (4U)
-#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
-#define AFIO_EVCR_PORT_PC_Pos (5U)
-#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
-#define AFIO_EVCR_PORT_PD_Pos (4U)
-#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
-#define AFIO_EVCR_PORT_PE_Pos (6U)
-#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
-
-#define AFIO_EVCR_EVOE_Pos (7U)
-#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
-#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
-
-/****************** Bit definition for AFIO_MAPR register *******************/
-#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
-#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
-#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
-#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
-#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
-#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
-#define AFIO_MAPR_USART1_REMAP_Pos (2U)
-#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
-#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
-#define AFIO_MAPR_USART2_REMAP_Pos (3U)
-#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
-#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
-
-#define AFIO_MAPR_USART3_REMAP_Pos (4U)
-#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
-#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
-#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
-
-/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
-#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
-#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
-#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
-
-/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
-#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
-#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
-#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
-
-/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
-#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
-#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
-#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
-
-/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
-#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
-#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
-
-#define AFIO_MAPR_CAN_REMAP_Pos (13U)
-#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
-#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
-#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
-
-/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_MAPR_PD01_REMAP_Pos (15U)
-#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
-#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-
-/*!< SWJ_CFG configuration */
-#define AFIO_MAPR_SWJ_CFG_Pos (24U)
-#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
-#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
-#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
-#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-
-#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
-
-
-/***************** Bit definition for AFIO_EXTICR1 register *****************/
-#define AFIO_EXTICR1_EXTI0_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
-
-/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
-#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
-#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
-#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
-
-/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
-#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
-#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
-#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
-
-/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
-#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
-#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
-#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
-
-/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
-#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
-#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
-#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
-
-/***************** Bit definition for AFIO_EXTICR2 register *****************/
-#define AFIO_EXTICR2_EXTI4_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI5_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI6_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI7_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
-
-/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
-#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
-#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
-#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
-#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
-#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
-#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
-#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
-#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
-#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
-
-/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
-#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
-#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
-#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
-#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
-#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
-#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
-#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
-#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
-#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
-
-/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
-#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
-#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
-#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
-#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
-#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
-#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
-#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
-#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
-#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
-
-/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
-#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
-#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
-#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
-#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
-#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
-#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
-#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
-#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
-#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
-
-/***************** Bit definition for AFIO_EXTICR3 register *****************/
-#define AFIO_EXTICR3_EXTI8_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI9_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI10_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI11_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
-
-/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
-#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
-#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
-#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
-#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
-#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
-#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
-#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
-#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
-#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
-
-/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
-#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
-#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
-#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
-#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
-#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
-#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
-#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
-#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
-#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
-
-/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
-#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
-#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
-#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
-#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
-#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
-#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
-#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
-#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
-#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
-
-/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
-#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
-#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
-#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
-#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
-#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
-#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
-#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
-#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
-#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
-
-/***************** Bit definition for AFIO_EXTICR4 register *****************/
-#define AFIO_EXTICR4_EXTI12_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI13_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI14_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI15_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
-
-/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
-#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
-#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
-#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
-#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
-#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
-#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
-#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
-#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
-#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
-
-/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
-#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
-#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
-#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
-#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
-#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
-#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
-#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
-#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
-#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
-
-/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
-#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
-#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
-#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
-#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
-#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
-#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
-#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
-#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
-#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
-
-/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
-#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
-#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
-#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
-#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
-#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
-#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
-#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
-#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
-#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
-
-/****************** Bit definition for AFIO_MAPR2 register ******************/
-
-
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0_Pos (0U)
-#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
-#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos (1U)
-#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
-#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos (2U)
-#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
-#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos (3U)
-#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
-#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos (4U)
-#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
-#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos (5U)
-#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
-#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos (6U)
-#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
-#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos (7U)
-#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
-#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos (8U)
-#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
-#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos (9U)
-#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
-#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos (10U)
-#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
-#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos (11U)
-#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
-#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos (12U)
-#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
-#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos (13U)
-#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
-#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos (14U)
-#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
-#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos (15U)
-#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
-#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos (16U)
-#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
-#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos (17U)
-#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
-#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos (18U)
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-
-/* References Defines */
-#define EXTI_IMR_IM0 EXTI_IMR_MR0
-#define EXTI_IMR_IM1 EXTI_IMR_MR1
-#define EXTI_IMR_IM2 EXTI_IMR_MR2
-#define EXTI_IMR_IM3 EXTI_IMR_MR3
-#define EXTI_IMR_IM4 EXTI_IMR_MR4
-#define EXTI_IMR_IM5 EXTI_IMR_MR5
-#define EXTI_IMR_IM6 EXTI_IMR_MR6
-#define EXTI_IMR_IM7 EXTI_IMR_MR7
-#define EXTI_IMR_IM8 EXTI_IMR_MR8
-#define EXTI_IMR_IM9 EXTI_IMR_MR9
-#define EXTI_IMR_IM10 EXTI_IMR_MR10
-#define EXTI_IMR_IM11 EXTI_IMR_MR11
-#define EXTI_IMR_IM12 EXTI_IMR_MR12
-#define EXTI_IMR_IM13 EXTI_IMR_MR13
-#define EXTI_IMR_IM14 EXTI_IMR_MR14
-#define EXTI_IMR_IM15 EXTI_IMR_MR15
-#define EXTI_IMR_IM16 EXTI_IMR_MR16
-#define EXTI_IMR_IM17 EXTI_IMR_MR17
-#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
-
-/******************* Bit definition for EXTI_EMR register *******************/
-#define EXTI_EMR_MR0_Pos (0U)
-#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
-#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos (1U)
-#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
-#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos (2U)
-#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
-#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos (3U)
-#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
-#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos (4U)
-#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
-#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos (5U)
-#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
-#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos (6U)
-#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
-#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos (7U)
-#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
-#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos (8U)
-#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
-#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos (9U)
-#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
-#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos (10U)
-#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
-#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos (11U)
-#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
-#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos (12U)
-#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
-#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos (13U)
-#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
-#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos (14U)
-#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
-#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos (15U)
-#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
-#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos (16U)
-#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
-#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos (17U)
-#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
-#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos (18U)
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-
-/* References Defines */
-#define EXTI_EMR_EM0 EXTI_EMR_MR0
-#define EXTI_EMR_EM1 EXTI_EMR_MR1
-#define EXTI_EMR_EM2 EXTI_EMR_MR2
-#define EXTI_EMR_EM3 EXTI_EMR_MR3
-#define EXTI_EMR_EM4 EXTI_EMR_MR4
-#define EXTI_EMR_EM5 EXTI_EMR_MR5
-#define EXTI_EMR_EM6 EXTI_EMR_MR6
-#define EXTI_EMR_EM7 EXTI_EMR_MR7
-#define EXTI_EMR_EM8 EXTI_EMR_MR8
-#define EXTI_EMR_EM9 EXTI_EMR_MR9
-#define EXTI_EMR_EM10 EXTI_EMR_MR10
-#define EXTI_EMR_EM11 EXTI_EMR_MR11
-#define EXTI_EMR_EM12 EXTI_EMR_MR12
-#define EXTI_EMR_EM13 EXTI_EMR_MR13
-#define EXTI_EMR_EM14 EXTI_EMR_MR14
-#define EXTI_EMR_EM15 EXTI_EMR_MR15
-#define EXTI_EMR_EM16 EXTI_EMR_MR16
-#define EXTI_EMR_EM17 EXTI_EMR_MR17
-#define EXTI_EMR_EM18 EXTI_EMR_MR18
-
-/****************** Bit definition for EXTI_RTSR register *******************/
-#define EXTI_RTSR_TR0_Pos (0U)
-#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
-#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos (1U)
-#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
-#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos (2U)
-#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
-#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos (3U)
-#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
-#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos (4U)
-#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
-#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos (5U)
-#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
-#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos (6U)
-#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
-#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos (7U)
-#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
-#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos (8U)
-#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
-#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos (9U)
-#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
-#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos (10U)
-#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
-#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos (11U)
-#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
-#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos (12U)
-#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
-#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos (13U)
-#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
-#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos (14U)
-#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
-#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos (15U)
-#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
-#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos (16U)
-#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
-#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos (17U)
-#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
-#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos (18U)
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-
-/* References Defines */
-#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-
-/****************** Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0_Pos (0U)
-#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
-#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos (1U)
-#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
-#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos (2U)
-#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
-#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos (3U)
-#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
-#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos (4U)
-#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
-#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos (5U)
-#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
-#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos (6U)
-#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
-#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos (7U)
-#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
-#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos (8U)
-#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
-#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos (9U)
-#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
-#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos (10U)
-#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
-#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos (11U)
-#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
-#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos (12U)
-#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
-#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos (13U)
-#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
-#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos (14U)
-#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
-#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos (15U)
-#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
-#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos (16U)
-#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
-#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos (17U)
-#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
-#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos (18U)
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-
-/* References Defines */
-#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-
-/****************** Bit definition for EXTI_SWIER register ******************/
-#define EXTI_SWIER_SWIER0_Pos (0U)
-#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos (1U)
-#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos (2U)
-#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos (3U)
-#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos (4U)
-#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos (5U)
-#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos (6U)
-#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos (7U)
-#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos (8U)
-#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos (9U)
-#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos (10U)
-#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos (11U)
-#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos (12U)
-#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos (13U)
-#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos (14U)
-#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos (15U)
-#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos (16U)
-#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos (17U)
-#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos (18U)
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-
-/* References Defines */
-#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-
-/******************* Bit definition for EXTI_PR register ********************/
-#define EXTI_PR_PR0_Pos (0U)
-#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
-#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos (1U)
-#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
-#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos (2U)
-#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
-#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos (3U)
-#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
-#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos (4U)
-#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
-#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos (5U)
-#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
-#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos (6U)
-#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
-#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos (7U)
-#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
-#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos (8U)
-#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
-#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos (9U)
-#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
-#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos (10U)
-#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
-#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos (11U)
-#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
-#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos (12U)
-#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
-#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos (13U)
-#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
-#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos (14U)
-#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
-#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos (15U)
-#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
-#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos (16U)
-#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
-#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos (17U)
-#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
-#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos (18U)
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-
-/* References Defines */
-#define EXTI_PR_PIF0 EXTI_PR_PR0
-#define EXTI_PR_PIF1 EXTI_PR_PR1
-#define EXTI_PR_PIF2 EXTI_PR_PR2
-#define EXTI_PR_PIF3 EXTI_PR_PR3
-#define EXTI_PR_PIF4 EXTI_PR_PR4
-#define EXTI_PR_PIF5 EXTI_PR_PR5
-#define EXTI_PR_PIF6 EXTI_PR_PR6
-#define EXTI_PR_PIF7 EXTI_PR_PR7
-#define EXTI_PR_PIF8 EXTI_PR_PR8
-#define EXTI_PR_PIF9 EXTI_PR_PR9
-#define EXTI_PR_PIF10 EXTI_PR_PR10
-#define EXTI_PR_PIF11 EXTI_PR_PR11
-#define EXTI_PR_PIF12 EXTI_PR_PR12
-#define EXTI_PR_PIF13 EXTI_PR_PR13
-#define EXTI_PR_PIF14 EXTI_PR_PR14
-#define EXTI_PR_PIF15 EXTI_PR_PR15
-#define EXTI_PR_PIF16 EXTI_PR_PR16
-#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-
-/******************************************************************************/
-/* */
-/* DMA Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1_Pos (0U)
-#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
-#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos (1U)
-#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
-#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos (2U)
-#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
-#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos (3U)
-#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
-#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos (4U)
-#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
-#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos (5U)
-#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
-#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos (6U)
-#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
-#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos (7U)
-#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
-#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos (8U)
-#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
-#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos (9U)
-#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
-#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos (10U)
-#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
-#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos (11U)
-#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
-#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos (12U)
-#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
-#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos (13U)
-#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
-#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos (14U)
-#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
-#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos (15U)
-#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
-#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos (16U)
-#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
-#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos (17U)
-#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
-#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos (18U)
-#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
-#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos (19U)
-#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
-#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos (20U)
-#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
-#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos (21U)
-#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
-#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos (22U)
-#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
-#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos (23U)
-#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
-#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos (24U)
-#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
-#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos (25U)
-#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
-#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos (26U)
-#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
-#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos (27U)
-#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
-#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
-
-/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1_Pos (0U)
-#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos (1U)
-#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos (2U)
-#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos (3U)
-#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos (4U)
-#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos (5U)
-#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos (6U)
-#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos (7U)
-#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos (8U)
-#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos (9U)
-#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos (10U)
-#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos (11U)
-#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos (12U)
-#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos (13U)
-#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos (14U)
-#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos (15U)
-#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos (16U)
-#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos (17U)
-#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos (18U)
-#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos (19U)
-#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos (20U)
-#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos (21U)
-#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos (22U)
-#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos (23U)
-#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos (24U)
-#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos (25U)
-#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos (26U)
-#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos (27U)
-#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
-
-/******************* Bit definition for DMA_CCR register *******************/
-#define DMA_CCR_EN_Pos (0U)
-#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
-#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
-#define DMA_CCR_TCIE_Pos (1U)
-#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
-#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos (2U)
-#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
-#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos (3U)
-#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
-#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos (4U)
-#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
-#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos (5U)
-#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
-#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
-#define DMA_CCR_PINC_Pos (6U)
-#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
-#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos (7U)
-#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
-#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos (8U)
-#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
-#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos (10U)
-#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos (12U)
-#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
-#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
-#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos (14U)
-#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
-
-/****************** Bit definition for DMA_CNDTR register ******************/
-#define DMA_CNDTR_NDT_Pos (0U)
-#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CPAR register *******************/
-#define DMA_CPAR_PA_Pos (0U)
-#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CMAR register *******************/
-#define DMA_CMAR_MA_Pos (0U)
-#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter (ADC) */
-/* */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
- */
-#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
-
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD_Pos (0U)
-#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
-#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOS_Pos (1U)
-#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
-#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos (2U)
-#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
-#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos (3U)
-#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
-#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos (4U)
-#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
-#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
-
-/* Legacy defines */
-#define ADC_SR_EOC (ADC_SR_EOS)
-#define ADC_SR_JEOC (ADC_SR_JEOS)
-
-/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH_Pos (0U)
-#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
-#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
-
-#define ADC_CR1_EOSIE_Pos (5U)
-#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
-#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos (6U)
-#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
-#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos (7U)
-#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos (8U)
-#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
-#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos (9U)
-#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos (10U)
-#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
-#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos (11U)
-#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
-#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos (12U)
-#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos (13U)
-#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
-
-#define ADC_CR1_DUALMOD_Pos (16U)
-#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
-#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
-#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
-#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
-#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
-#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
-
-#define ADC_CR1_JAWDEN_Pos (22U)
-#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos (23U)
-#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
-#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-/* Legacy defines */
-#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
-#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
-
-/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON_Pos (0U)
-#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
-#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
-#define ADC_CR2_CONT_Pos (1U)
-#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
-#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CAL_Pos (2U)
-#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
-#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
-#define ADC_CR2_RSTCAL_Pos (3U)
-#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
-#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
-#define ADC_CR2_DMA_Pos (8U)
-#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
-#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
-#define ADC_CR2_ALIGN_Pos (11U)
-#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos (12U)
-#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
-#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
-#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
-#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
-
-#define ADC_CR2_JEXTTRIG_Pos (15U)
-#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
-#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
-
-#define ADC_CR2_EXTSEL_Pos (17U)
-#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
-#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
-#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
-#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
-
-#define ADC_CR2_EXTTRIG_Pos (20U)
-#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
-#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
-#define ADC_CR2_JSWSTART_Pos (21U)
-#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
-#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
-#define ADC_CR2_SWSTART_Pos (22U)
-#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
-#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
-#define ADC_CR2_TSVREFE_Pos (23U)
-#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
-#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP10_Pos (0U)
-#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
-#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
-#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
-#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP11_Pos (3U)
-#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
-#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
-#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
-#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP12_Pos (6U)
-#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
-#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
-#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP13_Pos (9U)
-#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
-#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
-#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP14_Pos (12U)
-#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
-#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
-#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
-#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP15_Pos (15U)
-#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
-#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
-#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
-#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
-#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP16_Pos (18U)
-#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
-#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
-#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP17_Pos (21U)
-#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
-#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
-#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
-
-/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP0_Pos (0U)
-#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
-#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
-#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
-#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP1_Pos (3U)
-#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
-#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
-#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
-#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP2_Pos (6U)
-#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
-#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
-#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP3_Pos (9U)
-#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
-#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
-#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP4_Pos (12U)
-#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
-#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
-#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
-#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP5_Pos (15U)
-#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
-#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
-#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
-#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP6_Pos (18U)
-#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
-#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
-#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP7_Pos (21U)
-#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
-#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
-#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP8_Pos (24U)
-#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
-#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
-#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
-#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP9_Pos (27U)
-#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
-#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
-#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
-#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
-
-/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1_Pos (0U)
-#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
-
-/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2_Pos (0U)
-#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
-
-/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3_Pos (0U)
-#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
-
-/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4_Pos (0U)
-#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
-
-/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT_Pos (0U)
-#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
-#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
-
-/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT_Pos (0U)
-#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
-#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
-
-/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ13_Pos (0U)
-#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
-#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
-#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
-#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
-#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
-#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR1_SQ14_Pos (5U)
-#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
-#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
-#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
-#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
-#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
-#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ15_Pos (10U)
-#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
-#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
-#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
-#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
-#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
-#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ16_Pos (15U)
-#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
-#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
-#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
-#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
-#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
-#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
-
-#define ADC_SQR1_L_Pos (20U)
-#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
-#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
-#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
-#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
-
-/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ7_Pos (0U)
-#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
-#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
-#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
-#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
-#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
-#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ8_Pos (5U)
-#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
-#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
-#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
-#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
-#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
-#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ9_Pos (10U)
-#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
-#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
-#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
-#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
-#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
-#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ10_Pos (15U)
-#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
-#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
-#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
-#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
-#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
-#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ11_Pos (20U)
-#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
-#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
-#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
-#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
-#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
-#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ12_Pos (25U)
-#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
-#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
-#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
-#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
-#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
-#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
-
-/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ1_Pos (0U)
-#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
-#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
-#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
-#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
-#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
-#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ2_Pos (5U)
-#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
-#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
-#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
-#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
-#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
-#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ3_Pos (10U)
-#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
-#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
-#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
-#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
-#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
-#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ4_Pos (15U)
-#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
-#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
-#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
-#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
-#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
-#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ5_Pos (20U)
-#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
-#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
-#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
-#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
-#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
-#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ6_Pos (25U)
-#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
-#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
-#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
-#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
-#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
-#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
-
-/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1_Pos (0U)
-#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos (5U)
-#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos (10U)
-#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos (15U)
-#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos (20U)
-#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
-#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
-#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
-
-/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
-
-/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
-
-/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
-
-/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA_Pos (0U)
-#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
-#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
-#define ADC_DR_ADC2DATA_Pos (16U)
-#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
-#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
-
-
-/*****************************************************************************/
-/* */
-/* Timers (TIM) */
-/* */
-/*****************************************************************************/
-/******************* Bit definition for TIM_CR1 register *******************/
-#define TIM_CR1_CEN_Pos (0U)
-#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
-#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos (1U)
-#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
-#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
-#define TIM_CR1_URS_Pos (2U)
-#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
-#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
-#define TIM_CR1_OPM_Pos (3U)
-#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
-#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos (4U)
-#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
-#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
-
-#define TIM_CR1_CMS_Pos (5U)
-#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
-#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
-#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos (7U)
-#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
-#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos (8U)
-#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
-#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
-#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
-
-/******************* Bit definition for TIM_CR2 register *******************/
-#define TIM_CR2_CCPC_Pos (0U)
-#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
-#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS_Pos (2U)
-#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
-#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos (3U)
-#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
-#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos (4U)
-#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
-#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
-#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
-#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos (7U)
-#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
-#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos (8U)
-#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
-#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N_Pos (9U)
-#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
-#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos (10U)
-#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
-#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N_Pos (11U)
-#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
-#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos (12U)
-#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
-#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N_Pos (13U)
-#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
-#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos (14U)
-#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
-#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register ******************/
-#define TIM_SMCR_SMS_Pos (0U)
-#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
-#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos (4U)
-#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
-#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
-#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
-#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos (7U)
-#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
-#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos (8U)
-#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
-#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos (12U)
-#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
-#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos (14U)
-#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
-#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos (15U)
-#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
-#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register ******************/
-#define TIM_DIER_UIE_Pos (0U)
-#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
-#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos (1U)
-#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
-#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos (2U)
-#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
-#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos (3U)
-#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
-#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos (4U)
-#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
-#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE_Pos (5U)
-#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
-#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
-#define TIM_DIER_TIE_Pos (6U)
-#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
-#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE_Pos (7U)
-#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
-#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
-#define TIM_DIER_UDE_Pos (8U)
-#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
-#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos (9U)
-#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
-#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos (10U)
-#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
-#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos (11U)
-#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
-#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos (12U)
-#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
-#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos (13U)
-#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
-#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos (14U)
-#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
-#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register *******************/
-#define TIM_SR_UIF_Pos (0U)
-#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
-#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos (1U)
-#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
-#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos (2U)
-#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
-#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos (3U)
-#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
-#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos (4U)
-#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
-#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF_Pos (5U)
-#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
-#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
-#define TIM_SR_TIF_Pos (6U)
-#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
-#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF_Pos (7U)
-#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
-#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF_Pos (9U)
-#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
-#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos (10U)
-#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
-#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos (11U)
-#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
-#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos (12U)
-#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
-#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register *******************/
-#define TIM_EGR_UG_Pos (0U)
-#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
-#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos (1U)
-#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
-#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos (2U)
-#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
-#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos (3U)
-#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
-#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos (4U)
-#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
-#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG_Pos (5U)
-#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
-#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos (6U)
-#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
-#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
-#define TIM_EGR_BG_Pos (7U)
-#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
-#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register ******************/
-#define TIM_CCMR1_CC1S_Pos (0U)
-#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos (2U)
-#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos (3U)
-#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos (4U)
-#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos (7U)
-#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos (8U)
-#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos (10U)
-#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos (11U)
-#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos (12U)
-#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos (15U)
-#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
-
-/*---------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos (2U)
-#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos (4U)
-#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos (10U)
-#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos (12U)
-#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
-
-/****************** Bit definition for TIM_CCMR2 register ******************/
-#define TIM_CCMR2_CC3S_Pos (0U)
-#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos (2U)
-#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos (3U)
-#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos (4U)
-#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos (7U)
-#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos (8U)
-#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos (10U)
-#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos (11U)
-#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos (12U)
-#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos (15U)
-#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
-
-/*---------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos (2U)
-#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos (4U)
-#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos (10U)
-#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos (12U)
-#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
-
-/******************* Bit definition for TIM_CCER register ******************/
-#define TIM_CCER_CC1E_Pos (0U)
-#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
-#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos (1U)
-#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
-#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE_Pos (2U)
-#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
-#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP_Pos (3U)
-#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
-#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos (4U)
-#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
-#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos (5U)
-#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
-#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE_Pos (6U)
-#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
-#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP_Pos (7U)
-#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
-#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos (8U)
-#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
-#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos (9U)
-#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
-#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE_Pos (10U)
-#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
-#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP_Pos (11U)
-#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
-#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos (12U)
-#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
-#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos (13U)
-#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
-#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-
-/******************* Bit definition for TIM_CNT register *******************/
-#define TIM_CNT_CNT_Pos (0U)
-#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
-
-/******************* Bit definition for TIM_PSC register *******************/
-#define TIM_PSC_PSC_Pos (0U)
-#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
-#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register *******************/
-#define TIM_ARR_ARR_Pos (0U)
-#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register *******************/
-#define TIM_RCR_REP_Pos (0U)
-#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
-#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register ******************/
-#define TIM_CCR1_CCR1_Pos (0U)
-#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register ******************/
-#define TIM_CCR2_CCR2_Pos (0U)
-#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register ******************/
-#define TIM_CCR3_CCR3_Pos (0U)
-#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register ******************/
-#define TIM_CCR4_CCR4_Pos (0U)
-#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register ******************/
-#define TIM_BDTR_DTG_Pos (0U)
-#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
-#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
-#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
-#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
-#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
-#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
-#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
-#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
-#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
-
-#define TIM_BDTR_LOCK_Pos (8U)
-#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
-#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
-#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
-
-#define TIM_BDTR_OSSI_Pos (10U)
-#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
-#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos (11U)
-#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
-#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE_Pos (12U)
-#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
-#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
-#define TIM_BDTR_BKP_Pos (13U)
-#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
-#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
-#define TIM_BDTR_AOE_Pos (14U)
-#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
-#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
-#define TIM_BDTR_MOE_Pos (15U)
-#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
-#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
-
-/******************* Bit definition for TIM_DCR register *******************/
-#define TIM_DCR_DBA_Pos (0U)
-#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
-#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
-#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
-#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
-#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
-#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos (8U)
-#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
-#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
-#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
-#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
-#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
-#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
-
-/******************* Bit definition for TIM_DMAR register ******************/
-#define TIM_DMAR_DMAB_Pos (0U)
-#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for RTC_CRH register ********************/
-#define RTC_CRH_SECIE_Pos (0U)
-#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
-#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
-#define RTC_CRH_ALRIE_Pos (1U)
-#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
-#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
-#define RTC_CRH_OWIE_Pos (2U)
-#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
-#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
-
-/******************* Bit definition for RTC_CRL register ********************/
-#define RTC_CRL_SECF_Pos (0U)
-#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
-#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
-#define RTC_CRL_ALRF_Pos (1U)
-#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
-#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
-#define RTC_CRL_OWF_Pos (2U)
-#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
-#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
-#define RTC_CRL_RSF_Pos (3U)
-#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
-#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
-#define RTC_CRL_CNF_Pos (4U)
-#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
-#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
-#define RTC_CRL_RTOFF_Pos (5U)
-#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
-#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
-
-/******************* Bit definition for RTC_PRLH register *******************/
-#define RTC_PRLH_PRL_Pos (0U)
-#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
-#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
-
-/******************* Bit definition for RTC_PRLL register *******************/
-#define RTC_PRLL_PRL_Pos (0U)
-#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
-#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
-
-/******************* Bit definition for RTC_DIVH register *******************/
-#define RTC_DIVH_RTC_DIV_Pos (0U)
-#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
-#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
-
-/******************* Bit definition for RTC_DIVL register *******************/
-#define RTC_DIVL_RTC_DIV_Pos (0U)
-#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
-#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
-
-/******************* Bit definition for RTC_CNTH register *******************/
-#define RTC_CNTH_RTC_CNT_Pos (0U)
-#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
-#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
-
-/******************* Bit definition for RTC_CNTL register *******************/
-#define RTC_CNTL_RTC_CNT_Pos (0U)
-#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
-#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
-
-/******************* Bit definition for RTC_ALRH register *******************/
-#define RTC_ALRH_RTC_ALR_Pos (0U)
-#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
-#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
-
-/******************* Bit definition for RTC_ALRL register *******************/
-#define RTC_ALRL_RTC_ALR_Pos (0U)
-#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
-#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG (IWDG) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY_Pos (0U)
-#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
-#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR_Pos (0U)
-#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
-#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
-#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
-#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL_Pos (0U)
-#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
-#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU_Pos (0U)
-#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
-#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos (1U)
-#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
-#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG (WWDG) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T_Pos (0U)
-#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
-#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
-#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
-#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
-#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
-#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
-#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
-#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
-
-/* Legacy defines */
-#define WWDG_CR_T0 WWDG_CR_T_0
-#define WWDG_CR_T1 WWDG_CR_T_1
-#define WWDG_CR_T2 WWDG_CR_T_2
-#define WWDG_CR_T3 WWDG_CR_T_3
-#define WWDG_CR_T4 WWDG_CR_T_4
-#define WWDG_CR_T5 WWDG_CR_T_5
-#define WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos (7U)
-#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
-#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W_Pos (0U)
-#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
-#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
-#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
-#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
-#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
-#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
-#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
-#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
-
-/* Legacy defines */
-#define WWDG_CFR_W0 WWDG_CFR_W_0
-#define WWDG_CFR_W1 WWDG_CFR_W_1
-#define WWDG_CFR_W2 WWDG_CFR_W_2
-#define WWDG_CFR_W3 WWDG_CFR_W_3
-#define WWDG_CFR_W4 WWDG_CFR_W_4
-#define WWDG_CFR_W5 WWDG_CFR_W_5
-#define WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos (7U)
-#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
-
-/* Legacy defines */
-#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos (9U)
-#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
-#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF_Pos (0U)
-#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
-#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/* */
-/* SD host Interface */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for SDIO_POWER register ******************/
-#define SDIO_POWER_PWRCTRL_Pos (0U)
-#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
-#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
-#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
-
-/****************** Bit definition for SDIO_CLKCR register ******************/
-#define SDIO_CLKCR_CLKDIV_Pos (0U)
-#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
-#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
-#define SDIO_CLKCR_CLKEN_Pos (8U)
-#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
-#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
-#define SDIO_CLKCR_PWRSAV_Pos (9U)
-#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
-#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS_Pos (10U)
-#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
-#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS_Pos (11U)
-#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
-#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
-#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
-
-#define SDIO_CLKCR_NEGEDGE_Pos (13U)
-#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
-#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN_Pos (14U)
-#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
-#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
-
-/******************* Bit definition for SDIO_ARG register *******************/
-#define SDIO_ARG_CMDARG_Pos (0U)
-#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
-
-/******************* Bit definition for SDIO_CMD register *******************/
-#define SDIO_CMD_CMDINDEX_Pos (0U)
-#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
-#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
-
-#define SDIO_CMD_WAITRESP_Pos (6U)
-#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
-#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
-#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
-
-#define SDIO_CMD_WAITINT_Pos (8U)
-#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
-#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND_Pos (9U)
-#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
-#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN_Pos (10U)
-#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
-#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
-#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
-#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
-#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
-#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
-#define SDIO_CMD_NIEN_Pos (13U)
-#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
-#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD_Pos (14U)
-#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
-#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
-
-/***************** Bit definition for SDIO_RESPCMD register *****************/
-#define SDIO_RESPCMD_RESPCMD_Pos (0U)
-#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
-#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
-
-/****************** Bit definition for SDIO_RESP0 register ******************/
-#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
-#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP1 register ******************/
-#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
-#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP2 register ******************/
-#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
-#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP3 register ******************/
-#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
-#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP4 register ******************/
-#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
-#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_DTIMER register *****************/
-#define SDIO_DTIMER_DATATIME_Pos (0U)
-#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
-
-/****************** Bit definition for SDIO_DLEN register *******************/
-#define SDIO_DLEN_DATALENGTH_Pos (0U)
-#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
-
-/****************** Bit definition for SDIO_DCTRL register ******************/
-#define SDIO_DCTRL_DTEN_Pos (0U)
-#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
-#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR_Pos (1U)
-#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
-#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE_Pos (2U)
-#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
-#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN_Pos (3U)
-#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
-#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
-#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
-#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
-#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
-#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
-#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
-
-#define SDIO_DCTRL_RWSTART_Pos (8U)
-#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
-#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
-#define SDIO_DCTRL_RWSTOP_Pos (9U)
-#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
-#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
-#define SDIO_DCTRL_RWMOD_Pos (10U)
-#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
-#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
-#define SDIO_DCTRL_SDIOEN_Pos (11U)
-#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
-#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
-
-/****************** Bit definition for SDIO_DCOUNT register *****************/
-#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
-#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
-
-/****************** Bit definition for SDIO_STA register ********************/
-#define SDIO_STA_CCRCFAIL_Pos (0U)
-#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
-#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL_Pos (1U)
-#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
-#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT_Pos (2U)
-#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
-#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
-#define SDIO_STA_DTIMEOUT_Pos (3U)
-#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
-#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
-#define SDIO_STA_TXUNDERR_Pos (4U)
-#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
-#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR_Pos (5U)
-#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
-#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
-#define SDIO_STA_CMDREND_Pos (6U)
-#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
-#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT_Pos (7U)
-#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
-#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
-#define SDIO_STA_DATAEND_Pos (8U)
-#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
-#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR_Pos (9U)
-#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
-#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND_Pos (10U)
-#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
-#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT_Pos (11U)
-#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
-#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
-#define SDIO_STA_TXACT_Pos (12U)
-#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
-#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
-#define SDIO_STA_RXACT_Pos (13U)
-#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
-#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
-#define SDIO_STA_TXFIFOHE_Pos (14U)
-#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
-#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF_Pos (15U)
-#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
-#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF_Pos (16U)
-#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
-#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
-#define SDIO_STA_RXFIFOF_Pos (17U)
-#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
-#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
-#define SDIO_STA_TXFIFOE_Pos (18U)
-#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
-#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE_Pos (19U)
-#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
-#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
-#define SDIO_STA_TXDAVL_Pos (20U)
-#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
-#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL_Pos (21U)
-#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
-#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
-#define SDIO_STA_SDIOIT_Pos (22U)
-#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
-#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
-#define SDIO_STA_CEATAEND_Pos (23U)
-#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
-#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
-
-/******************* Bit definition for SDIO_ICR register *******************/
-#define SDIO_ICR_CCRCFAILC_Pos (0U)
-#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
-#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC_Pos (1U)
-#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
-#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC_Pos (2U)
-#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
-#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC_Pos (3U)
-#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
-#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC_Pos (4U)
-#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
-#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC_Pos (5U)
-#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
-#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC_Pos (6U)
-#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
-#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC_Pos (7U)
-#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
-#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC_Pos (8U)
-#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
-#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC_Pos (9U)
-#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
-#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC_Pos (10U)
-#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
-#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC_Pos (22U)
-#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
-#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC_Pos (23U)
-#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
-#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
-
-/****************** Bit definition for SDIO_MASK register *******************/
-#define SDIO_MASK_CCRCFAILIE_Pos (0U)
-#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
-#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE_Pos (1U)
-#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
-#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
-#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
-#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
-#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
-#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE_Pos (4U)
-#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
-#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE_Pos (5U)
-#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
-#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE_Pos (6U)
-#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
-#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE_Pos (7U)
-#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
-#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE_Pos (8U)
-#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
-#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE_Pos (9U)
-#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
-#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE_Pos (10U)
-#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
-#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE_Pos (11U)
-#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
-#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE_Pos (12U)
-#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
-#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE_Pos (13U)
-#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
-#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
-#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
-#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
-#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
-#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE_Pos (16U)
-#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
-#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE_Pos (17U)
-#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
-#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE_Pos (18U)
-#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
-#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE_Pos (19U)
-#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
-#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE_Pos (20U)
-#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
-#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE_Pos (21U)
-#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
-#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE_Pos (22U)
-#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
-#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE_Pos (23U)
-#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
-#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/***************** Bit definition for SDIO_FIFOCNT register *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
-#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
-
-/****************** Bit definition for SDIO_FIFO register *******************/
-#define SDIO_FIFO_FIFODATA_Pos (0U)
-#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/* */
-/* USB Device FS */
-/* */
-/******************************************************************************/
-
-/*!< Endpoint-specific registers */
-#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
-#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
-#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
-#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
-#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
-#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
-#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
-#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
-
-/* bit positions */
-#define USB_EP_CTR_RX_Pos (15U)
-#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos (14U)
-#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos (12U)
-#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
-#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos (11U)
-#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos (9U)
-#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
-#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
-#define USB_EP_KIND_Pos (8U)
-#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
-#define USB_EP_CTR_TX_Pos (7U)
-#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos (6U)
-#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos (4U)
-#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
-#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos (0U)
-#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
-#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
- /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos (9U)
-#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
-#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************* Bit definition for USB_EP0R register *******************/
-#define USB_EP0R_EA_Pos (0U)
-#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos (4U)
-#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos (6U)
-#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos (7U)
-#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos (8U)
-#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos (9U)
-#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos (11U)
-#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos (12U)
-#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos (14U)
-#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos (15U)
-#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP1R register *******************/
-#define USB_EP1R_EA_Pos (0U)
-#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos (4U)
-#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos (6U)
-#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos (7U)
-#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos (8U)
-#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos (9U)
-#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos (11U)
-#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos (12U)
-#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos (14U)
-#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos (15U)
-#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP2R register *******************/
-#define USB_EP2R_EA_Pos (0U)
-#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos (4U)
-#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos (6U)
-#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos (7U)
-#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos (8U)
-#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos (9U)
-#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos (11U)
-#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos (12U)
-#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos (14U)
-#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos (15U)
-#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP3R register *******************/
-#define USB_EP3R_EA_Pos (0U)
-#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos (4U)
-#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos (6U)
-#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos (7U)
-#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos (8U)
-#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos (9U)
-#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos (11U)
-#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos (12U)
-#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos (14U)
-#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos (15U)
-#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP4R register *******************/
-#define USB_EP4R_EA_Pos (0U)
-#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos (4U)
-#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos (6U)
-#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos (7U)
-#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos (8U)
-#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos (9U)
-#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos (11U)
-#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos (12U)
-#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos (14U)
-#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos (15U)
-#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP5R register *******************/
-#define USB_EP5R_EA_Pos (0U)
-#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos (4U)
-#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos (6U)
-#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos (7U)
-#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos (8U)
-#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos (9U)
-#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos (11U)
-#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos (12U)
-#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos (14U)
-#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos (15U)
-#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP6R register *******************/
-#define USB_EP6R_EA_Pos (0U)
-#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos (4U)
-#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos (6U)
-#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos (7U)
-#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos (8U)
-#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos (9U)
-#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos (11U)
-#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos (12U)
-#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos (14U)
-#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos (15U)
-#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP7R register *******************/
-#define USB_EP7R_EA_Pos (0U)
-#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos (4U)
-#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos (6U)
-#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos (7U)
-#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos (8U)
-#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos (9U)
-#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos (11U)
-#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos (12U)
-#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos (14U)
-#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos (15U)
-#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/*!< Common registers */
-/******************* Bit definition for USB_CNTR register *******************/
-#define USB_CNTR_FRES_Pos (0U)
-#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
-#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
-#define USB_CNTR_PDWN_Pos (1U)
-#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
-#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
-#define USB_CNTR_LP_MODE_Pos (2U)
-#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
-#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
-#define USB_CNTR_FSUSP_Pos (3U)
-#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
-#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
-#define USB_CNTR_RESUME_Pos (4U)
-#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
-#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
-#define USB_CNTR_ESOFM_Pos (8U)
-#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
-#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos (9U)
-#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
-#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos (10U)
-#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
-#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos (11U)
-#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
-#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos (12U)
-#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
-#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos (13U)
-#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
-#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos (14U)
-#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos (15U)
-#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
-#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
-
-/******************* Bit definition for USB_ISTR register *******************/
-#define USB_ISTR_EP_ID_Pos (0U)
-#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
-#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
-#define USB_ISTR_DIR_Pos (4U)
-#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
-#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
-#define USB_ISTR_ESOF_Pos (8U)
-#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
-#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos (9U)
-#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
-#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
-#define USB_ISTR_RESET_Pos (10U)
-#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
-#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
-#define USB_ISTR_SUSP_Pos (11U)
-#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
-#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
-#define USB_ISTR_WKUP_Pos (12U)
-#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
-#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
-#define USB_ISTR_ERR_Pos (13U)
-#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
-#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
-#define USB_ISTR_PMAOVR_Pos (14U)
-#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos (15U)
-#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
-#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
-
-/******************* Bit definition for USB_FNR register ********************/
-#define USB_FNR_FN_Pos (0U)
-#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
-#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
-#define USB_FNR_LSOF_Pos (11U)
-#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
-#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
-#define USB_FNR_LCK_Pos (13U)
-#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
-#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
-#define USB_FNR_RXDM_Pos (14U)
-#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
-#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos (15U)
-#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
-#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
-
-/****************** Bit definition for USB_DADDR register *******************/
-#define USB_DADDR_ADD_Pos (0U)
-#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
-#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos (0U)
-#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
-#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
-#define USB_DADDR_ADD1_Pos (1U)
-#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
-#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
-#define USB_DADDR_ADD2_Pos (2U)
-#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
-#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
-#define USB_DADDR_ADD3_Pos (3U)
-#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
-#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
-#define USB_DADDR_ADD4_Pos (4U)
-#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
-#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
-#define USB_DADDR_ADD5_Pos (5U)
-#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
-#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
-#define USB_DADDR_ADD6_Pos (6U)
-#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
-#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
-
-#define USB_DADDR_EF_Pos (7U)
-#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
-#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
-
-/****************** Bit definition for USB_BTABLE register ******************/
-#define USB_BTABLE_BTABLE_Pos (3U)
-#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
-
-/*!< Buffer descriptor table */
-/***************** Bit definition for USB_ADDR0_TX register *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
-#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_TX register *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
-#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_TX register *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
-#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_TX register *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
-#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_TX register *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
-#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_TX register *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
-#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_TX register *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
-#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_TX register *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
-#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_TX register ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
-#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
-
-/***************** Bit definition for USB_COUNT1_TX register ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
-#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
-
-/***************** Bit definition for USB_COUNT2_TX register ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
-#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
-
-/***************** Bit definition for USB_COUNT3_TX register ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
-#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
-
-/***************** Bit definition for USB_COUNT4_TX register ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
-#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
-
-/***************** Bit definition for USB_COUNT5_TX register ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
-#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
-
-/***************** Bit definition for USB_COUNT6_TX register ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
-#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
-
-/***************** Bit definition for USB_COUNT7_TX register ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
-#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
-
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
-
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
-
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
-
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
-
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
-
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
-
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
-
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
-
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
-
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
-
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
-
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
-
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
-
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
-
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_ADDR0_RX register *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
-#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_RX register *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
-#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_RX register *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
-#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_RX register *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
-#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_RX register *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
-#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_RX register *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
-#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_RX register *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
-#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_RX register *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
-#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_RX register ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
-#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos (15U)
-#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT1_RX register ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
-#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos (15U)
-#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT2_RX register ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
-#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos (15U)
-#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT3_RX register ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
-#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos (15U)
-#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT4_RX register ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
-#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos (15U)
-#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT5_RX register ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
-#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos (15U)
-#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT6_RX register ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
-#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos (15U)
-#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT7_RX register ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
-#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos (15U)
-#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/* */
-/* Controller Area Network */
-/* */
-/******************************************************************************/
-
-/*!< CAN control and status registers */
-/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ_Pos (0U)
-#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
-#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
-#define CAN_MCR_SLEEP_Pos (1U)
-#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
-#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
-#define CAN_MCR_TXFP_Pos (2U)
-#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
-#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
-#define CAN_MCR_RFLM_Pos (3U)
-#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
-#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
-#define CAN_MCR_NART_Pos (4U)
-#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
-#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
-#define CAN_MCR_AWUM_Pos (5U)
-#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
-#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
-#define CAN_MCR_ABOM_Pos (6U)
-#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
-#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
-#define CAN_MCR_TTCM_Pos (7U)
-#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
-#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
-#define CAN_MCR_RESET_Pos (15U)
-#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
-#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
-#define CAN_MCR_DBF_Pos (16U)
-#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
-#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
-
-/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK_Pos (0U)
-#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
-#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
-#define CAN_MSR_SLAK_Pos (1U)
-#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
-#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
-#define CAN_MSR_ERRI_Pos (2U)
-#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
-#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
-#define CAN_MSR_WKUI_Pos (3U)
-#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
-#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
-#define CAN_MSR_SLAKI_Pos (4U)
-#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
-#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM_Pos (8U)
-#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
-#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
-#define CAN_MSR_RXM_Pos (9U)
-#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
-#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
-#define CAN_MSR_SAMP_Pos (10U)
-#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
-#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
-#define CAN_MSR_RX_Pos (11U)
-#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
-#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
-
-/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0_Pos (0U)
-#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
-#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0_Pos (1U)
-#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
-#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0_Pos (2U)
-#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
-#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0_Pos (3U)
-#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
-#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0_Pos (7U)
-#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
-#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1_Pos (8U)
-#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
-#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1_Pos (9U)
-#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
-#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1_Pos (10U)
-#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
-#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1_Pos (11U)
-#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
-#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1_Pos (15U)
-#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
-#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2_Pos (16U)
-#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
-#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2_Pos (17U)
-#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
-#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2_Pos (18U)
-#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
-#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2_Pos (19U)
-#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
-#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2_Pos (23U)
-#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
-#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE_Pos (24U)
-#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
-#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
-
-#define CAN_TSR_TME_Pos (26U)
-#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
-#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
-#define CAN_TSR_TME0_Pos (26U)
-#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
-#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1_Pos (27U)
-#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
-#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2_Pos (28U)
-#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
-#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW_Pos (29U)
-#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
-#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
-#define CAN_TSR_LOW0_Pos (29U)
-#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
-#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1_Pos (30U)
-#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
-#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2_Pos (31U)
-#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
-#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
-
-/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0_Pos (0U)
-#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
-#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0_Pos (3U)
-#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
-#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
-#define CAN_RF0R_FOVR0_Pos (4U)
-#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
-#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0_Pos (5U)
-#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
-#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
-
-/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1_Pos (0U)
-#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
-#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1_Pos (3U)
-#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
-#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
-#define CAN_RF1R_FOVR1_Pos (4U)
-#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
-#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1_Pos (5U)
-#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
-#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
-
-/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE_Pos (0U)
-#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
-#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0_Pos (1U)
-#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
-#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0_Pos (2U)
-#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
-#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0_Pos (3U)
-#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
-#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1_Pos (4U)
-#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
-#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1_Pos (5U)
-#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
-#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1_Pos (6U)
-#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
-#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE_Pos (8U)
-#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
-#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE_Pos (9U)
-#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
-#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE_Pos (10U)
-#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
-#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE_Pos (11U)
-#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
-#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE_Pos (15U)
-#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
-#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
-#define CAN_IER_WKUIE_Pos (16U)
-#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
-#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE_Pos (17U)
-#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
-#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
-
-/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF_Pos (0U)
-#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
-#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
-#define CAN_ESR_EPVF_Pos (1U)
-#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
-#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
-#define CAN_ESR_BOFF_Pos (2U)
-#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
-#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
-
-#define CAN_ESR_LEC_Pos (4U)
-#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
-#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
-#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
-#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
-
-#define CAN_ESR_TEC_Pos (16U)
-#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
-#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC_Pos (24U)
-#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
-#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
-
-/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP_Pos (0U)
-#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
-#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1_Pos (16U)
-#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
-#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
-#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
-#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
-#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
-#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
-#define CAN_BTR_TS2_Pos (20U)
-#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
-#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
-#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
-#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
-#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
-#define CAN_BTR_SJW_Pos (24U)
-#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
-#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
-#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
-#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
-#define CAN_BTR_LBKM_Pos (30U)
-#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
-#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM_Pos (31U)
-#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
-#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
-
-/*!< Mailbox registers */
-/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ_Pos (0U)
-#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
-#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
-#define CAN_TI0R_RTR_Pos (1U)
-#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_TI0R_IDE_Pos (2U)
-#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
-#define CAN_TI0R_EXID_Pos (3U)
-#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
-#define CAN_TI0R_STID_Pos (21U)
-#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC_Pos (0U)
-#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
-#define CAN_TDT0R_TGT_Pos (8U)
-#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
-#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
-#define CAN_TDT0R_TIME_Pos (16U)
-#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
-
-/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0_Pos (0U)
-#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_TDL0R_DATA1_Pos (8U)
-#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_TDL0R_DATA2_Pos (16U)
-#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_TDL0R_DATA3_Pos (24U)
-#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
-
-/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4_Pos (0U)
-#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_TDH0R_DATA5_Pos (8U)
-#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_TDH0R_DATA6_Pos (16U)
-#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_TDH0R_DATA7_Pos (24U)
-#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ_Pos (0U)
-#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
-#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
-#define CAN_TI1R_RTR_Pos (1U)
-#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_TI1R_IDE_Pos (2U)
-#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
-#define CAN_TI1R_EXID_Pos (3U)
-#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
-#define CAN_TI1R_STID_Pos (21U)
-#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC_Pos (0U)
-#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
-#define CAN_TDT1R_TGT_Pos (8U)
-#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
-#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
-#define CAN_TDT1R_TIME_Pos (16U)
-#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0_Pos (0U)
-#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_TDL1R_DATA1_Pos (8U)
-#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_TDL1R_DATA2_Pos (16U)
-#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_TDL1R_DATA3_Pos (24U)
-#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4_Pos (0U)
-#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_TDH1R_DATA5_Pos (8U)
-#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_TDH1R_DATA6_Pos (16U)
-#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_TDH1R_DATA7_Pos (24U)
-#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ_Pos (0U)
-#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
-#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
-#define CAN_TI2R_RTR_Pos (1U)
-#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_TI2R_IDE_Pos (2U)
-#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
-#define CAN_TI2R_EXID_Pos (3U)
-#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
-#define CAN_TI2R_STID_Pos (21U)
-#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC_Pos (0U)
-#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
-#define CAN_TDT2R_TGT_Pos (8U)
-#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
-#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
-#define CAN_TDT2R_TIME_Pos (16U)
-#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0_Pos (0U)
-#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_TDL2R_DATA1_Pos (8U)
-#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_TDL2R_DATA2_Pos (16U)
-#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_TDL2R_DATA3_Pos (24U)
-#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4_Pos (0U)
-#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_TDH2R_DATA5_Pos (8U)
-#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_TDH2R_DATA6_Pos (16U)
-#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_TDH2R_DATA7_Pos (24U)
-#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR_Pos (1U)
-#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_RI0R_IDE_Pos (2U)
-#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
-#define CAN_RI0R_EXID_Pos (3U)
-#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
-#define CAN_RI0R_STID_Pos (21U)
-#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC_Pos (0U)
-#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
-#define CAN_RDT0R_FMI_Pos (8U)
-#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
-#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
-#define CAN_RDT0R_TIME_Pos (16U)
-#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0_Pos (0U)
-#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_RDL0R_DATA1_Pos (8U)
-#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_RDL0R_DATA2_Pos (16U)
-#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_RDL0R_DATA3_Pos (24U)
-#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4_Pos (0U)
-#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_RDH0R_DATA5_Pos (8U)
-#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_RDH0R_DATA6_Pos (16U)
-#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_RDH0R_DATA7_Pos (24U)
-#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR_Pos (1U)
-#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_RI1R_IDE_Pos (2U)
-#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
-#define CAN_RI1R_EXID_Pos (3U)
-#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
-#define CAN_RI1R_STID_Pos (21U)
-#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC_Pos (0U)
-#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
-#define CAN_RDT1R_FMI_Pos (8U)
-#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
-#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
-#define CAN_RDT1R_TIME_Pos (16U)
-#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0_Pos (0U)
-#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_RDL1R_DATA1_Pos (8U)
-#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_RDL1R_DATA2_Pos (16U)
-#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_RDL1R_DATA3_Pos (24U)
-#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4_Pos (0U)
-#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_RDH1R_DATA5_Pos (8U)
-#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_RDH1R_DATA6_Pos (16U)
-#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_RDH1R_DATA7_Pos (24U)
-#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
-
-/*!< CAN filter registers */
-/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT_Pos (0U)
-#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
-#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
-#define CAN_FMR_CAN2SB_Pos (8U)
-#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
-#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
-
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM_Pos (0U)
-#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
-#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
-#define CAN_FM1R_FBM0_Pos (0U)
-#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
-#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
-#define CAN_FM1R_FBM1_Pos (1U)
-#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
-#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
-#define CAN_FM1R_FBM2_Pos (2U)
-#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
-#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
-#define CAN_FM1R_FBM3_Pos (3U)
-#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
-#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
-#define CAN_FM1R_FBM4_Pos (4U)
-#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
-#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
-#define CAN_FM1R_FBM5_Pos (5U)
-#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
-#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
-#define CAN_FM1R_FBM6_Pos (6U)
-#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
-#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
-#define CAN_FM1R_FBM7_Pos (7U)
-#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
-#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
-#define CAN_FM1R_FBM8_Pos (8U)
-#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
-#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
-#define CAN_FM1R_FBM9_Pos (9U)
-#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
-#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
-#define CAN_FM1R_FBM10_Pos (10U)
-#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
-#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
-#define CAN_FM1R_FBM11_Pos (11U)
-#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
-#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
-#define CAN_FM1R_FBM12_Pos (12U)
-#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
-#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
-#define CAN_FM1R_FBM13_Pos (13U)
-#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
-#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
-
-/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC_Pos (0U)
-#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
-#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
-#define CAN_FS1R_FSC0_Pos (0U)
-#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
-#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
-#define CAN_FS1R_FSC1_Pos (1U)
-#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
-#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
-#define CAN_FS1R_FSC2_Pos (2U)
-#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
-#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
-#define CAN_FS1R_FSC3_Pos (3U)
-#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
-#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
-#define CAN_FS1R_FSC4_Pos (4U)
-#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
-#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
-#define CAN_FS1R_FSC5_Pos (5U)
-#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
-#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
-#define CAN_FS1R_FSC6_Pos (6U)
-#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
-#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
-#define CAN_FS1R_FSC7_Pos (7U)
-#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
-#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
-#define CAN_FS1R_FSC8_Pos (8U)
-#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
-#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
-#define CAN_FS1R_FSC9_Pos (9U)
-#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
-#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
-#define CAN_FS1R_FSC10_Pos (10U)
-#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
-#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
-#define CAN_FS1R_FSC11_Pos (11U)
-#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
-#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
-#define CAN_FS1R_FSC12_Pos (12U)
-#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
-#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
-#define CAN_FS1R_FSC13_Pos (13U)
-#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
-#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
-
-/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA_Pos (0U)
-#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
-#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0_Pos (0U)
-#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
-#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
-#define CAN_FFA1R_FFA1_Pos (1U)
-#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
-#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
-#define CAN_FFA1R_FFA2_Pos (2U)
-#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
-#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
-#define CAN_FFA1R_FFA3_Pos (3U)
-#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
-#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
-#define CAN_FFA1R_FFA4_Pos (4U)
-#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
-#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
-#define CAN_FFA1R_FFA5_Pos (5U)
-#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
-#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
-#define CAN_FFA1R_FFA6_Pos (6U)
-#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
-#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
-#define CAN_FFA1R_FFA7_Pos (7U)
-#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
-#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
-#define CAN_FFA1R_FFA8_Pos (8U)
-#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
-#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
-#define CAN_FFA1R_FFA9_Pos (9U)
-#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
-#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
-#define CAN_FFA1R_FFA10_Pos (10U)
-#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
-#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
-#define CAN_FFA1R_FFA11_Pos (11U)
-#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
-#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
-#define CAN_FFA1R_FFA12_Pos (12U)
-#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
-#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
-#define CAN_FFA1R_FFA13_Pos (13U)
-#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
-#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
-
-/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT_Pos (0U)
-#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
-#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
-#define CAN_FA1R_FACT0_Pos (0U)
-#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
-#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
-#define CAN_FA1R_FACT1_Pos (1U)
-#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
-#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
-#define CAN_FA1R_FACT2_Pos (2U)
-#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
-#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
-#define CAN_FA1R_FACT3_Pos (3U)
-#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
-#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
-#define CAN_FA1R_FACT4_Pos (4U)
-#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
-#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
-#define CAN_FA1R_FACT5_Pos (5U)
-#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
-#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
-#define CAN_FA1R_FACT6_Pos (6U)
-#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
-#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
-#define CAN_FA1R_FACT7_Pos (7U)
-#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
-#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
-#define CAN_FA1R_FACT8_Pos (8U)
-#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
-#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
-#define CAN_FA1R_FACT9_Pos (9U)
-#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
-#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
-#define CAN_FA1R_FACT10_Pos (10U)
-#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
-#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
-#define CAN_FA1R_FACT11_Pos (11U)
-#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
-#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
-#define CAN_FA1R_FACT12_Pos (12U)
-#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
-#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
-#define CAN_FA1R_FACT13_Pos (13U)
-#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
-#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
-
-/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0_Pos (0U)
-#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F0R1_FB1_Pos (1U)
-#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F0R1_FB2_Pos (2U)
-#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F0R1_FB3_Pos (3U)
-#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F0R1_FB4_Pos (4U)
-#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F0R1_FB5_Pos (5U)
-#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F0R1_FB6_Pos (6U)
-#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F0R1_FB7_Pos (7U)
-#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F0R1_FB8_Pos (8U)
-#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F0R1_FB9_Pos (9U)
-#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F0R1_FB10_Pos (10U)
-#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F0R1_FB11_Pos (11U)
-#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F0R1_FB12_Pos (12U)
-#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F0R1_FB13_Pos (13U)
-#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F0R1_FB14_Pos (14U)
-#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F0R1_FB15_Pos (15U)
-#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F0R1_FB16_Pos (16U)
-#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F0R1_FB17_Pos (17U)
-#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F0R1_FB18_Pos (18U)
-#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F0R1_FB19_Pos (19U)
-#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F0R1_FB20_Pos (20U)
-#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F0R1_FB21_Pos (21U)
-#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F0R1_FB22_Pos (22U)
-#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F0R1_FB23_Pos (23U)
-#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F0R1_FB24_Pos (24U)
-#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F0R1_FB25_Pos (25U)
-#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F0R1_FB26_Pos (26U)
-#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F0R1_FB27_Pos (27U)
-#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F0R1_FB28_Pos (28U)
-#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F0R1_FB29_Pos (29U)
-#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F0R1_FB30_Pos (30U)
-#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F0R1_FB31_Pos (31U)
-#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0_Pos (0U)
-#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F1R1_FB1_Pos (1U)
-#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F1R1_FB2_Pos (2U)
-#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F1R1_FB3_Pos (3U)
-#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F1R1_FB4_Pos (4U)
-#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F1R1_FB5_Pos (5U)
-#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F1R1_FB6_Pos (6U)
-#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F1R1_FB7_Pos (7U)
-#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F1R1_FB8_Pos (8U)
-#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F1R1_FB9_Pos (9U)
-#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F1R1_FB10_Pos (10U)
-#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F1R1_FB11_Pos (11U)
-#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F1R1_FB12_Pos (12U)
-#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F1R1_FB13_Pos (13U)
-#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F1R1_FB14_Pos (14U)
-#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F1R1_FB15_Pos (15U)
-#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F1R1_FB16_Pos (16U)
-#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F1R1_FB17_Pos (17U)
-#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F1R1_FB18_Pos (18U)
-#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F1R1_FB19_Pos (19U)
-#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F1R1_FB20_Pos (20U)
-#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F1R1_FB21_Pos (21U)
-#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F1R1_FB22_Pos (22U)
-#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F1R1_FB23_Pos (23U)
-#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F1R1_FB24_Pos (24U)
-#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F1R1_FB25_Pos (25U)
-#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F1R1_FB26_Pos (26U)
-#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F1R1_FB27_Pos (27U)
-#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F1R1_FB28_Pos (28U)
-#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F1R1_FB29_Pos (29U)
-#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F1R1_FB30_Pos (30U)
-#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F1R1_FB31_Pos (31U)
-#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0_Pos (0U)
-#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F2R1_FB1_Pos (1U)
-#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F2R1_FB2_Pos (2U)
-#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F2R1_FB3_Pos (3U)
-#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F2R1_FB4_Pos (4U)
-#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F2R1_FB5_Pos (5U)
-#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F2R1_FB6_Pos (6U)
-#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F2R1_FB7_Pos (7U)
-#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F2R1_FB8_Pos (8U)
-#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F2R1_FB9_Pos (9U)
-#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F2R1_FB10_Pos (10U)
-#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F2R1_FB11_Pos (11U)
-#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F2R1_FB12_Pos (12U)
-#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F2R1_FB13_Pos (13U)
-#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F2R1_FB14_Pos (14U)
-#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F2R1_FB15_Pos (15U)
-#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F2R1_FB16_Pos (16U)
-#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F2R1_FB17_Pos (17U)
-#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F2R1_FB18_Pos (18U)
-#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F2R1_FB19_Pos (19U)
-#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F2R1_FB20_Pos (20U)
-#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F2R1_FB21_Pos (21U)
-#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F2R1_FB22_Pos (22U)
-#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F2R1_FB23_Pos (23U)
-#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F2R1_FB24_Pos (24U)
-#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F2R1_FB25_Pos (25U)
-#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F2R1_FB26_Pos (26U)
-#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F2R1_FB27_Pos (27U)
-#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F2R1_FB28_Pos (28U)
-#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F2R1_FB29_Pos (29U)
-#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F2R1_FB30_Pos (30U)
-#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F2R1_FB31_Pos (31U)
-#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0_Pos (0U)
-#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F3R1_FB1_Pos (1U)
-#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F3R1_FB2_Pos (2U)
-#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F3R1_FB3_Pos (3U)
-#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F3R1_FB4_Pos (4U)
-#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F3R1_FB5_Pos (5U)
-#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F3R1_FB6_Pos (6U)
-#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F3R1_FB7_Pos (7U)
-#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F3R1_FB8_Pos (8U)
-#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F3R1_FB9_Pos (9U)
-#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F3R1_FB10_Pos (10U)
-#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F3R1_FB11_Pos (11U)
-#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F3R1_FB12_Pos (12U)
-#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F3R1_FB13_Pos (13U)
-#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F3R1_FB14_Pos (14U)
-#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F3R1_FB15_Pos (15U)
-#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F3R1_FB16_Pos (16U)
-#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F3R1_FB17_Pos (17U)
-#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F3R1_FB18_Pos (18U)
-#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F3R1_FB19_Pos (19U)
-#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F3R1_FB20_Pos (20U)
-#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F3R1_FB21_Pos (21U)
-#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F3R1_FB22_Pos (22U)
-#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F3R1_FB23_Pos (23U)
-#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F3R1_FB24_Pos (24U)
-#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F3R1_FB25_Pos (25U)
-#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F3R1_FB26_Pos (26U)
-#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F3R1_FB27_Pos (27U)
-#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F3R1_FB28_Pos (28U)
-#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F3R1_FB29_Pos (29U)
-#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F3R1_FB30_Pos (30U)
-#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F3R1_FB31_Pos (31U)
-#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0_Pos (0U)
-#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F4R1_FB1_Pos (1U)
-#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F4R1_FB2_Pos (2U)
-#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F4R1_FB3_Pos (3U)
-#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F4R1_FB4_Pos (4U)
-#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F4R1_FB5_Pos (5U)
-#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F4R1_FB6_Pos (6U)
-#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F4R1_FB7_Pos (7U)
-#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F4R1_FB8_Pos (8U)
-#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F4R1_FB9_Pos (9U)
-#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F4R1_FB10_Pos (10U)
-#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F4R1_FB11_Pos (11U)
-#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F4R1_FB12_Pos (12U)
-#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F4R1_FB13_Pos (13U)
-#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F4R1_FB14_Pos (14U)
-#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F4R1_FB15_Pos (15U)
-#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F4R1_FB16_Pos (16U)
-#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F4R1_FB17_Pos (17U)
-#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F4R1_FB18_Pos (18U)
-#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F4R1_FB19_Pos (19U)
-#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F4R1_FB20_Pos (20U)
-#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F4R1_FB21_Pos (21U)
-#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F4R1_FB22_Pos (22U)
-#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F4R1_FB23_Pos (23U)
-#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F4R1_FB24_Pos (24U)
-#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F4R1_FB25_Pos (25U)
-#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F4R1_FB26_Pos (26U)
-#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F4R1_FB27_Pos (27U)
-#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F4R1_FB28_Pos (28U)
-#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F4R1_FB29_Pos (29U)
-#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F4R1_FB30_Pos (30U)
-#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F4R1_FB31_Pos (31U)
-#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0_Pos (0U)
-#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F5R1_FB1_Pos (1U)
-#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F5R1_FB2_Pos (2U)
-#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F5R1_FB3_Pos (3U)
-#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F5R1_FB4_Pos (4U)
-#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F5R1_FB5_Pos (5U)
-#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F5R1_FB6_Pos (6U)
-#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F5R1_FB7_Pos (7U)
-#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F5R1_FB8_Pos (8U)
-#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F5R1_FB9_Pos (9U)
-#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F5R1_FB10_Pos (10U)
-#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F5R1_FB11_Pos (11U)
-#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F5R1_FB12_Pos (12U)
-#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F5R1_FB13_Pos (13U)
-#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F5R1_FB14_Pos (14U)
-#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F5R1_FB15_Pos (15U)
-#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F5R1_FB16_Pos (16U)
-#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F5R1_FB17_Pos (17U)
-#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F5R1_FB18_Pos (18U)
-#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F5R1_FB19_Pos (19U)
-#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F5R1_FB20_Pos (20U)
-#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F5R1_FB21_Pos (21U)
-#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F5R1_FB22_Pos (22U)
-#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F5R1_FB23_Pos (23U)
-#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F5R1_FB24_Pos (24U)
-#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F5R1_FB25_Pos (25U)
-#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F5R1_FB26_Pos (26U)
-#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F5R1_FB27_Pos (27U)
-#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F5R1_FB28_Pos (28U)
-#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F5R1_FB29_Pos (29U)
-#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F5R1_FB30_Pos (30U)
-#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F5R1_FB31_Pos (31U)
-#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0_Pos (0U)
-#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F6R1_FB1_Pos (1U)
-#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F6R1_FB2_Pos (2U)
-#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F6R1_FB3_Pos (3U)
-#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F6R1_FB4_Pos (4U)
-#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F6R1_FB5_Pos (5U)
-#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F6R1_FB6_Pos (6U)
-#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F6R1_FB7_Pos (7U)
-#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F6R1_FB8_Pos (8U)
-#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F6R1_FB9_Pos (9U)
-#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F6R1_FB10_Pos (10U)
-#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F6R1_FB11_Pos (11U)
-#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F6R1_FB12_Pos (12U)
-#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F6R1_FB13_Pos (13U)
-#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F6R1_FB14_Pos (14U)
-#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F6R1_FB15_Pos (15U)
-#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F6R1_FB16_Pos (16U)
-#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F6R1_FB17_Pos (17U)
-#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F6R1_FB18_Pos (18U)
-#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F6R1_FB19_Pos (19U)
-#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F6R1_FB20_Pos (20U)
-#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F6R1_FB21_Pos (21U)
-#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F6R1_FB22_Pos (22U)
-#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F6R1_FB23_Pos (23U)
-#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F6R1_FB24_Pos (24U)
-#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F6R1_FB25_Pos (25U)
-#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F6R1_FB26_Pos (26U)
-#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F6R1_FB27_Pos (27U)
-#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F6R1_FB28_Pos (28U)
-#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F6R1_FB29_Pos (29U)
-#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F6R1_FB30_Pos (30U)
-#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F6R1_FB31_Pos (31U)
-#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0_Pos (0U)
-#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F7R1_FB1_Pos (1U)
-#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F7R1_FB2_Pos (2U)
-#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F7R1_FB3_Pos (3U)
-#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F7R1_FB4_Pos (4U)
-#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F7R1_FB5_Pos (5U)
-#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F7R1_FB6_Pos (6U)
-#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F7R1_FB7_Pos (7U)
-#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F7R1_FB8_Pos (8U)
-#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F7R1_FB9_Pos (9U)
-#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F7R1_FB10_Pos (10U)
-#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F7R1_FB11_Pos (11U)
-#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F7R1_FB12_Pos (12U)
-#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F7R1_FB13_Pos (13U)
-#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F7R1_FB14_Pos (14U)
-#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F7R1_FB15_Pos (15U)
-#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F7R1_FB16_Pos (16U)
-#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F7R1_FB17_Pos (17U)
-#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F7R1_FB18_Pos (18U)
-#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F7R1_FB19_Pos (19U)
-#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F7R1_FB20_Pos (20U)
-#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F7R1_FB21_Pos (21U)
-#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F7R1_FB22_Pos (22U)
-#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F7R1_FB23_Pos (23U)
-#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F7R1_FB24_Pos (24U)
-#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F7R1_FB25_Pos (25U)
-#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F7R1_FB26_Pos (26U)
-#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F7R1_FB27_Pos (27U)
-#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F7R1_FB28_Pos (28U)
-#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F7R1_FB29_Pos (29U)
-#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F7R1_FB30_Pos (30U)
-#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F7R1_FB31_Pos (31U)
-#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0_Pos (0U)
-#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F8R1_FB1_Pos (1U)
-#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F8R1_FB2_Pos (2U)
-#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F8R1_FB3_Pos (3U)
-#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F8R1_FB4_Pos (4U)
-#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F8R1_FB5_Pos (5U)
-#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F8R1_FB6_Pos (6U)
-#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F8R1_FB7_Pos (7U)
-#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F8R1_FB8_Pos (8U)
-#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F8R1_FB9_Pos (9U)
-#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F8R1_FB10_Pos (10U)
-#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F8R1_FB11_Pos (11U)
-#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F8R1_FB12_Pos (12U)
-#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F8R1_FB13_Pos (13U)
-#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F8R1_FB14_Pos (14U)
-#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F8R1_FB15_Pos (15U)
-#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F8R1_FB16_Pos (16U)
-#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F8R1_FB17_Pos (17U)
-#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F8R1_FB18_Pos (18U)
-#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F8R1_FB19_Pos (19U)
-#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F8R1_FB20_Pos (20U)
-#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F8R1_FB21_Pos (21U)
-#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F8R1_FB22_Pos (22U)
-#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F8R1_FB23_Pos (23U)
-#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F8R1_FB24_Pos (24U)
-#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F8R1_FB25_Pos (25U)
-#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F8R1_FB26_Pos (26U)
-#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F8R1_FB27_Pos (27U)
-#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F8R1_FB28_Pos (28U)
-#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F8R1_FB29_Pos (29U)
-#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F8R1_FB30_Pos (30U)
-#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F8R1_FB31_Pos (31U)
-#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0_Pos (0U)
-#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F9R1_FB1_Pos (1U)
-#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F9R1_FB2_Pos (2U)
-#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F9R1_FB3_Pos (3U)
-#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F9R1_FB4_Pos (4U)
-#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F9R1_FB5_Pos (5U)
-#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F9R1_FB6_Pos (6U)
-#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F9R1_FB7_Pos (7U)
-#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F9R1_FB8_Pos (8U)
-#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F9R1_FB9_Pos (9U)
-#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F9R1_FB10_Pos (10U)
-#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F9R1_FB11_Pos (11U)
-#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F9R1_FB12_Pos (12U)
-#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F9R1_FB13_Pos (13U)
-#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F9R1_FB14_Pos (14U)
-#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F9R1_FB15_Pos (15U)
-#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F9R1_FB16_Pos (16U)
-#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F9R1_FB17_Pos (17U)
-#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F9R1_FB18_Pos (18U)
-#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F9R1_FB19_Pos (19U)
-#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F9R1_FB20_Pos (20U)
-#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F9R1_FB21_Pos (21U)
-#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F9R1_FB22_Pos (22U)
-#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F9R1_FB23_Pos (23U)
-#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F9R1_FB24_Pos (24U)
-#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F9R1_FB25_Pos (25U)
-#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F9R1_FB26_Pos (26U)
-#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F9R1_FB27_Pos (27U)
-#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F9R1_FB28_Pos (28U)
-#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F9R1_FB29_Pos (29U)
-#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F9R1_FB30_Pos (30U)
-#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F9R1_FB31_Pos (31U)
-#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0_Pos (0U)
-#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F10R1_FB1_Pos (1U)
-#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F10R1_FB2_Pos (2U)
-#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F10R1_FB3_Pos (3U)
-#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F10R1_FB4_Pos (4U)
-#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F10R1_FB5_Pos (5U)
-#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F10R1_FB6_Pos (6U)
-#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F10R1_FB7_Pos (7U)
-#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F10R1_FB8_Pos (8U)
-#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F10R1_FB9_Pos (9U)
-#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F10R1_FB10_Pos (10U)
-#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F10R1_FB11_Pos (11U)
-#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F10R1_FB12_Pos (12U)
-#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F10R1_FB13_Pos (13U)
-#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F10R1_FB14_Pos (14U)
-#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F10R1_FB15_Pos (15U)
-#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F10R1_FB16_Pos (16U)
-#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F10R1_FB17_Pos (17U)
-#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F10R1_FB18_Pos (18U)
-#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F10R1_FB19_Pos (19U)
-#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F10R1_FB20_Pos (20U)
-#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F10R1_FB21_Pos (21U)
-#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F10R1_FB22_Pos (22U)
-#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F10R1_FB23_Pos (23U)
-#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F10R1_FB24_Pos (24U)
-#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F10R1_FB25_Pos (25U)
-#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F10R1_FB26_Pos (26U)
-#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F10R1_FB27_Pos (27U)
-#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F10R1_FB28_Pos (28U)
-#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F10R1_FB29_Pos (29U)
-#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F10R1_FB30_Pos (30U)
-#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F10R1_FB31_Pos (31U)
-#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0_Pos (0U)
-#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F11R1_FB1_Pos (1U)
-#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F11R1_FB2_Pos (2U)
-#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F11R1_FB3_Pos (3U)
-#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F11R1_FB4_Pos (4U)
-#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F11R1_FB5_Pos (5U)
-#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F11R1_FB6_Pos (6U)
-#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F11R1_FB7_Pos (7U)
-#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F11R1_FB8_Pos (8U)
-#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F11R1_FB9_Pos (9U)
-#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F11R1_FB10_Pos (10U)
-#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F11R1_FB11_Pos (11U)
-#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F11R1_FB12_Pos (12U)
-#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F11R1_FB13_Pos (13U)
-#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F11R1_FB14_Pos (14U)
-#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F11R1_FB15_Pos (15U)
-#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F11R1_FB16_Pos (16U)
-#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F11R1_FB17_Pos (17U)
-#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F11R1_FB18_Pos (18U)
-#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F11R1_FB19_Pos (19U)
-#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F11R1_FB20_Pos (20U)
-#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F11R1_FB21_Pos (21U)
-#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F11R1_FB22_Pos (22U)
-#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F11R1_FB23_Pos (23U)
-#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F11R1_FB24_Pos (24U)
-#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F11R1_FB25_Pos (25U)
-#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F11R1_FB26_Pos (26U)
-#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F11R1_FB27_Pos (27U)
-#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F11R1_FB28_Pos (28U)
-#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F11R1_FB29_Pos (29U)
-#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F11R1_FB30_Pos (30U)
-#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F11R1_FB31_Pos (31U)
-#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0_Pos (0U)
-#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F12R1_FB1_Pos (1U)
-#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F12R1_FB2_Pos (2U)
-#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F12R1_FB3_Pos (3U)
-#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F12R1_FB4_Pos (4U)
-#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F12R1_FB5_Pos (5U)
-#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F12R1_FB6_Pos (6U)
-#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F12R1_FB7_Pos (7U)
-#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F12R1_FB8_Pos (8U)
-#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F12R1_FB9_Pos (9U)
-#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F12R1_FB10_Pos (10U)
-#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F12R1_FB11_Pos (11U)
-#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F12R1_FB12_Pos (12U)
-#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F12R1_FB13_Pos (13U)
-#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F12R1_FB14_Pos (14U)
-#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F12R1_FB15_Pos (15U)
-#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F12R1_FB16_Pos (16U)
-#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F12R1_FB17_Pos (17U)
-#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F12R1_FB18_Pos (18U)
-#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F12R1_FB19_Pos (19U)
-#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F12R1_FB20_Pos (20U)
-#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F12R1_FB21_Pos (21U)
-#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F12R1_FB22_Pos (22U)
-#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F12R1_FB23_Pos (23U)
-#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F12R1_FB24_Pos (24U)
-#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F12R1_FB25_Pos (25U)
-#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F12R1_FB26_Pos (26U)
-#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F12R1_FB27_Pos (27U)
-#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F12R1_FB28_Pos (28U)
-#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F12R1_FB29_Pos (29U)
-#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F12R1_FB30_Pos (30U)
-#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F12R1_FB31_Pos (31U)
-#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0_Pos (0U)
-#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F13R1_FB1_Pos (1U)
-#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F13R1_FB2_Pos (2U)
-#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F13R1_FB3_Pos (3U)
-#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F13R1_FB4_Pos (4U)
-#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F13R1_FB5_Pos (5U)
-#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F13R1_FB6_Pos (6U)
-#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F13R1_FB7_Pos (7U)
-#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F13R1_FB8_Pos (8U)
-#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F13R1_FB9_Pos (9U)
-#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F13R1_FB10_Pos (10U)
-#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F13R1_FB11_Pos (11U)
-#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F13R1_FB12_Pos (12U)
-#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F13R1_FB13_Pos (13U)
-#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F13R1_FB14_Pos (14U)
-#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F13R1_FB15_Pos (15U)
-#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F13R1_FB16_Pos (16U)
-#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F13R1_FB17_Pos (17U)
-#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F13R1_FB18_Pos (18U)
-#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F13R1_FB19_Pos (19U)
-#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F13R1_FB20_Pos (20U)
-#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F13R1_FB21_Pos (21U)
-#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F13R1_FB22_Pos (22U)
-#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F13R1_FB23_Pos (23U)
-#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F13R1_FB24_Pos (24U)
-#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F13R1_FB25_Pos (25U)
-#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F13R1_FB26_Pos (26U)
-#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F13R1_FB27_Pos (27U)
-#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F13R1_FB28_Pos (28U)
-#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F13R1_FB29_Pos (29U)
-#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F13R1_FB30_Pos (30U)
-#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F13R1_FB31_Pos (31U)
-#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0_Pos (0U)
-#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F0R2_FB1_Pos (1U)
-#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F0R2_FB2_Pos (2U)
-#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F0R2_FB3_Pos (3U)
-#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F0R2_FB4_Pos (4U)
-#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F0R2_FB5_Pos (5U)
-#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F0R2_FB6_Pos (6U)
-#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F0R2_FB7_Pos (7U)
-#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F0R2_FB8_Pos (8U)
-#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F0R2_FB9_Pos (9U)
-#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F0R2_FB10_Pos (10U)
-#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F0R2_FB11_Pos (11U)
-#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F0R2_FB12_Pos (12U)
-#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F0R2_FB13_Pos (13U)
-#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F0R2_FB14_Pos (14U)
-#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F0R2_FB15_Pos (15U)
-#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F0R2_FB16_Pos (16U)
-#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F0R2_FB17_Pos (17U)
-#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F0R2_FB18_Pos (18U)
-#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F0R2_FB19_Pos (19U)
-#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F0R2_FB20_Pos (20U)
-#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F0R2_FB21_Pos (21U)
-#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F0R2_FB22_Pos (22U)
-#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F0R2_FB23_Pos (23U)
-#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F0R2_FB24_Pos (24U)
-#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F0R2_FB25_Pos (25U)
-#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F0R2_FB26_Pos (26U)
-#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F0R2_FB27_Pos (27U)
-#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F0R2_FB28_Pos (28U)
-#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F0R2_FB29_Pos (29U)
-#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F0R2_FB30_Pos (30U)
-#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F0R2_FB31_Pos (31U)
-#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0_Pos (0U)
-#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F1R2_FB1_Pos (1U)
-#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F1R2_FB2_Pos (2U)
-#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F1R2_FB3_Pos (3U)
-#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F1R2_FB4_Pos (4U)
-#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F1R2_FB5_Pos (5U)
-#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F1R2_FB6_Pos (6U)
-#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F1R2_FB7_Pos (7U)
-#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F1R2_FB8_Pos (8U)
-#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F1R2_FB9_Pos (9U)
-#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F1R2_FB10_Pos (10U)
-#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F1R2_FB11_Pos (11U)
-#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F1R2_FB12_Pos (12U)
-#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F1R2_FB13_Pos (13U)
-#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F1R2_FB14_Pos (14U)
-#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F1R2_FB15_Pos (15U)
-#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F1R2_FB16_Pos (16U)
-#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F1R2_FB17_Pos (17U)
-#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F1R2_FB18_Pos (18U)
-#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F1R2_FB19_Pos (19U)
-#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F1R2_FB20_Pos (20U)
-#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F1R2_FB21_Pos (21U)
-#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F1R2_FB22_Pos (22U)
-#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F1R2_FB23_Pos (23U)
-#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F1R2_FB24_Pos (24U)
-#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F1R2_FB25_Pos (25U)
-#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F1R2_FB26_Pos (26U)
-#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F1R2_FB27_Pos (27U)
-#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F1R2_FB28_Pos (28U)
-#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F1R2_FB29_Pos (29U)
-#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F1R2_FB30_Pos (30U)
-#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F1R2_FB31_Pos (31U)
-#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0_Pos (0U)
-#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F2R2_FB1_Pos (1U)
-#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F2R2_FB2_Pos (2U)
-#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F2R2_FB3_Pos (3U)
-#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F2R2_FB4_Pos (4U)
-#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F2R2_FB5_Pos (5U)
-#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F2R2_FB6_Pos (6U)
-#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F2R2_FB7_Pos (7U)
-#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F2R2_FB8_Pos (8U)
-#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F2R2_FB9_Pos (9U)
-#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F2R2_FB10_Pos (10U)
-#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F2R2_FB11_Pos (11U)
-#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F2R2_FB12_Pos (12U)
-#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F2R2_FB13_Pos (13U)
-#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F2R2_FB14_Pos (14U)
-#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F2R2_FB15_Pos (15U)
-#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F2R2_FB16_Pos (16U)
-#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F2R2_FB17_Pos (17U)
-#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F2R2_FB18_Pos (18U)
-#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F2R2_FB19_Pos (19U)
-#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F2R2_FB20_Pos (20U)
-#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F2R2_FB21_Pos (21U)
-#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F2R2_FB22_Pos (22U)
-#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F2R2_FB23_Pos (23U)
-#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F2R2_FB24_Pos (24U)
-#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F2R2_FB25_Pos (25U)
-#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F2R2_FB26_Pos (26U)
-#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F2R2_FB27_Pos (27U)
-#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F2R2_FB28_Pos (28U)
-#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F2R2_FB29_Pos (29U)
-#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F2R2_FB30_Pos (30U)
-#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F2R2_FB31_Pos (31U)
-#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0_Pos (0U)
-#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F3R2_FB1_Pos (1U)
-#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F3R2_FB2_Pos (2U)
-#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F3R2_FB3_Pos (3U)
-#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F3R2_FB4_Pos (4U)
-#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F3R2_FB5_Pos (5U)
-#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F3R2_FB6_Pos (6U)
-#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F3R2_FB7_Pos (7U)
-#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F3R2_FB8_Pos (8U)
-#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F3R2_FB9_Pos (9U)
-#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F3R2_FB10_Pos (10U)
-#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F3R2_FB11_Pos (11U)
-#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F3R2_FB12_Pos (12U)
-#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F3R2_FB13_Pos (13U)
-#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F3R2_FB14_Pos (14U)
-#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F3R2_FB15_Pos (15U)
-#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F3R2_FB16_Pos (16U)
-#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F3R2_FB17_Pos (17U)
-#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F3R2_FB18_Pos (18U)
-#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F3R2_FB19_Pos (19U)
-#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F3R2_FB20_Pos (20U)
-#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F3R2_FB21_Pos (21U)
-#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F3R2_FB22_Pos (22U)
-#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F3R2_FB23_Pos (23U)
-#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F3R2_FB24_Pos (24U)
-#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F3R2_FB25_Pos (25U)
-#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F3R2_FB26_Pos (26U)
-#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F3R2_FB27_Pos (27U)
-#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F3R2_FB28_Pos (28U)
-#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F3R2_FB29_Pos (29U)
-#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F3R2_FB30_Pos (30U)
-#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F3R2_FB31_Pos (31U)
-#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0_Pos (0U)
-#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F4R2_FB1_Pos (1U)
-#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F4R2_FB2_Pos (2U)
-#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F4R2_FB3_Pos (3U)
-#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F4R2_FB4_Pos (4U)
-#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F4R2_FB5_Pos (5U)
-#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F4R2_FB6_Pos (6U)
-#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F4R2_FB7_Pos (7U)
-#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F4R2_FB8_Pos (8U)
-#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F4R2_FB9_Pos (9U)
-#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F4R2_FB10_Pos (10U)
-#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F4R2_FB11_Pos (11U)
-#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F4R2_FB12_Pos (12U)
-#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F4R2_FB13_Pos (13U)
-#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F4R2_FB14_Pos (14U)
-#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F4R2_FB15_Pos (15U)
-#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F4R2_FB16_Pos (16U)
-#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F4R2_FB17_Pos (17U)
-#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F4R2_FB18_Pos (18U)
-#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F4R2_FB19_Pos (19U)
-#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F4R2_FB20_Pos (20U)
-#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F4R2_FB21_Pos (21U)
-#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F4R2_FB22_Pos (22U)
-#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F4R2_FB23_Pos (23U)
-#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F4R2_FB24_Pos (24U)
-#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F4R2_FB25_Pos (25U)
-#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F4R2_FB26_Pos (26U)
-#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F4R2_FB27_Pos (27U)
-#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F4R2_FB28_Pos (28U)
-#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F4R2_FB29_Pos (29U)
-#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F4R2_FB30_Pos (30U)
-#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F4R2_FB31_Pos (31U)
-#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0_Pos (0U)
-#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F5R2_FB1_Pos (1U)
-#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F5R2_FB2_Pos (2U)
-#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F5R2_FB3_Pos (3U)
-#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F5R2_FB4_Pos (4U)
-#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F5R2_FB5_Pos (5U)
-#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F5R2_FB6_Pos (6U)
-#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F5R2_FB7_Pos (7U)
-#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F5R2_FB8_Pos (8U)
-#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F5R2_FB9_Pos (9U)
-#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F5R2_FB10_Pos (10U)
-#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F5R2_FB11_Pos (11U)
-#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F5R2_FB12_Pos (12U)
-#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F5R2_FB13_Pos (13U)
-#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F5R2_FB14_Pos (14U)
-#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F5R2_FB15_Pos (15U)
-#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F5R2_FB16_Pos (16U)
-#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F5R2_FB17_Pos (17U)
-#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F5R2_FB18_Pos (18U)
-#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F5R2_FB19_Pos (19U)
-#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F5R2_FB20_Pos (20U)
-#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F5R2_FB21_Pos (21U)
-#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F5R2_FB22_Pos (22U)
-#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F5R2_FB23_Pos (23U)
-#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F5R2_FB24_Pos (24U)
-#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F5R2_FB25_Pos (25U)
-#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F5R2_FB26_Pos (26U)
-#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F5R2_FB27_Pos (27U)
-#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F5R2_FB28_Pos (28U)
-#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F5R2_FB29_Pos (29U)
-#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F5R2_FB30_Pos (30U)
-#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F5R2_FB31_Pos (31U)
-#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0_Pos (0U)
-#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F6R2_FB1_Pos (1U)
-#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F6R2_FB2_Pos (2U)
-#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F6R2_FB3_Pos (3U)
-#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F6R2_FB4_Pos (4U)
-#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F6R2_FB5_Pos (5U)
-#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F6R2_FB6_Pos (6U)
-#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F6R2_FB7_Pos (7U)
-#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F6R2_FB8_Pos (8U)
-#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F6R2_FB9_Pos (9U)
-#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F6R2_FB10_Pos (10U)
-#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F6R2_FB11_Pos (11U)
-#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F6R2_FB12_Pos (12U)
-#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F6R2_FB13_Pos (13U)
-#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F6R2_FB14_Pos (14U)
-#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F6R2_FB15_Pos (15U)
-#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F6R2_FB16_Pos (16U)
-#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F6R2_FB17_Pos (17U)
-#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F6R2_FB18_Pos (18U)
-#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F6R2_FB19_Pos (19U)
-#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F6R2_FB20_Pos (20U)
-#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F6R2_FB21_Pos (21U)
-#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F6R2_FB22_Pos (22U)
-#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F6R2_FB23_Pos (23U)
-#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F6R2_FB24_Pos (24U)
-#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F6R2_FB25_Pos (25U)
-#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F6R2_FB26_Pos (26U)
-#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F6R2_FB27_Pos (27U)
-#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F6R2_FB28_Pos (28U)
-#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F6R2_FB29_Pos (29U)
-#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F6R2_FB30_Pos (30U)
-#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F6R2_FB31_Pos (31U)
-#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0_Pos (0U)
-#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F7R2_FB1_Pos (1U)
-#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F7R2_FB2_Pos (2U)
-#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F7R2_FB3_Pos (3U)
-#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F7R2_FB4_Pos (4U)
-#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F7R2_FB5_Pos (5U)
-#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F7R2_FB6_Pos (6U)
-#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F7R2_FB7_Pos (7U)
-#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F7R2_FB8_Pos (8U)
-#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F7R2_FB9_Pos (9U)
-#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F7R2_FB10_Pos (10U)
-#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F7R2_FB11_Pos (11U)
-#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F7R2_FB12_Pos (12U)
-#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F7R2_FB13_Pos (13U)
-#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F7R2_FB14_Pos (14U)
-#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F7R2_FB15_Pos (15U)
-#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F7R2_FB16_Pos (16U)
-#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F7R2_FB17_Pos (17U)
-#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F7R2_FB18_Pos (18U)
-#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F7R2_FB19_Pos (19U)
-#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F7R2_FB20_Pos (20U)
-#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F7R2_FB21_Pos (21U)
-#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F7R2_FB22_Pos (22U)
-#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F7R2_FB23_Pos (23U)
-#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F7R2_FB24_Pos (24U)
-#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F7R2_FB25_Pos (25U)
-#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F7R2_FB26_Pos (26U)
-#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F7R2_FB27_Pos (27U)
-#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F7R2_FB28_Pos (28U)
-#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F7R2_FB29_Pos (29U)
-#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F7R2_FB30_Pos (30U)
-#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F7R2_FB31_Pos (31U)
-#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0_Pos (0U)
-#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F8R2_FB1_Pos (1U)
-#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F8R2_FB2_Pos (2U)
-#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F8R2_FB3_Pos (3U)
-#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F8R2_FB4_Pos (4U)
-#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F8R2_FB5_Pos (5U)
-#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F8R2_FB6_Pos (6U)
-#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F8R2_FB7_Pos (7U)
-#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F8R2_FB8_Pos (8U)
-#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F8R2_FB9_Pos (9U)
-#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F8R2_FB10_Pos (10U)
-#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F8R2_FB11_Pos (11U)
-#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F8R2_FB12_Pos (12U)
-#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F8R2_FB13_Pos (13U)
-#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F8R2_FB14_Pos (14U)
-#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F8R2_FB15_Pos (15U)
-#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F8R2_FB16_Pos (16U)
-#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F8R2_FB17_Pos (17U)
-#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F8R2_FB18_Pos (18U)
-#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F8R2_FB19_Pos (19U)
-#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F8R2_FB20_Pos (20U)
-#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F8R2_FB21_Pos (21U)
-#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F8R2_FB22_Pos (22U)
-#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F8R2_FB23_Pos (23U)
-#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F8R2_FB24_Pos (24U)
-#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F8R2_FB25_Pos (25U)
-#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F8R2_FB26_Pos (26U)
-#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F8R2_FB27_Pos (27U)
-#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F8R2_FB28_Pos (28U)
-#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F8R2_FB29_Pos (29U)
-#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F8R2_FB30_Pos (30U)
-#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F8R2_FB31_Pos (31U)
-#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0_Pos (0U)
-#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F9R2_FB1_Pos (1U)
-#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F9R2_FB2_Pos (2U)
-#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F9R2_FB3_Pos (3U)
-#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F9R2_FB4_Pos (4U)
-#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F9R2_FB5_Pos (5U)
-#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F9R2_FB6_Pos (6U)
-#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F9R2_FB7_Pos (7U)
-#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F9R2_FB8_Pos (8U)
-#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F9R2_FB9_Pos (9U)
-#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F9R2_FB10_Pos (10U)
-#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F9R2_FB11_Pos (11U)
-#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F9R2_FB12_Pos (12U)
-#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F9R2_FB13_Pos (13U)
-#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F9R2_FB14_Pos (14U)
-#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F9R2_FB15_Pos (15U)
-#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F9R2_FB16_Pos (16U)
-#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F9R2_FB17_Pos (17U)
-#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F9R2_FB18_Pos (18U)
-#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F9R2_FB19_Pos (19U)
-#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F9R2_FB20_Pos (20U)
-#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F9R2_FB21_Pos (21U)
-#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F9R2_FB22_Pos (22U)
-#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F9R2_FB23_Pos (23U)
-#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F9R2_FB24_Pos (24U)
-#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F9R2_FB25_Pos (25U)
-#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F9R2_FB26_Pos (26U)
-#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F9R2_FB27_Pos (27U)
-#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F9R2_FB28_Pos (28U)
-#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F9R2_FB29_Pos (29U)
-#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F9R2_FB30_Pos (30U)
-#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F9R2_FB31_Pos (31U)
-#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0_Pos (0U)
-#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F10R2_FB1_Pos (1U)
-#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F10R2_FB2_Pos (2U)
-#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F10R2_FB3_Pos (3U)
-#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F10R2_FB4_Pos (4U)
-#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F10R2_FB5_Pos (5U)
-#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F10R2_FB6_Pos (6U)
-#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F10R2_FB7_Pos (7U)
-#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F10R2_FB8_Pos (8U)
-#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F10R2_FB9_Pos (9U)
-#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F10R2_FB10_Pos (10U)
-#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F10R2_FB11_Pos (11U)
-#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F10R2_FB12_Pos (12U)
-#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F10R2_FB13_Pos (13U)
-#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F10R2_FB14_Pos (14U)
-#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F10R2_FB15_Pos (15U)
-#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F10R2_FB16_Pos (16U)
-#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F10R2_FB17_Pos (17U)
-#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F10R2_FB18_Pos (18U)
-#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F10R2_FB19_Pos (19U)
-#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F10R2_FB20_Pos (20U)
-#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F10R2_FB21_Pos (21U)
-#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F10R2_FB22_Pos (22U)
-#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F10R2_FB23_Pos (23U)
-#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F10R2_FB24_Pos (24U)
-#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F10R2_FB25_Pos (25U)
-#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F10R2_FB26_Pos (26U)
-#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F10R2_FB27_Pos (27U)
-#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F10R2_FB28_Pos (28U)
-#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F10R2_FB29_Pos (29U)
-#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F10R2_FB30_Pos (30U)
-#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F10R2_FB31_Pos (31U)
-#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0_Pos (0U)
-#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F11R2_FB1_Pos (1U)
-#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F11R2_FB2_Pos (2U)
-#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F11R2_FB3_Pos (3U)
-#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F11R2_FB4_Pos (4U)
-#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F11R2_FB5_Pos (5U)
-#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F11R2_FB6_Pos (6U)
-#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F11R2_FB7_Pos (7U)
-#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F11R2_FB8_Pos (8U)
-#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F11R2_FB9_Pos (9U)
-#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F11R2_FB10_Pos (10U)
-#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F11R2_FB11_Pos (11U)
-#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F11R2_FB12_Pos (12U)
-#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F11R2_FB13_Pos (13U)
-#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F11R2_FB14_Pos (14U)
-#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F11R2_FB15_Pos (15U)
-#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F11R2_FB16_Pos (16U)
-#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F11R2_FB17_Pos (17U)
-#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F11R2_FB18_Pos (18U)
-#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F11R2_FB19_Pos (19U)
-#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F11R2_FB20_Pos (20U)
-#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F11R2_FB21_Pos (21U)
-#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F11R2_FB22_Pos (22U)
-#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F11R2_FB23_Pos (23U)
-#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F11R2_FB24_Pos (24U)
-#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F11R2_FB25_Pos (25U)
-#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F11R2_FB26_Pos (26U)
-#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F11R2_FB27_Pos (27U)
-#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F11R2_FB28_Pos (28U)
-#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F11R2_FB29_Pos (29U)
-#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F11R2_FB30_Pos (30U)
-#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F11R2_FB31_Pos (31U)
-#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0_Pos (0U)
-#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F12R2_FB1_Pos (1U)
-#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F12R2_FB2_Pos (2U)
-#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F12R2_FB3_Pos (3U)
-#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F12R2_FB4_Pos (4U)
-#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F12R2_FB5_Pos (5U)
-#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F12R2_FB6_Pos (6U)
-#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F12R2_FB7_Pos (7U)
-#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F12R2_FB8_Pos (8U)
-#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F12R2_FB9_Pos (9U)
-#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F12R2_FB10_Pos (10U)
-#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F12R2_FB11_Pos (11U)
-#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F12R2_FB12_Pos (12U)
-#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F12R2_FB13_Pos (13U)
-#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F12R2_FB14_Pos (14U)
-#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F12R2_FB15_Pos (15U)
-#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F12R2_FB16_Pos (16U)
-#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F12R2_FB17_Pos (17U)
-#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F12R2_FB18_Pos (18U)
-#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F12R2_FB19_Pos (19U)
-#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F12R2_FB20_Pos (20U)
-#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F12R2_FB21_Pos (21U)
-#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F12R2_FB22_Pos (22U)
-#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F12R2_FB23_Pos (23U)
-#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F12R2_FB24_Pos (24U)
-#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F12R2_FB25_Pos (25U)
-#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F12R2_FB26_Pos (26U)
-#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F12R2_FB27_Pos (27U)
-#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F12R2_FB28_Pos (28U)
-#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F12R2_FB29_Pos (29U)
-#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F12R2_FB30_Pos (30U)
-#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F12R2_FB31_Pos (31U)
-#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0_Pos (0U)
-#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F13R2_FB1_Pos (1U)
-#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F13R2_FB2_Pos (2U)
-#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F13R2_FB3_Pos (3U)
-#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F13R2_FB4_Pos (4U)
-#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F13R2_FB5_Pos (5U)
-#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F13R2_FB6_Pos (6U)
-#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F13R2_FB7_Pos (7U)
-#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F13R2_FB8_Pos (8U)
-#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F13R2_FB9_Pos (9U)
-#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F13R2_FB10_Pos (10U)
-#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F13R2_FB11_Pos (11U)
-#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F13R2_FB12_Pos (12U)
-#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F13R2_FB13_Pos (13U)
-#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F13R2_FB14_Pos (14U)
-#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F13R2_FB15_Pos (15U)
-#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F13R2_FB16_Pos (16U)
-#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F13R2_FB17_Pos (17U)
-#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F13R2_FB18_Pos (18U)
-#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F13R2_FB19_Pos (19U)
-#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F13R2_FB20_Pos (20U)
-#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F13R2_FB21_Pos (21U)
-#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F13R2_FB22_Pos (22U)
-#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F13R2_FB23_Pos (23U)
-#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F13R2_FB24_Pos (24U)
-#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F13R2_FB25_Pos (25U)
-#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F13R2_FB26_Pos (26U)
-#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F13R2_FB27_Pos (27U)
-#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F13R2_FB28_Pos (28U)
-#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F13R2_FB29_Pos (29U)
-#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F13R2_FB30_Pos (30U)
-#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F13R2_FB31_Pos (31U)
-#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA_Pos (0U)
-#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
-#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos (1U)
-#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
-#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos (2U)
-#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
-#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos (3U)
-#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
-#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
-#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
-#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos (6U)
-#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
-#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos (7U)
-#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
-#define SPI_CR1_SSI_Pos (8U)
-#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
-#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos (9U)
-#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
-#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos (10U)
-#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
-#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
-#define SPI_CR1_DFF_Pos (11U)
-#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
-#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos (12U)
-#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos (13U)
-#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
-#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos (14U)
-#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos (15U)
-#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN_Pos (0U)
-#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos (1U)
-#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos (2U)
-#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
-#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos (5U)
-#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
-#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos (6U)
-#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos (7U)
-#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
-#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE_Pos (0U)
-#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
-#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos (1U)
-#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
-#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos (2U)
-#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
-#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
-#define SPI_SR_UDR_Pos (3U)
-#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
-#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos (4U)
-#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
-#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos (5U)
-#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
-#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
-#define SPI_SR_OVR_Pos (6U)
-#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
-#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
-#define SPI_SR_BSY_Pos (7U)
-#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
-#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR_Pos (0U)
-#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
-#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY_Pos (0U)
-#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC_Pos (0U)
-#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC_Pos (0U)
-#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_I2SMOD_Pos (11U)
-#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE_Pos (0U)
-#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
-#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos (1U)
-#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
-#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos (3U)
-#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos (4U)
-#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
-#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos (5U)
-#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
-#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos (6U)
-#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
-#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos (7U)
-#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos (8U)
-#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
-#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
-#define I2C_CR1_STOP_Pos (9U)
-#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
-#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos (10U)
-#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
-#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos (11U)
-#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
-#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos (12U)
-#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
-#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos (13U)
-#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
-#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos (15U)
-#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
-#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
-
-/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ_Pos (0U)
-#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
-#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos (8U)
-#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
-#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos (9U)
-#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos (10U)
-#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos (11U)
-#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
-#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos (12U)
-#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
-#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
-
-/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos (0U)
-#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
-#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos (1U)
-#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
-#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos (2U)
-#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
-#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos (3U)
-#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
-#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos (4U)
-#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
-#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos (5U)
-#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
-#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos (6U)
-#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
-#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos (7U)
-#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
-#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos (8U)
-#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
-#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos (9U)
-#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
-#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos (15U)
-#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
-
-/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL_Pos (0U)
-#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos (1U)
-#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
-#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
-
-/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR_Pos (0U)
-#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
-#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
-
-/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB_Pos (0U)
-#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
-#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos (1U)
-#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
-#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos (2U)
-#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
-#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos (3U)
-#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
-#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos (4U)
-#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
-#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos (6U)
-#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
-#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos (7U)
-#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
-#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos (8U)
-#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
-#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos (9U)
-#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
-#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos (10U)
-#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
-#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos (11U)
-#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
-#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos (12U)
-#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
-#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos (14U)
-#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos (15U)
-#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
-
-/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL_Pos (0U)
-#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
-#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos (1U)
-#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
-#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos (2U)
-#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
-#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos (4U)
-#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
-#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos (5U)
-#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos (6U)
-#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos (7U)
-#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
-#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos (8U)
-#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
-#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
-
-/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR_Pos (0U)
-#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
-#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos (14U)
-#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
-#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos (15U)
-#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
-#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
-
-/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE_Pos (0U)
-#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
-#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE_Pos (0U)
-#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
-#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
-#define USART_SR_FE_Pos (1U)
-#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
-#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
-#define USART_SR_NE_Pos (2U)
-#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
-#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos (3U)
-#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
-#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
-#define USART_SR_IDLE_Pos (4U)
-#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
-#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos (5U)
-#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
-#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos (6U)
-#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
-#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
-#define USART_SR_TXE_Pos (7U)
-#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
-#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos (8U)
-#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
-#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos (9U)
-#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
-#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
-
-/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR_Pos (0U)
-#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
-#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction_Pos (0U)
-#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa_Pos (4U)
-#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK_Pos (0U)
-#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
-#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
-#define USART_CR1_RWU_Pos (1U)
-#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
-#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos (2U)
-#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
-#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
-#define USART_CR1_TE_Pos (3U)
-#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
-#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos (4U)
-#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
-#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos (5U)
-#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
-#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos (6U)
-#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
-#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos (7U)
-#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
-#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos (8U)
-#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
-#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos (9U)
-#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
-#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
-#define USART_CR1_PCE_Pos (10U)
-#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
-#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos (11U)
-#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
-#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
-#define USART_CR1_M_Pos (12U)
-#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
-#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
-#define USART_CR1_UE_Pos (13U)
-#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
-#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD_Pos (0U)
-#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
-#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos (5U)
-#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
-#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos (6U)
-#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
-#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos (8U)
-#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
-#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos (9U)
-#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
-#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos (10U)
-#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
-#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos (11U)
-#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
-#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos (12U)
-#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
-#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
-#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos (14U)
-#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
-#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE_Pos (0U)
-#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
-#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos (1U)
-#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
-#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos (2U)
-#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
-#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos (3U)
-#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
-#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos (4U)
-#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
-#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos (5U)
-#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
-#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos (6U)
-#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
-#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos (7U)
-#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
-#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos (8U)
-#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
-#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos (9U)
-#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
-#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos (10U)
-#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
-#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC_Pos (0U)
-#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
-#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
-#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
-#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
-#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
-#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
-#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
-#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
-#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos (8U)
-#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
-#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
-
-/******************************************************************************/
-/* */
-/* Debug MCU */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
-#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos (16U)
-#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos (1U)
-#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
-#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
-#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos (6U)
-#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
-#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
-#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
-#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
-#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
-#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
-#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
-#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
-#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
-#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
-#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************************************************************************/
-/* */
-/* FLASH and Option Bytes Registers */
-/* */
-/******************************************************************************/
-/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY_Pos (0U)
-#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
-#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
-#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
-
-#define FLASH_ACR_HLFCYA_Pos (3U)
-#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
-#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
-#define FLASH_ACR_PRFTBE_Pos (4U)
-#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
-#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS_Pos (5U)
-#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
-#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
-
-/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR_Pos (0U)
-#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
-
-#define RDP_KEY_Pos (0U)
-#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
-#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
-#define FLASH_KEY1_Pos (0U)
-#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
-#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
-#define FLASH_KEY2_Pos (0U)
-#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
-#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
-
-/***************** Bit definition for FLASH_OPTKEYR register ****************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
-#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
-
-#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
-#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
-
-/****************** Bit definition for FLASH_SR register ********************/
-#define FLASH_SR_BSY_Pos (0U)
-#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
-#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
-#define FLASH_SR_PGERR_Pos (2U)
-#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
-#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
-#define FLASH_SR_WRPRTERR_Pos (4U)
-#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
-#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
-#define FLASH_SR_EOP_Pos (5U)
-#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
-#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
-
-/******************* Bit definition for FLASH_CR register *******************/
-#define FLASH_CR_PG_Pos (0U)
-#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
-#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
-#define FLASH_CR_PER_Pos (1U)
-#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
-#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
-#define FLASH_CR_MER_Pos (2U)
-#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
-#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
-#define FLASH_CR_OPTPG_Pos (4U)
-#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
-#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
-#define FLASH_CR_OPTER_Pos (5U)
-#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
-#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
-#define FLASH_CR_STRT_Pos (6U)
-#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
-#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
-#define FLASH_CR_LOCK_Pos (7U)
-#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
-#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
-#define FLASH_CR_OPTWRE_Pos (9U)
-#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
-#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
-#define FLASH_CR_ERRIE_Pos (10U)
-#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
-#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
-#define FLASH_CR_EOPIE_Pos (12U)
-#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
-#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
-
-/******************* Bit definition for FLASH_AR register *******************/
-#define FLASH_AR_FAR_Pos (0U)
-#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR_Pos (0U)
-#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
-#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
-#define FLASH_OBR_RDPRT_Pos (1U)
-#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
-#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
-
-#define FLASH_OBR_IWDG_SW_Pos (2U)
-#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
-#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
-#define FLASH_OBR_nRST_STOP_Pos (3U)
-#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
-#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos (4U)
-#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
-#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
-#define FLASH_OBR_USER_Pos (2U)
-#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
-#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
-#define FLASH_OBR_DATA0_Pos (10U)
-#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
-#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
-#define FLASH_OBR_DATA1_Pos (18U)
-#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
-#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
-
-/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP_Pos (0U)
-#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for FLASH_RDP register *******************/
-#define FLASH_RDP_RDP_Pos (0U)
-#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
-#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
-#define FLASH_RDP_nRDP_Pos (8U)
-#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
-#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
-
-/****************** Bit definition for FLASH_USER register ******************/
-#define FLASH_USER_USER_Pos (16U)
-#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
-#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
-#define FLASH_USER_nUSER_Pos (24U)
-#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
-#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
-
-/****************** Bit definition for FLASH_Data0 register *****************/
-#define FLASH_DATA0_DATA0_Pos (0U)
-#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
-#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
-#define FLASH_DATA0_nDATA0_Pos (8U)
-#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
-#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_Data1 register *****************/
-#define FLASH_DATA1_DATA1_Pos (16U)
-#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
-#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
-#define FLASH_DATA1_nDATA1_Pos (24U)
-#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
-#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_WRP0 register ******************/
-#define FLASH_WRP0_WRP0_Pos (0U)
-#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
-#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP0_nWRP0_Pos (8U)
-#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
-#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP1 register ******************/
-#define FLASH_WRP1_WRP1_Pos (16U)
-#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
-#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP1_nWRP1_Pos (24U)
-#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
-#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP2 register ******************/
-#define FLASH_WRP2_WRP2_Pos (0U)
-#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
-#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP2_nWRP2_Pos (8U)
-#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
-#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP3 register ******************/
-#define FLASH_WRP3_WRP3_Pos (16U)
-#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
-#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP3_nWRP3_Pos (24U)
-#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
-#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
-
-
-
-/**
- * @}
-*/
-
-/**
- * @}
-*/
-
-/** @addtogroup Exported_macro
- * @{
- */
-
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
- ((INSTANCE) == ADC2))
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
-
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/****************************** CAN Instances *********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
- ((INSTANCE) == DMA1_Channel2) || \
- ((INSTANCE) == DMA1_Channel3) || \
- ((INSTANCE) == DMA1_Channel4) || \
- ((INSTANCE) == DMA1_Channel5) || \
- ((INSTANCE) == DMA1_Channel6) || \
- ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
- ((INSTANCE) == I2C2))
-
-/******************************* SMBUS Instances ******************************/
-#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
- ((INSTANCE) == SPI2))
-
-/****************************** START TIM Instances ***************************/
-/****************************** TIM Instances *********************************/
-#define IS_TIM_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM1)
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
- ((((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM2) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM3) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM4) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))))
-
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
- (((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3)))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM1)
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM1)
-
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
-
-/****************************** END TIM Instances *****************************/
-
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/***************** UART Instances : DMA mode available **********************/
-#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
-
-/**************************** WWDG Instances *****************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-
-
-#define RCC_HSE_MIN 4000000U
-#define RCC_HSE_MAX 16000000U
-
-#define RCC_MAX_FREQUENCY 72000000U
-
-/**
- * @}
- */
-/******************************************************************************/
-/* For a painless codes migration between the STM32F1xx device product */
-/* lines, the aliases defined below are put in place to overcome the */
-/* differences in the interrupt handlers and IRQn definitions. */
-/* No need to update developed interrupt code when moving across */
-/* product lines within the same STM32F1 Family */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define ADC1_IRQn ADC1_2_IRQn
-#define TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
-#define TIM10_IRQn TIM1_UP_IRQn
-#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
-#define CEC_IRQn USBWakeUp_IRQn
-#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
-#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
-#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
-#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
-
-
-/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
-#define CEC_IRQHandler USBWakeUp_IRQHandler
-#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
-#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
- }
-#endif /* __cplusplus */
-
-#endif /* __STM32F103xB_H */
-
-
-
- /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,238 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx.h
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The STM32F1xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
- * rather than drivers API), this option is controlled by
- * "#define USE_HAL_DRIVER"
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f1xx
- * @{
- */
-
-#ifndef __STM32F1XX_H
-#define __STM32F1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/**
- * @brief STM32 Family
- */
-#if !defined (STM32F1)
-#define STM32F1
-#endif /* STM32F1 */
-
-/* Uncomment the line below according to the target STM32L device used in your
- application
- */
-
-#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
- !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
- !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
- /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
- /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
- /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
- /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
- /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
- /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
- /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
- /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
- /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
-#define STM32F103xB /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
- /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
- /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
- /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
- /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if !defined (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
- * @brief CMSIS Device version number V4.2.0
- */
-#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
-#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
- |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
- |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
- |(__STM32F1_CMSIS_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Device_Included
- * @{
- */
-
-#if defined(STM32F100xB)
- #include "stm32f100xb.h"
-#elif defined(STM32F100xE)
- #include "stm32f100xe.h"
-#elif defined(STM32F101x6)
- #include "stm32f101x6.h"
-#elif defined(STM32F101xB)
- #include "stm32f101xb.h"
-#elif defined(STM32F101xE)
- #include "stm32f101xe.h"
-#elif defined(STM32F101xG)
- #include "stm32f101xg.h"
-#elif defined(STM32F102x6)
- #include "stm32f102x6.h"
-#elif defined(STM32F102xB)
- #include "stm32f102xb.h"
-#elif defined(STM32F103x6)
- #include "stm32f103x6.h"
-#elif defined(STM32F103xB)
- #include "stm32f103xb.h"
-#elif defined(STM32F103xE)
- #include "stm32f103xe.h"
-#elif defined(STM32F103xG)
- #include "stm32f103xg.h"
-#elif defined(STM32F105xC)
- #include "stm32f105xc.h"
-#elif defined(STM32F107xC)
- #include "stm32f107xc.h"
-#else
- #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_types
- * @{
- */
-typedef enum
-{
- RESET = 0,
- SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
- DISABLE = 0,
- ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
- ERROR = 0,
- SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
- * @}
- */
-
-
-/** @addtogroup Exported_macros
- * @{
- */
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
-
-
-/**
- * @}
- */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32f1xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F1xx_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,365 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal.h
- * @author MCD Application Team
- * @brief This file contains all the functions prototypes for the HAL
- * module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_H
-#define __STM32F1xx_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_conf.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HAL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
- * @{
- */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
- * @{
- */
-typedef enum
-{
- HAL_TICK_FREQ_10HZ = 100U,
- HAL_TICK_FREQ_100HZ = 10U,
- HAL_TICK_FREQ_1KHZ = 1U,
- HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
- * @{
- */
-
-/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
- * @brief Freeze/Unfreeze Peripherals in Debug mode
- * Note: On devices STM32F10xx8 and STM32F10xxB,
- * STM32F101xC/D/E and STM32F103xC/D/E,
- * STM32F101xF/G and STM32F103xF/G
- * STM32F10xx4 and STM32F10xx6
- * Debug registers DBGMCU_IDCODE and DBGMCU_CR are accessible only in
- * debug mode (not accessible by the user software in normal mode).
- * Refer to errata sheet of these devices for more details.
- * @{
- */
-
-/* Peripherals on APB1 */
-/**
- * @brief TIM2 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM2_STOP)
-
-/**
- * @brief TIM3 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM3_STOP)
-
-#if defined (DBGMCU_CR_DBG_TIM4_STOP)
-/**
- * @brief TIM4 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM4_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM5_STOP)
-/**
- * @brief TIM5 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM5_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM6_STOP)
-/**
- * @brief TIM6 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM6_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM7_STOP)
-/**
- * @brief TIM7 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM7_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM12_STOP)
-/**
- * @brief TIM12 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM12_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM13_STOP)
-/**
- * @brief TIM13 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM13_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM14_STOP)
-/**
- * @brief TIM14 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM14_STOP)
-#endif
-
-/**
- * @brief WWDG Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_WWDG_STOP)
-
-/**
- * @brief IWDG Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_IWDG_STOP)
-
-/**
- * @brief I2C1 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT)
-
-#if defined (DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-/**
- * @brief I2C2 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#endif
-
-#if defined (DBGMCU_CR_DBG_CAN1_STOP)
-/**
- * @brief CAN1 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN1_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_CAN2_STOP)
-/**
- * @brief CAN2 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CAN2_STOP)
-#endif
-
-/* Peripherals on APB2 */
-#if defined (DBGMCU_CR_DBG_TIM1_STOP)
-/**
- * @brief TIM1 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM1_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM8_STOP)
-/**
- * @brief TIM8 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM8_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM9_STOP)
-/**
- * @brief TIM9 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM9_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM10_STOP)
-/**
- * @brief TIM10 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM10_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM11_STOP)
-/**
- * @brief TIM11 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM11_STOP)
-#endif
-
-
-#if defined (DBGMCU_CR_DBG_TIM15_STOP)
-/**
- * @brief TIM15 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM15_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM16_STOP)
-/**
- * @brief TIM16 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM16_STOP)
-#endif
-
-#if defined (DBGMCU_CR_DBG_TIM17_STOP)
-/**
- * @brief TIM17 Peripherals Debug mode
- */
-#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TIM17_STOP)
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
- * @{
- */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
- ((FREQ) == HAL_TICK_FREQ_100HZ) || \
- ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
- * @{
- */
-/** @addtogroup HAL_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
-/**
- * @}
- */
-
-/** @addtogroup HAL_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-void HAL_GetUID(uint32_t *UID);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
- * @{
- */
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Constants HAL Private Constants
- * @{
- */
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_adc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,965 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_adc.h
- * @author MCD Application Team
- * @brief Header file containing functions prototypes of ADC HAL library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_ADC_H
-#define __STM32F1xx_HAL_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
- * @{
- */
-
-/**
- * @brief Structure definition of ADC and regular group initialization
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
- * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
- * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
- * ADC can be either disabled or enabled without conversion on going on regular group.
- */
-typedef struct
-{
- uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
- or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
- This parameter can be a value of @ref ADC_Data_align */
- uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
- This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
- If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
- Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
- If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
- Scan direction is upward: from rank1 to rank 'n'.
- This parameter can be a value of @ref ADC_Scan_mode
- Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
- or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
- the last conversion of the sequence. All previous conversions would be overwritten by the last one.
- Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
- uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
- after the selected trigger occurred (software start or external trigger).
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
- To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
- uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE. */
- uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
- If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
- This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
- uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
- If set to ADC_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge.
- This parameter can be a value of @ref ADC_External_trigger_source_Regular */
-}ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of ADC channel for regular group
- * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
- * ADC can be either disabled or enabled without conversion on going on regular group.
- */
-typedef struct
-{
- uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
- This parameter can be a value of @ref ADC_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
- Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
- Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
- It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
- Refer to errata sheet of these devices for more details. */
- uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
- This parameter can be a value of @ref ADC_regular_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
- This parameter can be a value of @ref ADC_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
-}ADC_ChannelConfTypeDef;
-
-/**
- * @brief ADC Configuration analog watchdog definition
- * @note The setting of these parameters with function is conditioned to ADC state.
- * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
- */
-typedef struct
-{
- uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
- This parameter can be a value of @ref ADC_analog_watchdog_mode. */
- uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
- This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
- This parameter can be a value of @ref ADC_channels. */
- uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
- This parameter can be set to ENABLE or DISABLE */
- uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
- uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
- This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
- uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
-}ADC_AnalogWDGConfTypeDef;
-
-/**
- * @brief HAL ADC state machine: ADC states definition (bitfields)
- */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
- external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Not available on STM32F1 device: Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP 0x00000800U /*!< Not available on STM32F1 device: End Of Sampling flag raised */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
- external trigger, low power auto power-on, multimode ADC master control) */
-#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF 0x00004000U /*!< Not available on STM32F1 device: Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F1 device: Out-of-window occurrence of analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< ADC in multimode slave state, controlled by another ADC master ( */
-
-
-/**
- * @brief ADC handle Structure definition
- */
-typedef struct
-{
- ADC_TypeDef *Instance; /*!< Register base address */
-
- ADC_InitTypeDef Init; /*!< ADC required parameters */
-
- DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
-
- HAL_LockTypeDef Lock; /*!< ADC locking object */
-
- __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
-
- __IO uint32_t ErrorCode; /*!< ADC Error code */
-}ADC_HandleTypeDef;
-/**
- * @}
- */
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_Error_Code ADC Error Code
- * @{
- */
-#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
-#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
- enable/disable, erroneous state */
-#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
-#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
-
-/**
- * @}
- */
-
-
-/** @defgroup ADC_Data_align ADC data alignment
- * @{
- */
-#define ADC_DATAALIGN_RIGHT 0x00000000U
-#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
-/**
- * @}
- */
-
-/** @defgroup ADC_Scan_mode ADC scan mode
- * @{
- */
-/* Note: Scan mode values are not among binary choices ENABLE/DISABLE for */
-/* compatibility with other STM32 devices having a sequencer with */
-/* additional options. */
-#define ADC_SCAN_DISABLE 0x00000000U
-#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
-/**
- * @}
- */
-
-/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
- * @{
- */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
-#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
-/**
- * @}
- */
-
-/** @defgroup ADC_channels ADC channels
- * @{
- */
-/* Note: Depending on devices, some channels may not be available on package */
-/* pins. Refer to device datasheet for channels availability. */
-#define ADC_CHANNEL_0 0x00000000U
-#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR3_SQ1_1 ))
-#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR3_SQ1_2 ))
-#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
-#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR3_SQ1_3 ))
-#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 ))
-#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 ))
-#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 ))
-#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR3_SQ1_3 | ADC_SQR3_SQ1_2 | ADC_SQR3_SQ1_1 | ADC_SQR3_SQ1_0))
-#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4 ))
-#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 | ADC_SQR3_SQ1_0))
-
-#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin) */
-#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin) */
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_times ADC sampling times
- * @{
- */
-#define ADC_SAMPLETIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_0)) /*!< Sampling time 7.5 ADC clock cycles */
-#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 )) /*!< Sampling time 13.5 ADC clock cycles */
-#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)( ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 28.5 ADC clock cycles */
-#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 )) /*!< Sampling time 41.5 ADC clock cycles */
-#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 55.5 ADC clock cycles */
-#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 )) /*!< Sampling time 71.5 ADC clock cycles */
-#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0)) /*!< Sampling time 239.5 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_rank ADC rank into regular group
- * @{
- */
-#define ADC_REGULAR_RANK_1 0x00000001U
-#define ADC_REGULAR_RANK_2 0x00000002U
-#define ADC_REGULAR_RANK_3 0x00000003U
-#define ADC_REGULAR_RANK_4 0x00000004U
-#define ADC_REGULAR_RANK_5 0x00000005U
-#define ADC_REGULAR_RANK_6 0x00000006U
-#define ADC_REGULAR_RANK_7 0x00000007U
-#define ADC_REGULAR_RANK_8 0x00000008U
-#define ADC_REGULAR_RANK_9 0x00000009U
-#define ADC_REGULAR_RANK_10 0x0000000AU
-#define ADC_REGULAR_RANK_11 0x0000000BU
-#define ADC_REGULAR_RANK_12 0x0000000CU
-#define ADC_REGULAR_RANK_13 0x0000000DU
-#define ADC_REGULAR_RANK_14 0x0000000EU
-#define ADC_REGULAR_RANK_15 0x0000000FU
-#define ADC_REGULAR_RANK_16 0x00000010U
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
- * @{
- */
-#define ADC_ANALOGWATCHDOG_NONE 0x00000000U
-#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-/**
- * @}
- */
-
-/** @defgroup ADC_conversion_group ADC conversion group
- * @{
- */
-#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
-#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
-#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
-/**
- * @}
- */
-
-/** @defgroup ADC_Event_type ADC Event type
- * @{
- */
-#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
-
-#define ADC_AWD1_EVENT ADC_AWD_EVENT /*!< ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having several analog watchdogs */
-/**
- * @}
- */
-
-/** @defgroup ADC_interrupts_definition ADC interrupts definition
- * @{
- */
-#define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition ADC flags definition
- * @{
- */
-#define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
-#define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
-#define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
-#define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
-#define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup ADC_Private_Constants ADC Private Constants
- * @{
- */
-
-/** @defgroup ADC_conversion_cycles ADC conversion cycles
- * @{
- */
-/* ADC conversion cycles (unit: ADC clock cycles) */
-/* (selected sampling time + conversion time of 12.5 ADC clock cycles, with */
-/* resolution 12 bits) */
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_1CYCLE5 14U
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 20U
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_13CYCLES5 26U
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5 41U
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_41CYCLES5 54U
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_55CYCLES5 68U
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 84U
-#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5 252U
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
- * @{
- */
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
- (ADC_SMPR2_SMP9_2 | ADC_SMPR2_SMP8_2 | ADC_SMPR2_SMP7_2 | ADC_SMPR2_SMP6_2 | \
- ADC_SMPR2_SMP5_2 | ADC_SMPR2_SMP4_2 | ADC_SMPR2_SMP3_2 | ADC_SMPR2_SMP2_2 | \
- ADC_SMPR2_SMP1_2 | ADC_SMPR2_SMP0_2)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
- (ADC_SMPR1_SMP17_2 | ADC_SMPR1_SMP16_2 | ADC_SMPR1_SMP15_2 | ADC_SMPR1_SMP14_2 | \
- ADC_SMPR1_SMP13_2 | ADC_SMPR1_SMP12_2 | ADC_SMPR1_SMP11_2 | ADC_SMPR1_SMP10_2 )
-
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
- (ADC_SMPR2_SMP9_1 | ADC_SMPR2_SMP8_1 | ADC_SMPR2_SMP7_1 | ADC_SMPR2_SMP6_1 | \
- ADC_SMPR2_SMP5_1 | ADC_SMPR2_SMP4_1 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP2_1 | \
- ADC_SMPR2_SMP1_1 | ADC_SMPR2_SMP0_1)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
- (ADC_SMPR1_SMP17_1 | ADC_SMPR1_SMP16_1 | ADC_SMPR1_SMP15_1 | ADC_SMPR1_SMP14_1 | \
- ADC_SMPR1_SMP13_1 | ADC_SMPR1_SMP12_1 | ADC_SMPR1_SMP11_1 | ADC_SMPR1_SMP10_1 )
-
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
- (ADC_SMPR2_SMP9_0 | ADC_SMPR2_SMP8_0 | ADC_SMPR2_SMP7_0 | ADC_SMPR2_SMP6_0 | \
- ADC_SMPR2_SMP5_0 | ADC_SMPR2_SMP4_0 | ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP2_0 | \
- ADC_SMPR2_SMP1_0 | ADC_SMPR2_SMP0_0)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
- (ADC_SMPR1_SMP17_0 | ADC_SMPR1_SMP16_0 | ADC_SMPR1_SMP15_0 | ADC_SMPR1_SMP14_0 | \
- ADC_SMPR1_SMP13_0 | ADC_SMPR1_SMP12_0 | ADC_SMPR1_SMP11_0 | ADC_SMPR1_SMP10_0 )
-
-#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS 0x00000000U
-#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
-#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
-#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
-#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
-
-#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS 0x00000000U
-#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
-#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
-#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
-#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 | ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
-/**
- * @}
- */
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
-#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD )
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
- * @{
- */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user. */
-
-/**
- * @brief Enable the ADC peripheral
- * @note ADC enable requires a delay for ADC stabilization time
- * (refer to device datasheet, parameter tSTAB)
- * @note On STM32F1, if ADC is already enabled this macro trigs a conversion
- * SW start on regular group.
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define __HAL_ADC_ENABLE(__HANDLE__) \
- (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-
-/**
- * @brief Disable the ADC peripheral
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define __HAL_ADC_DISABLE(__HANDLE__) \
- (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
-
-/** @brief Enable the ADC end of conversion interrupt.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
- * @retval None
- */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
- (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief Disable the ADC end of conversion interrupt.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC Interrupt
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
- * @retval None
- */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
- (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
- * @param __HANDLE__: ADC handle
- * @param __INTERRUPT__: ADC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
- * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
- * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
- * @retval None
- */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
- (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected ADC's flag status.
- * @param __HANDLE__: ADC handle
- * @param __FLAG__: ADC flag
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_STRT: ADC Regular group start flag
- * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
- * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
- * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
- * @retval None
- */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
- ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the ADC's pending flags
- * @param __HANDLE__: ADC handle
- * @param __FLAG__: ADC flag
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_STRT: ADC Regular group start flag
- * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
- * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
- * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
- * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
- * @retval None
- */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
-
-/** @brief Reset ADC handle state
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
- ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
- * @{
- */
-/* Macro reserved for internal HAL driver usage, not intended to be used in */
-/* code of final user. */
-
-/**
- * @brief Verification of ADC state: enabled or disabled
- * @param __HANDLE__: ADC handle
- * @retval SET (ADC enabled) or RESET (ADC disabled)
- */
-#define ADC_IS_ENABLE(__HANDLE__) \
- ((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
- ) ? SET : RESET)
-
-/**
- * @brief Test if conversion trigger of regular group is software start
- * or external trigger.
- * @param __HANDLE__: ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
- (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
-
-/**
- * @brief Test if conversion trigger of injected group is software start
- * or external trigger.
- * @param __HANDLE__: ADC handle
- * @retval SET (software start) or RESET (external trigger)
- */
-#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
- (READ_BIT((__HANDLE__)->Instance->CR2, ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
-
-/**
- * @brief Simultaneously clears and sets specific bits of the handle State
- * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
- * the first parameter is the ADC handle State, the second parameter is the
- * bit field to clear, the third and last parameter is the bit field to set.
- * @retval None
- */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
- * @brief Clear ADC error code (set it to error code: "no error")
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
- ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
- * @brief Set ADC number of conversions into regular channel sequence length.
- * @param _NbrOfConversion_: Regular channel sequence length
- * @retval None
- */
-#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
- (((_NbrOfConversion_) - (uint8_t)1) << ADC_SQR1_L_Pos)
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 10 and 18.
- * @param _SAMPLETIME_: Sample time parameter.
- * @param _CHANNELNB_: Channel number.
- * @retval None
- */
-#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (ADC_SMPR1_SMP11_Pos * ((_CHANNELNB_) - 10)))
-
-/**
- * @brief Set the ADC's sample time for channel numbers between 0 and 9.
- * @param _SAMPLETIME_: Sample time parameter.
- * @param _CHANNELNB_: Channel number.
- * @retval None
- */
-#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
- ((_SAMPLETIME_) << (ADC_SMPR2_SMP1_Pos * (_CHANNELNB_)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 1 and 6.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @retval None
- */
-#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (ADC_SQR3_SQ2_Pos * ((_RANKNB_) - 1)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 7 and 12.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @retval None
- */
-#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (ADC_SQR2_SQ8_Pos * ((_RANKNB_) - 7)))
-
-/**
- * @brief Set the selected regular channel rank for rank between 13 and 16.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @retval None
- */
-#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
- ((_CHANNELNB_) << (ADC_SQR1_SQ14_Pos * ((_RANKNB_) - 13)))
-
-/**
- * @brief Set the injected sequence length.
- * @param _JSQR_JL_: Sequence length.
- * @retval None
- */
-#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
- (((_JSQR_JL_) -1) << ADC_JSQR_JL_Pos)
-
-/**
- * @brief Set the selected injected channel rank
- * Note: on STM32F1 devices, channel rank position in JSQR register
- * is depending on total number of ranks selected into
- * injected sequencer (ranks sequence starting from 4-JL)
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @param _JSQR_JL_: Sequence length.
- * @retval None
- */
-#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
- ((_CHANNELNB_) << (ADC_JSQR_JSQ2_Pos * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
-
-/**
- * @brief Enable ADC continuous conversion mode.
- * @param _CONTINUOUS_MODE_: Continuous mode.
- * @retval None
- */
-#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
- ((_CONTINUOUS_MODE_) << ADC_CR2_CONT_Pos)
-
-/**
- * @brief Configures the number of discontinuous conversions for the regular group channels.
- * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
- * @retval None
- */
-#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
- (((_NBR_DISCONTINUOUS_CONV_) - 1) << ADC_CR1_DISCNUM_Pos)
-
-/**
- * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
- * @param _SCAN_MODE_: Scan conversion mode.
- * @retval None
- */
-/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
-/* is equivalent to ADC_SCAN_ENABLE. */
-#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
- (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
- )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
- )
-
-/**
- * @brief Get the maximum ADC conversion cycles on all channels.
- * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
- * Approximation of sampling time within 4 ranges, returns the highest value:
- * below 7.5 cycles {1.5 cycle; 7.5 cycles},
- * between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
- * between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
- * equal to 239.5 cycles
- * Unit: ADC clock cycles
- * @param __HANDLE__: ADC handle
- * @retval ADC conversion cycles on all channels
- */
-#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
- (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
- \
- (( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
- ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
- : \
- ((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) || \
- ((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
- (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
- ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
- )
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
- ((ALIGN) == ADC_DATAALIGN_LEFT) )
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
- ((SCAN_MODE) == ADC_SCAN_ENABLE) )
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
- ((CHANNEL) == ADC_CHANNEL_1) || \
- ((CHANNEL) == ADC_CHANNEL_2) || \
- ((CHANNEL) == ADC_CHANNEL_3) || \
- ((CHANNEL) == ADC_CHANNEL_4) || \
- ((CHANNEL) == ADC_CHANNEL_5) || \
- ((CHANNEL) == ADC_CHANNEL_6) || \
- ((CHANNEL) == ADC_CHANNEL_7) || \
- ((CHANNEL) == ADC_CHANNEL_8) || \
- ((CHANNEL) == ADC_CHANNEL_9) || \
- ((CHANNEL) == ADC_CHANNEL_10) || \
- ((CHANNEL) == ADC_CHANNEL_11) || \
- ((CHANNEL) == ADC_CHANNEL_12) || \
- ((CHANNEL) == ADC_CHANNEL_13) || \
- ((CHANNEL) == ADC_CHANNEL_14) || \
- ((CHANNEL) == ADC_CHANNEL_15) || \
- ((CHANNEL) == ADC_CHANNEL_16) || \
- ((CHANNEL) == ADC_CHANNEL_17) )
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
- ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \
- ((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
-
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
- ((CHANNEL) == ADC_REGULAR_RANK_10) || \
- ((CHANNEL) == ADC_REGULAR_RANK_11) || \
- ((CHANNEL) == ADC_REGULAR_RANK_12) || \
- ((CHANNEL) == ADC_REGULAR_RANK_13) || \
- ((CHANNEL) == ADC_REGULAR_RANK_14) || \
- ((CHANNEL) == ADC_REGULAR_RANK_15) || \
- ((CHANNEL) == ADC_REGULAR_RANK_16) )
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
- ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
-
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
- ((CONVERSION) == ADC_INJECTED_GROUP) || \
- ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
-
-#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
-
-
-/** @defgroup ADC_range_verification ADC range verification
- * For a unique ADC resolution: 12 bits
- * @{
- */
-#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= 0x0FFFU)
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
- * @{
- */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
-/**
- * @}
- */
-
-/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
- * @{
- */
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include ADC HAL Extension module */
-#include "stm32f1xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
- * @{
- */
-
-/** @addtogroup ADC_Exported_Functions_Group1
- * @{
- */
-
-
-/* Initialization and de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
- * @}
- */
-
-/* IO operation functions *****************************************************/
-
-/** @addtogroup ADC_Exported_Functions_Group2
- * @{
- */
-
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADC_Exported_Functions_Group3
- * @{
- */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
- * @}
- */
-
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
- * @{
- */
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/* Internal HAL driver functions **********************************************/
-/** @addtogroup ADC_Private_Functions
- * @{
- */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
-void ADC_StabilizationTime(uint32_t DelayUs);
-void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-void ADC_DMAError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_adc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_adc_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,726 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_adc_ex.h
- * @author MCD Application Team
- * @brief Header file of ADC HAL extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_ADC_EX_H
-#define __STM32F1xx_HAL_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup ADCEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
- * @{
- */
-
-/**
- * @brief ADC Configuration injected Channel structure definition
- * @note Parameters of this structure are shared within 2 scopes:
- * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
- * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
- * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
- * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
- * ADC state can be either:
- * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
- * - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
- */
-typedef struct
-{
- uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
- This parameter can be a value of @ref ADC_channels
- Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
- Note: On STM32F1 devices with several ADC: Only ADC1 can access internal measurement channels (VrefInt/TempSensor)
- Note: On STM32F10xx8 and STM32F10xxB devices: A low-amplitude voltage glitch may be generated (on ADC input 0) on the PA0 pin, when the ADC is converting with injection trigger.
- It is advised to distribute the analog channels so that Channel 0 is configured as an injected channel.
- Refer to errata sheet of these devices for more details. */
- uint32_t InjectedRank; /*!< Rank in the injected group sequencer
- This parameter must be a value of @ref ADCEx_injected_rank
- Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
- uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
- Unit: ADC clock cycles
- Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
- This parameter can be a value of @ref ADC_sampling_times
- Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
- If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
- Note: In case of usage of internal measurement channels (VrefInt/TempSensor),
- sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
- Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 5us to 17.1us min). */
- uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
- Offset value must be a positive number.
- Depending of ADC resolution selected (12, 10, 8 or 6 bits),
- this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
- uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
- To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
- This parameter must be a number between Min_Data = 1 and Max_Data = 4.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
- Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
- Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
- This parameter can be set to ENABLE or DISABLE.
- Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
- This parameter can be set to ENABLE or DISABLE.
- Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
- Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
- Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
- To maintain JAUTO always enabled, DMA must be configured in circular mode.
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
- uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
- If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
- If set to external trigger source, triggering is on event rising edge.
- This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
- Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
- If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
- Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
- configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef;
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/**
- * @brief Structure definition of ADC multimode
- * @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
- * State of ADCs of the common group must be: disabled.
- */
-typedef struct
-{
- uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
- This parameter can be a value of @ref ADCEx_Common_mode
- Note: In dual mode, a change of channel configuration generates a restart that can produce a loss of synchronization. It is recommended to disable dual mode before any configuration change.
- Note: In case of simultaneous mode used: Exactly the same sampling time should be configured for the 2 channels that will be sampled simultaneously by ACD1 and ADC2.
- Note: In case of interleaved mode used: To avoid overlap between conversions, maximum sampling time allowed is 7 ADC clock cycles for fast interleaved mode and 14 ADC clock cycles for slow interleaved mode.
- Note: Some multimode parameters are fixed on STM32F1 and can be configured on other STM32 devices with several ADC (multimode configuration structure can have additional parameters).
- The equivalences are:
- - Parameter 'DMAAccessMode': On STM32F1, this parameter is fixed to 1 DMA channel (one DMA channel for both ADC, DMA of ADC master). On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_DMAACCESSMODE_12_10_BITS'.
- - Parameter 'TwoSamplingDelay': On STM32F1, this parameter is fixed to 7 or 14 ADC clock cycles depending on fast or slow interleaved mode selected. On other STM32 devices with several ADC, this is equivalent to parameter 'ADC_TWOSAMPLINGDELAY_7CYCLES' (for fast interleaved mode). */
-
-
-}ADC_MultiModeTypeDef;
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
- * @}
- */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
- * @{
- */
-
-/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
- * @{
- */
-#define ADC_INJECTED_RANK_1 0x00000001U
-#define ADC_INJECTED_RANK_2 0x00000002U
-#define ADC_INJECTED_RANK_3 0x00000003U
-#define ADC_INJECTED_RANK_4 0x00000004U
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
- * @{
- */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE 0x00000000U
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
-/**
- * @}
- */
-
-/** @defgroup ADC_External_trigger_source_Regular ADC External trigger selection for regular group
- * @{
- */
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target, sorted by trigger name: */
-
-/*!< External triggers of regular group for ADC1&ADC2 only */
-#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/*!< External triggers of regular group for ADC3 only */
-#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_EXTERNALTRIG_T2_CC3
-#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_EXTERNALTRIG_T3_CC1
-#define ADC_EXTERNALTRIGCONV_T5_CC1 ADC3_EXTERNALTRIG_T5_CC1
-#define ADC_EXTERNALTRIGCONV_T5_CC3 ADC3_EXTERNALTRIG_T5_CC3
-#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_EXTERNALTRIG_T8_CC1
-#endif /* STM32F103xE || defined STM32F103xG */
-
-/*!< External triggers of regular group for all ADC instances */
-#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_3_EXTERNALTRIG_T1_CC3
-
-#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/*!< Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
-/* XL-density devices. */
-/* To use it on ADC or ADC2, a remap of trigger must be done from */
-/* EXTI line 11 to TIM8_TRGO with macro: */
-/* __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() */
-/* __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() */
-
-/* Note for internal constant value management: If TIM8_TRGO is available, */
-/* its definition is set to value for ADC1&ADC2 by default and changed to */
-/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
-#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
-#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#define ADC_SOFTWARE_START ADC1_2_3_SWSTART
-/**
- * @}
- */
-
-/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger selection for injected group
- * @{
- */
-/*!< List of external triggers with generic trigger name, independently of */
-/* ADC target, sorted by trigger name: */
-
-/*!< External triggers of injected group for ADC1&ADC2 only */
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/*!< External triggers of injected group for ADC3 only */
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_EXTERNALTRIGINJEC_T4_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_EXTERNALTRIGINJEC_T8_CC2
-#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ADC3_EXTERNALTRIGINJEC_T5_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ADC3_EXTERNALTRIGINJEC_T5_CC4
-#endif /* STM32F103xE || defined STM32F103xG */
-
-/*!< External triggers of injected group for all ADC instances */
-#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO
-
-#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/*!< Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
-/* XL-density devices. */
-/* To use it on ADC1 or ADC2, a remap of trigger must be done from */
-/* EXTI line 11 to TIM8_CC4 with macro: */
-/* __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() */
-/* __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() */
-
-/* Note for internal constant value management: If TIM8_CC4 is available, */
-/* its definition is set to value for ADC1&ADC2 by default and changed to */
-/* value for ADC3 by HAL ADC driver if ADC3 is selected. */
-#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
-#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#define ADC_INJECTED_SOFTWARE_START ADC1_2_3_JSWSTART
-/**
- * @}
- */
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
- * @{
- */
-#define ADC_MODE_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
-#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined regular simultaneous + injected simultaneous mode, on groups regular and injected */
-#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)( ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Combined regular simultaneous + alternate trigger mode, on groups regular and injected */
-#define ADC_DUALMODE_INJECSIMULT_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Combined injected simultaneous + fast interleaved mode, on groups regular and injected (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_INJECSIMULT_INTERLSLOW ((uint32_t)( ADC_CR1_DUALMOD_2 )) /*!< ADC dual mode enabled: Combined injected simultaneous + slow Interleaved mode, on groups regular and injected (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_INJECSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Injected simultaneous mode, on group injected */
-#define ADC_DUALMODE_REGSIMULT ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 )) /*!< ADC dual mode enabled: Regular simultaneous mode, on group regular */
-#define ADC_DUALMODE_INTERLFAST ((uint32_t)( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Fast interleaved mode, on group regular (delay between ADC sampling phases: 7 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_INTERLSLOW ((uint32_t)(ADC_CR1_DUALMOD_3 )) /*!< ADC dual mode enabled: Slow interleaved mode, on group regular (delay between ADC sampling phases: 14 ADC clock cycles (equivalent to parameter "TwoSamplingDelay" set to "ADC_TWOSAMPLINGDELAY_7CYCLES" on other STM32 devices)) */
-#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0)) /*!< ADC dual mode enabled: Alternate trigger mode, on group injected */
-/**
- * @}
- */
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
- * @{
- */
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
- * @{
- */
-/* List of external triggers of regular group for ADC1, ADC2, ADC3 (if ADC */
-/* instance is available on the selected device). */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-
-/* External triggers of regular group for ADC1&ADC2 (if ADCx available) */
-#define ADC1_2_EXTERNALTRIG_T1_CC1 0x00000000U
-#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)( ADC_CR2_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 ))
-#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
-#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
-#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
-/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
-/* XL-density devices. */
-#define ADC1_2_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_EXT_IT11
-#endif
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/* External triggers of regular group for ADC3 */
-#define ADC3_EXTERNALTRIG_T3_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
-#define ADC3_EXTERNALTRIG_T2_CC3 ADC1_2_EXTERNALTRIG_T1_CC2
-#define ADC3_EXTERNALTRIG_T8_CC1 ADC1_2_EXTERNALTRIG_T2_CC2
-#define ADC3_EXTERNALTRIG_T8_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
-#define ADC3_EXTERNALTRIG_T5_CC1 ADC1_2_EXTERNALTRIG_T4_CC4
-#define ADC3_EXTERNALTRIG_T5_CC3 ADC1_2_EXTERNALTRIG_EXT_IT11
-#endif
-
-/* External triggers of regular group for ADC1&ADC2&ADC3 (if ADCx available) */
-#define ADC1_2_3_EXTERNALTRIG_T1_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
-#define ADC1_2_3_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-/**
- * @}
- */
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
- * @{
- */
-/* List of external triggers of injected group for ADC1, ADC2, ADC3 (if ADC */
-/* instance is available on the selected device). */
-/* (used internally by HAL driver. To not use into HAL structure parameters) */
-
-/* External triggers of injected group for ADC1&ADC2 (if ADCx available) */
-#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
-#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 ))
-#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
-#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 ))
-#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG)
-/* Note: TIM8_CC4 is available on ADC1 and ADC2 only in high-density and */
-/* XL-density devices. */
-#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-#endif
-
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/* External triggers of injected group for ADC3 */
-#define ADC3_EXTERNALTRIGINJEC_T4_CC3 ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC3_EXTERNALTRIGINJEC_T8_CC2 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
-#define ADC3_EXTERNALTRIGINJEC_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
-#define ADC3_EXTERNALTRIGINJEC_T5_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC3_EXTERNALTRIGINJEC_T5_CC4 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
-#endif /* STM32F103xE || defined STM32F103xG */
-
-/* External triggers of injected group for ADC1&ADC2&ADC3 (if ADCx available) */
-#define ADC1_2_3_EXTERNALTRIGINJEC_T1_TRGO 0x00000000U
-#define ADC1_2_3_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)( ADC_CR2_JEXTSEL_0))
-#define ADC1_2_3_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
- * @{
- */
-/* Macro reserved for internal HAL driver usage, not intended to be used in */
-/* code of final user. */
-
-
-/**
- * @brief For devices with 3 ADCs: Defines the external trigger source
- * for regular group according to ADC into common group ADC1&ADC2 or
- * ADC3 (some triggers with same source have different value to
- * be programmed into ADC EXTSEL bits of CR2 register).
- * For devices with 2 ADCs or less: this macro makes no change.
- * @param __HANDLE__: ADC handle
- * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
- * @retval External trigger to be programmed into EXTSEL bits of CR2 register
- */
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
- (( (((__HANDLE__)->Instance) == ADC3) \
- )? \
- ( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
- )? \
- (ADC3_EXTERNALTRIG_T8_TRGO) \
- : \
- (__EXT_TRIG_CONV__) \
- ) \
- : \
- (__EXT_TRIG_CONV__) \
- )
-#else
-#define ADC_CFGR_EXTSEL(__HANDLE__, __EXT_TRIG_CONV__) \
- (__EXT_TRIG_CONV__)
-#endif /* STM32F103xE || STM32F103xG */
-
-/**
- * @brief For devices with 3 ADCs: Defines the external trigger source
- * for injected group according to ADC into common group ADC1&ADC2 or
- * ADC3 (some triggers with same source have different value to
- * be programmed into ADC JEXTSEL bits of CR2 register).
- * For devices with 2 ADCs or less: this macro makes no change.
- * @param __HANDLE__: ADC handle
- * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group.
- * @retval External trigger to be programmed into JEXTSEL bits of CR2 register
- */
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
- (( (((__HANDLE__)->Instance) == ADC3) \
- )? \
- ( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
- )? \
- (ADC3_EXTERNALTRIGINJEC_T8_CC4) \
- : \
- (__EXT_TRIG_INJECTCONV__) \
- ) \
- : \
- (__EXT_TRIG_INJECTCONV__) \
- )
-#else
-#define ADC_CFGR_JEXTSEL(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
- (__EXT_TRIG_INJECTCONV__)
-#endif /* STM32F103xE || STM32F103xG */
-
-
-/**
- * @brief Verification if multimode is enabled for the selected ADC (multimode ADC master or ADC slave) (applicable for devices with several ADCs)
- * @param __HANDLE__: ADC handle
- * @retval Multimode state: RESET if multimode is disabled, other value if multimode is enabled
- */
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
- (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
- )? \
- (ADC1->CR1 & ADC_CR1_DUALMOD) \
- : \
- (RESET) \
- )
-#else
-#define ADC_MULTIMODE_IS_ENABLE(__HANDLE__) \
- (RESET)
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
- * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
- (( (((__HANDLE__)->Instance) == ADC2) \
- )? \
- ((ADC1->CR1 & ADC_CR1_DUALMOD) == RESET) \
- : \
- (!RESET) \
- )
-#else
-#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
- (!RESET)
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
- * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
- * @param __HANDLE__: ADC handle
- * @retval None
- */
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
- (( (((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2) \
- )? \
- (ADC1->CR1 & ADC_CR1_JAUTO) \
- : \
- (RESET) \
- )
-#else
-#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
- (RESET)
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/**
- * @brief Set handle of the other ADC sharing the common multimode settings
- * @param __HANDLE__: ADC handle
- * @param __HANDLE_OTHER_ADC__: other ADC handle
- * @retval None
- */
-#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
- ((__HANDLE_OTHER_ADC__)->Instance = ADC2)
-
-/**
- * @brief Set handle of the ADC slave associated to the ADC master
- * On STM32F1 devices, ADC slave is always ADC2 (this can be different
- * on other STM32 devices)
- * @param __HANDLE_MASTER__: ADC master handle
- * @param __HANDLE_SLAVE__: ADC slave handle
- * @retval None
- */
-#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
- ((__HANDLE_SLAVE__)->Instance = ADC2)
-
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
- ((CHANNEL) == ADC_INJECTED_RANK_2) || \
- ((CHANNEL) == ADC_INJECTED_RANK_3) || \
- ((CHANNEL) == ADC_INJECTED_RANK_4))
-
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
- ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING))
-
-/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
- * @{
- */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_SOFTWARE_START))
-#endif
-#if defined (STM32F101xE)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_SOFTWARE_START))
-#endif
-#if defined (STM32F101xG)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_SOFTWARE_START))
-#endif
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
- ((REGTRIG) == ADC_SOFTWARE_START))
-#endif
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101x6) || defined (STM32F101xB) || defined (STM32F102x6) || defined (STM32F102xB) || defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-#endif
-#if defined (STM32F101xE)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-#endif
-#if defined (STM32F101xG)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-#endif
-#if defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
- ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
- ((REGTRIG) == ADC_INJECTED_SOFTWARE_START))
-#endif
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLFAST) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT_INTERLSLOW) || \
- ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
- ((MODE) == ADC_DUALMODE_REGSIMULT) || \
- ((MODE) == ADC_DUALMODE_INTERLFAST) || \
- ((MODE) == ADC_DUALMODE_INTERLSLOW) || \
- ((MODE) == ADC_DUALMODE_ALTERTRIG) )
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/**
- * @}
- */
-
-
-
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
- * @{
- */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group1
- * @{
- */
-
-/* ADC calibration */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc);
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-/* ADC multimode */
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-/**
- * @}
- */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
-HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_adc_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_can.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,796 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_can.h
- * @author MCD Application Team
- * @brief Header file of CAN HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CAN_H
-#define __STM32F1xx_HAL_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
- defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
- HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
- HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
-
-}HAL_CAN_StateTypeDef;
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
-
- uint32_t Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE */
-
- uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_Identifier_Type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
-}CanTxMsgTypeDef;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
-
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_Identifier_Type */
-
- uint32_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
-
- uint32_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
- uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
-
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
- This parameter can be CAN_FIFO0 or CAN_FIFO1 */
-
-}CanRxMsgTypeDef;
-
-/**
- * @brief CAN handle Structure definition
- */
-typedef struct
-{
- CAN_TypeDef *Instance; /*!< Register base address */
-
- CAN_InitTypeDef Init; /*!< CAN required parameters */
-
- CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
-
- CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
-
- CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
-
- __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
-
- HAL_LockTypeDef Lock; /*!< CAN locking object */
-
- __IO uint32_t ErrorCode; /*!< CAN Error code */
-
-}CAN_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
- * @{
- */
-
-/** @defgroup CAN_Error_Code CAN Error Code
- * @{
- */
-#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
-#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
-#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
-#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
-#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
-#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
-#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
-#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
-/**
- * @}
- */
-
-/** @defgroup CAN_InitStatus CAN initialization Status
- * @{
- */
-#define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
- * @{
- */
-#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
-#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
-#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
-#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
- * @{
- */
-#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
-#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
-#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
-#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
- * @{
- */
-#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
-#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
-#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
-#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
-#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
-#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
-#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
-#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
-#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
-#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
-#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
-#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
-#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
-#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
-#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
-#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
- * @{
- */
-#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
-#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
-#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
-#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
-#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
-#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
-#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
-#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode CAN Filter Mode
- * @{
- */
-#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
- * @{
- */
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
- * @{
- */
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-/**
- * @}
- */
-
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
- * @{
- */
-#define CAN_ID_STD 0x00000000U /*!< Standard Id */
-#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
- * @{
- */
-#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
-#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants CAN Transmit Constants
- * @{
- */
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags CAN Flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */
-#define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */
-#define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */
-#define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */
-
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */
-#define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */
-#define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Interrupts CAN Interrupts
- * @{
- */
-#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
-#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
-#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
-#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
-#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
-#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
-#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
-#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup CAN_Private_Constants CAN Private Constants
- * @{
- */
-
-/* CAN intermediate shift values used for CAN flags */
-#define TSR_REGISTER_INDEX 0x5U
-#define RF0R_REGISTER_INDEX 0x2U
-#define RF1R_REGISTER_INDEX 0x4U
-#define MSR_REGISTER_INDEX 0x1U
-#define ESR_REGISTER_INDEX 0x3U
-
-/* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */
-/* Transmit Flags */
-#define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U
-#define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U
-#define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U
-#define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U
-#define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U
-#define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U
-#define CAN_TSR_TME0_BIT_POSITION 0x0000001AU
-#define CAN_TSR_TME1_BIT_POSITION 0x0000001BU
-#define CAN_TSR_TME2_BIT_POSITION 0x0000001CU
-
-/* Receive Flags */
-#define CAN_RF0R_FF0_BIT_POSITION 0x00000003U
-#define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U
-
-#define CAN_RF1R_FF1_BIT_POSITION 0x00000003U
-#define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U
-
-/* Operating Mode Flags */
-#define CAN_MSR_WKU_BIT_POSITION 0x00000003U
-#define CAN_MSR_SLAK_BIT_POSITION 0x00000001U
-#define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U
-
-/* Error Flags */
-#define CAN_ESR_EWG_BIT_POSITION 0x00000000U
-#define CAN_ESR_EPV_BIT_POSITION 0x00000001U
-#define CAN_ESR_BOF_BIT_POSITION 0x00000002U
-
-/* Mask used by macro to get/clear CAN flags*/
-#define CAN_FLAG_MASK 0x000000FFU
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macros CAN Exported Macros
- * @{
- */
-
-/** @brief Reset CAN handle state
- * @param __HANDLE__: CAN handle.
- * @retval None
- */
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-
-/**
- * @brief Enable the specified CAN interrupts
- * @param __HANDLE__: CAN handle.
- * @param __INTERRUPT__: CAN Interrupt.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
- * @arg CAN_IT_FF0 : FIFO 0 full interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
- * @arg CAN_IT_FF1 : FIFO 1 full interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
- * @arg CAN_IT_WKU : Wake-up interrupt
- * @arg CAN_IT_SLK : Sleep acknowledge interrupt
- * @arg CAN_IT_EWG : Error warning interrupt
- * @arg CAN_IT_EPV : Error passive interrupt
- * @arg CAN_IT_BOF : Bus-off interrupt
- * @arg CAN_IT_LEC : Last error code interrupt
- * @arg CAN_IT_ERR : Error Interrupt
- * @retval None.
- */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified CAN interrupts
- * @param __HANDLE__: CAN handle.
- * @param __INTERRUPT__: CAN Interrupt.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
- * @arg CAN_IT_FF0 : FIFO 0 full interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
- * @arg CAN_IT_FF1 : FIFO 1 full interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
- * @arg CAN_IT_WKU : Wake-up interrupt
- * @arg CAN_IT_SLK : Sleep acknowledge interrupt
- * @arg CAN_IT_EWG : Error warning interrupt
- * @arg CAN_IT_EPV : Error passive interrupt
- * @arg CAN_IT_BOF : Bus-off interrupt
- * @arg CAN_IT_LEC : Last error code interrupt
- * @arg CAN_IT_ERR : Error Interrupt
- * @retval None.
- */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/**
- * @brief Return the number of pending received messages.
- * @param __HANDLE__: CAN handle.
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval The number of pending message.
- */
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
-
-/** @brief Check whether the specified CAN flag is set or not.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag // MBED patch
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief Clear the specified CAN pending flag.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag // MBED patch
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
-
-/** @brief Check if the specified CAN interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __INTERRUPT__: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt
- * @arg CAN_IT_FF0 : FIFO 0 full interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt
- * @arg CAN_IT_FF1 : FIFO 1 full interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt
- * @arg CAN_IT_WKU : Wake-up interrupt
- * @arg CAN_IT_SLK : Sleep acknowledge interrupt
- * @arg CAN_IT_EWG : Error warning interrupt
- * @arg CAN_IT_EPV : Error passive interrupt
- * @arg CAN_IT_BOF : Bus-off interrupt
- * @arg CAN_IT_LEC : Last error code interrupt
- * @arg CAN_IT_ERR : Error Interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Check the transmission status of a CAN Frame.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval The new status of transmission (TRUE or FALSE).
- */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
-
-/**
- * @brief Release the specified receive FIFO.
- * @param __HANDLE__: CAN handle.
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval None.
- */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
-
-/**
- * @brief Cancel a transmit request.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval None.
- */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
-
-/**
- * @brief Enable or disables the DBG Freeze for CAN.
- * @param __HANDLE__: specifies the CAN Handle.
- * @param __NEWSTATE__: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
- * @}
- */
-
-/* Include CAN HAL Extension module */
-#include "stm32f1xx_hal_can_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
- * @{
- */
-
-/** @addtogroup CAN_Exported_Functions_Group1
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group2
- * @brief I/O operation functions
- * @{
- */
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group3
- * @brief CAN Peripheral State functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
- * @{
- */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
- ((MODE) == CAN_MODE_LOOPBACK)|| \
- ((MODE) == CAN_MODE_SILENT) || \
- ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
- ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
- ((MODE) == CAN_FILTERMODE_IDLIST))
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
- ((SCALE) == CAN_FILTERSCALE_32BIT))
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
- ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU)
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
- ((IDTYPE) == CAN_ID_EXT))
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CAN_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_can.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_can_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,144 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_can_ex.h
- * @author MCD Application Team
- * @brief Header file of CAN HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CAN_EX_H
-#define __STM32F1xx_HAL_CAN_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
- defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup CANEx CANEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief CAN filter configuration structure definition
- */
-/* CAN filter banks differences over STM32F1 devices: */
-/* - STM32F1 Connectivity line: 28 filter banks shared between CAN1 and CAN2 */
-/* - Other STM32F10x devices: 14 filter banks */
-
-typedef struct
-{
- uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-#else
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between Min_Data = 0 and Max_Data = 13. */
-#endif /* STM32F105xC || STM32F107xC */
- uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint32_t FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- uint32_t FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t BankNumber; /*!< Select the start slave bank filter
- This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
-
-}CAN_FilterConfTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup CANEx_Private_Macros CAN Extended Private Macros
- * @{
- */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
-#else
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13U)
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CAN_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_cec.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,516 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_cec.h
- * @author MCD Application Team
- * @brief Header file of CEC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CEC_H
-#define __STM32F1xx_HAL_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CEC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CEC_Exported_Types CEC Exported Types
- * @{
- */
-/**
- * @brief CEC Init Structure definition
- */
-typedef struct
-{
- uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode.
- This parameter can be a value of @ref CEC_BitTimingErrorMode */
- uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode.
- This parameter can be a value of @ref CEC_BitPeriodErrorMode */
- uint16_t OwnAddress; /*!< Own addresses configuration
- This parameter can be a value of @ref CEC_OWN_ADDRESS */
- uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
-}CEC_InitTypeDef;
-
-/**
- * @brief HAL CEC State structures definition
- * @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
- * - gState contains CEC state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7 (not used)
- * x : Should be set to 0
- * b6 Error information
- * 0 : No Error
- * 1 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized. HAL CEC Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
-}HAL_CEC_StateTypeDef;
-
-/**
- * @brief CEC handle Structure definition
- */
-typedef struct
-{
- CEC_TypeDef *Instance; /*!< CEC registers base address */
-
- CEC_InitTypeDef Init; /*!< CEC communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
-
- uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
-
- uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
- HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
- This parameter can be a value of @ref HAL_CEC_StateTypeDef */
-
- uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
- in case error is reported */
-}CEC_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CEC_Exported_Constants CEC Exported Constants
- * @{
- */
-
-/** @defgroup CEC_Error_Code CEC Error Code
- * @{
- */
-#define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */
-#define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */
-#define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */
-#define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */
-#define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */
-#define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */
-#define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */
-#define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */
-/**
- * @}
- */
-
-/** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode
- * @{
- */
-#define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */
-#define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */
-/**
- * @}
- */
-
-/** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode
- * @{
- */
-#define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */
-#define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */
-/**
- * @}
- */
-
-/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
- * @{
- */
-#define CEC_INITIATOR_LSB_POS 4U
-/**
- * @}
- */
-
-/** @defgroup CEC_OWN_ADDRESS CEC Own Address
- * @{
- */
-#define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */
-#define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */
-#define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */
-#define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */
-#define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */
-#define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */
-#define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */
-#define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */
-#define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */
-#define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */
-#define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */
-#define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */
-#define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */
-#define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */
-#define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */
-#define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */
-#define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */
-/**
- * @}
- */
-
-/** @defgroup CEC_Interrupts_Definitions Interrupts definition
- * @{
- */
-#define CEC_IT_IE CEC_CFGR_IE
-/**
- * @}
- */
-
-/** @defgroup CEC_Flags_Definitions Flags definition
- * @{
- */
-#define CEC_FLAG_TSOM CEC_CSR_TSOM
-#define CEC_FLAG_TEOM CEC_CSR_TEOM
-#define CEC_FLAG_TERR CEC_CSR_TERR
-#define CEC_FLAG_TBTRF CEC_CSR_TBTRF
-#define CEC_FLAG_RSOM CEC_CSR_RSOM
-#define CEC_FLAG_REOM CEC_CSR_REOM
-#define CEC_FLAG_RERR CEC_CSR_RERR
-#define CEC_FLAG_RBTF CEC_CSR_RBTF
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CEC_Exported_Macros CEC Exported Macros
- * @{
- */
-
-/** @brief Reset CEC handle gstate & RxState
- * @param __HANDLE__: CEC handle.
- * @retval None
- */
-#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
- } while(0U)
-
-/** @brief Checks whether or not the specified CEC interrupt flag is set.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the flag to check.
- * @arg CEC_FLAG_TERR: Tx Error
- * @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished
- * @arg CEC_FLAG_RERR: Rx Error
- * @arg CEC_FLAG_RBTF: Rx Block Transfer Finished
- * @retval ITStatus
- */
-#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__))
-
-/** @brief Clears the CEC's pending flags.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_CSR_TERR: Tx Error
- * @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished
- * @arg CEC_CSR_RERR: Rx Error
- * @arg CEC_CSR_RBTF: Rx Block Transfer Finished
- * @retval none
- */
-#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
- do { \
- uint32_t tmp = 0x0U; \
- tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \
- (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\
- } while(0U)
-
-/** @brief Enables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to enable.
- * This parameter can be:
- * @arg CEC_IT_IE : Interrupt Enable.
- * @retval none
- */
-#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
-
-/** @brief Disables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to disable.
- * This parameter can be:
- * @arg CEC_IT_IE : Interrupt Enable
- * @retval none
- */
-#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
-
-/** @brief Checks whether or not the specified CEC interrupt is enabled.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to check.
- * This parameter can be:
- * @arg CEC_IT_IE : Interrupt Enable
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__))
-
-/** @brief Enables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
-
-/** @brief Disables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE)
-
-/** @brief Set Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
-
-/** @brief Set Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
-
-/** @brief Get Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM)
-
-/** @brief Get Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval FlagStatus
- */
-#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM)
-
-/** @brief Clear OAR register
- * @param __HANDLE__: specifies the CEC Handle.
- * @retval none
- */
-#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA)
-
-/** @brief Set OAR register
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __ADDRESS__: Own Address value.
- * @retval none
- */
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__));
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CEC_Exported_Functions CEC Exported Functions
- * @{
- */
-
-/** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- * @{
- */
-/* Initialization and de-initialization functions ****************************/
-HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
-HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
-void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
-void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions
- * @brief CEC Transmit/Receive functions
- * @{
- */
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
-void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
-void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
-void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
-void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
-void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions
- * @brief CEC control functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CEC_Private_Types CEC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Variables CEC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Constants CEC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CEC_Private_Macros CEC Private Macros
- * @{
- */
-#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \
- ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE))
-
-#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \
- ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE))
-
-/** @brief Check CEC message size.
- * The message size is the payload size: without counting the header,
- * it varies from 0 byte (ping operation, one header only, no payload) to
- * 15 bytes (1 opcode and up to 14 operands following the header).
- * @param __SIZE__: CEC message size.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
-/** @brief Check CEC device Own Address Register (OAR) setting.
- * @param __ADDRESS__: CEC own address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
-
-/** @brief Check CEC initiator or destination logical address setting.
- * Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__: CEC initiator or logical address.
- * @retval Test result (TRUE or FALSE).
- */
-#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU)
-
-
-
-/**
- * @}
- */
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CEC_Private_Functions CEC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CEC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_cec.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_conf.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,383 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_conf.h
- * @author MCD Application Team
- * @brief HAL configuration template file.
- * This file should be copied to the application folder and renamed
- * to stm32f1xx_hal_conf.h.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CONF_H
-#define __STM32F1xx_HAL_CONF_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
- * @brief This is the list of modules to be used in the HAL driver
- */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_CAN_MODULE_ENABLED
-#define HAL_CEC_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_HCD_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_NAND_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_PCCARD_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-#define HAL_MMC_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
- * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSE_VALUE)
-#if defined(USE_STM3210C_EVAL)
-#define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */
-#else
-#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
-#endif
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief Internal High Speed oscillator (HSI) value.
- * This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
- */
-#if !defined (HSI_VALUE)
-#define HSI_VALUE 8000000U /*!< Value of the Internal oscillator in Hz */
-#endif /* HSI_VALUE */
-
-/**
- * @brief Internal Low Speed oscillator (LSI) value.
- */
-#if !defined (LSI_VALUE)
-#define LSI_VALUE 32000U /*!< LSI Typical Value in Hz */
-#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
-/**
- * @brief External Low Speed oscillator (LSE) value.
- * This value is used by the UART, RTC HAL module to compute the system frequency
- */
-#if !defined (LSE_VALUE)
-#define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined (LSE_STARTUP_TIMEOUT)
-#define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
- === you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
- * @brief This is the HAL system configuration section
- */
-#define VDD_VALUE 3300U /*!< Value of VDD in mv */
-#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
-#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
-
-/* ########################## Assert Selection ############################## */
-/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
- * HAL drivers code
- */
-/* #define USE_FULL_ASSERT 1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0 2U
-#define MAC_ADDR1 0U
-#define MAC_ADDR2 0U
-#define MAC_ADDR3 0U
-#define MAC_ADDR4 0U
-#define MAC_ADDR5 0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
-#define ETH_RXBUFNB 8U /* 8 Rx buffers of size ETH_RX_BUF_SIZE */
-#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848 PHY Address*/
-#define DP83848_PHY_ADDRESS 0x01U
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY 0x00000FFFU
-
-#define PHY_READ_TO 0x0000FFFFU
-#define PHY_WRITE_TO 0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
-#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
-
-#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
-#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
-#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
-#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
-#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
-#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
-#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
-
-#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
-#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
-#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
-
-/* Section 4: Extended PHY Registers */
-
-#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
-#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
-#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
-
-#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
-#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
-#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
-
-#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
-#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
-
-#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
-#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC 1U
-
-/* Includes ------------------------------------------------------------------*/
-/**
- * @brief Include module's header file
- */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-#include "stm32f1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-#include "stm32f1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-#include "stm32f1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-#include "stm32f1xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-#include "stm32f1xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
-#include "stm32f1xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-#include "stm32f1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-#include "stm32f1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-#include "stm32f1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-#include "stm32f1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-#include "stm32f1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-#include "stm32f1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-#include "stm32f1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-#include "stm32f1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-#include "stm32f1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-#include "stm32f1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-#include "stm32f1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-#include "stm32f1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-#include "stm32f1xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
-#include "stm32f1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-#include "stm32f1xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
-#include "stm32f1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-#include "stm32f1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
-#include "stm32f1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
-#include "stm32f1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-#include "stm32f1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-#include "stm32f1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-#include "stm32f1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-#include "stm32f1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
-#include "stm32f1xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
-#include "stm32f1xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-// MBED patch: all targets use the same assert file
-#include "stm32_assert.h"
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
-//#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-//void assert_failed(uint8_t *file, uint32_t line);
-#else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_cortex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,426 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CORTEX_H
-#define __STM32F1xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CORTEX
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
- * @{
- */
-
-#if (__MPU_PRESENT == 1U)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
- * @brief MPU Region initialization structure
- * @{
- */
-typedef struct
-{
- uint8_t Enable; /*!< Specifies the status of the region.
- This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
- uint8_t Number; /*!< Specifies the number of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Number */
- uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
- uint8_t Size; /*!< Specifies the size of the region to protect.
- This parameter can be a value of @ref CORTEX_MPU_Region_Size */
- uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint8_t TypeExtField; /*!< Specifies the TEX field level.
- This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
- uint8_t AccessPermission; /*!< Specifies the region access permission type.
- This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
- uint8_t DisableExec; /*!< Specifies the instruction access status.
- This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
- uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
- uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
- This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
- uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
- This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
-}MPU_Region_InitTypeDef;
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
- * @{
- */
-#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority
- 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority
- 0 bits for subpriority */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
- * @{
- */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
-
-/**
- * @}
- */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
- * @{
- */
-#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
-#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
-#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
-#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
- * @{
- */
-#define MPU_REGION_ENABLE ((uint8_t)0x01)
-#define MPU_REGION_DISABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
- * @{
- */
-#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
-#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
- * @{
- */
-#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
- * @{
- */
-#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
- * @{
- */
-#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
-#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
- * @{
- */
-#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
-#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
-#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
- * @{
- */
-#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
-#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
-#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
-#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
-#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
-#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
-#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
-#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
-#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
-#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
-#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
-#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
-#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
-#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
-#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
-#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
-#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
-#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
-#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
-#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
-#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
-#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
-#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
-#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
-#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
-#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
-#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
-#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
- * @{
- */
-#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
-#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
-#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
-#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
-#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
-#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
-/**
- * @}
- */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
- * @{
- */
-#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
-#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
-#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
-#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
-#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
-#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
-#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
-#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-
-/* Exported Macros -----------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
- * @{
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
- * @}
- */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
- * @{
- */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
- ((GROUP) == NVIC_PRIORITYGROUP_1) || \
- ((GROUP) == NVIC_PRIORITYGROUP_2) || \
- ((GROUP) == NVIC_PRIORITYGROUP_3) || \
- ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
- ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1U)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
- ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
- ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
- ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
- ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
- ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
- ((TYPE) == MPU_TEX_LEVEL1) || \
- ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RW) || \
- ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
- ((TYPE) == MPU_REGION_FULL_ACCESS) || \
- ((TYPE) == MPU_REGION_PRIV_RO) || \
- ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
- ((NUMBER) == MPU_REGION_NUMBER1) || \
- ((NUMBER) == MPU_REGION_NUMBER2) || \
- ((NUMBER) == MPU_REGION_NUMBER3) || \
- ((NUMBER) == MPU_REGION_NUMBER4) || \
- ((NUMBER) == MPU_REGION_NUMBER5) || \
- ((NUMBER) == MPU_REGION_NUMBER6) || \
- ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
- ((SIZE) == MPU_REGION_SIZE_64B) || \
- ((SIZE) == MPU_REGION_SIZE_128B) || \
- ((SIZE) == MPU_REGION_SIZE_256B) || \
- ((SIZE) == MPU_REGION_SIZE_512B) || \
- ((SIZE) == MPU_REGION_SIZE_1KB) || \
- ((SIZE) == MPU_REGION_SIZE_2KB) || \
- ((SIZE) == MPU_REGION_SIZE_4KB) || \
- ((SIZE) == MPU_REGION_SIZE_8KB) || \
- ((SIZE) == MPU_REGION_SIZE_16KB) || \
- ((SIZE) == MPU_REGION_SIZE_32KB) || \
- ((SIZE) == MPU_REGION_SIZE_64KB) || \
- ((SIZE) == MPU_REGION_SIZE_128KB) || \
- ((SIZE) == MPU_REGION_SIZE_256KB) || \
- ((SIZE) == MPU_REGION_SIZE_512KB) || \
- ((SIZE) == MPU_REGION_SIZE_1MB) || \
- ((SIZE) == MPU_REGION_SIZE_2MB) || \
- ((SIZE) == MPU_REGION_SIZE_4MB) || \
- ((SIZE) == MPU_REGION_SIZE_8MB) || \
- ((SIZE) == MPU_REGION_SIZE_16MB) || \
- ((SIZE) == MPU_REGION_SIZE_32MB) || \
- ((SIZE) == MPU_REGION_SIZE_64MB) || \
- ((SIZE) == MPU_REGION_SIZE_128MB) || \
- ((SIZE) == MPU_REGION_SIZE_256MB) || \
- ((SIZE) == MPU_REGION_SIZE_512MB) || \
- ((SIZE) == MPU_REGION_SIZE_1GB) || \
- ((SIZE) == MPU_REGION_SIZE_2GB) || \
- ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_cortex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_crc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,193 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_crc.h
- * @author MCD Application Team
- * @brief Header file of CRC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_CRC_H
-#define __STM32F1xx_HAL_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Types CRC Exported Types
- * @{
- */
-
-/**
- * @brief CRC HAL State Structure definition
- */
-typedef enum
-{
- HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
- HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
- HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
- HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
- HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
-
-}HAL_CRC_StateTypeDef;
-
-/**
- * @brief CRC handle Structure definition
- */
-typedef struct
-{
- CRC_TypeDef *Instance; /*!< Register base address */
-
- HAL_LockTypeDef Lock; /*!< CRC locking object */
-
- __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
-
-}CRC_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
- * @{
- */
-
-/** @brief Reset CRC handle state
- * @param __HANDLE__: CRC handle
- * @retval None
- */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
- * @brief Resets CRC Data Register.
- * @param __HANDLE__: CRC handle
- * @retval None
- */
-#define __HAL_CRC_DR_RESET(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
-
-/**
- * @brief Stores a 8-bit data in the Independent Data(ID) register.
- * @param __HANDLE__: CRC handle
- * @param __VALUE__: 8-bit value to be stored in the ID register
- * @retval None
- */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
- * @param __HANDLE__: CRC handle
- * @retval 8-bit value of the ID register
- */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRC_Exported_Functions
- * @{
- */
-
-/** @addtogroup CRC_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-
-/**
- * @}
- */
-
-/** @addtogroup CRC_Exported_Functions_Group2
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-
-
-/**
- * @}
- */
-
-/** @addtogroup CRC_Exported_Functions_Group3
- ** @{
- */
-
-/* Peripheral State functions **************************************************/
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_crc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dac.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,322 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DAC_H
-#define __STM32F1xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
- HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
- HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
- HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
- HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
-
-}HAL_DAC_StateTypeDef;
-
-/**
- * @brief DAC handle Structure definition
- */
-typedef struct
-{
- DAC_TypeDef *Instance; /*!< Register base address */
-
- __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
-
- HAL_LockTypeDef Lock; /*!< DAC locking object */
-
- DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
-
- DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
-
- __IO uint32_t ErrorCode; /*!< DAC Error code */
-
-}DAC_HandleTypeDef;
-
-/**
- * @brief DAC Configuration regular Channel structure definition
- */
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DACEx_trigger_selection
- Note: For STM32F100x high-density value line devices, additional trigger sources are available. */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-
-}DAC_ChannelConfTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_Error_Code DAC Error Code
- * @{
- */
-#define HAL_DAC_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x00000001U /*!< DAC channel1 DMA underrun error */
-#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x00000002U /*!< DAC channel2 DMA underrun error */
-#define HAL_DAC_ERROR_DMA 0x00000004U /*!< DMA error */
-/**
- * @}
- */
-
-/** @defgroup DAC_output_buffer DAC output buffer
- * @{
- */
-#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
- * @{
- */
-#define DAC_CHANNEL_1 0x00000000U
-#define DAC_CHANNEL_2 0x00000010U
-
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignement DAC data alignement
- * @{
- */
-#define DAC_ALIGN_12B_R 0x00000000U
-#define DAC_ALIGN_12B_L 0x00000004U
-#define DAC_ALIGN_8B_R 0x00000008U
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @brief Reset DAC handle state
- * @param __HANDLE__: specifies the DAC handle.
- * @retval None
- */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel
- * @param __HANDLE__: specifies the DAC handle.
- * @param __DAC_Channel__: specifies the DAC channel
- * @retval None
- */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Disable the DAC channel
- * @param __HANDLE__: specifies the DAC handle
- * @param __DAC_Channel__: specifies the DAC channel.
- * @retval None
- */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
-
-
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
- * @{
- */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
- ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
- ((CHANNEL) == DAC_CHANNEL_2))
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
- ((ALIGN) == DAC_ALIGN_12B_L) || \
- ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
-
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
-
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
-
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
-
-/**
- * @}
- */
-
-
-/* Include DAC HAL Extension module */
-#include "stm32f1xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
- * @{
- */
-
-/** @addtogroup DAC_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions *************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup DAC_Private_Functions DAC Private Functions
- * @{
- */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /*__STM32F1xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dac.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dac_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,370 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_dac_ex.h
- * @author MCD Application Team
- * @brief Header file of DAC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DAC_EX_H
-#define __STM32F1xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DACEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
- * @{
- */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
- * @{
- */
-#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-/**
- * @}
- */
-
-/** @defgroup DACEx_trigger_selection DAC trigger selection
- * @{
- */
-#define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
-/* For STM32F10x high-density and XL-density devices: TIM8 */
-#define DAC_TRIGGER_T8_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
-/* For STM32F10x connectivity line devices and STM32F100x devices: TIM3 */
-#define DAC_TRIGGER_T3_TRGO ((uint32_t) DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
-#endif /* STM32F100xB || STM32F100xE || STM32F105xC || STM32F107xC */
-
-/* Availability of trigger from TIM5 and TIM15: */
-/* - For STM32F10x value line devices STM32F100xB: */
-/* trigger from TIM15 is available, TIM5 not available. */
-/* - For STM32F10x value line devices STM32F100xE: */
-/* trigger from TIM15 and TIM5 are both available, */
-/* selection depends on remap (with TIM5 as default configuration). */
-/* - Other STM32F1 devices: */
-/* trigger from TIM5 is available, TIM15 not available. */
-#if defined (STM32F100xB)
-#define DAC_TRIGGER_T15_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
-#else
-
-#define DAC_TRIGGER_T5_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-
-#if defined (STM32F100xE)
-/*!< DAC trigger availability depending on STM32F1 devices:
- For STM32F100x high-density value line devices, the TIM15 TRGO event can be selected
- as replacement of TIM5 TRGO if the MISC_REMAP bit in the AFIO_MAPR2 register is set.
- Refer to macro "__HAL_AFIO_REMAP_MISC_ENABLE()/__HAL_AFIO_REMAP_MISC_DISABLE()".
- Otherwise, TIM5 TRGO is used and TIM15 TRGO is not used (default case).
- For more details please refer to the AFIO section. */
-#define DAC_TRIGGER_T15_TRGO DAC_TRIGGER_T5_TRGO
-#endif /* STM32F100xE */
-
-#endif /* STM32F100xB */
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/** @defgroup DAC_flags_definition DAC flags definition
- * @{
- */
-#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_IT_definition DAC IT definition
- * @{
- */
-#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
-
-/**
- * @}
- */
-#endif /* STM32F100xB || STM32F100xE */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-/** @defgroup DACEx_Exported_Macros DACEx Exported Macros
- * @{
- */
-
-/** @brief Enable the DAC interrupt
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval None
- */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
- * @param __HANDLE__: DAC handle
- * @param __INTERRUPT__: DAC interrupt source to check
- * This parameter can be any combination of the following values:
- * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
- * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
- * @retval State of interruption (SET or RESET)
- */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Get the selected DAC's flag status.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the DAC flag to get.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the DAC's flag.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the DAC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
- * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
- * @retval None
- */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-
-/**
- * @}
- */
-#endif /* STM32F100xB || STM32F100xE */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
- * @{
- */
-#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-#if defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F100xE || STM32F105xC || STM32F107xC */
-#if defined (STM32F100xB)
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
- ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
- ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
- ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif /* STM32F100xB */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
- ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
- ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DACEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup DACEx_Exported_Functions_Group1
- * @{
- */
-/* Extension features functions ***********************************************/
-
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-
-#if defined (STM32F100xB) || defined (STM32F100xE)
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-#endif /* STM32F100xB) || defined (STM32F100xE) */
-
-/**
- * @}
- */
-
-
-
-
-/**
- * @}
- */
-
-/** @addtogroup DACEx_Private_Functions
- * @{
- */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F100xB || STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F1xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dac_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_def.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,214 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_def.h
- * @author MCD Application Team
- * @brief This file contains HAL common defines, enumeration, macros and
- * structures definitions.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DEF
-#define __STM32F1xx_HAL_DEF
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-#if defined(USE_HAL_LEGACY)
-#include "stm32_hal_legacy.h" // MBED patch
-#endif
-#include <stdio.h>
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief HAL Status structures definition
- */
-typedef enum
-{
- HAL_OK = 0x00U,
- HAL_ERROR = 0x01U,
- HAL_BUSY = 0x02U,
- HAL_TIMEOUT = 0x03U
-} HAL_StatusTypeDef;
-
-/**
- * @brief HAL Lock structures definition
- */
-typedef enum
-{
- HAL_UNLOCKED = 0x00U,
- HAL_LOCKED = 0x01U
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-#define HAL_MAX_DELAY 0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
- do{ \
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
- (__DMA_HANDLE__).Parent = (__HANDLE__); \
- } while(0U)
-
-#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
-
-/** @brief Reset the Handle's State field.
- * @param __HANDLE__: specifies the Peripheral Handle.
- * @note This macro can be used for the following purpose:
- * - When the Handle is declared as local variable; before passing it as parameter
- * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
- * to set to 0 the Handle's "State" field.
- * Otherwise, "State" field may have any random value and the first time the function
- * HAL_PPP_Init() is called, the low level hardware initialization will be missed
- * (i.e. HAL_PPP_MspInit() will not be executed).
- * - When there is a need to reconfigure the low level hardware: instead of calling
- * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
- * In this later function, when the Handle's "State" field is set to 0, it will execute the function
- * HAL_PPP_MspInit() which will reconfigure the low level hardware.
- * @retval None
- */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-
-#if (USE_RTOS == 1U)
-/* Reserved for future use */
-#error "USE_RTOS should be 0 in the current HAL release"
-#else
-#define __HAL_LOCK(__HANDLE__) \
- do{ \
- if((__HANDLE__)->Lock == HAL_LOCKED) \
- { \
- return HAL_BUSY; \
- } \
- else \
- { \
- (__HANDLE__)->Lock = HAL_LOCKED; \
- } \
- }while (0U)
-
-#define __HAL_UNLOCK(__HANDLE__) \
- do{ \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0U)
-#endif /* USE_RTOS */
-
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-#ifndef __weak
-#define __weak __attribute__((weak))
-#endif /* __weak */
-#ifndef __packed
-#define __packed __attribute__((__packed__))
-#endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-#ifndef __ALIGN_END
-#define __ALIGN_END __attribute__ ((aligned (4)))
-#endif /* __ALIGN_END */
-#ifndef __ALIGN_BEGIN
-#define __ALIGN_BEGIN
-#endif /* __ALIGN_BEGIN */
-#else
-#ifndef __ALIGN_END
-#define __ALIGN_END
-#endif /* __ALIGN_END */
-#ifndef __ALIGN_BEGIN
-#if defined (__CC_ARM) /* ARM Compiler */
-#define __ALIGN_BEGIN __align(4)
-#elif defined (__ICCARM__) /* IAR Compiler */
-#define __ALIGN_BEGIN
-#endif /* __CC_ARM */
-#endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-
-/**
- * @brief __RAM_FUNC definition
- */
-#if defined ( __CC_ARM )
-/* ARM Compiler
- ------------
- RAM functions are defined using the toolchain options.
- Functions that are executed in RAM should reside in a separate source module.
- Using the 'Options for File' dialog you can simply change the 'Code / Const'
- area of a module to a memory space in physical RAM.
- Available memory areas are declared in the 'Target' tab of the 'Options for Target'
- dialog.
-*/
-#define __RAM_FUNC
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
- RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc
-
-#elif defined ( __GNUC__ )
-/* GNU Compiler
- ------------
- RAM functions are defined using a specific toolchain attribute
- "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC __attribute__((section(".RamFunc")))
-
-#endif
-
-/**
- * @brief __NOINLINE definition
- */
-#if defined ( __CC_ARM ) || defined ( __GNUC__ )
-/* ARM & GNUCompiler
- ----------------
-*/
-#define __NOINLINE __attribute__ ( (noinline) )
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
- ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32F1xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dma.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,473 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DMA_H
-#define __STM32F1xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
- * @{
- */
-
-/**
- * @brief DMA Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_Data_transfer_direction */
-
- uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
- This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
- uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
- This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
- uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_Peripheral_data_size */
-
- uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_Memory_data_size */
-
- uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_mode
- @note The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
- * @brief HAL DMA State structures definition
- */
-typedef enum
-{
- HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
- HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
- HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
- HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
-}HAL_DMA_StateTypeDef;
-
-/**
- * @brief HAL DMA Error Code structure definition
- */
-typedef enum
-{
- HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
- HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/**
- * @brief HAL DMA Callback ID structure definition
- */
-typedef enum
-{
- HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
- HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
- HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
- HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
- HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
-
-}HAL_DMA_CallbackIDTypeDef;
-
-/**
- * @brief DMA handle Structure definition
- */
-typedef struct __DMA_HandleTypeDef
-{
- DMA_Channel_TypeDef *Instance; /*!< Register base address */
-
- DMA_InitTypeDef Init; /*!< DMA communication parameters */
-
- HAL_LockTypeDef Lock; /*!< DMA locking object */
-
- HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
-
- void *Parent; /*!< Parent object state */
-
- void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
-
- void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
-
- void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
-
- void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
-
- __IO uint32_t ErrorCode; /*!< DMA Error code */
-
- DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
-
- uint32_t ChannelIndex; /*!< DMA Channel Index */
-
-} DMA_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
- * @{
- */
-
-/** @defgroup DMA_Error_Code DMA Error Code
- * @{
- */
-#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */
-#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
-#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
- * @{
- */
-#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
- * @{
- */
-#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
- * @{
- */
-#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
-#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
- * @{
- */
-#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
- * @{
- */
-#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_mode DMA mode
- * @{
- */
-#define DMA_NORMAL 0x00000000U /*!< Normal mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_Priority_level DMA Priority level
- * @{
- */
-#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
- * @{
- */
-#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
-#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
-#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
-/**
- * @}
- */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
- * @{
- */
-#define DMA_FLAG_GL1 0x00000001U
-#define DMA_FLAG_TC1 0x00000002U
-#define DMA_FLAG_HT1 0x00000004U
-#define DMA_FLAG_TE1 0x00000008U
-#define DMA_FLAG_GL2 0x00000010U
-#define DMA_FLAG_TC2 0x00000020U
-#define DMA_FLAG_HT2 0x00000040U
-#define DMA_FLAG_TE2 0x00000080U
-#define DMA_FLAG_GL3 0x00000100U
-#define DMA_FLAG_TC3 0x00000200U
-#define DMA_FLAG_HT3 0x00000400U
-#define DMA_FLAG_TE3 0x00000800U
-#define DMA_FLAG_GL4 0x00001000U
-#define DMA_FLAG_TC4 0x00002000U
-#define DMA_FLAG_HT4 0x00004000U
-#define DMA_FLAG_TE4 0x00008000U
-#define DMA_FLAG_GL5 0x00010000U
-#define DMA_FLAG_TC5 0x00020000U
-#define DMA_FLAG_HT5 0x00040000U
-#define DMA_FLAG_TE5 0x00080000U
-#define DMA_FLAG_GL6 0x00100000U
-#define DMA_FLAG_TC6 0x00200000U
-#define DMA_FLAG_HT6 0x00400000U
-#define DMA_FLAG_TE6 0x00800000U
-#define DMA_FLAG_GL7 0x01000000U
-#define DMA_FLAG_TC7 0x02000000U
-#define DMA_FLAG_HT7 0x04000000U
-#define DMA_FLAG_TE7 0x08000000U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @brief Reset DMA handle state.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
- * @brief Enable the specified DMA Channel.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-/**
- * @brief Disable the specified DMA Channel.
- * @param __HANDLE__: DMA handle
- * @retval None
- */
-#define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-
-/* Interrupt & Flag management */
-
-/**
- * @brief Enables the specified DMA Channel interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
-
-/**
- * @brief Disable the specified DMA Channel interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval None
- */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
-
-/**
- * @brief Check whether the specified DMA Channel interrupt is enabled or not.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer complete interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @retval The state of DMA_IT (SET or RESET).
- */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Return the number of remaining data units in the current DMA Channel transfer.
- * @param __HANDLE__: DMA handle
- * @retval The number of remaining data units in the current DMA Channel transfer.
- */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
- * @}
- */
-
-/* Include DMA HAL Extension module */
-#include "stm32f1xx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
- * @}
- */
-
-/** @addtogroup DMA_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
- * @{
- */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
- ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
- ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
- ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
- ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
- ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
- ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
- ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
- ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
- ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
- ((PRIORITY) == DMA_PRIORITY_HIGH) || \
- ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dma.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dma_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,293 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_dma_ex.h
- * @author MCD Application Team
- * @brief Header file of DMA HAL extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_DMA_EX_H
-#define __STM32F1xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup DMAEx DMAEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
- * @{
- */
-/* Interrupt & Flag management */
-#if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \
- defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices
- * @{
- */
-
-/**
- * @brief Returns the current DMA Channel transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
- DMA_FLAG_TC5)
-
-/**
- * @brief Returns the current DMA Channel half transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
- DMA_FLAG_HT5)
-
-/**
- * @brief Returns the current DMA Channel transfer error flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
- DMA_FLAG_TE5)
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
- DMA_FLAG_GL5)
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
- (DMA1->ISR & (__FLAG__)))
-
-/**
- * @brief Clears the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
- (DMA1->IFCR = (__FLAG__)))
-
-/**
- * @}
- */
-
-#else
-/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
- * @{
- */
-
-/**
- * @brief Returns the current DMA Channel transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer complete flag index.
- */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- DMA_FLAG_TC7)
-
-/**
- * @brief Return the current DMA Channel half transfer complete flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified half transfer complete flag index.
- */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- DMA_FLAG_HT7)
-
-/**
- * @brief Return the current DMA Channel transfer error flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- DMA_FLAG_TE7)
-
-/**
- * @brief Return the current DMA Channel Global interrupt flag.
- * @param __HANDLE__: DMA handle
- * @retval The specified transfer error flag index.
- */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
- DMA_FLAG_GL7)
-
-/**
- * @brief Get the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: Get the specified flag.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * @arg DMA_FLAG_GLx: Global interrupt flag
- * Where x can be 1_7 to select the DMA Channel flag.
- * @retval The state of FLAG (SET or RESET).
- */
-
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
-
-/**
- * @brief Clear the DMA Channel pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg DMA_FLAG_TCx: Transfer complete flag
- * @arg DMA_FLAG_HTx: Half transfer complete flag
- * @arg DMA_FLAG_TEx: Transfer error flag
- * @arg DMA_FLAG_GLx: Global interrupt flag
- * Where x can be 1_7 to select the DMA Channel flag.
- * @retval None
- */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
-
-/**
- * @}
- */
-
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */
- /* STM32F103xG || STM32F105xC || STM32F107xC */
-
-#endif /* __STM32F1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_eth.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2111 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_eth.h
- * @author MCD Application Team
- * @brief Header file of ETH HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_ETH_H
-#define __STM32F1xx_HAL_ETH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-#if defined (STM32F107xC)
-
-/** @addtogroup ETH
- * @{
- */
-
-/** @addtogroup ETH_Private_Macros
- * @{
- */
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
-#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
- ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
-#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
- ((SPEED) == ETH_SPEED_100M))
-#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
- ((MODE) == ETH_MODE_HALFDUPLEX))
-#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
- ((MODE) == ETH_RXINTERRUPT_MODE))
-#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
- ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
-#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
- ((MODE) == ETH_MEDIA_INTERFACE_RMII))
-#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
- ((CMD) == ETH_WATCHDOG_DISABLE))
-#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
- ((CMD) == ETH_JABBER_DISABLE))
-#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
- ((GAP) == ETH_INTERFRAMEGAP_40BIT))
-#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
- ((CMD) == ETH_CARRIERSENCE_DISABLE))
-#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
- ((CMD) == ETH_RECEIVEOWN_DISABLE))
-#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
- ((CMD) == ETH_LOOPBACKMODE_DISABLE))
-#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
- ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
-#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
- ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
-#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
- ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
-#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
- ((LIMIT) == ETH_BACKOFFLIMIT_1))
-#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
- ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
-#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
- ((CMD) == ETH_RECEIVEAll_DISABLE))
-#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
- ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
-#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
- ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
-#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
- ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
-#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
- ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
-#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
- ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
-#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
- ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
-#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
- ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
-#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
- ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
-#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
- ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
-#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
- ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
-#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
-#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
- ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
-#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
- ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
-#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
- ((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
- ((ADDRESS) == ETH_MAC_ADDRESS2) || \
- ((ADDRESS) == ETH_MAC_ADDRESS3))
-#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
- ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
-#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
- ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
-#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
- ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
-#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
-#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
- ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
-#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
- ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
-#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
- ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
-#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
-#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
- ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
-#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
- ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
-#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
- ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
-#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
- ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
-#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
- ((CMD) == ETH_FIXEDBURST_DISABLE))
-#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
- ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
-#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
- ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
- ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
-#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
- ((FLAG) == ETH_DMATXDESC_IC) || \
- ((FLAG) == ETH_DMATXDESC_LS) || \
- ((FLAG) == ETH_DMATXDESC_FS) || \
- ((FLAG) == ETH_DMATXDESC_DC) || \
- ((FLAG) == ETH_DMATXDESC_DP) || \
- ((FLAG) == ETH_DMATXDESC_TTSE) || \
- ((FLAG) == ETH_DMATXDESC_TER) || \
- ((FLAG) == ETH_DMATXDESC_TCH) || \
- ((FLAG) == ETH_DMATXDESC_TTSS) || \
- ((FLAG) == ETH_DMATXDESC_IHE) || \
- ((FLAG) == ETH_DMATXDESC_ES) || \
- ((FLAG) == ETH_DMATXDESC_JT) || \
- ((FLAG) == ETH_DMATXDESC_FF) || \
- ((FLAG) == ETH_DMATXDESC_PCE) || \
- ((FLAG) == ETH_DMATXDESC_LCA) || \
- ((FLAG) == ETH_DMATXDESC_NC) || \
- ((FLAG) == ETH_DMATXDESC_LCO) || \
- ((FLAG) == ETH_DMATXDESC_EC) || \
- ((FLAG) == ETH_DMATXDESC_VF) || \
- ((FLAG) == ETH_DMATXDESC_CC) || \
- ((FLAG) == ETH_DMATXDESC_ED) || \
- ((FLAG) == ETH_DMATXDESC_UF) || \
- ((FLAG) == ETH_DMATXDESC_DB))
-#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
- ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
-#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
- ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
-#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
- ((FLAG) == ETH_DMARXDESC_AFM) || \
- ((FLAG) == ETH_DMARXDESC_ES) || \
- ((FLAG) == ETH_DMARXDESC_DE) || \
- ((FLAG) == ETH_DMARXDESC_SAF) || \
- ((FLAG) == ETH_DMARXDESC_LE) || \
- ((FLAG) == ETH_DMARXDESC_OE) || \
- ((FLAG) == ETH_DMARXDESC_VLAN) || \
- ((FLAG) == ETH_DMARXDESC_FS) || \
- ((FLAG) == ETH_DMARXDESC_LS) || \
- ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
- ((FLAG) == ETH_DMARXDESC_LC) || \
- ((FLAG) == ETH_DMARXDESC_FT) || \
- ((FLAG) == ETH_DMARXDESC_RWT) || \
- ((FLAG) == ETH_DMARXDESC_RE) || \
- ((FLAG) == ETH_DMARXDESC_DBE) || \
- ((FLAG) == ETH_DMARXDESC_CE) || \
- ((FLAG) == ETH_DMARXDESC_MAMPCE))
-#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
- ((BUFFER) == ETH_DMARXDESC_BUFFER2))
-#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
- ((FLAG) == ETH_PMT_FLAG_MPR))
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
-#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
- ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
- ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
- ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
- ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
- ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
- ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
- ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
- ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
- ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
- ((FLAG) == ETH_DMA_FLAG_T))
-#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
-#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
- ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
- ((IT) == ETH_MAC_IT_PMT))
-#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
- ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
- ((FLAG) == ETH_MAC_FLAG_PMT))
-#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
-#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
- ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
- ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
- ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
- ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
- ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
- ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
- ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
- ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
-#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
- ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
-#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
- ((IT) != 0x00U))
-#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
- ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
- ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
-#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
- ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
-
-/**
- * @}
- */
-
-/** @addtogroup ETH_Private_Defines
- * @{
- */
-/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY 0x00000001U
-
-/* ETHERNET Errors */
-#define ETH_SUCCESS 0U
-#define ETH_ERROR 1U
-
-/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
-
-/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
-
-/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
-
-/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
-
-/* ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
-
-/* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
-
-/* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
-
-/* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
-
-/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8U
-
-/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ETH_Exported_Types ETH Exported Types
- * @{
- */
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
- HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
- HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
- HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
- HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-} HAL_ETH_StateTypeDef;
-
-/**
- * @brief ETH Init Structure definition
- */
-
-typedef struct
-{
- uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
- The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
- and the mode (half/full-duplex).
- This parameter can be a value of @ref ETH_AutoNegotiation */
-
- uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
- This parameter can be a value of @ref ETH_Speed */
-
- uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
- This parameter can be a value of @ref ETH_Duplex_Mode */
-
- uint16_t PhyAddress; /*!< Ethernet PHY address.
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-
- uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-
- uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
- This parameter can be a value of @ref ETH_Rx_Mode */
-
- uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
- This parameter can be a value of @ref ETH_Checksum_Mode */
-
- uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
- This parameter can be a value of @ref ETH_Media_Interface */
-
-} ETH_InitTypeDef;
-
-
-/**
- * @brief ETH MAC Configuration Structure definition
- */
-
-typedef struct
-{
- uint32_t Watchdog; /*!< Selects or not the Watchdog timer
- When enabled, the MAC allows no more then 2048 bytes to be received.
- When disabled, the MAC can receive up to 16384 bytes.
- This parameter can be a value of @ref ETH_Watchdog */
-
- uint32_t Jabber; /*!< Selects or not Jabber timer
- When enabled, the MAC allows no more then 2048 bytes to be sent.
- When disabled, the MAC can send up to 16384 bytes.
- This parameter can be a value of @ref ETH_Jabber */
-
- uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
- This parameter can be a value of @ref ETH_Inter_Frame_Gap */
-
- uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
- This parameter can be a value of @ref ETH_Carrier_Sense */
-
- uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
- ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
- in Half-Duplex mode.
- This parameter can be a value of @ref ETH_Receive_Own */
-
- uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
- This parameter can be a value of @ref ETH_Loop_Back_Mode */
-
- uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
- This parameter can be a value of @ref ETH_Checksum_Offload */
-
- uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
- when a collision occurs (Half-Duplex mode).
- This parameter can be a value of @ref ETH_Retry_Transmission */
-
- uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
- This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
-
- uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
- This parameter can be a value of @ref ETH_Back_Off_Limit */
-
- uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
- This parameter can be a value of @ref ETH_Deferral_Check */
-
- uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
- This parameter can be a value of @ref ETH_Receive_All */
-
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
- This parameter can be a value of @ref ETH_Source_Addr_Filter */
-
- uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
- This parameter can be a value of @ref ETH_Pass_Control_Frames */
-
- uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
- This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
-
- uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
- This parameter can be a value of @ref ETH_Destination_Addr_Filter */
-
- uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
- This parameter can be a value of @ref ETH_Promiscuous_Mode */
-
- uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
-
- uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
-
- uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
-
- uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
-
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
-
- uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
- This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
-
- uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
- automatic retransmission of PAUSE Frame.
- This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-
- uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
- unicast address and unique multicast address).
- This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
-
- uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
- disable its transmitter for a specified time (Pause Time)
- This parameter can be a value of @ref ETH_Receive_Flow_Control */
-
- uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
- or the MAC back-pressure operation (Half-Duplex mode)
- This parameter can be a value of @ref ETH_Transmit_Flow_Control */
-
- uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
- comparison and filtering.
- This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
-
- uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
-
-} ETH_MACInitTypeDef;
-
-/**
- * @brief ETH DMA Configuration Structure definition
- */
-
-typedef struct
-{
- uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
- This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
-
- uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
- This parameter can be a value of @ref ETH_Receive_Store_Forward */
-
- uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
- This parameter can be a value of @ref ETH_Flush_Received_Frame */
-
- uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
- This parameter can be a value of @ref ETH_Transmit_Store_Forward */
-
- uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
- This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
-
- uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
- This parameter can be a value of @ref ETH_Forward_Error_Frames */
-
- uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
- and length less than 64 bytes) including pad-bytes and CRC)
- This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
-
- uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
- This parameter can be a value of @ref ETH_Receive_Threshold_Control */
-
- uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
- frame of Transmit data even before obtaining the status for the first frame.
- This parameter can be a value of @ref ETH_Second_Frame_Operate */
-
- uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
- This parameter can be a value of @ref ETH_Address_Aligned_Beats */
-
- uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
- This parameter can be a value of @ref ETH_Fixed_Burst */
-
- uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
- This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
-
- uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
- This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
-
- uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-
- uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
- This parameter can be a value of @ref ETH_DMA_Arbitration */
-} ETH_DMAInitTypeDef;
-
-
-/**
- * @brief ETH DMA Descriptors data structure definition
- */
-
-typedef struct
-{
- __IO uint32_t Status; /*!< Status */
-
- uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
-
- uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
-
- uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
-
-} ETH_DMADescTypeDef;
-
-/**
- * @brief Received Frame Informations structure definition
- */
-typedef struct
-{
- ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
-
- ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
-
- uint32_t SegCount; /*!< Segment count */
-
- uint32_t length; /*!< Frame length */
-
- uint32_t buffer; /*!< Frame buffer */
-
-} ETH_DMARxFrameInfos;
-
-/**
- * @brief ETH Handle Structure definition
- */
-
-typedef struct
-{
- ETH_TypeDef *Instance; /*!< Register base address */
-
- ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
-
- uint32_t LinkStatus; /*!< Ethernet link status */
-
- ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
-
- ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
-
- ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
-
- __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
-
- HAL_LockTypeDef Lock; /*!< ETH Lock */
-
-} ETH_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ETH_Exported_Constants ETH Exported Constants
- * @{
- */
-
-/** @defgroup ETH_Buffers_setting ETH Buffers setting
- * @{
- */
-#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC 4U /*!< Ethernet CRC */
-#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
-#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
-
-/* Ethernet driver receive buffers are organized in a chained linked-list, when
- an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
- to the driver receive buffers memory.
-
- Depending on the size of the received ethernet packet and the size of
- each ethernet driver receive buffer, the received packet can take one or more
- ethernet driver receive buffer.
-
- In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
- and the total count of the driver receive buffers ETH_RXBUFNB.
-
- The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
-
-/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
- packet */
-#ifndef ETH_RX_BUF_SIZE
-#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
-#endif
-
-/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
-#ifndef ETH_RXBUFNB
-#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
-#endif
-
-
-/* Ethernet driver transmit buffers are organized in a chained linked-list, when
- an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
- driver transmit buffers memory to the TxFIFO.
-
- Depending on the size of the Ethernet packet to be transmitted and the size of
- each ethernet driver transmit buffer, the packet to be transmitted can take
- one or more ethernet driver transmit buffer.
-
- In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
- and the total count of the driver transmit buffers ETH_TXBUFNB.
-
- The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
-
-/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
- packet */
-#ifndef ETH_TX_BUF_SIZE
-#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
-#endif
-
-/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
-#ifndef ETH_TXBUFNB
-#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
- * @{
- */
-
-/*
- DMA Tx Descriptor
- -----------------------------------------------------------------------------------------------
- TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
- -----------------------------------------------------------------------------------------------
- TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
- -----------------------------------------------------------------------------------------------
- TDES2 | Buffer1 Address [31:0] |
- -----------------------------------------------------------------------------------------------
- TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
- -----------------------------------------------------------------------------------------------
-*/
-
-/**
- * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
- */
-#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
-#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
-#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
-#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
-#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
-#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
-
-/**
- * @brief Bit definition of TDES1 register
- */
-#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
-
-/**
- * @brief Bit definition of TDES2 register
- */
-#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-
-/**
- * @brief Bit definition of TDES3 register
- */
-#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
-
-/**
- * @}
- */
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
- * @{
- */
-
-/*
- DMA Rx Descriptor
- --------------------------------------------------------------------------------------------------------------------
- RDES0 | OWN(31) | Status [30:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES2 | Buffer1 Address [31:0] |
- ---------------------------------------------------------------------------------------------------------------------
- RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
- ---------------------------------------------------------------------------------------------------------------------
-*/
-
-/**
- * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
- */
-#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
-#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
-#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
-#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
-#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
-#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
-#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-
-/**
- * @brief Bit definition of RDES1 register
- */
-#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
-
-/**
- * @brief Bit definition of RDES2 register
- */
-#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-
-/**
- * @brief Bit definition of RDES3 register
- */
-#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
-
-/**
- * @}
- */
-/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
- * @{
- */
-#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
-#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
-
-/**
- * @}
- */
-/** @defgroup ETH_Speed ETH Speed
- * @{
- */
-#define ETH_SPEED_10M 0x00000000U
-#define ETH_SPEED_100M 0x00004000U
-
-/**
- * @}
- */
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
- * @{
- */
-#define ETH_MODE_FULLDUPLEX 0x00000800U
-#define ETH_MODE_HALFDUPLEX 0x00000000U
-/**
- * @}
- */
-/** @defgroup ETH_Rx_Mode ETH Rx Mode
- * @{
- */
-#define ETH_RXPOLLING_MODE 0x00000000U
-#define ETH_RXINTERRUPT_MODE 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
- * @{
- */
-#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
-#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup ETH_Media_Interface ETH Media Interface
- * @{
- */
-#define ETH_MEDIA_INTERFACE_MII 0x00000000U
-#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
-
-/**
- * @}
- */
-
-/** @defgroup ETH_Watchdog ETH Watchdog
- * @{
- */
-#define ETH_WATCHDOG_ENABLE 0x00000000U
-#define ETH_WATCHDOG_DISABLE 0x00800000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Jabber ETH Jabber
- * @{
- */
-#define ETH_JABBER_ENABLE 0x00000000U
-#define ETH_JABBER_DISABLE 0x00400000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
- * @{
- */
-#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
-/**
- * @}
- */
-
-/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
- * @{
- */
-#define ETH_CARRIERSENCE_ENABLE 0x00000000U
-#define ETH_CARRIERSENCE_DISABLE 0x00010000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Own ETH Receive Own
- * @{
- */
-#define ETH_RECEIVEOWN_ENABLE 0x00000000U
-#define ETH_RECEIVEOWN_DISABLE 0x00002000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
- * @{
- */
-#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
-#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
- * @{
- */
-#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
-#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
- * @{
- */
-#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
-#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
-/**
- * @}
- */
-
-/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
- * @{
- */
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
- * @{
- */
-#define ETH_BACKOFFLIMIT_10 0x00000000U
-#define ETH_BACKOFFLIMIT_8 0x00000020U
-#define ETH_BACKOFFLIMIT_4 0x00000040U
-#define ETH_BACKOFFLIMIT_1 0x00000060U
-/**
- * @}
- */
-
-/** @defgroup ETH_Deferral_Check ETH Deferral Check
- * @{
- */
-#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
-#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_All ETH Receive All
- * @{
- */
-#define ETH_RECEIVEALL_ENABLE 0x80000000U
-#define ETH_RECEIVEAll_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
- * @{
- */
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
-#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
- * @{
- */
-#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
-/**
- * @}
- */
-
-/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
- * @{
- */
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
-/**
- * @}
- */
-
-/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
- * @{
- */
-#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
-#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
- * @{
- */
-#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
-#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
- * @{
- */
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
-#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
-#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
- * @{
- */
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
-#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
- * @{
- */
-#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
-#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
-/**
- * @}
- */
-
-/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
- * @{
- */
-#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
-/**
- * @}
- */
-
-/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
- * @{
- */
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
- * @{
- */
-#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
-#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
- * @{
- */
-#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
-#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
- * @{
- */
-#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
-#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses ETH MAC addresses
- * @{
- */
-#define ETH_MAC_ADDRESS0 0x00000000U
-#define ETH_MAC_ADDRESS1 0x00000008U
-#define ETH_MAC_ADDRESS2 0x00000010U
-#define ETH_MAC_ADDRESS3 0x00000018U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
- * @{
- */
-#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
-#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
- * @{
- */
-#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
-/**
- * @}
- */
-
-/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
- * @{
- */
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
- * @{
- */
-#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
-#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
- * @{
- */
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
- * @{
- */
-#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
-#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
- * @{
- */
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
- * @{
- */
-#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
-#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
- * @{
- */
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
- * @{
- */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-/**
- * @}
- */
-
-/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
- * @{
- */
-#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
-#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
- * @{
- */
-#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
-#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
- * @{
- */
-#define ETH_FIXEDBURST_ENABLE 0x00010000U
-#define ETH_FIXEDBURST_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
- * @{
- */
-#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
-/**
- * @}
- */
-
-/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
- * @{
- */
-#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
- * @{
- */
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
-#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
- * @{
- */
-#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
- * @{
- */
-#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
- * @{
- */
-#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
-/**
- * @}
- */
-
-/** @defgroup ETH_PMT_Flags ETH PMT Flags
- * @{
- */
-#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
-#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
-/**
- * @}
- */
-
-/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
- * @{
- */
-#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
-/**
- * @}
- */
-
-/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
- * @{
- */
-#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Flags ETH MAC Flags
- * @{
- */
-#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
-#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
-#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
-#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Flags ETH DMA Flags
- * @{
- */
-#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
-#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
-#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
-#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
-#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
-/**
- * @}
- */
-
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
- * @{
- */
-#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
-#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
-#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
-#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
- * @{
- */
-#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
-#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
-#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
-#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
-#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
-#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
-#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
-#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
-#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
-#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
-#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
- * @{
- */
-#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
-#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
-#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
-#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
-#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
-
-/**
- * @}
- */
-
-
-/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
- * @{
- */
-#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
-#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
-#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
-#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
-
-/**
- * @}
- */
-
-/** @defgroup ETH_DMA_overflow ETH DMA overflow
- * @{
- */
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
-/**
- * @}
- */
-
-/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
- * @{
- */
-#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ETH_Exported_Macros ETH Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/** @brief Reset ETH handle state
- * @param __HANDLE__: specifies the ETH handle.
- * @retval None
- */
-#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
-
-/**
- * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of TDES0 to check.
- * @retval the ETH_DMATxDescFlag (SET or RESET).
- */
-#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of RDES0 to check.
- * @retval the ETH_DMATxDescFlag (SET or RESET).
- */
-#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
-
-/**
- * @brief Enables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
-
-/**
- * @brief Disables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
-
-/**
- * @brief Set the specified DMA Rx Desc Own bit.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
-
-/**
- * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
- * @param __HANDLE__: ETH Handle
- * @retval The Transmit descriptor collision counter value.
- */
-#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
-
-/**
- * @brief Set the specified DMA Tx Desc Own bit.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
-
-/**
- * @brief Enables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
-
-/**
- * @brief Disables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
-
-/**
- * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
- * @param __HANDLE__: ETH Handle
- * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
- * This parameter can be one of the following values:
- * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
- * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
-
-/**
- * @brief Enables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
-
-/**
- * @brief Disables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
-
-/**
- * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
-
-/**
- * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
-
-/**
- * @brief Enables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
- * enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_IT_PMT : PMT interrupt
- * @retval None
- */
-#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
- * enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_IT_PMT : PMT interrupt
- * @retval None
- */
-#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
-
-/**
- * @brief Initiate a Pause Control Frame (Full-duplex only).
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Checks whether the ETHERNET flow control busy bit is set or not.
- * @param __HANDLE__: ETH Handle
- * @retval The new state of flow control busy status bit (SET or RESET).
- */
-#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
-
-/**
- * @brief Checks whether the specified ETHERNET MAC flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
- * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
- * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
- * @arg ETH_MAC_FLAG_MMC : MMC flag
- * @arg ETH_MAC_FLAG_PMT : PMT flag
- * @retval The state of ETHERNET MAC flag.
- */
-#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Enables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * enabled @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
- * disabled. @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
-
-/**
- * @brief Clears the ETHERNET DMA IT pending bit.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
- * @retval None
- */
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA flag is set or not.
-* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
- * @retval The new state of ETH_DMA_FLAG (SET or RESET).
- */
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
- * @retval The new state of ETH_DMA_FLAG (SET or RESET).
- */
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
-
-/**
- * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __OVERFLOW__: specifies the DMA overflow flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
- * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
- * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
- */
-#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
-
-/**
- * @brief Set the DMA Receive status watchdog timer register value
- * @param __HANDLE__: ETH Handle
- * @param __VALUE__: DMA Receive status watchdog timer register value
- * @retval None
- */
-#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
-
-/**
- * @brief Enables any unicast packet filtered by the MAC address
- * recognition to be a wake-up frame.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
-
-/**
- * @brief Disables any unicast packet filtered by the MAC address
- * recognition to be a wake-up frame.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
-
-/**
- * @brief Enables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Disables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Enables the MAC Magic Packet Detection.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
-
-/**
- * @brief Disables the MAC Magic Packet Detection.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
-
-/**
- * @brief Enables the MAC Power Down.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
-
-/**
- * @brief Disables the MAC Power Down.
- * @param __HANDLE__: ETH Handle
- * @retval None
- */
-#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
-
-/**
- * @brief Checks whether the specified ETHERNET PMT flag is set or not.
- * @param __HANDLE__: ETH Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
- * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
- * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
- * @retval The new state of ETHERNET PMT Flag (SET or RESET).
- */
-#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
-
-/**
- * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
-
-/**
- * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
- (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U)
-
-/**
- * @brief Enables the MMC Counter Freeze.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
-
-/**
- * @brief Disables the MMC Counter Freeze.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
-
-/**
- * @brief Enables the MMC Reset On Read.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
-
-/**
- * @brief Disables the MMC Reset On Read.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
-
-/**
- * @brief Enables the MMC Counter Stop Rollover.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
-
-/**
- * @brief Disables the MMC Counter Stop Rollover.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
-
-/**
- * @brief Resets the MMC Counters.
- * @param __HANDLE__: ETH Handle.
- * @retval None
- */
-#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
-
-/**
- * @brief Enables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
-/**
- * @brief Disables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
-/**
- * @brief Enables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
-
-/**
- * @brief Disables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
- * @retval None
- */
-#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
-
-/**
- * @brief Enables the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disables the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enable event on ETH External event line.
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disable event on ETH External event line
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Get flag of the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Clear flag of the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enables rising edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
-
-/**
- * @brief Disables the rising edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enables falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Disables falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
-/**
- * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
- }while(0U)
-
-/**
- * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
- * @retval None
- */
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- }while(0U)
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None.
- */
-#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
-
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup ETH_Exported_Functions
- * @{
- */
-
-/* Initialization and de-initialization functions ****************************/
-
-/** @addtogroup ETH_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
-void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
-HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
-
-/**
- * @}
- */
-/* IO operation functions ****************************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
-/* Communication with PHY functions*/
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
-void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
-/* Callback in non blocking modes (Interrupt) */
-void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group3
- * @{
- */
-
-HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-
-/** @addtogroup ETH_Exported_Functions_Group4
- * @{
- */
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F107xC */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_ETH_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_eth.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_flash.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,344 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash.h
- * @author MCD Application Team
- * @brief Header file of Flash HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_FLASH_H
-#define __STM32F1xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/** @addtogroup FLASH_Private_Constants
- * @{
- */
-#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Private_Macros
- * @{
- */
-
-#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
- ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
-
-#if defined(FLASH_ACR_LATENCY)
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
- ((__LATENCY__) == FLASH_LATENCY_1) || \
- ((__LATENCY__) == FLASH_LATENCY_2))
-
-#else
-#define IS_FLASH_LATENCY(__LATENCY__) ((__LATENCY__) == FLASH_LATENCY_0)
-#endif /* FLASH_ACR_LATENCY */
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Procedure structure definition
- */
-typedef enum
-{
- FLASH_PROC_NONE = 0U,
- FLASH_PROC_PAGEERASE = 1U,
- FLASH_PROC_MASSERASE = 2U,
- FLASH_PROC_PROGRAMHALFWORD = 3U,
- FLASH_PROC_PROGRAMWORD = 4U,
- FLASH_PROC_PROGRAMDOUBLEWORD = 5U
-} FLASH_ProcedureTypeDef;
-
-/**
- * @brief FLASH handle Structure definition
- */
-typedef struct
-{
- __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
-
- __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
-
- __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
-
- __IO uint64_t Data; /*!< Internal variable to save data to be programmed */
-
- HAL_LockTypeDef Lock; /*!< FLASH locking object */
-
- __IO uint32_t ErrorCode; /*!< FLASH error code
- This parameter can be a value of @ref FLASH_Error_Codes */
-} FLASH_ProcessTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
- * @{
- */
-
-/** @defgroup FLASH_Error_Codes FLASH Error Codes
- * @{
- */
-
-#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
-#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
-#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
-#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Type_Program FLASH Type Program
- * @{
- */
-#define FLASH_TYPEPROGRAM_HALFWORD 0x01U /*!<Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_WORD 0x02U /*!<Program a word (32-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x03U /*!<Program a double word (64-bit) at a specified address*/
-
-/**
- * @}
- */
-
-#if defined(FLASH_ACR_LATENCY)
-/** @defgroup FLASH_Latency FLASH Latency
- * @{
- */
-#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
-#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
-#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
-
-/**
- * @}
- */
-
-#else
-/** @defgroup FLASH_Latency FLASH Latency
- * @{
- */
-#define FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
-
-/**
- * @}
- */
-
-#endif /* FLASH_ACR_LATENCY */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
- * @brief macros to control FLASH features
- * @{
- */
-
-/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
- * @brief macros to handle FLASH half cycle
- * @{
- */
-
-/**
- * @brief Enable the FLASH half cycle access.
- * @note half cycle access can only be used with a low-frequency clock of less than
- 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
- * @retval None
- */
-#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
-
-/**
- * @brief Disable the FLASH half cycle access.
- * @note half cycle access can only be used with a low-frequency clock of less than
- 8 MHz that can be obtained with the use of HSI or HSE but not of PLL.
- * @retval None
- */
-#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
-
-/**
- * @}
- */
-
-#if defined(FLASH_ACR_LATENCY)
-/** @defgroup FLASH_EM_Latency FLASH Latency
- * @brief macros to handle FLASH Latency
- * @{
- */
-
-/**
- * @brief Set the FLASH Latency.
- * @param __LATENCY__ FLASH Latency
- * The value of this parameter depend on device used within the same series
- * @retval None
- */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
-
-
-/**
- * @brief Get the FLASH Latency.
- * @retval FLASH Latency
- * The value of this parameter depend on device used within the same series
- */
-#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
- * @}
- */
-
-#endif /* FLASH_ACR_LATENCY */
-/** @defgroup FLASH_Prefetch FLASH Prefetch
- * @brief macros to handle FLASH Prefetch buffer
- * @{
- */
-/**
- * @brief Enable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
-
-/**
- * @brief Disable the FLASH prefetch buffer.
- * @retval None
- */
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include FLASH HAL Extended module */
-#include "stm32f1xx_hal_flash_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group1
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-
-/* FLASH IRQ handler function */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-void HAL_FLASH_OB_Launch(void);
-
-/**
- * @}
- */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-uint32_t HAL_FLASH_GetError(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private function -------------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
- * @{
- */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-#if defined(FLASH_BANK2_END)
-HAL_StatusTypeDef FLASH_WaitForLastOperationBank2(uint32_t Timeout);
-#endif /* FLASH_BANK2_END */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_flash.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_flash_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,802 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_flash_ex.h
- * @author MCD Application Team
- * @brief Header file of Flash HAL Extended module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_FLASH_EX_H
-#define __STM32F1xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup FLASHEx
- * @{
- */
-
-/** @addtogroup FLASHEx_Private_Constants
- * @{
- */
-
-#define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
-#define OBR_REG_INDEX 1U
-#define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Private_Macros
- * @{
- */
-
-#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
-
-#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
-
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#if defined(FLASH_BANK2_END)
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-#endif /* FLASH_BANK2_END */
-
-/* Low Density */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-
-/* High Density */
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
-#endif /* FLASH_BANK2_END */
-
-/* Connectivity Line */
-#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
- (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
- ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
-#endif /* STM32F105xC || STM32F107xC */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
-
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
- ((BANK) == FLASH_BANK_2) || \
- ((BANK) == FLASH_BANK_BOTH))
-#else
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* FLASH_BANK2_END */
-
-/* Low Density */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
-
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
- ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
- ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
-
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-
-/* High Density */
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
- ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
-
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if defined(FLASH_BANK2_END)
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
- ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
-
-#endif /* FLASH_BANK2_END */
-
-/* Connectivity Line */
-#if (defined(STM32F105xC) || defined(STM32F107xC))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
- ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
- ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
- * @{
- */
-
-/**
- * @brief FLASH Erase structure definition
- */
-typedef struct
-{
- uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
- This parameter can be a value of @ref FLASHEx_Type_Erase */
-
- uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
- This parameter must be a value of @ref FLASHEx_Banks */
-
- uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
- This parameter must be a number between Min_Data = 0x08000000 and Max_Data = FLASH_BANKx_END
- (x = 1 or 2 depending on devices)*/
-
- uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
- This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
-
-} FLASH_EraseInitTypeDef;
-
-/**
- * @brief FLASH Options bytes program structure definition
- */
-typedef struct
-{
- uint32_t OptionType; /*!< OptionType: Option byte to be configured.
- This parameter can be a value of @ref FLASHEx_OB_Type */
-
- uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
- This parameter can be a value of @ref FLASHEx_OB_WRP_State */
-
- uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
- This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
-
- uint32_t Banks; /*!< Select banks for WRP activation/deactivation of all sectors.
- This parameter must be a value of @ref FLASHEx_Banks */
-
- uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
- This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
-
-#if defined(FLASH_BANK2_END)
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
- IWDG / STOP / STDBY / BOOT1
- This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
- @ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1 */
-#else
- uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
- IWDG / STOP / STDBY
- This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
- @ref FLASHEx_OB_nRST_STDBY */
-#endif /* FLASH_BANK2_END */
-
- uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
- This parameter can be a value of @ref FLASHEx_OB_Data_Address */
-
- uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-} FLASH_OBProgramInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
- * @{
- */
-
-/** @defgroup FLASHEx_Constants FLASH Constants
- * @{
- */
-
-/** @defgroup FLASHEx_Page_Size Page Size
- * @{
- */
-#if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
-#define FLASH_PAGE_SIZE 0x400U
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
- /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-
-#if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
-#define FLASH_PAGE_SIZE 0x800U
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
- /* STM32F101xG || STM32F103xG */
- /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Type_Erase Type Erase
- * @{
- */
-#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE 0x02U /*!<Flash mass erase activation*/
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_Banks Banks
- * @{
- */
-#if defined(FLASH_BANK2_END)
-#define FLASH_BANK_1 1U /*!< Bank 1 */
-#define FLASH_BANK_2 2U /*!< Bank 2 */
-#define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
-
-#else
-#define FLASH_BANK_1 1U /*!< Bank 1 */
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
- * @{
- */
-
-/** @defgroup FLASHEx_OB_Type Option Bytes Type
- * @{
- */
-#define OPTIONBYTE_WRP 0x01U /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP 0x02U /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER 0x04U /*!<USER option byte configuration*/
-#define OPTIONBYTE_DATA 0x08U /*!<DATA option byte configuration*/
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
- * @{
- */
-#define OB_WRPSTATE_DISABLE 0x00U /*!<Disable the write protection of the desired pages*/
-#define OB_WRPSTATE_ENABLE 0x01U /*!<Enable the write protection of the desired pagess*/
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_Write_Protection Option Bytes Write Protection
- * @{
- */
-/* STM32 Low and Medium density devices */
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
- || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
- || defined(STM32F103xB)
-#define OB_WRP_PAGES0TO3 0x00000001U /*!< Write protection of page 0 to 3 */
-#define OB_WRP_PAGES4TO7 0x00000002U /*!< Write protection of page 4 to 7 */
-#define OB_WRP_PAGES8TO11 0x00000004U /*!< Write protection of page 8 to 11 */
-#define OB_WRP_PAGES12TO15 0x00000008U /*!< Write protection of page 12 to 15 */
-#define OB_WRP_PAGES16TO19 0x00000010U /*!< Write protection of page 16 to 19 */
-#define OB_WRP_PAGES20TO23 0x00000020U /*!< Write protection of page 20 to 23 */
-#define OB_WRP_PAGES24TO27 0x00000040U /*!< Write protection of page 24 to 27 */
-#define OB_WRP_PAGES28TO31 0x00000080U /*!< Write protection of page 28 to 31 */
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
- /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-
-/* STM32 Medium-density devices */
-#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
-#define OB_WRP_PAGES32TO35 0x00000100U /*!< Write protection of page 32 to 35 */
-#define OB_WRP_PAGES36TO39 0x00000200U /*!< Write protection of page 36 to 39 */
-#define OB_WRP_PAGES40TO43 0x00000400U /*!< Write protection of page 40 to 43 */
-#define OB_WRP_PAGES44TO47 0x00000800U /*!< Write protection of page 44 to 47 */
-#define OB_WRP_PAGES48TO51 0x00001000U /*!< Write protection of page 48 to 51 */
-#define OB_WRP_PAGES52TO55 0x00002000U /*!< Write protection of page 52 to 55 */
-#define OB_WRP_PAGES56TO59 0x00004000U /*!< Write protection of page 56 to 59 */
-#define OB_WRP_PAGES60TO63 0x00008000U /*!< Write protection of page 60 to 63 */
-#define OB_WRP_PAGES64TO67 0x00010000U /*!< Write protection of page 64 to 67 */
-#define OB_WRP_PAGES68TO71 0x00020000U /*!< Write protection of page 68 to 71 */
-#define OB_WRP_PAGES72TO75 0x00040000U /*!< Write protection of page 72 to 75 */
-#define OB_WRP_PAGES76TO79 0x00080000U /*!< Write protection of page 76 to 79 */
-#define OB_WRP_PAGES80TO83 0x00100000U /*!< Write protection of page 80 to 83 */
-#define OB_WRP_PAGES84TO87 0x00200000U /*!< Write protection of page 84 to 87 */
-#define OB_WRP_PAGES88TO91 0x00400000U /*!< Write protection of page 88 to 91 */
-#define OB_WRP_PAGES92TO95 0x00800000U /*!< Write protection of page 92 to 95 */
-#define OB_WRP_PAGES96TO99 0x01000000U /*!< Write protection of page 96 to 99 */
-#define OB_WRP_PAGES100TO103 0x02000000U /*!< Write protection of page 100 to 103 */
-#define OB_WRP_PAGES104TO107 0x04000000U /*!< Write protection of page 104 to 107 */
-#define OB_WRP_PAGES108TO111 0x08000000U /*!< Write protection of page 108 to 111 */
-#define OB_WRP_PAGES112TO115 0x10000000U /*!< Write protection of page 112 to 115 */
-#define OB_WRP_PAGES116TO119 0x20000000U /*!< Write protection of page 115 to 119 */
-#define OB_WRP_PAGES120TO123 0x40000000U /*!< Write protection of page 120 to 123 */
-#define OB_WRP_PAGES124TO127 0x80000000U /*!< Write protection of page 124 to 127 */
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
-
-
-/* STM32 High-density, XL-density and Connectivity line devices */
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
- || defined(STM32F101xG) || defined(STM32F103xG) \
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define OB_WRP_PAGES0TO1 0x00000001U /*!< Write protection of page 0 TO 1 */
-#define OB_WRP_PAGES2TO3 0x00000002U /*!< Write protection of page 2 TO 3 */
-#define OB_WRP_PAGES4TO5 0x00000004U /*!< Write protection of page 4 TO 5 */
-#define OB_WRP_PAGES6TO7 0x00000008U /*!< Write protection of page 6 TO 7 */
-#define OB_WRP_PAGES8TO9 0x00000010U /*!< Write protection of page 8 TO 9 */
-#define OB_WRP_PAGES10TO11 0x00000020U /*!< Write protection of page 10 TO 11 */
-#define OB_WRP_PAGES12TO13 0x00000040U /*!< Write protection of page 12 TO 13 */
-#define OB_WRP_PAGES14TO15 0x00000080U /*!< Write protection of page 14 TO 15 */
-#define OB_WRP_PAGES16TO17 0x00000100U /*!< Write protection of page 16 TO 17 */
-#define OB_WRP_PAGES18TO19 0x00000200U /*!< Write protection of page 18 TO 19 */
-#define OB_WRP_PAGES20TO21 0x00000400U /*!< Write protection of page 20 TO 21 */
-#define OB_WRP_PAGES22TO23 0x00000800U /*!< Write protection of page 22 TO 23 */
-#define OB_WRP_PAGES24TO25 0x00001000U /*!< Write protection of page 24 TO 25 */
-#define OB_WRP_PAGES26TO27 0x00002000U /*!< Write protection of page 26 TO 27 */
-#define OB_WRP_PAGES28TO29 0x00004000U /*!< Write protection of page 28 TO 29 */
-#define OB_WRP_PAGES30TO31 0x00008000U /*!< Write protection of page 30 TO 31 */
-#define OB_WRP_PAGES32TO33 0x00010000U /*!< Write protection of page 32 TO 33 */
-#define OB_WRP_PAGES34TO35 0x00020000U /*!< Write protection of page 34 TO 35 */
-#define OB_WRP_PAGES36TO37 0x00040000U /*!< Write protection of page 36 TO 37 */
-#define OB_WRP_PAGES38TO39 0x00080000U /*!< Write protection of page 38 TO 39 */
-#define OB_WRP_PAGES40TO41 0x00100000U /*!< Write protection of page 40 TO 41 */
-#define OB_WRP_PAGES42TO43 0x00200000U /*!< Write protection of page 42 TO 43 */
-#define OB_WRP_PAGES44TO45 0x00400000U /*!< Write protection of page 44 TO 45 */
-#define OB_WRP_PAGES46TO47 0x00800000U /*!< Write protection of page 46 TO 47 */
-#define OB_WRP_PAGES48TO49 0x01000000U /*!< Write protection of page 48 TO 49 */
-#define OB_WRP_PAGES50TO51 0x02000000U /*!< Write protection of page 50 TO 51 */
-#define OB_WRP_PAGES52TO53 0x04000000U /*!< Write protection of page 52 TO 53 */
-#define OB_WRP_PAGES54TO55 0x08000000U /*!< Write protection of page 54 TO 55 */
-#define OB_WRP_PAGES56TO57 0x10000000U /*!< Write protection of page 56 TO 57 */
-#define OB_WRP_PAGES58TO59 0x20000000U /*!< Write protection of page 58 TO 59 */
-#define OB_WRP_PAGES60TO61 0x40000000U /*!< Write protection of page 60 TO 61 */
-#define OB_WRP_PAGES62TO127 0x80000000U /*!< Write protection of page 62 TO 127 */
-#define OB_WRP_PAGES62TO255 0x80000000U /*!< Write protection of page 62 TO 255 */
-#define OB_WRP_PAGES62TO511 0x80000000U /*!< Write protection of page 62 TO 511 */
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
- /* STM32F101xG || STM32F103xG */
- /* STM32F105xC || STM32F107xC */
-
-#define OB_WRP_ALLPAGES 0xFFFFFFFFU /*!< Write protection of all Pages */
-
-/* Low Density */
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
-#define OB_WRP_PAGES0TO31MASK 0x000000FFU
-#endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
-
-/* Medium Density */
-#if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
-#define OB_WRP_PAGES0TO31MASK 0x000000FFU
-#define OB_WRP_PAGES32TO63MASK 0x0000FF00U
-#define OB_WRP_PAGES64TO95MASK 0x00FF0000U
-#define OB_WRP_PAGES96TO127MASK 0xFF000000U
-#endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
-
-/* High Density */
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
-#define OB_WRP_PAGES0TO15MASK 0x000000FFU
-#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
-#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
-#define OB_WRP_PAGES48TO255MASK 0xFF000000U
-#endif /* STM32F100xE || STM32F101xE || STM32F103xE */
-
-/* XL Density */
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define OB_WRP_PAGES0TO15MASK 0x000000FFU
-#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
-#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
-#define OB_WRP_PAGES48TO511MASK 0xFF000000U
-#endif /* STM32F101xG || STM32F103xG */
-
-/* Connectivity line devices */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define OB_WRP_PAGES0TO15MASK 0x000000FFU
-#define OB_WRP_PAGES16TO31MASK 0x0000FF00U
-#define OB_WRP_PAGES32TO47MASK 0x00FF0000U
-#define OB_WRP_PAGES48TO127MASK 0xFF000000U
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
- * @{
- */
-#define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
-#define OB_RDP_LEVEL_1 ((uint8_t)0x00)
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
- * @{
- */
-#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
- * @{
- */
-#define OB_STOP_NO_RST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */
-/**
- * @}
- */
-
-/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
- * @{
- */
-#define OB_STDBY_NO_RST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */
-/**
- * @}
- */
-
-#if defined(FLASH_BANK2_END)
-/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
- * @{
- */
-#define OB_BOOT1_RESET ((uint16_t)0x0000) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET ((uint16_t)0x0008) /*!< BOOT1 Set */
-/**
- * @}
- */
-#endif /* FLASH_BANK2_END */
-
-/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
- * @{
- */
-#define OB_DATA_ADDRESS_DATA0 0x1FFFF804U
-#define OB_DATA_ADDRESS_DATA1 0x1FFFF806U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Constants
- * @{
- */
-
-/** @defgroup FLASH_Flag_definition Flag definition
- * @brief Flag definition
- * @{
- */
-#if defined(FLASH_BANK2_END)
- #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1 /*!< FLASH Bank1 Busy flag */
- #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1 /*!< FLASH Bank1 Programming error flag */
- #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1 /*!< FLASH Bank1 Write protected error flag */
- #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1 /*!< FLASH Bank1 End of Operation flag */
-
- #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank1 Busy flag */
- #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR /*!< FLASH Bank1 Programming error flag */
- #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR /*!< FLASH Bank1 Write protected error flag */
- #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< FLASH Bank1 End of Operation flag */
-
- #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U) /*!< FLASH Bank2 Busy flag */
- #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U) /*!< FLASH Bank2 Programming error flag */
- #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U) /*!< FLASH Bank2 Write protected error flag */
- #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U) /*!< FLASH Bank2 End of Operation flag */
-
-#else
-
- #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
- #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
- #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR /*!< FLASH Write protected error flag */
- #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
-
-#endif
- #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR)) /*!< Option Byte Error */
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupt_definition Interrupt definition
- * @brief FLASH Interrupt definition
- * @{
- */
-#if defined(FLASH_BANK2_END)
- #define FLASH_IT_EOP FLASH_IT_EOP_BANK1 /*!< End of FLASH Operation Interrupt source Bank1 */
- #define FLASH_IT_ERR FLASH_IT_ERR_BANK1 /*!< Error Interrupt source Bank1 */
-
- #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source Bank1 */
- #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE /*!< Error Interrupt source Bank1 */
-
- #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U) /*!< End of FLASH Operation Interrupt source Bank2 */
- #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U) /*!< Error Interrupt source Bank2 */
-
-#else
-
- #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
- #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
-
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
- * @{
- */
-
-/** @defgroup FLASH_Interrupt Interrupt
- * @brief macros to handle FLASH interrupts
- * @{
- */
-
-#if defined(FLASH_BANK2_END)
-/**
- * @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
- * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
- * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
- * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
- * @retval none
- */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
- /* Enable Bank1 IT */ \
- SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
- /* Enable Bank2 IT */ \
- SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
- } while(0U)
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_IT_EOP_BANK1 End of FLASH Operation Interrupt on bank1
- * @arg @ref FLASH_IT_ERR_BANK1 Error Interrupt on bank1
- * @arg @ref FLASH_IT_EOP_BANK2 End of FLASH Operation Interrupt on bank2
- * @arg @ref FLASH_IT_ERR_BANK2 Error Interrupt on bank2
- * @retval none
- */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
- /* Disable Bank1 IT */ \
- CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
- /* Disable Bank2 IT */ \
- CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
- } while(0U)
-
-/**
- * @brief Get the specified FLASH flag status.
- * @param __FLAG__ specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
- * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
- * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
- * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
- * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
- * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
- * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
- * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
- (FLASH->OBR & FLASH_OBR_OPTERR) : \
- ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
- (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
- (FLASH->SR2 & ((__FLAG__) >> 16U))))
-
-/**
- * @brief Clear the specified FLASH flag.
- * @param __FLAG__ specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_FLAG_EOP_BANK1 FLASH End of Operation flag on bank1
- * @arg @ref FLASH_FLAG_WRPERR_BANK1 FLASH Write protected error flag on bank1
- * @arg @ref FLASH_FLAG_PGERR_BANK1 FLASH Programming error flag on bank1
- * @arg @ref FLASH_FLAG_BSY_BANK1 FLASH Busy flag on bank1
- * @arg @ref FLASH_FLAG_EOP_BANK2 FLASH End of Operation flag on bank2
- * @arg @ref FLASH_FLAG_WRPERR_BANK2 FLASH Write protected error flag on bank2
- * @arg @ref FLASH_FLAG_PGERR_BANK2 FLASH Programming error flag on bank2
- * @arg @ref FLASH_FLAG_BSY_BANK2 FLASH Busy flag on bank2
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval none
- */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
- /* Clear FLASH_FLAG_OPTVERR flag */ \
- if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
- { \
- CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
- } \
- else { \
- /* Clear Flag in Bank1 */ \
- if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
- { \
- FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
- } \
- /* Clear Flag in Bank2 */ \
- if (((__FLAG__) >> 16U) != RESET) \
- { \
- FLASH->SR2 = ((__FLAG__) >> 16U); \
- } \
- } \
- } while(0U)
-#else
-/**
- * @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
- * @arg @ref FLASH_IT_ERR Error Interrupt
- * @retval none
- */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
-
-/**
- * @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ FLASH interrupt
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
- * @arg @ref FLASH_IT_ERR Error Interrupt
- * @retval none
- */
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
-
-/**
- * @brief Get the specified FLASH flag status.
- * @param __FLAG__ specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
- * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
- * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
- * @arg @ref FLASH_FLAG_BSY FLASH Busy flag
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval The new state of __FLAG__ (SET or RESET).
- */
-#define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
- (FLASH->OBR & FLASH_OBR_OPTERR) : \
- (FLASH->SR & (__FLAG__)))
-/**
- * @brief Clear the specified FLASH flag.
- * @param __FLAG__ specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
- * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
- * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
- * @arg @ref FLASH_FLAG_OPTVERR Loaded OB and its complement do not match
- * @retval none
- */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
- /* Clear FLASH_FLAG_OPTVERR flag */ \
- if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
- { \
- CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
- } \
- else { \
- /* Clear Flag in Bank1 */ \
- FLASH->SR = (__FLAG__); \
- } \
- } while(0U)
-
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-
-/**
- * @}
- */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group2
- * @{
- */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_flash_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_gpio.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,324 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_GPIO_H
-#define __STM32F1xx_HAL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
- * @{
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_mode_define */
-
- uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
- This parameter can be a value of @ref GPIO_pull_define */
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_speed_define */
-} GPIO_InitTypeDef;
-
-/**
- * @brief GPIO Bit SET and Bit RESET enumeration
- */
-typedef enum
-{
- GPIO_PIN_RESET = 0U,
- GPIO_PIN_SET
-} GPIO_PinState;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define GPIO pins define
- * @{
- */
-#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
-#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
-#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
-#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
-#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
-#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
-#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
-#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
-#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
-
-#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */
-/**
- * @}
- */
-
-/** @defgroup GPIO_mode_define GPIO mode define
- * @brief GPIO Configuration Mode
- * Elements values convention: 0xX0yz00YZ
- * - X : GPIO mode or EXTI Mode
- * - y : External IT or Event trigger detection
- * - z : IO configuration on External IT or Event
- * - Y : Output type (Push Pull or Open Drain)
- * - Z : IO Direction mode (Input, Output, Alternate or Analog)
- * @{
- */
-#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */
-#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */
-#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */
-#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */
-#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */
-#define GPIO_MODE_AF_INPUT GPIO_MODE_INPUT /*!< Alternate Function Input Mode */
-
-#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */
-
-#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */
-#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */
-#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */
-#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_speed_define GPIO speed define
- * @brief GPIO Output Maximum frequency
- * @{
- */
-#define GPIO_SPEED_FREQ_LOW (GPIO_CRL_MODE0_1) /*!< Low speed */
-#define GPIO_SPEED_FREQ_MEDIUM (GPIO_CRL_MODE0_0) /*!< Medium speed */
-#define GPIO_SPEED_FREQ_HIGH (GPIO_CRL_MODE0) /*!< High speed */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_pull_define GPIO pull define
- * @brief GPIO Pull-Up or Pull-Down Activation
- * @{
- */
-#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */
-#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */
-#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param __EXTI_LINE__: specifies the EXTI line flag to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param __EXTI_LINE__: specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval The new state of __EXTI_LINE__ (SET or RESET).
- */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param __EXTI_LINE__: specifies the EXTI lines to clear.
- * This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param __EXTI_LINE__: specifies the EXTI line to check.
- * This parameter can be GPIO_PIN_x where x can be(0..15)
- * @retval None
- */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-/**
- * @}
- */
-
-/* Include GPIO HAL Extension module */
-#include "stm32f1xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
- * @{
- */
-/* Initialization and de-initialization functions *****************************/
-void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
-/**
- * @}
- */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
- * @{
- */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN) ((((PIN) & GPIO_PIN_MASK ) != 0x00U) && (((PIN) & ~GPIO_PIN_MASK) == 0x00U))
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
- ((MODE) == GPIO_MODE_OUTPUT_PP) ||\
- ((MODE) == GPIO_MODE_OUTPUT_OD) ||\
- ((MODE) == GPIO_MODE_AF_PP) ||\
- ((MODE) == GPIO_MODE_AF_OD) ||\
- ((MODE) == GPIO_MODE_IT_RISING) ||\
- ((MODE) == GPIO_MODE_IT_FALLING) ||\
- ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING) ||\
- ((MODE) == GPIO_MODE_EVT_FALLING) ||\
- ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
- ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || \
- ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || ((SPEED) == GPIO_SPEED_FREQ_HIGH))
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
- ((PULL) == GPIO_PULLDOWN))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Functions GPIO Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_gpio.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_gpio_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,910 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_gpio_ex.h
- * @author MCD Application Team
- * @brief Header file of GPIO HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_GPIO_EX_H
-#define __STM32F1xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup GPIOEx GPIOEx
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
- * @{
- */
-
-/** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration
- * @brief This section propose definition to use the Cortex EVENTOUT signal.
- * @{
- */
-
-/** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin
- * @{
- */
-
-#define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
-#define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
-#define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
-#define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
-#define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
-#define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
-#define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
-#define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
-#define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
-#define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
-#define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
-#define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
-#define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
-#define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
-#define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
-#define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
-
-#define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \
- ((__PIN__) == AFIO_EVENTOUT_PIN_15))
-/**
- * @}
- */
-
-/** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port
- * @{
- */
-
-#define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
-#define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
-#define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
-#define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
-#define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
-
-#define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \
- ((__PORT__) == AFIO_EVENTOUT_PORT_E))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping
- * @brief This section propose definition to remap the alternate function to some other port/pins.
- * @{
- */
-
-/**
- * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP)
-
-/**
- * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP)
-
-/**
- * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
- * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP)
-
-/**
- * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
- * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP)
-
-/**
- * @brief Enable the remapping of USART1 alternate function TX and RX.
- * @note ENABLE: Remap (TX/PB6, RX/PB7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP)
-
-/**
- * @brief Disable the remapping of USART1 alternate function TX and RX.
- * @note DISABLE: No remap (TX/PA9, RX/PA10)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP)
-
-/**
- * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP)
-
-/**
- * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP)
-
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
-
-/**
- * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
- * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP)
-
-/**
- * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
- * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP)
-
-/**
- * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
- * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP)
-
-#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP)
-
-#endif
-
-/**
- * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP)
-
-/**
- * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @note DISABLE: No remapping of PD0 and PD1
- * @retval None
- */
-#define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP)
-
-#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
-/**
- * @brief Enable the remapping of TIM5CH4.
- * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP)
-
-/**
- * @brief Disable the remapping of TIM5CH4.
- * @note DISABLE: TIM5_CH4 is connected to PA3
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP)
-#endif
-
-#if defined(AFIO_MAPR_ETH_REMAP)
-/**
- * @brief Enable the remapping of Ethernet MAC connections with the PHY.
- * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP)
-
-/**
- * @brief Disable the remapping of Ethernet MAC connections with the PHY.
- * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_CAN2_REMAP)
-
-/**
- * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP)
-
-/**
- * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_MII_RMII_SEL)
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL)
-
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL)
-#endif
-
-/**
- * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-
-/**
- * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-
-/**
- * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
-
-/**
- * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP)
-
-#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-#endif
-
-#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-#define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP)
-#endif
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET)
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST)
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
- * @retval None
- */
-
-#define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE)
-
-/**
- * @brief Disable the Serial wire JTAG configuration
- * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE)
-
-#if defined(AFIO_MAPR_SPI3_REMAP)
-
-/**
- * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP)
-
-/**
- * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP)
-#endif
-
-#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP)
-#endif
-
-#if defined(AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note ENABLE: PTP_PPS is output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @note DISABLE: PTP_PPS not output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-#define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM9_REMAP)
-
-/**
- * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
- * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
-
-/**
- * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
- * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM10_REMAP)
-
-/**
- * @brief Enable the remapping of TIM10_CH1.
- * @note ENABLE: Remap (TIM10_CH1 on PF6).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
-
-/**
- * @brief Disable the remapping of TIM10_CH1.
- * @note DISABLE: No remap (TIM10_CH1 on PB8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM11_REMAP)
-/**
- * @brief Enable the remapping of TIM11_CH1.
- * @note ENABLE: Remap (TIM11_CH1 on PF7).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
-
-/**
- * @brief Disable the remapping of TIM11_CH1.
- * @note DISABLE: No remap (TIM11_CH1 on PB9).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM13_REMAP)
-
-/**
- * @brief Enable the remapping of TIM13_CH1.
- * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
-
-/**
- * @brief Disable the remapping of TIM13_CH1.
- * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM14_REMAP)
-
-/**
- * @brief Enable the remapping of TIM14_CH1.
- * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
-
-/**
- * @brief Disable the remapping of TIM14_CH1.
- * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
- * @retval None
- */
-#define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @note CONNECTED: The NADV signal is connected to the output (default).
- * @retval None
- */
-#define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM15_REMAP)
-
-/**
- * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
- * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
-
-/**
- * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
- * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM16_REMAP)
-
-/**
- * @brief Enable the remapping of TIM16_CH1.
- * @note ENABLE: Remap (TIM16_CH1 on PA6).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
-
-/**
- * @brief Disable the remapping of TIM16_CH1.
- * @note DISABLE: No remap (TIM16_CH1 on PB8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM17_REMAP)
-
-/**
- * @brief Enable the remapping of TIM17_CH1.
- * @note ENABLE: Remap (TIM17_CH1 on PA7).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
-
-/**
- * @brief Disable the remapping of TIM17_CH1.
- * @note DISABLE: No remap (TIM17_CH1 on PB9).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_CEC_REMAP)
-
-/**
- * @brief Enable the remapping of CEC.
- * @note ENABLE: Remap (CEC on PB10).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
-
-/**
- * @brief Disable the remapping of CEC.
- * @note DISABLE: No remap (CEC on PB8).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_TIM12_REMAP)
-
-/**
- * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
- * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
-
-/**
- * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
- * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP)
-#endif
-
-#if defined(AFIO_MAPR2_MISC_REMAP)
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
- * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
- * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-#define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP)
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
- * @{
- */
-#if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :3U)
-#elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :4U)
-#elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
- ((__GPIOx__) == (GPIOB))? 1U :\
- ((__GPIOx__) == (GPIOC))? 2U :\
- ((__GPIOx__) == (GPIOD))? 3U :\
- ((__GPIOx__) == (GPIOE))? 4U :\
- ((__GPIOx__) == (GPIOF))? 5U :6U)
-#endif
-
-#define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg |= AFIO_MAPR_SWJ_CFG; \
- tmpreg |= REMAP_PIN; \
- AFIO->MAPR = tmpreg; \
- }while(0U)
-
-#define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg |= AFIO_MAPR_SWJ_CFG; \
- tmpreg &= ~REMAP_PIN; \
- AFIO->MAPR = tmpreg; \
- }while(0U)
-
-#define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg &= ~REMAP_PIN_MASK; \
- tmpreg |= AFIO_MAPR_SWJ_CFG; \
- tmpreg |= REMAP_PIN; \
- AFIO->MAPR = tmpreg; \
- }while(0U)
-
-#define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \
- tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \
- tmpreg |= DBGAFR_SWJCFG; \
- AFIO->MAPR = tmpreg; \
- }while(0U)
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup GPIOEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIOEx_Exported_Functions_Group1
- * @{
- */
-void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource);
-void HAL_GPIOEx_EnableEventout(void);
-void HAL_GPIOEx_DisableEventout(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_gpio_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_hcd.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,252 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_hcd.h
- * @author MCD Application Team
- * @brief Header file of HCD HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_HCD_H
-#define __STM32F1xx_HAL_HCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_usb.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup HCD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Types HCD Exported Types
- * @{
- */
-
-/**
- * @brief HCD Status structure definition
- */
-typedef enum
-{
- HAL_HCD_STATE_RESET = 0x00U,
- HAL_HCD_STATE_READY = 0x01U,
- HAL_HCD_STATE_ERROR = 0x02U,
- HAL_HCD_STATE_BUSY = 0x03U,
- HAL_HCD_STATE_TIMEOUT = 0x04U
-} HCD_StateTypeDef;
-
-typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
-typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef HCD_HCTypeDef;
-typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;
-typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef;
-
-/**
- * @brief HCD Handle Structure definition
- */
-typedef struct
-{
- HCD_TypeDef *Instance; /*!< Register base address */
- HCD_InitTypeDef Init; /*!< HCD required parameters */
- HCD_HCTypeDef hc[15U]; /*!< Host channels parameters */
- HAL_LockTypeDef Lock; /*!< HCD peripheral status */
- __IO HCD_StateTypeDef State; /*!< HCD communication state */
- void *pData; /*!< Pointer Stack Handler */
-} HCD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HCD_Exported_Constants HCD Exported Constants
- * @{
- */
-/** @defgroup HCD_Speed HCD Speed
- * @{
- */
-#define HCD_SPEED_LOW 2U
-#define HCD_SPEED_FULL 3U
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HCD_Exported_Macros HCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-
-
-#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
-#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
-#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HCD_Exported_Functions HCD Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-
-HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num);
-
-void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/** @addtogroup HCD_Exported_Functions_Group2 IO operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t pipe,
- uint8_t direction,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
- uint16_t length,
- uint8_t do_ping);
-
- /* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
- HCD_URBStateTypeDef urb_state);
-/**
- * @}
- */
-/* Peripheral Control functions **********************************************/
-/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-/* Peripheral State functions ************************************************/
-/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
-uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HCD_Private_Macros HCD Private Macros
- * @{
- */
-/** @defgroup HCD_Instance_definition HCD Instance definition
- * @{
- */
- #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_hcd.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_i2c.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,650 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_i2c.h
- * @author MCD Application Team
- * @brief Header file of I2C HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_I2C_H
-#define __STM32F1xx_HAL_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
- * @{
- */
-
-/**
- * @brief I2C Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz */
-
- uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
- uint32_t OwnAddress1; /*!< Specifies the first device own address.
- This parameter can be a 7-bit or 10-bit address. */
-
- uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
- This parameter can be a value of @ref I2C_addressing_mode */
-
- uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
- This parameter can be a value of @ref I2C_dual_addressing_mode */
-
- uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
- This parameter can be a 7-bit address. */
-
- uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
- This parameter can be a value of @ref I2C_general_call_addressing_mode */
-
- uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
- This parameter can be a value of @ref I2C_nostretch_mode */
-
-}I2C_InitTypeDef;
-
-/**
- * @brief HAL State structure definition
- * @note HAL I2C State value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : Abort (Abort user request on going)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
- * b4 (not used)
- * x : Should be set to 0
- * b3
- * 0 : Ready or Busy (No Listen mode ongoing)
- * 1 : Listen (IP in Address Listen Mode)
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- */
-typedef enum
-{
- HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
- HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
- HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
- HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
- HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
- HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
- process is ongoing */
- HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
- process is ongoing */
- HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
- HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
-
-}HAL_I2C_StateTypeDef;
-
-/**
- * @brief HAL Mode structure definition
- * @note HAL I2C Mode value coding follow below described bitmap :
- * b7 (not used)
- * x : Should be set to 0
- * b6
- * 0 : None
- * 1 : Memory (HAL I2C communication is in Memory Mode)
- * b5
- * 0 : None
- * 1 : Slave (HAL I2C communication is in Slave Mode)
- * b4
- * 0 : None
- * 1 : Master (HAL I2C communication is in Master Mode)
- * b3-b2-b1-b0 (not used)
- * xxxx : Should be set to 0000
- */
-typedef enum
-{
- HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
- HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
- HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
- HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
-
-}HAL_I2C_ModeTypeDef;
-
-/**
- * @brief I2C handle Structure definition
- */
-typedef struct
-{
- I2C_TypeDef *Instance; /*!< I2C registers base address */
-
- I2C_InitTypeDef Init; /*!< I2C communication parameters */
-
- uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
-
- uint16_t XferSize; /*!< I2C transfer size */
-
- __IO uint16_t XferCount; /*!< I2C transfer counter */
-
- __IO uint32_t XferOptions; /*!< I2C transfer options */
-
- __IO uint32_t PreviousState; /*!< I2C communication Previous state and mode
- context for internal usage */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
-
- HAL_LockTypeDef Lock; /*!< I2C locking object */
-
- __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
-
- __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
-
- __IO uint32_t ErrorCode; /*!< I2C Error code */
-
- __IO uint32_t Devaddress; /*!< I2C Target device address */
-
- __IO uint32_t Memaddress; /*!< I2C Target memory address */
-
- __IO uint32_t MemaddSize; /*!< I2C Target memory address size */
-
- __IO uint32_t EventCount; /*!< I2C Event counter */
-
-}I2C_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_Error_Code I2C Error Code
- * @brief I2C Error Code
- * @{
- */
-#define HAL_I2C_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_I2C_ERROR_BERR 0x00000001U /*!< BERR error */
-#define HAL_I2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
-#define HAL_I2C_ERROR_AF 0x00000004U /*!< AF error */
-#define HAL_I2C_ERROR_OVR 0x00000008U /*!< OVR error */
-#define HAL_I2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout Error */
-/**
- * @}
- */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
- * @{
- */
-#define I2C_DUTYCYCLE_2 0x00000000U
-#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
-/**
- * @}
- */
-
-/** @defgroup I2C_addressing_mode I2C addressing mode
- * @{
- */
-#define I2C_ADDRESSINGMODE_7BIT 0x00004000U
-#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U)
-/**
- * @}
- */
-
-/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
- * @{
- */
-#define I2C_DUALADDRESS_DISABLE 0x00000000U
-#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
-/**
- * @}
- */
-
-/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
- * @{
- */
-#define I2C_GENERALCALL_DISABLE 0x00000000U
-#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
-/**
- * @}
- */
-
-/** @defgroup I2C_nostretch_mode I2C nostretch mode
- * @{
- */
-#define I2C_NOSTRETCH_DISABLE 0x00000000U
-#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
-/**
- * @}
- */
-
-/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
- * @{
- */
-#define I2C_MEMADD_SIZE_8BIT 0x00000001U
-#define I2C_MEMADD_SIZE_16BIT 0x00000010U
-/**
- * @}
- */
-
-/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
- * @{
- */
-#define I2C_DIRECTION_RECEIVE 0x00000000U
-#define I2C_DIRECTION_TRANSMIT 0x00000001U
-/**
- * @}
- */
-
-/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
- * @{
- */
-#define I2C_FIRST_FRAME 0x00000001U
-#define I2C_NEXT_FRAME 0x00000002U
-#define I2C_FIRST_AND_LAST_FRAME 0x00000004U
-#define I2C_LAST_FRAME 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
- * @{
- */
-#define I2C_IT_BUF I2C_CR2_ITBUFEN
-#define I2C_IT_EVT I2C_CR2_ITEVTEN
-#define I2C_IT_ERR I2C_CR2_ITERREN
-/**
- * @}
- */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
- * @{
- */
-#define I2C_FLAG_SMBALERT 0x00018000U
-#define I2C_FLAG_TIMEOUT 0x00014000U
-#define I2C_FLAG_PECERR 0x00011000U
-#define I2C_FLAG_OVR 0x00010800U
-#define I2C_FLAG_AF 0x00010400U
-#define I2C_FLAG_ARLO 0x00010200U
-#define I2C_FLAG_BERR 0x00010100U
-#define I2C_FLAG_TXE 0x00010080U
-#define I2C_FLAG_RXNE 0x00010040U
-#define I2C_FLAG_STOPF 0x00010010U
-#define I2C_FLAG_ADD10 0x00010008U
-#define I2C_FLAG_BTF 0x00010004U
-#define I2C_FLAG_ADDR 0x00010002U
-#define I2C_FLAG_SB 0x00010001U
-#define I2C_FLAG_DUALF 0x00100080U
-#define I2C_FLAG_SMBHOST 0x00100040U
-#define I2C_FLAG_SMBDEFAULT 0x00100020U
-#define I2C_FLAG_GENCALL 0x00100010U
-#define I2C_FLAG_TRA 0x00100004U
-#define I2C_FLAG_BUSY 0x00100002U
-#define I2C_FLAG_MSL 0x00100001U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @brief Reset I2C handle state
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @retval None
- */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief Enable or disable the specified I2C interrupts.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt enable
- * @arg I2C_IT_EVT: Event interrupt enable
- * @arg I2C_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-
-/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __INTERRUPT__: specifies the I2C interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_BUF: Buffer interrupt enable
- * @arg I2C_IT_EVT: Event interrupt enable
- * @arg I2C_IT_ERR: Error interrupt enable
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified I2C flag is set or not.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag
- * @arg I2C_FLAG_BERR: Bus error flag
- * @arg I2C_FLAG_TXE: Data register empty flag
- * @arg I2C_FLAG_RXNE: Data register not empty flag
- * @arg I2C_FLAG_STOPF: Stop detection flag
- * @arg I2C_FLAG_ADD10: 10-bit header sent flag
- * @arg I2C_FLAG_BTF: Byte transfer finished flag
- * @arg I2C_FLAG_ADDR: Address sent flag
- * Address matched flag
- * @arg I2C_FLAG_SB: Start bit flag
- * @arg I2C_FLAG_DUALF: Dual flag
- * @arg I2C_FLAG_SMBHOST: SMBus host header
- * @arg I2C_FLAG_SMBDEFAULT: SMBus default header
- * @arg I2C_FLAG_GENCALL: General call header flag
- * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
- * @arg I2C_FLAG_BUSY: Bus busy flag
- * @arg I2C_FLAG_MSL: Master/Slave flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
- ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
-
-/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
- * @arg I2C_FLAG_PECERR: PEC error in reception flag
- * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
- * @arg I2C_FLAG_AF: Acknowledge failure flag
- * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
- * @arg I2C_FLAG_BERR: Bus error flag
- * @retval None
- */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
-
-/** @brief Clears the I2C ADDR pending flag.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @retval None
- */
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR1; \
- tmpreg = (__HANDLE__)->Instance->SR2; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clears the I2C STOPF pending flag.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @retval None
- */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR1; \
- (__HANDLE__)->Instance->CR1 |= I2C_CR1_PE; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Enable the I2C peripheral.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
-
-/** @brief Disable the I2C peripheral.
- * @param __HANDLE__: specifies the I2C Handle.
- * This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2C_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions *****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
- * @}
- */
-
-/** @addtogroup I2C_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State, Mode and Errors functions *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
- * @{
- */
-#define I2C_FLAG_MASK 0x0000FFFFU
-#define I2C_MIN_PCLK_FREQ_STANDARD 2000000U /*!< 2 MHz */
-#define I2C_MIN_PCLK_FREQ_FAST 4000000U /*!< 4 MHz */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macros I2C Private Macros
- * @{
- */
-
-#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))
-#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__) (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)
-#define I2C_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__) ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
- ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \
- ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
-#define I2C_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F0U))))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300U))) >> 7U) | (uint16_t)(0x00F1U))))
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters
- * @{
- */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
- ((CYCLE) == I2C_DUTYCYCLE_16_9))
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
- ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
- ((CALL) == I2C_GENERALCALL_ENABLE))
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
- ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
- ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000U))
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00U)) == 0U)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01U)) == 0U)
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
- ((REQUEST) == I2C_NEXT_FRAME) || \
- ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_i2c.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_i2s.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,491 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_i2s.h
- * @author MCD Application Team
- * @brief Header file of I2S HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_I2S_H
-#define __STM32F1xx_HAL_I2S_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup I2S
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_Mode */
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_Standard */
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_Data_Format */
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_MCLK_Output */
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_Audio_Frequency */
-
- uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
- HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
- HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
- HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
- HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
-
-}HAL_I2S_StateTypeDef;
-
-/**
- * @brief I2S handle Structure definition
- */
-typedef struct __I2S_HandleTypeDef
-{
- SPI_TypeDef *Instance; /*!< I2S registers base address */
-
- I2S_InitTypeDef Init; /*!< I2S communication parameters */
-
- uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
-
- __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
-
- __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
-
- uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
-
- __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
-
- __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
- (This field is initialized at the
- same value as transfer size at the
- beginning of the transfer and
- decremented when a sample is received
- NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
- void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
-
- DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
-
- __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
-
- __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
-
- __IO uint32_t ErrorCode; /*!< I2S Error code
- This parameter can be a value of @ref I2S_ErrorCode */
-
-}I2S_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
- * @{
- */
-/**
- * @defgroup I2S_ErrorCode I2S Error Code
- * @{
- */
-#define HAL_I2S_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_I2S_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
-#define HAL_I2S_ERROR_OVR 0x00000002U /*!< OVR error */
-#define HAL_I2S_ERROR_UDR 0x00000004U /*!< UDR error */
-#define HAL_I2S_ERROR_DMA 0x00000008U /*!< DMA transfer error */
-#define HAL_I2S_ERROR_PRESCALER 0x00000010U /*!< Prescaler Calculation error */
-/**
- * @}
- */
-
-/** @defgroup I2S_Mode I2S Mode
- * @{
- */
-#define I2S_MODE_SLAVE_TX 0x00000000U
-#define I2S_MODE_SLAVE_RX ((uint32_t)SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX ((uint32_t)SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
-/**
- * @}
- */
-
-/** @defgroup I2S_Standard I2S Standard
- * @{
- */
-#define I2S_STANDARD_PHILIPS 0x00000000U
-#define I2S_STANDARD_MSB ((uint32_t)SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB ((uint32_t)SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
-/**
- * @}
- */
-
-/** @defgroup I2S_Data_Format I2S Data Format
- * @{
- */
-#define I2S_DATAFORMAT_16B 0x00000000U
-#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
-/**
- * @}
- */
-
-/** @defgroup I2S_MCLK_Output I2S Mclk Output
- * @{
- */
-#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
- * @{
- */
-#define I2S_AUDIOFREQ_192K 192000U
-#define I2S_AUDIOFREQ_96K 96000U
-#define I2S_AUDIOFREQ_48K 48000U
-#define I2S_AUDIOFREQ_44K 44100U
-#define I2S_AUDIOFREQ_32K 32000U
-#define I2S_AUDIOFREQ_22K 22050U
-#define I2S_AUDIOFREQ_16K 16000U
-#define I2S_AUDIOFREQ_11K 11025U
-#define I2S_AUDIOFREQ_8K 8000U
-#define I2S_AUDIOFREQ_DEFAULT 2U
-/**
- * @}
- */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
- * @{
- */
-#define I2S_CPOL_LOW 0x00000000U
-#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
-/**
- * @}
- */
-
-/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
- * @{
- */
-#define I2S_IT_TXE SPI_CR2_TXEIE
-#define I2S_IT_RXNE SPI_CR2_RXNEIE
-#define I2S_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup I2S_Flags_Definition I2S Flags Definition
- * @{
- */
-#define I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_RXNE SPI_SR_RXNE
-
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define I2S_FLAG_OVR SPI_SR_OVR
-#define I2S_FLAG_FRE SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_BSY SPI_SR_BSY
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @brief Reset I2S handle state
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-
-/** @brief Enable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief Disable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief Enable the specified I2S interrupts.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief Disable the specified I2S interrupts.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the I2S Handle.
- * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
- * @param __INTERRUPT__: specifies the I2S interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
- * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
- * @arg I2S_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Checks whether the specified I2S flag is set or not.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
- * @arg I2S_FLAG_TXE: Transmit buffer empty flag
- * @arg I2S_FLAG_UDR: Underrun flag
- * @arg I2S_FLAG_OVR: Overrun flag
- * @arg I2S_FLAG_FRE: Frame error flag
- * @arg I2S_FLAG_CHSIDE: Channel Side flag
- * @arg I2S_FLAG_BSY: Busy flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clears the I2S UDR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
- * @retval None
- */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg); \
- } while(0U)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2S_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ***************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/** @addtogroup I2S_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control and State functions ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Constants I2S Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
- * @{
- */
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
- ((MODE) == I2S_MODE_SLAVE_RX) || \
- ((MODE) == I2S_MODE_MASTER_TX) || \
- ((MODE) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
- ((STANDARD) == I2S_STANDARD_MSB) || \
- ((STANDARD) == I2S_STANDARD_LSB) || \
- ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
- ((STANDARD) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
- ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
- ((FORMAT) == I2S_DATAFORMAT_24B) || \
- ((FORMAT) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
- ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
- ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
- ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
- ((CPOL) == I2S_CPOL_HIGH))
-/**
- * @}
- */
-
-/* Private Fonctions ---------------------------------------------------------*/
-/** @defgroup I2S_Private_Functions I2S Private Functions
- * @{
- */
-/* Private functions are defined in stm32f1xx_hal_i2s.c file */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_i2s.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_irda.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,597 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_irda.h
- * @author MCD Application Team
- * @brief Header file of IRDA HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_IRDA_H
-#define __STM32F1xx_HAL_IRDA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IRDA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
- * @{
- */
-
-/**
- * @brief IRDA Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (hirda->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref IRDA_Word_Length */
-
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref IRDA_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref IRDA_Transfer_Mode */
-
- uint8_t Prescaler; /*!< Specifies the Prescaler value prescaler value to be programmed
- in the IrDA low-power Baud Register, for defining pulse width on which
- burst acceptance/rejection will be decided. This value is used as divisor
- of system clock to achieve required pulse width. */
-
- uint32_t IrDAMode; /*!< Specifies the IrDA mode
- This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
-
-/**
- * @brief HAL IRDA State structures definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
- * - gState contains IRDA state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL IRDA Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_IRDA_StateTypeDef;
-
-/**
- * @brief IRDA handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
- This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< IRDA Error code */
-}IRDA_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported constants
- * @{
- */
-/** @defgroup IRDA_Error_Code IRDA Error Code
- * @{
- */
-#define HAL_IRDA_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_IRDA_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_IRDA_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_IRDA_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_IRDA_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_IRDA_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-/**
- * @}
- */
-
-/** @defgroup IRDA_Word_Length IRDA Word Length
- * @{
- */
-#define IRDA_WORDLENGTH_8B 0x00000000U
-#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup IRDA_Parity IRDA Parity
- * @{
- */
-#define IRDA_PARITY_NONE 0x00000000U
-#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
- * @{
- */
-#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power
- * @{
- */
-#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup IRDA_Flags IRDA Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define IRDA_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define IRDA_FLAG_TC ((uint32_t)USART_SR_TC)
-#define IRDA_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define IRDA_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define IRDA_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define IRDA_FLAG_NE ((uint32_t)USART_SR_NE)
-#define IRDA_FLAG_FE ((uint32_t)USART_SR_FE)
-#define IRDA_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
- * - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * @{
- */
-#define IRDA_IT_PE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define IRDA_IT_TXE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define IRDA_IT_TC ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define IRDA_IT_RXNE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define IRDA_IT_IDLE ((uint32_t)(IRDA_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define IRDA_IT_LBD ((uint32_t)(IRDA_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define IRDA_IT_CTS ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define IRDA_IT_ERR ((uint32_t)(IRDA_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
- * @{
- */
-
-/** @brief Reset IRDA handle gstate & RxState
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
- } while(0U)
-
-/** @brief Flush the IRDA DR register
- * @param __HANDLE__: specifies the USART Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief Check whether the specified IRDA flag is set or not.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IRDA_FLAG_TXE: Transmit data register empty flag
- * @arg IRDA_FLAG_TC: Transmission Complete flag
- * @arg IRDA_FLAG_RXNE: Receive data register not empty flag
- * @arg IRDA_FLAG_IDLE: Idle Line detection flag
- * @arg IRDA_FLAG_ORE: OverRun Error flag
- * @arg IRDA_FLAG_NE: Noise Error flag
- * @arg IRDA_FLAG_FE: Framing Error flag
- * @arg IRDA_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified IRDA pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg IRDA_FLAG_TC: Transmission Complete flag.
- * @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register followed by a read
- * operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
- *
- */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clear the IRDA PE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clear the IRDA FE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the IRDA NE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the IRDA ORE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the IRDA IDLE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enable the specified IRDA interrupt.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-/** @brief Disable the specified IRDA interrupt.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @arg IRDA_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == IRDA_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == IRDA_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-
-/** @brief Check whether the specified IRDA interrupt has occurred or not.
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __IT__: specifies the IRDA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
- * @arg IRDA_IT_TC: Transmission complete interrupt
- * @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
- * @arg IRDA_IT_IDLE: Idle line detection interrupt
- * @arg IRDA_IT_ERR: Error interrupt
- * @arg IRDA_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == IRDA_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == IRDA_CR2_REG_INDEX)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
-
-/** @brief Enable UART/USART associated to IRDA Handle
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief Disable UART/USART associated to IRDA Handle
- * @param __HANDLE__: specifies the IRDA Handle.
- * IRDA Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_IRDA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions
- * @{
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-
-/** @addtogroup IRDA_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants IRDA Private Constants
- * @{
- */
-
-/** @brief IRDA interruptions flag mask
- *
- */
-#define IRDA_IT_MASK 0x0000FFFFU
-
-#define IRDA_CR1_REG_INDEX 1U
-#define IRDA_CR2_REG_INDEX 2U
-#define IRDA_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros IRDA Private Macros
- * @{
- */
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
- ((LENGTH) == IRDA_WORDLENGTH_9B))
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
- ((PARITY) == IRDA_PARITY_EVEN) || \
- ((PARITY) == IRDA_PARITY_ODD))
-#define IS_IRDA_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00000000U))
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
- ((MODE) == IRDA_POWERMODE_NORMAL))
-#define IS_IRDA_BAUDRATE(BAUDRATE) ((BAUDRATE) < 115201U)
-
-#define IRDA_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define IRDA_DIVMANT(_PCLK_, _BAUD_) (IRDA_DIV((_PCLK_), (_BAUD_))/100U)
-#define IRDA_DIVFRAQ(_PCLK_, _BAUD_) (((IRDA_DIV((_PCLK_), (_BAUD_)) - (IRDA_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define IRDA_BRR(_PCLK_, _BAUD_) (((IRDA_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
- (IRDA_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup IRDA_Private_Functions IRDA Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_irda.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_iwdg.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,238 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_iwdg.h
- * @author MCD Application Team
- * @brief Header file of IWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_IWDG_H
-#define __STM32F1xx_HAL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
- * @{
- */
-
-/**
- * @brief IWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
- This parameter can be a value of @ref IWDG_Prescaler */
-
- uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-} IWDG_InitTypeDef;
-
-/**
- * @brief IWDG Handle Structure definition
- */
-typedef struct
-{
- IWDG_TypeDef *Instance; /*!< Register base address */
-
- IWDG_InitTypeDef Init; /*!< IWDG required parameters */
-
-} IWDG_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
- * @{
- */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
- * @{
- */
-#define IWDG_PRESCALER_4 0x00000000U /*!< IWDG prescaler set to 4 */
-#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
-#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
-#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
-#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
-#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the IWDG peripheral.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
- * @brief Reload IWDG counter with value defined in the reload register
- * (write access to IWDG_PR & IWDG_RLR registers disabled).
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
- * @{
- */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
- * @{
- */
-/* Initialization/Start functions ********************************************/
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
- * @{
- */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
- * @{
- */
-
-/**
- * @brief IWDG Key Register BitMask
- */
-#define IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
-#define IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
- * @{
- */
-
-/**
- * @brief Enable write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
- * @brief Disable write access to IWDG_PR and IWDG_RLR registers.
- * @param __HANDLE__ IWDG handle
- * @retval None
- */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-/**
- * @brief Check IWDG prescaler value.
- * @param __PRESCALER__ IWDG prescaler value
- * @retval None
- */
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
- ((__PRESCALER__) == IWDG_PRESCALER_8) || \
- ((__PRESCALER__) == IWDG_PRESCALER_16) || \
- ((__PRESCALER__) == IWDG_PRESCALER_32) || \
- ((__PRESCALER__) == IWDG_PRESCALER_64) || \
- ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
- ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
- * @brief Check IWDG reload value.
- * @param __RELOAD__ IWDG reload value
- * @retval None
- */
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_iwdg.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_mmc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,716 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_mmc.h
- * @author MCD Application Team
- * @brief Header file of MMC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_MMC_H
-#define __STM32F1xx_HAL_MMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup MMC MMC
- * @brief MMC HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_Types MMC Exported Types
- * @{
- */
-
-/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */
- HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */
- HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */
- HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */
- HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */
- HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */
- HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */
-}HAL_MMC_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_MMC_CARD_READY = 0x00000001U, /*!< Card state is ready */
- HAL_MMC_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
- HAL_MMC_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
- HAL_MMC_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
- HAL_MMC_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
- HAL_MMC_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
- HAL_MMC_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
- HAL_MMC_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
- HAL_MMC_CARD_ERROR = 0x000000FFU /*!< Card response Error */
-}HAL_MMC_CardStateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
- * @{
- */
-#define MMC_InitTypeDef SDIO_InitTypeDef
-#define MMC_TypeDef SDIO_TypeDef
-
-/**
- * @brief MMC Card Information Structure definition
- */
-typedef struct
-{
- uint32_t CardType; /*!< Specifies the card Type */
-
- uint32_t Class; /*!< Specifies the class of the card class */
-
- uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
- uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
-
- uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
- uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
-
- uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
-}HAL_MMC_CardInfoTypeDef;
-
-/**
- * @brief MMC handle Structure definition
- */
-typedef struct
-{
- MMC_TypeDef *Instance; /*!< MMC registers base address */
-
- MMC_InitTypeDef Init; /*!< MMC required parameters */
-
- HAL_LockTypeDef Lock; /*!< MMC locking object */
-
- uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
-
- uint32_t TxXferSize; /*!< MMC Tx Transfer size */
-
- uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
-
- uint32_t RxXferSize; /*!< MMC Rx Transfer size */
-
- __IO uint32_t Context; /*!< MMC transfer context */
-
- __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
-
- __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
-
- DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
-
- HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
-
- uint32_t CSD[4U]; /*!< MMC card specific data table */
-
- uint32_t CID[4U]; /*!< MMC card identification number table */
-
-}MMC_HandleTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t CSDStruct; /*!< CSD structure */
- __IO uint8_t SysSpecVersion; /*!< System specification version */
- __IO uint8_t Reserved1; /*!< Reserved */
- __IO uint8_t TAAC; /*!< Data read access time 1 */
- __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
- __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
- __IO uint16_t CardComdClasses; /*!< Card command classes */
- __IO uint8_t RdBlockLen; /*!< Max. read data block length */
- __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
- __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
- __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
- __IO uint8_t DSRImpl; /*!< DSR implemented */
- __IO uint8_t Reserved2; /*!< Reserved */
- __IO uint32_t DeviceSize; /*!< Device Size */
- __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
- __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
- __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
- __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
- __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
- __IO uint8_t EraseGrSize; /*!< Erase group size */
- __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
- __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
- __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
- __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
- __IO uint8_t WrSpeedFact; /*!< Write speed factor */
- __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
- __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
- __IO uint8_t Reserved3; /*!< Reserved */
- __IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
- __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
- __IO uint8_t PermWrProtect; /*!< Permanent write protection */
- __IO uint8_t TempWrProtect; /*!< Temporary write protection */
- __IO uint8_t FileFormat; /*!< File format */
- __IO uint8_t ECC; /*!< ECC code */
- __IO uint8_t CSD_CRC; /*!< CSD CRC */
- __IO uint8_t Reserved4; /*!< Always 1 */
-
-}HAL_MMC_CardCSDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
- __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
- __IO uint32_t ProdName1; /*!< Product Name part1 */
- __IO uint8_t ProdName2; /*!< Product Name part2 */
- __IO uint8_t ProdRev; /*!< Product Revision */
- __IO uint32_t ProdSN; /*!< Product Serial Number */
- __IO uint8_t Reserved1; /*!< Reserved1 */
- __IO uint16_t ManufactDate; /*!< Manufacturing Date */
- __IO uint8_t CID_CRC; /*!< CID CRC */
- __IO uint8_t Reserved2; /*!< Always 1 */
-
-}HAL_MMC_CardCIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Types_Group6 MMC Card Status returned by ACMD13
- * @{
- */
-typedef struct
-{
- __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
- __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
- __IO uint16_t CardType; /*!< Carries information about card type */
- __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
- __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
- __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
-
-}HAL_MMC_CardStatusTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Constants Exported Constants
- * @{
- */
-
-#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-#define CAPACITY 0x400000U /*!< Log Block Nuumber for 2 G bytes Cards */
-
-/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
- * @{
- */
-#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration structure
- * @{
- */
-#define MMC_CONTEXT_NONE 0x00000000U /*!< None */
-#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
- * @{
- */
-/**
- * @brief
- */
-#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
-#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
-#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
- * @{
- */
-#define MMC_HIGH_VOLTAGE_CARD 0x00000000U
-#define MMC_DUAL_VOLTAGE_CARD 0x00000001U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup MMC_Exported_macros MMC Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/**
- * @brief Enable the MMC device.
- * @retval None
- */
-#define __HAL_MMC_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the MMC device.
- * @retval None
- */
-#define __HAL_MMC_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Disable the MMC device interrupt.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified MMC flag is set or not.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval The new state of MMC FLAG (SET or RESET).
- */
-#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Clear the MMC's pending flags.
- * @param __HANDLE__: MMC Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval None
- */
-#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Check whether the specified MMC interrupt has occurred or not.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval The new state of MMC IT (SET or RESET).
- */
-#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Clear the MMC's interrupt pending bits.
- * @param __HANDLE__: MMC Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup MMC_Exported_Functions MMC Exported Functions
- * @{
- */
-
-/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
- * @{
- */
-HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
- * @{
- */
-HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
-uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
- * @{
- */
-HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
-HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup MMC_Private_Types MMC Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup MMC_Private_Defines MMC Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Variables MMC Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Constants MMC Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup MMC_Private_Macros MMC Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup MMC_Private_Functions MMC Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_mmc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_nand.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,345 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_nand.h
- * @author MCD Application Team
- * @brief Header file of NAND HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_NAND_H
-#define __STM32F1xx_HAL_NAND_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-/** @addtogroup NAND
- * @{
- */
-
-
-/* Exported typedef ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup NAND_Exported_Types NAND Exported Types
- * @{
- */
-
-/**
- * @brief HAL NAND State structures definition
- */
-typedef enum
-{
- HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
- HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
- HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
- HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
-}HAL_NAND_StateTypeDef;
-
-/**
- * @brief NAND Memory electronic signature Structure definition
- */
-typedef struct
-{
- /*<! NAND memory electronic signature maker and device IDs */
-
- uint8_t Maker_Id;
-
- uint8_t Device_Id;
-
- uint8_t Third_Id;
-
- uint8_t Fourth_Id;
-}NAND_IDTypeDef;
-
-/**
- * @brief NAND Memory address Structure definition
- */
-typedef struct
-{
- uint16_t Page; /*!< NAND memory Page address */
-
- uint16_t Plane; /*!< NAND memory Plane address */
-
- uint16_t Block; /*!< NAND memory Block address */
-
-}NAND_AddressTypeDef;
-
-/**
- * @brief NAND Memory info Structure definition
- */
-typedef struct
-{
- uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
-
- uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
-
- uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
-
- uint32_t BlockNbr; /*!< NAND memory number of total blocks */
-
- uint32_t PlaneNbr; /*!< NAND memory number of planes */
-
- uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */
-
- FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
- parameter is mandatory for some NAND parts after the read
- command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
- Example: Toshiba THTH58BYG3S0HBAI6.
- This parameter could be ENABLE or DISABLE
- Please check the Read Mode sequnece in the NAND device datasheet */
-}NAND_DeviceConfigTypeDef;
-
-/**
- * @brief NAND handle Structure definition
- */
-typedef struct
-{
- FSMC_NAND_TypeDef *Instance; /*!< Register base address */
-
- FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< NAND locking object */
-
- __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
-
- NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
-
-}NAND_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */
-
-/** @brief Reset NAND handle state
- * @param __HANDLE__: specifies the NAND handle.
- * @retval None
- */
-#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NAND_Exported_Functions NAND Exported Functions
- * @{
- */
-
-/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
-HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
-
-HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
-
-void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
-void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
-void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
- * @{
- */
-
-/* IO operation functions ****************************************************/
-
-HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
-
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
-
-/**
- * @}
- */
-
-/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-
-/* NAND Control functions ****************************************************/
-HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-
-/* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup NAND_Private_Constants
- * @{
- */
-
-#define NAND_DEVICE1 FSMC_BANK2
-#define NAND_DEVICE2 FSMC_BANK3
-#define NAND_WRITE_TIMEOUT 1000U
-
-#define CMD_AREA (1U<<16U) /* A16 = CLE high */
-#define ADDR_AREA (1U<<17U) /* A17 = ALE high */
-
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
-
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS 0x00000100U
-#define NAND_INVALID_ADDRESS 0x00000200U
-#define NAND_TIMEOUT_ERROR 0x00000400U
-#define NAND_BUSY 0x00000000U
-#define NAND_ERROR 0x00000001U
-#define NAND_READY 0x00000040U
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup NAND_Private_Macros
- * @{
- */
-
-/**
- * @brief NAND memory address computation.
- * @param __ADDRESS__: NAND memory address.
- * @param __HANDLE__ : NAND handle.
- * @retval NAND Raw address value
- */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
-
-/**
- * @brief NAND memory Column address computation.
- * @param __HANDLE__: NAND handle.
- * @retval NAND Raw address value
- */
-#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
-
-/**
- * @brief NAND memory address cycling.
- * @param __ADDRESS__: NAND memory address.
- * @retval NAND address cycling value.
- */
-#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
-
-/**
- * @brief NAND memory Columns cycling.
- * @param __ADDRESS__: NAND memory address.
- * @retval NAND Column address cycling value.
- */
-#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
-#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd Column addressing cycle */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_nand.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_nor.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,304 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_nor.h
- * @author MCD Application Team
- * @brief Header file of NOR HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_NOR_H
-#define __STM32F1xx_HAL_NOR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
-/** @addtogroup NOR
- * @{
- */
-
-/** @addtogroup NOR_Private_Constants
- * @{
- */
-
-/* NOR device IDs addresses */
-#define MC_ADDRESS ((uint16_t)0x0000)
-#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
-#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
-#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS ((uint16_t)0x10)
-#define CFI2_ADDRESS ((uint16_t)0x11)
-#define CFI3_ADDRESS ((uint16_t)0x12)
-#define CFI4_ADDRESS ((uint16_t)0x13)
-
-/* NOR operation wait timeout */
-#define NOR_TMEOUT ((uint16_t)0xFFFF)
-
-/* NOR memory data width */
-#define NOR_MEMORY_8B ((uint8_t)0x0)
-#define NOR_MEMORY_16B ((uint8_t)0x1)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1 FSMC_BANK1_1
-#define NOR_MEMORY_ADRESS2 FSMC_BANK1_2
-#define NOR_MEMORY_ADRESS3 FSMC_BANK1_3
-#define NOR_MEMORY_ADRESS4 FSMC_BANK1_4
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Private_Macros
- * @{
- */
-
-/**
- * @brief NOR memory address shifting.
- * @param __NOR_ADDRESS: NOR base address
- * @param __NOR_MEMORY_WIDTH_: NOR memory width
- * @param __ADDRESS__: NOR memory address
- * @retval NOR shifted address value
- */
-#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
- ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
- ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
- ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
-/**
- * @brief NOR memory write data to specified address.
- * @param __ADDRESS__: NOR memory address
- * @param __DATA__: Data to write
- * @retval None
- */
-#define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
-
-/**
- * @}
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup NOR_Exported_Types NOR Exported Types
- * @{
- */
-
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
- HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
- HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
- HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
- HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
-}HAL_NOR_StateTypeDef;
-
-/**
- * @brief FSMC NOR Status typedef
- */
-typedef enum
-{
- HAL_NOR_STATUS_SUCCESS = 0U,
- HAL_NOR_STATUS_ONGOING,
- HAL_NOR_STATUS_ERROR,
- HAL_NOR_STATUS_TIMEOUT
-}HAL_NOR_StatusTypeDef;
-
-/**
- * @brief FSMC NOR ID typedef
- */
-typedef struct
-{
- uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
-
- uint16_t Device_Code1;
-
- uint16_t Device_Code2;
-
- uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
- These codes can be accessed by performing read operations with specific
- control signals and addresses set.They can also be accessed by issuing
- an Auto Select command */
-}NOR_IDTypeDef;
-
-/**
- * @brief FSMC NOR CFI typedef
- */
-typedef struct
-{
- /*!< Defines the information stored in the memory's Common flash interface
- which contains a description of various electrical and timing parameters,
- density information and functions supported by the memory */
-
- uint16_t CFI_1;
-
- uint16_t CFI_2;
-
- uint16_t CFI_3;
-
- uint16_t CFI_4;
-}NOR_CFITypeDef;
-
-/**
- * @brief NOR handle Structure definition
- */
-typedef struct
-{
- FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< NOR locking object */
-
- __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
-
-}NOR_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup NOR_Exported_macro NOR Exported Macros
- * @{
- */
-
-/** @brief Reset NOR handle state
- * @param __HANDLE__: NOR handle
- * @retval None
- */
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup NOR_Exported_Functions NOR Exported Functions
- * @{
- */
-
-/** @addtogroup NOR_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group2
- * @{
- */
-
-/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group3
- * @{
- */
-
-/* NOR Control functions *****************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-
-/**
- * @}
- */
-
-/** @addtogroup NOR_Exported_Functions_Group4
- * @{
- */
-
-/* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_nor.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pccard.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,246 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_pccard.h
- * @author MCD Application Team
- * @brief Header file of PCCARD HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PCCARD_H
-#define __STM32F1xx_HAL_PCCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
-/** @addtogroup PCCARD
- * @{
- */
-
-/** @addtogroup PCCARD_Private_Constants
- * @{
- */
-
-#define PCCARD_DEVICE_ADDRESS FSMC_BANK4
-#define PCCARD_ATTRIBUTE_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x08000000U)) /* Attribute space size to @0x9BFF FFFF */
-#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
-#define PCCARD_IO_SPACE_ADDRESS ((uint32_t)(FSMC_BANK4 + 0x0C000000U)) /* IO space size to @0x9FFF FFFF */
-#define PCCARD_IO_SPACE_PRIMARY_ADDR ((uint32_t)(FSMC_BANK4 + 0x0C0001F0U)) /* IO space size to @0x9FFF FFFF */
-
-/* Compact Flash-ATA registers description */
-#define ATA_DATA ((uint8_t)0x00) /* Data register */
-#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
-#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
-#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
-#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
-#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
-#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
-#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
-#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
-#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
-
-/* Compact Flash-ATA commands */
-#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
-#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
-#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
-#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
-
-/* Compact Flash status */
-#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
-#define PCCARD_BUSY ((uint8_t)0x80)
-#define PCCARD_PROGR ((uint8_t)0x01)
-#define PCCARD_READY ((uint8_t)0x40)
-
-#define PCCARD_SECTOR_SIZE 255U /* In half words */
-
-
-/* Compact Flash redefinition */
-#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
-#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
-#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
-#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
-#define HAL_CF_Reset HAL_PCCARD_Reset
-
-#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
-#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
-
-#define CF_SUCCESS HAL_PCCARD_STATUS_SUCCESS
-#define CF_ONGOING HAL_PCCARD_STATUS_ONGOING
-#define CF_ERROR HAL_PCCARD_STATUS_ERROR
-#define CF_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
-#define CF_StatusTypedef HAL_PCCARD_StatusTypeDef
-
-#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
-#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
-#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
-#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
-#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
-
-#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
-#define CF_BUSY PCCARD_BUSY
-#define CF_PROGR PCCARD_PROGR
-#define CF_READY PCCARD_READY
-
-#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
-
-/**
- * @}
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
- * @{
- */
-
-/**
- * @brief HAL PCCARD State structures definition
- */
-typedef enum
-{
- HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
- HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
- HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
- HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
-}HAL_PCCARD_StateTypeDef;
-
-typedef enum
-{
- HAL_PCCARD_STATUS_SUCCESS = 0U,
- HAL_PCCARD_STATUS_ONGOING,
- HAL_PCCARD_STATUS_ERROR,
- HAL_PCCARD_STATUS_TIMEOUT
-}HAL_PCCARD_StatusTypeDef;
-
-/**
- * @brief FSMC_PCCARD handle Structure definition
- */
-typedef struct
-{
- FSMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
-
- FSMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
-
- __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
-
- HAL_LockTypeDef Lock; /*!< PCCARD Lock */
-
-}PCCARD_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
- * @{
- */
-
-/** @brief Reset PCCARD handle state
- * @param __HANDLE__: specifies the PCCARD handle.
- * @retval None
- */
-#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCCARD_Exported_Functions PCCARD Exported Functions
- * @{
- */
-
-/** @addtogroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FSMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FSMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
-HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
-/**
- * @}
- */
-
-/** @addtogroup PCCARD_Exported_Functions_Group2 Input Output and memory functions
- * @{
- */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
-HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
-void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
-
-/**
- * @}
- */
-
-/** @defgroup PCCARD_Exported_Functions_Group3 Peripheral State functions
- * @{
- */
-/* PCCARD State functions *******************************************************/
-HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
-HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_PCCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pccard.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pcd.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,851 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_pcd.h
- * @author MCD Application Team
- * @brief Header file of PCD HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PCD_H
-#define __STM32F1xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || \
- defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_usb.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PCD_Exported_Types PCD Exported Types
- * @{
- */
-
-/**
- * @brief PCD State structure definition
- */
-typedef enum
-{
- HAL_PCD_STATE_RESET = 0x00U,
- HAL_PCD_STATE_READY = 0x01U,
- HAL_PCD_STATE_ERROR = 0x02U,
- HAL_PCD_STATE_BUSY = 0x03U,
- HAL_PCD_STATE_TIMEOUT = 0x04U
-} PCD_StateTypeDef;
-
-#if defined (USB)
-/**
- * @brief PCD double buffered endpoint direction
- */
-typedef enum
-{
- PCD_EP_DBUF_OUT,
- PCD_EP_DBUF_IN,
- PCD_EP_DBUF_ERR,
-}PCD_EP_DBUF_DIR;
-
-/**
- * @brief PCD endpoint buffer number
- */
-typedef enum
-{
- PCD_EP_NOBUF,
- PCD_EP_BUF0,
- PCD_EP_BUF1
-}PCD_EP_BUF_NUM;
-#endif /* USB */
-
-#if defined (USB_OTG_FS)
-typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
-typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
-typedef USB_OTG_EPTypeDef PCD_EPTypeDef;
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-typedef USB_TypeDef PCD_TypeDef;
-typedef USB_CfgTypeDef PCD_InitTypeDef;
-typedef USB_EPTypeDef PCD_EPTypeDef;
-#endif /* USB */
-
-/**
- * @brief PCD Handle Structure definition
- */
-typedef struct
-{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address: not used by USB OTG FS */
- PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- uint32_t Setup[12U]; /*!< Setup packet buffer */
- void *pData; /*!< Pointer to upper stack Handler */
-} PCD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Include PCD HAL Extension module */
-#include "stm32f1xx_hal_pcd_ex.h"
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
- * @{
- */
-
-/** @defgroup PCD_Speed PCD Speed
- * @{
- */
-#define PCD_SPEED_HIGH 0U /* Not Supported */
-#define PCD_SPEED_HIGH_IN_FULL 1U /* Not Supported */
-#define PCD_SPEED_FULL 2U
-/**
- * @}
- */
-
-/** @defgroup PCD_PHY_Module PCD PHY Module
- * @{
- */
-#define PCD_PHY_EMBEDDED 2U
-/**
- * @}
- */
-
-/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
- * @{
- */
-#ifndef USBD_FS_TRDT_VALUE
- #define USBD_FS_TRDT_VALUE 5U
-#endif /* USBD_FS_TRDT_VALUE */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#if defined (USB_OTG_FS)
-
-#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
- ~(USB_OTG_PCGCCTL_STOPCLK)
-
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do{ \
- EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- } while(0U)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
- do{ \
- EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- } while(0U)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do{ \
- EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
- } while(0U)
-
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
-#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
-#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
- do{ \
- EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
- } while(0U)
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE() \
- do{ \
- EXTI->FTSR |= (USB_WAKEUP_EXTI_LINE); \
- EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
- } while(0U)
-
-#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() \
- do{ \
- EXTI->RTSR &= ~(USB_WAKEUP_EXTI_LINE); \
- EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
- EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
- EXTI->FTSR |= USB_WAKEUP_EXTI_LINE; \
- } while(0U)
-#endif /* USB */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCD_Exported_Functions PCD Exported Functions
- * @{
- */
-
-/* Initialization/de-initialization functions ********************************/
-/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* I/O operation functions ***************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2 IO operation functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* Peripheral Control functions **********************************************/
-/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/* Peripheral State functions ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
- * @{
- */
-/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
- * @{
- */
-#if defined (USB_OTG_FS)
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE 0x08U
-#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE 0x0CU
-#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE 0x10U
-
-#define USB_OTG_FS_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-#define USB_WAKEUP_EXTI_LINE 0x00040000U /*!< External interrupt line 18 Connected to the USB EXTI Line */
-#endif /* USB */
-/**
- * @}
- */
-
-#if defined (USB)
-/** @defgroup PCD_EP0_MPS PCD EP0 MPS
- * @{
- */
-#define PCD_EP0MPS_64 DEP0CTL_MPS_64
-#define PCD_EP0MPS_32 DEP0CTL_MPS_32
-#define PCD_EP0MPS_16 DEP0CTL_MPS_16
-#define PCD_EP0MPS_08 DEP0CTL_MPS_8
-/**
- * @}
- */
-
-/** @defgroup PCD_ENDP PCD ENDP
- * @{
- */
-#define PCD_ENDP0 ((uint8_t)0)
-#define PCD_ENDP1 ((uint8_t)1)
-#define PCD_ENDP2 ((uint8_t)2)
-#define PCD_ENDP3 ((uint8_t)3)
-#define PCD_ENDP4 ((uint8_t)4)
-#define PCD_ENDP5 ((uint8_t)5)
-#define PCD_ENDP6 ((uint8_t)6)
-#define PCD_ENDP7 ((uint8_t)7)
-/**
- * @}
- */
-
-/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
- * @{
- */
-#define PCD_SNG_BUF 0U
-#define PCD_DBL_BUF 1U
-/**
- * @}
- */
-#endif /* USB */
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup PCD_Private_Macros PCD Private Macros
- * @{
- */
-#if defined (USB)
-/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2U)= (uint16_t)(wRegValue))
-
-/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2U))
-
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer USB_EPStartXfer
-
-/**
- * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wType: Endpoint Type.
- * @retval None
- */
-#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
-
-/**
- * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval Endpoint Type
- */
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
-
-/**
- * @brief free buffer used from the application realizing it to the line
- toggles bit SW_BUF in the double buffered endpoint register
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param bDir: Direction
- * @retval None
- */
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
-{\
- if ((bDir) == PCD_EP_DBUF_OUT)\
- { /* OUT double buffered endpoint */\
- PCD_TX_DTOG((USBx), (bEpNum));\
- }\
- else if ((bDir) == PCD_EP_DBUF_IN)\
- { /* IN double buffered endpoint */\
- PCD_RX_DTOG((USBx), (bEpNum));\
- }\
-}
-
-/**
- * @brief gets direction of the double buffered endpoint
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval EP_DBUF_OUT, EP_DBUF_IN,
- * EP_DBUF_ERR if the endpoint counter not yet programmed.
- */
-#define PCD_GET_DB_DIR(USBx, bEpNum)\
-{\
- if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
- return(PCD_EP_DBUF_OUT);\
- else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
- return(PCD_EP_DBUF_IN);\
- else\
- return(PCD_EP_DBUF_ERR);\
-}
-
-/**
- * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wState: new state
- * @retval None
- */
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
- /* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wState))!= 0U)\
- { \
- _wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wState))!= 0U) \
- { \
- _wRegVal ^= USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));\
- } /* PCD_SET_EP_TX_STATUS */
-
-/**
- * @brief sets the status for rx transfer (bits STAT_TX[1:0])
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wState: new state
- * @retval None
- */
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
- register uint16_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
- /* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & (wState))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wState))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
- } /* PCD_SET_EP_RX_STATUS */
-
-/**
- * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wStaterx: new state.
- * @param wStatetx: new state.
- * @retval None
- */
-#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
- register uint32_t _wRegVal; \
- \
- _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
- /* toggle first bit ? */ \
- if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
- { \
- _wRegVal ^= USB_EPRX_DTOG2; \
- } \
- /* toggle first bit ? */ \
- if((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
- { \
- _wRegVal ^= USB_EPTX_DTOG1; \
- } \
- /* toggle second bit ? */ \
- if((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
- { \
- _wRegVal ^= USB_EPTX_DTOG2; \
- } \
- PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX); \
- } /* PCD_SET_EP_TXRX_STATUS */
-
-/**
- * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
- * /STAT_RX[1:0])
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval status
- */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
-
-/**
- * @brief sets directly the VALID tx/rx-status into the endpoint register
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
-
-/**
- * @brief checks stall condition in an endpoint.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval TRUE = endpoint in stall condition.
- */
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
- == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
- == USB_EP_RX_STALL)
-
-/**
- * @brief set & clear EP_KIND bit.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
-
-/**
- * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
- * @brief Sets/clears directly EP_KIND bit in the endpoint register.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
- * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
- PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
-
-/**
- * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
-#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
- USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
-
-/**
- * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0U)\
- { \
- PCD_RX_DTOG((USBx), (bEpNum)); \
- }
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0U)\
- { \
- PCD_TX_DTOG((USBx), (bEpNum)); \
- }
-
-/**
- * @brief Sets address in an endpoint register.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param bAddr: Address.
- * @retval None
- */
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
- USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
-
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U)*2U+ ((uint32_t)(USBx) + 0x400U)))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+2U)*2U+ ((uint32_t)(USBx) + 0x400U)))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+4U)*2U+ ((uint32_t)(USBx) + 0x400U)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8U+6U)*2U+ ((uint32_t)(USBx) + 0x400U)))
-
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
- uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
- }
-
-/**
- * @brief sets address of the tx/rx buffer.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wAddr: address to be set (must be word aligned).
- * @retval None
- */
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1U) << 1U))
-
-/**
- * @brief Gets address of the tx/rx buffer.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval address of the buffer.
- */
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
- * @brief Sets counter of rx buffer with no. of blocks.
- * @param dwReg: Register
- * @param wCount: Counter.
- * @param wNBlocks: no. of Blocks.
- * @retval None
- */
-#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 5U;\
- if(((wCount) & 0x1FU) == 0U)\
- { \
- (wNBlocks)--;\
- } \
- *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | 0x8000U); \
- }/* PCD_CALC_BLK32 */
-
-#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
- (wNBlocks) = (wCount) >> 1U;\
- if(((wCount) & 0x01U) != 0U)\
- { \
- (wNBlocks)++;\
- } \
- *pdwReg = (uint16_t)((wNBlocks) << 10U);\
- }/* PCD_CALC_BLK2 */
-
-#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
- uint16_t wNBlocks;\
- if((wCount) > 62U) \
- { \
- PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \
- } \
- else \
- { \
- PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \
- } \
- }/* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
- uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
- PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
- }
-
-/**
- * @brief sets counter for the tx/rx buffer.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wCount: Counter value.
- * @retval None
- */
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
-
-
-/**
- * @brief gets counter of the tx buffer.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval Counter value
- */
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3FFU)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3FFU)
-
-/**
- * @brief Sets buffer 0/1 address in a double buffer endpoint.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wBuf0Addr: buffer 0 address.
- * @retval Counter value
- */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
-
-/**
- * @brief Sets addresses in a double buffer endpoint.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param wBuf0Addr: buffer 0 address.
- * @param wBuf1Addr = buffer 1 address.
- * @retval None
- */
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
- PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
- PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
- } /* PCD_SET_EP_DBUF_ADDR */
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @param bDir: endpoint dir EP_DBUF_OUT = OUT
- * EP_DBUF_IN = IN
- * @param wCount: Counter value
- * @retval None
- */
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
- if((bDir) == PCD_EP_DBUF_OUT)\
- /* OUT endpoint */ \
- {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
- else if((bDir) == PCD_EP_DBUF_IN)\
- /* IN endpoint */ \
- *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
- } /* SetEPDblBuf0Count*/
-
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
- if((bDir) == PCD_EP_DBUF_OUT)\
- {/* OUT endpoint */ \
- PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \
- } \
- else if((bDir) == PCD_EP_DBUF_IN)\
- {/* IN endpoint */ \
- *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
- } \
- } /* SetEPDblBuf1Count */
-
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
- PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
- PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
- } /* PCD_SET_EP_DBUF_CNT */
-
-/**
- * @brief Gets buffer 0/1 rx/tx counter for double buffering.
- * @param USBx: USB peripheral instance register address.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-
-#endif /* USB */
-
-/** @defgroup PCD_Instance_definition PCD Instance definition
- * @{
- */
-#define IS_PCD_ALL_INSTANCE IS_USB_ALL_INSTANCE
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F102x6 || STM32F102xB || */
- /* STM32F103x6 || STM32F103xB || */
- /* STM32F103xE || STM32F103xG || */
- /* STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pcd.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pcd_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,114 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_pcd_ex.h
- * @author MCD Application Team
- * @brief Header file of Extended PCD HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PCD_EX_H
-#define __STM32F1xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || \
- defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PCDEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
- * @{
- */
-/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
- * @{
- */
-#if defined (USB_OTG_FS)
-HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
-HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress);
-#endif /* USB */
-/**
- * @}
- */
-
-/** @addtogroup PCDEx_Exported_Functions_Group2 Peripheral State functions
- * @{
- */
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
-/**
- * @}
- */
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F102x6 || STM32F102xB || */
- /* STM32F103x6 || STM32F103xB || */
- /* STM32F103xE || STM32F103xG || */
- /* STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pcd_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pwr.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,404 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_PWR_H
-#define __STM32F1xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
- * @{
- */
-
-/**
- * @brief PWR PVD configuration structure definition
- */
-typedef struct
-{
- uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
- This parameter can be a value of @ref PWR_PVD_detection_level */
-
- uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-
-/**
- * @}
- */
-
-
-/* Internal constants --------------------------------------------------------*/
-
-/** @addtogroup PWR_Private_Constants
- * @{
- */
-
-#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-
-/**
- * @}
- */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
- * @{
- */
-#define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
-#define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
-#define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
-#define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
-#define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
-#define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
-#define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
-#define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
-
-/**
- * @}
- */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
- * @{
- */
-#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
-
-/**
- * @}
- */
-
-
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
- * @{
- */
-
-#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
- * @{
- */
-#define PWR_MAINREGULATOR_ON 0x00000000U
-#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
-
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
- * @{
- */
-#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
- * @{
- */
-#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
-#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag PWR Flag
- * @{
- */
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @brief Check PWR flag is set or not.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
- * was received from the WKUP pin or from the RTC alarm
- * An additional wakeup event is detected if the WKUP pin is enabled
- * (by setting the EWUP bit) when the WKUP pin level is already high.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
- * resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
- * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
- * For this reason, this bit is equal to 0 after Standby or reset
- * until the PVDE bit is set.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the PWR's pending flags.
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
-
-/**
- * @brief Enable interrupt on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable interrupt on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Enable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable event on PVD Exti Line 16.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief PVD EXTI line configuration: set falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief Disable the PVD Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
- * @brief PVD EXTI line configuration: set rising edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising Trigger.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
- * @brief PVD EXTI line configuration: set rising & falling edge trigger.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-
-/**
- * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
-
-
-
-/**
- * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
- * @retval EXTI PVD Line Status.
- */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Clear the PVD EXTI flag.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None.
- */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
-/**
- * @}
- */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
- * @{
- */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
- ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
- ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
- ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
- ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
- ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
- ((MODE) == PWR_PVD_MODE_NORMAL))
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
- ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-
-/**
- * @}
- */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
- * @}
- */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-/* #define HAL_PWR_ConfigPVD 12*/
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-
-
-
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_pwr.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rcc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1393 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RCC_H
-#define __STM32F1xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
- * @{
- */
-
-/**
- * @brief RCC PLL configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLState; /*!< PLLState: The new state of the PLL.
- This parameter can be a value of @ref RCC_PLL_Config */
-
- uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
- This parameter must be a value of @ref RCC_PLL_Clock_Source */
-
- uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
- This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
-} RCC_PLLInitTypeDef;
-
-/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t ClockType; /*!< The clock to be configured.
- This parameter can be a value of @ref RCC_System_Clock_Type */
-
- uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
- This parameter can be a value of @ref RCC_System_Clock_Source */
-
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-} RCC_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
- * @{
- */
-
-#define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
- * @{
- */
-#define RCC_OSCILLATORTYPE_NONE 0x00000000U
-#define RCC_OSCILLATORTYPE_HSE 0x00000001U
-#define RCC_OSCILLATORTYPE_HSI 0x00000002U
-#define RCC_OSCILLATORTYPE_LSE 0x00000004U
-#define RCC_OSCILLATORTYPE_LSI 0x00000008U
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Config HSE Config
- * @{
- */
-#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
-#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
-#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Config LSE Config
- * @{
- */
-#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
-#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
-#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Config HSI Config
- * @{
- */
-#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
-#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
-
-#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Config LSI Config
- * @{
- */
-#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
-#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Config PLL Config
- * @{
- */
-#define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
-#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
-#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
- * @{
- */
-#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
- * @{
- */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
- * @{
- */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
- * @{
- */
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
- * @{
- */
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
- * @{
- */
-#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */
-#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
-/**
- * @}
- */
-
-
-/** @defgroup RCC_MCO_Index MCO Index
- * @{
- */
-#define RCC_MCO1 0x00000000U
-#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
-
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
- * @{
- */
-#define RCC_MCODIV_1 0x00000000U
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt Interrupts
- * @{
- */
-#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
-#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
-#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag Flags
- * Elements values convention: XXXYYYYYb
- * - YYYYY : Flag position in the register
- * - XXX : Register index
- * - 001: CR register
- * - 010: BDCR register
- * - 011: CSR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
-#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CRC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
-#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
-#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
-#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
-#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
-#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
-#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USART2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_BKP_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_PWR_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-
-#define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
-#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
-#define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-#define __HAL_RCC_AFIO_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USART1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- /* Delay after an RCC peripheral clock enabling */\
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
-#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
-#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
-#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-
-#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
-#define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-
-#define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
-#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
-#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-
-#define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
-#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
-#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
-#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
-#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-
-#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
-#define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
-#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-
-#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
- * @{
- */
-
-/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
- * @note After enabling the HSI, the application software should wait on HSIRDY
- * flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
- * (default is RCC_HSICALIBRATION_DEFAULT).
- * This parameter must be a number between 0 and 0x1F.
- */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
- (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSI_Configuration LSI Configuration
- * @{
- */
-
-/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- */
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-
-/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
- * @note LSI can not be disabled if the IWDG is running.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- */
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
- * supported by this macro. User should request a transition to HSE Off
- * first and then HSE On or HSE Bypass.
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function reset the CSSON bit, so if the clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param __STATE__ specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
- * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
- */
-#define __HAL_RCC_HSE_CONFIG(__STATE__) \
- do{ \
- if ((__STATE__) == RCC_HSE_ON) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else if ((__STATE__) == RCC_HSE_OFF) \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- else if ((__STATE__) == RCC_HSE_BYPASS) \
- { \
- SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
- SET_BIT(RCC->CR, RCC_CR_HSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
- } \
- }while(0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
- * @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
- * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param __STATE__ specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
- * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
- */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
- do{ \
- if ((__STATE__) == RCC_LSE_ON) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else if ((__STATE__) == RCC_LSE_OFF) \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- else if ((__STATE__) == RCC_LSE_BYPASS) \
- { \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- } \
- else \
- { \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
- } \
- }while(0U)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
- * @{
- */
-
-/** @brief Macro to enable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-
-/** @brief Macro to disable the main PLL.
- * @note The main PLL can not be disabled if it is used as system clock source
- */
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-/** @brief Macro to configure the main PLL clock source and multiplication factors.
- * @note This function must be used only when the main PLL is disabled.
- *
- * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
- * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
- * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
- @if STM32F105xC
- * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
- @elseif STM32F107xC
- * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
- @else
- * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
- * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
- * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
- * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
- * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
- * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
- * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
- * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
- * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
- @endif
- * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
- * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
- *
- */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
- MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
-
-/** @brief Get oscillator clock selected as PLL input clock
- * @retval The clock source used for PLL entry. The returned value can be one
- * of the following:
- * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
- * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
- */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
- * @{
- */
-
-/**
- * @brief Macro to configure the system clock source.
- * @param __SYSCLKSOURCE__ specifies the system clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
- * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
- * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
- */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
-
-/** @brief Macro to get the clock source used as system clock.
- * @retval The clock source used as system clock. The returned value can be one
- * of the following:
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
- * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
- * @{
- */
-
-#if defined(RCC_CFGR_MCO_3)
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
- */
-#else
-/** @brief Macro to configure the MCO clock.
- * @param __MCOCLKSOURCE__ specifies the MCO clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
- * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
- * @param __MCODIV__ specifies the MCO clock prescaler.
- * This parameter can be one of the following values:
- * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
- */
-#endif
-
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
-
-
-/**
- * @}
- */
-
- /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
- * @{
- */
-
-/** @brief Macro to configure the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
- * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
- * a Power On Reset (POR).
- *
- * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
- * RTC clock source).
- */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
-
-/** @brief Macro to get the RTC clock source.
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
- * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
- */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/** @brief Macro to enable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
-
-/** @brief Macro to disable the the RTC clock.
- * @note These macros must be used only after the RTC clock source was selected.
- */
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
-
-/** @brief Macro to force the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_BDCR register.
- */
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
-
-/** @brief Macros to release the Backup domain reset.
- */
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
- * @brief macros to manage the specified RCC Flags and interrupts.
- * @{
- */
-
-/** @brief Enable RCC interrupt.
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt.
- * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt
- * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief Clear the RCC's interrupt pending bits.
- * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- * @arg @ref RCC_IT_CSS Clock Security System interrupt
- */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
- * @param __INTERRUPT__ specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
- * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
- * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
- * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
- * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
- @if STM32F105xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @elsif STM32F107xx
- * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
- * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
- @endif
- * @arg @ref RCC_IT_CSS Clock Security System interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
- * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
- * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
-
-/** @brief Check RCC flag is set or not.
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
- * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
- * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
- @if STM32F105xx
- * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
- * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
- @elsif STM32F107xx
- * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
- * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
- @endif
- * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
- * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
- * @arg @ref RCC_FLAG_PINRST Pin reset.
- * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
- * @arg @ref RCC_FLAG_SFTRST Software reset.
- * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
- * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
- * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
- ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
- RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Include RCC HAL Extension module */
-#include "stm32f1xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Exported_Functions_Group2
- * @{
- */
-
-/* Peripheral Control functions ************************************************/
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void HAL_RCC_EnableCSS(void);
-void HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Private_Constants
- * @{
- */
-
-/** @defgroup RCC_Timeout RCC Timeout
- * @{
- */
-
-/* Disable Backup domain write protection state change timeout */
-#define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
-/* LSE state change timeout */
-#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
-#define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
-#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Register_Offset Register offsets
- * @{
- */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET 0x00U
-#define RCC_CFGR_OFFSET 0x04U
-#define RCC_CIR_OFFSET 0x08U
-#define RCC_BDCR_OFFSET 0x20U
-#define RCC_CSR_OFFSET 0x24U
-
-/**
- * @}
- */
-
-/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
- * @brief RCC registers bit address in the alias region
- * @{
- */
-#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
-#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
-#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
-#define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
-#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
-#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
-/* Alias word address of HSEON bit */
-#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
-#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
-#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
-#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
-#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
-
-/* Alias word address of RMVF bit */
-#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
-#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
-
-/* --- BDCR Registers ---*/
-/* Alias word address of LSEON bit */
-#define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
-#define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
-
-/* Alias word address of LSEON bit */
-#define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
-#define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
-
-/* Alias word address of RTCEN bit */
-#define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
-#define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
-
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
-#define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
-
-/**
- * @}
- */
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
-
-/* Defines used for Flags */
-#define CR_REG_INDEX ((uint8_t)1)
-#define BDCR_REG_INDEX ((uint8_t)2)
-#define CSR_REG_INDEX ((uint8_t)3)
-
-#define RCC_FLAG_MASK ((uint8_t)0x1F)
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_Private_Macros
- * @{
- */
-/** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
- * @{
- */
-#define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-/**
- * @}
- */
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
- ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
- (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
- ((__HSE__) == RCC_HSE_BYPASS))
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
- ((__LSE__) == RCC_LSE_BYPASS))
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
- ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
- (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
- (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
- ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
- ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
- ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
- ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
- ((__HCLK__) == RCC_SYSCLK_DIV512))
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
- ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
- ((__PCLK__) == RCC_HCLK_DIV16))
-#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
- ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rcc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rcc_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1924 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rcc_ex.h
- * @author MCD Application Team
- * @brief Header file of RCC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RCC_EX_H
-#define __STM32F1xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RCCEx
- * @{
- */
-
-/** @addtogroup RCCEx_Private_Constants
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Alias word address of PLLI2SON bit */
-#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos
-#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
-/* Alias word address of PLL2ON bit */
-#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos
-#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))
-
-#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */
-#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-
-#define CR_REG_INDEX ((uint8_t)1)
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Private_Macros
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
- ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
- ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
-
-#else
-#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
- ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
- ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
- ((__MUL__) == RCC_PLL_MUL6_5))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-
-#else
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
- ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
- ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
- ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
- ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
- ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
- ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
- ((__MUL__) == RCC_PLL_MUL16))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
- || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-
-#endif /* STM32F105xC || STM32F107xC*/
-
-#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
- ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
-
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
-
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
-
-#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
- ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
- ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
- ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
- ((__MUL__) == RCC_PLLI2S_MUL20))
-
-#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
- ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
-
-#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
- ((__PLL__) == RCC_PLL2_ON))
-
-#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
- ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
- ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
- ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
- ((__MUL__) == RCC_PLL2_MUL20))
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
-
-#elif defined(STM32F103xE) || defined(STM32F103xG)
-
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
-
-#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
- (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
-
-
-#elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB)
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
-
-#else
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
- ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
- (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-
-#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/**
- * @brief RCC PLL2 configuration structure definition
- */
-typedef struct
-{
- uint32_t PLL2State; /*!< The new state of the PLL2.
- This parameter can be a value of @ref RCCEx_PLL2_Config */
-
- uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
- This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
- This parameter can be a value of @ref RCCEx_Prediv2_Factor */
-
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_PLL2InitTypeDef;
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
- */
-typedef struct
-{
- uint32_t OscillatorType; /*!< The oscillators to be configured.
- This parameter can be a value of @ref RCC_Oscillator_Type */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t Prediv1Source; /*!< The Prediv1 source value.
- This parameter can be a value of @ref RCCEx_Prediv1_Source */
-#endif /* STM32F105xC || STM32F107xC */
-
- uint32_t HSEState; /*!< The new state of the HSE.
- This parameter can be a value of @ref RCC_HSE_Config */
-
- uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
- This parameter can be a value of @ref RCCEx_Prediv1_Factor */
-
- uint32_t LSEState; /*!< The new state of the LSE.
- This parameter can be a value of @ref RCC_LSE_Config */
-
- uint32_t HSIState; /*!< The new state of the HSI.
- This parameter can be a value of @ref RCC_HSI_Config */
-
- uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
- uint32_t LSIState; /*!< The new state of the LSI.
- This parameter can be a value of @ref RCC_LSI_Config */
-
- RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_OscInitTypeDef;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/**
- * @brief RCC PLLI2S configuration structure definition
- */
-typedef struct
-{
- uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
- This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
- This parameter can be a value of @ref RCCEx_Prediv2_Factor */
-
-#endif /* STM32F105xC || STM32F107xC */
-} RCC_PLLI2SInitTypeDef;
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @brief RCC extended clocks structure definition
- */
-typedef struct
-{
- uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
- This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
- uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
- This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
- uint32_t AdcClockSelection; /*!< ADC clock source
- This parameter can be a value of @ref RCCEx_ADC_Prescaler */
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
- uint32_t I2s2ClockSelection; /*!< I2S2 clock source
- This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
-
- uint32_t I2s3ClockSelection; /*!< I2S3 clock source
- This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
- This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
-
-#endif /* STM32F105xC || STM32F107xC */
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t UsbClockSelection; /*!< USB clock source
- This parameter can be a value of @ref RCCEx_USB_Prescaler */
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-} RCC_PeriphCLKInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
- * @{
- */
-
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
- * @{
- */
-#define RCC_PERIPHCLK_RTC 0x00000001U
-#define RCC_PERIPHCLK_ADC 0x00000002U
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define RCC_PERIPHCLK_I2S2 0x00000004U
-#define RCC_PERIPHCLK_I2S3 0x00000008U
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PERIPHCLK_USB 0x00000010U
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
- * @{
- */
-#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
-#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
-#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
-#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
-
-/**
- * @}
- */
-
-#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
- * @{
- */
-#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
- * @{
- */
-#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler
- * @{
- */
-#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
-#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U
-
-/**
- * @}
- */
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_USB_Prescaler USB Prescaler
- * @{
- */
-#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
-#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
- * @{
- */
-
-#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
-#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
-#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
-#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
-#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
-#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
-#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
-#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
-#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
- * @{
- */
-
-#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
-#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
- * @{
- */
-
-#define RCC_HSE_PREDIV_DIV1 0x00000000U
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
-#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
-#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
-#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
-#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
-#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
-#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
-#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
-#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
-#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
-#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
-#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
-#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
-#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
-#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
-#else
-#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
- * @{
- */
-
-#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
-#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
-#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
-#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
-#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
-#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
-#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
-#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
-#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
-#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
-#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
-#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
-#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
-#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
-#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
-#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_PLL2_Config PLL Config
- * @{
- */
-#define RCC_PLL2_NONE 0x00000000U
-#define RCC_PLL2_OFF 0x00000001U
-#define RCC_PLL2_ON 0x00000002U
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
- * @{
- */
-
-#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
-#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
-#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
-#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
-#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
-#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
-#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
-#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
-#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#else
-#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
-#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
-#endif /* STM32F105xC || STM32F107xC */
-#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
-#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
-#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
-#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
-#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
-#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
-#else
-#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
-#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
-#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
-#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
-#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
-#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
-#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
- * @{
- */
-#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
-#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
-#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
-#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
-#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
-#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
-#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
-#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
-#endif /* STM32F105xC || STM32F107xC*/
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Interrupt RCCEx Interrupt
- * @{
- */
-#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
-#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
-/**
- * @}
- */
-
-/** @defgroup RCCEx_Flag RCCEx Flag
- * Elements values convention: 0XXYYYYYb
- * - YYYYY : Flag position in the register
- * - XX : Register index
- * - 01: CR register
- * @{
- */
-/* Flags in the CR register */
-#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos))
-#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos))
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC*/
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
- * @brief Enable or disable the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
- || defined (STM32F100xE)
-#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined (STM32F100xE)
-#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-
-#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
-#endif /* STM32F105xC || STM32F107xC*/
-
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
-
-/**
- * @brief Enable ETHERNET clock.
- */
-#define __HAL_RCC_ETH_CLK_ENABLE() do { \
- __HAL_RCC_ETHMAC_CLK_ENABLE(); \
- __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
- __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
- } while(0U)
-/**
- * @brief Disable ETHERNET clock.
- */
-#define __HAL_RCC_ETH_CLK_DISABLE() do { \
- __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
- __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
- __HAL_RCC_ETHMAC_CLK_DISABLE(); \
- } while(0U)
-
-#endif /* STM32F107xC*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the AHB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
- || defined (STM32F100xE)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined (STM32F100xE)
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
-#endif /* STM32F103xE || STM32F103xG */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
-#endif /* STM32F105xC || STM32F107xC*/
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
-#endif /* STM32F107xC*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
- * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined (STM32F100xE)
-#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_DAC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CEC_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#endif /* STM32F100xB || STM32F100xE */
-
-#ifdef STM32F100xE
-#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART4_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_UART5_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#endif /* STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB1 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
-#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F100xB) || defined (STM32F100xE)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
-#endif /* STM32F100xB || STM32F100xE */
-#ifdef STM32F100xE
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#endif /* STM32F100xE */
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#endif /* STM32F105xC || STM32F107xC */
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
- * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
-#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
-#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
-#endif /* STM32F100xE */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
- __IO uint32_t tmpreg; \
- SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
- /* Delay after an RCC peripheral clock enabling */ \
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
- UNUSED(tmpreg); \
- } while(0U)
-
-#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
- * @brief Get the enable or disable status of the APB2 peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @{
- */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
-#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
-#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
-#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
-#endif /* STM32F100xB || STM32F100xE */
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-#endif /* STM32F103xE || STM32F103xG */
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
-#endif /* STM32F100xE */
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
- * @brief Force or release AHB peripheral reset.
- * @{
- */
-#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
-#endif /* STM32F107xC */
-
-#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
-#if defined(STM32F107xC)
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
-#endif /* STM32F107xC */
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
- * @brief Force or release APB1 peripheral reset.
- * @{
- */
-
-#if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
- || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
-#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-
-#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
- || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
- || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-
-#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F100xB) || defined (STM32F100xE)
-#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-
-#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined (STM32F100xE)
-#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-
-#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#endif /* STM32F100xE */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-
-#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-
-#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#endif /* STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
- * @brief Force or release APB2 peripheral reset.
- * @{
- */
-
-#if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
- || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
- || defined(STM32F103xG)
-#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
-
-#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
-#endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
-#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
-
-#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
-#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
-#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
-#endif /* STM32F100xB || STM32F100xE */
-
-#if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
- || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
- || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
- || defined(STM32F107xC)
-#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
-
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
-#endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
-
-#if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
- || defined(STM32F103xG)
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
-
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
-#endif /* STM32F103xE || STM32F103xG */
-
-#if defined(STM32F100xE)
-#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
-
-#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
-#endif /* STM32F100xE */
-
-#if defined(STM32F101xG) || defined(STM32F103xG)
-#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-
-#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-#endif /* STM32F101xG || STM32F103xG*/
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_HSE_Configuration HSE Configuration
- * @{
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
- * @note Predivision factor can not be changed if PLL is used as system clock
- * In this case, you have to select another source of the system clock, disable the PLL and
- * then change the HSE predivision factor.
- * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
- * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
- */
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
-#else
-/**
- * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
- * @note Predivision factor can not be changed if PLL is used as system clock
- * In this case, you have to select another source of the system clock, disable the PLL and
- * then change the HSE predivision factor.
- * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
- * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
- */
-#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
- MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
- || defined(STM32F100xE)
-/**
- * @brief Macro to get prediv1 factor for PLL.
- */
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
-
-#else
-/**
- * @brief Macro to get prediv1 factor for PLL.
- */
-#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
-
-#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
- * @{
- */
-
-/** @brief Macros to enable the main PLLI2S.
- * @note After enabling the main PLLI2S, the application software should wait on
- * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
- * be used as system clock source.
- * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
-
-/** @brief Macros to disable the main PLLI2S.
- * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
-
-/** @brief macros to configure the main PLLI2S multiplication factor.
- * @note This function must be used only when the main PLLI2S is disabled.
- *
- * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
- * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
- * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
- * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
- * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
- * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
- * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
- * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
- * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
- *
- */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
- * @brief Macros to configure clock source of different peripherals.
- * @{
- */
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
- || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
-/** @brief Macro to configure the USB clock.
- * @param __USBCLKSOURCE__ specifies the USB clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
- */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
-
-/** @brief Macro to get the USB clock (USBCLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
-
-#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @brief Macro to configure the USB OTSclock.
- * @param __USBCLKSOURCE__ specifies the USB clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
- */
-#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
-
-/** @brief Macro to get the USB clock (USBCLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
- * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
- */
-#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
-
-#endif /* STM32F105xC || STM32F107xC */
-
-/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
- * @param __ADCCLKSOURCE__ specifies the ADC clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
- */
-#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
-
-/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
- * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
- */
-#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-
-/** @addtogroup RCCEx_HSE_Configuration
- * @{
- */
-
-/**
- * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
- * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
- * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
- * then change the PREDIV2 factor.
- * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
- * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
- */
-#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
-
-/**
- * @brief Macro to get prediv2 factor for PLL2 & PLL3.
- */
-#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_PLLI2S_Configuration
- * @{
- */
-
-/** @brief Macros to enable the main PLL2.
- * @note After enabling the main PLL2, the application software should wait on
- * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
- * be used as system clock source.
- * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
-
-/** @brief Macros to disable the main PLL2.
- * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
- * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
- */
-#define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
-
-/** @brief macros to configure the main PLL2 multiplication factor.
- * @note This function must be used only when the main PLL2 is disabled.
- *
- * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
- * This parameter can be one of the following values:
- * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
- * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
- * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
- * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
- * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
- * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
- * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
- * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
- * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
- *
- */
-#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
-
-/**
- * @}
- */
-
-/** @defgroup RCCEx_I2S_Configuration I2S Configuration
- * @brief Macros to configure clock source of I2S peripherals.
- * @{
- */
-
-/** @brief Macro to configure the I2S2 clock.
- * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
-
-/** @brief Macro to get the I2S2 clock (I2S2CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
-
-/** @brief Macro to configure the I2S3 clock.
- * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
- * This parameter can be one of the following values:
- * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
-
-/** @brief Macro to get the I2S3 clock (I2S3CLK).
- * @retval The clock source can be one of the following values:
- * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
- * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
- */
-#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
-
-/**
- * @}
- */
-
-#endif /* STM32F105xC || STM32F107xC */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
- * @{
- */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
- * @}
- */
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
-/** @addtogroup RCCEx_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
-
-/**
- * @}
- */
-
-/** @addtogroup RCCEx_Exported_Functions_Group3
- * @{
- */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
-
-/**
- * @}
- */
-#endif /* STM32F105xC || STM32F107xC */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rcc_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rtc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,579 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rtc.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RTC_H
-#define __STM32F1xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/** @addtogroup RTC_Private_Macros
- * @{
- */
-
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) (((PREDIV) <= 0xFFFFFU) || ((PREDIV) == RTC_AUTO_1_SECOND))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
-#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_ALARM_A)
-#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUTSOURCE_NONE) || \
- ((__OUTPUT__) == RTC_OUTPUTSOURCE_CALIBCLOCK) || \
- ((__OUTPUT__) == RTC_OUTPUTSOURCE_ALARM) || \
- ((__OUTPUT__) == RTC_OUTPUTSOURCE_SECOND))
-
-
-/**
- * @}
- */
-
-/** @addtogroup RTC_Private_Constants
- * @{
- */
-/** @defgroup RTC_Timeout_Value Default Timeout Value
- * @{
- */
-#define RTC_TIMEOUT_VALUE 1000U
-/**
- * @}
- */
-
-/** @defgroup RTC_EXTI_Line_Event RTC EXTI Line event
- * @{
- */
-#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
- * @{
- */
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
-
- uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
-
- uint32_t Alarm; /*!< Specifies the alarm ID (only 1 alarm ID for STM32F1).
- This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
- HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
- HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
- HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
- HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
-
-}HAL_RTCStateTypeDef;
-
-/**
- * @brief RTC Configuration Structure definition
- */
-typedef struct
-{
- uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF or RTC_AUTO_1_SECOND
- If RTC_AUTO_1_SECOND is selected, AsynchPrediv will be set automatically to get 1sec timebase */
-
- uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC Tamper pin.
- This parameter can be a value of @ref RTC_output_source_to_output_on_the_Tamper_pin */
-
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay (not necessary for HAL_RTC_SetDate).
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t Date; /*!< Specifies the RTC Date.
- This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
- uint8_t Year; /*!< Specifies the RTC Date Year.
- This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-}RTC_DateTypeDef;
-
-/**
- * @brief Time Handle Structure definition
- */
-typedef struct
-{
- RTC_TypeDef *Instance; /*!< Register base address */
-
- RTC_InitTypeDef Init; /*!< RTC required parameters */
-
- RTC_DateTypeDef DateToUpdate; /*!< Current date set by user and updated automatically */
-
- HAL_LockTypeDef Lock; /*!< RTC locking object */
-
- __IO HAL_RTCStateTypeDef State; /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
- * @{
- */
-
-/** @defgroup RTC_Automatic_Prediv_1_Second Automatic calculation of prediv for 1sec timebase
- * @{
- */
-#define RTC_AUTO_1_SECOND 0xFFFFFFFFU
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
- * @{
- */
-#define RTC_FORMAT_BIN 0x000000000U
-#define RTC_FORMAT_BCD 0x000000001U
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions Month Definitions
- * @{
- */
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
-#define RTC_MONTH_MARCH ((uint8_t)0x03)
-#define RTC_MONTH_APRIL ((uint8_t)0x04)
-#define RTC_MONTH_MAY ((uint8_t)0x05)
-#define RTC_MONTH_JUNE ((uint8_t)0x06)
-#define RTC_MONTH_JULY ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions
- * @{
- */
-#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x00)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions Alarms Definitions
- * @{
- */
-#define RTC_ALARM_A 0U /*!< Specify alarm ID (mainly for legacy purposes) */
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin Output source to output on the Tamper pin
- * @{
- */
-
-#define RTC_OUTPUTSOURCE_NONE 0x00000000U /*!< No output on the TAMPER pin */
-#define RTC_OUTPUTSOURCE_CALIBCLOCK BKP_RTCCR_CCO /*!< RTC clock with a frequency divided by 64 on the TAMPER pin */
-#define RTC_OUTPUTSOURCE_ALARM BKP_RTCCR_ASOE /*!< Alarm pulse signal on the TAMPER pin */
-#define RTC_OUTPUTSOURCE_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Second pulse signal on the TAMPER pin */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions
- * @{
- */
-#define RTC_IT_OW RTC_CRH_OWIE /*!< Overflow interrupt */
-#define RTC_IT_ALRA RTC_CRH_ALRIE /*!< Alarm interrupt */
-#define RTC_IT_SEC RTC_CRH_SECIE /*!< Second interrupt */
-#define RTC_IT_TAMP1 BKP_CSR_TPIE /*!< TAMPER Pin interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions Flags Definitions
- * @{
- */
-#define RTC_FLAG_RTOFF RTC_CRL_RTOFF /*!< RTC Operation OFF flag */
-#define RTC_FLAG_RSF RTC_CRL_RSF /*!< Registers Synchronized flag */
-#define RTC_FLAG_OW RTC_CRL_OWF /*!< Overflow flag */
-#define RTC_FLAG_ALRAF RTC_CRL_ALRF /*!< Alarm flag */
-#define RTC_FLAG_SEC RTC_CRL_SECF /*!< Second flag */
-#define RTC_FLAG_TAMP1F BKP_CSR_TEF /*!< Tamper Interrupt Flag */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_macros RTC Exported Macros
- * @{
- */
-
-/** @brief Reset RTC handle state
- * @param __HANDLE__: RTC handle.
- * @retval None
- */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-
-/**
- * @brief Disable the write protection for RTC registers.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
-
-/**
- * @brief Enable the write protection for RTC registers.
- * @param __HANDLE__: specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CRL, RTC_CRL_CNF)
-
-/**
- * @brief Enable the RTC Alarm interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Alarm interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be checked
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Alarm's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Check whether the specified RTC Alarm interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
- * This parameter can be:
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @retval None
- */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CRL) & (__INTERRUPT__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Alarm's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_ALRAF
- * @retval None
- */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
-
-/**
- * @brief Enable interrupt on ALARM Exti Line 17.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable interrupt on ALARM Exti Line 17.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Enable event on ALARM Exti Line 17.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable event on ALARM Exti Line 17.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RTC_EXTI_LINE_ALARM_EVENT)
-
-
-/**
- * @brief ALARM EXTI line configuration: set falling edge trigger.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-
-/**
- * @brief Disable the ALARM Extended Interrupt Falling Trigger.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-
-/**
- * @brief ALARM EXTI line configuration: set rising edge trigger.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief Disable the ALARM Extended Interrupt Rising Trigger.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RTC_EXTI_LINE_ALARM_EVENT)
-
-/**
- * @brief ALARM EXTI line configuration: set rising & falling edge trigger.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \
-do{ \
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Disable the ALARM Extended Interrupt Rising & Falling Trigger.
- * This parameter can be:
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \
-do{ \
- __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
-
-/**
- * @brief Check whether the specified ALARM EXTI interrupt flag is set or not.
- * @retval EXTI ALARM Line Status.
- */
-#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & (RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Clear the ALARM EXTI flag.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = (RTC_EXTI_LINE_ALARM_EVENT))
-
-/**
- * @brief Generate a Software interrupt on selected EXTI line.
- * @retval None.
- */
-#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RTC_EXTI_LINE_ALARM_EVENT)
-/**
- * @}
- */
-
-/* Include RTC HAL Extension module */
-#include "stm32f1xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
- * @{
- */
-
-
-/* Initialization and de-initialization functions ****************************/
-/** @addtogroup RTC_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/* RTC Time and Date functions ************************************************/
-/** @addtogroup RTC_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-
-uint32_t RTC_ReadTimeCounter(RTC_HandleTypeDef* hrtc);
-HAL_StatusTypeDef RTC_WriteTimeCounter(RTC_HandleTypeDef* hrtc, uint32_t TimeCounter);
-/**
- * @}
- */
-
-/* RTC Alarm functions ********************************************************/
-/** @addtogroup RTC_Exported_Functions_Group3
- * @{
- */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup RTC_Exported_Functions_Group4
- * @{
- */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
- * @}
- */
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup RTC_Exported_Functions_Group5
- * @{
- */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rtc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rtc_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,428 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_rtc_ex.h
- * @author MCD Application Team
- * @brief Header file of RTC HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_RTC_EX_H
-#define __STM32F1xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup RTCEx
- * @{
- */
-
-/** @addtogroup RTCEx_Private_Macros
- * @{
- */
-
-/** @defgroup RTCEx_Alias_For_Legacy Alias define maintained for legacy
- * @{
- */
-#define HAL_RTCEx_TamperTimeStampIRQHandler HAL_RTCEx_TamperIRQHandler
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
- * @{
- */
-#define IS_RTC_TAMPER(__TAMPER__) ((__TAMPER__) == RTC_TAMPER_1)
-
-#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
- ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-
-#if RTC_BKP_NUMBER > 10U
-#define IS_RTC_BKP(BKP) (((BKP) <= (uint32_t)RTC_BKP_DR10) || (((BKP) >= (uint32_t)RTC_BKP_DR11) && ((BKP) <= (uint32_t)RTC_BKP_DR42)))
-#else
-#define IS_RTC_BKP(BKP) ((BKP) <= (uint32_t)RTC_BKP_NUMBER)
-#endif
-#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= 0x0000007FU)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
- * @{
- */
-/**
- * @brief RTC Tamper structure definition
- */
-typedef struct
-{
- uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
-
- uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
-
-}RTC_TamperTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
- * @{
- */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
- * @{
- */
-#define RTC_TAMPER_1 BKP_CR_TPE /*!< Select tamper to be enabled (mainly for legacy purposes) */
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions
- * @{
- */
-#define RTC_TAMPERTRIGGER_LOWLEVEL BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
-#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x00000000U /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
-
-/**
- * @}
- */
-
-/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions
- * @{
- */
-#if RTC_BKP_NUMBER > 0U
-#define RTC_BKP_DR1 0x00000001U
-#define RTC_BKP_DR2 0x00000002U
-#define RTC_BKP_DR3 0x00000003U
-#define RTC_BKP_DR4 0x00000004U
-#define RTC_BKP_DR5 0x00000005U
-#define RTC_BKP_DR6 0x00000006U
-#define RTC_BKP_DR7 0x00000007U
-#define RTC_BKP_DR8 0x00000008U
-#define RTC_BKP_DR9 0x00000009U
-#define RTC_BKP_DR10 0x0000000AU
-#endif /* RTC_BKP_NUMBER > 0 */
-
-#if RTC_BKP_NUMBER > 10U
-#define RTC_BKP_DR11 0x00000010U
-#define RTC_BKP_DR12 0x00000011U
-#define RTC_BKP_DR13 0x00000012U
-#define RTC_BKP_DR14 0x00000013U
-#define RTC_BKP_DR15 0x00000014U
-#define RTC_BKP_DR16 0x00000015U
-#define RTC_BKP_DR17 0x00000016U
-#define RTC_BKP_DR18 0x00000017U
-#define RTC_BKP_DR19 0x00000018U
-#define RTC_BKP_DR20 0x00000019U
-#define RTC_BKP_DR21 0x0000001AU
-#define RTC_BKP_DR22 0x0000001BU
-#define RTC_BKP_DR23 0x0000001CU
-#define RTC_BKP_DR24 0x0000001DU
-#define RTC_BKP_DR25 0x0000001EU
-#define RTC_BKP_DR26 0x0000001FU
-#define RTC_BKP_DR27 0x00000020U
-#define RTC_BKP_DR28 0x00000021U
-#define RTC_BKP_DR29 0x00000022U
-#define RTC_BKP_DR30 0x00000023U
-#define RTC_BKP_DR31 0x00000024U
-#define RTC_BKP_DR32 0x00000025U
-#define RTC_BKP_DR33 0x00000026U
-#define RTC_BKP_DR34 0x00000027U
-#define RTC_BKP_DR35 0x00000028U
-#define RTC_BKP_DR36 0x00000029U
-#define RTC_BKP_DR37 0x0000002AU
-#define RTC_BKP_DR38 0x0000002BU
-#define RTC_BKP_DR39 0x0000002CU
-#define RTC_BKP_DR40 0x0000002DU
-#define RTC_BKP_DR41 0x0000002EU
-#define RTC_BKP_DR42 0x0000002FU
-#endif /* RTC_BKP_NUMBER > 10 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
- * @{
- */
-
-/**
- * @brief Enable the RTC Tamper interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be enabled
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP1: Tamper A interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(BKP->CSR, (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Tamper interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TAMP1: Tamper A interrupt
- * @retval None
- */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(BKP->CSR, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
- * This parameter can be:
- * @arg RTC_IT_TAMP1
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & ((__INTERRUPT__))) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((BKP->CSR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt sources to be checked.
- * This parameter can be:
- * @arg RTC_IT_TAMP1
- * @retval None
- */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((BKP->CSR) & (BKP_CSR_TEF)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_TAMP1F
- * @retval None
- */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(BKP->CSR, BKP_CSR_CTE | BKP_CSR_CTI)
-
-/**
- * @brief Enable the RTC Second interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_SEC: Second A interrupt
- * @retval None
- */
-#define __HAL_RTC_SECOND_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Second interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_SEC: Second A interrupt
- * @retval None
- */
-#define __HAL_RTC_SECOND_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Second interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Second interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_SEC: Second A interrupt
- * @retval None
- */
-#define __HAL_RTC_SECOND_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__)))) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Second's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_SEC
- * @retval None
- */
-#define __HAL_RTC_SECOND_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Second's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Second Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_SEC
- * @retval None
- */
-#define __HAL_RTC_SECOND_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
-
-/**
- * @brief Enable the RTC Overflow interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_OW: Overflow A interrupt
- * @retval None
- */
-#define __HAL_RTC_OVERFLOW_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
- * @brief Disable the RTC Overflow interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_OW: Overflow A interrupt
- * @retval None
- */
-#define __HAL_RTC_OVERFLOW_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CRH, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified RTC Overflow interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Overflow interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_IT_OW: Overflow A interrupt
- * @retval None
- */
-#define __HAL_RTC_OVERFLOW_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->CRH)& ((__INTERRUPT__))) ) != RESET)? SET : RESET)
-
-/**
- * @brief Get the selected RTC Overflow's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_OW
- * @retval None
- */
-#define __HAL_RTC_OVERFLOW_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->CRL) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
- * @brief Clear the RTC Overflow's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Overflow Flag sources to be enabled or disabled.
- * This parameter can be:
- * @arg RTC_FLAG_OW
- * @retval None
- */
-#define __HAL_RTC_OVERFLOW_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CRL) = ~(__FLAG__)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
- * @{
- */
-
-/* RTC Tamper functions *****************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-
-/**
- * @}
- */
-
-/* RTC Second functions *****************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef HAL_RTCEx_SetSecond_IT(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateSecond(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_RTCIRQHandler(RTC_HandleTypeDef* hrtc);
-void HAL_RTCEx_RTCEventCallback(RTC_HandleTypeDef *hrtc);
-void HAL_RTCEx_RTCEventErrorCallback(RTC_HandleTypeDef *hrtc);
-
-/**
- * @}
- */
-
-/* Extension Control functions ************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group3
- * @{
- */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_rtc_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_sd.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,715 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_sd.h
- * @author MCD Application Team
- * @brief Header file of SD HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SD_H
-#define __STM32F1xx_HAL_SD_H
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_sdmmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @defgroup SD SD
- * @brief SD HAL module driver
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SD_Exported_Types SD Exported Types
- * @{
- */
-
-/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */
- HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */
- HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */
- HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */
- HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */
- HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receinving State */
- HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */
- HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */
-}HAL_SD_StateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
- * @{
- */
-typedef enum
-{
- HAL_SD_CARD_READY = 0x00000001U, /*!< Card state is ready */
- HAL_SD_CARD_IDENTIFICATION = 0x00000002U, /*!< Card is in identification state */
- HAL_SD_CARD_STANDBY = 0x00000003U, /*!< Card is in standby state */
- HAL_SD_CARD_TRANSFER = 0x00000004U, /*!< Card is in transfer state */
- HAL_SD_CARD_SENDING = 0x00000005U, /*!< Card is sending an operation */
- HAL_SD_CARD_RECEIVING = 0x00000006U, /*!< Card is receiving operation information */
- HAL_SD_CARD_PROGRAMMING = 0x00000007U, /*!< Card is in programming state */
- HAL_SD_CARD_DISCONNECTED = 0x00000008U, /*!< Card is disconnected */
- HAL_SD_CARD_ERROR = 0x000000FFU /*!< Card response Error */
-}HAL_SD_CardStateTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
- * @{
- */
-#define SD_InitTypeDef SDIO_InitTypeDef
-#define SD_TypeDef SDIO_TypeDef
-
-/**
- * @brief SD Card Information Structure definition
- */
-typedef struct
-{
- uint32_t CardType; /*!< Specifies the card Type */
-
- uint32_t CardVersion; /*!< Specifies the card version */
-
- uint32_t Class; /*!< Specifies the class of the card class */
-
- uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
-
- uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
-
- uint32_t BlockSize; /*!< Specifies one block size in bytes */
-
- uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
-
- uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
-
-}HAL_SD_CardInfoTypeDef;
-
-/**
- * @brief SD handle Structure definition
- */
-typedef struct
-{
- SD_TypeDef *Instance; /*!< SD registers base address */
-
- SD_InitTypeDef Init; /*!< SD required parameters */
-
- HAL_LockTypeDef Lock; /*!< SD locking object */
-
- uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
-
- uint32_t TxXferSize; /*!< SD Tx Transfer size */
-
- uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
-
- uint32_t RxXferSize; /*!< SD Rx Transfer size */
-
- __IO uint32_t Context; /*!< SD transfer context */
-
- __IO HAL_SD_StateTypeDef State; /*!< SD card State */
-
- __IO uint32_t ErrorCode; /*!< SD Card Error codes */
-
- DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */
-
- DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */
-
- HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
-
- uint32_t CSD[4]; /*!< SD card specific data table */
-
- uint32_t CID[4]; /*!< SD card identification number table */
-
-}SD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t CSDStruct; /*!< CSD structure */
- __IO uint8_t SysSpecVersion; /*!< System specification version */
- __IO uint8_t Reserved1; /*!< Reserved */
- __IO uint8_t TAAC; /*!< Data read access time 1 */
- __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
- __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
- __IO uint16_t CardComdClasses; /*!< Card command classes */
- __IO uint8_t RdBlockLen; /*!< Max. read data block length */
- __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
- __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
- __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
- __IO uint8_t DSRImpl; /*!< DSR implemented */
- __IO uint8_t Reserved2; /*!< Reserved */
- __IO uint32_t DeviceSize; /*!< Device Size */
- __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
- __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
- __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
- __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
- __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
- __IO uint8_t EraseGrSize; /*!< Erase group size */
- __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
- __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
- __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
- __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
- __IO uint8_t WrSpeedFact; /*!< Write speed factor */
- __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
- __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
- __IO uint8_t Reserved3; /*!< Reserved */
- __IO uint8_t ContentProtectAppli; /*!< Content protection application */
- __IO uint8_t FileFormatGrouop; /*!< File format group */
- __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
- __IO uint8_t PermWrProtect; /*!< Permanent write protection */
- __IO uint8_t TempWrProtect; /*!< Temporary write protection */
- __IO uint8_t FileFormat; /*!< File format */
- __IO uint8_t ECC; /*!< ECC code */
- __IO uint8_t CSD_CRC; /*!< CSD CRC */
- __IO uint8_t Reserved4; /*!< Always 1 */
-
-}HAL_SD_CardCSDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
- * @{
- */
-typedef struct
-{
- __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
- __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
- __IO uint32_t ProdName1; /*!< Product Name part1 */
- __IO uint8_t ProdName2; /*!< Product Name part2 */
- __IO uint8_t ProdRev; /*!< Product Revision */
- __IO uint32_t ProdSN; /*!< Product Serial Number */
- __IO uint8_t Reserved1; /*!< Reserved1 */
- __IO uint16_t ManufactDate; /*!< Manufacturing Date */
- __IO uint8_t CID_CRC; /*!< CID CRC */
- __IO uint8_t Reserved2; /*!< Always 1 */
-
-}HAL_SD_CardCIDTypeDef;
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
- * @{
- */
-typedef struct
-{
- __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
- __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
- __IO uint16_t CardType; /*!< Carries information about card type */
- __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
- __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
- __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
- __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
- __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
- __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
- __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
-
-}HAL_SD_CardStatusTypeDef;
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
- * @{
- */
-
-#define BLOCKSIZE 512U /*!< Block size is 512 bytes */
-
-/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
- * @{
- */
-#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
-#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
-#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
-#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
-#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
-#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
-#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
-#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
-#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
-#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
-#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
-#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
-#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
-#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
-#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
-#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
-#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
-#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
-#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
-#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
-#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
-#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
-#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
-#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
-#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
-#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
-#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
-#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
-#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
-#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
- * @{
- */
-#define SD_CONTEXT_NONE 0x00000000U /*!< None */
-#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */
-#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */
-#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */
-#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */
-#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */
-#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
- * @{
- */
-#define CARD_SDSC 0x00000000U
-#define CARD_SDHC_SDXC 0x00000001U
-#define CARD_SECURED 0x00000003U
-
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
- * @{
- */
-#define CARD_V1_X 0x00000000U
-#define CARD_V2_X 0x00000001U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/**
- * @brief Enable the SD device.
- * @retval None
- */
-#define __HAL_SD_ENABLE(__HANDLE__) __SDIO_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the SD device.
- * @retval None
- */
-#define __HAL_SD_DISABLE(__HANDLE__) __SDIO_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDIO_DMA_ENABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Disable the SDMMC DMA transfer.
- * @retval None
- */
-#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDIO_DMA_DISABLE((__HANDLE__)->Instance)
-
-/**
- * @brief Enable the SD device interrupt.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Disable the SD device interrupt.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified SD flag is set or not.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval The new state of SD FLAG (SET or RESET).
- */
-#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Clear the SD's pending flags.
- * @param __HANDLE__: SD Handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval None
- */
-#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
- * @brief Check whether the specified SD interrupt has occurred or not.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval The new state of SD IT (SET or RESET).
- */
-#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDIO_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @brief Clear the SD's interrupt pending bits.
- * @param __HANDLE__: SD Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SD_Exported_Functions SD Exported Functions
- * @{
- */
-
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
-/* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group4 SD card related functions
- * @{
- */
-HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
-HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
-HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
-HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
- * @{
- */
-HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
- * @{
- */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup SD_Private_Types SD Private Types
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup SD_Private_Defines SD Private Defines
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup SD_Private_Variables SD Private Variables
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SD_Private_Constants SD Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SD_Private_Macros SD Private Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SD_Private_Functions SD Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#endif /* __STM32F1xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_sd.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_smartcard.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,683 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_smartcard.h
- * @author MCD Application Team
- * @brief Header file of SMARTCARD HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SMARTCARD_H
-#define __STM32F1xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SMARTCARD
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
- * @{
- */
-
-/**
- * @brief SMARTCARD Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the SmartCard communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (hsmartcard->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref SMARTCARD_Word_Length */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref SMARTCARD_Stop_Bits */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref SMARTCARD_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits).*/
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref SMARTCARD_Mode */
-
- uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
- uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
- uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock
- to provide the smartcard clock. The value given in the register (5 significant bits)
- is multiplied by 2 to give the division factor of the source clock frequency.
- This parameter can be a value of @ref SMARTCARD_Prescaler */
-
- uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
-
- uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state
- This parameter can be a value of @ref SMARTCARD_NACK_State */
-} SMARTCARD_InitTypeDef;
-
-/**
- * @brief HAL SMARTCARD State structures definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
- * - gState contains SMARTCARD state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL SMARTCARD Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_SMARTCARD_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_SMARTCARD_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_SMARTCARD_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_SMARTCARD_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_SMARTCARD_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-} HAL_SMARTCARD_StateTypeDef;
-
-/**
- * @brief SMARTCARD handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< SmartCard Error code */
-} SMARTCARD_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported constants
- * @{
- */
-
-/** @defgroup SMARTCARD_Error_Code SMARTCARD Error Code
- * @{
- */
-#define HAL_SMARTCARD_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_SMARTCARD_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_SMARTCARD_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_SMARTCARD_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_SMARTCARD_ERROR_ORE 0x00000008U /*!< OverRun error */
-#define HAL_SMARTCARD_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
- * @{
- */
-#define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
- * @{
- */
-#define SMARTCARD_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
- * @{
- */
-#define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Mode
- * @{
- */
-#define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
- * @{
- */
-#define SMARTCARD_POLARITY_LOW 0x00000000U
-#define SMARTCARD_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
- * @{
- */
-#define SMARTCARD_PHASE_1EDGE 0x00000000U
-#define SMARTCARD_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
- * @{
- */
-#define SMARTCARD_LASTBIT_DISABLE 0x00000000U
-#define SMARTCARD_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_NACK_State SMARTCARD NACK State
- * @{
- */
-#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
- * @{
- */
-#define SMARTCARD_DMAREQ_TX ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX ((uint32_t)USART_CR3_DMAR)
-/**
- * @}
- */
-
-/** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
- * @{
- */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2 0x00000001U /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4 0x00000002U /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6 0x00000003U /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8 0x00000004U /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10 0x00000005U /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12 0x00000006U /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14 0x00000007U /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16 0x00000008U /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18 0x00000009U /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20 0x0000000AU /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22 0x0000000BU /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24 0x0000000CU /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26 0x0000000DU /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28 0x0000000EU /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30 0x0000000FU /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32 0x00000010U /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34 0x00000011U /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36 0x00000012U /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38 0x00000013U /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40 0x00000014U /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42 0x00000015U /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44 0x00000016U /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46 0x00000017U /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48 0x00000018U /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50 0x00000019U /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52 0x0000001AU /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54 0x0000001BU /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56 0x0000001CU /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58 0x0000001DU /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60 0x0000001EU /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62 0x0000001FU /*!< SYSCLK divided by 62 */
-/**
- * @}
- */
-
-/** @defgroup SmartCard_Flags SMARTCARD Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define SMARTCARD_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define SMARTCARD_FLAG_TC ((uint32_t)USART_SR_TC)
-#define SMARTCARD_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define SMARTCARD_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define SMARTCARD_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define SMARTCARD_FLAG_NE ((uint32_t)USART_SR_NE)
-#define SMARTCARD_FLAG_FE ((uint32_t)USART_SR_FE)
-#define SMARTCARD_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup SmartCard_Interrupt_definition SMARTCARD Interrupts Definition
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
- * - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 11: CR3 register
- * @{
- */
-#define SMARTCARD_IT_PE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define SMARTCARD_IT_TXE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define SMARTCARD_IT_TC ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define SMARTCARD_IT_RXNE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define SMARTCARD_IT_IDLE ((uint32_t)(SMARTCARD_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-#define SMARTCARD_IT_ERR ((uint32_t)(SMARTCARD_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
- * @{
- */
-
-/** @brief Reset SMARTCARD handle gstate & RxState
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
- } while(0U)
-
-/** @brief Flush the Smartcard DR register
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief Check whether the specified Smartcard flag is set or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
- * @arg SMARTCARD_FLAG_TC: Transmission Complete flag
- * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
- * @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
- * @arg SMARTCARD_FLAG_ORE: OverRun Error flag
- * @arg SMARTCARD_FLAG_NE: Noise Error flag
- * @arg SMARTCARD_FLAG_FE: Framing Error flag
- * @arg SMARTCARD_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the specified Smartcard pending flags.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
- * @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun
- * error) flags are cleared by software sequence: a read operation to
- * USART_SR register followed by a read operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
- */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clear the SMARTCARD PE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clear the SMARTCARD FE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the SMARTCARD NE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the SMARTCARD ORE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the SMARTCARD IDLE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enable the specified SmartCard interrupt.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)
- */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief Disable the specified SmartCard interrupt.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt(Frame error, noise error, overRun error)
- */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
- * @param __HANDLE__: specifies the SmartCard Handle.
- * @param __IT__: specifies the SMARTCARD interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
- * @arg SMARTCARD_IT_TC: Transmission complete interrupt
- * @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
- * @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
- * @arg SMARTCARD_IT_ERR: Error interrupt
- * @arg SMARTCARD_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == SMARTCARD_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
-
-/** @brief Enable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-
-/** @brief Macros to enable the SmartCard DMA request.
- * @param __HANDLE__: specifies the SmartCard Handle.
- * @param __REQUEST__: specifies the SmartCard DMA request.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
- * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
- */
-#define __HAL_SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 |= (__REQUEST__))
-
-/** @brief Macros to disable the SmartCard DMA request.
- * @param __HANDLE__: specifies the SmartCard Handle.
- * @param __REQUEST__: specifies the SmartCard DMA request.
- * This parameter can be one of the following values:
- * @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
- * @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
- */
-#define __HAL_SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__) ((__HANDLE__)->Instance->CR3 &= ~(__REQUEST__))
-
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions
- * @{
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
-/**
- * @}
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsc);
-
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-/**
- * @}
- */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
- * @{
- */
-
-/** @brief SMARTCARD interruptions flag mask
- *
- */
-#define SMARTCARD_IT_MASK 0x0000FFFFU
-
-#define SMARTCARD_CR1_REG_INDEX 1U
-#define SMARTCARD_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
- * @{
- */
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
- ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
- ((PARITY) == SMARTCARD_PARITY_ODD))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x000000U))
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
- ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \
- ((NACK) == SMARTCARD_NACK_DISABLE))
-#define IS_SMARTCARD_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
-
-#define SMARTCARD_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define SMARTCARD_DIVMANT(_PCLK_, _BAUD_) (SMARTCARD_DIV((_PCLK_), (_BAUD_))/100U)
-#define SMARTCARD_DIVFRAQ(_PCLK_, _BAUD_) (((SMARTCARD_DIV((_PCLK_), (_BAUD_)) - (SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-/* SMARTCARD BRR = mantissa + overflow + fraction
- = (SMARTCARD DIVMANT << 4) + (SMARTCARD DIVFRAQ & 0xF0) + (SMARTCARD DIVFRAQ & 0x0FU) */
-#define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \
- (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0U)) + \
- (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_smartcard.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_spi.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,587 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SPI_H
-#define __STM32F1xx_HAL_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
- * @{
- */
-
-/**
- * @brief SPI Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the SPI operating mode.
- This parameter can be a value of @ref SPI_Mode */
-
- uint32_t Direction; /*!< Specifies the SPI Directional mode state.
- This parameter can be a value of @ref SPI_Direction */
-
- uint32_t DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_Data_Size */
-
- uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
- This parameter can be a value of @ref SPI_TI_mode */
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_CRC_Calculation */
-
- uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
-}SPI_InitTypeDef;
-
-/**
- * @brief HAL SPI State structure definition
- */
-typedef enum
-{
- HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
- HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
- HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
- HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
- HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
-}HAL_SPI_StateTypeDef;
-
-/**
- * @brief SPI handle Structure definition
- */
-typedef struct __SPI_HandleTypeDef
-{
- SPI_TypeDef *Instance; /*!< SPI registers base address */
-
- SPI_InitTypeDef Init; /*!< SPI communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< SPI Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< SPI Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
-
- void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
-
- void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
-
- DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
-
- __IO uint32_t ErrorCode; /*!< SPI Error code */
-
-}SPI_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_Error_Code SPI Error Code
- * @{
- */
-#define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
-#define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
-#define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
-#define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
-#define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
-/**
- * @}
- */
-
-/** @defgroup SPI_Mode SPI Mode
- * @{
- */
-#define SPI_MODE_SLAVE 0x00000000U
-#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
- * @}
- */
-
-/** @defgroup SPI_Direction SPI Direction Mode
- * @{
- */
-#define SPI_DIRECTION_2LINES 0x00000000U
-#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
-/**
- * @}
- */
-
-/** @defgroup SPI_Data_Size SPI Data Size
- * @{
- */
-#define SPI_DATASIZE_8BIT 0x00000000U
-#define SPI_DATASIZE_16BIT SPI_CR1_DFF
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
- * @{
- */
-#define SPI_POLARITY_LOW 0x00000000U
-#define SPI_POLARITY_HIGH SPI_CR1_CPOL
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
- * @{
- */
-#define SPI_PHASE_1EDGE 0x00000000U
-#define SPI_PHASE_2EDGE SPI_CR1_CPHA
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
- * @{
- */
-#define SPI_NSS_SOFT SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT 0x00000000U
-#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
- * @{
- */
-#define SPI_BAUDRATEPRESCALER_2 0x00000000U
-#define SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0
-#define SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1
-#define SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2
-#define SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
- * @{
- */
-#define SPI_FIRSTBIT_MSB 0x00000000U
-#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
-/**
- * @}
- */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
- * @{
- */
-#define SPI_TIMODE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
- * @{
- */
-#define SPI_CRCCALCULATION_DISABLE 0x00000000U
-#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
-/**
- * @}
- */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
- * @{
- */
-#define SPI_IT_TXE SPI_CR2_TXEIE
-#define SPI_IT_RXNE SPI_CR2_RXNEIE
-#define SPI_IT_ERR SPI_CR2_ERRIE
-/**
- * @}
- */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
- * @{
- */
-#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
-#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
-#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
-#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
-#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @brief Reset SPI handle state.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief Enable the specified SPI interrupts.
- * @param __HANDLE__: specifies the SPI handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
-
-/** @brief Disable the specified SPI interrupts.
- * @param __HANDLE__: specifies the SPI handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval None
- */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
-
-/** @brief Check whether the specified SPI interrupt source is enabled or not.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __INTERRUPT__: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
- * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
- * @arg SPI_IT_ERR: Error interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Check whether the specified SPI flag is set or not.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
- * @arg SPI_FLAG_TXE: Transmit buffer empty flag
- * @arg SPI_FLAG_CRCERR: CRC error flag
- * @arg SPI_FLAG_MODF: Mode fault flag
- * @arg SPI_FLAG_OVR: Overrun flag
- * @arg SPI_FLAG_BSY: Busy flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the SPI CRCERR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief Clear the SPI MODF pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg_modf = 0x00U; \
- tmpreg_modf = (__HANDLE__)->Instance->SR; \
- (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
- UNUSED(tmpreg_modf); \
- } while(0U)
-
-/** @brief Clear the SPI OVR pending flag.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
-do{ \
- __IO uint32_t tmpreg_ovr = 0x00U; \
- tmpreg_ovr = (__HANDLE__)->Instance->DR; \
- tmpreg_ovr = (__HANDLE__)->Instance->SR; \
- UNUSED(tmpreg_ovr); \
- } while(0U)
-
-
-/** @brief Enable the SPI peripheral.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
-
-/** @brief Disable the SPI peripheral.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/** @addtogroup SPI_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
- * @{
- */
-#define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
-#define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
- * @{
- */
-
-/** @brief Set the SPI transmit-only mode.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
-
-/** @brief Set the SPI receive-only mode.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
-
-/** @brief Reset the CRC calculation of the SPI.
- * @param __HANDLE__: specifies the SPI Handle.
- * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
- * @retval None
- */
-#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
- (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
- ((MODE) == SPI_MODE_MASTER))
-
-#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
- ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
- ((DATASIZE) == SPI_DATASIZE_8BIT))
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
- ((CPOL) == SPI_POLARITY_HIGH))
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
- ((CPHA) == SPI_PHASE_2EDGE))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
- ((NSS) == SPI_NSS_HARD_INPUT) || \
- ((NSS) == SPI_NSS_HARD_OUTPUT))
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
- ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
- ((BIT) == SPI_FIRSTBIT_LSB))
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
- ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
- * @{
- */
-uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_spi.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_spi_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_sram.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,199 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_sram.h
- * @author MCD Application Team
- * @brief Header file of SRAM HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_SRAM_H
-#define __STM32F1xx_HAL_SRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_fsmc.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
-
-/** @addtogroup SRAM
- * @{
- */
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Types SRAM Exported Types
- * @{
- */
-/**
- * @brief HAL SRAM State structures definition
- */
-typedef enum
-{
- HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
- HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
- HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
- HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
- HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
-
-}HAL_SRAM_StateTypeDef;
-
-/**
- * @brief SRAM handle Structure definition
- */
-typedef struct
-{
- FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
-
- FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
-
- FSMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
-
- HAL_LockTypeDef Lock; /*!< SRAM locking object */
-
- __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
-
- DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
-
-}SRAM_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
-
-/** @brief Reset SRAM handle state
- * @param __HANDLE__: SRAM handle
- * @retval None
- */
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SRAM_Exported_Functions
- * @{
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group1
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
-
-void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group2
- * @{
- */
-
-/* I/O operation functions *****************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group3
- * @{
- */
-
-/* SRAM Control functions ******************************************************/
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group4
- * @{
- */
-
-/* SRAM State functions *********************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_sram.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_tim.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1791 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_TIM_H
-#define __STM32F1xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
- * @{
- */
-/**
- * @brief TIM Time base Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_ClockDivision */
-
- uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
- This parameter can be a value of @ref TIM_AutoReloadPreload */
-} TIM_Base_InitTypeDef;
-
-/**
- * @brief TIM Output Compare Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCFastMode; /*!< Specifies the Fast mode state.
- This parameter can be a value of @ref TIM_Output_Fast_State
- @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM One Pulse Mode Configuration Structure definition
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1 and TIM8. */
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-
-/**
- * @brief TIM Input Capture Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
- * @brief TIM Encoder Configuration Structure definition
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Encoder_Mode */
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC2Selection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC2Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-
-/**
- * @brief TIM Clock Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClockSource; /*!< TIM clock sources
- This parameter can be a value of @ref TIM_Clock_Source */
- uint32_t ClockPolarity; /*!< TIM clock polarity
- This parameter can be a value of @ref TIM_Clock_Polarity */
- uint32_t ClockPrescaler; /*!< TIM clock prescaler
- This parameter can be a value of @ref TIM_Clock_Prescaler */
- uint32_t ClockFilter; /*!< TIM clock filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
-
-/**
- * @brief TIM Clear Input Configuration Handle Structure definition
- */
-typedef struct
-{
- uint32_t ClearInputState; /*!< TIM clear Input state
- This parameter can be ENABLE or DISABLE */
- uint32_t ClearInputSource; /*!< TIM clear Input sources
- This parameter can be a value of @ref TIM_ClearInput_Source */
- uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
- This parameter can be a value of @ref TIM_ClearInput_Polarity */
- uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
- This parameter can be a value of @ref TIM_ClearInput_Prescaler */
- uint32_t ClearInputFilter; /*!< TIM Clear Input filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/**
- * @brief TIM Slave configuration Structure definition
- */
-typedef struct {
- uint32_t SlaveMode; /*!< Slave mode selection
- This parameter can be a value of @ref TIM_Slave_Mode */
- uint32_t InputTrigger; /*!< Input Trigger source
- This parameter can be a value of @ref TIM_Trigger_Selection */
- uint32_t TriggerPolarity; /*!< Input Trigger polarity
- This parameter can be a value of @ref TIM_Trigger_Polarity */
- uint32_t TriggerPrescaler; /*!< Input trigger prescaler
- This parameter can be a value of @ref TIM_Trigger_Prescaler */
- uint32_t TriggerFilter; /*!< Input trigger filter
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-}TIM_SlaveConfigTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
- HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
- HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_TIM_StateTypeDef;
-
-/**
- * @brief HAL Active channel structures definition
- */
-typedef enum
-{
- HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
- HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
- HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
- HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
- HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/**
- * @brief TIM Time Base Handle Structure definition
- */
-typedef struct
-{
- TIM_TypeDef *Instance; /*!< Register base address */
- TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
- HAL_TIM_ActiveChannel Channel; /*!< Active channel */
- DMA_HandleTypeDef *hdma[7U]; /*!< DMA Handlers array
- This array is accessed by a @ref TIM_DMA_Handle_index */
- HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
-}TIM_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
- * @{
- */
-#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
-#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
- * @{
- */
-#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
-/**
- * @}
- */
-
-/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
- * @{
- */
-#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode TIM Counter Mode
- * @{
- */
-#define TIM_COUNTERMODE_UP 0x00000000U
-#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
-/**
- * @}
- */
-
-/** @defgroup TIM_ClockDivision TIM ClockDivision
- * @{
- */
-#define TIM_CLOCKDIVISION_DIV1 0x00000000U
-#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
-/**
- * @}
- */
-
-/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
- * @{
- */
-#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /*!< TIMx_ARR register is not buffered */
-#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
- * @{
- */
-#define TIM_OCMODE_TIMING 0x00000000U
-#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_State TIM Output Compare State
- * @{
- */
-#define TIM_OUTPUTSTATE_DISABLE 0x00000000U
-#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Fast_State TIM Output Fast State
- * @{
- */
-#define TIM_OCFAST_DISABLE 0x00000000U
-#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
- * @{
- */
-#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
-#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
- * @{
- */
-#define TIM_OCPOLARITY_HIGH 0x00000000U
-#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
- * @{
- */
-#define TIM_OCNPOLARITY_HIGH 0x00000000U
-#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
- * @{
- */
-#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
- * @{
- */
-#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
-#define TIM_OCNIDLESTATE_RESET 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel TIM Channel
- * @{
- */
-#define TIM_CHANNEL_1 0x00000000U
-#define TIM_CHANNEL_2 0x00000004U
-#define TIM_CHANNEL_3 0x00000008U
-#define TIM_CHANNEL_4 0x0000000CU
-#define TIM_CHANNEL_ALL 0x00000018U
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
- * @{
- */
-#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
-#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
- * @{
- */
-#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
- * @{
- */
-#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
- * @{
- */
-#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
- * @{
- */
-#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-/**
- * @}
- */
-
-/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
- * @{
- */
-#define TIM_IT_UPDATE (TIM_DIER_UIE)
-#define TIM_IT_CC1 (TIM_DIER_CC1IE)
-#define TIM_IT_CC2 (TIM_DIER_CC2IE)
-#define TIM_IT_CC3 (TIM_DIER_CC3IE)
-#define TIM_IT_CC4 (TIM_DIER_CC4IE)
-#define TIM_IT_COM (TIM_DIER_COMIE)
-#define TIM_IT_TRIGGER (TIM_DIER_TIE)
-#define TIM_IT_BREAK (TIM_DIER_BIE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Commutation_Source TIM Commutation Source
- * @{
- */
-#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
-#define TIM_COMMUTATION_SOFTWARE 0x00000000U
-
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources TIM DMA Sources
- * @{
- */
-#define TIM_DMA_UPDATE (TIM_DIER_UDE)
-#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
-#define TIM_DMA_COM (TIM_DIER_COMDE)
-#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
-/**
- * @}
- */
-
-/** @defgroup TIM_Event_Source TIM Event Source
- * @{
- */
-#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
-#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
-#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
-#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
-#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
-#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
-#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
-#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
-/**
- * @}
- */
-
-/** @defgroup TIM_Flag_definition TIM Flag Definition
- * @{
- */
-#define TIM_FLAG_UPDATE (TIM_SR_UIF)
-#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
-#define TIM_FLAG_COM (TIM_SR_COMIF)
-#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
-#define TIM_FLAG_BREAK (TIM_SR_BIF)
-#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Source TIM Clock Source
- * @{
- */
-#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
-#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
-#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
-#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
-#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
- * @{
- */
-#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
- * @{
- */
-#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
- * @{
- */
-#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
-#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
- * @{
- */
-#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
-/**
- * @}
- */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
- * @{
- */
-#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
- * @{
- */
-#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
- * @{
- */
-#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_Lock_level TIM Lock level
- * @{
- */
-#define TIM_LOCKLEVEL_OFF 0x00000000U
-#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
- * @{
- */
-#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
-#define TIM_BREAK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
- * @{
- */
-#define TIM_BREAKPOLARITY_LOW 0x00000000U
-#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
-/**
- * @}
- */
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
- * @{
- */
-#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
-#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
- * @{
- */
-#define TIM_TRGO_RESET 0x00000000U
-#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
-#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
-#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
-#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode TIM Slave Mode
- * @{
- */
-#define TIM_SLAVEMODE_DISABLE 0x00000000U
-#define TIM_SLAVEMODE_RESET 0x00000004U
-#define TIM_SLAVEMODE_GATED 0x00000005U
-#define TIM_SLAVEMODE_TRIGGER 0x00000006U
-#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
- * @{
- */
-#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
-#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
- * @{
- */
-#define TIM_TS_ITR0 0x00000000U
-#define TIM_TS_ITR1 0x00000010U
-#define TIM_TS_ITR2 0x00000020U
-#define TIM_TS_ITR3 0x00000030U
-#define TIM_TS_TI1F_ED 0x00000040U
-#define TIM_TS_TI1FP1 0x00000050U
-#define TIM_TS_TI2FP2 0x00000060U
-#define TIM_TS_ETRF 0x00000070U
-#define TIM_TS_NONE 0x0000FFFFU
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
- * @{
- */
-#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
- * @{
- */
-#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-/**
- * @}
- */
-
-/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
- * @{
- */
-#define TIM_TI1SELECTION_CH1 0x00000000U
-#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
- * @{
- */
-#define TIM_DMABASE_CR1 0x00000000U
-#define TIM_DMABASE_CR2 0x00000001U
-#define TIM_DMABASE_SMCR 0x00000002U
-#define TIM_DMABASE_DIER 0x00000003U
-#define TIM_DMABASE_SR 0x00000004U
-#define TIM_DMABASE_EGR 0x00000005U
-#define TIM_DMABASE_CCMR1 0x00000006U
-#define TIM_DMABASE_CCMR2 0x00000007U
-#define TIM_DMABASE_CCER 0x00000008U
-#define TIM_DMABASE_CNT 0x00000009U
-#define TIM_DMABASE_PSC 0x0000000AU
-#define TIM_DMABASE_ARR 0x0000000BU
-#define TIM_DMABASE_RCR 0x0000000CU
-#define TIM_DMABASE_CCR1 0x0000000DU
-#define TIM_DMABASE_CCR2 0x0000000EU
-#define TIM_DMABASE_CCR3 0x0000000FU
-#define TIM_DMABASE_CCR4 0x00000010U
-#define TIM_DMABASE_BDTR 0x00000011U
-#define TIM_DMABASE_DCR 0x00000012U
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
- * @{
- */
-#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
-#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
-#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
-#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
-#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
-#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
-#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
-#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
-#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
-#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
-#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
-#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
-#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
-#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
-#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
-#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
-#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
-#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
- * @{
- */
-#define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1 ((uint16_t)0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2 ((uint16_t)0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3 ((uint16_t)0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4 ((uint16_t)0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
-#define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
- * @{
- */
-#define TIM_CCx_ENABLE 0x00000001U
-#define TIM_CCx_DISABLE 0x00000000U
-#define TIM_CCxN_ENABLE 0x00000004U
-#define TIM_CCxN_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private Constants -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM Private Constants
- * @{
- */
-
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
-/**
- * @}
- */
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Macros TIM Private Macros
- * @{
- */
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
- ((MODE) == TIM_COUNTERMODE_DOWN) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
- ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
- ((DIV) == TIM_CLOCKDIVISION_DIV4))
-
-#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
- ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
- ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \
- ((MODE) == TIM_OCMODE_ACTIVE) || \
- ((MODE) == TIM_OCMODE_INACTIVE) || \
- ((MODE) == TIM_OCMODE_TOGGLE) || \
- ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \
- ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
- ((STATE) == TIM_OCFAST_ENABLE))
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCPOLARITY_LOW))
-
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
- ((POLARITY) == TIM_OCNPOLARITY_LOW))
-
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
- ((STATE) == TIM_OCIDLESTATE_RESET))
-
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
- ((STATE) == TIM_OCNIDLESTATE_RESET))
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4) || \
- ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3))
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
- ((POLARITY) == TIM_ICPOLARITY_FALLING))
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
- ((SELECTION) == TIM_ICSELECTION_TRC))
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
- ((MODE) == TIM_OPMODE_REPETITIVE))
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
- ((MODE) == TIM_ENCODERMODE_TI2) || \
- ((MODE) == TIM_ENCODERMODE_TI12))
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
- ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
- ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
- ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-
-#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
- ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
- ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
- ((STATE) == TIM_OSSR_DISABLE))
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
- ((STATE) == TIM_OSSI_DISABLE))
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
- ((LEVEL) == TIM_LOCKLEVEL_1) || \
- ((LEVEL) == TIM_LOCKLEVEL_2) || \
- ((LEVEL) == TIM_LOCKLEVEL_3))
-
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
- ((STATE) == TIM_BREAK_DISABLE))
-
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
- ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
- ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
- ((SOURCE) == TIM_TRGO_ENABLE) || \
- ((SOURCE) == TIM_TRGO_UPDATE) || \
- ((SOURCE) == TIM_TRGO_OC1) || \
- ((SOURCE) == TIM_TRGO_OC1REF) || \
- ((SOURCE) == TIM_TRGO_OC2REF) || \
- ((SOURCE) == TIM_TRGO_OC3REF) || \
- ((SOURCE) == TIM_TRGO_OC4REF))
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
- ((MODE) == TIM_SLAVEMODE_GATED) || \
- ((MODE) == TIM_SLAVEMODE_RESET) || \
- ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
- ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
- ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_NONE))
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
- ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
- ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-
-#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
- ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) || \
- ((BASE) == TIM_DMABASE_CR2) || \
- ((BASE) == TIM_DMABASE_SMCR) || \
- ((BASE) == TIM_DMABASE_DIER) || \
- ((BASE) == TIM_DMABASE_SR) || \
- ((BASE) == TIM_DMABASE_EGR) || \
- ((BASE) == TIM_DMABASE_CCMR1) || \
- ((BASE) == TIM_DMABASE_CCMR2) || \
- ((BASE) == TIM_DMABASE_CCER) || \
- ((BASE) == TIM_DMABASE_CNT) || \
- ((BASE) == TIM_DMABASE_PSC) || \
- ((BASE) == TIM_DMABASE_ARR) || \
- ((BASE) == TIM_DMABASE_RCR) || \
- ((BASE) == TIM_DMABASE_CCR1) || \
- ((BASE) == TIM_DMABASE_CCR2) || \
- ((BASE) == TIM_DMABASE_CCR3) || \
- ((BASE) == TIM_DMABASE_CCR4) || \
- ((BASE) == TIM_DMABASE_BDTR) || \
- ((BASE) == TIM_DMABASE_DCR))
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
- ((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
-
-/** @brief Set TIM IC prescaler
- * @param __HANDLE__: TIM handle
- * @param __CHANNEL__: specifies TIM Channel
- * @param __ICPSC__: specifies the prescaler value.
- * @retval None
- */
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
-
-/** @brief Reset TIM IC prescaler
- * @param __HANDLE__: TIM handle
- * @param __CHANNEL__: specifies TIM Channel
- * @retval None
- */
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
-
-
-/** @brief Set TIM IC polarity
- * @param __HANDLE__: TIM handle
- * @param __CHANNEL__: specifies TIM Channel
- * @param __POLARITY__: specifies TIM Channel Polarity
- * @retval None
- */
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
-
-/** @brief Reset TIM IC polarity
- * @param __HANDLE__: TIM handle
- * @param __CHANNEL__: specifies TIM Channel
- * @retval None
- */
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
-
-/**
- * @}
- */
-
-/* Private Functions --------------------------------------------------------*/
-/** @addtogroup TIM_Private_Functions
- * @{
- */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-void TIM_DMAError(DMA_HandleTypeDef *hdma);
-void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @brief Reset TIM handle state
- * @param __HANDLE__: TIM handle.
- * @retval None
- */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
- * @brief Enable the TIM peripheral.
- * @param __HANDLE__: TIM handle
- * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
- * @brief Enable the TIM main Output.
- * @param __HANDLE__: TIM handle
- * @retval None
- */
-#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/**
- * @brief Disable the TIM peripheral.
- * @param __HANDLE__: TIM handle
- * @retval None
- */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
- { \
- (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
- } \
- } \
- } while(0U)
-/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__: TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
- */
-#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
- do { \
- if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
- { \
- if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
- { \
- (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
- } \
- } \
- } while(0U)
-
-/**
- * @brief Disable the TIM main Output.
- * @param __HANDLE__: TIM handle
- * @retval None
- * @note The Main Output Enable of a timer instance is disabled unconditionally
- */
-#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
-
-/**
- * @brief Enables the specified TIM interrupt.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/**
- * @brief Disables the specified TIM interrupt.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg TIM_IT_UPDATE: Update interrupt
- * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
- * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
- * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
- * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
- * @arg TIM_IT_COM: Commutation interrupt
- * @arg TIM_IT_TRIGGER: Trigger interrupt
- * @arg TIM_IT_BREAK: Break interrupt
- * @retval None
- */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/**
- * @brief Enables the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to enable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/**
- * @brief Disables the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to disable.
- * This parameter can be one of the following values:
- * @arg TIM_DMA_UPDATE: Update DMA request
- * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
- * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
- * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
- * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
- * @arg TIM_DMA_COM: Commutation DMA request
- * @arg TIM_DMA_TRIGGER: Trigger DMA request
- * @retval None
- */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/**
- * @brief Checks whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clears the specified TIM interrupt flag.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to clear.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_UPDATE: Update interrupt flag
- * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
- * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
- * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
- * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
- * @arg TIM_FLAG_COM: Commutation interrupt flag
- * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
- * @arg TIM_FLAG_BREAK: Break interrupt flag
- * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
- * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
- * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
- * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
- * @brief Checks whether the specified TIM interrupt has occurred or not.
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the TIM interrupt source to check.
- * @retval The state of TIM_IT (SET or RESET).
- */
-#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
- * @brief Clear the TIM interrupt pending bits
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * @retval None
- */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/**
- * @brief Indicates whether or not the TIM Counter is used as downcounter
- * @param __HANDLE__: TIM handle.
- * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
- * @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
- */
-#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/**
- * @brief Sets the TIM active prescaler register value on update event.
- * @param __HANDLE__: TIM handle.
- * @param __PRESC__: specifies the active prescaler register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/**
- * @brief Sets the TIM Capture Compare Register value on runtime without
- * calling another time ConfigChannel function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __COMPARE__: specifies the Capture Compare register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
-
-/**
- * @brief Gets the TIM Capture Compare Register value on runtime
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channel associated with the capture compare register
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get capture/compare 1 register value
- * @arg TIM_CHANNEL_2: get capture/compare 2 register value
- * @arg TIM_CHANNEL_3: get capture/compare 3 register value
- * @arg TIM_CHANNEL_4: get capture/compare 4 register value
- * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
- */
-#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
- (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
-
-/**
- * @brief Sets the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __COUNTER__: specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
- * @brief Gets the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
- */
-#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
- ((__HANDLE__)->Instance->CNT)
-
-/**
- * @brief Sets the TIM Autoreload Register value on runtime without calling
- * another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __AUTORELOAD__: specifies the Counter register new value.
- * @retval None
- */
-#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
- do{ \
- (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
- (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
- } while(0U)
-
-/**
- * @brief Gets the TIM Autoreload Register value on runtime
- * @param __HANDLE__: TIM handle.
- * @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
- */
-#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
- ((__HANDLE__)->Instance->ARR)
-
-/**
- * @brief Sets the TIM Clock Division value on runtime without calling
- * another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __CKD__: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- * @retval None
- */
-#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
- do{ \
- (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
- (__HANDLE__)->Instance->CR1 |= (__CKD__); \
- (__HANDLE__)->Init.ClockDivision = (__CKD__); \
- } while(0U)
-
-/**
- * @brief Gets the TIM Clock Division value on runtime
- * @param __HANDLE__: TIM handle.
- * @retval The clock division can be one of the following values:
- * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
- * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
- */
-#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
- * @brief Sets the TIM Input Capture prescaler on runtime without calling
- * another time HAL_TIM_IC_ConfigChannel() function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
- do{ \
- TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
- } while(0U)
-
-/**
- * @brief Gets the TIM Input Capture prescaler on runtime
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
- * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
- * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
- * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval The input capture prescaler can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- */
-#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
- (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
-
-/**
- * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__: TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is set, only counter
- * overflow/underflow generates an update interrupt or DMA request (if
- * enabled)
- * @retval None
- */
-#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
-
-/**
- * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__: TIM handle.
- * @note When the USR bit of the TIMx_CR1 register is reset, any of the
- * following events generate an update interrupt or DMA request (if
- * enabled):
- * (+) Counter overflow/underflow
- * (+) Setting the UG bit
- * (+) Update generation through the slave mode controller
- * @retval None
- */
-#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
- ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-/**
- * @brief Sets the TIM Capture x input polarity on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__: Polarity for TIx source
- * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
- * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
- * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
- * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
- * @retval None
- */
-#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
- do{ \
- TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
- TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
- }while(0U)
-
-/**
- * @}
- */
-
-/* Include TIM HAL Extension module */
-#include "stm32f1xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIM_Exported_Functions_Group1
- * @{
- */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group2
- * @{
- */
-/* Timer Output Compare functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group3
- * @{
- */
-/* Timer PWM functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group4
- * @{
- */
-/* Timer Input Capture functions ***********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group5
- * @{
- */
-/* Timer One Pulse functions ***************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group6
- * @{
- */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group7
- * @{
- */
-/* Interrupt Handler functions **********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group8
- * @{
- */
-/* Control functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
- uint32_t *BurstBuffer, uint32_t BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group9
- * @{
- */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-/** @addtogroup TIM_Exported_Functions_Group10
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_tim.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_tim_ex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,343 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_tim_ex.h
- * @author MCD Application Team
- * @brief Header file of TIM HAL Extension module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_TIM_EX_H
-#define __STM32F1xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup TIMEx
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
- * @{
- */
-
-
-/**
- * @brief TIM Hall sensor Configuration Structure definition
- */
-
-typedef struct
-{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint32_t IC1Filter; /*!< Specifies the input capture filter.
- This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
- uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-} TIM_HallSensor_InitTypeDef;
-
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-
-/**
- * @brief TIM Break and Dead time configuration Structure definition
- */
-typedef struct
-{
- uint32_t OffStateRunMode; /*!< TIM off state in run mode
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
- uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
- uint32_t LockLevel; /*!< TIM Lock level
- This parameter can be a value of @ref TIM_Lock_level */
- uint32_t DeadTime; /*!< TIM dead Time
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
- uint32_t BreakState; /*!< TIM Break State
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
- uint32_t BreakPolarity; /*!< TIM Break input polarity
- This parameter can be a value of @ref TIM_Break_Polarity */
- uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BreakDeadTimeConfigTypeDef;
-
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/**
- * @brief TIM Master configuration Structure definition
- */
-typedef struct {
- uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
- This parameter can be a value of @ref TIM_Master_Mode_Selection */
- uint32_t MasterSlaveMode; /*!< Master/slave mode selection
- This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
- * @{
- */
-
-/** @defgroup TIMEx_Clock_Filter TIMEx Clock Filter
- * @{
- */
-#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/* Exported macro ------------------------------------------------------------*/
-/**
- * @brief Sets the TIM Output compare preload.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
-
-/**
- * @brief Resets the TIM Output compare preload.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
- * This parameter can be one of the following values:
- * @arg TIM_CHANNEL_1: TIM Channel 1 selected
- * @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @retval None
- */
-#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
- (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group1
- * @{
- */
-/* Timer Hall Sensor functions **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
-
-void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
-
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-
-/** @addtogroup TIMEx_Exported_Functions_Group2
- * @{
- */
-/* Timer Complementary Output Compare functions *****************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group3
- * @{
- */
-/* Timer Complementary PWM functions ****************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group4
- * @{
- */
-/* Timer Complementary One Pulse functions **********************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
- * @}
- */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/** @addtogroup TIMEx_Exported_Functions_Group5
- * @{
- */
-/* Extended Control functions ************************************************/
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
-HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
-/**
- * @}
- */
-
-/** @addtogroup TIMEx_Exported_Functions_Group6
- * @{
- */
-/* Extension Callback *********************************************************/
-void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
-void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-
-#if defined (STM32F100xB) || defined (STM32F100xE) || \
- defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F103xE) || defined (STM32F103xG) || \
- defined (STM32F105xC) || defined (STM32F107xC)
-/** @addtogroup TIMEx_Exported_Functions_Group7
- * @{
- */
-/* Extension Peripheral State functions **************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-/**
- * @}
- */
-#endif /* defined(STM32F100xB) || defined(STM32F100xE) || */
- /* defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || */
- /* defined(STM32F105xC) || defined(STM32F107xC) */
-
-/**
- * @}
- */
-/* End of exported functions -------------------------------------------------*/
-
-/* Private functions----------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
-* @{
-*/
-void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
-/**
-* @}
-*/
-/* End of private functions --------------------------------------------------*/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_tim_ex.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_uart.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,785 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_uart.h
- * @author MCD Application Team
- * @brief Header file of UART HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_UART_H
-#define __STM32F1xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup UART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
- * @{
- */
-
-/**
- * @brief UART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (huart->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref UART_Word_Length */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref UART_Stop_Bits */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref UART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref UART_Mode */
-
- uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
- This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
- uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
- This parameter can be a value of @ref UART_Over_Sampling. This feature is only available
- on STM32F100xx family, so OverSampling parameter should always be set to 16. */
-}UART_InitTypeDef;
-
-/**
- * @brief HAL UART State structures definition
- * @note HAL UART State value is a combination of 2 different substates: gState and RxState.
- * - gState contains UART state information related to global Handle management
- * and also information related to Tx operations.
- * gState value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : (Not Used)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized. HAL UART Init function already called)
- * b4-b3 (not used)
- * xx : Should be set to 00
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 (not used)
- * x : Should be set to 0
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
- * 1 : Busy (Tx operation ongoing)
- * - RxState contains information related to Rx operations.
- * RxState value coding follow below described bitmap :
- * b7-b6 (not used)
- * xx : Should be set to 00
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP not initialized)
- * b4-b2 (not used)
- * xxx : Should be set to 000
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 (not used)
- * x : Should be set to 0.
- */
-typedef enum
-{
- HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
- Value is allowed for gState and RxState */
- HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
- HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
- HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
- Value is allowed for RxState only */
- HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
- HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
- Value is allowed for gState only */
- HAL_UART_STATE_ERROR = 0xE0U /*!< Error
- Value is allowed for gState only */
-}HAL_UART_StateTypeDef;
-
-/**
- * @brief UART handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< UART registers base address */
-
- UART_InitTypeDef Init; /*!< UART communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< UART Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< UART Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
- This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
- __IO uint32_t ErrorCode; /*!< UART Error code */
-}UART_HandleTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported constants
- * @{
- */
-
-/** @defgroup UART_Error_Code UART Error Code
- * @{
- */
-#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-/**
- * @}
- */
-
-/** @defgroup UART_Word_Length UART Word Length
- * @{
- */
-#define UART_WORDLENGTH_8B 0x00000000U
-#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
- * @{
- */
-#define UART_STOPBITS_1 0x00000000U
-#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-/**
- * @}
- */
-
-/** @defgroup UART_Parity UART Parity
- * @{
- */
-#define UART_PARITY_NONE 0x00000000U
-#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
- * @{
- */
-#define UART_HWCONTROL_NONE 0x00000000U
-#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-/**
- * @}
- */
-
-/** @defgroup UART_Mode UART Transfer Mode
- * @{
- */
-#define UART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup UART_State UART State
- * @{
- */
-#define UART_STATE_DISABLE 0x00000000U
-#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE)
-/**
- * @}
- */
-
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
- * @{
- */
-#define UART_OVERSAMPLING_16 0x00000000U
-#if defined(USART_CR1_OVER8)
-#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8)
-#endif /* USART_CR1_OVER8 */
-/**
- * @}
- */
-
-
-/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length
- * @{
- */
-#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U
-#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL)
-/**
- * @}
- */
-/** @defgroup UART_WakeUp_functions UART Wakeup Functions
- * @{
- */
-#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U
-#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE)
-/**
- * @}
- */
-
-/** @defgroup UART_Flags UART FLags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS)
-#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD)
-#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define UART_FLAG_TC ((uint32_t)USART_SR_TC)
-#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define UART_FLAG_NE ((uint32_t)USART_SR_NE)
-#define UART_FLAG_FE ((uint32_t)USART_SR_FE)
-#define UART_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup UART_Interrupt_definition UART Interrupt Definitions
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask (16 bits) in the Y register
- * - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- * @{
- */
-
-#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
- * @{
- */
-
-/** @brief Reset UART handle gstate & RxState
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->gState = HAL_UART_STATE_RESET; \
- (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
- } while(0U)
-
-/** @brief Flushs the UART DR register
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief Checks whether the specified UART flag is set or not.
- * @param __HANDLE__: specifies the UART Handle.
- * This parameter can be UARTx where x: 1, 2, 3, 4 or 5 to select the USART or
- * UART peripheral.
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
- * @arg UART_FLAG_LBD: LIN Break detection flag
- * @arg UART_FLAG_TXE: Transmit data register empty flag
- * @arg UART_FLAG_TC: Transmission Complete flag
- * @arg UART_FLAG_RXNE: Receive data register not empty flag
- * @arg UART_FLAG_IDLE: Idle Line detection flag
- * @arg UART_FLAG_ORE: OverRun Error flag
- * @arg UART_FLAG_NE: Noise Error flag
- * @arg UART_FLAG_FE: Framing Error flag
- * @arg UART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the specified UART pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
- * @arg UART_FLAG_LBD: LIN Break detection flag.
- * @arg UART_FLAG_TC: Transmission Complete flag.
- * @arg UART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register followed by a read
- * operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register.
- * @note TXE flag is cleared only by a write to the USART_DR register.
- *
- */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clears the UART PE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clears the UART FE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clears the UART NE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clears the UART ORE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clears the UART IDLE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enable the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__: specifies the UART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief Disable the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __INTERRUPT__: specifies the UART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg UART_IT_CTS: CTS change interrupt
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_PE: Parity Error interrupt
- * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief Checks whether the specified UART interrupt has occurred or not.
- * @param __HANDLE__: specifies the UART Handle.
- * UART Handle selects the USARTx or UARTy peripheral
- * (USART,UART availability and x,y values depending on device).
- * @param __IT__: specifies the UART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
- * @arg UART_IT_LBD: LIN Break detection interrupt
- * @arg UART_IT_TXE: Transmit Data Register empty interrupt
- * @arg UART_IT_TC: Transmission complete interrupt
- * @arg UART_IT_RXNE: Receive Data register not empty interrupt
- * @arg UART_IT_IDLE: Idle line detection interrupt
- * @arg UART_IT_ERR: Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-
-/** @brief Enable CTS flow control
- * This macro allows to enable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \
- } while(0U)
-
-/** @brief Disable CTS flow control
- * This macro allows to disable CTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
- } while(0U)
-
-/** @brief Enable RTS flow control
- * This macro allows to enable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
- do{ \
- SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
- (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \
- } while(0U)
-
-/** @brief Disable RTS flow control
- * This macro allows to disable RTS hardware flow control for a given UART instance,
- * without need to call HAL_UART_Init() function.
- * As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
- * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
- * for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
- * - UART instance should have already been initialised (through call of HAL_UART_Init() )
- * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
- * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
- * The Handle Instance can be any USARTx (supporting the HW Flow control feature).
- * It is used to select the USART peripheral (USART availability and x value depending on device).
- */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
- do{ \
- CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
- (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
- } while(0U)
-
-#if defined(USART_CR3_ONEBIT)
-/** @brief macros to enables the UART's one bit sample method
- * @param __HANDLE__: specifies the UART Handle.
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief macros to disables the UART's one bit sample method
- * @param __HANDLE__: specifies the UART Handle.
- * @retval None
- */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-#endif /* USART_CR3_ONEBIT */
-
-/** @brief Enable UART
- * @param __HANDLE__: specifies the UART Handle.
- */
-#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
-
-/** @brief Disable UART
- * @param __HANDLE__: specifies the UART Handle.
- */
-#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions
- * @{
- */
-
-/** @addtogroup UART_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback (UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback (UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group3
- * @{
- */
-/* Peripheral Control functions ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/** @addtogroup UART_Exported_Functions_Group4
- * @{
- */
-/* Peripheral State functions **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
- * @{
- */
-/** @brief UART interruptions flag mask
- *
- */
-#define UART_IT_MASK 0x0000FFFFU
-
-#define UART_CR1_REG_INDEX 1U
-#define UART_CR2_REG_INDEX 2U
-#define UART_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
- * @{
- */
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
- ((LENGTH) == UART_WORDLENGTH_9B))
-#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
- ((STOPBITS) == UART_STOPBITS_2))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
- ((PARITY) == UART_PARITY_EVEN) || \
- ((PARITY) == UART_PARITY_ODD))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == UART_HWCONTROL_NONE) || \
- ((CONTROL) == UART_HWCONTROL_RTS) || \
- ((CONTROL) == UART_HWCONTROL_CTS) || \
- ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
- ((STATE) == UART_STATE_ENABLE))
-#if defined(USART_CR1_OVER8)
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
- ((SAMPLING) == UART_OVERSAMPLING_8))
-#endif /* USART_CR1_OVER8 */
-#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
- ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
- ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \
- (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
- ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \
- (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup UART_Private_Functions UART Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_uart.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_usart.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,593 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_usart.h
- * @author MCD Application Team
- * @brief Header file of USART HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_USART_H
-#define __STM32F1xx_HAL_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Types USART Exported Types
- * @{
- */
-
-/**
- * @brief USART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (husart->Init.BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-}USART_InitTypeDef;
-
-/**
- * @brief HAL State structures definition
- */
-typedef enum
-{
- HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not yet initialized */
- HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
- HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
- HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
- HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
- HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
- HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
- HAL_USART_STATE_ERROR = 0x04U /*!< Error */
-}HAL_USART_StateTypeDef;
-
-/**
- * @brief USART handle Structure definition
- */
-typedef struct
-{
- USART_TypeDef *Instance; /*!< USART registers base address */
-
- USART_InitTypeDef Init; /*!< Usart communication parameters */
-
- uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */
-
- uint16_t TxXferSize; /*!< Usart Tx Transfer size */
-
- __IO uint16_t TxXferCount; /*!< Usart Tx Transfer Counter */
-
- uint8_t *pRxBuffPtr; /*!< Pointer to Usart Rx transfer Buffer */
-
- uint16_t RxXferSize; /*!< Usart Rx Transfer size */
-
- __IO uint16_t RxXferCount; /*!< Usart Rx Transfer Counter */
-
- DMA_HandleTypeDef *hdmatx; /*!< Usart Tx DMA Handle parameters */
-
- DMA_HandleTypeDef *hdmarx; /*!< Usart Rx DMA Handle parameters */
-
- HAL_LockTypeDef Lock; /*!< Locking object */
-
- __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */
-
- __IO uint32_t ErrorCode; /*!< USART Error code */
-}USART_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_Error_Code USART Error Code
- * @brief USART Error Code
- * @{
- */
-#define HAL_USART_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_USART_ERROR_PE 0x00000001U /*!< Parity error */
-#define HAL_USART_ERROR_NE 0x00000002U /*!< Noise error */
-#define HAL_USART_ERROR_FE 0x00000004U /*!< Frame error */
-#define HAL_USART_ERROR_ORE 0x00000008U /*!< Overrun error */
-#define HAL_USART_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-/**
- * @}
- */
-
-/** @defgroup USART_Word_Length USART Word Length
- * @{
- */
-#define USART_WORDLENGTH_8B 0x00000000U
-#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits USART Number of Stop Bits
- * @{
- */
-#define USART_STOPBITS_1 0x00000000U
-#define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity USART Parity
- * @{
- */
-#define USART_PARITY_NONE 0x00000000U
-#define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode USART Mode
- * @{
- */
-#define USART_MODE_RX ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock USART Clock
- * @{
- */
-#define USART_CLOCK_DISABLE 0x00000000U
-#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN)
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity USART Clock Polarity
- * @{
- */
-#define USART_POLARITY_LOW 0x00000000U
-#define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL)
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase USART Clock Phase
- * @{
- */
-#define USART_PHASE_1EDGE 0x00000000U
-#define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA)
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit USART Last Bit
- * @{
- */
-#define USART_LASTBIT_DISABLE 0x00000000U
-#define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL)
-/**
- * @}
- */
-
-/** @defgroup USART_NACK_State USART NACK State
- * @{
- */
-#define USART_NACK_ENABLE ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup USART_Flags USART Flags
- * Elements values convention: 0xXXXX
- * - 0xXXXX : Flag mask in the SR register
- * @{
- */
-#define USART_FLAG_TXE ((uint32_t)USART_SR_TXE)
-#define USART_FLAG_TC ((uint32_t)USART_SR_TC)
-#define USART_FLAG_RXNE ((uint32_t)USART_SR_RXNE)
-#define USART_FLAG_IDLE ((uint32_t)USART_SR_IDLE)
-#define USART_FLAG_ORE ((uint32_t)USART_SR_ORE)
-#define USART_FLAG_NE ((uint32_t)USART_SR_NE)
-#define USART_FLAG_FE ((uint32_t)USART_SR_FE)
-#define USART_FLAG_PE ((uint32_t)USART_SR_PE)
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
- * Elements values convention: 0xY000XXXX
- * - XXXX : Interrupt mask in the XX register
- * - Y : Interrupt source register (2bits)
- * - 01: CR1 register
- * - 10: CR2 register
- * - 11: CR3 register
- *
- * @{
- */
-
-#define USART_IT_PE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define USART_IT_TXE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define USART_IT_TC ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define USART_IT_RXNE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define USART_IT_IDLE ((uint32_t)(USART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define USART_IT_LBD ((uint32_t)(USART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define USART_IT_CTS ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define USART_IT_ERR ((uint32_t)(USART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @brief Reset USART handle state
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-
-/** @brief Checks whether the specified USART flag is set or not.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_TXE: Transmit data register empty flag
- * @arg USART_FLAG_TC: Transmission Complete flag
- * @arg USART_FLAG_RXNE: Receive data register not empty flag
- * @arg USART_FLAG_IDLE: Idle Line detection flag
- * @arg USART_FLAG_ORE: OverRun Error flag
- * @arg USART_FLAG_NE: Noise Error flag
- * @arg USART_FLAG_FE: Framing Error flag
- * @arg USART_FLAG_PE: Parity Error flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the specified USART pending flags.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- *
- * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
- * error) and IDLE (Idle line detected) flags are cleared by software
- * sequence: a read operation to USART_SR register followed by a read
- * operation to USART_DR register.
- * @note RXNE flag can be also cleared by a read to the USART_DR register.
- * @note TC flag can be also cleared by software sequence: a read operation to
- * USART_SR register followed by a write operation to USART_DR register
- * @note TXE flag is cleared only by a write to the USART_DR register
- *
- */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief Clear the USART PE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) \
- do{ \
- __IO uint32_t tmpreg = 0x00U; \
- tmpreg = (__HANDLE__)->Instance->SR; \
- tmpreg = (__HANDLE__)->Instance->DR; \
- UNUSED(tmpreg); \
- } while(0U)
-
-/** @brief Clear the USART FE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the USART NE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the USART ORE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
-
- */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Clear the USART IDLE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief Enable the specified USART interrupts.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __INTERRUPT__: specifies the USART interrupt source to enable.
- * This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * This parameter can be: ENABLE or DISABLE.
- */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-
-/** @brief Disable the specified USART interrupts.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __INTERRUPT__: specifies the USART interrupt source to disable.
- * This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * This parameter can be: ENABLE or DISABLE.
- */
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
-/** @brief Checks whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- * @param __IT__: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_TXE: Transmit Data Register empty interrupt
- * @arg USART_IT_TC: Transmission complete interrupt
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt
- * @arg USART_IT_IDLE: Idle line detection interrupt
- * @arg USART_IT_ERR: Error interrupt
- * @arg USART_IT_PE: Parity Error interrupt
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \
- (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
-
-/** @brief Enable USART
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_USART_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
-
-/** @brief Disable USART
- * @param __HANDLE__: specifies the USART Handle.
- * USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
- */
-#define __HAL_USART_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE))
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USART_Exported_Functions
- * @{
- */
-
-/** @addtogroup USART_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-/**
- * @}
- */
-
-/** @addtogroup USART_Exported_Functions_Group2
- * @{
- */
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
-
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
-/**
- * @}
- */
-
-/** @addtogroup USART_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ************************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
-/**
- * @}
- */
-
-/**
- * @}
- */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_Private_Constants USART Private Constants
- * @{
- */
-/** @brief USART interruptions flag mask
- *
- */
-#define USART_IT_MASK 0x0000FFFFU
-
-#define USART_CR1_REG_INDEX 1U
-#define USART_CR2_REG_INDEX 2U
-#define USART_CR3_REG_INDEX 3U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup USART_Private_Macros USART Private Macros
- * @{
- */
-#define IS_USART_NACK_STATE(NACK) (((NACK) == USART_NACK_ENABLE) || \
- ((NACK) == USART_NACK_DISABLE))
-
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LASTBIT_DISABLE) || \
- ((LASTBIT) == USART_LASTBIT_ENABLE))
-
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
-
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
-
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \
- ((CLOCK) == USART_CLOCK_ENABLE))
-
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WORDLENGTH_8B) || \
- ((LENGTH) == USART_WORDLENGTH_9B))
-
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_STOPBITS_1) || \
- ((STOPBITS) == USART_STOPBITS_0_5) || \
- ((STOPBITS) == USART_STOPBITS_1_5) || \
- ((STOPBITS) == USART_STOPBITS_2))
-
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PARITY_NONE) || \
- ((PARITY) == USART_PARITY_EVEN) || \
- ((PARITY) == USART_PARITY_ODD))
-
-#define IS_USART_MODE(MODE) ((((MODE) & 0xFFF3U) == 0x00U) && ((MODE) != 0x00U))
-
-#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 4500001U)
-
-#define USART_DIV(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_)))
-
-#define USART_DIVMANT(_PCLK_, _BAUD_) (USART_DIV((_PCLK_), (_BAUD_))/100U)
-
-#define USART_DIVFRAQ(_PCLK_, _BAUD_) (((USART_DIV((_PCLK_), (_BAUD_)) - (USART_DIVMANT((_PCLK_), (_BAUD_)) * 100U)) * 16U + 50U) / 100U)
-
-#define USART_BRR(_PCLK_, _BAUD_) ((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U)|(USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0FU))
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup USART_Private_Functions USART Private Functions
- * @{
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_usart.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_wwdg.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,281 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_hal_wwdg.h
- * @author MCD Application Team
- * @brief Header file of WWDG HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_HAL_WWDG_H
-#define __STM32F1xx_HAL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
- * @{
- */
-
-/**
- * @brief WWDG Init structure definition
- */
-typedef struct
-{
- uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
- This parameter can be a value of @ref WWDG_Prescaler */
-
- uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
- This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
-
- uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
- This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
- This parameter can be a value of @ref WWDG_EWI_Mode */
-
-} WWDG_InitTypeDef;
-
-/**
- * @brief WWDG handle Structure definition
- */
-typedef struct
-{
- WWDG_TypeDef *Instance; /*!< Register base address */
-
- WWDG_InitTypeDef Init; /*!< WWDG required parameters */
-
-} WWDG_HandleTypeDef;
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
- * @{
- */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
- * @{
- */
-#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
- * @brief WWDG Flag definition
- * @{
- */
-#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
-/**
- * @}
- */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
- * @{
- */
-#define WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
- * @}
- */
-
-/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
- * @{
- */
-#define WWDG_EWI_DISABLE 0x00000000U /*!< EWI Disable */
-#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Macros WWDG Private Macros
- * @{
- */
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
- ((__PRESCALER__) == WWDG_PRESCALER_2) || \
- ((__PRESCALER__) == WWDG_PRESCALER_4) || \
- ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
-
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
-
-#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
- ((__MODE__) == WWDG_EWI_DISABLE))
-/**
- * @}
- */
-
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
- * @{
- */
-
-/**
- * @brief Enables the WWDG peripheral.
- * @param __HANDLE__: WWDG handle
- * @retval None
- */
-#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
- * @brief Enables the WWDG early wakeup interrupt.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__ specifies the interrupt to enable.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early wakeup interrupt
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @retval None
- */
-#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
-
-/**
- * @brief Checks whether the selected WWDG interrupt has occurred or not.
- * @param __HANDLE__ WWDG handle
- * @param __INTERRUPT__ specifies the it to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
-
-/** @brief Clear the WWDG's interrupt pending bits
- * bits to clear the selected interrupt pending bits.
- * @param __HANDLE__: WWDG handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
- * @brief Check whether the specified WWDG flag is set or not.
- * @param __HANDLE__ WWDG handle
- * @param __FLAG__ specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval The new state of WWDG_FLAG (SET or RESET).
- */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clears the WWDG's pending flags.
- * @param __HANDLE__: WWDG handle
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
- * @retval None
- */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
-/** @brief Checks if the specified WWDG interrupt source is enabled or disabled.
- * @param __HANDLE__: WWDG Handle.
- * @param __INTERRUPT__: specifies the WWDG interrupt source to check.
- * This parameter can be one of the following values:
- * @arg WWDG_IT_EWI: Early Wakeup Interrupt
- * @retval state of __INTERRUPT__ (TRUE or FALSE).
- */
-#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup WWDG_Exported_Functions
- * @{
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions **********************************/
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-/**
- * @}
- */
-
-/** @addtogroup WWDG_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_wwdg.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_adc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,3948 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_adc.h
- * @author MCD Application Team
- * @brief Header file of ADC LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_ADC_H
-#define __STM32F1xx_LL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (ADC1) || defined (ADC2) || defined (ADC3)
-
-/** @defgroup ADC_LL ADC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Constants ADC Private Constants
- * @{
- */
-
-/* Internal mask for ADC group regular sequencer: */
-/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
-/* - sequencer register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group regular sequencer configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SQR1_REGOFFSET 0x00000000U
-#define ADC_SQR2_REGOFFSET 0x00000100U
-#define ADC_SQR3_REGOFFSET 0x00000200U
-#define ADC_SQR4_REGOFFSET 0x00000300U
-
-#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
-#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Definition of ADC group regular sequencer bits information to be inserted */
-/* into ADC group regular sequencer ranks literals definition. */
-#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
-#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
-#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
-#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
-#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
-#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
-#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
-#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
-#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
-#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
-#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
-#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
-#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
-#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
-#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
-#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
-
-/* Internal mask for ADC group injected sequencer: */
-/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
-/* - data register offset */
-/* - offset register offset */
-/* - sequencer rank bits position into the selected register */
-
-/* Internal register offset for ADC group injected data register */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JDR1_REGOFFSET 0x00000000U
-#define ADC_JDR2_REGOFFSET 0x00000100U
-#define ADC_JDR3_REGOFFSET 0x00000200U
-#define ADC_JDR4_REGOFFSET 0x00000300U
-
-/* Internal register offset for ADC group injected offset configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_JOFR1_REGOFFSET 0x00000000U
-#define ADC_JOFR2_REGOFFSET 0x00001000U
-#define ADC_JOFR3_REGOFFSET 0x00002000U
-#define ADC_JOFR4_REGOFFSET 0x00003000U
-
-#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
-#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
-#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
-
-/* Internal mask for ADC channel: */
-/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
-/* - channel identifier defined by number */
-/* - channel differentiation between external channels (connected to */
-/* GPIO pins) and internal channels (connected to internal paths) */
-/* - channel sampling time defined by SMPRx register offset */
-/* and SMPx bits positions into SMPRx register */
-#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
-#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
-
-/* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
-#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
-#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
-
-/* Internal register offset for ADC channel sampling time configuration */
-/* (offset placed into a spare area of literal definition) */
-#define ADC_SMPR1_REGOFFSET 0x00000000U
-#define ADC_SMPR2_REGOFFSET 0x02000000U
-#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
-
-#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
-#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
-
-/* Definition of channels ID number information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_NUMBER 0x00000000U
-#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
-#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
-#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
-#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
-#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
-#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
-#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
-
-/* Definition of channels sampling time information to be inserted into */
-/* channels literals definition. */
-#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
-#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
-#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
-#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
-#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
-#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
-#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
-#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
-#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
-#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
-#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
-#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
-#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
-#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
-#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
-#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
-#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
-#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
-
-/* Internal mask for ADC analog watchdog: */
-/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
-/* (concatenation of multiple bits used in different analog watchdogs, */
-/* (feature of several watchdogs not available on all STM32 families)). */
-/* - analog watchdog 1: monitored channel defined by number, */
-/* selection of ADC group (ADC groups regular and-or injected). */
-
-/* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET 0x00000000U
-
-#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
-
-#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
-#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
-
-/* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
-#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
-#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
-
-/* ADC registers bits positions */
-#define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Private_Macros ADC Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: isolate bits with the
- * selected mask and shift them to the register LSB
- * (shift mask on register position bit 0).
- * @param __BITS__ Bits in register 32 bits
- * @param __MASK__ Mask in register 32 bits
- * @retval Bits in register 32 bits
- */
-#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
- (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- * @retval Pointer to register address
- */
-#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
-
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of ADC common parameters
- * and multimode
- * (all ADC instances belonging to the same ADC common instance).
- * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
- * is conditioned to ADC instances state (all ADC instances
- * sharing the same ADC common instance):
- * All ADC instances sharing the same ADC common instance must be
- * disabled.
- */
-typedef struct
-{
- uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
- This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
-} LL_ADC_CommonInitTypeDef;
-/**
- * @brief Structure definition of some features of ADC instance.
- * @note These parameters have an impact on ADC scope: ADC instance.
- * Affects both group regular and group injected (availability
- * of ADC group injected depends on STM32 families).
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Instance .
- * @note The setting of these parameters by function @ref LL_ADC_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
- This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
-
- uint32_t SequencersScanMode; /*!< Set ADC scan selection.
- This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
-
-} LL_ADC_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group regular.
- * @note These parameters have an impact on ADC scope: ADC group regular.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "REG").
- * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
- (only trigger polarity available on this STM32 serie).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
- This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
- @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
- This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group regular sequencer is enabled
- (scan length of 2 ranks or more).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
-
- uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
- This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
- Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
-
- uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
- This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
-
-} LL_ADC_REG_InitTypeDef;
-
-/**
- * @brief Structure definition of some features of ADC group injected.
- * @note These parameters have an impact on ADC scope: ADC group injected.
- * Refer to corresponding unitary functions into
- * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
- * (functions with prefix "INJ").
- * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
- * is conditioned to ADC state:
- * ADC instance must be disabled.
- * This condition is applied to all ADC features, for efficiency
- * and compatibility over all STM32 families. However, the different
- * features can be set under different ADC state conditions
- * (setting possible with ADC enabled without conversion on going,
- * ADC enabled with conversion on going, ...)
- * Each feature can be updated afterwards with a unitary function
- * and potentially with ADC in a different state than disabled,
- * refer to description of each function for setting
- * conditioned to ADC state.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
- (only trigger polarity available on this STM32 serie).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
-
- uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
- This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
- @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
-
- uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
- This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
- @note This parameter has an effect only if group injected sequencer is enabled
- (scan length of 2 ranks or more).
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
-
- uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
- This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
- Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
-
- This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
-
-} LL_ADC_INJ_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
- * @{
- */
-
-/** @defgroup ADC_LL_EC_FLAG ADC flags
- * @brief Flags defines which can be used with LL_ADC_ReadReg function
- * @{
- */
-#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
-#define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
-#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
-#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
-#if defined(ADC_MULTIMODE_SUPPORT)
-#define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
-#define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
-#define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
-#define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
-#define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
- * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
- * @{
- */
-#define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
-#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
-#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
- * @{
- */
-/* List of ADC registers intended to be used (most commonly) with */
-/* DMA transfer. */
-/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
-#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
-#if defined(ADC_MULTIMODE_SUPPORT)
-#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
- * @{
- */
-/* Note: Other measurement paths to internal channels may be available */
-/* (connections to other peripherals). */
-/* If they are not listed below, they do not require any specific */
-/* path enable. In this case, Access to measurement path is done */
-/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
-#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
-#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
- * @{
- */
-#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
- * @{
- */
-#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
- * @{
- */
-#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
-#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
- * @{
- */
-#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
-#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
-#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
- * @{
- */
-#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
-#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
-#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
-#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
-#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
-#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
-#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
-#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
-#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
-#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
-#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */
-#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
- * @{
- */
-/* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
-#define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-/* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
-/* XL-density devices. */
-/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
-/* A remap of trigger must be done at top level (refer to */
-/* AFIO peripheral). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/
-#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
-#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
- * @{
- */
-#define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
-* @{
-*/
-#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
-#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
- * @{
- */
-#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
-#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
- * @{
- */
-#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
-#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
- * @{
- */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
-#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
-#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
-#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
- * @{
- */
-#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
-#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
-#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
-#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
-#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
-#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
-#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
-#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
-#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
-#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
-#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
-#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
-#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
-#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
-#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
-#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
- * @{
- */
-/* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
-#define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-/* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
-#if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
-/* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */
-/* XL-density devices. */
-/* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
-/* A remap of trigger must be done at top level (refer to */
-/* AFIO peripheral). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */
-#endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
-#if defined (STM32F103xE) || defined (STM32F103xG)
-/* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
-#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#endif
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
- * @{
- */
-#define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
-* @{
-*/
-#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
-#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
-/**
- * @}
- */
-
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
- * @{
- */
-#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
-#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
- * @{
- */
-#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
-#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
- * @{
- */
-#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
-#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
-#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
-#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
- * @{
- */
-#define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
-#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
-#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
- * @{
- */
-#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
- * @{
- */
-#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
-#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
-#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
-#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
-#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
-#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
-#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
-#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
-#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
-#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
-#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
- * @{
- */
-#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
-#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
-/**
- * @}
- */
-
-#if !defined(ADC_MULTIMODE_SUPPORT)
-/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
- * @{
- */
-#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
-/**
- * @}
- */
-#endif
-#if defined(ADC_MULTIMODE_SUPPORT)
-/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
- * @{
- */
-#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
-#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */
-#define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
-#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
-#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
-#define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */
-#define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
- * @{
- */
-#define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */
-#define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */
-#define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
-/**
- * @}
- */
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-
-/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
- * @note Only ADC IP HW delays are defined in ADC LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
-/* not timeout values. */
-/* Timeout values for ADC operations are dependent to device clock */
-/* configuration (system clock versus ADC clock), */
-/* and therefore must be defined in user application. */
-/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
-/* - ADC enable time: maximum delay is 1us */
-/* (refer to device datasheet, parameter "tSTAB") */
-/* - ADC conversion time: duration depending on ADC clock and ADC */
-/* configuration. */
-/* (refer to device reference manual, section "Timing") */
-
-/* Delay for temperature sensor stabilization time. */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSTART"). */
-/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */
-
-/* Delay required between ADC disable and ADC calibration start. */
-/* Note: On this STM32 serie, before starting a calibration, */
-/* ADC must be disabled. */
-/* A minimum number of ADC clock cycles are required */
-/* between ADC disable state and calibration start. */
-/* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */
-/* Wait time can be computed in user application by waiting for the */
-/* equivalent number of CPU cycles, by taking into account */
-/* ratio of CPU clock versus ADC clock prescalers. */
-/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */
-
-/* Delay required between end of ADC Enable and the start of ADC calibration. */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
-/* are required between the end of ADC enable and the start of ADC */
-/* calibration. */
-/* Wait time can be computed in user application by waiting for the */
-/* equivalent number of CPU cycles, by taking into account */
-/* ratio of CPU clock versus ADC clock prescalers. */
-/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
- * @{
- */
-
-/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in ADC register
- * @param __INSTANCE__ ADC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get ADC channel number in decimal format
- * from literals LL_ADC_CHANNEL_x.
- * @note Example:
- * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
- * will return decimal number "4".
- * @note The input can be a value from functions where a channel
- * number is returned, either defined with number
- * or with bitfield (only one bit must be set).
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval Value between Min_Data=0 and Max_Data=18
- */
-#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
-
-/**
- * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
- * from number in decimal format.
- * @note Example:
- * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
- * will return a data equivalent to "LL_ADC_CHANNEL_4".
- * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- * (1) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9U) \
- ? ( \
- ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
- : \
- ( \
- ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
- (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
- )
-
-/**
- * @brief Helper macro to determine whether the selected channel
- * corresponds to literal definitions of driver.
- * @note The different literal definitions of ADC channels are:
- * - ADC internal channel:
- * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
- * - ADC external channel (channel connected to a GPIO pin):
- * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
- * @note The channel parameter must be a value defined from literal
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
- * must not be a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
- * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
- */
-#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
- (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
-
-/**
- * @brief Helper macro to convert a channel defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * to its equivalent parameter definition of a ADC external channel
- * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
- * @note The channel parameter can be, additionally to a value
- * defined from parameter definition of a ADC internal channel
- * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is returned
- * from ADC registers.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- */
-#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
- ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
-
-/**
- * @brief Helper macro to determine whether the internal channel
- * selected is available on the ADC instance selected.
- * @note The channel parameter must be a value defined from parameter
- * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
- * LL_ADC_CHANNEL_TEMPSENSOR, ...),
- * must not be a value defined from parameter definition of
- * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
- * or a value from functions where a channel number is
- * returned from ADC registers,
- * because internal and external channels share the same channel
- * number in ADC registers. The differentiation is made only with
- * parameters definitions of driver.
- * @param __ADC_INSTANCE__ ADC instance
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
- * Value "1" if the internal channel selected is available on the ADC instance selected.
- */
-#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- (((__ADC_INSTANCE__) == ADC1) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
- ) \
- : \
- (0U) \
- )
-
-/**
- * @brief Helper macro to define ADC analog watchdog parameter:
- * define a single channel to monitor with analog watchdog
- * from sequencer channel and groups definition.
- * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
- * Example:
- * LL_ADC_SetAnalogWDMonitChannels(
- * ADC1, LL_ADC_AWD1,
- * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- * (1) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- * @param __GROUP__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_GROUP_REGULAR
- * @arg @ref LL_ADC_GROUP_INJECTED
- * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- */
-#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
- (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
- : \
- ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
- ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
- : \
- (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
- )
-
-/**
- * @brief Helper macro to set the value of ADC analog watchdog threshold high
- * or low in function of ADC resolution, when ADC resolution is
- * different of 12 bits.
- * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
- * Example, with a ADC resolution of 8 bits, to set the value of
- * analog watchdog threshold high (on 8 bits):
- * LL_ADC_SetAnalogWDThresholds
- * (< ADCx param >,
- * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
- * );
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
-/* This macro has been kept anyway for compatibility with other */
-/* STM32 families featuring different ADC resolutions. */
-#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
- ((__AWD_THRESHOLD__) << (0U))
-
-/**
- * @brief Helper macro to get the value of ADC analog watchdog threshold high
- * or low in function of ADC resolution, when ADC resolution is
- * different of 12 bits.
- * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
- * Example, with a ADC resolution of 8 bits, to get the value of
- * analog watchdog threshold high (on 8 bits):
- * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
- * (LL_ADC_RESOLUTION_8B,
- * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
- * );
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-/* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
-/* This macro has been kept anyway for compatibility with other */
-/* STM32 families featuring different ADC resolutions. */
-#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
- (__AWD_THRESHOLD_12_BITS__)
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Helper macro to get the ADC multimode conversion data of ADC master
- * or ADC slave from raw value with both ADC conversion data concatenated.
- * @note This macro is intended to be used when multimode transfer by DMA
- * is enabled.
- * In this case the transferred data need to processed with this macro
- * to separate the conversion data of ADC master and ADC slave.
- * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_MULTI_MASTER
- * @arg @ref LL_ADC_MULTI_SLAVE
- * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
- (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
-#endif
-
-/**
- * @brief Helper macro to select the ADC common instance
- * to which is belonging the selected ADC instance.
- * @note ADC common register instance can be used for:
- * - Set parameters common to several ADC instances
- * - Multimode (for devices with several ADC instances)
- * Refer to functions having argument "ADCxy_COMMON" as parameter.
- * @note On STM32F1, there is no common ADC instance.
- * However, ADC instance ADC1 has a role of common ADC instance
- * for ADC1 and ADC2:
- * this instance is used to manage internal channels
- * and multimode (these features are managed in ADC common
- * instances on some other STM32 devices).
- * ADC instance ADC3 (if available on the selected device)
- * has no ADC common instance.
- * @param __ADCx__ ADC instance
- * @retval ADC common register instance
- */
-#if defined(ADC1) && defined(ADC2) && defined(ADC3)
-#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
- ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
- ? ( \
- (ADC12_COMMON) \
- ) \
- : \
- ( \
- (0U) \
- ) \
- )
-#elif defined(ADC1) && defined(ADC2)
-#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
- (ADC12_COMMON)
-#else
-#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
- (ADC1_COMMON)
-#endif
-
-/**
- * @brief Helper macro to check if all ADC instances sharing the same
- * ADC common instance are disabled.
- * @note This check is required by functions with setting conditioned to
- * ADC state:
- * All ADC instances of the ADC common group must be disabled.
- * Refer to functions having argument "ADCxy_COMMON" as parameter.
- * @note On devices with only 1 ADC common instance, parameter of this macro
- * is useless and can be ignored (parameter kept for compatibility
- * with devices featuring several ADC common instances).
- * @note On STM32F1, there is no common ADC instance.
- * However, ADC instance ADC1 has a role of common ADC instance
- * for ADC1 and ADC2:
- * this instance is used to manage internal channels
- * and multimode (these features are managed in ADC common
- * instances on some other STM32 devices).
- * ADC instance ADC3 (if available on the selected device)
- * has no ADC common instance.
- * @param __ADCXY_COMMON__ ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Value "0" if all ADC instances sharing the same ADC common instance
- * are disabled.
- * Value "1" if at least one ADC instance sharing the same ADC common instance
- * is enabled.
- */
-#if defined(ADC1) && defined(ADC2) && defined(ADC3)
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- (((__ADCXY_COMMON__) == ADC12_COMMON) \
- ? ( \
- (LL_ADC_IsEnabled(ADC1) | \
- LL_ADC_IsEnabled(ADC2) ) \
- ) \
- : \
- ( \
- LL_ADC_IsEnabled(ADC3) \
- ) \
- )
-#elif defined(ADC1) && defined(ADC2)
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- (LL_ADC_IsEnabled(ADC1) | \
- LL_ADC_IsEnabled(ADC2) )
-#else
-#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
- LL_ADC_IsEnabled(ADC1)
-#endif
-
-/**
- * @brief Helper macro to define the ADC conversion data full-scale digital
- * value corresponding to the selected ADC resolution.
- * @note ADC conversion data full-scale corresponds to voltage range
- * determined by analog voltage references Vref+ and Vref-
- * (refer to reference manual).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- */
-#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- (0xFFFU)
-
-
-/**
- * @brief Helper macro to calculate the voltage (unit: mVolt)
- * corresponding to a ADC conversion data (unit: digital value).
- * @note Analog reference voltage (Vref+) must be known from
- * user board environment or can be calculated using ADC measurement.
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
- * (unit: digital value).
- * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- */
-#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
- __ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- )
-
-
-/**
- * @brief Helper macro to calculate the temperature (unit: degree Celsius)
- * from ADC conversion data of internal temperature sensor.
- * @note Computation is using temperature sensor typical values
- * (refer to device datasheet).
- * @note Calculation formula:
- * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
- * / Avg_Slope + CALx_TEMP
- * with TS_ADC_DATA = temperature sensor raw data measured by ADC
- * (unit: digital value)
- * Avg_Slope = temperature sensor slope
- * (unit: uV/Degree Celsius)
- * TS_TYP_CALx_VOLT = temperature sensor digital value at
- * temperature CALx_TEMP (unit: mV)
- * Caution: Calculation relevancy under reserve the temperature sensor
- * of the current device has characteristics in line with
- * datasheet typical values.
- * If temperature sensor calibration values are available on
- * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
- * temperature calculation will be more accurate using
- * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
- * @note As calculation input, the analog reference voltage (Vref+) must be
- * defined as it impacts the ADC LSB equivalent voltage.
- * @note Analog reference voltage (Vref+) must be known from
- * user board environment or can be calculated using ADC measurement.
- * @note ADC measurement data must correspond to a resolution of 12bits
- * (full scale digital value 4095). If not the case, the data must be
- * preliminarily rescaled to an equivalent resolution of 12 bits.
- * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
- * On STM32F1, refer to device datasheet parameter "Avg_Slope".
- * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
- * On STM32F1, refer to device datasheet parameter "V25".
- * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
- * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
- * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
- * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
- * This parameter can be one of the following values:
- * @arg @ref LL_ADC_RESOLUTION_12B
- * @retval Temperature (unit: degree Celsius)
- */
-#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
- __TEMPSENSOR_TYP_CALX_V__,\
- __TEMPSENSOR_CALX_TEMP__,\
- __VREFANALOG_VOLTAGE__,\
- __TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((( ( \
- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
- * 1000) \
- - \
- (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
- * 1000) \
- ) \
- ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
- ) + (__TEMPSENSOR_CALX_TEMP__) \
- )
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
- * @{
- */
-
-/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
- * @{
- */
-/* Note: LL ADC functions to set DMA transfer are located into sections of */
-/* configuration of ADC instance, groups and multimode (if available): */
-/* @ref LL_ADC_REG_SetDMATransfer(), ... */
-
-/**
- * @brief Function to help to configure DMA transfer from ADC: retrieve the
- * ADC register address from ADC instance and a list of ADC registers
- * intended to be used (most commonly) with DMA transfer.
- * @note These ADC registers are data registers:
- * when ADC conversion data is available in ADC data registers,
- * ADC generates a DMA transfer request.
- * @note This macro is intended to be used with LL DMA driver, refer to
- * function "LL_DMA_ConfigAddresses()".
- * Example:
- * LL_DMA_ConfigAddresses(DMA1,
- * LL_DMA_CHANNEL_1,
- * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
- * (uint32_t)&< array or variable >,
- * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
- * @note For devices with several ADC: in multimode, some devices
- * use a different data register outside of ADC instance scope
- * (common data register). This macro manages this register difference,
- * only ADC instance has to be set as parameter.
- * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer
- * capability, not ADC2 (ADC2 and ADC3 instances not available on
- * all devices).
- * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3.
- * Therefore, the corresponding parameter of data transfer
- * for multimode can be used only with ADC1 and ADC2.
- * (ADC2 and ADC3 instances not available on all devices).
- * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
- * @param ADCx ADC instance
- * @param Register This parameter can be one of the following values:
- * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
- * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
- *
- * (1) Available on devices with several ADC instances.
- * @retval ADC register address
- */
-#if defined(ADC_MULTIMODE_SUPPORT)
-__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
-{
- register uint32_t data_reg_addr = 0U;
-
- if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
- {
- /* Retrieve address of register DR */
- data_reg_addr = (uint32_t)&(ADCx->DR);
- }
- else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
- {
- /* Retrieve address of register of multimode data */
- data_reg_addr = (uint32_t)&(ADC12_COMMON->DR);
- }
-
- return data_reg_addr;
-}
-#else
-__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
-{
- /* Retrieve address of register DR */
- return (uint32_t)&(ADCx->DR);
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
- * @{
- */
-
-/**
- * @brief Set parameter common to several ADC: measurement path to internal
- * channels (VrefInt, temperature sensor, ...).
- * @note One or several values can be selected.
- * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * @note Stabilization time of measurement path to internal channel:
- * After enabling internal paths, before starting ADC conversion,
- * a delay is required for internal voltage reference and
- * temperature sensor stabilization time.
- * Refer to device datasheet.
- * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
- * @note ADC internal channel sampling time constraint:
- * For ADC conversion of internal channels,
- * a sampling time minimum value is required.
- * Refer to device datasheet.
- * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @param PathInternal This parameter can be a combination of the following values:
- * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
-{
- MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
-}
-
-/**
- * @brief Get parameter common to several ADC: measurement path to internal
- * channels (VrefInt, temperature sensor, ...).
- * @note One or several values can be selected.
- * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
- * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Returned value can be a combination of the following values:
- * @arg @ref LL_ADC_PATH_INTERNAL_NONE
- * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
- * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
- */
-__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
- * @{
- */
-
-/**
- * @brief Set ADC conversion data alignment.
- * @note Refer to reference manual for alignments formats
- * dependencies to ADC resolutions.
- * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
- * @param ADCx ADC instance
- * @param DataAlignment This parameter can be one of the following values:
- * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
- * @arg @ref LL_ADC_DATA_ALIGN_LEFT
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
-{
- MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
-}
-
-/**
- * @brief Get ADC conversion data alignment.
- * @note Refer to reference manual for alignments formats
- * dependencies to ADC resolutions.
- * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
- * @arg @ref LL_ADC_DATA_ALIGN_LEFT
- */
-__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
-}
-
-/**
- * @brief Set ADC sequencers scan mode, for all ADC groups
- * (group regular, group injected).
- * @note According to sequencers scan mode :
- * - If disabled: ADC conversion is performed in unitary conversion
- * mode (one channel converted, that defined in rank 1).
- * Configuration of sequencers of all ADC groups
- * (sequencer scan length, ...) is discarded: equivalent to
- * scan length of 1 rank.
- * - If enabled: ADC conversions are performed in sequence conversions
- * mode, according to configuration of sequencers of
- * each ADC group (sequencer scan length, ...).
- * Refer to function @ref LL_ADC_REG_SetSequencerLength()
- * and to function @ref LL_ADC_INJ_SetSequencerLength().
- * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
- * @param ADCx ADC instance
- * @param ScanMode This parameter can be one of the following values:
- * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
-{
- MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
-}
-
-/**
- * @brief Get ADC sequencers scan mode, for all ADC groups
- * (group regular, group injected).
- * @note According to sequencers scan mode :
- * - If disabled: ADC conversion is performed in unitary conversion
- * mode (one channel converted, that defined in rank 1).
- * Configuration of sequencers of all ADC groups
- * (sequencer scan length, ...) is discarded: equivalent to
- * scan length of 1 rank.
- * - If enabled: ADC conversions are performed in sequence conversions
- * mode, according to configuration of sequencers of
- * each ADC group (sequencer scan length, ...).
- * Refer to function @ref LL_ADC_REG_SetSequencerLength()
- * and to function @ref LL_ADC_INJ_SetSequencerLength().
- * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
- */
-__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
- * @{
- */
-
-/**
- * @brief Set ADC group regular conversion trigger source:
- * internal (SW start) or from external IP (timer event,
- * external interrupt line).
- * @note On this STM32 serie, external trigger is set with trigger polarity:
- * rising edge (only trigger polarity available on this STM32 serie).
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
- * @param ADCx ADC instance
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
- *
- * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
- * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
- * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
- * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
-{
-/* Note: On this STM32 serie, ADC group regular external trigger edge */
-/* is used to perform a ADC conversion start. */
-/* This function does not set external trigger edge. */
-/* This feature is set using function */
-/* @ref LL_ADC_REG_StartConversionExtTrig(). */
- MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
-}
-
-/**
- * @brief Get ADC group regular conversion trigger source:
- * internal (SW start) or from external IP (timer event,
- * external interrupt line).
- * @note To determine whether group regular trigger source is
- * internal (SW start) or external, without detail
- * of which peripheral is selected as external trigger,
- * (equivalent to
- * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
- * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
- * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
- *
- * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
- * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
- * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
- * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
-}
-
-/**
- * @brief Get ADC group regular conversion trigger source internal (SW start)
- or external.
- * @note In case of group regular trigger source set to external trigger,
- * to determine which peripheral is selected as external trigger,
- * use function @ref LL_ADC_REG_GetTriggerSource().
- * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
- * @param ADCx ADC instance
- * @retval Value "0" if trigger source external trigger
- * Value "1" if trigger source SW start.
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
-{
- return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
-}
-
-
-/**
- * @brief Set ADC group regular sequencer length and scan direction.
- * @note Description of ADC group regular sequencer features:
- * - For devices with sequencer fully configurable
- * (function "LL_ADC_REG_SetSequencerRanks()" available):
- * sequencer length and each rank affectation to a channel
- * are configurable.
- * This function performs configuration of:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerRanks()".
- * - For devices with sequencer not fully configurable
- * (function "LL_ADC_REG_SetSequencerChannels()" available):
- * sequencer length and each rank affectation to a channel
- * are defined by channel number.
- * This function performs configuration of:
- * - Sequence length: Number of ranks in the scan sequence is
- * defined by number of channels set in the sequence,
- * rank of each channel is fixed by channel HW number.
- * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from lowest channel number to
- * highest channel number).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerChannels()".
- * @note On this STM32 serie, group regular sequencer configuration
- * is conditioned to ADC instance sequencer mode.
- * If ADC instance sequencer mode is disabled, sequencers of
- * all groups (group regular, group injected) can be configured
- * but their execution is disabled (limited to rank 1).
- * Refer to function @ref LL_ADC_SetSequencersScanMode().
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
- * @param ADCx ADC instance
- * @param SequencerNbRanks This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
-{
- MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
-}
-
-/**
- * @brief Get ADC group regular sequencer length and scan direction.
- * @note Description of ADC group regular sequencer features:
- * - For devices with sequencer fully configurable
- * (function "LL_ADC_REG_SetSequencerRanks()" available):
- * sequencer length and each rank affectation to a channel
- * are configurable.
- * This function retrieves:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerRanks()".
- * - For devices with sequencer not fully configurable
- * (function "LL_ADC_REG_SetSequencerChannels()" available):
- * sequencer length and each rank affectation to a channel
- * are defined by channel number.
- * This function retrieves:
- * - Sequence length: Number of ranks in the scan sequence is
- * defined by number of channels set in the sequence,
- * rank of each channel is fixed by channel HW number.
- * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from lowest channel number to
- * highest channel number).
- * Sequencer ranks are selected using
- * function "LL_ADC_REG_SetSequencerChannels()".
- * @note On this STM32 serie, group regular sequencer configuration
- * is conditioned to ADC instance sequencer mode.
- * If ADC instance sequencer mode is disabled, sequencers of
- * all groups (group regular, group injected) can be configured
- * but their execution is disabled (limited to rank 1).
- * Refer to function @ref LL_ADC_SetSequencersScanMode().
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
- * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
-}
-
-/**
- * @brief Set ADC group regular sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @note It is not possible to enable both ADC group regular
- * continuous mode and sequencer discontinuous mode.
- * @note It is not possible to enable both ADC auto-injected mode
- * and ADC group regular sequencer discontinuous mode.
- * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
- * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
- * @param ADCx ADC instance
- * @param SeqDiscont This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
-{
- MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
-}
-
-/**
- * @brief Get ADC group regular sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
- * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
- * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
-}
-
-/**
- * @brief Set ADC group regular sequence: channel on the selected
- * scan sequence rank.
- * @note This function performs configuration of:
- * - Channels ordering into each rank of scan sequence:
- * whatever channel can be placed into whatever rank.
- * @note On this STM32 serie, ADC group regular sequencer is
- * fully configurable: sequencer length and each rank
- * affectation to a channel are configurable.
- * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
- * @note Depending on devices and packages, some channels may not be available.
- * Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
- * TempSensor, ...), measurement paths to internal channels must be
- * enabled separately.
- * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
- * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
- * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
- * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
- * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
- * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
- * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_RANK_1
- * @arg @ref LL_ADC_REG_RANK_2
- * @arg @ref LL_ADC_REG_RANK_3
- * @arg @ref LL_ADC_REG_RANK_4
- * @arg @ref LL_ADC_REG_RANK_5
- * @arg @ref LL_ADC_REG_RANK_6
- * @arg @ref LL_ADC_REG_RANK_7
- * @arg @ref LL_ADC_REG_RANK_8
- * @arg @ref LL_ADC_REG_RANK_9
- * @arg @ref LL_ADC_REG_RANK_10
- * @arg @ref LL_ADC_REG_RANK_11
- * @arg @ref LL_ADC_REG_RANK_12
- * @arg @ref LL_ADC_REG_RANK_13
- * @arg @ref LL_ADC_REG_RANK_14
- * @arg @ref LL_ADC_REG_RANK_15
- * @arg @ref LL_ADC_REG_RANK_16
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
-{
- /* Set bits with content of parameter "Channel" with bits position */
- /* in register and register position depending on parameter "Rank". */
- /* Parameters "Rank" and "Channel" are used with masks because containing */
- /* other bits reserved for other purpose. */
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
- (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
-}
-
-/**
- * @brief Get ADC group regular sequence: channel on the selected
- * scan sequence rank.
- * @note On this STM32 serie, ADC group regular sequencer is
- * fully configurable: sequencer length and each rank
- * affectation to a channel are configurable.
- * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
- * @note Depending on devices and packages, some channels may not be available.
- * Refer to device datasheet for channels availability.
- * @note Usage of the returned channel number:
- * - To reinject this channel into another function LL_ADC_xxx:
- * the returned channel number is only partly formatted on definition
- * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- * with parts of literals LL_ADC_CHANNEL_x or using
- * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Then the selected literal LL_ADC_CHANNEL_x can be used
- * as parameter for another function.
- * - To get the channel number in decimal format:
- * process the returned value with the helper macro
- * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
- * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
- * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
- * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
- * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
- * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
- * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_RANK_1
- * @arg @ref LL_ADC_REG_RANK_2
- * @arg @ref LL_ADC_REG_RANK_3
- * @arg @ref LL_ADC_REG_RANK_4
- * @arg @ref LL_ADC_REG_RANK_5
- * @arg @ref LL_ADC_REG_RANK_6
- * @arg @ref LL_ADC_REG_RANK_7
- * @arg @ref LL_ADC_REG_RANK_8
- * @arg @ref LL_ADC_REG_RANK_9
- * @arg @ref LL_ADC_REG_RANK_10
- * @arg @ref LL_ADC_REG_RANK_11
- * @arg @ref LL_ADC_REG_RANK_12
- * @arg @ref LL_ADC_REG_RANK_13
- * @arg @ref LL_ADC_REG_RANK_14
- * @arg @ref LL_ADC_REG_RANK_15
- * @arg @ref LL_ADC_REG_RANK_16
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- * (1) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
-
- return (uint32_t) (READ_BIT(*preg,
- ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
- >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
- );
-}
-
-/**
- * @brief Set ADC continuous conversion mode on ADC group regular.
- * @note Description of ADC continuous conversion mode:
- * - single mode: one conversion per trigger
- * - continuous mode: after the first trigger, following
- * conversions launched successively automatically.
- * @note It is not possible to enable both ADC group regular
- * continuous mode and sequencer discontinuous mode.
- * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
- * @param ADCx ADC instance
- * @param Continuous This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_CONV_SINGLE
- * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
-{
- MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
-}
-
-/**
- * @brief Get ADC continuous conversion mode on ADC group regular.
- * @note Description of ADC continuous conversion mode:
- * - single mode: one conversion per trigger
- * - continuous mode: after the first trigger, following
- * conversions launched successively automatically.
- * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_CONV_SINGLE
- * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
-}
-
-/**
- * @brief Set ADC group regular conversion data transfer: no transfer or
- * transfer by DMA, and DMA requests mode.
- * @note If transfer by DMA selected, specifies the DMA requests
- * mode:
- * - Limited mode (One shot mode): DMA transfer requests are stopped
- * when number of DMA data transfers (number of
- * ADC conversions) is reached.
- * This ADC mode is intended to be used with DMA mode non-circular.
- * - Unlimited mode: DMA transfer requests are unlimited,
- * whatever number of DMA data transfers (number of
- * ADC conversions).
- * This ADC mode is intended to be used with DMA mode circular.
- * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- * mode non-circular:
- * when DMA transfers size will be reached, DMA will stop transfers of
- * ADC conversions data ADC will raise an overrun error
- * (overrun flag and interruption if enabled).
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_ADC_DMA_GetRegAddr().
- * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
- * @param ADCx ADC instance
- * @param DMATransfer This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
-{
- MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
-}
-
-/**
- * @brief Get ADC group regular conversion data transfer: no transfer or
- * transfer by DMA, and DMA requests mode.
- * @note If transfer by DMA selected, specifies the DMA requests
- * mode:
- * - Limited mode (One shot mode): DMA transfer requests are stopped
- * when number of DMA data transfers (number of
- * ADC conversions) is reached.
- * This ADC mode is intended to be used with DMA mode non-circular.
- * - Unlimited mode: DMA transfer requests are unlimited,
- * whatever number of DMA data transfers (number of
- * ADC conversions).
- * This ADC mode is intended to be used with DMA mode circular.
- * @note If ADC DMA requests mode is set to unlimited and DMA is set to
- * mode non-circular:
- * when DMA transfers size will be reached, DMA will stop transfers of
- * ADC conversions data ADC will raise an overrun error
- * (overrun flag and interruption if enabled).
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_ADC_DMA_GetRegAddr().
- * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
- * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
- * @{
- */
-
-/**
- * @brief Set ADC group injected conversion trigger source:
- * internal (SW start) or from external IP (timer event,
- * external interrupt line).
- * @note On this STM32 serie, external trigger is set with trigger polarity:
- * rising edge (only trigger polarity available on this STM32 serie).
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
- * @param ADCx ADC instance
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
- *
- * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
- * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
- * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
- * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
-{
-/* Note: On this STM32 serie, ADC group injected external trigger edge */
-/* is used to perform a ADC conversion start. */
-/* This function does not set external trigger edge. */
-/* This feature is set using function */
-/* @ref LL_ADC_INJ_StartConversionExtTrig(). */
- MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
-}
-
-/**
- * @brief Get ADC group injected conversion trigger source:
- * internal (SW start) or from external IP (timer event,
- * external interrupt line).
- * @note To determine whether group injected trigger source is
- * internal (SW start) or external, without detail
- * of which peripheral is selected as external trigger,
- * (equivalent to
- * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
- * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
- * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
- *
- * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
- * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
- * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
- * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
-}
-
-/**
- * @brief Get ADC group injected conversion trigger source internal (SW start)
- or external
- * @note In case of group injected trigger source set to external trigger,
- * to determine which peripheral is selected as external trigger,
- * use function @ref LL_ADC_INJ_GetTriggerSource.
- * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
- * @param ADCx ADC instance
- * @retval Value "0" if trigger source external trigger
- * Value "1" if trigger source SW start.
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
-{
- return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
-}
-
-/**
- * @brief Set ADC group injected sequencer length and scan direction.
- * @note This function performs configuration of:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * @note On this STM32 serie, group injected sequencer configuration
- * is conditioned to ADC instance sequencer mode.
- * If ADC instance sequencer mode is disabled, sequencers of
- * all groups (group regular, group injected) can be configured
- * but their execution is disabled (limited to rank 1).
- * Refer to function @ref LL_ADC_SetSequencersScanMode().
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
- * @param ADCx ADC instance
- * @param SequencerNbRanks This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
-{
- MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
-}
-
-/**
- * @brief Get ADC group injected sequencer length and scan direction.
- * @note This function retrieves:
- * - Sequence length: Number of ranks in the scan sequence.
- * - Sequence direction: Unless specified in parameters, sequencer
- * scan direction is forward (from rank 1 to rank n).
- * @note On this STM32 serie, group injected sequencer configuration
- * is conditioned to ADC instance sequencer mode.
- * If ADC instance sequencer mode is disabled, sequencers of
- * all groups (group regular, group injected) can be configured
- * but their execution is disabled (limited to rank 1).
- * Refer to function @ref LL_ADC_SetSequencersScanMode().
- * @note Sequencer disabled is equivalent to sequencer of 1 rank:
- * ADC conversion on only 1 channel.
- * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
- * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
-}
-
-/**
- * @brief Set ADC group injected sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @note It is not possible to enable both ADC group injected
- * auto-injected mode and sequencer discontinuous mode.
- * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
- * @param ADCx ADC instance
- * @param SeqDiscont This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
-{
- MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
-}
-
-/**
- * @brief Get ADC group injected sequencer discontinuous mode:
- * sequence subdivided and scan conversions interrupted every selected
- * number of ranks.
- * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
- * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
-}
-
-/**
- * @brief Set ADC group injected sequence: channel on the selected
- * sequence rank.
- * @note Depending on devices and packages, some channels may not be available.
- * Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
- * TempSensor, ...), measurement paths to internal channels must be
- * enabled separately.
- * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
-{
- /* Set bits with content of parameter "Channel" with bits position */
- /* in register depending on parameter "Rank". */
- /* Parameters "Rank" and "Channel" are used with masks because containing */
- /* other bits reserved for other purpose. */
- register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
-
- MODIFY_REG(ADCx->JSQR,
- ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
- (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
-}
-
-/**
- * @brief Get ADC group injected sequence: channel on the selected
- * sequence rank.
- * @note Depending on devices and packages, some channels may not be available.
- * Refer to device datasheet for channels availability.
- * @note Usage of the returned channel number:
- * - To reinject this channel into another function LL_ADC_xxx:
- * the returned channel number is only partly formatted on definition
- * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- * with parts of literals LL_ADC_CHANNEL_x or using
- * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Then the selected literal LL_ADC_CHANNEL_x can be used
- * as parameter for another function.
- * - To get the channel number in decimal format:
- * process the returned value with the helper macro
- * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
- * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
- * (1) For ADC channel read back from ADC register,
- * comparison with internal channel parameter to be done
- * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
-{
- register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
-
- return (uint32_t)(READ_BIT(ADCx->JSQR,
- ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
- >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
- );
-}
-
-/**
- * @brief Set ADC group injected conversion trigger:
- * independent or from ADC group regular.
- * @note This mode can be used to extend number of data registers
- * updated after one ADC conversion trigger and with data
- * permanently kept (not erased by successive conversions of scan of
- * ADC sequencer ranks), up to 5 data registers:
- * 1 data register on ADC group regular, 4 data registers
- * on ADC group injected.
- * @note If ADC group injected injected trigger source is set to an
- * external trigger, this feature must be must be set to
- * independent trigger.
- * ADC group injected automatic trigger is compliant only with
- * group injected trigger source set to SW start, without any
- * further action on ADC group injected conversion start or stop:
- * in this case, ADC group injected is controlled only
- * from ADC group regular.
- * @note It is not possible to enable both ADC group injected
- * auto-injected mode and sequencer discontinuous mode.
- * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
- * @param ADCx ADC instance
- * @param TrigAuto This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
- * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
-{
- MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
-}
-
-/**
- * @brief Get ADC group injected conversion trigger:
- * independent or from ADC group regular.
- * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
- * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
-}
-
-/**
- * @brief Set ADC group injected offset.
- * @note It sets:
- * - ADC group injected rank to which the offset programmed
- * will be applied
- * - Offset level (offset to be subtracted from the raw
- * converted data).
- * Caution: Offset format is dependent to ADC resolution:
- * offset has to be left-aligned on bit 11, the LSB (right bits)
- * are set to 0.
- * @note Offset cannot be enabled or disabled.
- * To emulate offset disabled, set an offset value equal to 0.
- * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
- * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
- * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
- * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- ADC_JOFR1_JOFFSET1,
- OffsetLevel);
-}
-
-/**
- * @brief Get ADC group injected offset.
- * @note It gives offset level (offset to be subtracted from the raw converted data).
- * Caution: Offset format is dependent to ADC resolution:
- * offset has to be left-aligned on bit 11, the LSB (right bits)
- * are set to 0.
- * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
- * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
- * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
- * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
-
- return (uint32_t)(READ_BIT(*preg,
- ADC_JOFR1_JOFFSET1)
- );
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
- * @{
- */
-
-/**
- * @brief Set sampling time of the selected ADC channel
- * Unit: ADC clock cycles.
- * @note On this device, sampling time is on channel scope: independently
- * of channel mapped on ADC group regular or injected.
- * @note In case of internal channel (VrefInt, TempSensor, ...) to be
- * converted:
- * sampling time constraints must be respected (sampling time can be
- * adjusted in function of ADC clock frequency and sampling time
- * setting).
- * Refer to device datasheet for timings values (parameters TS_vrefint,
- * TS_temp, ...).
- * @note Conversion time is the addition of sampling time and processing time.
- * Refer to reference manual for ADC processing time of
- * this STM32 serie.
- * @note In case of ADC conversion of internal channel (VrefInt,
- * temperature sensor, ...), a sampling time minimum value
- * is required.
- * Refer to device datasheet.
- * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
- * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
- * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
- * @param ADCx ADC instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @param SamplingTime This parameter can be one of the following values:
- * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
- * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
-{
- /* Set bits with content of parameter "SamplingTime" with bits position */
- /* in register and register position depending on parameter "Channel". */
- /* Parameter "Channel" is used with masks because containing */
- /* other bits reserved for other purpose. */
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
- SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get sampling time of the selected ADC channel
- * Unit: ADC clock cycles.
- * @note On this device, sampling time is on channel scope: independently
- * of channel mapped on ADC group regular or injected.
- * @note Conversion time is the addition of sampling time and processing time.
- * Refer to reference manual for ADC processing time of
- * this STM32 serie.
- * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
- * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
- * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
- * @param ADCx ADC instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_ADC_CHANNEL_0
- * @arg @ref LL_ADC_CHANNEL_1
- * @arg @ref LL_ADC_CHANNEL_2
- * @arg @ref LL_ADC_CHANNEL_3
- * @arg @ref LL_ADC_CHANNEL_4
- * @arg @ref LL_ADC_CHANNEL_5
- * @arg @ref LL_ADC_CHANNEL_6
- * @arg @ref LL_ADC_CHANNEL_7
- * @arg @ref LL_ADC_CHANNEL_8
- * @arg @ref LL_ADC_CHANNEL_9
- * @arg @ref LL_ADC_CHANNEL_10
- * @arg @ref LL_ADC_CHANNEL_11
- * @arg @ref LL_ADC_CHANNEL_12
- * @arg @ref LL_ADC_CHANNEL_13
- * @arg @ref LL_ADC_CHANNEL_14
- * @arg @ref LL_ADC_CHANNEL_15
- * @arg @ref LL_ADC_CHANNEL_16
- * @arg @ref LL_ADC_CHANNEL_17
- * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
- * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
- * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
- * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
- */
-__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
-
- return (uint32_t)(READ_BIT(*preg,
- ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
- >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
- );
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
- * @{
- */
-
-/**
- * @brief Set ADC analog watchdog monitored channels:
- * a single channel or all channels,
- * on ADC groups regular and-or injected.
- * @note Once monitored channels are selected, analog watchdog
- * is enabled.
- * @note In case of need to define a single channel to monitor
- * with analog watchdog from sequencer channel definition,
- * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
- * instance:
- * - AWD standard (instance AWD1):
- * - channels monitored: can monitor 1 channel or all channels.
- * - groups monitored: ADC groups regular and-or injected.
- * - resolution: resolution is not limited (corresponds to
- * ADC resolution configured).
- * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
- * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
- * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
- * @param ADCx ADC instance
- * @param AWDChannelGroup This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
- * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
- *
- * (1) On STM32F1, parameter available only on ADC instance: ADC1.
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
-{
- MODIFY_REG(ADCx->CR1,
- (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
- AWDChannelGroup);
-}
-
-/**
- * @brief Get ADC analog watchdog monitored channel.
- * @note Usage of the returned channel number:
- * - To reinject this channel into another function LL_ADC_xxx:
- * the returned channel number is only partly formatted on definition
- * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
- * with parts of literals LL_ADC_CHANNEL_x or using
- * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Then the selected literal LL_ADC_CHANNEL_x can be used
- * as parameter for another function.
- * - To get the channel number in decimal format:
- * process the returned value with the helper macro
- * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
- * Applicable only when the analog watchdog is set to monitor
- * one channel.
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
- * instance:
- * - AWD standard (instance AWD1):
- * - channels monitored: can monitor 1 channel or all channels.
- * - groups monitored: ADC groups regular and-or injected.
- * - resolution: resolution is not limited (corresponds to
- * ADC resolution configured).
- * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
- * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
- * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
- * @param ADCx ADC instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_AWD_DISABLE
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
- * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
- * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
- * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
- */
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
-{
- return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
-}
-
-/**
- * @brief Set ADC analog watchdog threshold value of threshold
- * high or low.
- * @note On this STM32 serie, there is only 1 kind of analog watchdog
- * instance:
- * - AWD standard (instance AWD1):
- * - channels monitored: can monitor 1 channel or all channels.
- * - groups monitored: ADC groups regular and-or injected.
- * - resolution: resolution is not limited (corresponds to
- * ADC resolution configured).
- * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
- * LTR LT LL_ADC_SetAnalogWDThresholds
- * @param ADCx ADC instance
- * @param AWDThresholdsHighLow This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
- * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
- * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
-
- MODIFY_REG(*preg,
- ADC_HTR_HT,
- AWDThresholdValue);
-}
-
-/**
- * @brief Get ADC analog watchdog threshold value of threshold high or
- * threshold low.
- * @note In case of ADC resolution different of 12 bits,
- * analog watchdog thresholds data require a specific shift.
- * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
- * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
- * LTR LT LL_ADC_GetAnalogWDThresholds
- * @param ADCx ADC instance
- * @param AWDThresholdsHighLow This parameter can be one of the following values:
- * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
- * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
-*/
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
-
- return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
- * @{
- */
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Set ADC multimode configuration to operate in independent mode
- * or multimode (for devices with several ADC instances).
- * @note If multimode configuration: the selected ADC instance is
- * either master or slave depending on hardware.
- * Refer to reference manual.
- * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @param Multimode This parameter can be one of the following values:
- * @arg @ref LL_ADC_MULTI_INDEPENDENT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
-{
- MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode);
-}
-
-/**
- * @brief Get ADC multimode configuration to operate in independent mode
- * or multimode (for devices with several ADC instances).
- * @note If multimode configuration: the selected ADC instance is
- * either master or slave depending on hardware.
- * Refer to reference manual.
- * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_ADC_MULTI_INDEPENDENT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
- * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
- * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
- * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
- */
-__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD));
-}
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
- * @{
- */
-
-/**
- * @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
- * ADC internal analog stabilization is required before performing a
- * ADC conversion start.
- * Refer to device datasheet, parameter tSTAB.
- * @rmtoll CR2 ADON LL_ADC_Enable
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
-{
- SET_BIT(ADCx->CR2, ADC_CR2_ADON);
-}
-
-/**
- * @brief Disable the selected ADC instance.
- * @rmtoll CR2 ADON LL_ADC_Disable
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
-{
- CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
-}
-
-/**
- * @brief Get the selected ADC instance enable state.
- * @rmtoll CR2 ADON LL_ADC_IsEnabled
- * @param ADCx ADC instance
- * @retval 0: ADC is disabled, 1: ADC is enabled.
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
-{
- return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
-}
-
-/**
- * @brief Start ADC calibration in the mode single-ended
- * or differential (for devices with differential mode available).
- * @note On this STM32 serie, before starting a calibration,
- * ADC must be disabled.
- * A minimum number of ADC clock cycles are required
- * between ADC disable state and calibration start.
- * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
- * @note On this STM32 serie, hardware prerequisite before starting a calibration:
- the ADC must have been in power-on state for at least
- two ADC clock cycles.
- * @rmtoll CR2 CAL LL_ADC_StartCalibration
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
-{
- SET_BIT(ADCx->CR2, ADC_CR2_CAL);
-}
-
-/**
- * @brief Get ADC calibration state.
- * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
- * @param ADCx ADC instance
- * @retval 0: calibration complete, 1: calibration in progress.
- */
-__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
-{
- return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
- * @{
- */
-
-/**
- * @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant only for
- * internal trigger (SW start), not for external trigger:
- * - If ADC trigger has been set to software start, ADC conversion
- * starts immediately.
- * - If ADC trigger has been set to external trigger, ADC conversion
- * start must be performed using function
- * @ref LL_ADC_REG_StartConversionExtTrig().
- * (if external trigger edge would have been set during ADC other
- * settings, ADC conversion would start at trigger event
- * as soon as ADC is enabled).
- * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
-{
- SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
-}
-
-/**
- * @brief Start ADC group regular conversion from external trigger.
- * @note ADC conversion will start at next trigger event (on the selected
- * trigger edge) following the ADC start conversion command.
- * @note On this STM32 serie, this function is relevant for
- * ADC conversion start from external trigger.
- * If internal trigger (SW start) is needed, perform ADC conversion
- * start using function @ref LL_ADC_REG_StartConversionSWStart().
- * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
- * @param ExternalTriggerEdge This parameter can be one of the following values:
- * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
-{
- SET_BIT(ADCx->CR2, ExternalTriggerEdge);
-}
-
-/**
- * @brief Stop ADC group regular conversion from external trigger.
- * @note No more ADC conversion will start at next trigger event
- * following the ADC stop conversion command.
- * If a conversion is on-going, it will be completed.
- * @note On this STM32 serie, there is no specific command
- * to stop a conversion on-going or to stop ADC converting
- * in continuous mode. These actions can be performed
- * using function @ref LL_ADC_Disable().
- * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
-{
- CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTSEL);
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * all ADC configurations: all ADC resolutions and
- * all oversampling increased data width (for devices
- * with feature oversampling).
- * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
- * @param ADCx ADC instance
- * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
-{
- return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * ADC resolution 12 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_REG_ReadConversionData32.
- * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
- * @param ADCx ADC instance
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
-{
- return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
-}
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Get ADC multimode conversion data of ADC master, ADC slave
- * or raw data with ADC master and slave concatenated.
- * @note If raw data with ADC master and slave concatenated is retrieved,
- * a macro is available to get the conversion data of
- * ADC master or ADC slave: see helper macro
- * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * (however this macro is mainly intended for multimode
- * transfer by DMA, because this function can do the same
- * by getting multimode conversion data of ADC master or ADC slave
- * separately).
- * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n
- * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32
- * @param ADCx ADC instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @param ConversionData This parameter can be one of the following values:
- * @arg @ref LL_ADC_MULTI_MASTER
- * @arg @ref LL_ADC_MULTI_SLAVE
- * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
- * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData)
-{
- return (uint32_t)(READ_BIT(ADCx->DR,
- ADC_DR_ADC2DATA)
- >> POSITION_VAL(ConversionData)
- );
-}
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
- * @{
- */
-
-/**
- * @brief Start ADC group injected conversion.
- * @note On this STM32 serie, this function is relevant only for
- * internal trigger (SW start), not for external trigger:
- * - If ADC trigger has been set to software start, ADC conversion
- * starts immediately.
- * - If ADC trigger has been set to external trigger, ADC conversion
- * start must be performed using function
- * @ref LL_ADC_INJ_StartConversionExtTrig().
- * (if external trigger edge would have been set during ADC other
- * settings, ADC conversion would start at trigger event
- * as soon as ADC is enabled).
- * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
-{
- SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
-}
-
-/**
- * @brief Start ADC group injected conversion from external trigger.
- * @note ADC conversion will start at next trigger event (on the selected
- * trigger edge) following the ADC start conversion command.
- * @note On this STM32 serie, this function is relevant for
- * ADC conversion start from external trigger.
- * If internal trigger (SW start) is needed, perform ADC conversion
- * start using function @ref LL_ADC_INJ_StartConversionSWStart().
- * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
- * @param ExternalTriggerEdge This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
-{
- SET_BIT(ADCx->CR2, ExternalTriggerEdge);
-}
-
-/**
- * @brief Stop ADC group injected conversion from external trigger.
- * @note No more ADC conversion will start at next trigger event
- * following the ADC stop conversion command.
- * If a conversion is on-going, it will be completed.
- * @note On this STM32 serie, there is no specific command
- * to stop a conversion on-going or to stop ADC converting
- * in continuous mode. These actions can be performed
- * using function @ref LL_ADC_Disable().
- * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
-{
- CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);
-}
-
-/**
- * @brief Get ADC group regular conversion data, range fit for
- * all ADC configurations: all ADC resolutions and
- * all oversampling increased data width (for devices
- * with feature oversampling).
- * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
- * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
- * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
- * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
-
- return (uint32_t)(READ_BIT(*preg,
- ADC_JDR1_JDATA)
- );
-}
-
-/**
- * @brief Get ADC group injected conversion data, range fit for
- * ADC resolution 12 bits.
- * @note For devices with feature oversampling: Oversampling
- * can increase data width, function for extended range
- * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
- * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
- * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
- * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
- * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
- * @param ADCx ADC instance
- * @param Rank This parameter can be one of the following values:
- * @arg @ref LL_ADC_INJ_RANK_1
- * @arg @ref LL_ADC_INJ_RANK_2
- * @arg @ref LL_ADC_INJ_RANK_3
- * @arg @ref LL_ADC_INJ_RANK_4
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
-
- return (uint16_t)(READ_BIT(*preg,
- ADC_JDR1_JDATA)
- );
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
- * @{
- */
-
-/**
- * @brief Get flag ADC group regular end of sequence conversions.
- * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
- /* end of unitary conversion. */
- /* Flag noted as "EOC" is corresponding to flag "EOS" */
- /* in other STM32 families). */
- return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
-}
-
-
-/**
- * @brief Get flag ADC group injected end of sequence conversions.
- * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
- /* end of unitary conversion. */
- /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
- /* in other STM32 families). */
- return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
-}
-
-/**
- * @brief Get flag ADC analog watchdog 1 flag
- * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
-{
- return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
-}
-
-/**
- * @brief Clear flag ADC group regular end of sequence conversions.
- * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
- /* end of unitary conversion. */
- /* Flag noted as "EOC" is corresponding to flag "EOS" */
- /* in other STM32 families). */
- WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
-}
-
-
-/**
- * @brief Clear flag ADC group injected end of sequence conversions.
- * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
- /* end of unitary conversion. */
- /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
- /* in other STM32 families). */
- WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
-}
-
-/**
- * @brief Clear flag ADC analog watchdog 1.
- * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
-{
- WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
-}
-
-#if defined(ADC_MULTIMODE_SUPPORT)
-/**
- * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
- * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
- /* end of unitary conversion. */
- /* Flag noted as "EOC" is corresponding to flag "EOS" */
- /* in other STM32 families). */
- return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC));
-}
-
-/**
- * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
- * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
- /* end of unitary conversion. */
- /* Flag noted as "EOC" is corresponding to flag "EOS" */
- /* in other STM32 families). */
-
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
-
- return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
-}
-
-
-/**
- * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
- * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
- /* end of unitary conversion. */
- /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
- /* in other STM32 families). */
- return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
-}
-
-/**
- * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
- * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
- /* end of unitary conversion. */
- /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
- /* in other STM32 families). */
-
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
-
- return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
-}
-
-/**
- * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
- * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
-}
-
-/**
- * @brief Get flag multimode analog watchdog 1 of the ADC slave.
- * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1
- * @param ADCxy_COMMON ADC common instance
- * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
-{
- register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
-
- return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
-}
-
-#endif /* ADC_MULTIMODE_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup ADC_LL_EF_IT_Management ADC IT management
- * @{
- */
-
-/**
- * @brief Enable interruption ADC group regular end of sequence conversions.
- * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
- /* end of unitary conversion. */
- /* Flag noted as "EOC" is corresponding to flag "EOS" */
- /* in other STM32 families). */
- SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
-}
-
-
-/**
- * @brief Enable interruption ADC group injected end of sequence conversions.
- * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
- /* end of unitary conversion. */
- /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
- /* in other STM32 families). */
- SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
-}
-
-/**
- * @brief Enable interruption ADC analog watchdog 1.
- * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
-{
- SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
-}
-
-/**
- * @brief Disable interruption ADC group regular end of sequence conversions.
- * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
- /* end of unitary conversion. */
- /* Flag noted as "EOC" is corresponding to flag "EOS" */
- /* in other STM32 families). */
- CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
-}
-
-
-/**
- * @brief Disable interruption ADC group injected end of sequence conversions.
- * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
- /* end of unitary conversion. */
- /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
- /* in other STM32 families). */
- CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
-}
-
-/**
- * @brief Disable interruption ADC analog watchdog 1.
- * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
- * @param ADCx ADC instance
- * @retval None
- */
-__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
-{
- CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
-}
-
-/**
- * @brief Get state of interruption ADC group regular end of sequence conversions
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group regular */
- /* end of unitary conversion. */
- /* Flag noted as "EOC" is corresponding to flag "EOS" */
- /* in other STM32 families). */
- return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
-}
-
-
-/**
- * @brief Get state of interruption ADC group injected end of sequence conversions
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
-{
- /* Note: on this STM32 serie, there is no flag ADC group injected */
- /* end of unitary conversion. */
- /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
- /* in other STM32 families). */
- return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
-}
-
-/**
- * @brief Get state of interruption ADC analog watchdog 1
- * (0: interrupt disabled, 1: interrupt enabled).
- * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
- * @param ADCx ADC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
-{
- return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-/* Initialization of some features of ADC common parameters and multimode */
-ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
-
-/* De-initialization of ADC instance, ADC group regular and ADC group injected */
-/* (availability of ADC group injected depends on STM32 families) */
-ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
-
-/* Initialization of some features of ADC instance */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
-void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
-
-/* Initialization of some features of ADC instance and ADC group regular */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-
-/* Initialization of some features of ADC instance and ADC group injected */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
-void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* ADC1 || ADC2 || ADC3 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_adc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_bus.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1031 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_bus.h
- * @author MCD Application Team
- * @brief Header file of BUS LL module.
-
- @verbatim
- ##### RCC Limitations #####
- ==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
- from/to registers.
- (+) This delay depends on the peripheral mapping.
- (++) AHB & APB peripherals, 1 dummy read is necessary
-
- [..]
- Workarounds:
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
- inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_BUS_H
-#define __STM32F1xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-#if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
-#define RCC_AHBRSTR_SUPPORT
-#endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
- * @{
- */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
- * @{
- */
-#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
-#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
-#if defined(DMA2)
-#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
-#endif /*DMA2*/
-#if defined(ETH)
-#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
-#endif /*ETH*/
-#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
-#if defined(FSMC_Bank1)
-#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
-#endif /*FSMC_Bank1*/
-#if defined(USB_OTG_FS)
-#define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
-#endif /*USB_OTG_FS*/
-#if defined(SDIO)
-#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
-#endif /*SDIO*/
-#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
- * @{
- */
-#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
-#if defined(CAN1)
-#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
-#endif /*CAN1*/
-#if defined(CAN2)
-#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
-#endif /*CAN2*/
-#if defined(CEC)
-#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
-#endif /*CEC*/
-#if defined(DAC)
-#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
-#endif /*DAC*/
-#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
-#if defined(I2C2)
-#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
-#endif /*I2C2*/
-#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
-#if defined(SPI2)
-#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
-#endif /*SPI2*/
-#if defined(SPI3)
-#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
-#endif /*SPI3*/
-#if defined(TIM12)
-#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
-#endif /*TIM12*/
-#if defined(TIM13)
-#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
-#endif /*TIM13*/
-#if defined(TIM14)
-#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
-#endif /*TIM14*/
-#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
-#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
-#if defined(TIM4)
-#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
-#endif /*TIM4*/
-#if defined(TIM5)
-#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
-#endif /*TIM5*/
-#if defined(TIM6)
-#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
-#endif /*TIM6*/
-#if defined(TIM7)
-#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
-#endif /*TIM7*/
-#if defined(UART4)
-#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
-#endif /*UART4*/
-#if defined(UART5)
-#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
-#endif /*UART5*/
-#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
-#if defined(USART3)
-#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
-#endif /*USART3*/
-#if defined(USB)
-#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
-#endif /*USB*/
-#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
- * @{
- */
-#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
-#if defined(ADC2)
-#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
-#endif /*ADC2*/
-#if defined(ADC3)
-#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
-#endif /*ADC3*/
-#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
-#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
-#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
-#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
-#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
-#if defined(GPIOE)
-#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
-#endif /*GPIOE*/
-#if defined(GPIOF)
-#define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
-#endif /*GPIOF*/
-#if defined(GPIOG)
-#define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
-#endif /*GPIOG*/
-#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
-#if defined(TIM10)
-#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
-#endif /*TIM10*/
-#if defined(TIM11)
-#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
-#endif /*TIM11*/
-#if defined(TIM15)
-#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
-#endif /*TIM15*/
-#if defined(TIM16)
-#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
-#endif /*TIM16*/
-#if defined(TIM17)
-#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
-#endif /*TIM17*/
-#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
-#if defined(TIM8)
-#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
-#endif /*TIM8*/
-#if defined(TIM9)
-#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
-#endif /*TIM9*/
-#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
- * @{
- */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
- * @{
- */
-
-/**
- * @brief Enable AHB1 peripherals clock.
- * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHBENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHBENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB1 peripheral clock is enabled or not
- * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable AHB1 peripherals clock.
- * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHBENR, Periphs);
-}
-
-#if defined(RCC_AHBRSTR_SUPPORT)
-/**
- * @brief Force AHB1 peripherals reset.
- * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
- * @brief Release AHB1 peripherals reset.
- * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHBRSTR, Periphs);
-}
-#endif /* RCC_AHBRSTR_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
- * @{
- */
-
-/**
- * @brief Enable APB1 peripherals clock.
- * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB1 peripheral clock is enabled or not
- * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB1 peripherals clock.
- * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1ENR, Periphs);
-}
-
-/**
- * @brief Force APB1 peripherals reset.
- * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @brief Release APB1 peripherals reset.
- * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
- * @{
- */
-
-/**
- * @brief Enable APB2 peripherals clock.
- * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB2ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB2 peripheral clock is enabled or not
- * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB2 peripherals clock.
- * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
- * @brief Force APB2 peripherals reset.
- * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @brief Release APB2 peripherals reset.
- * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_BUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_cortex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,656 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL CORTEX driver contains a set of generic APIs that can be
- used by user:
- (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
- functions
- (+) Low power mode configuration (SCB register of Cortex-MCU)
- (+) MPU API to configure and enable regions
- (MPU services provided only on some devices)
- (+) API to access to MCU info (CPUID register)
- (+) API to enable fault handler (SHCSR accesses)
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_CORTEX_H
-#define __STM32F1xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-/** @defgroup CORTEX_LL CORTEX
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
- * @{
- */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
- * @{
- */
-#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
- * @{
- */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
- * @{
- */
-#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
- * @{
- */
-#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
- * @{
- */
-#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
- * @{
- */
-#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
- * @{
- */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
- * @{
- */
-#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
- * @{
- */
-#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
- * @{
- */
-#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
- * @{
- */
-
-/**
- * @brief This function checks if the Systick counter flag is active or not.
- * @note It can be used in timeout function on application side.
- * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
- return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
-}
-
-/**
- * @brief Configures the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
- if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
- {
- SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
- else
- {
- CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
-}
-
-/**
- * @brief Get the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
- return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
- * @brief Enable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Disable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Checks if the SYSTICK interrupt is enabled or disabled.
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
- return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
- * @{
- */
-
-/**
- * @brief Processor uses sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Processor uses deep sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
- * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
- * empty main application.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Do not sleep when returning to Thread mode.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
- * processor.
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
- /* Set SEVEONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
- * excluded
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
- /* Clear SEVEONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
- * @{
- */
-
-/**
- * @brief Enable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
-{
- /* Enable the system handler fault */
- SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @brief Disable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
-{
- /* Disable the system handler fault */
- CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
- * @{
- */
-
-/**
- * @brief Get Implementer code
- * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
- * @retval Value should be equal to 0x41 for ARM
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
- * @brief Get Variant number (The r value in the rnpn product revision identifier)
- * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
- * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
- * @brief Get Constant number
- * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
- * @retval Value should be equal to 0xF for Cortex-M3 devices
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
- * @brief Get Part number
- * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
- * @retval Value should be equal to 0xC23 for Cortex-M3
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
- * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
- * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
- * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
- * @{
- */
-
-/**
- * @brief Enable MPU with input options
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
- * @param Options This parameter can be one of the following values:
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
- * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
- * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
- /* Enable the MPU*/
- WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
- /* Ensure MPU settings take effects */
- __DSB();
- /* Sequence instruction fetches using update settings */
- __ISB();
-}
-
-/**
- * @brief Disable MPU
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
- /* Disable MPU*/
- WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
- * @brief Check if MPU is enabled or not
- * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
- return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
-}
-
-/**
- * @brief Enable a MPU region
- * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Enable the MPU region */
- SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @brief Configure and enable a region
- * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
- * MPU_RASR XN LL_MPU_ConfigRegion\n
- * MPU_RASR AP LL_MPU_ConfigRegion\n
- * MPU_RASR S LL_MPU_ConfigRegion\n
- * MPU_RASR C LL_MPU_ConfigRegion\n
- * MPU_RASR B LL_MPU_ConfigRegion\n
- * MPU_RASR SIZE LL_MPU_ConfigRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @param Address Value of region base address
- * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
- * @param Attributes This parameter can be a combination of the following values:
- * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
- * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
- * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
- * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
- * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
- * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
- * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
- * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
- * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
- * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
- * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
- * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
- * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Set base address */
- WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
- /* Configure MPU */
- WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
-}
-
-/**
- * @brief Disable a region
- * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
- * MPU_RASR ENABLE LL_MPU_DisableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Disable the MPU region */
- CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @}
- */
-
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_CORTEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_crc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,210 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_crc.h
- * @author MCD Application Team
- * @brief Header file of CRC LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_CRC_H
-#define __STM32F1xx_LL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(CRC)
-
-/** @defgroup CRC_LL CRC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
- * @{
- */
-
-/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in CRC register
- * @param __INSTANCE__ CRC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in CRC register
- * @param __INSTANCE__ CRC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
- * @{
- */
-
-/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
- * @{
- */
-
-/**
- * @brief Reset the CRC calculation unit.
- * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
- * @param CRCx CRC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
-{
- WRITE_REG(CRCx->CR, CRC_CR_RESET);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Write given 32-bit data to the CRC calculator
- * @rmtoll DR DR LL_CRC_FeedData32
- * @param CRCx CRC Instance
- * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
-{
- WRITE_REG(CRCx->DR, InData);
-}
-
-/**
- * @brief Return current CRC calculation result. 32 bits value is returned.
- * @rmtoll DR DR LL_CRC_ReadData32
- * @param CRCx CRC Instance
- * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
- */
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->DR));
-}
-
-/**
- * @brief Return data stored in the Independent Data(IDR) register.
- * @note This register can be used as a temporary storage location for one byte.
- * @rmtoll IDR IDR LL_CRC_Read_IDR
- * @param CRCx CRC Instance
- * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
- */
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
-{
- return (uint32_t)(READ_REG(CRCx->IDR));
-}
-
-/**
- * @brief Store data in the Independent Data(IDR) register.
- * @note This register can be used as a temporary storage location for one byte.
- * @rmtoll IDR IDR LL_CRC_Write_IDR
- * @param CRCx CRC Instance
- * @param InData value to be stored in CRC_IDR register (8-bit) between between Min_Data=0 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
-{
- *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
-}
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(CRC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_crc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_dac.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1347 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_dac.h
- * @author MCD Application Team
- * @brief Header file of DAC LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_DAC_H
-#define __STM32F1xx_LL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (DAC)
-
-/** @defgroup DAC_LL DAC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Constants DAC Private Constants
- * @{
- */
-
-/* Internal masks for DAC channels definition */
-/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
-/* - channel bits position into register CR */
-/* - channel bits position into register SWTRIG */
-/* - channel register offset of data holding register DHRx */
-/* - channel register offset of data output register DORx */
-#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
-#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
-
-#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
-#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
-#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
-
-#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
-#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
-#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
-#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
-
-#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
-#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
-#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
-
-/* DAC registers bits positions */
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
-
-/* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
-
-/**
- * @}
- */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Private_Macros DAC Private Macros
- * @{
- */
-
-/**
- * @brief Driver macro reserved for internal use: isolate bits with the
- * selected mask and shift them to the register LSB
- * (shift mask on register position bit 0).
- * @param __BITS__ Bits in register 32 bits
- * @param __MASK__ Mask in register 32 bits
- * @retval Bits in register 32 bits
-*/
-#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
- (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
-
-/**
- * @brief Driver macro reserved for internal use: set a pointer to
- * a register from a register basis from which an offset
- * is applied.
- * @param __REG__ Register basis from which the offset is applied.
- * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
- * @retval Pointer to register address
-*/
-#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
- ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
-
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
- * @{
- */
-
-/**
- * @brief Structure definition of some features of DAC instance.
- */
-typedef struct
-{
- uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
- This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
-
- uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
-
- uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
- If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
- If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
- @note If waveform automatic generation mode is disabled, this parameter is discarded.
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
-
- uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
- This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
-
- This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
-
-} LL_DAC_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
- * @{
- */
-
-/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
- * @brief Flags defines which can be used with LL_DAC_ReadReg function
- * @{
- */
-/* DAC channel 1 flags */
-#if defined(DAC_SR_DMAUDR1)
-#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
-#endif /* DAC_SR_DMAUDR1 */
-
-/* DAC channel 2 flags */
-#if defined(DAC_SR_DMAUDR2)
-#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
-#endif /* DAC_SR_DMAUDR2 */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_IT DAC interruptions
- * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
- * @{
- */
-#if defined(DAC_CR_DMAUDRIE1)
-#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
-#endif /* DAC_CR_DMAUDRIE1 */
-#if defined(DAC_CR_DMAUDRIE2)
-#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
-#endif /* DAC_CR_DMAUDRIE2 */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_CHANNEL DAC channels
- * @{
- */
-#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
-#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
- * @{
- */
-#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
-#define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
-#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
- * @{
- */
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
-#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
-#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
- * @{
- */
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
-#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
- * @{
- */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
-#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
- * @{
- */
-#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
-#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
-/**
- * @}
- */
-
-
-/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
- * @{
- */
-#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
- * @{
- */
-/* List of DAC registers intended to be used (most commonly) with */
-/* DMA transfer. */
-/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
-#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
-#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
-#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
- * @note Only DAC IP HW delays are defined in DAC LL driver driver,
- * not timeout values.
- * For details on delays values, refer to descriptions in source code
- * above each literal definition.
- * @{
- */
-
-/* Delay for DAC channel voltage settling time from DAC channel startup */
-/* (transition from disable to enable). */
-/* Note: DAC channel startup time depends on board application environment: */
-/* impedance connected to DAC channel output. */
-/* The delay below is specified under conditions: */
-/* - voltage maximum transition (lowest to highest value) */
-/* - until voltage reaches final value +-1LSB */
-/* - DAC channel output buffer enabled */
-/* - load impedance of 5kOhm (min), 50pF (max) */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tWAKEUP"). */
-/* Unit: us */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
-
-/* Delay for DAC channel voltage settling time. */
-/* Note: DAC channel startup time depends on board application environment: */
-/* impedance connected to DAC channel output. */
-/* The delay below is specified under conditions: */
-/* - voltage maximum transition (lowest to highest value) */
-/* - until voltage reaches final value +-1LSB */
-/* - DAC channel output buffer enabled */
-/* - load impedance of 5kOhm min, 50pF max */
-/* Literal set to maximum value (refer to device datasheet, */
-/* parameter "tSETTLING"). */
-/* Unit: us */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
- * @{
- */
-
-/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
- * @{
- */
-
-/**
- * @brief Write a value in DAC register
- * @param __INSTANCE__ DAC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DAC register
- * @param __INSTANCE__ DAC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
- * @{
- */
-
-/**
- * @brief Helper macro to get DAC channel number in decimal format
- * from literals LL_DAC_CHANNEL_x.
- * Example:
- * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
- * will return decimal number "1".
- * @note The input can be a value from functions where a channel
- * number is returned.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval 1...2
- */
-#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
-
-/**
- * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
- * from number in decimal format.
- * Example:
- * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
- * will return a data equivalent to "LL_DAC_CHANNEL_1".
- * @note If the input parameter does not correspond to a DAC channel,
- * this macro returns value '0'.
- * @param __DECIMAL_NB__ 1...2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- */
-#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) == 1U) \
- ? ( \
- LL_DAC_CHANNEL_1 \
- ) \
- : \
- (((__DECIMAL_NB__) == 2U) \
- ? ( \
- LL_DAC_CHANNEL_2 \
- ) \
- : \
- ( \
- 0 \
- ) \
- ) \
- )
-
-/**
- * @brief Helper macro to define the DAC conversion data full-scale digital
- * value corresponding to the selected DAC resolution.
- * @note DAC conversion data full-scale corresponds to voltage range
- * determined by analog voltage references Vref+ and Vref-
- * (refer to reference manual).
- * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_RESOLUTION_12B
- * @arg @ref LL_DAC_RESOLUTION_8B
- * @retval ADC conversion data equivalent voltage value (unit: mVolt)
- */
-#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
-
-/**
- * @brief Helper macro to calculate the DAC conversion data (unit: digital
- * value) corresponding to a voltage (unit: mVolt).
- * @note This helper macro is intended to provide input data in voltage
- * rather than digital value,
- * to be used with LL DAC functions such as
- * @ref LL_DAC_ConvertData12RightAligned().
- * @note Analog reference voltage (Vref+) must be either known from
- * user board environment or can be calculated using ADC measurement
- * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
- * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
- * (unit: mVolt).
- * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
- * @arg @ref LL_DAC_RESOLUTION_12B
- * @arg @ref LL_DAC_RESOLUTION_8B
- * @retval DAC conversion data (unit: digital value)
- */
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
- __DAC_VOLTAGE__,\
- __DAC_RESOLUTION__) \
- ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
- / (__VREFANALOG_VOLTAGE__) \
- )
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
- * @{
- */
-/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
- * @{
- */
-
-/**
- * @brief Set the conversion trigger source for the selected DAC channel.
- * @note For conversion trigger source to be effective, DAC trigger
- * must be enabled using function @ref LL_DAC_EnableTrigger().
- * @note To set conversion trigger source, DAC channel must be disabled.
- * Otherwise, the setting is discarded.
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
- * CR TSEL2 LL_DAC_SetTriggerSource
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param TriggerSource This parameter can be one of the following values:
- * @arg @ref LL_DAC_TRIG_SOFTWARE
- * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the conversion trigger source for the selected DAC channel.
- * @note For conversion trigger source to be effective, DAC trigger
- * must be enabled using function @ref LL_DAC_EnableTrigger().
- * @note Availability of parameters of trigger sources from timer
- * depends on timers availability on the selected device.
- * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
- * CR TSEL2 LL_DAC_GetTriggerSource
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_TRIG_SOFTWARE
- * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
- * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
- */
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the waveform automatic generation mode
- * for the selected DAC channel.
- * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
- * CR WAVE2 LL_DAC_SetWaveAutoGeneration
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param WaveAutoGeneration This parameter can be one of the following values:
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the waveform automatic generation mode
- * for the selected DAC channel.
- * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
- * CR WAVE2 LL_DAC_GetWaveAutoGeneration
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
- * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the noise waveform generation for the selected DAC channel:
- * Noise mode and parameters LFSR (linear feedback shift register).
- * @note For wave generation to be effective, DAC channel
- * wave generation mode must be enabled using
- * function @ref LL_DAC_SetWaveAutoGeneration().
- * @note This setting can be set when the selected DAC channel is disabled
- * (otherwise, the setting operation is ignored).
- * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
- * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param NoiseLFSRMask This parameter can be one of the following values:
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Set the noise waveform generation for the selected DAC channel:
- * Noise mode and parameters LFSR (linear feedback shift register).
- * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
- * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
- * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the triangle waveform generation for the selected DAC channel:
- * triangle mode and amplitude.
- * @note For wave generation to be effective, DAC channel
- * wave generation mode must be enabled using
- * function @ref LL_DAC_SetWaveAutoGeneration().
- * @note This setting can be set when the selected DAC channel is disabled
- * (otherwise, the setting operation is ignored).
- * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
- * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param TriangleAmplitude This parameter can be one of the following values:
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Set the triangle waveform generation for the selected DAC channel:
- * triangle mode and amplitude.
- * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
- * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
- * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
- */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @brief Set the output buffer for the selected DAC channel.
- * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
- * CR BOFF2 LL_DAC_SetOutputBuffer
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param OutputBuffer This parameter can be one of the following values:
- * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
- * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
-{
- MODIFY_REG(DACx->CR,
- DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
- OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get the output buffer state for the selected DAC channel.
- * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
- * CR BOFF2 LL_DAC_GetOutputBuffer
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
- * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
- */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
- );
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DAC DMA transfer request of the selected channel.
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_DAC_DMA_GetRegAddr().
- * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
- * CR DMAEN2 LL_DAC_EnableDMAReq
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC DMA transfer request of the selected channel.
- * @note To configure DMA source address (peripheral address),
- * use function @ref LL_DAC_DMA_GetRegAddr().
- * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
- * CR DMAEN2 LL_DAC_DisableDMAReq
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC DMA transfer request state of the selected channel.
- * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
- * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
- * CR DMAEN2 LL_DAC_IsDMAReqEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (READ_BIT(DACx->CR,
- DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
- * @brief Function to help to configure DMA transfer to DAC: retrieve the
- * DAC register address from DAC instance and a list of DAC registers
- * intended to be used (most commonly) with DMA transfer.
- * @note These DAC registers are data holding registers:
- * when DAC conversion is requested, DAC generates a DMA transfer
- * request to have data available in DAC data holding registers.
- * @note This macro is intended to be used with LL DMA driver, refer to
- * function "LL_DMA_ConfigAddresses()".
- * Example:
- * LL_DMA_ConfigAddresses(DMA1,
- * LL_DMA_CHANNEL_1,
- * (uint32_t)&< array or variable >,
- * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
- * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
- * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
- * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
- * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Register This parameter can be one of the following values:
- * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
- * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
- * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
- * @retval DAC register address
- */
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
-{
- /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
- /* DAC channel selected. */
- return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
-}
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
- * @{
- */
-
-/**
- * @brief Enable DAC selected channel.
- * @rmtoll CR EN1 LL_DAC_Enable\n
- * CR EN2 LL_DAC_Enable
- * @note After enable from off state, DAC channel requires a delay
- * for output voltage to reach accuracy +/- 1 LSB.
- * Refer to device datasheet, parameter "tWAKEUP".
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC selected channel.
- * @rmtoll CR EN1 LL_DAC_Disable\n
- * CR EN2 LL_DAC_Disable
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC enable state of the selected channel.
- * (0: DAC channel is disabled, 1: DAC channel is enabled)
- * @rmtoll CR EN1 LL_DAC_IsEnabled\n
- * CR EN2 LL_DAC_IsEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (READ_BIT(DACx->CR,
- DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
- * @brief Enable DAC trigger of the selected channel.
- * @note - If DAC trigger is disabled, DAC conversion is performed
- * automatically once the data holding register is updated,
- * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
- * @ref LL_DAC_ConvertData12RightAligned(), ...
- * - If DAC trigger is enabled, DAC conversion is performed
- * only when a hardware of software trigger event is occurring.
- * Select trigger source using
- * function @ref LL_DAC_SetTriggerSource().
- * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
- * CR TEN2 LL_DAC_EnableTrigger
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Disable DAC trigger of the selected channel.
- * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
- * CR TEN2 LL_DAC_DisableTrigger
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- CLEAR_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
-}
-
-/**
- * @brief Get DAC trigger state of the selected channel.
- * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
- * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
- * CR TEN2 LL_DAC_IsTriggerEnabled
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- return (READ_BIT(DACx->CR,
- DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
- == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
-}
-
-/**
- * @brief Trig DAC conversion by software for the selected DAC channel.
- * @note Preliminarily, DAC trigger must be set to software trigger
- * using function @ref LL_DAC_SetTriggerSource()
- * with parameter "LL_DAC_TRIGGER_SOFTWARE".
- * and DAC trigger must be enabled using
- * function @ref LL_DAC_EnableTrigger().
- * @note For devices featuring DAC with 2 channels: this function
- * can perform a SW start of both DAC channels simultaneously.
- * Two channels can be selected as parameter.
- * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
- * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
- * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can a combination of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- SET_BIT(DACx->SWTRIGR,
- (DAC_Channel & DAC_SWTR_CHX_MASK));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (LSB aligned on bit 0),
- * for the selected DAC channel.
- * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
- * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12R1_DACC1DHR,
- Data);
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (MSB aligned on bit 15),
- * for the selected DAC channel.
- * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
- * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR12L1_DACC1DHR,
- Data);
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 8 bits left alignment (LSB aligned on bit 0),
- * for the selected DAC channel.
- * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
- * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
-
- MODIFY_REG(*preg,
- DAC_DHR8R1_DACC1DHR,
- Data);
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (LSB aligned on bit 0),
- * for both DAC channels.
- * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
- * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
- MODIFY_REG(DACx->DHR12RD,
- (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
- ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 12 bits left alignment (MSB aligned on bit 15),
- * for both DAC channels.
- * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
- * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
- /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
- /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
- /* the 4 LSB must be taken into account for the shift value. */
- MODIFY_REG(DACx->DHR12LD,
- (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
- ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
-}
-
-/**
- * @brief Set the data to be loaded in the data holding register
- * in format 8 bits left alignment (LSB aligned on bit 0),
- * for both DAC channels.
- * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
- * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
- * @param DACx DAC instance
- * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
- * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
-{
- MODIFY_REG(DACx->DHR8RD,
- (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
- ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
-}
-
-/**
- * @brief Retrieve output data currently generated for the selected DAC channel.
- * @note Whatever alignment and resolution settings
- * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
- * @ref LL_DAC_ConvertData12RightAligned(), ...),
- * output data format is 12 bits right aligned (LSB aligned on bit 0).
- * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
- * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
- * @param DACx DAC instance
- * @param DAC_Channel This parameter can be one of the following values:
- * @arg @ref LL_DAC_CHANNEL_1
- * @arg @ref LL_DAC_CHANNEL_2
- * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
-{
- register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
-
- return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-#if defined(DAC_SR_DMAUDR1)
-/**
- * @brief Get DAC underrun flag for DAC channel 1
- * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
-}
-#endif /* DAC_SR_DMAUDR1 */
-
-#if defined(DAC_SR_DMAUDR2)
-/**
- * @brief Get DAC underrun flag for DAC channel 2
- * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
-}
-#endif /* DAC_SR_DMAUDR2 */
-
-#if defined(DAC_SR_DMAUDR1)
-/**
- * @brief Clear DAC underrun flag for DAC channel 1
- * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
-{
- WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
-}
-#endif /* DAC_SR_DMAUDR1 */
-
-#if defined(DAC_SR_DMAUDR2)
-/**
- * @brief Clear DAC underrun flag for DAC channel 2
- * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
-{
- WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
-}
-#endif /* DAC_SR_DMAUDR2 */
-
-/**
- * @}
- */
-/** @defgroup DAC_LL_EF_IT_Management IT management
- * @{
- */
-
-#if defined(DAC_CR_DMAUDRIE1)
-/**
- * @brief Enable DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-#endif /* DAC_CR_DMAUDRIE1 */
-
-#if defined(DAC_CR_DMAUDRIE2)
-/**
- * @brief Enable DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-#endif /* DAC_CR_DMAUDRIE2 */
-
-#if defined(DAC_CR_DMAUDRIE1)
-/**
- * @brief Disable DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
-}
-#endif /* DAC_CR_DMAUDRIE1 */
-
-#if defined(DAC_CR_DMAUDRIE2)
-/**
- * @brief Disable DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
- * @param DACx DAC instance
- * @retval None
- */
-__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
-}
-#endif /* DAC_CR_DMAUDRIE2 */
-
-#if defined(DAC_CR_DMAUDRIE1)
-/**
- * @brief Get DMA underrun interrupt for DAC channel 1
- * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
-}
-#endif /* DAC_CR_DMAUDRIE1 */
-
-#if defined(DAC_CR_DMAUDRIE2)
-/**
- * @brief Get DMA underrun interrupt for DAC channel 2
- * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
- * @param DACx DAC instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
-{
- return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
-}
-#endif /* DAC_CR_DMAUDRIE2 */
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
-void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DAC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_dac.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_dma.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1976 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_DMA_H
-#define __STM32F1xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
- * @{
- */
-/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
-static const uint8_t CHANNEL_OFFSET_TAB[] =
-{
- (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
-};
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_Private_Macros DMA Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
- * @{
- */
-typedef struct
-{
- uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
- or as Source base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
- or as Destination base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
- uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- This parameter can be a value of @ref DMA_LL_EC_MODE
- @note: The circular buffer mode cannot be used if the memory to memory
- data transfer direction is configured on the selected Channel
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
- uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
- uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
- uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
- uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
- uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
- The data unit is equal to the source buffer configuration set in PeripheralSize
- or MemorySize parameters depending in the transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
- uint32_t Priority; /*!< Specifies the channel priority level.
- This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
-
-} LL_DMA_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
- * @{
- */
-/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_DMA_WriteReg function
- * @{
- */
-#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
-#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
-#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
-#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
-#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
-#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
-#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
-#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
-#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_DMA_ReadReg function
- * @{
- */
-#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
-#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
-#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
-#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
-#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
-#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
-#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
-#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
-#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
-#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
-#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
-#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
-#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
-#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
-#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
-#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
- * @{
- */
-#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
-#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
-#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
- * @{
- */
-#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
-#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
-#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
-#endif /*USE_FULL_LL_DRIVER*/
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
- * @{
- */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MODE Transfer mode
- * @{
- */
-#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
-#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
- * @{
- */
-#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
- * @{
- */
-#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
-#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
- * @{
- */
-#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
-#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
- * @{
- */
-#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
-#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
- * @{
- */
-#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
-#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
-#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
- * @{
- */
-
-/**
- * @brief Convert DMAx_Channely into DMAx
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval DMAx
- */
-#if defined(DMA2)
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
-#else
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
-#endif
-
-/**
- * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval LL_DMA_CHANNEL_y
- */
-#if defined (DMA2)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#endif
-
-/**
- * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
- * @param __DMA_INSTANCE__ DMAx
- * @param __CHANNEL__ LL_DMA_CHANNEL_y
- * @retval DMAx_Channely
- */
-#if defined (DMA2)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable DMA channel.
- * @rmtoll CCR EN LL_DMA_EnableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
- * @brief Disable DMA channel.
- * @rmtoll CCR EN LL_DMA_DisableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
- * @brief Check if DMA channel is enabled or disabled.
- * @rmtoll CCR EN LL_DMA_IsEnabledChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_EN) == (DMA_CCR_EN));
-}
-
-/**
- * @brief Configure all parameters link to DMA transfer.
- * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
- * CCR MEM2MEM LL_DMA_ConfigTransfer\n
- * CCR CIRC LL_DMA_ConfigTransfer\n
- * CCR PINC LL_DMA_ConfigTransfer\n
- * CCR MINC LL_DMA_ConfigTransfer\n
- * CCR PSIZE LL_DMA_ConfigTransfer\n
- * CCR MSIZE LL_DMA_ConfigTransfer\n
- * CCR PL LL_DMA_ConfigTransfer
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
- * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
- * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
- * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
- * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
- * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
- Configuration);
-}
-
-/**
- * @brief Set Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_SetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
-}
-
-/**
- * @brief Get Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_GetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-}
-
-/**
- * @brief Set DMA mode circular or normal.
- * @note The circular buffer mode cannot be used if the memory-to-memory
- * data transfer is configured on the selected Channel.
- * @rmtoll CCR CIRC LL_DMA_SetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
- Mode);
-}
-
-/**
- * @brief Get DMA mode circular or normal.
- * @rmtoll CCR CIRC LL_DMA_GetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_CIRC));
-}
-
-/**
- * @brief Set Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
- PeriphOrM2MSrcIncMode);
-}
-
-/**
- * @brief Get Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PINC));
-}
-
-/**
- * @brief Set Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
- MemoryOrM2MDstIncMode);
-}
-
-/**
- * @brief Get Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_MINC));
-}
-
-/**
- * @brief Set Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
- PeriphOrM2MSrcDataSize);
-}
-
-/**
- * @brief Get Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PSIZE));
-}
-
-/**
- * @brief Set Memory size.
- * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
- MemoryOrM2MDstDataSize);
-}
-
-/**
- * @brief Get Memory size.
- * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_MSIZE));
-}
-
-/**
- * @brief Set Channel priority level.
- * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Priority This parameter can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
- Priority);
-}
-
-/**
- * @brief Get Channel priority level.
- * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PL));
-}
-
-/**
- * @brief Set Number of data to transfer.
- * @note This action has no effect if
- * channel is enabled.
- * @rmtoll CNDTR NDT LL_DMA_SetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
- DMA_CNDTR_NDT, NbData);
-}
-
-/**
- * @brief Get Number of data to transfer.
- * @note Once the channel is enabled, the return value indicate the
- * remaining bytes to be transmitted.
- * @rmtoll CNDTR NDT LL_DMA_GetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
- DMA_CNDTR_NDT));
-}
-
-/**
- * @brief Configure the Source and Destination addresses.
- * @note This API must not be called when the DMA channel is enabled.
- * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
- * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
- * CMAR MA LL_DMA_ConfigAddresses
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t Direction)
-{
- /* Direction Memory to Periph */
- if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
- {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
- }
- /* Direction Periph to Memory and Memory to Memory */
- else
- {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
- }
-}
-
-/**
- * @brief Set the Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
- * @brief Set the Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
-}
-
-/**
- * @brief Get Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
- * @brief Get Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
- * @brief Set the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
-}
-
-/**
- * @brief Set the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
- * @brief Get the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
- * @brief Get the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Channel 1 global interrupt flag.
- * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
-}
-
-/**
- * @brief Get Channel 2 global interrupt flag.
- * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
-}
-
-/**
- * @brief Get Channel 3 global interrupt flag.
- * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
-}
-
-/**
- * @brief Get Channel 4 global interrupt flag.
- * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
-}
-
-/**
- * @brief Get Channel 5 global interrupt flag.
- * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
-}
-
-/**
- * @brief Get Channel 6 global interrupt flag.
- * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
-}
-
-/**
- * @brief Get Channel 7 global interrupt flag.
- * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
-}
-
-/**
- * @brief Get Channel 1 transfer complete flag.
- * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
-}
-
-/**
- * @brief Get Channel 2 transfer complete flag.
- * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
-}
-
-/**
- * @brief Get Channel 3 transfer complete flag.
- * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
-}
-
-/**
- * @brief Get Channel 4 transfer complete flag.
- * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
-}
-
-/**
- * @brief Get Channel 5 transfer complete flag.
- * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
-}
-
-/**
- * @brief Get Channel 6 transfer complete flag.
- * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
-}
-
-/**
- * @brief Get Channel 7 transfer complete flag.
- * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
-}
-
-/**
- * @brief Get Channel 1 half transfer flag.
- * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
-}
-
-/**
- * @brief Get Channel 2 half transfer flag.
- * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
-}
-
-/**
- * @brief Get Channel 3 half transfer flag.
- * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
-}
-
-/**
- * @brief Get Channel 4 half transfer flag.
- * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
-}
-
-/**
- * @brief Get Channel 5 half transfer flag.
- * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
-}
-
-/**
- * @brief Get Channel 6 half transfer flag.
- * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
-}
-
-/**
- * @brief Get Channel 7 half transfer flag.
- * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
-}
-
-/**
- * @brief Get Channel 1 transfer error flag.
- * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
-}
-
-/**
- * @brief Get Channel 2 transfer error flag.
- * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
-}
-
-/**
- * @brief Get Channel 3 transfer error flag.
- * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
-}
-
-/**
- * @brief Get Channel 4 transfer error flag.
- * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
-}
-
-/**
- * @brief Get Channel 5 transfer error flag.
- * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
-}
-
-/**
- * @brief Get Channel 6 transfer error flag.
- * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
-}
-
-/**
- * @brief Get Channel 7 transfer error flag.
- * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
-}
-
-/**
- * @brief Clear Channel 1 global interrupt flag.
- * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
-}
-
-/**
- * @brief Clear Channel 2 global interrupt flag.
- * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
-}
-
-/**
- * @brief Clear Channel 3 global interrupt flag.
- * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
-}
-
-/**
- * @brief Clear Channel 4 global interrupt flag.
- * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
-}
-
-/**
- * @brief Clear Channel 5 global interrupt flag.
- * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
-}
-
-/**
- * @brief Clear Channel 6 global interrupt flag.
- * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
-}
-
-/**
- * @brief Clear Channel 7 global interrupt flag.
- * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
-}
-
-/**
- * @brief Clear Channel 1 transfer complete flag.
- * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer complete flag.
- * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer complete flag.
- * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer complete flag.
- * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer complete flag.
- * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer complete flag.
- * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
-}
-
-/**
- * @brief Clear Channel 7 transfer complete flag.
- * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
-}
-
-/**
- * @brief Clear Channel 1 half transfer flag.
- * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
-}
-
-/**
- * @brief Clear Channel 2 half transfer flag.
- * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
-}
-
-/**
- * @brief Clear Channel 3 half transfer flag.
- * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
-}
-
-/**
- * @brief Clear Channel 4 half transfer flag.
- * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
-}
-
-/**
- * @brief Clear Channel 5 half transfer flag.
- * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
-}
-
-/**
- * @brief Clear Channel 6 half transfer flag.
- * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
-}
-
-/**
- * @brief Clear Channel 7 half transfer flag.
- * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
-}
-
-/**
- * @brief Clear Channel 1 transfer error flag.
- * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer error flag.
- * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer error flag.
- * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer error flag.
- * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer error flag.
- * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer error flag.
- * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
-}
-
-/**
- * @brief Clear Channel 7 transfer error flag.
- * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
- * @brief Enable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
- * @brief Enable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
- * @brief Disable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
- * @brief Disable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
- * @brief Disable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
- * @brief Check if Transfer complete Interrupt is enabled.
- * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_TCIE) == (DMA_CCR_TCIE));
-}
-
-/**
- * @brief Check if Half transfer Interrupt is enabled.
- * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_HTIE) == (DMA_CCR_HTIE));
-}
-
-/**
- * @brief Check if Transfer error Interrupt is enabled.
- * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_TEIE) == (DMA_CCR_TEIE));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_dma.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_exti.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,904 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_EXTI_H
-#define __STM32F1xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
- * @{
- */
-typedef struct
-{
-
- uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
- This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
- FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-
- uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
- uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
- * @{
- */
-#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
-#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
-#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
-#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
-#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
-#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
-#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
-#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
-#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
-#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
-#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
-#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
-#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
-#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
-#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
-#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
-#if defined(EXTI_IMR_IM16)
-#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
-#endif
-#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
-#if defined(EXTI_IMR_IM18)
-#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
-#endif
-#if defined(EXTI_IMR_IM19)
-#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
-#endif
-#if defined(EXTI_IMR_IM20)
-#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
-#endif
-#if defined(EXTI_IMR_IM21)
-#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
-#endif
-#if defined(EXTI_IMR_IM22)
-#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
-#endif
-#if defined(EXTI_IMR_IM23)
-#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
-#endif
-#if defined(EXTI_IMR_IM24)
-#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
-#endif
-#if defined(EXTI_IMR_IM25)
-#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
-#endif
-#if defined(EXTI_IMR_IM26)
-#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
-#endif
-#if defined(EXTI_IMR_IM27)
-#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
-#endif
-#if defined(EXTI_IMR_IM28)
-#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
-#endif
-#if defined(EXTI_IMR_IM29)
-#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
-#endif
-#if defined(EXTI_IMR_IM30)
-#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
-#endif
-#if defined(EXTI_IMR_IM31)
-#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
-#endif
-#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
-
-
-#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
- * @{
- */
-#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
- * @{
- */
-#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
-
-/**
- * @}
- */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in EXTI register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in EXTI register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->IMR, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->IMR, ExtiLine);
-}
-
-
-/**
- * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->EMR, ExtiLine);
-
-}
-
-
-/**
- * @brief Disable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->EMR, ExtiLine);
-}
-
-
-/**
- * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
-
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
- * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
- * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
- * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for the same interrupt line.
- * In this case, both generate a trigger condition.
- * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
- * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
- * @{
- */
-
-/**
- * @brief Generate a software Interrupt Event for Lines in range 0 to 31
- * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
- * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
- * resulting in an interrupt request generation.
- * This bit is cleared by clearing the corresponding bit in the EXTI_PR
- * register (by writing a 1 into the bit)
- * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->SWIER, ExtiLine);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
- * @{
- */
-
-/**
- * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval @note This bit is set when the selected edge event arrives on the interrupt
- */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
- return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
-}
-
-
-/**
- * @brief Clear ExtLine Flags for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
- WRITE_REG(EXTI->PR, ExtiLine);
-}
-
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* EXTI */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_exti.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_fsmc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1079 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_fsmc.h
- * @author MCD Application Team
- * @brief Header file of FSMC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_FSMC_H
-#define __STM32F1xx_LL_FSMC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-#if defined(FSMC_BANK1)
-
-/** @addtogroup FSMC_LL
- * @{
- */
-
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC Low Layer Exported Types
- * @{
- */
-
-/**
- * @brief FSMC NORSRAM Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
- This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
- uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the data bus or not.
- This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
- uint32_t MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory device.
- This parameter can be a value of @ref FSMC_Memory_Type */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
-
- uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
- uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
- uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FSMC_Wrap_Mode */
-
- uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Timing */
-
- uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
- This parameter can be a value of @ref FSMC_Write_Operation */
-
- uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FSMC_Wait_Signal */
-
- uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FSMC_Extended_Mode */
-
- uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FSMC_AsynchronousWait */
-
- uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FSMC_Write_Burst */
-
-}FSMC_NORSRAM_InitTypeDef;
-
-/**
- * @brief FSMC NORSRAM Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between Min_Data = 1 and Max_Data = 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
- NOR Flash memories. */
-
- uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between Min_Data = 0 and Max_Data = 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
- HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
- accesses. */
-
- uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FSMC_Access_Mode */
-
-}FSMC_NORSRAM_TimingTypeDef;
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/**
- * @brief FSMC NAND Configuration Structure definition
- */
-typedef struct
-{
- uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
- This parameter can be a value of @ref FSMC_NAND_Bank */
-
- uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FSMC_NAND_Data_Width */
-
- uint32_t EccComputation; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FSMC_ECC */
-
- uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
- uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_NAND_InitTypeDef;
-
-/**
- * @brief FSMC NAND/PCCARD Timing parameters structure definition
- */
-typedef struct
-{
- uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- data bus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_NAND_PCC_TimingTypeDef;
-
-/**
- * @brief FSMC NAND Configuration Structure definition
- */
-typedef struct
-{
- uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
- This parameter can be any value of @ref FSMC_Wait_feature */
-
- uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
- uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
-
-}FSMC_PCCARD_InitTypeDef;
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Constants FSMC Low Layer Exported Constants
- * @{
- */
-
-/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
- * @{
- */
-/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
- * @{
- */
-#define FSMC_NORSRAM_BANK1 0x00000000U
-#define FSMC_NORSRAM_BANK2 0x00000002U
-#define FSMC_NORSRAM_BANK3 0x00000004U
-#define FSMC_NORSRAM_BANK4 0x00000006U
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
- * @{
- */
-#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
-#define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Memory_Type FSMC Memory Type
- * @{
- */
-#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
-#define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0)
-#define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
- * @{
- */
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
- * @{
- */
-#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
-/**
- * @}
- */
-
-/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
- * @{
- */
-#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
-#define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
- * @{
- */
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
-#define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
- * @{
- */
-#define FSMC_WRAP_MODE_DISABLE 0x00000000U
-#define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
- * @{
- */
-#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
-#define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Operation FSMC Write Operation
- * @{
- */
-#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
-#define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
- * @{
- */
-#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
-#define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
- * @{
- */
-#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
-#define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD)
-/**
- * @}
- */
-
-/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
- * @{
- */
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
-#define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Write_Burst FSMC Write Burst
- * @{
- */
-#define FSMC_WRITE_BURST_DISABLE 0x00000000U
-#define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Access_Mode FSMC Access Mode
- * @{
- */
-#define FSMC_ACCESS_MODE_A 0x00000000U
-#define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0)
-#define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1)
-#define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @defgroup FSMC_NAND_Controller FSMC NAND and PCCARD Controller
- * @{
- */
-/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
- * @{
- */
-#define FSMC_NAND_BANK2 0x00000010U
-#define FSMC_NAND_BANK3 0x00000100U
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_feature FSMC Wait feature
- * @{
- */
-#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
-#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)FSMC_PCRx_PWAITEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
- * @{
- */
-#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
-#define FSMC_PCR_MEMORY_TYPE_NAND ((uint32_t)FSMC_PCRx_PTYP)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
- * @{
- */
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
-#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_PCRx_PWID_0)
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC FSMC NAND ECC
- * @{
- */
-#define FSMC_NAND_ECC_DISABLE 0x00000000U
-#define FSMC_NAND_ECC_ENABLE ((uint32_t)FSMC_PCRx_ECCEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
- * @{
- */
-#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
-#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)FSMC_PCRx_ECCPS_0)
-#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)FSMC_PCRx_ECCPS_1)
-#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_1)
-#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)FSMC_PCRx_ECCPS_2)
-#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)FSMC_PCRx_ECCPS_0|FSMC_PCRx_ECCPS_2)
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
- * @brief FSMC Interrupt definition
- * @{
- */
-#define FSMC_IT_RISING_EDGE ((uint32_t)FSMC_SRx_IREN)
-#define FSMC_IT_LEVEL ((uint32_t)FSMC_SRx_ILEN)
-#define FSMC_IT_FALLING_EDGE ((uint32_t)FSMC_SRx_IFEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
- * @brief FSMC Flag definition
- * @{
- */
-#define FSMC_FLAG_RISING_EDGE ((uint32_t)FSMC_SRx_IRS)
-#define FSMC_FLAG_LEVEL ((uint32_t)FSMC_SRx_ILS)
-#define FSMC_FLAG_FALLING_EDGE ((uint32_t)FSMC_SRx_IFS)
-#define FSMC_FLAG_FEMPT ((uint32_t)FSMC_SRx_FEMPT)
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
- * @{
- */
-#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
-#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
-#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
-
-#define FSMC_NORSRAM_DEVICE FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
-#define FSMC_NAND_DEVICE FSMC_Bank2_3
-#define FSMC_PCCARD_DEVICE FSMC_Bank4
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FSMC_Exported_Macros FSMC Low Layer Exported Macros
- * @{
- */
-
-/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
- * @brief macros to handle NOR device enable/disable and read/write operations
- * @{
- */
-
-/**
- * @brief Enable the NORSRAM device access.
- * @param __INSTANCE__: FSMC_NORSRAM Instance
- * @param __BANK__: FSMC_NORSRAM Bank
- * @retval none
- */
-#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
-
-/**
- * @brief Disable the NORSRAM device access.
- * @param __INSTANCE__: FSMC_NORSRAM Instance
- * @param __BANK__: FSMC_NORSRAM Bank
- * @retval none
- */
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FSMC_BCRx_MBKEN)
-
-/**
- * @}
- */
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
-
-/**
- * @brief Enable the NAND device access.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @retval None
- */
-#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
- SET_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
-
-/**
- * @brief Disable the NAND device access.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @retval None
- */
-#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \
- CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN))
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
- * @brief macros to handle PCCARD read/write operations
- * @{
- */
-/**
- * @brief Enable the PCCARD device access.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @retval None
- */
-#define __FSMC_PCCARD_ENABLE(__INSTANCE__) SET_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
-
-/**
- * @brief Disable the PCCARD device access.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @retval None
- */
-#define __FSMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FSMC_PCRx_PBKEN)
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
- * @brief macros to handle FSMC flags and interrupts
- * @{
- */
-
-/**
- * @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __INTERRUPT__: FSMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
- SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
-
-/**
- * @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __INTERRUPT__: FSMC_NAND interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
- CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
-
-/**
- * @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__ : FSMC_NAND Bank
- * @param __FLAG__ : FSMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
- (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
-/**
- * @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FSMC_NAND Instance
- * @param __BANK__: FSMC_NAND Bank
- * @param __FLAG__: FSMC_NAND flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval None
- */
-#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
- CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
-
-/**
- * @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __INTERRUPT__: FSMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
-
-/**
- * @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __INTERRUPT__: FSMC_PCCARD interrupt
- * This parameter can be any combination of the following values:
- * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
- * @arg FSMC_IT_LEVEL: Interrupt level.
- * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
- * @retval None
- */
-#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
-
-/**
- * @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __FLAG__: FSMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval The state of FLAG (SET or RESET).
- */
-#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
-
-/**
- * @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__: FSMC_PCCARD Instance
- * @param __FLAG__: FSMC_PCCARD flag
- * This parameter can be any combination of the following values:
- * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
- * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
- * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
- * @arg FSMC_FLAG_FEMPT: FIFO empty flag.
- * @retval None
- */
-#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
-
-/**
- * @}
- */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros
- * @{
- */
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
- ((__BANK__) == FSMC_NORSRAM_BANK2) || \
- ((__BANK__) == FSMC_NORSRAM_BANK3) || \
- ((__BANK__) == FSMC_NORSRAM_BANK4))
-
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
-
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
-
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
-
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
-
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
- ((__MODE__) == FSMC_ACCESS_MODE_B) || \
- ((__MODE__) == FSMC_ACCESS_MODE_C) || \
- ((__MODE__) == FSMC_ACCESS_MODE_D))
-
-#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
- ((__BANK__) == FSMC_NAND_BANK3))
-
-#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
-
-#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
-
-#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FSMC_NAND_ECC_ENABLE))
-
-#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
-
-/** @defgroup FSMC_TCLR_Setup_Time FSMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_TAR_Setup_Time FSMC_TAR_Setup_Time
- * @{
- */
-#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Setup_Time FSMC_Setup_Time
- * @{
- */
-#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Wait_Setup_Time FSMC_Wait_Setup_Time
- * @{
- */
-#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Hold_Setup_Time FSMC_Hold_Setup_Time
- * @{
- */
-#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_HiZ_Setup_Time FSMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
- * @{
- */
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
- * @{
- */
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FSMC_NAND_Device_Instance FSMC NAND Device Instance
- * @{
- */
-#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
-/**
- * @}
- */
-
-/** @defgroup FSMC_PCCARD_Device_Instance FSMC PCCARD Device Instance
- * @{
- */
-#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
-
-/**
- * @}
- */
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
-
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
- ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
-
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
-
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
-
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
-
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
-
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
-
-/** @defgroup FSMC_Data_Latency FSMC Data Latency
- * @{
- */
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
- * @{
- */
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
-/**
- * @}
- */
-
-/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
- * @{
- */
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
- * @{
- */
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
-/**
- * @}
- */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
- * @{
- */
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants
- * @{
- */
-
-/* ----------------------- FSMC registers bit mask --------------------------- */
-#if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/* --- PCR Register ---*/
-/* PCR register clear mask */
-#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \
- FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \
- FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \
- FSMC_PCRx_TAR | FSMC_PCRx_ECCPS))
-
-/* --- PMEM Register ---*/
-/* PMEM register clear mask */
-#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\
- FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx))
-
-/* --- PATT Register ---*/
-/* PATT register clear mask */
-#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\
- FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx))
-
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-/* --- BCR Register ---*/
-/* BCR register clear mask */
-#define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \
- FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \
- FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \
- FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \
- FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \
- FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \
- FSMC_BCRx_CBURSTRW))
-/* --- BTR Register ---*/
-/* BTR register clear mask */
-#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\
- FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\
- FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\
- FSMC_BTRx_ACCMOD))
-
-/* --- BWTR Register ---*/
-/* BWTR register clear mask */
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
- FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
- FSMC_BWTRx_BUSTURN))
-#else
-#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \
- FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \
- FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT))
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/* --- PIO4 Register ---*/
-/* PIO4 register clear mask */
-#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
- FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
-/**
- * @}
- */
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FSMC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup FSMC_NORSRAM
- * @{
- */
-
-/** @addtogroup FSMC_NORSRAM_Group1
- * @{
- */
-/* FSMC_NORSRAM Controller functions ******************************************/
-/* Initialization/de-initialization functions */
-HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
-/**
- * @}
- */
-
-/** @addtogroup FSMC_NORSRAM_Group2
- * @{
- */
-/* FSMC_NORSRAM Control functions */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
-/** @addtogroup FSMC_NAND
- * @{
- */
-
-/* FSMC_NAND Controller functions **********************************************/
-/* Initialization/de-initialization functions */
-/** @addtogroup FSMC_NAND_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-/**
- * @}
- */
-
-/* FSMC_NAND Control functions */
-/** @addtogroup FSMC_NAND_Exported_Functions_Group2
- * @{
- */
-HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup FSMC_PCCARD
- * @{
- */
-
-/* FSMC_PCCARD Controller functions ********************************************/
-/* Initialization/de-initialization functions */
-/** @addtogroup FSMC_PCCARD_Exported_Functions_Group1
- * @{
- */
-HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init);
-HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing);
-HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* FSMC_BANK1 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_FSMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_fsmc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_gpio.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2377 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_GPIO_H
-#define __STM32F1xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
-
-/** @defgroup GPIO_LL GPIO
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-
-/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
- * @{
- */
-/* Defines used for Pin Mask Initialization */
-#define GPIO_PIN_MASK_POS 8U
-#define GPIO_PIN_NB 16U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
- * @{
- */
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
- * @{
- */
-
-/**
- * @brief LL GPIO Init Structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
- uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
- uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-} LL_GPIO_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
- * @{
- */
-#define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */
-#define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */
-#define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */
-#define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */
-#define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */
-#define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */
-#define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */
-#define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */
-#define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */
-#define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */
-#define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */
-#define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */
-#define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */
-#define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */
-#define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */
-#define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
- LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
- LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
- LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
- LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
- LL_GPIO_PIN_15) /*!< Select all pins */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
- * @{
- */
-#define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
-#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
-#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */
-#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
- * @{
- */
-#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
- * @{
- */
-#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */
-#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */
-#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */
-/**
- * @}
- */
-
-#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */
-#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
- * @{
- */
-#define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
-#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
- * @{
- */
-
-#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
-#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
-#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
-#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
-#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
-#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
-#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
-#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
-#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
-#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
-#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
-#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
-#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
-#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
-#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
-#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
- * @{
- */
-
-#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
-#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
-#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
-#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
-#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
- * @{
- */
-#define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */
-#define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */
-#define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */
-#define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */
-#define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */
-#define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */
-#define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
- * @{
- */
-#define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
-#define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
-#define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
-#define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
- * @{
- */
-
-/**
- * @brief Configure gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
- * Alternate function Output.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll CRL CNFy LL_GPIO_SetPinMode
- * @rmtoll CRL MODEy LL_GPIO_SetPinMode
- * @rmtoll CRH CNFy LL_GPIO_SetPinMode
- * @rmtoll CRH MODEy LL_GPIO_SetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @arg @ref LL_GPIO_MODE_FLOATING
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
- * Alternate function Output.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll CRL CNFy LL_GPIO_GetPinMode
- * @rmtoll CRL MODEy LL_GPIO_GetPinMode
- * @rmtoll CRH CNFy LL_GPIO_GetPinMode
- * @rmtoll CRH MODEy LL_GPIO_GetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @arg @ref LL_GPIO_MODE_FLOATING
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
- * @brief Configure gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium or Fast speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
- * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Speed This parameter can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
- (Speed << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
- * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
- * @brief Configure gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
- * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @param OutputType This parameter can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
- (OutputType << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
- * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-
-}
-
-/**
- * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll ODR ODR LL_GPIO_SetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Pull This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PULL_DOWN
- * @arg @ref LL_GPIO_PULL_UP
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
- MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
-}
-
-/**
- * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll ODR ODR LL_GPIO_GetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_PULL_DOWN
- * @arg @ref LL_GPIO_PULL_UP
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
-}
-
-/**
- * @brief Lock configuration of several pins for a dedicated port.
- * @note When the lock sequence has been applied on a port bit, the
- * value of this port bit can no longer be modified until the
- * next reset.
- * @note Each lock bit freezes a specific configuration register
- * (control and alternate function registers).
- * @rmtoll LCKR LCKK LL_GPIO_LockPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- __IO uint32_t temp;
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- temp = READ_REG(GPIOx->LCKR);
- (void) temp;
-}
-
-/**
- * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
- * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
- * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
- * @param GPIOx GPIO Port
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
- return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
- * @{
- */
-
-/**
- * @brief Return full input data register value for a dedicated port.
- * @rmtoll IDR IDy LL_GPIO_ReadInputPort
- * @param GPIOx GPIO Port
- * @retval Input data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
- return (READ_REG(GPIOx->IDR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @brief Write output data register for the port.
- * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
- * @param GPIOx GPIO Port
- * @param PortValue Level value for each pin of the port
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
- WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
- * @brief Return full output data register value for a dedicated port.
- * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
- * @param GPIOx GPIO Port
- * @retval Output data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
- return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @brief Set several pins to high level on dedicated gpio port.
- * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
-}
-
-/**
- * @brief Set several pins to low level on dedicated gpio port.
- * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
-}
-
-/**
- * @brief Toggle data value for several pin of dedicated port.
- * @rmtoll ODR ODy LL_GPIO_TogglePin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
- * @brief This section propose definition to remap the alternate function to some other port/pins.
- * @{
- */
-
-/**
- * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
- * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
-}
-
-/**
- * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
- * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
-}
-
-/**
- * @brief Check if SPI1 has been remaped or not
- * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
-}
-
-/**
- * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
- * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
- * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
-}
-
-/**
- * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
- * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
- * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
-}
-
-/**
- * @brief Check if I2C1 has been remaped or not
- * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
-}
-
-/**
- * @brief Enable the remapping of USART1 alternate function TX and RX.
- * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
- * @note ENABLE: Remap (TX/PB6, RX/PB7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
-}
-
-/**
- * @brief Disable the remapping of USART1 alternate function TX and RX.
- * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
- * @note DISABLE: No remap (TX/PA9, RX/PA10)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
-}
-
-/**
- * @brief Check if USART1 has been remaped or not
- * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
-}
-
-/**
- * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
- * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
-}
-
-/**
- * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
- * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
-}
-
-/**
- * @brief Check if USART2 has been remaped or not
- * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
-}
-
-#if defined (AFIO_MAPR_USART3_REMAP)
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
- * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
- * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
-}
-
-/**
- * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
- * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
-}
-#endif
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
- * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
- * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
- * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
- * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
- * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
-}
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
- * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
-}
-
-/**
- * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
- * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
- * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
- * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
- * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
- * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
-}
-
-#if defined(AFIO_MAPR_TIM4_REMAP)
-/**
- * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
- * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
- * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
-}
-/**
- * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
- * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
- * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
-}
-
-/**
- * @brief Check if TIM4 has been remaped or not
- * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
- * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
-}
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
- * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
-}
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
- * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
-}
-#endif
-
-/**
- * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
- * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
-}
-
-/**
- * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
- * @note DISABLE: No remapping of PD0 and PD1
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
-}
-
-/**
- * @brief Check if PD01 has been remaped or not
- * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
-}
-
-#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
-/**
- * @brief Enable the remapping of TIM5CH4.
- * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
- * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM5CH4.
- * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
- * @note DISABLE: TIM5_CH4 is connected to PA3
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
-}
-
-/**
- * @brief Check if TIM5CH4 has been remaped or not
- * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_ETH_REMAP)
-/**
- * @brief Enable the remapping of Ethernet MAC connections with the PHY.
- * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
- * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
-}
-
-/**
- * @brief Disable the remapping of Ethernet MAC connections with the PHY.
- * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
- * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
-}
-
-/**
- * @brief Check if ETH has been remaped or not
- * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_CAN2_REMAP)
-
-/**
- * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
- * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
-}
-/**
- * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
- * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
-}
-
-/**
- * @brief Check if CAN2 has been remaped or not
- * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_MII_RMII_SEL)
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
- * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
-}
-
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
- * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
-}
-#endif
-
-#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-/**
- * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
- * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
- * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Check if ADC1_ETRGINJ has been remaped or not
- * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
-/**
- * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
- * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
- * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
-}
-
-/**
- * @brief Check if ADC1_ETRGREG has been remaped or not
- * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
- * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
- * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Check if ADC2_ETRGINJ has been remaped or not
- * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
-}
-#endif
-
-#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
- * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
- * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
-}
-
-/**
- * @brief Check if ADC2_ETRGREG has been remaped or not
- * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
-}
-#endif
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
- * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
-}
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
- * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
-}
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
- * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
-}
-
-/**
- * @brief Disable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
- * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
-}
-
-#if defined(AFIO_MAPR_SPI3_REMAP)
-
-/**
- * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
- * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
-}
-
-/**
- * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
- * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
-}
-
-/**
- * @brief Check if SPI3 has been remaped or not
- * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
- * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
-}
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
- * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
-}
-#endif
-
-#if defined(AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
- * @note ENABLE: PTP_PPS is output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
- * @note DISABLE: PTP_PPS not output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM9_REMAP)
-
-/**
- * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
- * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
- * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
- * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
- * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
-}
-
-/**
- * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
- * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM10_REMAP)
-
-/**
- * @brief Enable the remapping of TIM10_CH1.
- * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
- * @note ENABLE: Remap (TIM10_CH1 on PF6).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM10_CH1.
- * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
- * @note DISABLE: No remap (TIM10_CH1 on PB8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
-}
-
-/**
- * @brief Check if TIM10_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM11_REMAP)
-/**
- * @brief Enable the remapping of TIM11_CH1.
- * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
- * @note ENABLE: Remap (TIM11_CH1 on PF7).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM11_CH1.
- * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
- * @note DISABLE: No remap (TIM11_CH1 on PB9).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
-}
-
-/**
- * @brief Check if TIM11_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM13_REMAP)
-
-/**
- * @brief Enable the remapping of TIM13_CH1.
- * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
- * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM13_CH1.
- * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
- * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
-}
-
-/**
- * @brief Check if TIM13_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM14_REMAP)
-
-/**
- * @brief Enable the remapping of TIM14_CH1.
- * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
- * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM14_CH1.
- * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
- * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
-}
-
-/**
- * @brief Check if TIM14_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
- * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
-}
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
- * @note CONNECTED: The NADV signal is connected to the output (default).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM15_REMAP)
-
-/**
- * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
- * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
- * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
-}
-/**
- * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
- * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
- * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
-}
-
-/**
- * @brief Check if TIM15_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM16_REMAP)
-
-/**
- * @brief Enable the remapping of TIM16_CH1.
- * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
- * @note ENABLE: Remap (TIM16_CH1 on PA6).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM16_CH1.
- * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
- * @note DISABLE: No remap (TIM16_CH1 on PB8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
-}
-
-/**
- * @brief Check if TIM16_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM17_REMAP)
-
-/**
- * @brief Enable the remapping of TIM17_CH1.
- * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
- * @note ENABLE: Remap (TIM17_CH1 on PA7).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM17_CH1.
- * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
- * @note DISABLE: No remap (TIM17_CH1 on PB9).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
-}
-
-/**
- * @brief Check if TIM17_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_CEC_REMAP)
-
-/**
- * @brief Enable the remapping of CEC.
- * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
- * @note ENABLE: Remap (CEC on PB10).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
-}
-
-/**
- * @brief Disable the remapping of CEC.
- * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
- * @note DISABLE: No remap (CEC on PB8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
-}
-
-/**
- * @brief Check if CEC has been remaped or not
- * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
- * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
-}
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
- * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
-}
-
-/**
- * @brief Check if TIM1DMA has been remaped or not
- * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
- * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
-}
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
- * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
-}
-
-/**
- * @brief Check if TIM67DACDMA has been remaped or not
- * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM12_REMAP)
-
-/**
- * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
- * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
- * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
- * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
- * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
-}
-
-/**
- * @brief Check if TIM12_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_MISC_REMAP)
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
- * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
- * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
-}
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
- * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
- * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
-}
-
-/**
- * @brief Check if MISC has been remaped or not
- * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
- * @brief This section propose definition to Configure EVENTOUT Cortex feature .
- * @{
- */
-
-/**
- * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
- * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
- * EVCR PIN LL_GPIO_AF_ConfigEventout
- * @param LL_GPIO_PortSource This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
- * @param LL_GPIO_PinSource This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
- * @retval None
-*/
-__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
-{
- MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
-}
-
-/**
- * @brief Enables the Event Output.
- * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
-{
- SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @brief Disables the Event Output.
- * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
-{
- CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @}
- */
-/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
- * @brief This section Configure source input for the EXTI external interrupt .
- * @{
- */
-
-/**
- * @brief Configure source input for the EXTI external interrupt.
- * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
- * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
- * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
- * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
- * @param Port This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_PORTA
- * @arg @ref LL_GPIO_AF_EXTI_PORTB
- * @arg @ref LL_GPIO_AF_EXTI_PORTC
- * @arg @ref LL_GPIO_AF_EXTI_PORTD
- * @arg @ref LL_GPIO_AF_EXTI_PORTE
- * @arg @ref LL_GPIO_AF_EXTI_PORTF
- * @arg @ref LL_GPIO_AF_EXTI_PORTG
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_LINE0
- * @arg @ref LL_GPIO_AF_EXTI_LINE1
- * @arg @ref LL_GPIO_AF_EXTI_LINE2
- * @arg @ref LL_GPIO_AF_EXTI_LINE3
- * @arg @ref LL_GPIO_AF_EXTI_LINE4
- * @arg @ref LL_GPIO_AF_EXTI_LINE5
- * @arg @ref LL_GPIO_AF_EXTI_LINE6
- * @arg @ref LL_GPIO_AF_EXTI_LINE7
- * @arg @ref LL_GPIO_AF_EXTI_LINE8
- * @arg @ref LL_GPIO_AF_EXTI_LINE9
- * @arg @ref LL_GPIO_AF_EXTI_LINE10
- * @arg @ref LL_GPIO_AF_EXTI_LINE11
- * @arg @ref LL_GPIO_AF_EXTI_LINE12
- * @arg @ref LL_GPIO_AF_EXTI_LINE13
- * @arg @ref LL_GPIO_AF_EXTI_LINE14
- * @arg @ref LL_GPIO_AF_EXTI_LINE15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
-{
- MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
-}
-
-/**
- * @brief Get the configured defined for specific EXTI Line
- * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
- * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
- * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
- * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_LINE0
- * @arg @ref LL_GPIO_AF_EXTI_LINE1
- * @arg @ref LL_GPIO_AF_EXTI_LINE2
- * @arg @ref LL_GPIO_AF_EXTI_LINE3
- * @arg @ref LL_GPIO_AF_EXTI_LINE4
- * @arg @ref LL_GPIO_AF_EXTI_LINE5
- * @arg @ref LL_GPIO_AF_EXTI_LINE6
- * @arg @ref LL_GPIO_AF_EXTI_LINE7
- * @arg @ref LL_GPIO_AF_EXTI_LINE8
- * @arg @ref LL_GPIO_AF_EXTI_LINE9
- * @arg @ref LL_GPIO_AF_EXTI_LINE10
- * @arg @ref LL_GPIO_AF_EXTI_LINE11
- * @arg @ref LL_GPIO_AF_EXTI_LINE12
- * @arg @ref LL_GPIO_AF_EXTI_LINE13
- * @arg @ref LL_GPIO_AF_EXTI_LINE14
- * @arg @ref LL_GPIO_AF_EXTI_LINE15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_PORTA
- * @arg @ref LL_GPIO_AF_EXTI_PORTB
- * @arg @ref LL_GPIO_AF_EXTI_PORTC
- * @arg @ref LL_GPIO_AF_EXTI_PORTD
- * @arg @ref LL_GPIO_AF_EXTI_PORTE
- * @arg @ref LL_GPIO_AF_EXTI_PORTF
- * @arg @ref LL_GPIO_AF_EXTI_PORTG
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
-{
- return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_gpio.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_i2c.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1800 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_i2c.h
- * @author MCD Application Team
- * @brief Header file of I2C LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_I2C_H
-#define __STM32F1xx_LL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (I2C1) || defined (I2C2)
-
-/** @defgroup I2C_LL I2C
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_LL_Private_Constants I2C Private Constants
- * @{
- */
-
-/* Defines used to perform compute and check in the macros */
-#define LL_I2C_MAX_SPEED_STANDARD 100000U
-#define LL_I2C_MAX_SPEED_FAST 400000U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_Private_Macros I2C Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
- * @{
- */
-typedef struct
-{
- uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
- This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
-
- uint32_t ClockSpeed; /*!< Specifies the clock frequency.
- This parameter must be set to a value lower than 400kHz (in Hz)
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
- or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
-
- uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
- This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
-
- uint32_t OwnAddress1; /*!< Specifies the device own address 1.
- This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-
- uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
-
- uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
- This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
-
- This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
-} LL_I2C_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
- * @{
- */
-
-/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2C_ReadReg function
- * @{
- */
-#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
-#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
- Address matched flag (slave mode) */
-#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
-#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
-#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
-#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
-#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
-#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
-#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
-#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
-#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
-#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
-#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
-#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
-#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
-#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
-#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
-#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
-#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
-#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
-#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
- * @{
- */
-#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
-#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
-#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
- * @{
- */
-#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
-#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
- * @{
- */
-#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
-#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
- * @{
- */
-#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
-#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
- * @{
- */
-#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
-#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
-#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
- * @{
- */
-#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
-#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
- * @{
- */
-#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
-#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
- * @{
- */
-
-/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2C register
- * @param __INSTANCE__ I2C Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2C register
- * @param __INSTANCE__ I2C Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
- * @{
- */
-
-/**
- * @brief Convert Peripheral Clock Frequency in Mhz.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @retval Value of peripheral clock (in Mhz)
- */
-#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
-
-/**
- * @brief Convert Peripheral Clock Frequency in Hz.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
- * @retval Value of peripheral clock (in Hz)
- */
-#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
-
-/**
- * @brief Compute I2C Clock rising time.
- * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
- * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
- * @retval Value between Min_Data=0x02 and Max_Data=0x3F
- */
-#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
-
-/**
- * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
- * @param __DUTYCYCLE__ This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
- */
-#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
- (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
- (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
-
-/**
- * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
- * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
- */
-#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
-
-/**
- * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
- * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
- * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
- * @param __DUTYCYCLE__ This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
- */
-#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
- (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
- (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
-
-/**
- * @brief Get the Least significant bits of a 10-Bits address.
- * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-/**
- * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
- * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
- * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
- */
-#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-
-/**
- * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
- * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
- * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
- */
-#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
- * @{
- */
-
-/** @defgroup I2C_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable I2C peripheral (PE = 1).
- * @rmtoll CR1 PE LL_I2C_Enable
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Disable I2C peripheral (PE = 0).
- * @rmtoll CR1 PE LL_I2C_Disable
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Check if the I2C peripheral is enabled or disabled.
- * @rmtoll CR1 PE LL_I2C_IsEnabled
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
-}
-
-
-/**
- * @brief Enable DMA transmission requests.
- * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Disable DMA transmission requests.
- * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Check if DMA transmission requests are enabled or disabled.
- * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
-}
-
-/**
- * @brief Enable DMA reception requests.
- * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Disable DMA reception requests.
- * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
-}
-
-/**
- * @brief Check if DMA reception requests are enabled or disabled.
- * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer.
- * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
- * @param I2Cx I2C Instance.
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
-{
- return (uint32_t) & (I2Cx->DR);
-}
-
-/**
- * @brief Enable Clock stretching.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
- * @brief Disable Clock stretching.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
-}
-
-/**
- * @brief Check if Clock stretching is enabled or disabled.
- * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
-}
-
-/**
- * @brief Enable General Call.
- * @note When enabled the Address 0x00 is ACKed.
- * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
-}
-
-/**
- * @brief Disable General Call.
- * @note When disabled the Address 0x00 is NACKed.
- * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
-}
-
-/**
- * @brief Check if General Call is enabled or disabled.
- * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
-}
-
-/**
- * @brief Set the Own Address1.
- * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
- * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
- * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
- * OAR1 ADDMODE LL_I2C_SetOwnAddress1
- * @param I2Cx I2C Instance.
- * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
- * @param OwnAddrSize This parameter can be one of the following values:
- * @arg @ref LL_I2C_OWNADDRESS1_7BIT
- * @arg @ref LL_I2C_OWNADDRESS1_10BIT
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
-{
- MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
-}
-
-/**
- * @brief Set the 7bits Own Address2.
- * @note This action has no effect if own address2 is enabled.
- * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
- * @param I2Cx I2C Instance.
- * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
-{
- MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
-}
-
-/**
- * @brief Enable acknowledge on Own Address2 match address.
- * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
-}
-
-/**
- * @brief Disable acknowledge on Own Address2 match address.
- * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
-}
-
-/**
- * @brief Check if Own Address1 acknowledge is enabled or disabled.
- * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
-}
-
-/**
- * @brief Configure the Peripheral clock frequency.
- * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
- * @param I2Cx I2C Instance.
- * @param PeriphClock Peripheral Clock (in Hz)
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
-{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
-}
-
-/**
- * @brief Get the Peripheral clock frequency.
- * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
- * @param I2Cx I2C Instance.
- * @retval Value of Peripheral Clock (in Hz)
- */
-__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
-}
-
-/**
- * @brief Configure the Duty cycle (Fast mode only).
- * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
- * @param I2Cx I2C Instance.
- * @param DutyCycle This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
-{
- MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
-}
-
-/**
- * @brief Get the Duty cycle (Fast mode only).
- * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- */
-__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
-}
-
-/**
- * @brief Configure the I2C master clock speed mode.
- * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
- * @param I2Cx I2C Instance.
- * @param ClockSpeedMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
- * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
-{
- MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
-}
-
-/**
- * @brief Get the the I2C master speed mode.
- * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
- * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
- */
-__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
-}
-
-/**
- * @brief Configure the SCL, SDA rising time.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
- * @param I2Cx I2C Instance.
- * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
-{
- MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
-}
-
-/**
- * @brief Get the SCL, SDA rising time.
- * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x02 and Max_Data=0x3F
- */
-__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
-}
-
-/**
- * @brief Configure the SCL high and low period.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CCR CCR LL_I2C_SetClockPeriod
- * @param I2Cx I2C Instance.
- * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
-{
- MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
-}
-
-/**
- * @brief Get the SCL high and low period.
- * @rmtoll CCR CCR LL_I2C_GetClockPeriod
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
- */
-__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
-}
-
-/**
- * @brief Configure the SCL speed.
- * @note This bit can only be programmed when the I2C is disabled (PE = 0).
- * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
- * TRISE TRISE LL_I2C_ConfigSpeed\n
- * CCR FS LL_I2C_ConfigSpeed\n
- * CCR DUTY LL_I2C_ConfigSpeed\n
- * CCR CCR LL_I2C_ConfigSpeed
- * @param I2Cx I2C Instance.
- * @param PeriphClock Peripheral Clock (in Hz)
- * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
- * @param DutyCycle This parameter can be one of the following values:
- * @arg @ref LL_I2C_DUTYCYCLE_2
- * @arg @ref LL_I2C_DUTYCYCLE_16_9
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
- uint32_t DutyCycle)
-{
- register uint32_t freqrange = 0x0U;
- register uint32_t clockconfig = 0x0U;
-
- /* Compute frequency range */
- freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
-
- /* Configure I2Cx: Frequency range register */
- MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
-
- /* Configure I2Cx: Rise Time register */
- MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
-
- /* Configure Speed mode, Duty Cycle and Clock control register value */
- if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
- {
- /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
- clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
- __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
- DutyCycle;
- }
- else
- {
- /* Set Speed mode at standard for Clock Speed request in standard clock range */
- clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
- __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
- }
-
- /* Configure I2Cx: Clock control register */
- MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
-}
-
-/**
- * @brief Configure peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
- * CR1 SMBTYPE LL_I2C_SetMode\n
- * CR1 ENARP LL_I2C_SetMode
- * @param I2Cx I2C Instance.
- * @param PeripheralMode This parameter can be one of the following values:
- * @arg @ref LL_I2C_MODE_I2C
- * @arg @ref LL_I2C_MODE_SMBUS_HOST
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
-{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
-}
-
-/**
- * @brief Get peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
- * CR1 SMBTYPE LL_I2C_GetMode\n
- * CR1 ENARP LL_I2C_GetMode
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_MODE_I2C
- * @arg @ref LL_I2C_MODE_SMBUS_HOST
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
- * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
- */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
-}
-
-/**
- * @brief Enable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note SMBus Device mode:
- * - SMBus Alert pin is drived low and
- * Alert Response Address Header acknowledge is enabled.
- * SMBus Host mode:
- * - SMBus Alert pin management is supported.
- * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
-}
-
-/**
- * @brief Disable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note SMBus Device mode:
- * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
- * Alert Response Address Header acknowledge is disabled.
- * SMBus Host mode:
- * - SMBus Alert pin management is not supported.
- * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
-}
-
-/**
- * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
-}
-
-/**
- * @brief Enable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
-}
-
-/**
- * @brief Disable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
-}
-
-/**
- * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable TXE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
- * CR2 ITBUFEN LL_I2C_EnableIT_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Disable TXE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
- * CR2 ITBUFEN LL_I2C_DisableIT_TX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Check if the TXE Interrupt is enabled or disabled.
- * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
- * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
-}
-
-/**
- * @brief Enable RXNE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
- * CR2 ITBUFEN LL_I2C_EnableIT_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Disable RXNE interrupt.
- * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
- * CR2 ITBUFEN LL_I2C_DisableIT_RX
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Check if the RXNE Interrupt is enabled or disabled.
- * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
- * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
-}
-
-/**
- * @brief Enable Events interrupts.
- * @note Any of these events will generate interrupt :
- * Start Bit (SB)
- * Address sent, Address matched (ADDR)
- * 10-bit header sent (ADD10)
- * Stop detection (STOPF)
- * Byte transfer finished (BTF)
- *
- * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
-}
-
-/**
- * @brief Disable Events interrupts.
- * @note Any of these events will generate interrupt :
- * Start Bit (SB)
- * Address sent, Address matched (ADDR)
- * 10-bit header sent (ADD10)
- * Stop detection (STOPF)
- * Byte transfer finished (BTF)
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
-}
-
-/**
- * @brief Check if Events interrupts are enabled or disabled.
- * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
-}
-
-/**
- * @brief Enable Buffer interrupts.
- * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Disable Buffer interrupts.
- * @note Any of these Buffer events will generate interrupt :
- * Receive buffer not empty (RXNE)
- * Transmit buffer empty (TXE)
- * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
-}
-
-/**
- * @brief Check if Buffer interrupts are enabled or disabled.
- * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
-}
-
-/**
- * @brief Enable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note Any of these errors will generate interrupt :
- * Bus Error detection (BERR)
- * Arbitration Loss (ARLO)
- * Acknowledge Failure(AF)
- * Overrun/Underrun (OVR)
- * SMBus Timeout detection (TIMEOUT)
- * SMBus PEC error detection (PECERR)
- * SMBus Alert pin event detection (SMBALERT)
- * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
-}
-
-/**
- * @brief Disable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note Any of these errors will generate interrupt :
- * Bus Error detection (BERR)
- * Arbitration Loss (ARLO)
- * Acknowledge Failure(AF)
- * Overrun/Underrun (OVR)
- * SMBus Timeout detection (TIMEOUT)
- * SMBus PEC error detection (PECERR)
- * SMBus Alert pin event detection (SMBALERT)
- * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
-}
-
-/**
- * @brief Check if Error interrupts are enabled or disabled.
- * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
- * @{
- */
-
-/**
- * @brief Indicate the status of Transmit data register empty flag.
- * @note RESET: When next data is written in Transmit data register.
- * SET: When Transmit data register is empty.
- * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
-}
-
-/**
- * @brief Indicate the status of Byte Transfer Finished flag.
- * RESET: When Data byte transfer not done.
- * SET: When Data byte transfer succeeded.
- * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
-}
-
-/**
- * @brief Indicate the status of Receive data register not empty flag.
- * @note RESET: When Receive data register is read.
- * SET: When the received data is copied in Receive data register.
- * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
-}
-
-/**
- * @brief Indicate the status of Start Bit (master mode).
- * @note RESET: When No Start condition.
- * SET: When Start condition is generated.
- * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
-}
-
-/**
- * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
- * @note RESET: Clear default value.
- * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
- * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
-}
-
-/**
- * @brief Indicate the status of 10-bit header sent (master mode).
- * @note RESET: When no ADD10 event occured.
- * SET: When the master has sent the first address byte (header).
- * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
-}
-
-/**
- * @brief Indicate the status of Acknowledge failure flag.
- * @note RESET: No acknowledge failure.
- * SET: When an acknowledge failure is received after a byte transmission.
- * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
-}
-
-/**
- * @brief Indicate the status of Stop detection flag (slave mode).
- * @note RESET: Clear default value.
- * SET: When a Stop condition is detected.
- * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
-}
-
-/**
- * @brief Indicate the status of Bus error flag.
- * @note RESET: Clear default value.
- * SET: When a misplaced Start or Stop condition is detected.
- * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
-}
-
-/**
- * @brief Indicate the status of Arbitration lost flag.
- * @note RESET: Clear default value.
- * SET: When arbitration lost.
- * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
-}
-
-/**
- * @brief Indicate the status of Overrun/Underrun flag.
- * @note RESET: Clear default value.
- * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
- * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
-}
-
-/**
- * @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
-}
-
-/**
- * @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
-}
-
-/**
- * @brief Indicate the status of SMBus alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
-}
-
-/**
- * @brief Indicate the status of Bus Busy flag.
- * @note RESET: Clear default value.
- * SET: When a Start condition is detected.
- * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
-}
-
-/**
- * @brief Indicate the status of Dual flag.
- * @note RESET: Received address matched with OAR1.
- * SET: Received address matched with OAR2.
- * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
-}
-
-/**
- * @brief Indicate the status of SMBus Host address reception (Slave mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: No SMBus Host address
- * SET: SMBus Host address received.
- * @note This status is cleared by hardware after a STOP condition or repeated START condition.
- * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
-}
-
-/**
- * @brief Indicate the status of SMBus Device default address reception (Slave mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note RESET: No SMBus Device default address
- * SET: SMBus Device default address received.
- * @note This status is cleared by hardware after a STOP condition or repeated START condition.
- * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
-}
-
-/**
- * @brief Indicate the status of General call address reception (Slave mode).
- * @note RESET: No Generall call address
- * SET: General call address received.
- * @note This status is cleared by hardware after a STOP condition or repeated START condition.
- * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
-}
-
-/**
- * @brief Indicate the status of Master/Slave flag.
- * @note RESET: Slave Mode.
- * SET: Master Mode.
- * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
-}
-
-/**
- * @brief Clear Address Matched flag.
- * @note Clearing this flag is done by a read access to the I2Cx_SR1
- * register followed by a read access to the I2Cx_SR2 register.
- * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
-{
- __IO uint32_t tmpreg;
- tmpreg = I2Cx->SR1;
- (void) tmpreg;
- tmpreg = I2Cx->SR2;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Acknowledge failure flag.
- * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
-}
-
-/**
- * @brief Clear Stop detection flag.
- * @note Clearing this flag is done by a read access to the I2Cx_SR1
- * register followed by a write access to I2Cx_CR1 register.
- * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
- * CR1 PE LL_I2C_ClearFlag_STOP
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
-{
- __IO uint32_t tmpreg;
- tmpreg = I2Cx->SR1;
- (void) tmpreg;
- SET_BIT(I2Cx->CR1, I2C_CR1_PE);
-}
-
-/**
- * @brief Clear Bus error flag.
- * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
-}
-
-/**
- * @brief Clear Arbitration lost flag.
- * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
-}
-
-/**
- * @brief Clear Overrun/Underrun flag.
- * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
-}
-
-/**
- * @brief Clear SMBus PEC error flag.
- * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
-}
-
-/**
- * @brief Clear SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
-}
-
-/**
- * @brief Clear SMBus Alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Enable Reset of I2C peripheral.
- * @rmtoll CR1 SWRST LL_I2C_EnableReset
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
-}
-
-/**
- * @brief Disable Reset of I2C peripheral.
- * @rmtoll CR1 SWRST LL_I2C_DisableReset
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
-}
-
-/**
- * @brief Check if the I2C peripheral is under reset state or not.
- * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
-}
-
-/**
- * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- * @note Usage in Slave or Master mode.
- * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
- * @param I2Cx I2C Instance.
- * @param TypeAcknowledge This parameter can be one of the following values:
- * @arg @ref LL_I2C_ACK
- * @arg @ref LL_I2C_NACK
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
-{
- MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
-}
-
-/**
- * @brief Generate a START or RESTART condition
- * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
- * This action has no effect when RELOAD is set.
- * @rmtoll CR1 START LL_I2C_GenerateStartCondition
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_START);
-}
-
-/**
- * @brief Generate a STOP condition after the current byte transfer (master mode).
- * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
-}
-
-/**
- * @brief Enable bit POS (master/host mode).
- * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
- * @rmtoll CR1 POS LL_I2C_EnableBitPOS
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_POS);
-}
-
-/**
- * @brief Disable bit POS (master/host mode).
- * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
- * @rmtoll CR1 POS LL_I2C_DisableBitPOS
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
-}
-
-/**
- * @brief Check if bit POS is enabled or disabled.
- * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
-}
-
-/**
- * @brief Indicate the value of transfer direction.
- * @note RESET: Bus is in read transfer (peripheral point of view).
- * SET: Bus is in write transfer (peripheral point of view).
- * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
- * @param I2Cx I2C Instance.
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2C_DIRECTION_WRITE
- * @arg @ref LL_I2C_DIRECTION_READ
- */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
-}
-
-/**
- * @brief Enable DMA last transfer.
- * @note This action mean that next DMA EOT is the last transfer.
- * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
-}
-
-/**
- * @brief Disable DMA last transfer.
- * @note This action mean that next DMA EOT is not the last transfer.
- * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
-}
-
-/**
- * @brief Check if DMA last transfer is enabled or disabled.
- * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
-}
-
-/**
- * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
- * or by a START or STOP condition, it is also cleared by software.
- * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
-}
-
-/**
- * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
-}
-
-/**
- * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
- * @param I2Cx I2C Instance.
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
-{
- return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
-}
-
-/**
- * @brief Get the SMBus Packet Error byte calculated.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
- * SMBus feature is supported by the I2Cx Instance.
- * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
-{
- return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
-}
-
-/**
- * @brief Read Receive Data register.
- * @rmtoll DR DR LL_I2C_ReceiveData8
- * @param I2Cx I2C Instance.
- * @retval Value between Min_Data=0x0 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
-{
- return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
-}
-
-/**
- * @brief Write in Transmit Data Register .
- * @rmtoll DR DR LL_I2C_TransmitData8
- * @param I2Cx I2C Instance.
- * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
-{
- MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
-void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
-
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* I2C1 || I2C2 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_i2c.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_iwdg.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,327 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_iwdg.h
- * @author MCD Application Team
- * @brief Header file of IWDG LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_IWDG_H
-#define __STM32F1xx_LL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(IWDG)
-
-/** @defgroup IWDG_LL IWDG
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
- * @{
- */
-
-#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
-#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
-#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
-#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
- * @{
- */
-
-/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_IWDG_ReadReg function
- * @{
- */
-#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
-#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
- * @{
- */
-#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
-#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
-#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
-#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
-#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
-#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
-#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
- * @{
- */
-
-/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in IWDG register
- * @param __INSTANCE__ IWDG Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in IWDG register
- * @param __INSTANCE__ IWDG Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
- * @{
- */
-/** @defgroup IWDG_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Start the Independent Watchdog
- * @note Except if the hardware watchdog option is selected
- * @rmtoll KR KEY LL_IWDG_Enable
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * @rmtoll KR KEY LL_IWDG_ReloadCounter
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
-}
-
-/**
- * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
- * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
-}
-
-/**
- * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
- * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
- * @param IWDGx IWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
-{
- WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
-}
-
-/**
- * @brief Select the prescaler of the IWDG
- * @rmtoll PR PR LL_IWDG_SetPrescaler
- * @param IWDGx IWDG Instance
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_IWDG_PRESCALER_4
- * @arg @ref LL_IWDG_PRESCALER_8
- * @arg @ref LL_IWDG_PRESCALER_16
- * @arg @ref LL_IWDG_PRESCALER_32
- * @arg @ref LL_IWDG_PRESCALER_64
- * @arg @ref LL_IWDG_PRESCALER_128
- * @arg @ref LL_IWDG_PRESCALER_256
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
-{
- WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
-}
-
-/**
- * @brief Get the selected prescaler of the IWDG
- * @rmtoll PR PR LL_IWDG_GetPrescaler
- * @param IWDGx IWDG Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_IWDG_PRESCALER_4
- * @arg @ref LL_IWDG_PRESCALER_8
- * @arg @ref LL_IWDG_PRESCALER_16
- * @arg @ref LL_IWDG_PRESCALER_32
- * @arg @ref LL_IWDG_PRESCALER_64
- * @arg @ref LL_IWDG_PRESCALER_128
- * @arg @ref LL_IWDG_PRESCALER_256
- */
-__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
-{
- return (uint32_t)(READ_REG(IWDGx->PR));
-}
-
-/**
- * @brief Specify the IWDG down-counter reload value
- * @rmtoll RLR RL LL_IWDG_SetReloadCounter
- * @param IWDGx IWDG Instance
- * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
- * @retval None
- */
-__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
-{
- WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
-}
-
-/**
- * @brief Get the specified IWDG down-counter reload value
- * @rmtoll RLR RL LL_IWDG_GetReloadCounter
- * @param IWDGx IWDG Instance
- * @retval Value between Min_Data=0 and Max_Data=0x0FFF
- */
-__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
-{
- return (uint32_t)(READ_REG(IWDGx->RLR));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if flag Prescaler Value Update is set or not
- * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
- * @param IWDGx IWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
-{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
-}
-
-/**
- * @brief Check if flag Reload Value Update is set or not
- * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
- * @param IWDGx IWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
-{
- return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
-}
-
-
-/**
- * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
- * @rmtoll SR PVU LL_IWDG_IsReady\n
- * SR RVU LL_IWDG_IsReady
- * @param IWDGx IWDG Instance
- * @retval State of bits (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
-{
- return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* IWDG) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_pwr.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,456 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_PWR_H
-#define __STM32F1xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_PWR_WriteReg function
- * @{
- */
-#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
-#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_PWR_ReadReg function
- * @{
- */
-#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
-#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
-#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
-#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
-/**
- * @}
- */
-
-
-/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
- * @{
- */
-#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
- * @{
- */
-#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
- * @{
- */
-#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
-#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
-#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
-#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
-#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
-#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
-#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
-#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
-/**
- * @}
- */
-/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
- * @{
- */
-#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in PWR register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in PWR register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable access to the backup domain
- * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
- SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Disable access to the backup domain
- * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Check if the backup domain is enabled
- * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
-}
-
-/**
- * @brief Set voltage Regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
- * @param RegulMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
- MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
-}
-
-/**
- * @brief Get voltage Regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
-}
-
-/**
- * @brief Set Power Down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_SetPowerMode
- * @param PDMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
-{
- MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
-}
-
-/**
- * @brief Get Power Down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_GetPowerMode
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
-}
-
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage Detector
- * @rmtoll CR PLS LL_PWR_SetPVDLevel
- * @param PVDLevel This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
- MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
-}
-
-/**
- * @brief Get the voltage threshold detection
- * @rmtoll CR PLS LL_PWR_GetPVDLevel
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
-}
-
-/**
- * @brief Enable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_EnablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
- SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Disable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_DisablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Check if Power Voltage Detector is enabled
- * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
-}
-
-/**
- * @brief Enable the WakeUp PINx functionality
- * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
- SET_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality
- * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
- CLEAR_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Check if the WakeUp PINx functionality is enabled
- * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
- return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Wake-up Flag
- * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
-}
-
-/**
- * @brief Get Standby Flag
- * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
-}
-
-/**
- * @brief Indicate whether VDD voltage is below the selected PVD threshold
- * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
-}
-
-/**
- * @brief Clear Standby Flag
- * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CSBF);
-}
-
-/**
- * @brief Clear Wake-up Flags
- * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CWUF);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_PWR_DeInit(void);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(PWR) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_pwr.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_rcc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2328 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_RCC_H
-#define __STM32F1xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
- * @{
- */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
- * @{
- */
-
-/**
- * @brief RCC Clocks Frequency Structure
- */
-typedef struct
-{
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
- * @brief Defines used to adapt values of different oscillators
- * @note These values could be modified in the user environment according to
- * HW set-up.
- * @{
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined (LSE_VALUE)
-#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined (LSI_VALUE)
-#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_RCC_WriteReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */
-#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */
-#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RCC_ReadReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */
-#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
-#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
-#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
-#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
- * @{
- */
-#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
-#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */
-#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */
-/**
- * @}
- */
-
-#if defined(RCC_CFGR2_PREDIV2)
-/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
- * @{
- */
-#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
-#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
-#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
-#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
-#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
-#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
-#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
-#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
-#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
-#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
-#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
-#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
-#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
-#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
-#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
-#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR2_PREDIV2 */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
- * @{
- */
-#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
- * @{
- */
-#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
- * @{
- */
-#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
- * @{
- */
-#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
-#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
-#if defined(RCC_CFGR_MCOSEL_PLL2CLK)
-#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /*!< PLL2 clock selected as MCO source*/
-#endif /* RCC_CFGR_MCOSEL_PLL2CLK */
-#if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
-#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/
-#endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
-#if defined(RCC_CFGR_MCOSEL_EXT_HSE)
-#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
-#endif /* RCC_CFGR_MCOSEL_EXT_HSE */
-#if defined(RCC_CFGR_MCOSEL_PLL3CLK)
-#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */
-#endif /* RCC_CFGR_MCOSEL_PLL3CLK */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
- * @{
- */
-#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
-#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
- * @{
- */
-#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */
-#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */
-#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */
-#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */
-/**
- * @}
- */
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
- * @{
- */
-#if defined(RCC_CFGR_USBPRE)
-#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */
-#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */
-#endif /*RCC_CFGR_USBPRE*/
-#if defined(RCC_CFGR_OTGFSPRE)
-#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */
-#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */
-#endif /*RCC_CFGR_OTGFSPRE*/
-/**
- * @}
- */
-#endif /* USB_OTG_FS || USB */
-
-/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
- * @{
- */
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
-/**
- * @}
- */
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
- * @{
- */
-#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */
-#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
- * @{
- */
-#define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */
-/**
- * @}
- */
-
-#endif /* USB_OTG_FS || USB */
-
-/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
- * @{
- */
-#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
- * @{
- */
-#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
- * @{
- */
-#if defined(RCC_CFGR_PLLMULL2)
-#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */
-#endif /*RCC_CFGR_PLLMULL2*/
-#if defined(RCC_CFGR_PLLMULL3)
-#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */
-#endif /*RCC_CFGR_PLLMULL3*/
-#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */
-#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */
-#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */
-#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */
-#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */
-#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */
-#if defined(RCC_CFGR_PLLMULL6_5)
-#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
-#else
-#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */
-#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */
-#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */
-#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */
-#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */
-#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */
-#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */
-#endif /*RCC_CFGR_PLLMULL6_5*/
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
- * @{
- */
-#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */
-#if defined(RCC_CFGR2_PREDIV1SRC)
-#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-
-#if defined(RCC_CFGR2_PREDIV1)
-#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
-#if defined(RCC_CFGR2_PREDIV1SRC)
-#define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-#else
-#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */
-#endif /*RCC_CFGR2_PREDIV1*/
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
- * @{
- */
-#if defined(RCC_CFGR2_PREDIV1)
-#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */
-#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */
-#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */
-#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */
-#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */
-#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */
-#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */
-#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */
-#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */
-#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */
-#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */
-#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */
-#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */
-#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */
-#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */
-#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */
-#else
-#define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */
-#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */
-#endif /*RCC_CFGR2_PREDIV1*/
-/**
- * @}
- */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
- * @{
- */
-#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
-#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
-#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
-#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
-#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
-#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
-#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
-#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
-#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
-/**
- * @}
- */
-
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
- * @{
- */
-#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
-#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
-#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
-#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
-#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
-#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
-#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
-#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
-#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
-/**
- * @}
- */
-
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RCC register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RCC register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
- * @{
- */
-
-#if defined(RCC_CFGR_PLLMULL6_5)
-/**
- * @brief Helper macro to calculate the PLLCLK frequency
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
- * @param __PLLMUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_6_5
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
- (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
- ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
- (((__INPUTFREQ__) * 13U) / 2U))
-
-#else
-/**
- * @brief Helper macro to calculate the PLLCLK frequency
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
- * @param __PLLMUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2
- * @arg @ref LL_RCC_PLL_MUL_3
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_10
- * @arg @ref LL_RCC_PLL_MUL_11
- * @arg @ref LL_RCC_PLL_MUL_12
- * @arg @ref LL_RCC_PLL_MUL_13
- * @arg @ref LL_RCC_PLL_MUL_14
- * @arg @ref LL_RCC_PLL_MUL_15
- * @arg @ref LL_RCC_PLL_MUL_16
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
-#endif /* RCC_CFGR_PLLMULL6_5 */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Helper macro to calculate the PLLI2S frequency
- * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
- * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
- * @param __PLLI2SMUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLI2S_MUL_8
- * @arg @ref LL_RCC_PLLI2S_MUL_9
- * @arg @ref LL_RCC_PLLI2S_MUL_10
- * @arg @ref LL_RCC_PLLI2S_MUL_11
- * @arg @ref LL_RCC_PLLI2S_MUL_12
- * @arg @ref LL_RCC_PLLI2S_MUL_13
- * @arg @ref LL_RCC_PLLI2S_MUL_14
- * @arg @ref LL_RCC_PLLI2S_MUL_16
- * @arg @ref LL_RCC_PLLI2S_MUL_20
- * @param __PLLI2SDIV__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @retval PLLI2S clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Helper macro to calculate the PLL2 frequency
- * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
- * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
- * @param __PLL2MUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL2_MUL_8
- * @arg @ref LL_RCC_PLL2_MUL_9
- * @arg @ref LL_RCC_PLL2_MUL_10
- * @arg @ref LL_RCC_PLL2_MUL_11
- * @arg @ref LL_RCC_PLL2_MUL_12
- * @arg @ref LL_RCC_PLL2_MUL_13
- * @arg @ref LL_RCC_PLL2_MUL_14
- * @arg @ref LL_RCC_PLL2_MUL_16
- * @arg @ref LL_RCC_PLL2_MUL_20
- * @param __PLL2DIV__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @retval PLL2 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Helper macro to calculate the HCLK frequency
- * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
- * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
- * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
- * @param __AHBPRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval HCLK clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
- * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
- * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB1PRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval PCLK1 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
- * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
- * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB2PRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval PCLK2 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_LL_EF_HSE HSE
- * @{
- */
-
-/**
- * @brief Enable the Clock Security System.
- * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
- SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
- * @brief Enable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Disable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Enable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Disable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Check if HSE oscillator Ready
- * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
-}
-
-#if defined(RCC_CFGR2_PREDIV2)
-/**
- * @brief Get PREDIV2 division factor
- * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
-}
-#endif /* RCC_CFGR2_PREDIV2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_HSI HSI
- * @{
- */
-
-/**
- * @brief Enable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Disable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Check if HSI clock is ready
- * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
-}
-
-/**
- * @brief Get HSI Calibration value
- * @note When HSITRIM is written, HSICAL is updated with the sum of
- * HSITRIM and the factory trim value
- * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
- * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
-}
-
-/**
- * @brief Set HSI Calibration trimming
- * @note user-programmable trimming value that is added to the HSICAL
- * @note Default value is 16, which, when added to the HSICAL value,
- * should trim the HSI to 16 MHz +/- 1 %
- * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
- * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @brief Get HSI Calibration trimming
- * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
- * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSE LSE
- * @{
- */
-
-/**
- * @brief Enable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Disable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Enable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Disable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Check if LSE oscillator Ready
- * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSI LSI
- * @{
- */
-
-/**
- * @brief Enable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Disable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
- CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Check if LSI is Ready
- * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_System System
- * @{
- */
-
-/**
- * @brief Configure the system clock source
- * @rmtoll CFGR SW LL_RCC_SetSysClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
- * @brief Get the system clock source
- * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
- * @brief Set AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
- * @brief Set APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
- * @brief Set APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
- * @brief Get AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
- * @brief Get APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
- * @brief Get APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_MCO MCO
- * @{
- */
-
-/**
- * @brief Configure MCOx
- * @rmtoll CFGR MCO LL_RCC_ConfigMCO
- * @param MCOxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
- * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
- * @arg @ref LL_RCC_MCO1SOURCE_HSI
- * @arg @ref LL_RCC_MCO1SOURCE_HSE
- * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
- * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
- * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
- * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
- * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
- * @{
- */
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/**
- * @brief Configure I2Sx clock source
- * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
- * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
-{
- MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
-}
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/**
- * @brief Configure USB clock source
- * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
- * CFGR USBPRE LL_RCC_SetUSBClockSource
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
-{
-#if defined(RCC_CFGR_USBPRE)
- MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
-#else /*RCC_CFGR_OTGFSPRE*/
- MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
-#endif /*RCC_CFGR_USBPRE*/
-}
-#endif /* USB_OTG_FS || USB */
-
-/**
- * @brief Configure ADC clock source
- * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
-}
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/**
- * @brief Get I2Sx clock source
- * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
- * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
- * @param I2Sx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE
- * @arg @ref LL_RCC_I2S3_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
-}
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/**
- * @brief Get USBx clock source
- * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
- * CFGR USBPRE LL_RCC_GetUSBClockSource
- * @param USBx This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
-}
-#endif /* USB_OTG_FS || USB */
-
-/**
- * @brief Get ADCx clock source
- * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
- * @param ADCx This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_RTC RTC
- * @{
- */
-
-/**
- * @brief Set RTC Clock Source
- * @note Once the RTC clock source has been selected, it cannot be changed any more unless
- * the Backup domain is reset. The BDRST bit can be used to reset them.
- * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
- * @brief Get RTC Clock Source
- * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
- */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
- * @brief Enable RTC
- * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Disable RTC
- * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Check if RTC has been enabled or not
- * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
-}
-
-/**
- * @brief Force the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @brief Release the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_PLL PLL
- * @{
- */
-
-/**
- * @brief Enable PLL
- * @rmtoll CR PLLON LL_RCC_PLL_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Disable PLL
- * @note Cannot be disabled if the PLL clock is used as the system clock
- * @rmtoll CR PLLON LL_RCC_PLL_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Check if PLL Ready
- * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
-}
-
-/**
- * @brief Configure PLL used for SYSCLK Domain
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
- *
- * (*) value not defined in all devices
- * @param PLLMul This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2 (*)
- * @arg @ref LL_RCC_PLL_MUL_3 (*)
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
- * @arg @ref LL_RCC_PLL_MUL_10 (*)
- * @arg @ref LL_RCC_PLL_MUL_11 (*)
- * @arg @ref LL_RCC_PLL_MUL_12 (*)
- * @arg @ref LL_RCC_PLL_MUL_13 (*)
- * @arg @ref LL_RCC_PLL_MUL_14 (*)
- * @arg @ref LL_RCC_PLL_MUL_15 (*)
- * @arg @ref LL_RCC_PLL_MUL_16 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
- (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul);
-#if defined(RCC_CFGR2_PREDIV1)
-#if defined(RCC_CFGR2_PREDIV1SRC)
- MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC),
- (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
-#else
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-#endif /*RCC_CFGR2_PREDIV1*/
-}
-
-/**
- * @brief Configure PLL clock source
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n
- * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource
- * @param PLLSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
-{
-#if defined(RCC_CFGR2_PREDIV1SRC)
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
-#endif /* RCC_CFGR2_PREDIV1SRC */
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
-}
-
-/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
- * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
-#if defined(RCC_CFGR2_PREDIV1SRC)
- register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
- register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
- return (uint32_t)(pllsrc | predivsrc);
-#else
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-}
-
-/**
- * @brief Get PLL multiplication Factor
- * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2 (*)
- * @arg @ref LL_RCC_PLL_MUL_3 (*)
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
- * @arg @ref LL_RCC_PLL_MUL_10 (*)
- * @arg @ref LL_RCC_PLL_MUL_11 (*)
- * @arg @ref LL_RCC_PLL_MUL_12 (*)
- * @arg @ref LL_RCC_PLL_MUL_13 (*)
- * @arg @ref LL_RCC_PLL_MUL_14 (*)
- * @arg @ref LL_RCC_PLL_MUL_15 (*)
- * @arg @ref LL_RCC_PLL_MUL_16 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
-}
-
-/**
- * @brief Get PREDIV1 division factor for the main PLL
- * @note They can be written only when the PLL is disabled
- * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
- * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PREDIV_DIV_1
- * @arg @ref LL_RCC_PREDIV_DIV_2
- * @arg @ref LL_RCC_PREDIV_DIV_3 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_4 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_5 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_6 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_7 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_8 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_9 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_10 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_11 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_12 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_13 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_14 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_15 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_16 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
-{
-#if defined(RCC_CFGR2_PREDIV1)
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
-#else
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
-#endif /*RCC_CFGR2_PREDIV1*/
-}
-
-/**
- * @}
- */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
- * @{
- */
-
-/**
- * @brief Enable PLLI2S
- * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLL3ON);
-}
-
-/**
- * @brief Disable PLLI2S
- * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
-}
-
-/**
- * @brief Check if PLLI2S Ready
- * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
-}
-
-/**
- * @brief Configure PLLI2S used for I2S Domain
- * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
- * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
- * @param Divider This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @param Multiplicator This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLI2S_MUL_8
- * @arg @ref LL_RCC_PLLI2S_MUL_9
- * @arg @ref LL_RCC_PLLI2S_MUL_10
- * @arg @ref LL_RCC_PLLI2S_MUL_11
- * @arg @ref LL_RCC_PLLI2S_MUL_12
- * @arg @ref LL_RCC_PLLI2S_MUL_13
- * @arg @ref LL_RCC_PLLI2S_MUL_14
- * @arg @ref LL_RCC_PLLI2S_MUL_16
- * @arg @ref LL_RCC_PLLI2S_MUL_20
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
-{
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator);
-}
-
-/**
- * @brief Get PLLI2S Multiplication Factor
- * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLI2S_MUL_8
- * @arg @ref LL_RCC_PLLI2S_MUL_9
- * @arg @ref LL_RCC_PLLI2S_MUL_10
- * @arg @ref LL_RCC_PLLI2S_MUL_11
- * @arg @ref LL_RCC_PLLI2S_MUL_12
- * @arg @ref LL_RCC_PLLI2S_MUL_13
- * @arg @ref LL_RCC_PLLI2S_MUL_14
- * @arg @ref LL_RCC_PLLI2S_MUL_16
- * @arg @ref LL_RCC_PLLI2S_MUL_20
- */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
-}
-
-/**
- * @}
- */
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/** @defgroup RCC_LL_EF_PLL2 PLL2
- * @{
- */
-
-/**
- * @brief Enable PLL2
- * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLL2ON);
-}
-
-/**
- * @brief Disable PLL2
- * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
-}
-
-/**
- * @brief Check if PLL2 Ready
- * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
-}
-
-/**
- * @brief Configure PLL2 used for PLL2 Domain
- * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
- * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
- * @param Divider This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @param Multiplicator This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL2_MUL_8
- * @arg @ref LL_RCC_PLL2_MUL_9
- * @arg @ref LL_RCC_PLL2_MUL_10
- * @arg @ref LL_RCC_PLL2_MUL_11
- * @arg @ref LL_RCC_PLL2_MUL_12
- * @arg @ref LL_RCC_PLL2_MUL_13
- * @arg @ref LL_RCC_PLL2_MUL_14
- * @arg @ref LL_RCC_PLL2_MUL_16
- * @arg @ref LL_RCC_PLL2_MUL_20
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
-{
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator);
-}
-
-/**
- * @brief Get PLL2 Multiplication Factor
- * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLL2_MUL_8
- * @arg @ref LL_RCC_PLL2_MUL_9
- * @arg @ref LL_RCC_PLL2_MUL_10
- * @arg @ref LL_RCC_PLL2_MUL_11
- * @arg @ref LL_RCC_PLL2_MUL_12
- * @arg @ref LL_RCC_PLL2_MUL_13
- * @arg @ref LL_RCC_PLL2_MUL_14
- * @arg @ref LL_RCC_PLL2_MUL_16
- * @arg @ref LL_RCC_PLL2_MUL_20
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
-}
-
-/**
- * @}
- */
-#endif /* RCC_PLL2_SUPPORT */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Clear LSI ready interrupt flag
- * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
-}
-
-/**
- * @brief Clear LSE ready interrupt flag
- * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
-}
-
-/**
- * @brief Clear HSI ready interrupt flag
- * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
-}
-
-/**
- * @brief Clear HSE ready interrupt flag
- * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
-}
-
-/**
- * @brief Clear PLL ready interrupt flag
- * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Clear PLLI2S ready interrupt flag
- * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Clear PLL2 ready interrupt flag
- * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Clear Clock security system interrupt flag
- * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_CSSC);
-}
-
-/**
- * @brief Check if LSI ready interrupt occurred or not
- * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
-}
-
-/**
- * @brief Check if LSE ready interrupt occurred or not
- * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
-}
-
-/**
- * @brief Check if HSI ready interrupt occurred or not
- * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
-}
-
-/**
- * @brief Check if HSE ready interrupt occurred or not
- * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
-}
-
-/**
- * @brief Check if PLL ready interrupt occurred or not
- * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Check if PLLI2S ready interrupt occurred or not
- * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Check if PLL2 ready interrupt occurred or not
- * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Check if Clock security system interrupt occurred or not
- * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
-}
-
-/**
- * @brief Check if RCC flag Independent Watchdog reset is set or not.
- * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
-}
-
-/**
- * @brief Check if RCC flag Low Power reset is set or not.
- * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
-}
-
-/**
- * @brief Check if RCC flag Pin reset is set or not.
- * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
-}
-
-/**
- * @brief Check if RCC flag POR/PDR reset is set or not.
- * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
-}
-
-/**
- * @brief Check if RCC flag Software reset is set or not.
- * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
-}
-
-/**
- * @brief Check if RCC flag Window Watchdog reset is set or not.
- * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
-}
-
-/**
- * @brief Set RMVF bit to clear the reset flags.
- * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
- * @{
- */
-
-/**
- * @brief Enable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Enable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Enable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Enable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Enable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Enable PLLI2S ready interrupt
- * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Enable PLL2 ready interrupt
- * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Disable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Disable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Disable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Disable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Disable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Disable PLLI2S ready interrupt
- * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Disable PLL2 ready interrupt
- * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Checks if LSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
-}
-
-/**
- * @brief Checks if LSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
-}
-
-/**
- * @brief Checks if HSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
-}
-
-/**
- * @brief Checks if HSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
-}
-
-/**
- * @brief Checks if PLL ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_RCC_DeInit(void);
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
- * @{
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-#if defined(RCC_CFGR2_I2S2SRC)
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-#endif /* RCC_CFGR2_I2S2SRC */
-#if defined(USB_OTG_FS) || defined(USB)
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-#endif /* USB_OTG_FS || USB */
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* RCC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_rcc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_rtc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1019 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_rtc.h
- * @author MCD Application Team
- * @brief Header file of RTC LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_RTC_H
-#define __STM32F1xx_LL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RTC)
-
-/** @defgroup RTC_LL RTC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_Private_Macros RTC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
- * @{
- */
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetAsynchPrescaler(). */
-
- uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin.
- This parameter can be a value of @ref LL_RTC_Output_Source
-
- This feature can be modified afterwards using unitary function
- @ref LL_RTC_SetOutputSource(). */
-
-} LL_RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t Hours; /*!< Specifies the RTC Time Hours.
- This parameter must be a number between Min_Data = 0 and Max_Data = 23 */
-
- uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
- uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-} LL_RTC_TimeTypeDef;
-
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
-} LL_RTC_AlarmTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
- * @{
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EC_FORMAT FORMAT
- * @{
- */
-#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup RTC_LL_EC_BKP BACKUP
- * @{
- */
-#if RTC_BKP_NUMBER > 0
-#define LL_RTC_BKP_DR1 (0x00000001U)
-#define LL_RTC_BKP_DR2 (0x00000002U)
-#define LL_RTC_BKP_DR3 (0x00000003U)
-#define LL_RTC_BKP_DR4 (0x00000004U)
-#define LL_RTC_BKP_DR5 (0x00000005U)
-#define LL_RTC_BKP_DR6 (0x00000006U)
-#define LL_RTC_BKP_DR7 (0x00000007U)
-#define LL_RTC_BKP_DR8 (0x00000008U)
-#define LL_RTC_BKP_DR9 (0x00000009U)
-#define LL_RTC_BKP_DR10 (0x0000000AU)
-#endif /* RTC_BKP_NUMBER > 0 */
-#if RTC_BKP_NUMBER > 10
-#define LL_RTC_BKP_DR11 (0x0000000BU)
-#define LL_RTC_BKP_DR12 (0x0000000CU)
-#define LL_RTC_BKP_DR13 (0x0000000DU)
-#define LL_RTC_BKP_DR14 (0x0000000EU)
-#define LL_RTC_BKP_DR15 (0x0000000FU)
-#define LL_RTC_BKP_DR16 (0x00000010U)
-#define LL_RTC_BKP_DR17 (0x00000011U)
-#define LL_RTC_BKP_DR18 (0x00000012U)
-#define LL_RTC_BKP_DR19 (0x00000013U)
-#define LL_RTC_BKP_DR20 (0x00000014U)
-#define LL_RTC_BKP_DR21 (0x00000015U)
-#define LL_RTC_BKP_DR22 (0x00000016U)
-#define LL_RTC_BKP_DR23 (0x00000017U)
-#define LL_RTC_BKP_DR24 (0x00000018U)
-#define LL_RTC_BKP_DR25 (0x00000019U)
-#define LL_RTC_BKP_DR26 (0x0000001AU)
-#define LL_RTC_BKP_DR27 (0x0000001BU)
-#define LL_RTC_BKP_DR28 (0x0000001CU)
-#define LL_RTC_BKP_DR29 (0x0000001DU)
-#define LL_RTC_BKP_DR30 (0x0000001EU)
-#define LL_RTC_BKP_DR31 (0x0000001FU)
-#define LL_RTC_BKP_DR32 (0x00000020U)
-#define LL_RTC_BKP_DR33 (0x00000021U)
-#define LL_RTC_BKP_DR34 (0x00000022U)
-#define LL_RTC_BKP_DR35 (0x00000023U)
-#define LL_RTC_BKP_DR36 (0x00000024U)
-#define LL_RTC_BKP_DR37 (0x00000025U)
-#define LL_RTC_BKP_DR38 (0x00000026U)
-#define LL_RTC_BKP_DR39 (0x00000027U)
-#define LL_RTC_BKP_DR40 (0x00000028U)
-#define LL_RTC_BKP_DR41 (0x00000029U)
-#define LL_RTC_BKP_DR42 (0x0000002AU)
-#endif /* RTC_BKP_NUMBER > 10 */
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EC_TAMPLEVEL Tamper Active Level
- * @{
- */
-#define LL_RTC_TAMPER_ACTIVELEVEL_LOW BKP_CR_TPAL /*!< A high level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
-#define LL_RTC_TAMPER_ACTIVELEVEL_HIGH (0x00000000U) /*!< A low level on the TAMPER pin resets all data backup registers (if TPE bit is set) */
-
-/**
- * @}
- */
-
-/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin
- * @{
- */
-#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */
-#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */
-#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */
-#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros
- * @{
- */
-
-/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RTC register
- * @param __INSTANCE__ RTC Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RTC register
- * @param __INSTANCE__ RTC Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EM_Convert Convert helper Macros
- * @{
- */
-
-/**
- * @brief Helper macro to convert a value from 2 digit decimal format to BCD format
- * @param __VALUE__ Byte to be converted
- * @retval Converted byte
- */
-#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
-
-/**
- * @brief Helper macro to convert a value from BCD format to 2 digit decimal format
- * @param __VALUE__ BCD value to be converted
- * @retval Converted byte
- */
-#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
- * @{
- */
-
-/** @defgroup RTC_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Set Asynchronous prescaler factor
- * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n
- * @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n
- * @param RTCx RTC Instance
- * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
-{
- MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16));
- MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL));
-}
-
-/**
- * @brief Get Asynchronous prescaler factor
- * @rmtoll DIVH DIV LL_RTC_GetDivider\n
- * @rmtoll DIVL DIV LL_RTC_GetDivider\n
- * @param RTCx RTC Instance
- * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx)
-{
- register uint16_t Highprescaler = 0 , Lowprescaler = 0;
- Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV);
- Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV);
-
- return (((uint32_t) Highprescaler << 16U) | Lowprescaler);
-}
-
-/**
- * @brief Set Output Source
- * @rmtoll RTCCR CCO LL_RTC_SetOutputSource
- * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource
- * @rmtoll RTCCR ASOS LL_RTC_SetOutputSource
- * @param BKPx BKP Instance
- * @param OutputSource This parameter can be one of the following values:
- * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
- * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK
- * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM
- * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_SetOutputSource(BKP_TypeDef *BKPx, uint32_t OutputSource)
-{
- MODIFY_REG(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource);
-}
-
-/**
- * @brief Get Output Source
- * @rmtoll RTCCR CCO LL_RTC_GetOutPutSource
- * @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource
- * @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource
- * @param BKPx BKP Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RTC_CALIB_OUTPUT_NONE
- * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK
- * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM
- * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND
- */
-__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(BKP_TypeDef *BKPx)
-{
- return (uint32_t)(READ_BIT(BKPx->RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS)));
-}
-
-/**
- * @brief Enable the write protection for RTC registers.
- * @rmtoll CRL CNF LL_RTC_EnableWriteProtection
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF);
-}
-
-/**
- * @brief Disable the write protection for RTC registers.
- * @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CRL, RTC_CRL_CNF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Time Time
- * @{
- */
-
-/**
- * @brief Set time counter in BCD format
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function)
- * @rmtoll CNTH CNT LL_RTC_TIME_Set\n
- * CNTL CNT LL_RTC_TIME_Set\n
- * @param RTCx RTC Instance
- * @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter)
-{
- /* Set RTC COUNTER MSB word */
- WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U));
- /* Set RTC COUNTER LSB word */
- WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT));
-}
-
-/**
- * @brief Get time counter in BCD format
- * @rmtoll CNTH CNT LL_RTC_TIME_Get\n
- * CNTL CNT LL_RTC_TIME_Get\n
- * @param RTCx RTC Instance
- * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
-{
- register uint16_t high = 0, low = 0;
-
- high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT);
- low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT);
- return ((uint32_t)(((uint32_t) high << 16U) | low));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_ALARM ALARM
- * @{
- */
-
-/**
- * @brief Set Alarm Counter
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll ALRH ALR LL_RTC_ALARM_Set\n
- * @rmtoll ALRL ALR LL_RTC_ALARM_Set\n
- * @param RTCx RTC Instance
- * @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter)
-{
- /* Set RTC COUNTER MSB word */
- WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16));
- /* Set RTC COUNTER LSB word */
- WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR));
-}
-
-/**
- * @brief Get Alarm Counter
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll ALRH ALR LL_RTC_ALARM_Get\n
- * @rmtoll ALRL ALR LL_RTC_ALARM_Get\n
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE uint32_t LL_RTC_ALARM_Get(RTC_TypeDef *RTCx)
-{
- register uint16_t high = 0, low = 0;
-
- high = READ_REG(RTCx->ALRH & RTC_ALRH_RTC_ALR);
- low = READ_REG(RTCx->ALRL & RTC_ALRL_RTC_ALR);
-
- return (((uint32_t) high << 16U) | low);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Tamper Tamper
- * @{
- */
-
-/**
- * @brief Enable RTC_TAMPx input detection
- * @rmtoll CR TPE LL_RTC_TAMPER_Enable\n
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_Enable(BKP_TypeDef *BKPx)
-{
- SET_BIT(BKPx->CR, BKP_CR_TPE);
-}
-
-/**
- * @brief Disable RTC_TAMPx Tamper
- * @rmtoll CR TPE LL_RTC_TAMPER_Disable\n
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_Disable(BKP_TypeDef *BKPx)
-{
- CLEAR_BIT(BKP->CR, BKP_CR_TPE);
-}
-
-/**
- * @brief Enable Active level for Tamper input
- * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n
- * @param BKPx BKP Instance
- * @param Tamper This parameter can be a combination of the following values:
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_LOW
- * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_TAMPER_SetActiveLevel(BKP_TypeDef *BKPx, uint32_t Tamper)
-{
- MODIFY_REG(BKPx->CR, BKP_CR_TPAL, Tamper);
-}
-
-/**
- * @brief Disable Active level for Tamper input
- * @rmtoll CR TPAL LL_RTC_TAMPER_SetActiveLevel\n
- * @retval None
- */
-__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetActiveLevel(BKP_TypeDef *BKPx)
-{
- return (uint32_t)(READ_BIT(BKPx->CR, BKP_CR_TPAL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @rmtoll BKPDR DR LL_RTC_BKP_SetRegister
- * @param BKPx BKP Instance
- * @param BackupRegister This parameter can be one of the following values:
- * @arg @ref LL_RTC_BKP_DR1
- * @arg @ref LL_RTC_BKP_DR2
- * @arg @ref LL_RTC_BKP_DR3
- * @arg @ref LL_RTC_BKP_DR4
- * @arg @ref LL_RTC_BKP_DR5
- * @arg @ref LL_RTC_BKP_DR6
- * @arg @ref LL_RTC_BKP_DR7
- * @arg @ref LL_RTC_BKP_DR8
- * @arg @ref LL_RTC_BKP_DR9
- * @arg @ref LL_RTC_BKP_DR10
- * @arg @ref LL_RTC_BKP_DR11 (*)
- * @arg @ref LL_RTC_BKP_DR12 (*)
- * @arg @ref LL_RTC_BKP_DR13 (*)
- * @arg @ref LL_RTC_BKP_DR14 (*)
- * @arg @ref LL_RTC_BKP_DR15 (*)
- * @arg @ref LL_RTC_BKP_DR16 (*)
- * @arg @ref LL_RTC_BKP_DR17 (*)
- * @arg @ref LL_RTC_BKP_DR18 (*)
- * @arg @ref LL_RTC_BKP_DR19 (*)
- * @arg @ref LL_RTC_BKP_DR20 (*)
- * @arg @ref LL_RTC_BKP_DR21 (*)
- * @arg @ref LL_RTC_BKP_DR22 (*)
- * @arg @ref LL_RTC_BKP_DR23 (*)
- * @arg @ref LL_RTC_BKP_DR24 (*)
- * @arg @ref LL_RTC_BKP_DR25 (*)
- * @arg @ref LL_RTC_BKP_DR26 (*)
- * @arg @ref LL_RTC_BKP_DR27 (*)
- * @arg @ref LL_RTC_BKP_DR28 (*)
- * @arg @ref LL_RTC_BKP_DR29 (*)
- * @arg @ref LL_RTC_BKP_DR30 (*)
- * @arg @ref LL_RTC_BKP_DR31 (*)
- * @arg @ref LL_RTC_BKP_DR32 (*)
- * @arg @ref LL_RTC_BKP_DR33 (*)
- * @arg @ref LL_RTC_BKP_DR34 (*)
- * @arg @ref LL_RTC_BKP_DR35 (*)
- * @arg @ref LL_RTC_BKP_DR36 (*)
- * @arg @ref LL_RTC_BKP_DR37 (*)
- * @arg @ref LL_RTC_BKP_DR38 (*)
- * @arg @ref LL_RTC_BKP_DR39 (*)
- * @arg @ref LL_RTC_BKP_DR40 (*)
- * @arg @ref LL_RTC_BKP_DR41 (*)
- * @arg @ref LL_RTC_BKP_DR42 (*)
- * (*) value not defined in all devices.
- * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_BKP_SetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister, uint32_t Data)
-{
- register uint32_t tmp = 0U;
-
- tmp = (uint32_t)BKP_BASE;
- tmp += (BackupRegister * 4U);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @rmtoll BKPDR DR LL_RTC_BKP_GetRegister
- * @param BKPx BKP Instance
- * @param BackupRegister This parameter can be one of the following values:
- * @arg @ref LL_RTC_BKP_DR1
- * @arg @ref LL_RTC_BKP_DR2
- * @arg @ref LL_RTC_BKP_DR3
- * @arg @ref LL_RTC_BKP_DR4
- * @arg @ref LL_RTC_BKP_DR5
- * @arg @ref LL_RTC_BKP_DR6
- * @arg @ref LL_RTC_BKP_DR7
- * @arg @ref LL_RTC_BKP_DR8
- * @arg @ref LL_RTC_BKP_DR9
- * @arg @ref LL_RTC_BKP_DR10
- * @arg @ref LL_RTC_BKP_DR11 (*)
- * @arg @ref LL_RTC_BKP_DR12 (*)
- * @arg @ref LL_RTC_BKP_DR13 (*)
- * @arg @ref LL_RTC_BKP_DR14 (*)
- * @arg @ref LL_RTC_BKP_DR15 (*)
- * @arg @ref LL_RTC_BKP_DR16 (*)
- * @arg @ref LL_RTC_BKP_DR17 (*)
- * @arg @ref LL_RTC_BKP_DR18 (*)
- * @arg @ref LL_RTC_BKP_DR19 (*)
- * @arg @ref LL_RTC_BKP_DR20 (*)
- * @arg @ref LL_RTC_BKP_DR21 (*)
- * @arg @ref LL_RTC_BKP_DR22 (*)
- * @arg @ref LL_RTC_BKP_DR23 (*)
- * @arg @ref LL_RTC_BKP_DR24 (*)
- * @arg @ref LL_RTC_BKP_DR25 (*)
- * @arg @ref LL_RTC_BKP_DR26 (*)
- * @arg @ref LL_RTC_BKP_DR27 (*)
- * @arg @ref LL_RTC_BKP_DR28 (*)
- * @arg @ref LL_RTC_BKP_DR29 (*)
- * @arg @ref LL_RTC_BKP_DR30 (*)
- * @arg @ref LL_RTC_BKP_DR31 (*)
- * @arg @ref LL_RTC_BKP_DR32 (*)
- * @arg @ref LL_RTC_BKP_DR33 (*)
- * @arg @ref LL_RTC_BKP_DR34 (*)
- * @arg @ref LL_RTC_BKP_DR35 (*)
- * @arg @ref LL_RTC_BKP_DR36 (*)
- * @arg @ref LL_RTC_BKP_DR37 (*)
- * @arg @ref LL_RTC_BKP_DR38 (*)
- * @arg @ref LL_RTC_BKP_DR39 (*)
- * @arg @ref LL_RTC_BKP_DR40 (*)
- * @arg @ref LL_RTC_BKP_DR41 (*)
- * @arg @ref LL_RTC_BKP_DR42 (*)
- * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(BKP_TypeDef *BKPx, uint32_t BackupRegister)
-{
- register uint32_t tmp = 0U;
-
- tmp = (uint32_t)BKP_BASE;
- tmp += (BackupRegister * 4U);
-
- /* Read the specified register */
- return ((*(__IO uint32_t *)tmp) & BKP_DR1_D);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_Calibration Calibration
- * @{
- */
-
-/**
- * @brief Set the coarse digital calibration
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function)
- * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n
- * @param BKPx RTC Instance
- * @param Value value of coarse calibration expressed in ppm (coded on 5 bits)
- * @note This Calibration value should be between 0 and 121 when using positive sign with a 4-ppm step.
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(BKP_TypeDef* BKPx, uint32_t Value)
-{
- MODIFY_REG(BKPx->RTCCR,BKP_RTCCR_CAL, Value);
-}
-
-/**
- * @brief Get the coarse digital calibration value
- * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n
- * @param BKPx BKP Instance
- * @retval value of coarse calibration expressed in ppm (coded on 5 bits)
- */
-__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(BKP_TypeDef *BKPx)
-{
- return (uint32_t)(READ_BIT(BKPx->RTCCR, BKP_RTCCR_CAL));
-}
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get RTC_TAMPI Interruption detection flag
- * @rmtoll CSR TIF LL_RTC_IsActiveFlag_TAMPI
- * @param BKPx BKP Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPI(BKP_TypeDef *BKPx)
-{
- return (READ_BIT(BKPx->CSR, BKP_CSR_TIF) == (BKP_CSR_TIF));
-}
-
-/**
- * @brief Clear RTC_TAMP Interruption detection flag
- * @rmtoll CSR CTI LL_RTC_ClearFlag_TAMPI
- * @param BKPx BKP Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMPI(BKP_TypeDef *BKPx)
-{
- SET_BIT(BKPx->CSR, BKP_CSR_CTI);
-}
-
-/**
- * @brief Get RTC_TAMPE Event detection flag
- * @rmtoll CSR TEF LL_RTC_IsActiveFlag_TAMPE
- * @param BKPx BKP Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMPE(BKP_TypeDef *BKPx)
-{
- return (READ_BIT(BKPx->CSR, BKP_CSR_TEF) == (BKP_CSR_TEF));
-}
-
-/**
- * @brief Clear RTC_TAMPE Even detection flag
- * @rmtoll CSR CTE LL_RTC_ClearFlag_TAMPE
- * @param BKPx BKP Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_TAMPE(BKP_TypeDef *BKPx)
-{
- SET_BIT(BKPx->CSR, BKP_CSR_CTE);
-}
-
-/**
- * @brief Get Alarm flag
- * @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF));
-}
-
-/**
- * @brief Clear Alarm flag
- * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF);
-}
-
-/**
- * @brief Get Registers synchronization flag
- * @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF));
-}
-
-/**
- * @brief Clear Registers synchronization flag
- * @rmtoll CRL RSF LL_RTC_ClearFlag_RS
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF);
-}
-
-/**
- * @brief Get Registers OverFlow flag
- * @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF));
-}
-
-/**
- * @brief Clear Registers OverFlow flag
- * @rmtoll CRL OWF LL_RTC_ClearFlag_OW
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF);
-}
-
-/**
- * @brief Get Registers synchronization flag
- * @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF));
-}
-
-/**
- * @brief Clear Registers synchronization flag
- * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF);
-}
-
-/**
- * @brief Get RTC Operation OFF status flag
- * @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable Alarm interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CRH, RTC_CRH_ALRIE);
-}
-
-/**
- * @brief Disable Alarm interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE);
-}
-
-/**
- * @brief Check if Alarm interrupt is enabled or not
- * @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE));
-}
-
-/**
- * @brief Enable Second Interrupt interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CRH SECIE LL_RTC_EnableIT_SEC
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CRH, RTC_CRH_SECIE);
-}
-
-/**
- * @brief Disable Second interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CRH SECIE LL_RTC_DisableIT_SEC
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE);
-}
-
-/**
- * @brief Check if Second interrupt is enabled or not
- * @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE));
-}
-
-/**
- * @brief Enable OverFlow interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CRH OWIE LL_RTC_EnableIT_OW
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx)
-{
- SET_BIT(RTCx->CRH, RTC_CRH_OWIE);
-}
-
-/**
- * @brief Disable OverFlow interrupt
- * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
- * @rmtoll CRH OWIE LL_RTC_DisableIT_OW
- * @param RTCx RTC Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx)
-{
- CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE);
-}
-
-/**
- * @brief Check if OverFlow interrupt is enabled or not
- * @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW
- * @param RTCx RTC Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx)
-{
- return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE));
-}
-
-/**
- * @brief Enable Tamper interrupt
- * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP
- * @param BKPx BKP Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_EnableIT_TAMP(BKP_TypeDef *BKPx)
-{
- SET_BIT(BKPx->CSR,BKP_CSR_TPIE);
-}
-
-/**
- * @brief Disable Tamper interrupt
- * @rmtoll CSR TPIE LL_RTC_EnableIT_TAMP
- * @param BKPx BKP Instance
- * @retval None
- */
-__STATIC_INLINE void LL_RTC_DisableIT_TAMP(BKP_TypeDef *BKPx)
-{
- CLEAR_BIT(BKPx->CSR,BKP_CSR_TPIE);
-}
-
-/**
- * @brief Check if all the TAMPER interrupts are enabled or not
- * @rmtoll CSR TPIE LL_RTC_IsEnabledIT_TAMP
- * @param BKPx BKP Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(BKP_TypeDef *BKPx)
-{
- return (READ_BIT(BKPx->CSR,BKP_CSR_TPIE) == BKP_CSR_TPIE);
-}
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
-void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
-ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
-void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
-ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
-ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
-ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter);
-ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RTC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_rtc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_sdmmc.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1125 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_sdmmc.h
- * @author MCD Application Team
- * @brief Header file of low layer SDMMC HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __stm32f1xx_LL_SD_H
-#define __stm32f1xx_LL_SD_H
-
-#if defined(STM32F103xE) || defined(STM32F103xG)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup SDMMC_LL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
- * @{
- */
-
-/**
- * @brief SDMMC Configuration Structure definition
- */
-typedef struct
-{
- uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
-
- uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
- enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
-
- uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
- disabled when the bus is idle.
- This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
-
- uint32_t BusWide; /*!< Specifies the SDIO bus width.
- This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
-
- uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
-
- uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
- This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
-
-}SDIO_InitTypeDef;
-
-
-/**
- * @brief SDIO Command Control structure
- */
-typedef struct
-{
- uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
- to a card as part of a command message. If a command
- contains an argument, it must be loaded into this register
- before writing the command to the command register. */
-
- uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
- Max_Data = 64 */
-
- uint32_t Response; /*!< Specifies the SDIO response type.
- This parameter can be a value of @ref SDMMC_LL_Response_Type */
-
- uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
- enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
-
- uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_CPSM_State */
-}SDIO_CmdInitTypeDef;
-
-
-/**
- * @brief SDIO Data Control structure
- */
-typedef struct
-{
- uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
-
- uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
-
- uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
- This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
-
- uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
- is a read or write.
- This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
-
- uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
- This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
-
- uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
- is enabled or disabled.
- This parameter can be a value of @ref SDMMC_LL_DPSM_State */
-}SDIO_DataInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
- * @{
- */
-#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */
-#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */
-#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */
-#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */
-#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */
-#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */
-#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */
-#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */
-#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
- number of transferred bytes does not match the block length */
-#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */
-#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */
-#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
- command or if there was an attempt to access a locked card */
-#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */
-#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */
-#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */
-#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */
-#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */
-#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */
-#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */
-#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */
-#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */
-#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */
-#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
- of erase sequence command was received */
-#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */
-#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */
-#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */
-#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */
-#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */
-#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */
-#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */
-#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */
-#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */
-
-/**
- * @brief SDMMC Commands Index
- */
-#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */
-#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
-#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */
-#define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
- operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
-#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */
-#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
- and asks the card whether card supports voltage. */
-#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
-#define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */
-#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */
-#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */
-#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */
-#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */
-#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */
-#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
- (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
- for SDHS and SDXC. */
-#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
- STOP_TRANSMISSION command. */
-#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
-#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */
-#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
- fixed 512 bytes in case of SDHC and SDXC. */
-#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
-#define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */
-#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */
-#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */
-#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */
-#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */
-#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */
-#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */
-#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
- system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
- Reserved for each command system set by switch function command (CMD6). */
-#define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */
-#define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */
-#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
- the SET_BLOCK_LEN command. */
-#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
- than a standard command. */
-#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
- for general purpose/application specific commands. */
-#define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */
-
-/**
- * @brief Following commands are SD Card Specific commands.
- * SDMMC_APP_CMD should be sent before sending these commands.
- */
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
- widths are given in SCR register. */
-#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
- 32bit+CRC data block. */
-#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
- send its operating condition register (OCR) content in the response on the CMD line. */
-#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
-#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */
-#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */
-#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */
-
-/**
- * @brief Following commands are SD Card Specific security commands.
- * SDMMC_CMD_APP_CMD should be sent before sending these commands.
- */
-#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
-#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
-#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
-#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
-#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
-#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
-#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
-#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
-#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
-#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
-
-/**
- * @brief Masks for errors Card Status R1 (OCR Register)
- */
-#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
-#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
-#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
-#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
-#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
-#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
-#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
-#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
-#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
-#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
-#define SDMMC_OCR_CC_ERROR 0x00100000U
-#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
-#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
-#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
-#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
-#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
-#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
-#define SDMMC_OCR_ERASE_RESET 0x00002000U
-#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
-#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
-
-/**
- * @brief Masks for R6 Response
- */
-#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
-#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
-#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
-
-#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
-#define SDMMC_HIGH_CAPACITY 0x40000000U
-#define SDMMC_STD_CAPACITY 0x00000000U
-#define SDMMC_CHECK_PATTERN 0x000001AAU
-
-#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
-
-#define SDMMC_MAX_TRIAL 0x0000FFFFU
-
-#define SDMMC_ALLZERO 0x00000000U
-
-#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
-#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
-#define SDMMC_CARD_LOCKED 0x02000000U
-
-#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
-
-#define SDMMC_0TO7BITS 0x000000FFU
-#define SDMMC_8TO15BITS 0x0000FF00U
-#define SDMMC_16TO23BITS 0x00FF0000U
-#define SDMMC_24TO31BITS 0xFF000000U
-#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
-
-#define SDMMC_HALFFIFO 0x00000008U
-#define SDMMC_HALFFIFOBYTES 0x00000020U
-
-/**
- * @brief Command Class supported
- */
-#define SDIO_CCCC_ERASE 0x00000020U
-
-#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
-#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
-
-
-/** @defgroup SDIO_LL_Clock_Edge Clock Edge
- * @{
- */
-#define SDIO_CLOCK_EDGE_RISING 0x00000000U
-#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
-
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
- ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
- * @{
- */
-#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
-#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
-
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
- ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
- * @{
- */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
-#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
-
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
- ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Bus_Wide Bus Width
- * @{
- */
-#define SDIO_BUS_WIDE_1B 0x00000000U
-#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
-#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
-
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
- ((WIDE) == SDIO_BUS_WIDE_4B) || \
- ((WIDE) == SDIO_BUS_WIDE_8B))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
- * @{
- */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
-#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
-
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
- ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Clock_Division Clock Division
- * @{
- */
-#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Command_Index Command Index
- * @{
- */
-#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Response_Type Response Type
- * @{
- */
-#define SDIO_RESPONSE_NO 0x00000000U
-#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
-#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
-
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
- ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
- ((RESPONSE) == SDIO_RESPONSE_LONG))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
- * @{
- */
-#define SDIO_WAIT_NO 0x00000000U
-#define SDIO_WAIT_IT SDIO_CMD_WAITINT
-#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
-
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
- ((WAIT) == SDIO_WAIT_IT) || \
- ((WAIT) == SDIO_WAIT_PEND))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_CPSM_State CPSM State
- * @{
- */
-#define SDIO_CPSM_DISABLE 0x00000000U
-#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
-
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
- ((CPSM) == SDIO_CPSM_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Response_Registers Response Register
- * @{
- */
-#define SDIO_RESP1 0x00000000U
-#define SDIO_RESP2 0x00000004U
-#define SDIO_RESP3 0x00000008U
-#define SDIO_RESP4 0x0000000CU
-
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
- ((RESP) == SDIO_RESP2) || \
- ((RESP) == SDIO_RESP3) || \
- ((RESP) == SDIO_RESP4))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Data_Length Data Lenght
- * @{
- */
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
- * @{
- */
-#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
-#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
-#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
-#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
-#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
-
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
- ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
- * @{
- */
-#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
-#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
-
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
- ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Transfer_Type Transfer Type
- * @{
- */
-#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
-#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
-
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
- ((MODE) == SDIO_TRANSFER_MODE_STREAM))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_DPSM_State DPSM State
- * @{
- */
-#define SDIO_DPSM_DISABLE 0x00000000U
-#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
-
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
- ((DPSM) == SDIO_DPSM_ENABLE))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
- * @{
- */
-#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
-#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
-
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
- ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
- * @{
- */
-#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
-#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
-#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
-#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
-#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
-#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
-#define SDIO_IT_CMDREND SDIO_STA_CMDREND
-#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
-#define SDIO_IT_DATAEND SDIO_STA_DATAEND
-#define SDIO_IT_STBITERR SDIO_STA_STBITERR
-#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
-#define SDIO_IT_CMDACT SDIO_STA_CMDACT
-#define SDIO_IT_TXACT SDIO_STA_TXACT
-#define SDIO_IT_RXACT SDIO_STA_RXACT
-#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
-#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
-#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
-#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
-#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
-#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
-#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
-#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
-#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
-#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
-/**
- * @}
- */
-
-/** @defgroup SDMMC_LL_Flags Flags
- * @{
- */
-#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
-#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
-#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
-#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
-#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
-#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
-#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
-#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
-#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
-#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
-#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
-#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
-#define SDIO_FLAG_TXACT SDIO_STA_TXACT
-#define SDIO_FLAG_RXACT SDIO_STA_RXACT
-#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
-#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
-#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
-#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
-#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
-#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
-#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
-#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
-#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
-#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
-#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
- SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\
- SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\
- SDIO_FLAG_DBCKEND))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
- * @{
- */
-
-/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
- * @{
- */
-/* ------------ SDIO registers bit address in the alias region -------------- */
-#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
-#define CLKEN_BITNUMBER 0x08U
-#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
-#define SDIOSUSPEND_BITNUMBER 0x0BU
-#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BITNUMBER 0x0CU
-#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BITNUMBER 0x0DU
-#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BITNUMBER 0x0EU
-#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
-#define DMAEN_BITNUMBER 0x03U
-#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BITNUMBER 0x08U
-#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BITNUMBER 0x09U
-#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BITNUMBER 0x0AU
-#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BITNUMBER 0x0BU
-#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
- * @brief SDIO_LL registers bit address in the alias region
- * @{
- */
-/* ---------------------- SDIO registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */
-#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
- SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
- SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
- SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
- SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
- SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
-
-/* SDIO Intialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0xC3)
-
-/* SDIO Data Transfer Frequency */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9)
-
-/**
- * @}
- */
-
-/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/**
- * @brief Enable the SDIO device.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
-
-/**
- * @brief Disable the SDIO device.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
-
-/**
- * @brief Enable the SDIO DMA transfer.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
-/**
- * @brief Disable the SDIO DMA transfer.
- * @param __INSTANCE__: SDIO Instance
- * @retval None
- */
-#define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
-
-/**
- * @brief Enable the SDIO device interrupt.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
- * @brief Disable the SDIO device interrupt.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
- * @brief Checks whether the specified SDIO flag is set or not.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_CMDACT: Command transfer in progress
- * @arg SDIO_FLAG_TXACT: Data transmit in progress
- * @arg SDIO_FLAG_RXACT: Data receive in progress
- * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
- * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
- * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
- * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
- * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
- * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
- * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
- * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval The new state of SDIO_FLAG (SET or RESET).
- */
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
-
-
-/**
- * @brief Clears the SDIO pending flags.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __FLAG__: specifies the flag to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
- * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
- * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
- * @arg SDIO_FLAG_DTIMEOUT: Data timeout
- * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
- * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
- * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
- * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
- * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
- * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
- * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
- * @retval None
- */
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
- * @brief Checks whether the specified SDIO interrupt has occurred or not.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
- * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
- * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
- * @arg SDIO_IT_RXACT: Data receive in progress interrupt
- * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
- * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
- * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
- * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
- * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
- * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
- * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
- * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval The new state of SDIO_IT (SET or RESET).
- */
-#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
- * @brief Clears the SDIO's interrupt pending bits.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
- * This parameter can be one or a combination of the following values:
- * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
- * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
- * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
- * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
- * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
- * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
- * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
- * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
- * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
- * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
- * @retval None
- */
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
- * @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
-
-/**
- * @brief Disable Start the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
-
-/**
- * @brief Enable Start the SD I/O Read Wait operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
-
-/**
- * @brief Disable Stop the SD I/O Read Wait operations.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
-
-/**
- * @brief Enable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
-
-/**
- * @brief Disable the SD I/O Mode Operation.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
-
-/**
- * @brief Enable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
-
-/**
- * @brief Disable the SD I/O Suspend command sending.
- * @param __INSTANCE__ : Pointer to SDIO register base
- * @retval None
- */
-#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-/**
- * @brief Enable the command completion signal.
- * @retval None
- */
-#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
-
-/**
- * @brief Disable the command completion signal.
- * @retval None
- */
-#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
-
-/**
- * @brief Enable the CE-ATA interrupt.
- * @retval None
- */
-#define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
-
-/**
- * @brief Disable the CE-ATA interrupt.
- * @retval None
- */
-#define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
-
-/**
- * @brief Enable send CE-ATA command (CMD61).
- * @retval None
- */
-#define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
-
-/**
- * @brief Disable send CE-ATA command (CMD61).
- * @retval None
- */
-#define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
- * @{
- */
-
-/* Initialization/de-initialization functions **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
- * @{
- */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
-/**
- * @}
- */
-
-/* I/O operation functions *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
- * @{
- */
-/* Blocking mode: Polling */
-uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
-/**
- * @}
- */
-
-/* Peripheral Control functions ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
- * @{
- */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
-uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
-uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
-uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
-uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
-uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
-
-/* SDMMC Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
-
-/* SDMMC Commands management functions */
-uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
-uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
-uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
-uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
-uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
-uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
-uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
-uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
-uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
-uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
-
-uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
-uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
-uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F103xE || STM32F103xG */
-
-#endif /* __stm32f1xx_LL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_sdmmc.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_spi.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1920 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_SPI_H
-#define __STM32F1xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @defgroup SPI_LL SPI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
- * @{
- */
-
-/**
- * @brief SPI Init structures definition
- */
-typedef struct
-{
- uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
-
- uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_LL_EC_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
-
- uint32_t DataWidth; /*!< Specifies the SPI data width.
- This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
-
- uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_LL_EC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
-
- uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
-
- uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master clock. The slave clock does not need to be set.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
-
- uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
-
- This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
-
- uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_SPI_ReadReg function
- * @{
- */
-#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
-#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
-#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
-#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
-#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
-#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
-/**
- * @}
- */
-
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
-#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
- * @{
- */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
- * @{
- */
-#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
- * @{
- */
-#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
-#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
-#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
- * @{
- */
-#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
-#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
-#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
-#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
- * @{
- */
-#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable SPI peripheral
- * @rmtoll CR1 SPE LL_SPI_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Disable SPI peripheral
- * @note When disabling the SPI, follow the procedure described in the Reference Manual.
- * @rmtoll CR1 SPE LL_SPI_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Check if SPI peripheral is enabled
- * @rmtoll CR1 SPE LL_SPI_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
-}
-
-/**
- * @brief Set SPI operation mode to Master or Slave
- * @note This bit should not be changed when communication is ongoing.
- * @rmtoll CR1 MSTR LL_SPI_SetMode\n
- * CR1 SSI LL_SPI_SetMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
- * @brief Get SPI operation mode (Master or Slave)
- * @rmtoll CR1 MSTR LL_SPI_GetMode\n
- * CR1 SSI LL_SPI_GetMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-
-/**
- * @brief Set clock phase
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
- * @param SPIx SPI Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
- * @brief Get clock phase
- * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
- * @brief Set clock polarity
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Get clock polarity
- * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
- * @brief Set baud rate prescaler
- * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
- * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @param BaudRate This parameter can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
- * @brief Get baud rate prescaler
- * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
- * @brief Set transfer bit order
- * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
- * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
- * @param SPIx SPI Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
- * @brief Get transfer bit order
- * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
- * @brief Set transfer direction mode
- * @note For Half-Duplex mode, Rx Direction is set by default.
- * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
- * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
- * CR1 BIDIOE LL_SPI_SetTransferDirection
- * @param SPIx SPI Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
-}
-
-/**
- * @brief Get transfer direction mode
- * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
- * CR1 BIDIOE LL_SPI_GetTransferDirection
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
- * @brief Set frame data width
- * @rmtoll CR1 DFF LL_SPI_SetDataWidth
- * @param SPIx SPI Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
-}
-
-/**
- * @brief Get frame data width
- * @rmtoll CR1 DFF LL_SPI_GetDataWidth
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
- * @{
- */
-
-/**
- * @brief Enable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Disable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Check if CRC is enabled
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
-}
-
-/**
- * @brief Set CRCNext to transfer CRC on the line
- * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
- * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
- * @brief Set polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
- * @param SPIx SPI Instance
- * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
-{
- WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
- * @brief Get polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
- * @brief Get Rx CRC
- * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
- * @brief Get Tx CRC
- * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
- * @{
- */
-
-/**
- * @brief Set NSS mode
- * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
- * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
- * @param SPIx SPI Instance
- * @param NSS This parameter can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
- MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
- * @brief Get NSS mode
- * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
-{
- register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
- register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
- return (Ssm | Ssoe);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
-}
-
-/**
- * @brief Get CRC error flag
- * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
-}
-
-/**
- * @brief Get mode fault error flag
- * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
-}
-
-/**
- * @brief Get busy flag
- * @note The BSY flag is cleared under any one of the following conditions:
- * -When the SPI is correctly disabled
- * -When a fault is detected in Master mode (MODF bit set to 1)
- * -In Master mode, when it finishes a data transmission and no new data is ready to be
- * sent
- * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
- * each data transfer.
- * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
-}
-
-
-/**
- * @brief Clear CRC error flag
- * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
- * @brief Clear mode fault error flag
- * @note Clearing this flag is done by a read access to the SPIx_SR
- * register followed by a write access to the SPIx_CR1 register
- * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
- tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
- (void) tmpreg;
-}
-
-/**
- * @brief Clear overrun error flag
- * @note Clearing this flag is done by a read access to the SPIx_DR
- * register followed by a read access to the SPIx_SR register
- * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->DR;
- (void) tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Enable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Enable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Disable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Disable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Disable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Check if error interrupt is enabled
- * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
-}
-
-/**
- * @brief Check if Rx buffer not empty interrupt is enabled
- * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
-}
-
-/**
- * @brief Check if Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
- * @param SPIx SPI Instance
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
-{
- return (uint32_t) & (SPIx->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
- * @{
- */
-
-/**
- * @brief Read 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData8
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
-{
- return (uint8_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Read 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Write 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData8
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
-{
- SPIx->DR = TxData;
-}
-
-/**
- * @brief Write 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
- SPIx->DR = TxData;
-}
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup I2S_LL I2S
- * @{
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_LL_EC_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
-
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
-
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
-
- This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
-
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
-
- Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
- and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
-
-
- uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_LL_EC_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
- * @{
- */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2S_ReadReg function
- * @{
- */
-#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
-#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
-#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
-#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
- * @{
- */
-#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
-#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
- * @{
- */
-#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
-#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
-#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
-#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
-#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
-#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
- * @{
- */
-#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
-#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
- * @{
- */
-#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
- * @{
- */
-
-#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
-#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
-#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
-#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
-#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
-#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
-#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
-#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
-#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
-#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Select I2S mode and Enable I2S peripheral
- * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
- * I2SCFGR I2SE LL_I2S_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Disable I2S peripheral
- * @rmtoll I2SCFGR I2SE LL_I2S_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Check if I2S peripheral is enabled
- * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
-}
-
-/**
- * @brief Set I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_SetDataFormat
- * @param SPIx SPI Instance
- * @param DataFormat This parameter can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
- * @brief Get I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_GetDataFormat
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
- * @brief Set I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
- * @brief Get I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
- * @brief Set I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
- * @brief Get I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
- * @brief Set I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
- * @brief Get I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
- * @brief Set I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
- * @param SPIx SPI Instance
- * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
- * @brief Get I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
- * @param SPIx SPI Instance
- * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
- * @brief Set I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
- * @param SPIx SPI Instance
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
- * @brief Get I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
- * @brief Enable the master clock ouput (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Disable the master clock ouput (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Check if the master clock ouput (Pin MCK) is enabled
- * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
- * @brief Get busy flag
- * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
- * @brief Get underrun error flag
- * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
-}
-
-/**
- * @brief Get channel side flag.
- * @note 0: Channel Left has to be transmitted or has been received\n
- * 1: Channel Right has to be transmitted or has been received\n
- * It has no significance in PCM mode.
- * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
-}
-
-/**
- * @brief Clear overrun error flag
- * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
- * @brief Clear underrun error flag
- * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void)tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
- * @brief Enable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Enable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
- * @brief Disable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
- * @brief Disable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Disable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
- * @brief Check if ERR IT is enabled
- * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
- * @brief Check if RXNE IT is enabled
- * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
- * @brief Check if TXE IT is enabled
- * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
- * @{
- */
-
-/**
- * @brief Read 16-Bits in data register
- * @rmtoll DR DR LL_I2S_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
- * @brief Write 16-Bits in data register
- * @rmtoll DR DR LL_I2S_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
- LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_spi.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_system.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,590 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_system.h
- * @author MCD Application Team
- * @brief Header file of SYSTEM LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL SYSTEM driver contains a set of generic APIs that can be
- used by user:
- (+) Some of the FLASH features need to be handled in the SYSTEM file.
- (+) Access to DBGCMU registers
- (+) Access to SYSCFG registers
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_SYSTEM_H
-#define __STM32F1xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (FLASH) || defined (DBGMCU)
-
-/** @defgroup SYSTEM_LL SYSTEM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
- * @{
- */
-
-
-
-/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
- * @{
- */
-#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
-#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
-#if defined(DBGMCU_CR_DBG_TIM5_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM5_STOP */
-#if defined(DBGMCU_CR_DBG_TIM6_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM6_STOP */
-#if defined(DBGMCU_CR_DBG_TIM7_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM7_STOP */
-#if defined(DBGMCU_CR_DBG_TIM12_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM12_STOP */
-#if defined(DBGMCU_CR_DBG_TIM13_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM13_STOP */
-#if defined(DBGMCU_CR_DBG_TIM14_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM14_STOP */
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
-#if defined(DBGMCU_CR_DBG_CAN1_STOP)
-#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
-#endif /* DBGMCU_CR_DBG_CAN1_STOP */
-#if defined(DBGMCU_CR_DBG_CAN2_STOP)
-#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
-#endif /* DBGMCU_CR_DBG_CAN2_STOP */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
-#if defined(DBGMCU_CR_DBG_TIM8_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_CAN1_STOP */
-#if defined(DBGMCU_CR_DBG_TIM9_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM9_STOP */
-#if defined(DBGMCU_CR_DBG_TIM10_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM10_STOP */
-#if defined(DBGMCU_CR_DBG_TIM11_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM11_STOP */
-#if defined(DBGMCU_CR_DBG_TIM15_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM15_STOP */
-#if defined(DBGMCU_CR_DBG_TIM16_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM16_STOP */
-#if defined(DBGMCU_CR_DBG_TIM17_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM17_STOP */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
- * @{
- */
-#if defined(FLASH_ACR_LATENCY)
-#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
-#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
-#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
-#else
-#endif /* FLASH_ACR_LATENCY */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
- * @{
- */
-
-
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
- * @{
- */
-
-/**
- * @brief Return the device identifier
- * @note For Low Density devices, the device ID is 0x412
- * @note For Medium Density devices, the device ID is 0x410
- * @note For High Density devices, the device ID is 0x414
- * @note For XL Density devices, the device ID is 0x430
- * @note For Connectivity Line devices, the device ID is 0x418
- * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
- * @brief Return the device revision identifier
- * @note This field indicates the revision of the device.
- For example, it is read as revA -> 0x1000,for Low Density devices
- For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
- For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
- For example, it is read as revA or 1 -> 0x1003,for XL Density devices
- For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
- * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Set Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
- * @param PinAssignment This parameter can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
-{
- MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
-}
-
-/**
- * @brief Get Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
-}
-
-/**
- * @brief Freeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->CR, Periphs);
-}
-
-/**
- * @brief Unfreeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->CR, Periphs);
-}
-
-/**
- * @brief Freeze APB2 peripherals
- * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->CR, Periphs);
-}
-
-/**
- * @brief Unfreeze APB2 peripherals
- * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->CR, Periphs);
-}
-/**
- * @}
- */
-
-#if defined(FLASH_ACR_LATENCY)
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
- * @{
- */
-
-/**
- * @brief Set FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
- * @param Latency This parameter can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
- * @brief Get FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
- return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
- * @brief Enable Prefetch
- * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
-}
-
-/**
- * @brief Disable Prefetch
- * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
-}
-
-/**
- * @brief Check if Prefetch buffer is enabled
- * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
- return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
-}
-
-#endif /* FLASH_ACR_LATENCY */
-/**
- * @brief Enable Flash Half Cycle Access
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
-}
-
-/**
- * @brief Disable Flash Half Cycle Access
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
-}
-
-/**
- * @brief Check if Flash Half Cycle Access is enabled or not
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
-{
- return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (FLASH) || defined (DBGMCU) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_tim.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,3835 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_TIM_H
-#define __STM32F1xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
-
-/** @defgroup TIM_LL TIM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
- * @{
- */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
- 0x00U, /* 0: TIMx_CH1 */
- 0x00U, /* 1: TIMx_CH1N */
- 0x00U, /* 2: TIMx_CH2 */
- 0x00U, /* 3: TIMx_CH2N */
- 0x04U, /* 4: TIMx_CH3 */
- 0x04U, /* 5: TIMx_CH3N */
- 0x04U /* 6: TIMx_CH4 */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
- 0U, /* 0: OC1M, OC1FE, OC1PE */
- 0U, /* 1: - NA */
- 8U, /* 2: OC2M, OC2FE, OC2PE */
- 0U, /* 3: - NA */
- 0U, /* 4: OC3M, OC3FE, OC3PE */
- 0U, /* 5: - NA */
- 8U /* 6: OC4M, OC4FE, OC4PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
- 0U, /* 0: CC1S, IC1PSC, IC1F */
- 0U, /* 1: - NA */
- 8U, /* 2: CC2S, IC2PSC, IC2F */
- 0U, /* 3: - NA */
- 0U, /* 4: CC3S, IC3PSC, IC3F */
- 0U, /* 5: - NA */
- 8U /* 6: CC4S, IC4PSC, IC4F */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
- 0U, /* 0: CC1P */
- 2U, /* 1: CC1NP */
- 4U, /* 2: CC2P */
- 6U, /* 3: CC2NP */
- 8U, /* 4: CC3P */
- 10U, /* 5: CC3NP */
- 12U /* 6: CC4P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] =
-{
- 0U, /* 0: OIS1 */
- 1U, /* 1: OIS1N */
- 2U, /* 2: OIS2 */
- 3U, /* 3: OIS2N */
- 4U, /* 4: OIS3 */
- 5U, /* 5: OIS3N */
- 6U /* 6: OIS4 */
-};
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
- * @{
- */
-
-
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7F)
-#define DT_DELAY_2 ((uint8_t)0x3F)
-#define DT_DELAY_3 ((uint8_t)0x1F)
-#define DT_DELAY_4 ((uint8_t)0x1F)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00)
-#define DT_RANGE_2 ((uint8_t)0x80)
-#define DT_RANGE_3 ((uint8_t)0xC0)
-#define DT_RANGE_4 ((uint8_t)0xE0)
-
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
- * @{
- */
-/** @brief Convert channel id into channel index.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval none
- */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
-
-/** @brief Calculate the deadtime sampling period(in ps).
- * @param __TIMCLK__ timer input clock frequency (in Hz).
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval none
- */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
- * @{
- */
-
-/**
- * @brief TIM Time Base configuration structure definition.
- */
-typedef struct
-{
- uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
-
- uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
-
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
- * @brief TIM Output Compare configuration structure definition.
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the output mode.
- This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
-
- uint32_t OCState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM Input Capture configuration structure definition.
- */
-
-typedef struct
-{
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t ICActiveInput; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
- * @brief TIM Encoder interface configuration structure definition.
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
- This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
- * @brief TIM Hall sensor interface configuration structure definition.
- */
-typedef struct
-{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- Prescaler must be set to get a maximum counter period longer than the
- time interval between 2 consecutive changes on the Hall inputs.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
- A positive pulse (TRGO event) is generated with a programmable delay every time
- a change occurs on the Hall inputs.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
- * @brief BDTR (Break and Dead Time) structure definition
- */
-typedef struct
-{
- uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_LL_EC_OSSR
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
-
- uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OSSI
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
-
- uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
- @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
- has been written, their content is frozen until the next reset.*/
-
- uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
-
- @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
-
- uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
- uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
- uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_TIM_ReadReg function.
- * @{
- */
-#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
-#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
- * @{
- */
-#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
- * @{
- */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
- * @{
- */
-#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
- * @{
- */
-#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
- * @{
- */
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
- * @{
- */
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
- * @{
- */
-#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
- * @{
- */
-#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
- * @{
- */
-#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
-#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
- * @{
- */
-#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
- * @{
- */
-#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
-#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
-#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
-#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
- * @{
- */
-#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
-#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
-#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
-#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
- * @{
- */
-#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
- * @{
- */
-#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
-#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
-#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
- * @{
- */
-#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
- * @{
- */
-#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
-#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
- * @{
- */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
- * @{
- */
-#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
- * @{
- */
-#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
- * @{
- */
-#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
-#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
- * @{
- */
-#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
- * @{
- */
-#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
- * @{
- */
-#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
-#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
-#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
-#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
- * @{
- */
-#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
- * @{
- */
-#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
- * @{
- */
-#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
- * @{
- */
-#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
- * @{
- */
-#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
- * @{
- */
-#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
-#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
-/**
- * @}
- */
-
-
-
-
-/** @defgroup TIM_LL_EC_OSSI OSSI
- * @{
- */
-#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OSSR OSSR
- * @{
- */
-#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
- * @{
- */
-#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
- * @{
- */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
-/**
- * @}
- */
-
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-/**
- * @brief Write a value in TIM register.
- * @param __INSTANCE__ TIM Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in TIM register.
- * @param __INSTANCE__ TIM Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
- * @{
- */
-
-/**
- * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
- * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @param __DT__ deadtime duration (in ns)
- * @retval DTG[0:7]
- */
-#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
- 0U)
-
-/**
- * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
- * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __CNTCLK__ counter clock frequency (in Hz)
- * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
- * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __FREQ__ output signal frequency (in Hz)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
-
-/**
- * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
- * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @retval Compare value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
-((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
- / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
- * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @param __PULSE__ pulse duration (in us)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
- + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
- * @brief HELPER macro retrieving the ratio of the input capture prescaler
- * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
- * @param __ICPSC__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- * @retval Input capture prescaler ratio (1, 2, 4 or 8)
- */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
- * @{
- */
-/**
- * @brief Enable timer counter.
- * @rmtoll CR1 CEN LL_TIM_EnableCounter
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
- * @brief Disable timer counter.
- * @rmtoll CR1 CEN LL_TIM_DisableCounter
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
- * @brief Indicates whether the timer counter is enabled.
- * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
-}
-
-/**
- * @brief Enable update event generation.
- * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
- * @brief Disable update event generation.
- * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
- * @brief Indicates whether update event generation is enabled.
- * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
-}
-
-/**
- * @brief Set update event source
- * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
- * generate an update interrupt or DMA request if enabled:
- * - Counter overflow/underflow
- * - Setting the UG bit
- * - Update generation through the slave mode controller
- * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
- * overflow/underflow generates an update interrupt or DMA request if enabled.
- * @rmtoll CR1 URS LL_TIM_SetUpdateSource
- * @param TIMx Timer instance
- * @param UpdateSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
- * @brief Get actual event update source
- * @rmtoll CR1 URS LL_TIM_GetUpdateSource
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
- * @brief Set one pulse mode (one shot v.s. repetitive).
- * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
- * @param TIMx Timer instance
- * @param OnePulseMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
- * @brief Get actual one pulse mode.
- * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
- * @brief Set the timer counter counting mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- * check whether or not the counter mode selection feature is supported
- * by a timer instance.
- * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
- * CR1 CMS LL_TIM_SetCounterMode
- * @param TIMx Timer instance
- * @param CounterMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_COUNTERMODE_UP
- * @arg @ref LL_TIM_COUNTERMODE_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
-}
-
-/**
- * @brief Get actual counter mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- * check whether or not the counter mode selection feature is supported
- * by a timer instance.
- * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
- * CR1 CMS LL_TIM_GetCounterMode
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_COUNTERMODE_UP
- * @arg @ref LL_TIM_COUNTERMODE_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
-}
-
-/**
- * @brief Enable auto-reload (ARR) preload.
- * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
- * @brief Disable auto-reload (ARR) preload.
- * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
- * @brief Indicates whether auto-reload (ARR) preload is enabled.
- * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
-}
-
-/**
- * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- * whether or not the clock division feature is supported by the timer
- * instance.
- * @rmtoll CR1 CKD LL_TIM_SetClockDivision
- * @param TIMx Timer instance
- * @param ClockDivision This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
- * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- * whether or not the clock division feature is supported by the timer
- * instance.
- * @rmtoll CR1 CKD LL_TIM_GetClockDivision
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
- * @brief Set the counter value.
- * @rmtoll CNT CNT LL_TIM_SetCounter
- * @param TIMx Timer instance
- * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
-{
- WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
- * @brief Get the counter value.
- * @rmtoll CNT CNT LL_TIM_GetCounter
- * @param TIMx Timer instance
- * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
- */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
- * @brief Get the current direction of the counter
- * @rmtoll CR1 DIR LL_TIM_GetDirection
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_COUNTERDIRECTION_UP
- * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
- */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
- * @brief Set the prescaler value.
- * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
- * @note The prescaler can be changed on the fly as this control register is buffered. The new
- * prescaler ratio is taken into account at the next update event.
- * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
- * @rmtoll PSC PSC LL_TIM_SetPrescaler
- * @param TIMx Timer instance
- * @param Prescaler between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
-{
- WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
- * @brief Get the prescaler value.
- * @rmtoll PSC PSC LL_TIM_GetPrescaler
- * @param TIMx Timer instance
- * @retval Prescaler value between Min_Data=0 and Max_Data=65535
- */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
- * @brief Set the auto-reload value.
- * @note The counter is blocked while the auto-reload value is null.
- * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
- * @rmtoll ARR ARR LL_TIM_SetAutoReload
- * @param TIMx Timer instance
- * @param AutoReload between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
-{
- WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
- * @brief Get the auto-reload value.
- * @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @param TIMx Timer instance
- * @retval Auto-reload value
- */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
- * @brief Set the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a repetition counter.
- * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
- * @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
-{
- WRITE_REG(TIMx->RCR, RepetitionCounter);
-}
-
-/**
- * @brief Get the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a repetition counter.
- * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
- * @param TIMx Timer instance
- * @retval Repetition counter value
- */
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->RCR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
- * @{
- */
-/**
- * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
- * they are updated only when a commutation event (COM) occurs.
- * @note Only on channels that have a complementary output.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation event.
- * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
- * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation event.
- * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
- * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation event.
- * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
- * @param TIMx Timer instance
- * @param CCUpdateSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
- * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
-{
- MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
-}
-
-/**
- * @brief Set the trigger of the capture/compare DMA request.
- * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
- * @param TIMx Timer instance
- * @param DMAReqTrigger This parameter can be one of the following values:
- * @arg @ref LL_TIM_CCDMAREQUEST_CC
- * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
-{
- MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
- * @brief Get actual trigger of the capture/compare DMA request.
- * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_CCDMAREQUEST_CC
- * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
- * @brief Set the lock level to freeze the
- * configuration of several capture/compare parameters.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * the lock mechanism is supported by a timer instance.
- * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
- * @param TIMx Timer instance
- * @param LockLevel This parameter can be one of the following values:
- * @arg @ref LL_TIM_LOCKLEVEL_OFF
- * @arg @ref LL_TIM_LOCKLEVEL_1
- * @arg @ref LL_TIM_LOCKLEVEL_2
- * @arg @ref LL_TIM_LOCKLEVEL_3
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
-}
-
-/**
- * @brief Enable capture/compare channels.
- * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
- * CCER CC1NE LL_TIM_CC_EnableChannel\n
- * CCER CC2E LL_TIM_CC_EnableChannel\n
- * CCER CC2NE LL_TIM_CC_EnableChannel\n
- * CCER CC3E LL_TIM_CC_EnableChannel\n
- * CCER CC3NE LL_TIM_CC_EnableChannel\n
- * CCER CC4E LL_TIM_CC_EnableChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
- SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
- * @brief Disable capture/compare channels.
- * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
- * CCER CC1NE LL_TIM_CC_DisableChannel\n
- * CCER CC2E LL_TIM_CC_DisableChannel\n
- * CCER CC2NE LL_TIM_CC_DisableChannel\n
- * CCER CC3E LL_TIM_CC_DisableChannel\n
- * CCER CC3NE LL_TIM_CC_DisableChannel\n
- * CCER CC4E LL_TIM_CC_DisableChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
- CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
- * @brief Indicate whether channel(s) is(are) enabled.
- * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC4E LL_TIM_CC_IsEnabledChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
- return (READ_BIT(TIMx->CCER, Channels) == (Channels));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
- * @{
- */
-/**
- * @brief Configure an output channel.
- * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
- * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
- * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
- * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
- * CCER CC1P LL_TIM_OC_ConfigOutput\n
- * CCER CC2P LL_TIM_OC_ConfigOutput\n
- * CCER CC3P LL_TIM_OC_ConfigOutput\n
- * CCER CC4P LL_TIM_OC_ConfigOutput\n
- * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS4 LL_TIM_OC_ConfigOutput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
- MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
- (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
- MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
- (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Define the behavior of the output reference signal OCxREF from which
- * OCx and OCxN (when relevant) are derived.
- * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
- * CCMR1 OC2M LL_TIM_OC_SetMode\n
- * CCMR2 OC3M LL_TIM_OC_SetMode\n
- * CCMR2 OC4M LL_TIM_OC_SetMode
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCMODE_FROZEN
- * @arg @ref LL_TIM_OCMODE_ACTIVE
- * @arg @ref LL_TIM_OCMODE_INACTIVE
- * @arg @ref LL_TIM_OCMODE_TOGGLE
- * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- * @arg @ref LL_TIM_OCMODE_PWM1
- * @arg @ref LL_TIM_OCMODE_PWM2
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
- * @brief Get the output compare mode of an output channel.
- * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
- * CCMR1 OC2M LL_TIM_OC_GetMode\n
- * CCMR2 OC3M LL_TIM_OC_GetMode\n
- * CCMR2 OC4M LL_TIM_OC_GetMode
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCMODE_FROZEN
- * @arg @ref LL_TIM_OCMODE_ACTIVE
- * @arg @ref LL_TIM_OCMODE_INACTIVE
- * @arg @ref LL_TIM_OCMODE_TOGGLE
- * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- * @arg @ref LL_TIM_OCMODE_PWM1
- * @arg @ref LL_TIM_OCMODE_PWM2
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
- * @brief Set the polarity of an output channel.
- * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
- * CCER CC1NP LL_TIM_OC_SetPolarity\n
- * CCER CC2P LL_TIM_OC_SetPolarity\n
- * CCER CC2NP LL_TIM_OC_SetPolarity\n
- * CCER CC3P LL_TIM_OC_SetPolarity\n
- * CCER CC3NP LL_TIM_OC_SetPolarity\n
- * CCER CC4P LL_TIM_OC_SetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH
- * @arg @ref LL_TIM_OCPOLARITY_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Get the polarity of an output channel.
- * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
- * CCER CC1NP LL_TIM_OC_GetPolarity\n
- * CCER CC2P LL_TIM_OC_GetPolarity\n
- * CCER CC2NP LL_TIM_OC_GetPolarity\n
- * CCER CC3P LL_TIM_OC_GetPolarity\n
- * CCER CC3NP LL_TIM_OC_GetPolarity\n
- * CCER CC4P LL_TIM_OC_GetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH
- * @arg @ref LL_TIM_OCPOLARITY_LOW
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Set the IDLE state of an output channel
- * @note This function is significant only for the timer instances
- * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
- * can be used to check whether or not a timer instance provides
- * a break input.
- * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
- * CR2 OIS1N LL_TIM_OC_SetIdleState\n
- * CR2 OIS2 LL_TIM_OC_SetIdleState\n
- * CR2 OIS2N LL_TIM_OC_SetIdleState\n
- * CR2 OIS3 LL_TIM_OC_SetIdleState\n
- * CR2 OIS3N LL_TIM_OC_SetIdleState\n
- * CR2 OIS4 LL_TIM_OC_SetIdleState
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param IdleState This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCIDLESTATE_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Get the IDLE state of an output channel
- * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
- * CR2 OIS1N LL_TIM_OC_GetIdleState\n
- * CR2 OIS2 LL_TIM_OC_GetIdleState\n
- * CR2 OIS2N LL_TIM_OC_GetIdleState\n
- * CR2 OIS3 LL_TIM_OC_GetIdleState\n
- * CR2 OIS3N LL_TIM_OC_GetIdleState\n
- * CR2 OIS4 LL_TIM_OC_GetIdleState
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCIDLESTATE_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Enable fast mode for the output channel.
- * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
- * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
- * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
- * CCMR2 OC4FE LL_TIM_OC_EnableFast
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
- * @brief Disable fast mode for the output channel.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
- * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
- * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
- * CCMR2 OC4FE LL_TIM_OC_DisableFast
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
- * @brief Indicates whether fast mode is enabled for the output channel.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
- * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
- * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
- * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
-}
-
-/**
- * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
- * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
- * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
- * CCMR2 OC4PE LL_TIM_OC_EnablePreload
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
- * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
- * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
- * CCMR2 OC4PE LL_TIM_OC_DisablePreload
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
-}
-
-/**
- * @brief Enable clearing the output channel on an external event.
- * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
- * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
- * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
- * CCMR2 OC4CE LL_TIM_OC_EnableClear
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Disable clearing the output channel on an external event.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
- * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
- * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
- * CCMR2 OC4CE LL_TIM_OC_DisableClear
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
- * @note This function enables clearing the output channel on an external event.
- * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
- * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
- * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
- * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
-}
-
-/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * dead-time insertion feature is supported by a timer instance.
- * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
- * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
- * @param TIMx Timer instance
- * @param DeadTime between Min_Data=0 and Max_Data=255
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
-}
-
-/**
- * @brief Set compare value for output channel 1 (TIMx_CCR1).
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * output channel 1 is supported by a timer instance.
- * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 2 (TIMx_CCR2).
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * output channel 2 is supported by a timer instance.
- * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 3 (TIMx_CCR3).
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * output channel is supported by a timer instance.
- * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 4 (TIMx_CCR4).
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * output channel 4 is supported by a timer instance.
- * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
- * @brief Get compare value (TIMx_CCR1) set for output channel 1.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * output channel 1 is supported by a timer instance.
- * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR2) set for output channel 2.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * output channel 2 is supported by a timer instance.
- * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR3) set for output channel 3.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * output channel 3 is supported by a timer instance.
- * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR4) set for output channel 4.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * output channel 4 is supported by a timer instance.
- * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
- * @{
- */
-/**
- * @brief Configure input channel.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
- * CCMR1 IC1PSC LL_TIM_IC_Config\n
- * CCMR1 IC1F LL_TIM_IC_Config\n
- * CCMR1 CC2S LL_TIM_IC_Config\n
- * CCMR1 IC2PSC LL_TIM_IC_Config\n
- * CCMR1 IC2F LL_TIM_IC_Config\n
- * CCMR2 CC3S LL_TIM_IC_Config\n
- * CCMR2 IC3PSC LL_TIM_IC_Config\n
- * CCMR2 IC3F LL_TIM_IC_Config\n
- * CCMR2 CC4S LL_TIM_IC_Config\n
- * CCMR2 IC4PSC LL_TIM_IC_Config\n
- * CCMR2 IC4F LL_TIM_IC_Config\n
- * CCER CC1P LL_TIM_IC_Config\n
- * CCER CC1NP LL_TIM_IC_Config\n
- * CCER CC2P LL_TIM_IC_Config\n
- * CCER CC2NP LL_TIM_IC_Config\n
- * CCER CC3P LL_TIM_IC_Config\n
- * CCER CC3NP LL_TIM_IC_Config\n
- * CCER CC4P LL_TIM_IC_Config\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
- * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
- * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
- * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
- ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
- MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Set the active input.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
- * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
- * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
- * CCMR2 CC4S LL_TIM_IC_SetActiveInput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICActiveInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the current active input.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
- * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
- * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
- * CCMR2 CC4S LL_TIM_IC_GetActiveInput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
- * @brief Set the prescaler of input channel.
- * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
- * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
- * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
- * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICPrescaler This parameter can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the current prescaler value acting on an input channel.
- * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
- * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
- * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
- * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
- * @brief Set the input filter duration.
- * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
- * CCMR1 IC2F LL_TIM_IC_SetFilter\n
- * CCMR2 IC3F LL_TIM_IC_SetFilter\n
- * CCMR2 IC4F LL_TIM_IC_SetFilter
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICFilter This parameter can be one of the following values:
- * @arg @ref LL_TIM_IC_FILTER_FDIV1
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the input filter duration.
- * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
- * CCMR1 IC2F LL_TIM_IC_GetFilter\n
- * CCMR2 IC3F LL_TIM_IC_GetFilter\n
- * CCMR2 IC4F LL_TIM_IC_GetFilter
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_IC_FILTER_FDIV1
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
- * @brief Set the input channel polarity.
- * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
- * CCER CC1NP LL_TIM_IC_SetPolarity\n
- * CCER CC2P LL_TIM_IC_SetPolarity\n
- * CCER CC2NP LL_TIM_IC_SetPolarity\n
- * CCER CC3P LL_TIM_IC_SetPolarity\n
- * CCER CC3NP LL_TIM_IC_SetPolarity\n
- * CCER CC4P LL_TIM_IC_SetPolarity\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_IC_POLARITY_RISING
- * @arg @ref LL_TIM_IC_POLARITY_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Get the current input channel polarity.
- * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
- * CCER CC1NP LL_TIM_IC_GetPolarity\n
- * CCER CC2P LL_TIM_IC_GetPolarity\n
- * CCER CC2NP LL_TIM_IC_GetPolarity\n
- * CCER CC3P LL_TIM_IC_GetPolarity\n
- * CCER CC3NP LL_TIM_IC_GetPolarity\n
- * CCER CC4P LL_TIM_IC_GetPolarity\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_IC_POLARITY_RISING
- * @arg @ref LL_TIM_IC_POLARITY_FALLING
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
- SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
- * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
- * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
-}
-
-/**
- * @brief Get captured value for input channel 1.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * input channel 1 is supported by a timer instance.
- * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
- * @brief Get captured value for input channel 2.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * input channel 2 is supported by a timer instance.
- * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
- * @brief Get captured value for input channel 3.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * input channel 3 is supported by a timer instance.
- * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
- * @brief Get captured value for input channel 4.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * input channel 4 is supported by a timer instance.
- * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
- * @{
- */
-/**
- * @brief Enable external clock mode 2.
- * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
- * @brief Disable external clock mode 2.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
- * @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
-}
-
-/**
- * @brief Set the clock source of the counter clock.
- * @note when selected clock source is external clock mode 1, the timer input
- * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
- * function. This timer input must be configured by calling
- * the @ref LL_TIM_IC_Config() function.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode1.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
- * SMCR ECE LL_TIM_SetClockSource
- * @param TIMx Timer instance
- * @param ClockSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
- * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
- * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
- * @brief Set the encoder interface mode.
- * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the encoder mode.
- * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
- * @param TIMx Timer instance
- * @param EncoderMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
- * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
- * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
- * @{
- */
-/**
- * @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance can operate as a master timer.
- * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
- * @param TIMx Timer instance
- * @param TimerSynchronization This parameter can be one of the following values:
- * @arg @ref LL_TIM_TRGO_RESET
- * @arg @ref LL_TIM_TRGO_ENABLE
- * @arg @ref LL_TIM_TRGO_UPDATE
- * @arg @ref LL_TIM_TRGO_CC1IF
- * @arg @ref LL_TIM_TRGO_OC1REF
- * @arg @ref LL_TIM_TRGO_OC2REF
- * @arg @ref LL_TIM_TRGO_OC3REF
- * @arg @ref LL_TIM_TRGO_OC4REF
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
-{
- MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
- * @brief Set the synchronization mode of a slave timer.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
- * @param TIMx Timer instance
- * @param SlaveMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_SLAVEMODE_DISABLED
- * @arg @ref LL_TIM_SLAVEMODE_RESET
- * @arg @ref LL_TIM_SLAVEMODE_GATED
- * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
- * @brief Set the selects the trigger input to be used to synchronize the counter.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR TS LL_TIM_SetTriggerInput
- * @param TIMx Timer instance
- * @param TriggerInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_TS_ITR0
- * @arg @ref LL_TIM_TS_ITR1
- * @arg @ref LL_TIM_TS_ITR2
- * @arg @ref LL_TIM_TS_ITR3
- * @arg @ref LL_TIM_TS_TI1F_ED
- * @arg @ref LL_TIM_TS_TI1FP1
- * @arg @ref LL_TIM_TS_TI2FP2
- * @arg @ref LL_TIM_TS_ETRF
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
- * @brief Enable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
- * @brief Disable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
- * @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
-}
-
-/**
- * @brief Configure the external trigger (ETR) input.
- * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an external trigger input.
- * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
- * SMCR ETPS LL_TIM_ConfigETR\n
- * SMCR ETF LL_TIM_ConfigETR
- * @param TIMx Timer instance
- * @param ETRPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
- * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
- * @param ETRPrescaler This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
- * @param ETRFilter This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
- uint32_t ETRFilter)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Break_Function Break function configuration
- * @{
- */
-/**
- * @brief Enable the break function.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR BKE LL_TIM_EnableBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
- * @brief Disable the break function.
- * @rmtoll BDTR BKE LL_TIM_DisableBRK
- * @param TIMx Timer instance
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
- * @brief Configure the break input.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR BKP LL_TIM_ConfigBRK
- * @param TIMx Timer instance
- * @param BreakPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_POLARITY_LOW
- * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
-}
-
-/**
- * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
- * BDTR OSSR LL_TIM_SetOffStates
- * @param TIMx Timer instance
- * @param OffStateIdle This parameter can be one of the following values:
- * @arg @ref LL_TIM_OSSI_DISABLE
- * @arg @ref LL_TIM_OSSI_ENABLE
- * @param OffStateRun This parameter can be one of the following values:
- * @arg @ref LL_TIM_OSSR_DISABLE
- * @arg @ref LL_TIM_OSSR_ENABLE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
-}
-
-/**
- * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
- * @brief Disable automatic output (MOE can be set only by software).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
- * @brief Indicate whether automatic output is enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
-}
-
-/**
- * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
- * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
- * software and is reset in case of break or break2 event
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
- * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
- * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
- * software and is reset in case of break or break2 event.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
- * @brief Indicates whether outputs are enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
- * @{
- */
-/**
- * @brief Configures the timer DMA burst feature.
- * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance supports the DMA burst mode.
- * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
- * DCR DBA LL_TIM_ConfigDMABurst
- * @param TIMx Timer instance
- * @param DMABurstBaseAddress This parameter can be one of the following values:
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
- * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
- * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
- * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
- * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
- * @param DMABurstLength This parameter can be one of the following values:
- * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
- * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
-{
- MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
- * @{
- */
-/**
- * @brief Clear the update interrupt flag (UIF).
- * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
- * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
- * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
-}
-
-/**
- * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
- * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
- * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
-}
-
-/**
- * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
- * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
- * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
-}
-
-/**
- * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
- * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
- * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
-}
-
-/**
- * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
- * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
- * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
-}
-
-/**
- * @brief Clear the commutation interrupt flag (COMIF).
- * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
-}
-
-/**
- * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
- * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
-}
-
-/**
- * @brief Clear the trigger interrupt flag (TIF).
- * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
- * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
- * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
-}
-
-/**
- * @brief Clear the break interrupt flag (BIF).
- * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
-}
-
-/**
- * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
- * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
-}
-
-/**
- * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
- * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
- * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
-}
-
-/**
- * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
- * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
- * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
-}
-
-/**
- * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
- * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
- * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
-}
-
-/**
- * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
- * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
- * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
- * @{
- */
-/**
- * @brief Enable update interrupt (UIE).
- * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
- * @brief Disable update interrupt (UIE).
- * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
- * @brief Indicates whether the update interrupt (UIE) is enabled.
- * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
-}
-
-/**
- * @brief Enable capture/compare 1 interrupt (CC1IE).
- * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
- * @brief Disable capture/compare 1 interrupt (CC1IE).
- * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
- * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
-}
-
-/**
- * @brief Enable capture/compare 2 interrupt (CC2IE).
- * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
- * @brief Disable capture/compare 2 interrupt (CC2IE).
- * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
- * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
-}
-
-/**
- * @brief Enable capture/compare 3 interrupt (CC3IE).
- * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
- * @brief Disable capture/compare 3 interrupt (CC3IE).
- * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
- * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
-}
-
-/**
- * @brief Enable capture/compare 4 interrupt (CC4IE).
- * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
- * @brief Disable capture/compare 4 interrupt (CC4IE).
- * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
- * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
-}
-
-/**
- * @brief Enable commutation interrupt (COMIE).
- * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
- * @brief Disable commutation interrupt (COMIE).
- * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
- * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
- * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
-}
-
-/**
- * @brief Enable trigger interrupt (TIE).
- * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
- * @brief Disable trigger interrupt (TIE).
- * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
- * @brief Indicates whether the trigger interrupt (TIE) is enabled.
- * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
-}
-
-/**
- * @brief Enable break interrupt (BIE).
- * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
- * @brief Disable break interrupt (BIE).
- * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
- * @brief Indicates whether the break interrupt (BIE) is enabled.
- * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
- * @{
- */
-/**
- * @brief Enable update DMA request (UDE).
- * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
- * @brief Disable update DMA request (UDE).
- * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
- * @brief Indicates whether the update DMA request (UDE) is enabled.
- * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
-}
-
-/**
- * @brief Enable capture/compare 1 DMA request (CC1DE).
- * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
- * @brief Disable capture/compare 1 DMA request (CC1DE).
- * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
- * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
-}
-
-/**
- * @brief Enable capture/compare 2 DMA request (CC2DE).
- * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
- * @brief Disable capture/compare 2 DMA request (CC2DE).
- * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
- * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
-}
-
-/**
- * @brief Enable capture/compare 3 DMA request (CC3DE).
- * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
- * @brief Disable capture/compare 3 DMA request (CC3DE).
- * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
- * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
-}
-
-/**
- * @brief Enable capture/compare 4 DMA request (CC4DE).
- * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
- * @brief Disable capture/compare 4 DMA request (CC4DE).
- * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
- * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
-}
-
-/**
- * @brief Enable commutation DMA request (COMDE).
- * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
- * @brief Disable commutation DMA request (COMDE).
- * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
- * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
- * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
-}
-
-/**
- * @brief Enable trigger interrupt (TDE).
- * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
- * @brief Disable trigger interrupt (TDE).
- * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
- * @brief Indicates whether the trigger interrupt (TDE) is enabled.
- * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
- * @{
- */
-/**
- * @brief Generate an update event.
- * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
- * @brief Generate Capture/Compare 1 event.
- * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
- * @brief Generate Capture/Compare 2 event.
- * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
- * @brief Generate Capture/Compare 3 event.
- * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
- * @brief Generate Capture/Compare 4 event.
- * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
- * @brief Generate commutation event.
- * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_COMG);
-}
-
-/**
- * @brief Generate trigger event.
- * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
- * @brief Generate break event.
- * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_BG);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
- * @{
- */
-
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_tim.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_usart.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,2587 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_usart.h
- * @author MCD Application Team
- * @brief Header file of USART LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_USART_H
-#define __STM32F1xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
-
-/** @defgroup USART_LL USART
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
- * @{
- */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
- * @{
- */
-
-/**
- * @brief LL USART Init Structure definition
- */
-typedef struct
-{
- uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
-
- uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
-
- uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
-
- uint32_t Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_LL_EC_PARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
-
- uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
-
- uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
-
-#if defined(USART_CR1_OVER8)
- uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
- This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
- This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
-
-#endif /* USART_OverSampling_Feature */
-} LL_USART_InitTypeDef;
-
-/**
- * @brief LL USART Clock Init Structure definition
- */
-typedef struct
-{
- uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
- USART HW configuration can be modified afterwards using unitary functions
- @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
- For more details, refer to description of this function. */
-
- uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
- For more details, refer to description of this function. */
-
- uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_LL_EC_PHASE.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
- For more details, refer to description of this function. */
-
- uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
- For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
- * @{
- */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_USART_ReadReg function
- * @{
- */
-#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */
-#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */
-#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */
-#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */
-#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */
-#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */
-#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */
-#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */
-#define LL_USART_SR_LBD USART_SR_LBD /*!< LIN break detection flag */
-#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
- * @{
- */
-#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */
-#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */
-#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
-#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
- * @{
- */
-#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
- * @{
- */
-#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
- * @{
- */
-#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
- * @}
- */
-
-#if defined(USART_CR1_OVER8)
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
- * @{
- */
-#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
-/**
- * @}
- */
-
-#endif /* USART_OverSampling_Feature */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
- * @{
- */
-
-#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
- * @{
- */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
- * @{
- */
-#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
- * @{
- */
-#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
- * @{
- */
-#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
- * @{
- */
-#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
- * @{
- */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in USART register
- * @param __INSTANCE__ USART Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
- * @{
- */
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
- */
-#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__)))
-#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
- = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
- ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
- (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
-
-/**
- * @brief Compute USARTDIV value according to Peripheral Clock and
- * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
- * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
- * @param __BAUDRATE__ Baud rate value to achieve
- * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
- */
-#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__)))
-#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100)
-/* USART BRR = mantissa + overflow + fraction
- = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
- (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
- (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
- * @{
- */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
- * @{
- */
-
-/**
- * @brief USART Enable
- * @rmtoll CR1 UE LL_USART_Enable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief USART Disable (all USART prescalers and outputs are disabled)
- * @note When USART is disabled, USART prescalers and outputs are stopped immediately,
- * and current operations are discarded. The configuration of the USART is kept, but all the status
- * flags, in the USARTx_SR are set to their default values.
- * @rmtoll CR1 UE LL_USART_Disable
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
- * @brief Indicate if USART is enabled
- * @rmtoll CR1 UE LL_USART_IsEnabled
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
-}
-
-/**
- * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
- * @rmtoll CR1 RE LL_USART_EnableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Receiver Disable
- * @rmtoll CR1 RE LL_USART_DisableDirectionRx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
- * @brief Transmitter Enable
- * @rmtoll CR1 TE LL_USART_EnableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Transmitter Disable
- * @rmtoll CR1 TE LL_USART_DisableDirectionTx
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
- * @brief Configure simultaneously enabled/disabled states
- * of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_SetTransferDirection\n
- * CR1 TE LL_USART_SetTransferDirection
- * @param USARTx USART Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
- * @brief Return enabled/disabled states of Transmitter and Receiver
- * @rmtoll CR1 RE LL_USART_GetTransferDirection\n
- * CR1 TE LL_USART_GetTransferDirection
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DIRECTION_NONE
- * @arg @ref LL_USART_DIRECTION_RX
- * @arg @ref LL_USART_DIRECTION_TX
- * @arg @ref LL_USART_DIRECTION_TX_RX
- */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
- * @brief Configure Parity (enabled/disabled and parity mode if enabled).
- * @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
- * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
- * (9th or 8th bit depending on data width) and parity is checked on the received data.
- * @rmtoll CR1 PS LL_USART_SetParity\n
- * CR1 PCE LL_USART_SetParity
- * @param USARTx USART Instance
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
- * @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
- * @rmtoll CR1 PS LL_USART_GetParity\n
- * CR1 PCE LL_USART_GetParity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
- * @brief Set Receiver Wake Up method from Mute mode.
- * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
- * @param USARTx USART Instance
- * @param Method This parameter can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
- * @brief Return Receiver Wake Up method from Mute mode
- * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_WAKEUP_IDLELINE
- * @arg @ref LL_USART_WAKEUP_ADDRESSMARK
- */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
- * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M LL_USART_SetDataWidth
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
- * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
- * @rmtoll CR1 M LL_USART_GetDataWidth
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-#if defined(USART_CR1_OVER8)
-/**
- * @brief Set Oversampling to 8-bit or 16-bit mode
- * @rmtoll CR1 OVER8 LL_USART_SetOverSampling
- * @param USARTx USART Instance
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
- * @brief Return Oversampling mode
- * @rmtoll CR1 OVER8 LL_USART_GetOverSampling
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-#endif /* USART_OverSampling_Feature */
-/**
- * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
- * @param USARTx USART Instance
- * @param LastBitClockPulse This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
- * @brief Retrieve Clock pulse of the last data bit output configuration
- * (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
- * @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_SetClockPhase
- * @param USARTx USART Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
- * @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPHA LL_USART_GetClockPhase
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
- * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_SetClockPolarity
- * @param USARTx USART Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CPOL LL_USART_GetClockPolarity
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
- * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
- * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
- * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
- * @rmtoll CR2 CPHA LL_USART_ConfigClock\n
- * CR2 CPOL LL_USART_ConfigClock\n
- * CR2 LBCL LL_USART_ConfigClock
- * @param USARTx USART Instance
- * @param Phase This parameter can be one of the following values:
- * @arg @ref LL_USART_PHASE_1EDGE
- * @arg @ref LL_USART_PHASE_2EDGE
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_USART_POLARITY_LOW
- * @arg @ref LL_USART_POLARITY_HIGH
- * @param LBCPOutput This parameter can be one of the following values:
- * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
- * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
- * @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
-}
-
-/**
- * @brief Set the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_SetStopBitsLength
- * @param USARTx USART Instance
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Retrieve the length of the stop bits
- * @rmtoll CR2 STOP LL_USART_GetStopBitsLength
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
- * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
- * @note Call of this function is equivalent to following function call sequence :
- * - Data Width configuration using @ref LL_USART_SetDataWidth() function
- * - Parity Control and mode configuration using @ref LL_USART_SetParity() function
- * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
- * @rmtoll CR1 PS LL_USART_ConfigCharacter\n
- * CR1 PCE LL_USART_ConfigCharacter\n
- * CR1 M LL_USART_ConfigCharacter\n
- * CR2 STOP LL_USART_ConfigCharacter
- * @param USARTx USART Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_USART_DATAWIDTH_8B
- * @arg @ref LL_USART_DATAWIDTH_9B
- * @param Parity This parameter can be one of the following values:
- * @arg @ref LL_USART_PARITY_NONE
- * @arg @ref LL_USART_PARITY_EVEN
- * @arg @ref LL_USART_PARITY_ODD
- * @param StopBits This parameter can be one of the following values:
- * @arg @ref LL_USART_STOPBITS_0_5
- * @arg @ref LL_USART_STOPBITS_1
- * @arg @ref LL_USART_STOPBITS_1_5
- * @arg @ref LL_USART_STOPBITS_2
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
- uint32_t StopBits)
-{
- MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
- MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
- * @brief Set Address of the USART node.
- * @note This is used in multiprocessor communication during Mute mode or Stop mode,
- * for wake up with address mark detection.
- * @rmtoll CR2 ADD LL_USART_SetNodeAddress
- * @param USARTx USART Instance
- * @param NodeAddress 4 bit Address of the USART node.
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
-}
-
-/**
- * @brief Return 4 bit Address of the USART node as set in ADD field of CR2.
- * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
- * @rmtoll CR2 ADD LL_USART_GetNodeAddress
- * @param USARTx USART Instance
- * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
- */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
-}
-
-/**
- * @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
- * @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
- * @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
- * CR3 CTSE LL_USART_SetHWFlowCtrl
- * @param USARTx USART Instance
- * @param HardwareFlowControl This parameter can be one of the following values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
- * @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
- * CR3 CTSE LL_USART_GetHWFlowCtrl
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_HWCONTROL_NONE
- * @arg @ref LL_USART_HWCONTROL_RTS
- * @arg @ref LL_USART_HWCONTROL_CTS
- * @arg @ref LL_USART_HWCONTROL_RTS_CTS
- */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-#if defined(USART_CR3_ONEBIT)
-/**
- * @brief Enable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Disable One bit sampling method
- * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
- * @brief Indicate if One bit sampling method is enabled
- * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
-}
-#endif /* USART_OneBitSampling_Feature */
-
-#if defined(USART_CR1_OVER8)
-/**
- * @brief Configure USART BRR register for achieving expected Baud Rate value.
- * @note Compute and set USARTDIV value in BRR Register (full BRR content)
- * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
- * @note Peripheral clock and Baud rate values provided as function parameters should be valid
- * (Baud rate value != 0)
- * @rmtoll BRR BRR LL_USART_SetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @param BaudRate Baud Rate
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
- uint32_t BaudRate)
-{
- if (OverSampling == LL_USART_OVERSAMPLING_8)
- {
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
- }
- else
- {
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
- }
-}
-
-/**
- * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
- * (full BRR content), and to used Peripheral Clock and Oversampling mode values
- * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
- * @rmtoll BRR BRR LL_USART_GetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param OverSampling This parameter can be one of the following values:
- * @arg @ref LL_USART_OVERSAMPLING_16
- * @arg @ref LL_USART_OVERSAMPLING_8
- * @retval Baud Rate
- */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
-{
- register uint32_t usartdiv = 0x0U;
- register uint32_t brrresult = 0x0U;
-
- usartdiv = USARTx->BRR;
-
- if (OverSampling == LL_USART_OVERSAMPLING_8)
- {
- if ((usartdiv & 0xFFF7U) != 0U)
- {
- usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
- brrresult = (PeriphClk * 2U) / usartdiv;
- }
- }
- else
- {
- if ((usartdiv & 0xFFFFU) != 0U)
- {
- brrresult = PeriphClk / usartdiv;
- }
- }
- return (brrresult);
-}
-#else
-/**
- * @brief Configure USART BRR register for achieving expected Baud Rate value.
- * @note Compute and set USARTDIV value in BRR Register (full BRR content)
- * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
- * @note Peripheral clock and Baud rate values provided as function parameters should be valid
- * (Baud rate value != 0)
- * @rmtoll BRR BRR LL_USART_SetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @param BaudRate Baud Rate
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate)
-{
- USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
-}
-
-/**
- * @brief Return current Baud Rate value, according to USARTDIV present in BRR register
- * (full BRR content), and to used Peripheral Clock and Oversampling mode values
- * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
- * @rmtoll BRR BRR LL_USART_GetBaudRate
- * @param USARTx USART Instance
- * @param PeriphClk Peripheral Clock
- * @retval Baud Rate
- */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk)
-{
- register uint32_t usartdiv = 0x0U;
- register uint32_t brrresult = 0x0U;
-
- usartdiv = USARTx->BRR;
-
- if ((usartdiv & 0xFFFFU) != 0U)
- {
- brrresult = PeriphClk / usartdiv;
- }
- return (brrresult);
-}
-#endif /* USART_OverSampling_Feature */
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
- * @{
- */
-
-/**
- * @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_EnableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_DisableIrda
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IREN LL_USART_IsEnabledIrda
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
-}
-
-/**
- * @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
- * @param USARTx USART Instance
- * @param PowerMode This parameter can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_IRDA_POWER_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
- MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
- * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_IRDA_POWER_NORMAL
- * @arg @ref LL_USART_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
- * @brief Set Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
- * @brief Return Irda prescaler value, used for dividing the USART clock source
- * to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
- * @param USARTx USART Instance
- * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
- * @{
- */
-
-/**
- * @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
- * @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
-}
-
-/**
- * @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_EnableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_DisableSmartcard
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
-}
-
-/**
- * @brief Set Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
- * @param USARTx USART Instance
- * @param PrescalerValue Value between Min_Data=0 and Max_Data=31
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
- * @brief Return Smartcard prescaler value, used for dividing the USART clock
- * source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
- * @param USARTx USART Instance
- * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
- * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
- * (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
- * @param USARTx USART Instance
- * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
- MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
-}
-
-/**
- * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
- * (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
- * @param USARTx USART Instance
- * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
- */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
- * @{
- */
-
-/**
- * @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
- * @{
- */
-
-/**
- * @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @param LINBDLength This parameter can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- * @retval None
- */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
- MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
- * @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
- * @param USARTx USART Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_USART_LINBREAK_DETECT_10B
- * @arg @ref LL_USART_LINBREAK_DETECT_11B
- */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
- return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
- * @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_EnableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_DisableLIN
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
- * @{
- */
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
- * @note In UART mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Asynchronous Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
- * CR2 CLKEN LL_USART_ConfigAsyncMode\n
- * CR3 SCEN LL_USART_ConfigAsyncMode\n
- * CR3 IREN LL_USART_ConfigAsyncMode\n
- * CR3 HDSEL LL_USART_ConfigAsyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
- /* In Asynchronous mode, the following bits must be kept cleared:
- - LINEN, CLKEN bits in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Synchronous Mode
- * @note In Synchronous mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
- * Synchronous mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * @note Other remaining configurations items related to Synchronous Mode
- * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
- * CR2 CLKEN LL_USART_ConfigSyncMode\n
- * CR3 SCEN LL_USART_ConfigSyncMode\n
- * CR3 IREN LL_USART_ConfigSyncMode\n
- * CR3 HDSEL LL_USART_ConfigSyncMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
- /* In Synchronous mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
- /* set the UART/USART in Synchronous mode */
- SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in LIN Mode
- * @note In LIN mode, the following bits must be kept cleared:
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
- * @note Other remaining configurations items related to LIN Mode
- * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
- * CR2 STOP LL_USART_ConfigLINMode\n
- * CR2 LINEN LL_USART_ConfigLINMode\n
- * CR3 IREN LL_USART_ConfigLINMode\n
- * CR3 SCEN LL_USART_ConfigLINMode\n
- * CR3 HDSEL LL_USART_ConfigLINMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
- /* In LIN mode, the following bits must be kept cleared:
- - STOP and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
- /* Set the UART/USART in LIN mode */
- SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
- * @note In Half Duplex mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
- * Half-Duplex mode is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
- * @note Other remaining configurations items related to Half Duplex Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
- * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
- * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
- * CR3 IREN LL_USART_ConfigHalfDuplexMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
- /* In Half Duplex mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - SCEN and IREN bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
- /* set the UART/USART in Half Duplex mode */
- SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Smartcard Mode
- * @note In Smartcard mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also configures Stop bits to 1.5 bits and
- * sets the USART in Smartcard mode (SCEN bit).
- * Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
- * Smartcard feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
- * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
- * @note Other remaining configurations items related to Smartcard Mode
- * (as Baud Rate, Word length, Parity, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
- * CR2 STOP LL_USART_ConfigSmartcardMode\n
- * CR2 CLKEN LL_USART_ConfigSmartcardMode\n
- * CR3 HDSEL LL_USART_ConfigSmartcardMode\n
- * CR3 SCEN LL_USART_ConfigSmartcardMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
- /* In Smartcard mode, the following bits must be kept cleared:
- - LINEN bit in the USART_CR2 register,
- - IREN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
- /* Configure Stop bits to 1.5 bits */
- /* Synchronous mode is activated by default */
- SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
- /* set the UART/USART in Smartcard mode */
- SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Irda Mode
- * @note In IRDA mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - STOP and CLKEN bits in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
- * IrDA feature is supported by the USARTx instance.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
- * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
- * @note Other remaining configurations items related to Irda Mode
- * (as Baud Rate, Word length, Power mode, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
- * CR2 CLKEN LL_USART_ConfigIrdaMode\n
- * CR2 STOP LL_USART_ConfigIrdaMode\n
- * CR3 SCEN LL_USART_ConfigIrdaMode\n
- * CR3 HDSEL LL_USART_ConfigIrdaMode\n
- * CR3 IREN LL_USART_ConfigIrdaMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
- /* In IRDA mode, the following bits must be kept cleared:
- - LINEN, STOP and CLKEN bits in the USART_CR2 register,
- - SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
- /* set the UART/USART in IRDA mode */
- SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
- * @brief Perform basic configuration of USART for enabling use in Multi processor Mode
- * (several USARTs connected in a network, one of the USARTs can be the master,
- * its TX output connected to the RX inputs of the other slaves USARTs).
- * @note In MultiProcessor mode, the following bits must be kept cleared:
- * - LINEN bit in the USART_CR2 register,
- * - CLKEN bit in the USART_CR2 register,
- * - SCEN bit in the USART_CR3 register,
- * - IREN bit in the USART_CR3 register,
- * - HDSEL bit in the USART_CR3 register.
- * @note Call of this function is equivalent to following function call sequence :
- * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
- * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
- * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
- * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
- * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
- * @note Other remaining configurations items related to Multi processor Mode
- * (as Baud Rate, Wake Up Method, Node address, ...) should be set using
- * dedicated functions
- * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
- * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
- * CR3 SCEN LL_USART_ConfigMultiProcessMode\n
- * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
- * CR3 IREN LL_USART_ConfigMultiProcessMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
- /* In Multi Processor mode, the following bits must be kept cleared:
- - LINEN and CLKEN bits in the USART_CR2 register,
- - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
- CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Check if the USART Parity Error Flag is set or not
- * @rmtoll SR PE LL_USART_IsActiveFlag_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
-}
-
-/**
- * @brief Check if the USART Framing Error Flag is set or not
- * @rmtoll SR FE LL_USART_IsActiveFlag_FE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
-}
-
-/**
- * @brief Check if the USART Noise error detected Flag is set or not
- * @rmtoll SR NF LL_USART_IsActiveFlag_NE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
-}
-
-/**
- * @brief Check if the USART OverRun Error Flag is set or not
- * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
-}
-
-/**
- * @brief Check if the USART IDLE line detected Flag is set or not
- * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
-}
-
-/**
- * @brief Check if the USART Read Data Register Not Empty Flag is set or not
- * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
-}
-
-/**
- * @brief Check if the USART Transmission Complete Flag is set or not
- * @rmtoll SR TC LL_USART_IsActiveFlag_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
-}
-
-/**
- * @brief Check if the USART Transmit Data Register Empty Flag is set or not
- * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll SR LBD LL_USART_IsActiveFlag_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
-}
-
-/**
- * @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
-}
-
-/**
- * @brief Check if the USART Send Break Flag is set or not
- * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
-}
-
-/**
- * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
- * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
-}
-
-/**
- * @brief Clear Parity Error Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * NE, FE, ORE, IDLE would also be cleared.
- * @rmtoll SR PE LL_USART_ClearFlag_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Framing Error Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, NE, ORE, IDLE would also be cleared.
- * @rmtoll SR FE LL_USART_ClearFlag_FE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Noise detected Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, FE, ORE, IDLE would also be cleared.
- * @rmtoll SR NF LL_USART_ClearFlag_NE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear OverRun Error Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, NE, FE, IDLE would also be cleared.
- * @rmtoll SR ORE LL_USART_ClearFlag_ORE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear IDLE line detected Flag
- * @note Clearing this flag is done by a read access to the USARTx_SR
- * register followed by a read access to the USARTx_DR register.
- * @note Please also consider that when clearing this flag, other flags as
- * PE, NE, FE, ORE would also be cleared.
- * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
- __IO uint32_t tmpreg;
- tmpreg = USARTx->SR;
- (void) tmpreg;
- tmpreg = USARTx->DR;
- (void) tmpreg;
-}
-
-/**
- * @brief Clear Transmission Complete Flag
- * @rmtoll SR TC LL_USART_ClearFlag_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR , ~(USART_SR_TC));
-}
-
-/**
- * @brief Clear RX Not Empty Flag
- * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR , ~(USART_SR_RXNE));
-}
-
-/**
- * @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll SR LBD LL_USART_ClearFlag_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR , ~(USART_SR_LBD));
-}
-
-/**
- * @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll SR CTS LL_USART_ClearFlag_nCTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
- WRITE_REG(USARTx->SR , ~(USART_SR_CTS));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
- * @brief Enable RX Not Empty Interrupt
- * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
- * @brief Enable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_EnableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
- * @brief Enable TX Empty Interrupt
- * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
- * @brief Enable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_EnableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Enable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
- * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
- * 0: Interrupt is inhibited
- * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
- * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Disable IDLE Interrupt
- * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
- * @brief Disable RX Not Empty Interrupt
- * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
- * @brief Disable Transmission Complete Interrupt
- * @rmtoll CR1 TCIE LL_USART_DisableIT_TC
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
- * @brief Disable TX Empty Interrupt
- * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
- * @brief Disable Parity Error Interrupt
- * @rmtoll CR1 PEIE LL_USART_DisableIT_PE
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
- * @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
- * @brief Disable Error Interrupt
- * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
- * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
- * 0: Interrupt is inhibited
- * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
- * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
- * @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
- * @brief Check if the USART IDLE Interrupt source is enabled or disabled.
- * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
-}
-
-/**
- * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled.
- * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
-}
-
-/**
- * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
- * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
-}
-
-/**
- * @brief Check if the USART TX Empty Interrupt is enabled or disabled.
- * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
-}
-
-/**
- * @brief Check if the USART Parity Error Interrupt is enabled or disabled.
- * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
-}
-
-/**
- * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
- * LIN feature is supported by the USARTx instance.
- * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
-}
-
-/**
- * @brief Check if the USART Error Interrupt is enabled or disabled.
- * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
-}
-
-/**
- * @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
- * Hardware Flow control feature is supported by the USARTx instance.
- * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
- * @{
- */
-
-/**
- * @brief Enable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Disable DMA Mode for reception
- * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for reception
- * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
-}
-
-/**
- * @brief Enable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Disable DMA Mode for transmission
- * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
- * @brief Check if DMA Mode is enabled for transmission
- * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
- * @param USARTx USART Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
- return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll DR DR LL_USART_DMA_GetRegAddr
- * @note Address of Data Register is valid for both Transmit and Receive transfers.
- * @param USARTx USART Instance
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
-{
- /* return address of DR register */
- return ((uint32_t) &(USARTx->DR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
- * @{
- */
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 8 bits)
- * @rmtoll DR DR LL_USART_ReceiveData8
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
- return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
- * @brief Read Receiver Data register (Receive Data value, 9 bits)
- * @rmtoll DR DR LL_USART_ReceiveData9
- * @param USARTx USART Instance
- * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
- */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
- return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
- * @rmtoll DR DR LL_USART_TransmitData8
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
- USARTx->DR = Value;
-}
-
-/**
- * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
- * @rmtoll DR DR LL_USART_TransmitData9
- * @param USARTx USART Instance
- * @param Value between Min_Data=0x00 and Max_Data=0x1FF
- * @retval None
- */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
- USARTx->DR = Value & 0x1FFU;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_LL_EF_Execution Execution
- * @{
- */
-
-/**
- * @brief Request Break sending
- * @rmtoll CR1 SBK LL_USART_RequestBreakSending
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_SBK);
-}
-
-/**
- * @brief Put USART in Mute mode
- * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
- SET_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
- * @brief Put USART in Active mode
- * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode
- * @param USARTx USART Instance
- * @retval None
- */
-__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
-{
- CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_usart.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_usb.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,614 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_usb.h
- * @author MCD Application Team
- * @brief Header file of USB Low Layer HAL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_USB_H
-#define __STM32F1xx_LL_USB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F102x6) || defined(STM32F102xB) || \
- defined(STM32F103x6) || defined(STM32F103xB) || \
- defined(STM32F103xE) || defined(STM32F103xG) || \
- defined(STM32F105xC) || defined(STM32F107xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_hal_def.h"
-
-/** @addtogroup STM32F1xx_HAL_Driver
- * @{
- */
-
-/** @addtogroup USB_LL
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Types USB Low Layer Exported Types
- * @{
- */
-/**
- * @brief USB Mode definition
- */
-typedef enum
-{
- USB_DEVICE_MODE = 0,
- USB_HOST_MODE = 1,
- USB_DRD_MODE = 2
-}USB_ModeTypeDef;
-
-#if defined (USB_OTG_FS)
-/**
- * @brief URB States definition
- */
-typedef enum {
- URB_IDLE = 0,
- URB_DONE,
- URB_NOTREADY,
- URB_NYET,
- URB_ERROR,
- URB_STALL
-}USB_OTG_URBStateTypeDef;
-
-/**
- * @brief Host channel States definition
- */
-typedef enum {
- HC_IDLE = 0,
- HC_XFRC,
- HC_HALTED,
- HC_NAK,
- HC_NYET,
- HC_STALL,
- HC_XACTERR,
- HC_BBLERR,
- HC_DATATGLERR
-}USB_OTG_HCStateTypeDef;
-
-/**
- * @brief USB OTG Initialization Structure definition
- */
-typedef struct
-{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t Host_channels; /*!< Host Channels number.
- This parameter Depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref USB_EP0_MPS_ */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
-
- uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
-
- uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
-
- uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
-}USB_OTG_CfgTypeDef;
-
-typedef struct
-{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type_ */
-
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t even_odd_frame; /*!< IFrame parity
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint16_t tx_fifo_num; /*!< Transmission FIFO number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
-
- uint32_t xfer_len; /*!< Current transfer length */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
-}USB_OTG_EPTypeDef;
-
-typedef struct
-{
- uint8_t dev_addr ; /*!< USB device address.
- This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
-
- uint8_t ch_num; /*!< Host channel number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t ep_num; /*!< Endpoint number.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t ep_is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t speed; /*!< USB Host speed.
- This parameter can be any value of @ref USB_Core_Speed_ */
-
- uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
-
- uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
-
- uint8_t ep_type; /*!< Endpoint Type.
- This parameter can be any value of @ref USB_EP_Type_ */
-
- uint16_t max_packet; /*!< Endpoint Max packet size.
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t data_pid; /*!< Initial data PID.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
-
- uint32_t xfer_len; /*!< Current transfer length. */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
-
- uint8_t toggle_in; /*!< IN transfer current toggle flag.
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t toggle_out; /*!< OUT transfer current toggle flag
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
-
- uint32_t ErrCnt; /*!< Host channel error count.*/
-
- USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
- This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
-
- USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
- This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
-}USB_OTG_HCTypeDef;
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-/**
- * @brief USB Initialization Structure definition
- */
-typedef struct
-{
- uint32_t dev_endpoints; /*!< Device Endpoints number.
- This parameter depends on the used USB core.
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint32_t speed; /*!< USB Core speed.
- This parameter can be any value of @ref USB_Core_Speed */
-
- uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
- This parameter can be any value of @ref USB_EP0_MPS */
-
- uint32_t phy_itface; /*!< Select the used PHY interface.
- This parameter can be any value of @ref USB_Core_PHY */
-
- uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
-
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
-
- uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
-
- uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
-} USB_CfgTypeDef;
-
-typedef struct
-{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
-
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
-
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type */
-
- uint16_t pmaadress; /*!< PMA Address
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
- uint16_t pmaaddr0; /*!< PMA Address0
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
- uint16_t pmaaddr1; /*!< PMA Address1
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
-
- uint8_t doublebuffer; /*!< Double buffer enable
- This parameter can be 0 or 1 */
-
- uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral
- This parameter is added to ensure compatibility across USB peripherals */
-
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
-
- uint32_t xfer_len; /*!< Current transfer length */
-
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
-
-} USB_EPTypeDef;
-#endif /* USB */
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Constants USB Low Layer Exported Constants
- * @{
- */
-#if defined (USB_OTG_FS)
-/** @defgroup USB_LL_Core_Mode USB Low Layer Core Mode
- * @{
- */
-#define USB_OTG_MODE_DEVICE 0
-#define USB_OTG_MODE_HOST 1
-#define USB_OTG_MODE_DRD 2
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
- * @{
- */
-#define USB_OTG_SPEED_LOW 2
-#define USB_OTG_SPEED_FULL 3
-
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY
- * @{
- */
-#define USB_OTG_ULPI_PHY 1
-#define USB_OTG_EMBEDDED_PHY 2
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS
- * @{
- */
-#define USB_OTG_FS_MAX_PACKET_SIZE 64
-#define USB_OTG_MAX_EP0_SIZE 64
-/**
- * @}
- */
-
-/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency
- * @{
- */
-#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)
-#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)
-#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)
-/**
- * @}
- */
-
-/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval
- * @{
- */
-#define DCFG_FRAME_INTERVAL_80 0
-#define DCFG_FRAME_INTERVAL_85 1
-#define DCFG_FRAME_INTERVAL_90 2
-#define DCFG_FRAME_INTERVAL_95 3
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
- * @{
- */
-#define DEP0CTL_MPS_64 0
-#define DEP0CTL_MPS_32 1
-#define DEP0CTL_MPS_16 2
-#define DEP0CTL_MPS_8 3
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
- * @{
- */
-#define EP_SPEED_LOW 0
-#define EP_SPEED_FULL 1
-#define EP_SPEED_HIGH 2
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
- * @{
- */
-#define EP_TYPE_CTRL 0
-#define EP_TYPE_ISOC 1
-#define EP_TYPE_BULK 2
-#define EP_TYPE_INTR 3
-#define EP_TYPE_MSK 3
-/**
- * @}
- */
-
-/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
- * @{
- */
-#define STS_GOUT_NAK 1
-#define STS_DATA_UPDT 2
-#define STS_XFER_COMP 3
-#define STS_SETUP_COMP 4
-#define STS_SETUP_UPDT 6
-/**
- * @}
- */
-
-/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines
- * @{
- */
-#define HCFG_30_60_MHZ 0
-#define HCFG_48_MHZ 1
-#define HCFG_6_MHZ 2
-/**
- * @}
- */
-
-/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
- * @{
- */
-#define HPRT0_PRTSPD_HIGH_SPEED 0
-#define HPRT0_PRTSPD_FULL_SPEED 1
-#define HPRT0_PRTSPD_LOW_SPEED 2
-/**
- * @}
- */
-
-#define HCCHAR_CTRL 0
-#define HCCHAR_ISOC 1
-#define HCCHAR_BULK 2
-#define HCCHAR_INTR 3
-
-#define HC_PID_DATA0 0
-#define HC_PID_DATA2 1
-#define HC_PID_DATA1 2
-#define HC_PID_SETUP 3
-
-#define GRXSTS_PKTSTS_IN 2
-#define GRXSTS_PKTSTS_IN_XFER_COMP 3
-#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
-#define GRXSTS_PKTSTS_CH_HALTED 7
-
-#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
-#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
-
-#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
-#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
-
-#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
-#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
- * @{
- */
-#define DEP0CTL_MPS_64 0
-#define DEP0CTL_MPS_32 1
-#define DEP0CTL_MPS_16 2
-#define DEP0CTL_MPS_8 3
-/**
- * @}
- */
-
-/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
- * @{
- */
-#define EP_TYPE_CTRL 0
-#define EP_TYPE_ISOC 1
-#define EP_TYPE_BULK 2
-#define EP_TYPE_INTR 3
-#define EP_TYPE_MSK 3
-/**
- * @}
- */
-
-#define BTABLE_ADDRESS (0x000)
-#endif /* USB */
-/**
- * @}
- */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros
- * @{
- */
-#if defined (USB_OTG_FS)
-#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
-#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
-
-#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
-#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
-#endif /* USB_OTG_FS */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
- * @{
- */
-/** @addtogroup USB_LL_Exported_Functions_Group1 Peripheral Control functions
- * @{
- */
-#if defined (USB_OTG_FS)
-HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
-void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t *psetup);
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
-void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
-uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
- uint8_t ch_num,
- uint8_t epnum,
- uint8_t dev_address,
- uint8_t speed,
- uint8_t ep_type,
- uint16_t mps);
-HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc);
-uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
-HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-#endif /* USB_OTG_FS */
-
-#if defined (USB)
-HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
-HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef Init);
-HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx , uint8_t speed);
-HAL_StatusTypeDef USB_FlushRxFifo (USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num );
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
-void * USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx , USB_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
-uint32_t USB_ReadInterrupts (USB_TypeDef *USBx);
-uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx);
-uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
-uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx);
-uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum);
-void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt);
-
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
-void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-#endif /* USB */
-/**
- * @}
- */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* STM32F102x6 || STM32F102xB || */
- /* STM32F103x6 || STM32F103xB || */
- /* STM32F103xE || STM32F103xG || */
- /* STM32F105xC || STM32F107xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F1xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_usb.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_utils.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,282 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_utils.h
- * @author MCD Application Team
- * @brief Header file of UTILS LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL UTILS driver contains a set of generic APIs that can be
- used by user:
- (+) Device electronic signature
- (+) Timing functions
- (+) PLL configuration functions
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_UTILS_H
-#define __STM32F1xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-/** @defgroup UTILS_LL UTILS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
- * @{
- */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY 0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
- * @{
- */
-/**
- * @}
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
- * @{
- */
-/**
- * @brief UTILS PLL structure definition
- */
-typedef struct
-{
- uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
- This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
- uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
- This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
- * @brief UTILS System, AHB and APB buses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAHBPrescaler(). */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB1Prescaler(). */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
- * @{
- */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
- * @{
- */
-#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
-#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
- * @{
- */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
- * @{
- */
-
-/**
- * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
- * @retval UID[31:0]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
- * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
- * @retval UID[63:32]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
- * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
- * @retval UID[95:64]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
- * @brief Get Flash memory size
- * @note This bitfield indicates the size of the device Flash memory expressed in
- * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
- * @retval FLASH_SIZE[15:0]: Flash memory size
- */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
- return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source of the time base.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @note When a RTOS is used, it is recommended to avoid changing the SysTick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
- * @retval None
- */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
- /* Configure the SysTick to have interrupt in 1ms time base */
- SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
-}
-
-void LL_Init1msTick(uint32_t HCLKFrequency);
-void LL_mDelay(uint32_t Delay);
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
- * @{
- */
-
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_utils.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_wwdg.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,340 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_wwdg.h
- * @author MCD Application Team
- * @brief Header file of WWDG LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_WWDG_H
-#define __STM32F1xx_LL_WWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (WWDG)
-
-/** @defgroup WWDG_LL WWDG
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
- * @{
- */
-
-
-/** @defgroup WWDG_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
- * @{
- */
-#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
-* @{
-*/
-#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
- * @{
- */
-/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in WWDG register
- * @param __INSTANCE__ WWDG Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in WWDG register
- * @param __INSTANCE__ WWDG Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
- * @{
- */
-
-/** @defgroup WWDG_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
- * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
- * then it cannot be disabled again except by a reset.
- * This bit is set by software and only cleared by hardware after a reset.
- * When WDGA = 1, the watchdog can generate a reset.
- * @rmtoll CR WDGA LL_WWDG_Enable
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
-{
- SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
-}
-
-/**
- * @brief Checks if Window Watchdog is enabled
- * @rmtoll CR WDGA LL_WWDG_IsEnabled
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
-}
-
-/**
- * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
- * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
- * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
- * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
- * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
- * @rmtoll CR T LL_WWDG_SetCounter
- * @param WWDGx WWDG Instance
- * @param Counter 0..0x7F (7 bit counter value)
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
-{
- MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
-}
-
-/**
- * @brief Return current Watchdog Counter Value (7 bits counter value)
- * @rmtoll CR T LL_WWDG_GetCounter
- * @param WWDGx WWDG Instance
- * @retval 7 bit Watchdog Counter value
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
-{
- return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
-}
-
-/**
- * @brief Set the time base of the prescaler (WDGTB).
- * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
- * is decremented every (4096 x 2expWDGTB) PCLK cycles
- * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
- * @param WWDGx WWDG Instance
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_WWDG_PRESCALER_1
- * @arg @ref LL_WWDG_PRESCALER_2
- * @arg @ref LL_WWDG_PRESCALER_4
- * @arg @ref LL_WWDG_PRESCALER_8
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
-{
- MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
-}
-
-/**
- * @brief Return current Watchdog Prescaler Value
- * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
- * @param WWDGx WWDG Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_WWDG_PRESCALER_1
- * @arg @ref LL_WWDG_PRESCALER_2
- * @arg @ref LL_WWDG_PRESCALER_4
- * @arg @ref LL_WWDG_PRESCALER_8
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
-{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
-}
-
-/**
- * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
- * @note This window value defines when write in the WWDG_CR register
- * to program Watchdog counter is allowed.
- * Watchdog counter value update must occur only when the counter value
- * is lower than the Watchdog window register value.
- * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
- * (in the control register) is refreshed before the downcounter has reached
- * the watchdog window register value.
- * Physically is possible to set the Window lower then 0x40 but it is not recommended.
- * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
- * @rmtoll CFR W LL_WWDG_SetWindow
- * @param WWDGx WWDG Instance
- * @param Window 0x00..0x7F (7 bit Window value)
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
-{
- MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
-}
-
-/**
- * @brief Return current Watchdog Window Value (7 bits value)
- * @rmtoll CFR W LL_WWDG_GetWindow
- * @param WWDGx WWDG Instance
- * @retval 7 bit Watchdog Window value
- */
-__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
-{
- return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-/**
- * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
- * @note This bit is set by hardware when the counter has reached the value 0x40.
- * It must be cleared by software by writing 0.
- * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
- * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
-}
-
-/**
- * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
- * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
-{
- WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_LL_EF_IT_Management IT_Management
- * @{
- */
-/**
- * @brief Enable the Early Wakeup Interrupt.
- * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
- * This interrupt is only cleared by hardware after a reset
- * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
- * @param WWDGx WWDG Instance
- * @retval None
- */
-__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
- SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
-}
-
-/**
- * @brief Check if Early Wakeup Interrupt is enabled
- * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
- * @param WWDGx WWDG Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
-{
- return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* WWDG */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm_spi_api.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/system_clock.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/system_stm32f1xx.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,118 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f10x.h
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F10X_H
-#define __SYSTEM_STM32F10X_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F10x_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F10x_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F10X_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/system_stm32f1xx.o has changed
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/trng_api.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/tz_context.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,70 +0,0 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include <stdint.h> - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H
Binary file STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/us_ticker.o has changed
--- a/STM32F103C8T6_MPA/mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/us_ticker_data.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef __US_TICKER_DATA_H
-#define __US_TICKER_DATA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32f1xx.h"
-#include "stm32f1xx_ll_tim.h"
-#include "cmsis_nvic.h"
-
-#define TIM_MST TIM4
-#define TIM_MST_IRQ TIM4_IRQn
-#define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE()
-#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4()
-
-#define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET()
-#define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET()
-
-#define TIM_MST_BIT_WIDTH 16 // 16 or 32
-
-#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __US_TICKER_DATA_H
-
--- a/STM32F103C8T6_MPA/mbed/drivers/AnalogIn.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,139 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_H
-#define MBED_ANALOGIN_H
-
-#include "platform/platform.h"
-
-#if DEVICE_ANALOGIN || defined(DOXYGEN_ONLY)
-
-#include "hal/analogin_api.h"
-#include "platform/SingletonPtr.h"
-#include "platform/PlatformMutex.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** An analog input, used for reading the voltage on a pin
- *
- * @note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Print messages when the AnalogIn is greater than 50%
- *
- * #include "mbed.h"
- *
- * AnalogIn temperature(p20);
- *
- * int main() {
- * while(1) {
- * if(temperature > 0.5) {
- * printf("Too hot! (%f)", temperature.read());
- * }
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class AnalogIn {
-
-public:
-
- /** Create an AnalogIn, connected to the specified pin
- *
- * @param pin AnalogIn pin to connect to
- */
- AnalogIn(PinName pin)
- {
- lock();
- analogin_init(&_adc, pin);
- unlock();
- }
-
- /** Read the input voltage, represented as a float in the range [0.0, 1.0]
- *
- * @returns A floating-point value representing the current input voltage, measured as a percentage
- */
- float read()
- {
- lock();
- float ret = analogin_read(&_adc);
- unlock();
- return ret;
- }
-
- /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
- *
- * @returns
- * 16-bit unsigned short representing the current input voltage, normalized to a 16-bit value
- */
- unsigned short read_u16()
- {
- lock();
- unsigned short ret = analogin_read_u16(&_adc);
- unlock();
- return ret;
- }
-
- /** An operator shorthand for read()
- *
- * The float() operator can be used as a shorthand for read() to simplify common code sequences
- *
- * Example:
- * @code
- * float x = volume.read();
- * float x = volume;
- *
- * if(volume.read() > 0.25) { ... }
- * if(volume > 0.25) { ... }
- * @endcode
- */
- operator float()
- {
- // Underlying call is thread safe
- return read();
- }
-
- virtual ~AnalogIn()
- {
- // Do nothing
- }
-
-protected:
-#if !defined(DOXYGEN_ONLY)
- virtual void lock()
- {
- _mutex->lock();
- }
-
- virtual void unlock()
- {
- _mutex->unlock();
- }
-
- analogin_t _adc;
- static SingletonPtr<PlatformMutex> _mutex;
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/drivers/AnalogOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,165 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_H
-#define MBED_ANALOGOUT_H
-
-#include "platform/platform.h"
-
-#if DEVICE_ANALOGOUT || defined(DOXYGEN_ONLY)
-
-#include "hal/analogout_api.h"
-#include "platform/PlatformMutex.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** An analog output, used for setting the voltage on a pin
- *
- * @note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Make a sawtooth output
- *
- * #include "mbed.h"
- *
- * AnalogOut tri(p18);
- * int main() {
- * while(1) {
- * tri = tri + 0.01;
- * wait_us(1);
- * if(tri == 1) {
- * tri = 0;
- * }
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class AnalogOut {
-
-public:
-
- /** Create an AnalogOut connected to the specified pin
- *
- * @param pin AnalogOut pin to connect to
- */
- AnalogOut(PinName pin)
- {
- analogout_init(&_dac, pin);
- }
-
- /** Set the output voltage, specified as a percentage (float)
- *
- * @param value A floating-point value representing the output voltage,
- * specified as a percentage. The value should lie between
- * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
- * Values outside this range will be saturated to 0.0f or 1.0f.
- */
- void write(float value)
- {
- lock();
- analogout_write(&_dac, value);
- unlock();
- }
-
- /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
- *
- * @param value 16-bit unsigned short representing the output voltage,
- * normalized to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
- */
- void write_u16(unsigned short value)
- {
- lock();
- analogout_write_u16(&_dac, value);
- unlock();
- }
-
- /** Return the current output voltage setting, measured as a percentage (float)
- *
- * @returns
- * A floating-point value representing the current voltage being output on the pin,
- * measured as a percentage. The returned value will lie between
- * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
- *
- * @note
- * This value may not match exactly the value set by a previous write().
- */
- float read()
- {
- lock();
- float ret = analogout_read(&_dac);
- unlock();
- return ret;
- }
-
- /** An operator shorthand for write()
- * \sa AnalogOut::write()
- */
- AnalogOut &operator= (float percent)
- {
- // Underlying write call is thread safe
- write(percent);
- return *this;
- }
-
- /** An operator shorthand for write()
- * \sa AnalogOut::write()
- */
- AnalogOut &operator= (AnalogOut &rhs)
- {
- // Underlying write call is thread safe
- write(rhs.read());
- return *this;
- }
-
- /** An operator shorthand for read()
- * \sa AnalogOut::read()
- */
- operator float()
- {
- // Underlying read call is thread safe
- return read();
- }
-
- virtual ~AnalogOut()
- {
- // Do nothing
- }
-
-protected:
-#if !defined(DOXYGEN_ONLY)
- virtual void lock()
- {
- _mutex.lock();
- }
-
- virtual void unlock()
- {
- _mutex.unlock();
- }
-
- dac_t _dac;
- PlatformMutex _mutex;
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/BusIn.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,131 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSIN_H
-#define MBED_BUSIN_H
-
-#include "platform/platform.h"
-#include "drivers/DigitalIn.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A digital input bus, used for reading the state of a collection of pins
- *
- * @note Synchronization level: Thread safe
- * @ingroup drivers
- */
-class BusIn : private NonCopyable<BusIn> {
-
-public:
- /* Group: Configuration Methods */
-
- /** Create an BusIn, connected to the specified pins
- *
- * @param p0 DigitalIn pin to connect to bus bit
- * @param p1 DigitalIn pin to connect to bus bit
- * @param p2 DigitalIn pin to connect to bus bit
- * @param p3 DigitalIn pin to connect to bus bit
- * @param p4 DigitalIn pin to connect to bus bit
- * @param p5 DigitalIn pin to connect to bus bit
- * @param p6 DigitalIn pin to connect to bus bit
- * @param p7 DigitalIn pin to connect to bus bit
- * @param p8 DigitalIn pin to connect to bus bit
- * @param p9 DigitalIn pin to connect to bus bit
- * @param p10 DigitalIn pin to connect to bus bit
- * @param p11 DigitalIn pin to connect to bus bit
- * @param p12 DigitalIn pin to connect to bus bit
- * @param p13 DigitalIn pin to connect to bus bit
- * @param p14 DigitalIn pin to connect to bus bit
- * @param p15 DigitalIn pin to connect to bus bit
- *
- * @note
- * It is only required to specify as many pin variables as is required
- * for the bus; the rest will default to NC (not connected)
- */
- BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
- PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
- PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
- PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-
- /** Create an BusIn, connected to the specified pins
- *
- * @param pins An array of pins to connect to bus bit
- */
- BusIn(PinName pins[16]);
-
- virtual ~BusIn();
-
- /** Read the value of the input bus
- *
- * @returns
- * An integer with each bit corresponding to the value read from the associated DigitalIn pin
- */
- int read();
-
- /** Set the input pin mode
- *
- * @param pull PullUp, PullDown, PullNone
- */
- void mode(PinMode pull);
-
- /** Binary mask of bus pins connected to actual pins (not NC pins)
- * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
- *
- * @returns
- * Binary mask of connected pins
- */
- int mask()
- {
- // No lock needed since _nc_mask is not modified outside the constructor
- return _nc_mask;
- }
-
- /** A shorthand for read()
- * \sa DigitalIn::read()
- */
- operator int();
-
- /** Access to particular bit in random-iterator fashion
- * @param index Position of bit
- */
- DigitalIn &operator[](int index);
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- DigitalIn *_pin[16];
-
- /* Mask of bus's NC pins
- * If bit[n] is set to 1 - pin is connected
- * if bit[n] is cleared - pin is not connected (NC)
- */
- int _nc_mask;
-
- PlatformMutex _mutex;
-
-private:
- virtual void lock();
- virtual void unlock();
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/drivers/BusInOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,146 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSINOUT_H
-#define MBED_BUSINOUT_H
-
-#include "drivers/DigitalInOut.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A digital input output bus, used for setting the state of a collection of pins
- *
- * @note Synchronization level: Thread safe
- * @ingroup drivers
- */
-class BusInOut : private NonCopyable<BusInOut> {
-
-public:
-
- /** Create an BusInOut, connected to the specified pins
- *
- * @param p0 DigitalInOut pin to connect to bus bit
- * @param p1 DigitalInOut pin to connect to bus bit
- * @param p2 DigitalInOut pin to connect to bus bit
- * @param p3 DigitalInOut pin to connect to bus bit
- * @param p4 DigitalInOut pin to connect to bus bit
- * @param p5 DigitalInOut pin to connect to bus bit
- * @param p6 DigitalInOut pin to connect to bus bit
- * @param p7 DigitalInOut pin to connect to bus bit
- * @param p8 DigitalInOut pin to connect to bus bit
- * @param p9 DigitalInOut pin to connect to bus bit
- * @param p10 DigitalInOut pin to connect to bus bit
- * @param p11 DigitalInOut pin to connect to bus bit
- * @param p12 DigitalInOut pin to connect to bus bit
- * @param p13 DigitalInOut pin to connect to bus bit
- * @param p14 DigitalInOut pin to connect to bus bit
- * @param p15 DigitalInOut pin to connect to bus bit
- *
- * @note
- * It is only required to specify as many pin variables as is required
- * for the bus; the rest will default to NC (not connected)
- */
- BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
- PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
- PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
- PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
- /** Create an BusInOut, connected to the specified pins
- *
- * @param pins An array of pins to construct a BusInOut from
- */
- BusInOut(PinName pins[16]);
-
- virtual ~BusInOut();
-
- /* Group: Access Methods */
-
- /** Write the value to the output bus
- *
- * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
- */
- void write(int value);
-
- /** Read the value currently output on the bus
- *
- * @returns
- * An integer with each bit corresponding to associated DigitalInOut pin setting
- */
- int read();
-
- /** Set all the pins in bus as output
- */
- void output();
-
- /** Set all the pins in bus as an input
- */
- void input();
-
- /** Set the input pin mode for all the pins in bus
- *
- * @param pull PullUp, PullDown, PullNone
- */
- void mode(PinMode pull);
-
- /** Binary mask of bus pins connected to actual pins (not NC pins)
- * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
- *
- * @returns
- * Binary mask of connected pins
- */
- int mask()
- {
- // No lock needed since _nc_mask is not modified outside the constructor
- return _nc_mask;
- }
-
- /** A shorthand for write()
- * \sa BusInOut::write()
- */
- BusInOut &operator= (int v);
- BusInOut &operator= (BusInOut &rhs);
-
- /** Access to particular bit in random-iterator fashion
- * @param index Bit Position
- */
- DigitalInOut &operator[](int index);
-
- /** A shorthand for read()
- * \sa BusInOut::read()
- */
- operator int();
-#if !defined(DOXYGEN_ONLY)
-protected:
- virtual void lock();
- virtual void unlock();
- DigitalInOut *_pin[16];
-
- /* Mask of bus's NC pins
- * If bit[n] is set to 1 - pin is connected
- * if bit[n] is cleared - pin is not connected (NC)
- */
- int _nc_mask;
-
- PlatformMutex _mutex;
-#endif
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/BusOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,130 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSOUT_H
-#define MBED_BUSOUT_H
-
-#include "drivers/DigitalOut.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A digital output bus, used for setting the state of a collection of pins
- * @ingroup drivers
- */
-class BusOut : private NonCopyable<BusOut> {
-
-public:
-
- /** Create an BusOut, connected to the specified pins
- *
- * @param p0 DigitalOut pin to connect to bus bit
- * @param p1 DigitalOut pin to connect to bus bit
- * @param p2 DigitalOut pin to connect to bus bit
- * @param p3 DigitalOut pin to connect to bus bit
- * @param p4 DigitalOut pin to connect to bus bit
- * @param p5 DigitalOut pin to connect to bus bit
- * @param p6 DigitalOut pin to connect to bus bit
- * @param p7 DigitalOut pin to connect to bus bit
- * @param p8 DigitalOut pin to connect to bus bit
- * @param p9 DigitalOut pin to connect to bus bit
- * @param p10 DigitalOut pin to connect to bus bit
- * @param p11 DigitalOut pin to connect to bus bit
- * @param p12 DigitalOut pin to connect to bus bit
- * @param p13 DigitalOut pin to connect to bus bit
- * @param p14 DigitalOut pin to connect to bus bit
- * @param p15 DigitalOut pin to connect to bus bit
- *
- * @note Synchronization level: Thread safe
- *
- * @note
- * It is only required to specify as many pin variables as is required
- * for the bus; the rest will default to NC (not connected)
- */
- BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
- PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
- PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
- PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
- /** Create an BusOut, connected to the specified pins
- *
- * @param pins An array of pins to connect to bus the bit
- */
- BusOut(PinName pins[16]);
-
- virtual ~BusOut();
-
- /** Write the value to the output bus
- *
- * @param value An integer specifying a bit to write for every corresponding DigitalOut pin
- */
- void write(int value);
-
- /** Read the value currently output on the bus
- *
- * @returns
- * An integer with each bit corresponding to associated DigitalOut pin setting
- */
- int read();
-
- /** Binary mask of bus pins connected to actual pins (not NC pins)
- * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
- *
- * @returns
- * Binary mask of connected pins
- */
- int mask()
- {
- // No lock needed since _nc_mask is not modified outside the constructor
- return _nc_mask;
- }
-
- /** A shorthand for write()
- * \sa BusOut::write()
- */
- BusOut &operator= (int v);
- BusOut &operator= (BusOut &rhs);
-
- /** Access to particular bit in random-iterator fashion
- * @param index Bit Position
- */
- DigitalOut &operator[](int index);
-
- /** A shorthand for read()
- * \sa BusOut::read()
- */
- operator int();
-#if !defined(DOXYGEN_ONLY)
-protected:
- virtual void lock();
- virtual void unlock();
- DigitalOut *_pin[16];
-
- /* Mask of bus's NC pins
- * If bit[n] is set to 1 - pin is connected
- * if bit[n] is cleared - pin is not connected (NC)
- */
- int _nc_mask;
-
- PlatformMutex _mutex;
-#endif
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/CAN.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,311 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_H
-#define MBED_CAN_H
-
-#include "platform/platform.h"
-
-#if DEVICE_CAN || defined(DOXYGEN_ONLY)
-
-#include "hal/can_api.h"
-#include "platform/Callback.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** CANMessage class
- *
- * @note Synchronization level: Thread safe
- * @ingroup drivers
- */
-class CANMessage : public CAN_Message {
-
-public:
- /** Creates empty CAN message.
- */
- CANMessage() : CAN_Message()
- {
- len = 8;
- type = CANData;
- format = CANStandard;
- id = 0;
- memset(data, 0, 8);
- }
-
- /** Creates CAN message with specific content.
- *
- * @param _id Message ID
- * @param _data Mesaage Data
- * @param _len Message Data length
- * @param _type Type of Data: Use enum CANType for valid parameter values
- * @param _format Data Format: Use enum CANFormat for valid parameter values
- */
- CANMessage(unsigned _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard)
- {
- len = _len & 0xF;
- type = _type;
- format = _format;
- id = _id;
- memcpy(data, _data, _len);
- }
-
- /** Creates CAN remote message.
- *
- * @param _id Message ID
- * @param _format Data Format: Use enum CANType for valid parameter values
- */
- CANMessage(unsigned _id, CANFormat _format = CANStandard)
- {
- len = 0;
- type = CANRemote;
- format = _format;
- id = _id;
- memset(data, 0, 8);
- }
-};
-
-/** A can bus client, used for communicating with can devices
- * @ingroup drivers
- */
-class CAN : private NonCopyable<CAN> {
-
-public:
- /** Creates a CAN interface connected to specific pins.
- *
- * @param rd read from transmitter
- * @param td transmit to transmitter
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- *
- * Ticker ticker;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- * //The constructor takes in RX, and TX pin respectively.
- * //These pins, for this example, are defined in mbed_app.json
- * CAN can1(MBED_CONF_APP_CAN1_RD, MBED_CONF_APP_CAN1_TD);
- * CAN can2(MBED_CONF_APP_CAN2_RD, MBED_CONF_APP_CAN2_TD);
- *
- * char counter = 0;
- *
- * void send() {
- * if(can1.write(CANMessage(1337, &counter, 1))) {
- * printf("Message sent: %d\n", counter);
- * counter++;
- * }
- * led1 = !led1;
- * }
- *
- * int main() {
- * ticker.attach(&send, 1);
- * CANMessage msg;
- * while(1) {
- * if(can2.read(msg)) {
- * printf("Message received: %d\n\n", msg.data[0]);
- * led2 = !led2;
- * }
- * wait(0.2);
- * }
- * }
- *
- * @endcode
- */
- CAN(PinName rd, PinName td);
-
- /** Initialize CAN interface and set the frequency
- *
- * @param rd the read pin
- * @param td the transmit pin
- * @param hz the bus frequency in hertz
- */
- CAN(PinName rd, PinName td, int hz);
-
- virtual ~CAN();
-
- /** Set the frequency of the CAN interface
- *
- * @param hz The bus frequency in hertz
- *
- * @returns
- * 1 if successful,
- * 0 otherwise
- */
- int frequency(int hz);
-
- /** Write a CANMessage to the bus.
- *
- * @param msg The CANMessage to write.
- *
- * @returns
- * 0 if write failed,
- * 1 if write was successful
- */
- int write(CANMessage msg);
-
- /** Read a CANMessage from the bus.
- *
- * @param msg A CANMessage to read to.
- * @param handle message filter handle (0 for any message)
- *
- * @returns
- * 0 if no message arrived,
- * 1 if message arrived
- */
- int read(CANMessage &msg, int handle = 0);
-
- /** Reset CAN interface.
- *
- * To use after error overflow.
- */
- void reset();
-
- /** Puts or removes the CAN interface into silent monitoring mode
- *
- * @param silent boolean indicating whether to go into silent mode or not
- */
- void monitor(bool silent);
-
- enum Mode {
- Reset = 0,
- Normal,
- Silent,
- LocalTest,
- GlobalTest,
- SilentTest
- };
-
- /** Change CAN operation to the specified mode
- *
- * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
- *
- * @returns
- * 0 if mode change failed or unsupported,
- * 1 if mode change was successful
- */
- int mode(Mode mode);
-
- /** Filter out incoming messages
- *
- * @param id the id to filter on
- * @param mask the mask applied to the id
- * @param format format to filter on (Default CANAny)
- * @param handle message filter handle (Optional)
- *
- * @returns
- * 0 if filter change failed or unsupported,
- * new filter handle if successful
- */
- int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
-
- /** Detects read errors - Used to detect read overflow errors.
- *
- * @returns number of read errors
- */
- unsigned char rderror();
-
- /** Detects write errors - Used to detect write overflow errors.
- *
- * @returns number of write errors
- */
- unsigned char tderror();
-
- enum IrqType {
- RxIrq = 0,
- TxIrq,
- EwIrq,
- DoIrq,
- WuIrq,
- EpIrq,
- AlIrq,
- BeIrq,
- IdIrq,
-
- IrqCnt
- };
-
- /** Attach a function to call whenever a CAN frame received interrupt is
- * generated.
- *
- * This function locks the deep sleep while a callback is attached
- *
- * @param func A pointer to a void function, or 0 to set as none
- * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
- */
- void attach(Callback<void()> func, IrqType type = RxIrq);
-
- /** Attach a member function to call whenever a CAN frame received interrupt
- * is generated.
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
- * @deprecated
- * The attach function does not support cv-qualifiers. Replaced by
- * attach(callback(obj, method), type).
- */
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The attach function does not support cv-qualifiers. Replaced by "
- "attach(callback(obj, method), type).")
- void attach(T *obj, void (T::*method)(), IrqType type = RxIrq)
- {
- // Underlying call thread safe
- attach(callback(obj, method), type);
- }
-
- /** Attach a member function to call whenever a CAN frame received interrupt
- * is generated.
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @param type Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
- * @deprecated
- * The attach function does not support cv-qualifiers. Replaced by
- * attach(callback(obj, method), type).
- */
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The attach function does not support cv-qualifiers. Replaced by "
- "attach(callback(obj, method), type).")
- void attach(T *obj, void (*method)(T *), IrqType type = RxIrq)
- {
- // Underlying call thread safe
- attach(callback(obj, method), type);
- }
-
- static void _irq_handler(uint32_t id, CanIrqType type);
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- virtual void lock();
- virtual void unlock();
- can_t _can;
- Callback<void()> _irq[IrqCnt];
- PlatformMutex _mutex;
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif // MBED_CAN_H
-
--- a/STM32F103C8T6_MPA/mbed/drivers/DigitalIn.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,132 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALIN_H
-#define MBED_DIGITALIN_H
-
-#include "platform/platform.h"
-
-#include "hal/gpio_api.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A digital input, used for reading the state of a pin
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Flash an LED while a DigitalIn is true
- *
- * #include "mbed.h"
- *
- * DigitalIn enable(p5);
- * DigitalOut led(LED1);
- *
- * int main() {
- * while(1) {
- * if(enable) {
- * led = !led;
- * }
- * wait(0.25);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class DigitalIn {
-
-public:
- /** Create a DigitalIn connected to the specified pin
- *
- * @param pin DigitalIn pin to connect to
- */
- DigitalIn(PinName pin) : gpio()
- {
- // No lock needed in the constructor
- gpio_init_in(&gpio, pin);
- }
-
- /** Create a DigitalIn connected to the specified pin
- *
- * @param pin DigitalIn pin to connect to
- * @param mode the initial mode of the pin
- */
- DigitalIn(PinName pin, PinMode mode) : gpio()
- {
- // No lock needed in the constructor
- gpio_init_in_ex(&gpio, pin, mode);
- }
- /** Read the input, represented as 0 or 1 (int)
- *
- * @returns
- * An integer representing the state of the input pin,
- * 0 for logical 0, 1 for logical 1
- */
- int read()
- {
- // Thread safe / atomic HAL call
- return gpio_read(&gpio);
- }
-
- /** Set the input pin mode
- *
- * @param pull PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode pull)
- {
- core_util_critical_section_enter();
- gpio_mode(&gpio, pull);
- core_util_critical_section_exit();
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * Non zero value if pin is connected to uc GPIO
- * 0 if gpio object was initialized with NC
- */
- int is_connected()
- {
- // Thread safe / atomic HAL call
- return gpio_is_connected(&gpio);
- }
-
- /** An operator shorthand for read()
- * \sa DigitalIn::read()
- * @code
- * DigitalIn button(BUTTON1);
- * DigitalOut led(LED1);
- * led = button; // Equivalent to led.write(button.read())
- * @endcode
- */
- operator int()
- {
- // Underlying read is thread safe
- return read();
- }
-
-protected:
-#if !defined(DOXYGEN_ONLY)
- gpio_t gpio;
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/DigitalInOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,176 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALINOUT_H
-#define MBED_DIGITALINOUT_H
-
-#include "platform/platform.h"
-
-#include "hal/gpio_api.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A digital input/output, used for setting or reading a bi-directional pin
- *
- * @note Synchronization level: Interrupt safe
- * @ingroup drivers
- */
-class DigitalInOut {
-
-public:
- /** Create a DigitalInOut connected to the specified pin
- *
- * @param pin DigitalInOut pin to connect to
- */
- DigitalInOut(PinName pin) : gpio()
- {
- // No lock needed in the constructor
- gpio_init_in(&gpio, pin);
- }
-
- /** Create a DigitalInOut connected to the specified pin
- *
- * @param pin DigitalInOut pin to connect to
- * @param direction the initial direction of the pin
- * @param mode the initial mode of the pin
- * @param value the initial value of the pin if is an output
- */
- DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio()
- {
- // No lock needed in the constructor
- gpio_init_inout(&gpio, pin, direction, mode, value);
- }
-
- /** Set the output, specified as 0 or 1 (int)
- *
- * @param value An integer specifying the pin output value,
- * 0 for logical 0, 1 (or any other non-zero value) for logical 1
- */
- void write(int value)
- {
- // Thread safe / atomic HAL call
- gpio_write(&gpio, value);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * an integer representing the output setting of the pin if it is an output,
- * or read the input if set as an input
- */
- int read()
- {
- // Thread safe / atomic HAL call
- return gpio_read(&gpio);
- }
-
- /** Set as an output
- */
- void output()
- {
- core_util_critical_section_enter();
- gpio_dir(&gpio, PIN_OUTPUT);
- core_util_critical_section_exit();
- }
-
- /** Set as an input
- */
- void input()
- {
- core_util_critical_section_enter();
- gpio_dir(&gpio, PIN_INPUT);
- core_util_critical_section_exit();
- }
-
- /** Set the input pin mode
- *
- * @param pull PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode pull)
- {
- core_util_critical_section_enter();
- gpio_mode(&gpio, pull);
- core_util_critical_section_exit();
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * Non zero value if pin is connected to uc GPIO
- * 0 if gpio object was initialized with NC
- */
- int is_connected()
- {
- // Thread safe / atomic HAL call
- return gpio_is_connected(&gpio);
- }
-
- /** A shorthand for write()
- * \sa DigitalInOut::write()
- * @code
- * DigitalInOut inout(PIN);
- * DigitalIn button(BUTTON1);
- * inout.output();
- *
- * inout = button; // Equivalent to inout.write(button.read())
- * @endcode
- */
- DigitalInOut &operator= (int value)
- {
- // Underlying write is thread safe
- write(value);
- return *this;
- }
-
- /**A shorthand for write() using the assignment operator which copies the
- * state from the DigitalInOut argument.
- * \sa DigitalInOut::write()
- */
- DigitalInOut &operator= (DigitalInOut &rhs)
- {
- core_util_critical_section_enter();
- write(rhs.read());
- core_util_critical_section_exit();
- return *this;
- }
-
- /** A shorthand for read()
- * \sa DigitalInOut::read()
- * @code
- * DigitalInOut inout(PIN);
- * DigitalOut led(LED1);
- *
- * inout.input();
- * led = inout; // Equivalent to led.write(inout.read())
- * @endcode
- */
- operator int()
- {
- // Underlying call is thread safe
- return read();
- }
-
-protected:
-#if !defined(DOXYGEN_ONLY)
- gpio_t gpio;
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/DigitalOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,155 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALOUT_H
-#define MBED_DIGITALOUT_H
-
-#include "platform/platform.h"
-#include "hal/gpio_api.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A digital output, used for setting the state of a pin
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Toggle a LED
- * #include "mbed.h"
- *
- * DigitalOut led(LED1);
- *
- * int main() {
- * while(1) {
- * led = !led;
- * wait(0.2);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class DigitalOut {
-
-public:
- /** Create a DigitalOut connected to the specified pin
- *
- * @param pin DigitalOut pin to connect to
- */
- DigitalOut(PinName pin) : gpio()
- {
- // No lock needed in the constructor
- gpio_init_out(&gpio, pin);
- }
-
- /** Create a DigitalOut connected to the specified pin
- *
- * @param pin DigitalOut pin to connect to
- * @param value the initial pin value
- */
- DigitalOut(PinName pin, int value) : gpio()
- {
- // No lock needed in the constructor
- gpio_init_out_ex(&gpio, pin, value);
- }
-
- /** Set the output, specified as 0 or 1 (int)
- *
- * @param value An integer specifying the pin output value,
- * 0 for logical 0, 1 (or any other non-zero value) for logical 1
- */
- void write(int value)
- {
- // Thread safe / atomic HAL call
- gpio_write(&gpio, value);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * an integer representing the output setting of the pin,
- * 0 for logical 0, 1 for logical 1
- */
- int read()
- {
- // Thread safe / atomic HAL call
- return gpio_read(&gpio);
- }
-
- /** Return the output setting, represented as 0 or 1 (int)
- *
- * @returns
- * Non zero value if pin is connected to uc GPIO
- * 0 if gpio object was initialized with NC
- */
- int is_connected()
- {
- // Thread safe / atomic HAL call
- return gpio_is_connected(&gpio);
- }
-
- /** A shorthand for write()
- * \sa DigitalOut::write()
- * @code
- * DigitalIn button(BUTTON1);
- * DigitalOut led(LED1);
- * led = button; // Equivalent to led.write(button.read())
- * @endcode
- */
- DigitalOut &operator= (int value)
- {
- // Underlying write is thread safe
- write(value);
- return *this;
- }
-
- /** A shorthand for write() using the assignment operator which copies the
- * state from the DigitalOut argument.
- * \sa DigitalOut::write()
- */
- DigitalOut &operator= (DigitalOut &rhs)
- {
- core_util_critical_section_enter();
- write(rhs.read());
- core_util_critical_section_exit();
- return *this;
- }
-
- /** A shorthand for read()
- * \sa DigitalOut::read()
- * @code
- * DigitalIn button(BUTTON1);
- * DigitalOut led(LED1);
- * led = button; // Equivalent to led.write(button.read())
- * @endcode
- */
- operator int()
- {
- // Underlying call is thread safe
- return read();
- }
-
-protected:
-#if !defined(DOXYGEN_ONLY)
- gpio_t gpio;
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/Ethernet.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,177 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_H
-#define MBED_ETHERNET_H
-
-#include "platform/platform.h"
-#include "platform/NonCopyable.h"
-
-#if DEVICE_ETHERNET || defined(DOXYGEN_ONLY)
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** An ethernet interface, to use with the ethernet pins.
- *
- * @note Synchronization level: Not protected
- *
- * Example:
- * @code
- * // Read destination and source from every ethernet packet
- *
- * #include "mbed.h"
- *
- * Ethernet eth;
- *
- * int main() {
- * char buf[0x600];
- *
- * while(1) {
- * int size = eth.receive();
- * if(size > 0) {
- * eth.read(buf, size);
- * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n",
- * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
- * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
- * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
- * }
- *
- * wait(1);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class Ethernet : private NonCopyable<Ethernet> {
-
-public:
-
- /** Initialize the ethernet interface.
- */
- Ethernet();
-
- /** Powers the hardware down.
- */
- virtual ~Ethernet();
-
- enum Mode {
- AutoNegotiate,
- HalfDuplex10,
- FullDuplex10,
- HalfDuplex100,
- FullDuplex100
- };
-
- /** Writes into an outgoing ethernet packet.
- *
- * It will append size bytes of data to the previously written bytes.
- *
- * @param data An array to write.
- * @param size The size of data.
- *
- * @returns
- * The number of written bytes.
- */
- int write(const char *data, int size);
-
- /** Send an outgoing ethernet packet.
- *
- * After filling in the data in an ethernet packet it must be send.
- * Send will provide a new packet to write to.
- *
- * @returns
- * 0 if the sending was failed,
- * or the size of the packet successfully sent.
- */
- int send();
-
- /** Receives an arrived ethernet packet.
- *
- * Receiving an ethernet packet will drop the last received ethernet packet
- * and make a new ethernet packet ready to read.
- * If no ethernet packet is arrived it will return 0.
- *
- * @returns
- * 0 if no ethernet packet is arrived,
- * or the size of the arrived packet.
- */
- int receive();
-
- /** Read from an received ethernet packet.
- *
- * After receive returned a number bigger than 0 it is
- * possible to read bytes from this packet.
- *
- * @param data Pointer to data packet
- * @param size Size of data to be read.
- * @returns The number of byte read.
- *
- * @note It is possible to use read multiple times.
- * Each time read will start reading after the last read byte before.
- *
- */
- int read(char *data, int size);
-
- /** Gives the ethernet address of the mbed.
- *
- * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
- */
- void address(char *mac);
-
- /** Returns if an ethernet link is present or not. It takes a while after Ethernet initialization to show up.
- *
- * @returns
- * 0 if no ethernet link is present,
- * 1 if an ethernet link is present.
- *
- * Example:
- * @code
- * // Using the Ethernet link function
- * #include "mbed.h"
- *
- * Ethernet eth;
- *
- * int main() {
- * wait(1); // Needed after startup.
- * if (eth.link()) {
- * printf("online\n");
- * } else {
- * printf("offline\n");
- * }
- * }
- * @endcode
- */
- int link();
-
- /** Sets the speed and duplex parameters of an ethernet link
- *
- * - AutoNegotiate Auto negotiate speed and duplex
- * - HalfDuplex10 10 Mbit, half duplex
- * - FullDuplex10 10 Mbit, full duplex
- * - HalfDuplex100 100 Mbit, half duplex
- * - FullDuplex100 100 Mbit, full duplex
- *
- * @param mode the speed and duplex mode to set the link to:
- */
- void set_link(Mode mode);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/FlashIAP.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,166 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- */
-#ifndef MBED_FLASHIAP_H
-#define MBED_FLASHIAP_H
-
-#if DEVICE_FLASH || defined(DOXYGEN_ONLY)
-
-#include "flash_api.h"
-#include "platform/SingletonPtr.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-#include <algorithm>
-
-// Export ROM end address
-#if defined(TOOLCHAIN_GCC_ARM)
-extern uint32_t __etext;
-extern uint32_t __data_start__;
-extern uint32_t __data_end__;
-#define FLASHIAP_APP_ROM_END_ADDR (((uint32_t) &__etext) + ((uint32_t) &__data_end__) - ((uint32_t) &__data_start__))
-#elif defined(TOOLCHAIN_ARM)
-extern uint32_t Load$$LR$$LR_IROM1$$Limit[];
-#define FLASHIAP_APP_ROM_END_ADDR ((uint32_t)Load$$LR$$LR_IROM1$$Limit)
-#elif defined(TOOLCHAIN_IAR)
-#pragma section=".rodata"
-#pragma section=".text"
-#pragma section=".init_array"
-#define FLASHIAP_APP_ROM_END_ADDR std::max(std::max((uint32_t) __section_end(".rodata"), (uint32_t) __section_end(".text")), \
- (uint32_t) __section_end(".init_array"))
-#endif
-
-namespace mbed {
-
-/** \addtogroup drivers */
-
-/** Flash IAP driver. It invokes flash HAL functions.
- *
- * @note Synchronization level: Thread safe
- * @ingroup drivers
- */
-class FlashIAP : private NonCopyable<FlashIAP> {
-public:
- FlashIAP();
- ~FlashIAP();
-
- /** Initialize a flash IAP device
- *
- * Should be called once per lifetime of the object.
- * @return 0 on success or a negative error code on failure
- */
- int init();
-
- /** Deinitialize a flash IAP device
- *
- * @return 0 on success or a negative error code on failure
- */
- int deinit();
-
- /** Read data from a flash device.
- *
- * This method invokes memcpy - reads number of bytes from the address
- *
- * @param buffer Buffer to write to
- * @param addr Flash address to begin reading from
- * @param size Size to read in bytes
- * @return 0 on success, negative error code on failure
- */
- int read(void *buffer, uint32_t addr, uint32_t size);
-
- /** Program data to pages
- *
- * The sectors must have been erased prior to being programmed
- *
- * @param buffer Buffer of data to be written
- * @param addr Address of a page to begin writing to
- * @param size Size to write in bytes, must be a multiple of program size
- * @return 0 on success, negative error code on failure
- */
- int program(const void *buffer, uint32_t addr, uint32_t size);
-
- /** Erase sectors
- *
- * The state of an erased sector is undefined until it has been programmed
- *
- * @param addr Address of a sector to begin erasing, must be a multiple of the sector size
- * @param size Size to erase in bytes, must be a multiple of the sector size
- * @return 0 on success, negative error code on failure
- */
- int erase(uint32_t addr, uint32_t size);
-
- /** Get the sector size at the defined address
- *
- * Sector size might differ at address ranges.
- * An example <0-0x1000, sector size=1024; 0x10000-0x20000, size=2048>
- *
- * @param addr Address of or inside the sector to query
- * @return Size of a sector in bytes or MBED_FLASH_INVALID_SIZE if not mapped
- */
- uint32_t get_sector_size(uint32_t addr) const;
-
- /** Get the flash start address
- *
- * @return Flash start address
- */
- uint32_t get_flash_start() const;
-
- /** Get the flash size
- *
- * @return Flash size
- */
- uint32_t get_flash_size() const;
-
- /** Get the program page size
- *
- * The page size defines the writable page size
- * @return Size of a program page in bytes
- */
- uint32_t get_page_size() const;
-
- /** Get the flash erase value
- *
- * Get the value we read after erase operation
- * @return flash erase value
- */
- uint8_t get_erase_value() const;
-
-#if !defined(DOXYGEN_ONLY)
-private:
-
- /* Check if address and size are aligned to a sector
- *
- * @param addr Address of block to check for alignment
- * @param size Size of block to check for alignment
- * @return true if the block is sector aligned, false otherwise
- */
- bool is_aligned_to_sector(uint32_t addr, uint32_t size);
-
- flash_t _flash;
- uint8_t *_page_buf;
- static SingletonPtr<PlatformMutex> _mutex;
-#endif
-};
-
-} /* namespace mbed */
-
-#endif /* DEVICE_FLASH */
-
-#endif /* MBED_FLASHIAP_H */
--- a/STM32F103C8T6_MPA/mbed/drivers/I2C.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,249 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_H
-#define MBED_I2C_H
-
-#include "platform/platform.h"
-#include "hal/gpio_api.h"
-
-#if DEVICE_I2C || defined(DOXYGEN_ONLY)
-
-#include "hal/i2c_api.h"
-#include "platform/SingletonPtr.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-
-#if DEVICE_I2C_ASYNCH
-#include "platform/CThunk.h"
-#include "hal/dma_api.h"
-#include "platform/FunctionPointer.h"
-#endif
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** An I2C Master, used for communicating with I2C slave devices
- *
- * @note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * Read temperature from LM75BD
- * #include "mbed.h"
- * I2C i2c(I2C_SDA , I2C_SCL);
- * const int addr7bit = 0x48; // 7-bit I2C address
- * const int addr8bit = 0x48 << 1; // 8-bit I2C address, 0x90
- *
- * int main() {
- * char cmd[2];
- * while (1) {
- * cmd[0] = 0x01;
- * cmd[1] = 0x00;
- *
- * // read and write takes the 8-bit version of the address.
- * // set up configuration register (at 0x01)
- * i2c.write(addr8bit, cmd, 2);
- *
- * wait(0.5);
- *
- * // read temperature register
- * cmd[0] = 0x00;
- * i2c.write(addr8bit, cmd, 1);
- * i2c.read( addr8bit, cmd, 2);
- *
- * float tmp = (float((cmd[0]<<8)|cmd[1]) / 256.0);
- * printf("Temp = %.2f\n", tmp);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class I2C : private NonCopyable<I2C> {
-
-public:
- enum RxStatus {
- NoData,
- MasterGeneralCall,
- MasterWrite,
- MasterRead
- };
-
- enum Acknowledge {
- NoACK = 0,
- ACK = 1
- };
-
- /** Create an I2C Master interface, connected to the specified pins
- *
- * @param sda I2C data line pin
- * @param scl I2C clock line pin
- */
- I2C(PinName sda, PinName scl);
-
- /** Set the frequency of the I2C interface
- *
- * @param hz The bus frequency in hertz
- */
- void frequency(int hz);
-
- /** Read from an I2C slave
- *
- * Performs a complete read transaction. The bottom bit of
- * the address is forced to 1 to indicate a read.
- *
- * @param address 8-bit I2C slave address [ addr | 1 ]
- * @param data Pointer to the byte-array to read data in to
- * @param length Number of bytes to read
- * @param repeated Repeated start, true - don't send stop at end
- * default value is false.
- *
- * @returns
- * 0 on success (ack),
- * nonzero on failure (nack)
- */
- int read(int address, char *data, int length, bool repeated = false);
-
- /** Read a single byte from the I2C bus
- *
- * @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
- *
- * @returns
- * the byte read
- */
- int read(int ack);
-
- /** Write to an I2C slave
- *
- * Performs a complete write transaction. The bottom bit of
- * the address is forced to 0 to indicate a write.
- *
- * @param address 8-bit I2C slave address [ addr | 0 ]
- * @param data Pointer to the byte-array data to send
- * @param length Number of bytes to send
- * @param repeated Repeated start, true - do not send stop at end
- * default value is false.
- *
- * @returns
- * 0 on success (ack),
- * nonzero on failure (nack)
- */
- int write(int address, const char *data, int length, bool repeated = false);
-
- /** Write single byte out on the I2C bus
- *
- * @param data data to write out on bus
- *
- * @returns
- * '0' - NAK was received
- * '1' - ACK was received,
- * '2' - timeout
- */
- int write(int data);
-
- /** Creates a start condition on the I2C bus
- */
- void start(void);
-
- /** Creates a stop condition on the I2C bus
- */
- void stop(void);
-
- /** Acquire exclusive access to this I2C bus
- */
- virtual void lock(void);
-
- /** Release exclusive access to this I2C bus
- */
- virtual void unlock(void);
-
- virtual ~I2C()
- {
- // Do nothing
- }
-
-#if DEVICE_I2C_ASYNCH
-
- /** Start nonblocking I2C transfer.
- *
- * This function locks the deep sleep until any event has occurred
- *
- * @param address 8/10 bit I2C slave address
- * @param tx_buffer The TX buffer with data to be transferred
- * @param tx_length The length of TX buffer in bytes
- * @param rx_buffer The RX buffer, which is used for received data
- * @param rx_length The length of RX buffer in bytes
- * @param event The logical OR of events to modify
- * @param callback The event callback function
- * @param repeated Repeated start, true - do not send stop at end
- * default value is false.
- *
- * @returns Zero if the transfer has started, or -1 if I2C peripheral is busy
- */
- int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t &callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
-
- /** Abort the ongoing I2C transfer
- */
- void abort_transfer();
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- /** Lock deep sleep only if it is not yet locked */
- void lock_deep_sleep();
-
- /** Unlock deep sleep only if it has been locked */
- void unlock_deep_sleep();
-
- void irq_handler_asynch(void);
- event_callback_t _callback;
- CThunk<I2C> _irq;
- DMAUsage _usage;
- bool _deep_sleep_locked;
-#endif
-#endif
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- void aquire();
-
- i2c_t _i2c;
- static I2C *_owner;
- int _hz;
- static SingletonPtr<PlatformMutex> _mutex;
- PinName _sda;
- PinName _scl;
-
-private:
- /** Recover I2C bus, when stuck with SDA low
- * @note : Initialization of I2C bus is required after this API.
- *
- * @param sda I2C data line pin
- * @param scl I2C clock line pin
- *
- * @returns
- * '0' - Successfully recovered
- * 'I2C_ERROR_BUS_BUSY' - In case of failure
- *
- */
- int recover(PinName sda, PinName scl);
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/I2CSlave.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,167 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_SLAVE_H
-#define MBED_I2C_SLAVE_H
-
-#include "platform/platform.h"
-
-#if DEVICE_I2CSLAVE || defined(DOXYGEN_ONLY)
-
-#include "hal/i2c_api.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** An I2C Slave, used for communicating with an I2C Master device.
- *
- * @note Synchronization level: Not protected
- *
- * Example Simple I2C responder:
- * @code
- * #include <mbed.h>
- *
- * const int SLAVE_ADDRESS = 0xA0;
- * const char message[] = "Slave!";
- *
- * I2CSlave slave(I2C_SDA, I2C_SCL);
- *
- * int main() {
- * slave.address(SLAVE_ADDRESS);
- * while (1) {
- * int operation = slave.receive();
- * switch (operation) {
- * case I2CSlave::ReadAddressed:
- * int status = slave.write(message, sizeof(message));
- * if (status == 0) {
- * printf("Written message: %s\n", message);
- * } else {
- * printf("Failed to write message.\n");
- * }
- * break;
- * case I2CSlave::WriteGeneral:
- * int byte_read = slave.read();
- * printf("Read General: %c (%d)\n", byte_read, byte_read);
- * break;
- * case I2CSlave::WriteAddressed:
- * int byte_read = slave.read();
- * printf("Read Addressed: %c (%d)\n", byte_read, byte_read);
- * break;
- * }
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class I2CSlave {
-
-public:
- enum RxStatus {
- NoData = 0,
- ReadAddressed = 1,
- WriteGeneral = 2,
- WriteAddressed = 3
- };
-
- /** Create an I2C Slave interface, connected to the specified pins.
- *
- * @param sda I2C data line pin.
- * @param scl I2C clock line pin.
- */
- I2CSlave(PinName sda, PinName scl);
-
- /** Set the frequency of the I2C interface.
- *
- * @param hz The bus frequency in Hertz.
- */
- void frequency(int hz);
-
- /** Check if this I2C Slave has been addressed.
- *
- * @return A status indicating if the device has been addressed and how.
- * @retval NoData The slave has not been addressed.
- * @retval ReadAddressed The master has requested a read from this slave.
- * @retval WriteAddressed The master is writing to this slave.
- * @retval WriteGeneral The master is writing to all slave.
- */
- int receive(void);
-
- /** Read specified number of bytes from an I2C master.
- *
- * @param data Pointer to the buffer to read data into.
- * @param length Number of bytes to read.
- *
- * @return Result of the operation.
- * @retval 0 If the number of bytes read is equal to length requested.
- * @retval nonzero On error or if the number of bytes read is less than requested.
- */
- int read(char *data, int length);
-
- /** Read a single byte from an I2C master.
- *
- * @return The byte read.
- */
- int read(void);
-
- /** Write to an I2C master.
- *
- * @param data Pointer to the buffer containing the data to be sent.
- * @param length Number of bytes to send.
- *
- * @return
- * @retval 0 If written all bytes successfully.
- * @retval nonzero On error or if the number of bytes written is less than requested.
- */
- int write(const char *data, int length);
-
- /** Write a single byte to an I2C master.
- *
- * @param data Value to write.
- *
- * @return Result of the operation.
- * @retval 0 If a NACK is received.
- * @retval 1 If an ACK is received.
- * @retval 2 On timeout.
- */
- int write(int data);
-
- /** Set the I2C slave address.
- *
- * @param address The address to set for the slave (least significant bit is ignored).
- *
- * @note If address is set to 0, the slave will only respond to the
- * general call address.
- */
- void address(int address);
-
- /** Reset the I2C slave back into the known ready receiving state.
- */
- void stop(void);
-
-#if !defined(DOXYGEN_ONLY)
-
-protected:
- /* Internal i2c object identifying the resources */
- i2c_t _i2c;
-
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/InterruptIn.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,182 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERRUPTIN_H
-#define MBED_INTERRUPTIN_H
-
-#include "platform/platform.h"
-
-#if DEVICE_INTERRUPTIN || defined(DOXYGEN_ONLY)
-
-#include "hal/gpio_api.h"
-#include "hal/gpio_irq_api.h"
-#include "platform/Callback.h"
-#include "platform/mbed_critical.h"
-#include "platform/mbed_toolchain.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A digital interrupt input, used to call a function on a rising or falling edge
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Flash an LED while waiting for events
- *
- * #include "mbed.h"
- *
- * InterruptIn event(p16);
- * DigitalOut led(LED1);
- *
- * void trigger() {
- * printf("triggered!\n");
- * }
- *
- * int main() {
- * // register trigger() to be called upon the rising edge of event
- * event.rise(&trigger);
- * while(1) {
- * led = !led;
- * wait(0.25);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class InterruptIn : private NonCopyable<InterruptIn> {
-
-public:
-
- /** Create an InterruptIn connected to the specified pin
- *
- * @param pin InterruptIn pin to connect to
- */
- InterruptIn(PinName pin);
-
- /** Create an InterruptIn connected to the specified pin,
- * and the pin configured to the specified mode.
- *
- * @param pin InterruptIn pin to connect to
- * @param mode Desired Pin mode configuration.
- * (Valid values could be PullNone, PullDown, PullUp and PullDefault.
- * See PinNames.h for your target for definitions)
- *
- */
- InterruptIn(PinName pin, PinMode mode);
-
- virtual ~InterruptIn();
-
- /** Read the input, represented as 0 or 1 (int)
- *
- * @returns
- * An integer representing the state of the input pin,
- * 0 for logical 0, 1 for logical 1
- */
- int read();
-
- /** An operator shorthand for read()
- */
- operator int();
-
-
- /** Attach a function to call when a rising edge occurs on the input
- *
- * @param func A pointer to a void function, or 0 to set as none
- */
- void rise(Callback<void()> func);
-
- /** Attach a member function to call when a rising edge occurs on the input
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @deprecated
- * The rise function does not support cv-qualifiers. Replaced by
- * rise(callback(obj, method)).
- */
- template<typename T, typename M>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The rise function does not support cv-qualifiers. Replaced by "
- "rise(callback(obj, method)).")
- void rise(T *obj, M method)
- {
- core_util_critical_section_enter();
- rise(callback(obj, method));
- core_util_critical_section_exit();
- }
-
- /** Attach a function to call when a falling edge occurs on the input
- *
- * @param func A pointer to a void function, or 0 to set as none
- */
- void fall(Callback<void()> func);
-
- /** Attach a member function to call when a falling edge occurs on the input
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @deprecated
- * The rise function does not support cv-qualifiers. Replaced by
- * rise(callback(obj, method)).
- */
- template<typename T, typename M>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The fall function does not support cv-qualifiers. Replaced by "
- "fall(callback(obj, method)).")
- void fall(T *obj, M method)
- {
- core_util_critical_section_enter();
- fall(callback(obj, method));
- core_util_critical_section_exit();
- }
-
- /** Set the input pin mode
- *
- * @param pull PullUp, PullDown, PullNone, PullDefault
- * See PinNames.h for your target for definitions)
- */
- void mode(PinMode pull);
-
- /** Enable IRQ. This method depends on hardware implementation, might enable one
- * port interrupts. For further information, check gpio_irq_enable().
- */
- void enable_irq();
-
- /** Disable IRQ. This method depends on hardware implementation, might disable one
- * port interrupts. For further information, check gpio_irq_disable().
- */
- void disable_irq();
-
- static void _irq_handler(uint32_t id, gpio_irq_event event);
-#if !defined(DOXYGEN_ONLY)
-protected:
- gpio_t gpio;
- gpio_irq_t gpio_irq;
-
- Callback<void()> _rise;
- Callback<void()> _fall;
-
- void irq_init(PinName pin);
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/InterruptManager.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,208 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERRUPTMANAGER_H
-#define MBED_INTERRUPTMANAGER_H
-
-#include "cmsis.h"
-#include "platform/CallChain.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-#include <string.h>
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** Use this singleton if you need to chain interrupt handlers.
- * @deprecated Do not use this class. This class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @note Synchronization level: Thread safe
- *
- * Example (for LPC1768):
- * @code
- * #include "InterruptManager.h"
- * #include "mbed.h"
- *
- * Ticker flipper;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * void flip(void) {
- * led1 = !led1;
- * }
- *
- * void handler(void) {
- * led2 = !led1;
- * }
- *
- * int main() {
- * led1 = led2 = 0;
- * flipper.attach(&flip, 1.0);
- * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
- * }
- * @endcode
- * @ingroup drivers
- */
-class InterruptManager : private NonCopyable<InterruptManager> {
-public:
- /** Get the instance of InterruptManager Class
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @return the only instance of this class
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- static InterruptManager *get();
-
- /** Destroy the current instance of the interrupt manager
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- static void destroy();
-
- /** Add a handler for an interrupt at the end of the handler list
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param function the handler to add
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'function'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq)
- {
- // Underlying call is thread safe
- return add_common(function, irq);
- }
-
- /** Add a handler for an interrupt at the beginning of the handler list
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param function the handler to add
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'function'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq)
- {
- // Underlying call is thread safe
- return add_common(function, irq, true);
- }
-
- /** Add a handler for an interrupt at the end of the handler list
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param tptr pointer to the object that has the handler function
- * @param mptr pointer to the actual handler function
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t add_handler(T *tptr, void (T::*mptr)(void), IRQn_Type irq)
- {
- // Underlying call is thread safe
- return add_common(tptr, mptr, irq);
- }
-
- /** Add a handler for an interrupt at the beginning of the handler list
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param tptr pointer to the object that has the handler function
- * @param mptr pointer to the actual handler function
- * @param irq interrupt number
- *
- * @returns
- * The function object created for 'tptr' and 'mptr'
- */
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t add_handler_front(T *tptr, void (T::*mptr)(void), IRQn_Type irq)
- {
- // Underlying call is thread safe
- return add_common(tptr, mptr, irq, true);
- }
-
- /** Remove a handler from an interrupt
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param handler the function object for the handler to remove
- * @param irq the interrupt number
- *
- * @returns
- * true if the handler was found and removed, false otherwise
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
-
-#if !defined(DOXYGEN_ONLY)
-private:
- InterruptManager();
- ~InterruptManager();
-
- void lock();
- void unlock();
-
- template<typename T>
- pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front = false)
- {
- _mutex.lock();
- int irq_pos = get_irq_index(irq);
- bool change = must_replace_vector(irq);
-
- pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
- if (change) {
- NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
- }
- _mutex.unlock();
- return pf;
- }
-
- pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front = false);
- bool must_replace_vector(IRQn_Type irq);
- int get_irq_index(IRQn_Type irq);
- void irq_helper();
- void add_helper(void (*function)(void), IRQn_Type irq, bool front = false);
- static void static_irq_helper();
-
- CallChain *_chains[NVIC_NUM_VECTORS];
- static InterruptManager *_instance;
- PlatformMutex _mutex;
-#endif
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/LowPowerTicker.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,52 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTICKER_H
-#define MBED_LOWPOWERTICKER_H
-
-#include "platform/platform.h"
-#include "drivers/Ticker.h"
-#include "platform/NonCopyable.h"
-
-#if defined (DEVICE_LPTICKER) || defined(DOXYGEN_ONLY)
-
-#include "hal/lp_ticker_api.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** Low Power Ticker
- *
- * @note Synchronization level: Interrupt safe
- * @ingroup drivers
- */
-class LowPowerTicker : public Ticker, private NonCopyable<LowPowerTicker> {
-
-public:
- LowPowerTicker() : Ticker(get_lp_ticker_data())
- {
- }
-
- virtual ~LowPowerTicker()
- {
- }
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/LowPowerTimeout.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,50 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTIMEOUT_H
-#define MBED_LOWPOWERTIMEOUT_H
-
-#include "platform/platform.h"
-
-#if DEVICE_LPTICKER || defined(DOXYGEN_ONLY)
-
-#include "hal/lp_ticker_api.h"
-#include "drivers/LowPowerTicker.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** Low Power Timout
- *
- * @note Synchronization level: Interrupt safe
- * @ingroup drivers
- */
-class LowPowerTimeout : public LowPowerTicker, private NonCopyable<LowPowerTimeout> {
-#if !defined(DOXYGEN_ONLY)
-private:
- virtual void handler(void)
- {
- _function.call();
- }
-#endif
-};
-
-}
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/LowPowerTimer.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTIMER_H
-#define MBED_LOWPOWERTIMER_H
-
-#include "platform/platform.h"
-#include "drivers/Timer.h"
-#include "platform/NonCopyable.h"
-
-#if DEVICE_LPTICKER || defined(DOXYGEN_ONLY)
-
-#include "hal/lp_ticker_api.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** Low power timer
- *
- * @note Synchronization level: Interrupt safe
- * @ingroup drivers
- */
-class LowPowerTimer : public Timer, private NonCopyable<LowPowerTimer> {
-
-public:
- LowPowerTimer() : Timer(get_lp_ticker_data())
- {
- }
-
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/MbedCRC.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,563 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CRC_API_H
-#define MBED_CRC_API_H
-
-#include "drivers/TableCRC.h"
-#include "hal/crc_api.h"
-#include "platform/mbed_assert.h"
-#include "platform/SingletonPtr.h"
-#include "platform/PlatformMutex.h"
-
-/* This is invalid warning from the compiler for below section of code
-if ((width < 8) && (NULL == _crc_table)) {
- p_crc = (uint32_t)(p_crc << (8 - width));
-}
-Compiler warns of the shift operation with width as it is width=(std::uint8_t),
-but we check for ( width < 8) before performing shift, so it should not be an issue.
-*/
-#if defined ( __CC_ARM )
-#pragma diag_suppress 62 // Shift count is negative
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wshift-count-negative"
-#elif defined (__ICCARM__)
-#pragma diag_suppress=Pe062 // Shift count is negative
-#endif
-
-namespace mbed {
-/** \addtogroup drivers */
-/** @{*/
-
-/** CRC object provides CRC generation through hardware/software
- *
- * ROM polynomial tables for supported polynomials (:: crc_polynomial_t) will be used for
- * software CRC computation, if ROM tables are not available then CRC is computed runtime
- * bit by bit for all data input.
- * @note Synchronization level: Thread safe
- *
- * @tparam polynomial CRC polynomial value in hex
- * @tparam width CRC polynomial width
- *
- * Example: Compute CRC data
- * @code
- *
- * #include "mbed.h"
- *
- * int main() {
- * MbedCRC<POLY_32BIT_ANSI, 32> ct;
- *
- * char test[] = "123456789";
- * uint32_t crc = 0;
- *
- * printf("\nPolynomial = 0x%lx Width = %d \n", ct.get_polynomial(), ct.get_width());
- *
- * ct.compute((void *)test, strlen((const char*)test), &crc);
- *
- * printf("The CRC of data \"123456789\" is : 0x%lx\n", crc);
- * return 0;
- * }
- * @endcode
- * Example: Compute CRC with data available in parts
- * @code
- *
- * #include "mbed.h"
- * int main() {
- * MbedCRC<POLY_32BIT_ANSI, 32> ct;
- *
- * char test[] = "123456789";
- * uint32_t crc = 0;
- *
- * printf("\nPolynomial = 0x%lx Width = %d \n", ct.get_polynomial(), ct.get_width());
- * ct.compute_partial_start(&crc);
- * ct.compute_partial((void *)&test, 4, &crc);
- * ct.compute_partial((void *)&test[4], 5, &crc);
- * ct.compute_partial_stop(&crc);
- * printf("The CRC of data \"123456789\" is : 0x%lx\n", crc);
- * return 0;
- * }
- * @endcode
- * @ingroup drivers
- */
-
-extern SingletonPtr<PlatformMutex> mbed_crc_mutex;
-
-template <uint32_t polynomial = POLY_32BIT_ANSI, uint8_t width = 32>
-class MbedCRC {
-
-public:
- enum CrcMode {
-#if DEVICE_CRC
- HARDWARE = 0,
-#endif
- TABLE = 1,
- BITWISE
- };
-
- typedef uint64_t crc_data_size_t;
-
- /** Lifetime of CRC object
- *
- * @param initial_xor Inital value/seed to Xor
- * @param final_xor Final Xor value
- * @param reflect_data
- * @param reflect_remainder
- * @note Default constructor without any arguments is valid only for supported CRC polynomials. :: crc_polynomial_t
- * MbedCRC <POLY_7BIT_SD, 7> ct; --- Valid POLY_7BIT_SD
- * MbedCRC <0x1021, 16> ct; --- Valid POLY_16BIT_CCITT
- * MbedCRC <POLY_16BIT_CCITT, 32> ct; --- Invalid, compilation error
- * MbedCRC <POLY_16BIT_CCITT, 32> ct (i,f,rd,rr) Constructor can be used for not supported polynomials
- * MbedCRC<POLY_16BIT_CCITT, 16> sd(0, 0, false, false); Constructor can also be used for supported
- * polynomials with different intial/final/reflect values
- *
- */
- MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder) :
- _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data),
- _reflect_remainder(reflect_remainder)
- {
- mbed_crc_ctor();
- }
- MbedCRC();
- virtual ~MbedCRC()
- {
- // Do nothing
- }
-
- /** Compute CRC for the data input
- * Compute CRC performs the initialization, computation and collection of
- * final CRC.
- *
- * @param buffer Data bytes
- * @param size Size of data
- * @param crc CRC is the output value
- * @return 0 on success, negative error code on failure
- */
- int32_t compute(void *buffer, crc_data_size_t size, uint32_t *crc)
- {
- MBED_ASSERT(crc != NULL);
- int32_t status = 0;
-
- status = compute_partial_start(crc);
- if (0 != status) {
- unlock();
- return status;
- }
-
- status = compute_partial(buffer, size, crc);
- if (0 != status) {
- unlock();
- return status;
- }
-
- status = compute_partial_stop(crc);
- if (0 != status) {
- *crc = 0;
- }
-
- return status;
-
- }
-
- /** Compute partial CRC for the data input.
- *
- * CRC data if not available fully, CRC can be computed in parts with available data.
- *
- * In case of hardware, intermediate values and states are saved by hardware. Mutex
- * locking is used to serialize access to hardware CRC.
- *
- * In case of software CRC, previous CRC output should be passed as argument to the
- * current compute_partial call. Please note the intermediate CRC value is maintained by
- * application and not the driver.
- *
- * @pre: Call `compute_partial_start` to start the partial CRC calculation.
- * @post: Call `compute_partial_stop` to get the final CRC value.
- *
- * @param buffer Data bytes
- * @param size Size of data
- * @param crc CRC value is intermediate CRC value filled by API.
- * @return 0 on success or a negative error code on failure
- * @note: CRC as output in compute_partial is not final CRC value, call `compute_partial_stop`
- * to get final correct CRC value.
- */
- int32_t compute_partial(void *buffer, crc_data_size_t size, uint32_t *crc)
- {
- int32_t status = 0;
-
- switch (_mode) {
-#if DEVICE_CRC
- case HARDWARE:
- hal_crc_compute_partial((uint8_t *)buffer, size);
- *crc = 0;
- break;
-#endif
- case TABLE:
- status = table_compute_partial(buffer, size, crc);
- break;
- case BITWISE:
- status = bitwise_compute_partial(buffer, size, crc);
- break;
- default:
- status = -1;
- break;
- }
-
- return status;
- }
-
- /** Compute partial start, indicate start of partial computation.
- *
- * This API should be called before performing any partial computation
- * with compute_partial API.
- *
- * @param crc Initial CRC value set by the API
- * @return 0 on success or a negative in case of failure
- * @note: CRC is an out parameter and must be reused with compute_partial
- * and `compute_partial_stop` without any modifications in application.
- */
- int32_t compute_partial_start(uint32_t *crc)
- {
- MBED_ASSERT(crc != NULL);
-
-#if DEVICE_CRC
- if (_mode == HARDWARE) {
- lock();
- crc_mbed_config_t config;
- config.polynomial = polynomial;
- config.width = width;
- config.initial_xor = _initial_value;
- config.final_xor = _final_xor;
- config.reflect_in = _reflect_data;
- config.reflect_out = _reflect_remainder;
-
- hal_crc_compute_partial_start(&config);
- }
-#endif
-
- *crc = _initial_value;
- return 0;
- }
-
- /** Get the final CRC value of partial computation.
- *
- * CRC value available in partial computation is not correct CRC, as some
- * algorithms require remainder to be reflected and final value to be XORed
- * This API is used to perform final computation to get correct CRC value.
- *
- * @param crc CRC result
- * @return 0 on success or a negative in case of failure.
- */
- int32_t compute_partial_stop(uint32_t *crc)
- {
- MBED_ASSERT(crc != NULL);
-
-#if DEVICE_CRC
- if (_mode == HARDWARE) {
- *crc = hal_crc_get_result();
- unlock();
- return 0;
- }
-#endif
- uint32_t p_crc = *crc;
- if ((width < 8) && (NULL == _crc_table)) {
- p_crc = (uint32_t)(p_crc << (8 - width));
- }
- // Optimized algorithm for 32BitANSI does not need additional reflect_remainder
- if ((TABLE == _mode) && (POLY_32BIT_REV_ANSI == polynomial)) {
- *crc = (p_crc ^ _final_xor) & get_crc_mask();
- } else {
- *crc = (reflect_remainder(p_crc) ^ _final_xor) & get_crc_mask();
- }
- unlock();
- return 0;
- }
-
- /** Get the current CRC polynomial.
- *
- * @return Polynomial value
- */
- uint32_t get_polynomial(void) const
- {
- return polynomial;
- }
-
- /** Get the current CRC width
- *
- * @return CRC width
- */
- uint8_t get_width(void) const
- {
- return width;
- }
-
-#if !defined(DOXYGEN_ONLY)
-private:
- uint32_t _initial_value;
- uint32_t _final_xor;
- bool _reflect_data;
- bool _reflect_remainder;
- uint32_t *_crc_table;
- CrcMode _mode;
-
- /** Acquire exclusive access to CRC hardware/software.
- */
- void lock()
- {
-#if DEVICE_CRC
- if (_mode == HARDWARE) {
- mbed_crc_mutex->lock();
- }
-#endif
- }
-
- /** Release exclusive access to CRC hardware/software.
- */
- virtual void unlock()
- {
-#if DEVICE_CRC
- if (_mode == HARDWARE) {
- mbed_crc_mutex->unlock();
- }
-#endif
- }
-
- /** Get the current CRC data size.
- *
- * @return CRC data size in bytes
- */
- uint8_t get_data_size(void) const
- {
- return (width <= 8 ? 1 : (width <= 16 ? 2 : 4));
- }
-
- /** Get the top bit of current CRC.
- *
- * @return Top bit is set high for respective data width of current CRC
- * Top bit for CRC width less then 8 bits will be set as 8th bit.
- */
- uint32_t get_top_bit(void) const
- {
- return (width < 8 ? (1u << 7) : (uint32_t)(1ul << (width - 1)));
- }
-
- /** Get the CRC data mask.
- *
- * @return CRC data mask is generated based on current CRC width
- */
- uint32_t get_crc_mask(void) const
- {
- return (width < 8 ? ((1u << 8) - 1) : (uint32_t)((uint64_t)(1ull << width) - 1));
- }
-
- /** Final value of CRC is reflected.
- *
- * @param data final crc value, which should be reflected
- * @return Reflected CRC value
- */
- uint32_t reflect_remainder(uint32_t data) const
- {
- if (_reflect_remainder) {
- uint32_t reflection = 0x0;
- uint8_t const nBits = (width < 8 ? 8 : width);
-
- for (uint8_t bit = 0; bit < nBits; ++bit) {
- if (data & 0x01) {
- reflection |= (1 << ((nBits - 1) - bit));
- }
- data = (data >> 1);
- }
- return (reflection);
- } else {
- return data;
- }
- }
-
- /** Data bytes are reflected.
- *
- * @param data value to be reflected
- * @return Reflected data value
- */
- uint32_t reflect_bytes(uint32_t data) const
- {
- if (_reflect_data) {
- uint32_t reflection = 0x0;
-
- for (uint8_t bit = 0; bit < 8; ++bit) {
- if (data & 0x01) {
- reflection |= (1 << (7 - bit));
- }
- data = (data >> 1);
- }
- return (reflection);
- } else {
- return data;
- }
- }
-
- /** Bitwise CRC computation.
- *
- * @param buffer data buffer
- * @param size size of the data
- * @param crc CRC value is filled in, but the value is not the final
- * @return 0 on success or a negative error code on failure
- */
- int32_t bitwise_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
- {
- MBED_ASSERT(crc != NULL);
-
- const uint8_t *data = static_cast<const uint8_t *>(buffer);
- uint32_t p_crc = *crc;
-
- if (width < 8) {
- uint8_t data_byte;
- for (crc_data_size_t byte = 0; byte < size; byte++) {
- data_byte = reflect_bytes(data[byte]);
- for (uint8_t bit = 8; bit > 0; --bit) {
- p_crc <<= 1;
- if ((data_byte ^ p_crc) & get_top_bit()) {
- p_crc ^= polynomial;
- }
- data_byte <<= 1;
- }
- }
- } else {
- for (crc_data_size_t byte = 0; byte < size; byte++) {
- p_crc ^= (reflect_bytes(data[byte]) << (width - 8));
-
- // Perform modulo-2 division, a bit at a time
- for (uint8_t bit = 8; bit > 0; --bit) {
- if (p_crc & get_top_bit()) {
- p_crc = (p_crc << 1) ^ polynomial;
- } else {
- p_crc = (p_crc << 1);
- }
- }
- }
- }
- *crc = p_crc & get_crc_mask();
- return 0;
- }
-
- /** CRC computation using ROM tables.
- *
- * @param buffer data buffer
- * @param size size of the data
- * @param crc CRC value is filled in, but the value is not the final
- * @return 0 on success or a negative error code on failure
- */
- int32_t table_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
- {
- MBED_ASSERT(crc != NULL);
-
- const uint8_t *data = static_cast<const uint8_t *>(buffer);
- uint32_t p_crc = *crc;
- uint8_t data_byte = 0;
-
- if (width <= 8) {
- uint8_t *crc_table = (uint8_t *)_crc_table;
- for (crc_data_size_t byte = 0; byte < size; byte++) {
- data_byte = reflect_bytes(data[byte]) ^ p_crc;
- p_crc = crc_table[data_byte];
- }
- } else if (width <= 16) {
- uint16_t *crc_table = (uint16_t *)_crc_table;
- for (crc_data_size_t byte = 0; byte < size; byte++) {
- data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
- p_crc = crc_table[data_byte] ^ (p_crc << 8);
- }
- } else {
- uint32_t *crc_table = (uint32_t *)_crc_table;
- if (POLY_32BIT_REV_ANSI == polynomial) {
- for (crc_data_size_t i = 0; i < size; i++) {
- p_crc = (p_crc >> 4) ^ crc_table[(p_crc ^ (data[i] >> 0)) & 0xf];
- p_crc = (p_crc >> 4) ^ crc_table[(p_crc ^ (data[i] >> 4)) & 0xf];
- }
- } else {
- for (crc_data_size_t byte = 0; byte < size; byte++) {
- data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
- p_crc = crc_table[data_byte] ^ (p_crc << 8);
- }
- }
- }
- *crc = p_crc & get_crc_mask();
- return 0;
- }
-
- /** Constructor init called from all specialized cases of constructor.
- * Note: All constructor common code should be in this function.
- */
- void mbed_crc_ctor(void)
- {
- MBED_STATIC_ASSERT(width <= 32, "Max 32-bit CRC supported");
-
-#if DEVICE_CRC
- if (POLY_32BIT_REV_ANSI == polynomial) {
- _crc_table = (uint32_t *)Table_CRC_32bit_Rev_ANSI;
- _mode = TABLE;
- return;
- }
- crc_mbed_config_t config;
- config.polynomial = polynomial;
- config.width = width;
- config.initial_xor = _initial_value;
- config.final_xor = _final_xor;
- config.reflect_in = _reflect_data;
- config.reflect_out = _reflect_remainder;
-
- if (hal_crc_is_supported(&config)) {
- _mode = HARDWARE;
- return;
- }
-#endif
-
- switch (polynomial) {
- case POLY_32BIT_ANSI:
- _crc_table = (uint32_t *)Table_CRC_32bit_ANSI;
- break;
- case POLY_32BIT_REV_ANSI:
- _crc_table = (uint32_t *)Table_CRC_32bit_Rev_ANSI;
- break;
- case POLY_8BIT_CCITT:
- _crc_table = (uint32_t *)Table_CRC_8bit_CCITT;
- break;
- case POLY_7BIT_SD:
- _crc_table = (uint32_t *)Table_CRC_7Bit_SD;
- break;
- case POLY_16BIT_CCITT:
- _crc_table = (uint32_t *)Table_CRC_16bit_CCITT;
- break;
- case POLY_16BIT_IBM:
- _crc_table = (uint32_t *)Table_CRC_16bit_IBM;
- break;
- default:
- _crc_table = NULL;
- break;
- }
- _mode = (_crc_table != NULL) ? TABLE : BITWISE;
- }
-#endif
-};
-
-#if defined ( __CC_ARM )
-#elif defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#elif defined (__ICCARM__)
-#endif
-
-/** @}*/
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/PortIn.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,107 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTIN_H
-#define MBED_PORTIN_H
-
-#include "platform/platform.h"
-
-#if DEVICE_PORTIN || defined(DOXYGEN_ONLY)
-
-#include "hal/port_api.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A multiple pin digital input
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Turn on an LED if any pins of Port2[0:5] are high
- *
- * #include "mbed.h"
- *
- * PortIn p(Port2, 0x0000003F); // Port2 pins [0:5] only
- * DigitalOut led(LED4);
- *
- * int main() {
- * while(1) {
- * int pins = p.read();
- * if(pins) {
- * led = 1;
- * } else {
- * led = 0;
- * }
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class PortIn {
-public:
-
- /** Create a PortIn, connected to the specified port
- *
- * @param port Port to connect to (as defined in target's PortNames.h)
- * @param mask Bitmask defines which port pins should be an input (0 - ignore, 1 - include)
- */
- PortIn(PortName port, int mask = 0xFFFFFFFF)
- {
- core_util_critical_section_enter();
- port_init(&_port, port, mask, PIN_INPUT);
- core_util_critical_section_exit();
- }
-
- /** Read the value input to the port
- *
- * @returns
- * An integer with each bit corresponding to the associated pin value
- */
- int read()
- {
- return port_read(&_port);
- }
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode mode)
- {
- core_util_critical_section_enter();
- port_mode(&_port, mode);
- core_util_critical_section_exit();
- }
-
- /** A shorthand for read()
- */
- operator int()
- {
- return read();
- }
-
-private:
- port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/PortInOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,132 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTINOUT_H
-#define MBED_PORTINOUT_H
-
-#include "platform/platform.h"
-
-#if DEVICE_PORTINOUT || defined(DOXYGEN_ONLY)
-
-#include "hal/port_api.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A multiple pin digital in/out used to set/read multiple bi-directional pins
- *
- * @note Synchronization level: Interrupt safe
- * @ingroup drivers
- */
-class PortInOut {
-public:
-
- /** Create an PortInOut, connected to the specified port
- *
- * @param port Port to connect to (Port0-Port5)
- * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
- */
- PortInOut(PortName port, int mask = 0xFFFFFFFF)
- {
- core_util_critical_section_enter();
- port_init(&_port, port, mask, PIN_INPUT);
- core_util_critical_section_exit();
- }
-
- /** Write the value to the output port
- *
- * @param value An integer specifying a bit to write for every corresponding port pin
- */
- void write(int value)
- {
- port_write(&_port, value);
- }
-
- /** Read the value currently output on the port
- *
- * @returns
- * An integer with each bit corresponding to associated port pin setting
- */
- int read()
- {
- return port_read(&_port);
- }
-
- /** Set as an output
- */
- void output()
- {
- core_util_critical_section_enter();
- port_dir(&_port, PIN_OUTPUT);
- core_util_critical_section_exit();
- }
-
- /** Set as an input
- */
- void input()
- {
- core_util_critical_section_enter();
- port_dir(&_port, PIN_INPUT);
- core_util_critical_section_exit();
- }
-
- /** Set the input pin mode
- *
- * @param mode PullUp, PullDown, PullNone, OpenDrain
- */
- void mode(PinMode mode)
- {
- core_util_critical_section_enter();
- port_mode(&_port, mode);
- core_util_critical_section_exit();
- }
-
- /** A shorthand for write()
- * \sa PortInOut::write()
- */
- PortInOut &operator= (int value)
- {
- write(value);
- return *this;
- }
-
- /** A shorthand for write()
- * \sa PortInOut::write()
- */
- PortInOut &operator= (PortInOut &rhs)
- {
- write(rhs.read());
- return *this;
- }
-
- /** A shorthand for read()
- * \sa PortInOut::read()
- */
- operator int()
- {
- return read();
- }
-
-private:
- port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/PortOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTOUT_H
-#define MBED_PORTOUT_H
-
-#include "platform/platform.h"
-
-#if DEVICE_PORTOUT || defined(DOXYGEN_ONLY)
-
-#include "hal/port_api.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-/** A multiple pin digital output
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Toggle all four LEDs
- *
- * #include "mbed.h"
- *
- * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23
- * #define LED_MASK 0x00B40000
- *
- * PortOut ledport(Port1, LED_MASK);
- *
- * int main() {
- * while(1) {
- * ledport = LED_MASK;
- * wait(1);
- * ledport = 0;
- * wait(1);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class PortOut {
-public:
-
- /** Create a PortOut, connected to the specified port
- *
- * @param port Port to connect to (as defined in target's PortNames.h)
- * @param mask Bitmask defines which port pins are an output (0 - ignore, 1 - include)
- */
- PortOut(PortName port, int mask = 0xFFFFFFFF)
- {
- core_util_critical_section_enter();
- port_init(&_port, port, mask, PIN_OUTPUT);
- core_util_critical_section_exit();
- }
-
- /** Write the value to the output port
- *
- * @param value An integer specifying a bit to write for every corresponding PortOut pin
- */
- void write(int value)
- {
- port_write(&_port, value);
- }
-
- /** Read the value currently output on the port
- *
- * @returns
- * An integer with each bit corresponding to associated pin value
- */
- int read()
- {
- return port_read(&_port);
- }
-
- /** A shorthand for write()
- * \sa PortOut::write()
- */
- PortOut &operator= (int value)
- {
- write(value);
- return *this;
- }
-
- /** A shorthand for read()
- * \sa PortOut::read()
- */
- PortOut &operator= (PortOut &rhs)
- {
- write(rhs.read());
- return *this;
- }
-
- /** A shorthand for read()
- * \sa PortOut::read()
- */
- operator int()
- {
- return read();
- }
-
-private:
- port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/PwmOut.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,230 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_H
-#define MBED_PWMOUT_H
-
-#include "platform/platform.h"
-
-#if DEVICE_PWMOUT || defined(DOXYGEN_ONLY)
-#include "hal/pwmout_api.h"
-#include "platform/mbed_critical.h"
-#include "platform/mbed_power_mgmt.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A pulse-width modulation digital output
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example
- * @code
- * // Gradually change the intensity of the LED.
- * #include "mbed.h"
- *
- * PwmOut led(LED1);
- *
- * int main() {
- * while(1) {
- * led = led + 0.01;
- * wait(0.2);
- * if(led == 1.0) {
- * led = 0;
- * }
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class PwmOut {
-
-public:
-
- /** Create a PwmOut connected to the specified pin
- *
- * @param pin PwmOut pin to connect to
- */
- PwmOut(PinName pin) : _deep_sleep_locked(false)
- {
- core_util_critical_section_enter();
- pwmout_init(&_pwm, pin);
- core_util_critical_section_exit();
- }
-
- ~PwmOut()
- {
- core_util_critical_section_enter();
- unlock_deep_sleep();
- core_util_critical_section_exit();
- }
-
- /** Set the output duty-cycle, specified as a percentage (float)
- *
- * @param value A floating-point value representing the output duty-cycle,
- * specified as a percentage. The value should lie between
- * 0.0f (representing on 0%) and 1.0f (representing on 100%).
- * Values outside this range will be saturated to 0.0f or 1.0f.
- */
- void write(float value)
- {
- core_util_critical_section_enter();
- lock_deep_sleep();
- pwmout_write(&_pwm, value);
- core_util_critical_section_exit();
- }
-
- /** Return the current output duty-cycle setting, measured as a percentage (float)
- *
- * @returns
- * A floating-point value representing the current duty-cycle being output on the pin,
- * measured as a percentage. The returned value will lie between
- * 0.0f (representing on 0%) and 1.0f (representing on 100%).
- *
- * @note
- * This value may not match exactly the value set by a previous write().
- */
- float read()
- {
- core_util_critical_section_enter();
- float val = pwmout_read(&_pwm);
- core_util_critical_section_exit();
- return val;
- }
-
- /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
- *
- * @param seconds Change the period of a PWM signal in seconds (float) without modifying the duty cycle
- * @note
- * The resolution is currently in microseconds; periods smaller than this
- * will be set to zero.
- */
- void period(float seconds)
- {
- core_util_critical_section_enter();
- pwmout_period(&_pwm, seconds);
- core_util_critical_section_exit();
- }
-
- /** Set the PWM period, specified in milliseconds (int), keeping the duty cycle the same.
- * @param ms Change the period of a PWM signal in milliseconds without modifying the duty cycle
- */
- void period_ms(int ms)
- {
- core_util_critical_section_enter();
- pwmout_period_ms(&_pwm, ms);
- core_util_critical_section_exit();
- }
-
- /** Set the PWM period, specified in microseconds (int), keeping the duty cycle the same.
- * @param us Change the period of a PWM signal in microseconds without modifying the duty cycle
- */
- void period_us(int us)
- {
- core_util_critical_section_enter();
- pwmout_period_us(&_pwm, us);
- core_util_critical_section_exit();
- }
-
- /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
- * @param seconds Change the pulse width of a PWM signal specified in seconds (float)
- */
- void pulsewidth(float seconds)
- {
- core_util_critical_section_enter();
- pwmout_pulsewidth(&_pwm, seconds);
- core_util_critical_section_exit();
- }
-
- /** Set the PWM pulsewidth, specified in milliseconds (int), keeping the period the same.
- * @param ms Change the pulse width of a PWM signal specified in milliseconds
- */
- void pulsewidth_ms(int ms)
- {
- core_util_critical_section_enter();
- pwmout_pulsewidth_ms(&_pwm, ms);
- core_util_critical_section_exit();
- }
-
- /** Set the PWM pulsewidth, specified in microseconds (int), keeping the period the same.
- * @param us Change the pulse width of a PWM signal specified in microseconds
- */
- void pulsewidth_us(int us)
- {
- core_util_critical_section_enter();
- pwmout_pulsewidth_us(&_pwm, us);
- core_util_critical_section_exit();
- }
-
- /** A operator shorthand for write()
- * \sa PwmOut::write()
- */
- PwmOut &operator= (float value)
- {
- // Underlying call is thread safe
- write(value);
- return *this;
- }
-
- /** A operator shorthand for write()
- * \sa PwmOut::write()
- */
- PwmOut &operator= (PwmOut &rhs)
- {
- // Underlying call is thread safe
- write(rhs.read());
- return *this;
- }
-
- /** An operator shorthand for read()
- * \sa PwmOut::read()
- */
- operator float()
- {
- // Underlying call is thread safe
- return read();
- }
-
-#if !(DOXYGEN_ONLY)
-protected:
- /** Lock deep sleep only if it is not yet locked */
- void lock_deep_sleep()
- {
- if (_deep_sleep_locked == false) {
- sleep_manager_lock_deep_sleep();
- _deep_sleep_locked = true;
- }
- }
-
- /** Unlock deep sleep in case it is locked */
- void unlock_deep_sleep()
- {
- if (_deep_sleep_locked == true) {
- sleep_manager_unlock_deep_sleep();
- _deep_sleep_locked = false;
- }
- }
-
- pwmout_t _pwm;
- bool _deep_sleep_locked;
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/QSPI.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,232 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_QSPI_H
-#define MBED_QSPI_H
-
-#include "platform/platform.h"
-
-#if DEVICE_QSPI || defined(DOXYGEN_ONLY)
-
-#include "hal/qspi_api.h"
-#include "platform/PlatformMutex.h"
-#include "platform/SingletonPtr.h"
-#include "platform/NonCopyable.h"
-
-#define ONE_MHZ 1000000
-
-namespace mbed {
-
-/** \addtogroup drivers */
-
-/** A QSPI Driver, used for communicating with QSPI slave devices
- *
- * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
- * Most QSPI devices will also require Chip Select which is indicated by ssel.
- *
- * @note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
- *
- * #include "mbed.h"
- *
- * #define CMD_WRITE 0x02
- * #define CMD_READ 0x03
- * #define ADDRESS 0x1000
- *
- * // hardware ssel (where applicable)
- * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
- *
- *
- * int main() {
- * char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
- * char rx_buf[4];
- * int buf_len = sizeof(tx_buf);
- *
- * qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
- * if (result != QSPI_STATUS_OK) {
- * printf("Write failed");
- * }
- * result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
- * if (result != QSPI_STATUS_OK) {
- * printf("Read failed");
- * }
- *
- * }
- * @endcode
- * @ingroup drivers
- */
-class QSPI : private NonCopyable<QSPI> {
-
-public:
-
- /** Create a QSPI master connected to the specified pins
- *
- * io0-io3 is used to specify the Pins used for Quad SPI mode
- *
- * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
- * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
- * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
- * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
- * @param sclk QSPI Clock pin
- * @param ssel QSPI chip select pin
- * @param mode Clock polarity and phase mode (0 - 3) of SPI
- * (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
- *
- */
- QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
- virtual ~QSPI()
- {
- }
-
- /** Configure the data transmission format
- *
- * @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
- * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
- * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
- * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
- * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
- * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
- * @param dummy_cycles Number of dummy clock cycles to be used after alt phase
- *
- */
- qspi_status_t configure_format(qspi_bus_width_t inst_width,
- qspi_bus_width_t address_width,
- qspi_address_size_t address_size,
- qspi_bus_width_t alt_width,
- qspi_alt_size_t alt_size,
- qspi_bus_width_t data_width,
- int dummy_cycles);
-
- /** Set the qspi bus clock frequency
- *
- * @param hz SCLK frequency in hz (default = 1MHz)
- * @returns
- * Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
- */
- qspi_status_t set_frequency(int hz = ONE_MHZ);
-
- /** Read from QSPI peripheral with the preset read_instruction and alt_value
- *
- * @param address Address to be accessed in QSPI peripheral
- * @param rx_buffer Buffer for data to be read from the peripheral
- * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
- *
- * @returns
- * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
- */
- qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
-
- /** Write to QSPI peripheral using custom write instruction
- *
- * @param address Address to be accessed in QSPI peripheral
- * @param tx_buffer Buffer containing data to be sent to peripheral
- * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
- *
- * @returns
- * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
- */
- qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
-
- /** Read from QSPI peripheral using custom read instruction, alt values
- *
- * @param instruction Instruction value to be used in instruction phase
- * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
- * @param address Address to be accessed in QSPI peripheral
- * @param rx_buffer Buffer for data to be read from the peripheral
- * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
- *
- * @returns
- * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
- */
- qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
-
- /** Write to QSPI peripheral using custom write instruction, alt values
- *
- * @param instruction Instruction value to be used in instruction phase
- * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
- * @param address Address to be accessed in QSPI peripheral
- * @param tx_buffer Buffer containing data to be sent to peripheral
- * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
- *
- * @returns
- * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
- */
- qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
-
- /** Perform a transaction to write to an address(a control register) and get the status results
- *
- * @param instruction Instruction value to be used in instruction phase
- * @param address Some instruction might require address. Use -1 if no address
- * @param tx_buffer Buffer containing data to be sent to peripheral
- * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
- * @param rx_buffer Buffer for data to be read from the peripheral
- * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
- *
- * @returns
- * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
- */
- qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- /** Acquire exclusive access to this SPI bus
- */
- virtual void lock(void);
-
- /** Release exclusive access to this SPI bus
- */
- virtual void unlock(void);
-
- qspi_t _qspi;
-
- bool acquire(void);
- static QSPI *_owner;
- static SingletonPtr<PlatformMutex> _mutex;
- qspi_bus_width_t _inst_width; //Bus width for Instruction phase
- qspi_bus_width_t _address_width; //Bus width for Address phase
- qspi_address_size_t _address_size;
- qspi_bus_width_t _alt_width; //Bus width for Alt phase
- qspi_alt_size_t _alt_size;
- qspi_bus_width_t _data_width; //Bus width for Data phase
- qspi_command_t _qspi_command; //QSPI Hal command struct
- unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
- int _hz; //Bus Frequency
- int _mode; //SPI mode
- bool _initialized;
- PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
-
-private:
- /* Private acquire function without locking/unlocking
- * Implemented in order to avoid duplicate locking and boost performance
- */
- bool _acquire(void);
- bool _initialize();
-
- /*
- * This function builds the qspi command struct to be send to Hal
- */
- inline void _build_qspi_command(int instruction, int address, int alt);
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/RawSerial.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RAW_SERIAL_H
-#define MBED_RAW_SERIAL_H
-
-#include "platform/platform.h"
-
-#if DEVICE_SERIAL || defined(DOXYGEN_ONLY)
-
-#include "mbed_toolchain.h"
-#include "drivers/SerialBase.h"
-#include "hal/serial_api.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A serial port (UART) for communication with other serial devices
- * This is a variation of the Serial class that doesn't use streams,
- * thus making it safe to use in interrupt handlers with the RTOS.
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * @note Synchronization level: Not protected
- *
- * Example:
- * @code
- * // Send a char to the PC
- *
- * #include "mbed.h"
- *
- * RawSerial pc(USBTX, USBRX);
- *
- * int main() {
- * pc.putc('A');
- * }
- * @endcode
- * @ingroup drivers
- */
-class RawSerial: public SerialBase, private NonCopyable<RawSerial> {
-
-public:
- /** Create a RawSerial port, connected to the specified transmit and receive pins, with the specified baud.
- *
- * @param tx Transmit pin
- * @param rx Receive pin
- * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
- *
- * @note
- * Either tx or rx may be specified as NC if unused
- */
- RawSerial(PinName tx, PinName rx, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
-
- /** Write a char to the serial port
- *
- * @param c The char to write
- *
- * @returns The written char or -1 if an error occurred
- */
- int putc(int c);
-
- /** Read a char from the serial port
- *
- * @returns The char read from the serial port
- */
- int getc();
-
- /** Write a string to the serial port
- *
- * @param str The string to write
- *
- * @returns 0 if the write succeeds, EOF for error
- */
- int puts(const char *str);
-
- int printf(const char *format, ...) MBED_PRINTF_METHOD(1, 2);
-
-#if !(DOXYGEN_ONLY)
-protected:
-
- /* Acquire exclusive access to this serial port
- */
- virtual void lock(void);
-
- /* Release exclusive access to this serial port
- */
- virtual void unlock(void);
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/SPI.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,340 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_H
-#define MBED_SPI_H
-
-#include "platform/platform.h"
-
-#if DEVICE_SPI || defined(DOXYGEN_ONLY)
-
-#include "platform/PlatformMutex.h"
-#include "hal/spi_api.h"
-#include "platform/SingletonPtr.h"
-#include "platform/NonCopyable.h"
-
-#if DEVICE_SPI_ASYNCH
-#include "platform/CThunk.h"
-#include "hal/dma_api.h"
-#include "platform/CircularBuffer.h"
-#include "platform/FunctionPointer.h"
-#include "platform/Transaction.h"
-#endif
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A SPI Master, used for communicating with SPI slave devices.
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz.
- *
- * Most SPI devices will also require Chip Select and Reset signals. These
- * can be controlled using DigitalOut pins.
- *
- * @note Synchronization level: Thread safe
- *
- * Example of how to send a byte to a SPI slave and record the response:
- * @code
- * #include "mbed.h"
- *
- * SPI device(SPI_MOSI, SPI_MISO, SPI_SCLK)
- *
- * DigitalOut chip_select(SPI_CS);
- *
- * int main() {
- * device.lock();
- * chip_select = 0;
- *
- * int response = device.write(0xFF);
- *
- * chip_select = 1;
- * device.unlock();
- * }
- * @endcode
- *
- * Example using hardware Chip Select line:
- * @code
- * #include "mbed.h"
- *
- * SPI device(SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS)
- *
- * int main() {
- * device.lock();
- * int response = device.write(0xFF);
- * device.unlock();
- * }
- * @endcode
- * @ingroup drivers
- */
-class SPI : private NonCopyable<SPI> {
-
-public:
-
- /** Create a SPI master connected to the specified pins.
- *
- * @note You can specify mosi or miso as NC if not used.
- *
- * @param mosi SPI Master Out, Slave In pin.
- * @param miso SPI Master In, Slave Out pin.
- * @param sclk SPI Clock pin.
- * @param ssel SPI Chip Select pin.
- */
- SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel = NC);
- virtual ~SPI();
-
- /** Configure the data transmission format.
- *
- * @param bits Number of bits per SPI frame (4 - 16).
- * @param mode Clock polarity and phase mode (0 - 3).
- *
- * @code
- * mode | POL PHA
- * -----+--------
- * 0 | 0 0
- * 1 | 0 1
- * 2 | 1 0
- * 3 | 1 1
- * @endcode
- */
- void format(int bits, int mode = 0);
-
- /** Set the SPI bus clock frequency.
- *
- * @param hz Clock frequency in Hz (default = 1MHz).
- */
- void frequency(int hz = 1000000);
-
- /** Write to the SPI Slave and return the response.
- *
- * @param value Data to be sent to the SPI slave.
- *
- * @return Response from the SPI slave.
- */
- virtual int write(int value);
-
- /** Write to the SPI Slave and obtain the response.
- *
- * The total number of bytes sent and received will be the maximum of
- * tx_length and rx_length. The bytes written will be padded with the
- * value 0xff.
- *
- * @param tx_buffer Pointer to the byte-array of data to write to the device.
- * @param tx_length Number of bytes to write, may be zero.
- * @param rx_buffer Pointer to the byte-array of data to read from the device.
- * @param rx_length Number of bytes to read, may be zero.
- * @return
- * The number of bytes written and read from the device. This is
- * maximum of tx_length and rx_length.
- */
- virtual int write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length);
-
- /** Acquire exclusive access to this SPI bus.
- */
- virtual void lock(void);
-
- /** Release exclusive access to this SPI bus.
- */
- virtual void unlock(void);
-
- /** Set default write data.
- * SPI requires the master to send some data during a read operation.
- * Different devices may require different default byte values.
- * For example: A SD Card requires default bytes to be 0xFF.
- *
- * @param data Default character to be transmitted during a read operation.
- */
- void set_default_write_value(char data);
-
-#if DEVICE_SPI_ASYNCH
-
- /** Start non-blocking SPI transfer using 8bit buffers.
- *
- * This function locks the deep sleep until any event has occurred.
- *
- * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
- * the default SPI value is sent.
- * @param tx_length The length of TX buffer in bytes.
- * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored.
- * @param rx_length The length of RX buffer in bytes.
- * @param callback The event callback function.
- * @param event The event mask of events to modify. @see spi_api.h for SPI events.
- *
- * @return Operation result.
- * @retval 0 If the transfer has started.
- * @retval -1 If SPI peripheral is busy.
- */
- template<typename Type>
- int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t &callback, int event = SPI_EVENT_COMPLETE)
- {
- if (spi_active(&_spi)) {
- return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type) * 8, callback, event);
- }
- start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type) * 8, callback, event);
- return 0;
- }
-
- /** Abort the on-going SPI transfer, and continue with transfers in the queue, if any.
- */
- void abort_transfer();
-
- /** Clear the queue of transfers.
- */
- void clear_transfer_buffer();
-
- /** Clear the queue of transfers and abort the on-going transfer.
- */
- void abort_all_transfers();
-
- /** Configure DMA usage suggestion for non-blocking transfers.
- *
- * @param usage The usage DMA hint for peripheral.
- *
- * @return Result of the operation.
- * @retval 0 The usage was set.
- * @retval -1 Usage cannot be set as there is an ongoing transaction.
- */
- int set_dma_usage(DMAUsage usage);
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- /** SPI interrupt handler.
- */
- void irq_handler_asynch(void);
-
- /** Start the transfer or put it on the queue.
- *
- * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
- * the default SPI value is sent
- * @param tx_length The length of TX buffer in bytes.
- * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored.
- * @param rx_length The length of RX buffer in bytes.
- * @param bit_width The buffers element width in bits.
- * @param callback The event callback function.
- * @param event The event mask of events to modify.
- *
- * @return Operation success.
- * @retval 0 A transfer was started or added to the queue.
- * @retval -1 Transfer can't be added because queue is full.
- */
- int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
-
- /** Put a transfer on the transfer queue.
- *
- * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
- * the default SPI value is sent.
- * @param tx_length The length of TX buffer in bytes.
- * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored.
- * @param rx_length The length of RX buffer in bytes.
- * @param bit_width The buffers element width in bits.
- * @param callback The event callback function.
- * @param event The event mask of events to modify.
- *
- * @return Operation success.
- * @retval 0 A transfer was added to the queue.
- * @retval -1 Transfer can't be added because queue is full.
- */
- int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
-
- /** Configure a callback, SPI peripheral, and initiate a new transfer.
- *
- * @param tx_buffer The TX buffer with data to be transferred. If NULL is passed,
- * the default SPI value is sent.
- * @param tx_length The length of TX buffer in bytes.
- * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
- * received data are ignored.
- * @param rx_length The length of RX buffer in bytes.
- * @param bit_width The buffers element width.
- * @param callback The event callback function.
- * @param event The event mask of events to modify.
- */
- void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t &callback, int event);
-
-private:
- /** Lock deep sleep only if it is not yet locked */
- void lock_deep_sleep();
-
- /** Unlock deep sleep in case it is locked */
- void unlock_deep_sleep();
-
-
-#if TRANSACTION_QUEUE_SIZE_SPI
-
- /** Start a new transaction.
- *
- * @param data Transaction data.
- */
- void start_transaction(transaction_t *data);
-
- /** Dequeue a transaction and start the transfer if there was one pending.
- */
- void dequeue_transaction();
-
- /* Queue of pending transfers */
- static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
-#endif
-
-#endif //!defined(DOXYGEN_ONLY)
-
-#endif //DEVICE_SPI_ASYNCH
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- /* Internal SPI object identifying the resources */
- spi_t _spi;
-
-#if DEVICE_SPI_ASYNCH
- /* Interrupt */
- CThunk<SPI> _irq;
- /* Interrupt handler callback */
- event_callback_t _callback;
- /* Current preferred DMA mode @see dma_api.h */
- DMAUsage _usage;
- /* Current sate of the sleep manager */
- bool _deep_sleep_locked;
-#endif
-
- /* Take over the physical SPI and apply our settings (thread safe) */
- void aquire(void);
- /* Current user of the SPI */
- static SPI *_owner;
- /* Used by lock and unlock for thread safety */
- static SingletonPtr<PlatformMutex> _mutex;
- /* Size of the SPI frame */
- int _bits;
- /* Clock polairy and phase */
- int _mode;
- /* Clock frequency */
- int _hz;
- /* Default character used for NULL transfers */
- char _write_fill;
-
-private:
- /** Private acquire function without locking/unlocking.
- * Implemented in order to avoid duplicate locking and boost performance.
- */
- void _acquire(void);
-
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/SPISlave.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,134 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPISLAVE_H
-#define MBED_SPISLAVE_H
-
-#include "platform/platform.h"
-#include "platform/NonCopyable.h"
-
-#if DEVICE_SPISLAVE || defined(DOXYGEN_ONLY)
-
-#include "hal/spi_api.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A SPI slave, used for communicating with a SPI master device.
- *
- * The default format is set to 8 bits, mode 0 and a clock frequency of 1MHz.
- *
- * @note Synchronization level: Not protected
- *
- * Example of how to reply to a SPI master as slave:
- * @code
- *
- * #include "mbed.h"
- *
- * SPISlave device(SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS);
- *
- * int main() {
- * device.reply(0x00); // Prime SPI with first reply
- * while(1) {
- * if(device.receive()) {
- * int v = device.read(); // Read byte from master
- * v = (v + 1) % 0x100; // Add one to it, modulo 256
- * device.reply(v); // Make this the next reply
- * }
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class SPISlave : private NonCopyable<SPISlave> {
-
-public:
-
- /** Create a SPI slave connected to the specified pins.
- *
- * @note Either mosi or miso can be specified as NC if not used.
- *
- * @param mosi SPI Master Out, Slave In pin.
- * @param miso SPI Master In, Slave Out pin.
- * @param sclk SPI Clock pin.
- * @param ssel SPI Chip Select pin.
- */
- SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
- /** Configure the data transmission format.
- *
- * @param bits Number of bits per SPI frame (4 - 16).
- * @param mode Clock polarity and phase mode (0 - 3).
- *
- * @code
- * mode | POL PHA
- * -----+--------
- * 0 | 0 0
- * 1 | 0 1
- * 2 | 1 0
- * 3 | 1 1
- * @endcode
- */
- void format(int bits, int mode = 0);
-
- /** Set the SPI bus clock frequency.
- *
- * @param hz Clock frequency in hz (default = 1MHz).
- */
- void frequency(int hz = 1000000);
-
- /** Polls the SPI to see if data has been received.
- *
- * @return Presence of received data.
- * @retval 0 No data waiting.
- * @retval 1 Data waiting.
- */
- int receive(void);
-
- /** Retrieve data from receive buffer as slave.
- *
- * @return The data in the receive buffer.
- */
- int read(void);
-
- /** Fill the transmission buffer with the value to be written out
- * as slave on the next received message from the master.
- *
- * @param value The data to be transmitted next.
- */
- void reply(int value);
-
-#if !defined(DOXYGEN_ONLY)
-
-protected:
- /* Internal SPI object identifying the resources */
- spi_t _spi;
-
- /* How many bits in an SPI frame */
- int _bits;
- /* Clock phase and polarity */
- int _mode;
- /* Clock frequency */
- int _hz;
-
-#endif //!defined(DOXYGEN_ONLY)
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/Serial.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,118 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_H
-#define MBED_SERIAL_H
-
-#include "platform/platform.h"
-
-#if DEVICE_SERIAL || defined(DOXYGEN_ONLY)
-
-#include "platform/Stream.h"
-#include "SerialBase.h"
-#include "platform/PlatformMutex.h"
-#include "hal/serial_api.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A serial port (UART) for communication with other serial devices
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * @note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * // Print "Hello World" to the PC
- *
- * #include "mbed.h"
- *
- * Serial pc(USBTX, USBRX);
- *
- * int main() {
- * pc.printf("Hello World\n");
- * }
- * @endcode
- * @ingroup drivers
- */
-class Serial : public SerialBase, public Stream, private NonCopyable<Serial> {
-
-public:
-#if DEVICE_SERIAL_ASYNCH
- using SerialBase::read;
- using SerialBase::write;
-#endif
-
- /** Create a Serial port, connected to the specified transmit and receive pins
- *
- * @param tx Transmit pin
- * @param rx Receive pin
- * @param name The name of the stream associated with this serial port (optional)
- * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE or 9600)
- *
- * @note
- * Either tx or rx may be specified as NC (Not Connected) if unused
- */
- Serial(PinName tx, PinName rx, const char *name = NULL, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
-
-
- /** Create a Serial port, connected to the specified transmit and receive pins, with the specified baud
- *
- * @param tx Transmit pin
- * @param rx Receive pin
- * @param baud The baud rate of the serial port
- *
- * @note
- * Either tx or rx may be specified as NC (Not Connected) if unused
- */
- Serial(PinName tx, PinName rx, int baud);
-
- /* Stream gives us a FileHandle with non-functional poll()/readable()/writable. Pass through
- * the calls from the SerialBase instead for backwards compatibility. This problem is
- * part of why Stream and Serial should be deprecated.
- */
- bool readable()
- {
- return SerialBase::readable();
- }
- bool writable()
- {
- return SerialBase::writeable();
- }
- bool writeable()
- {
- return SerialBase::writeable();
- }
-
-#if !(DOXYGEN_ONLY)
-protected:
- virtual int _getc();
- virtual int _putc(int c);
- virtual void lock();
- virtual void unlock();
-
- PlatformMutex _mutex;
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/SerialBase.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,284 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIALBASE_H
-#define MBED_SERIALBASE_H
-
-#include "platform/platform.h"
-
-#if DEVICE_SERIAL || defined(DOXYGEN_ONLY)
-
-#include "platform/Callback.h"
-#include "hal/serial_api.h"
-#include "platform/mbed_toolchain.h"
-#include "platform/NonCopyable.h"
-
-#if DEVICE_SERIAL_ASYNCH
-#include "platform/CThunk.h"
-#include "hal/dma_api.h"
-#endif
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A base class for serial port implementations
- * Can't be instantiated directly (use Serial or RawSerial)
- *
- * @note Synchronization level: Set by subclass
- * @ingroup drivers
- */
-class SerialBase : private NonCopyable<SerialBase> {
-
-public:
- /** Set the baud rate of the serial port
- *
- * @param baudrate The baudrate of the serial port (default = 9600).
- */
- void baud(int baudrate);
-
- enum Parity {
- None = 0,
- Odd,
- Even,
- Forced1,
- Forced0
- };
-
- enum IrqType {
- RxIrq = 0,
- TxIrq,
-
- IrqCnt
- };
-
- enum Flow {
- Disabled = 0,
- RTS,
- CTS,
- RTSCTS
- };
-
- /** Set the transmission format used by the serial port
- *
- * @param bits The number of bits in a word (5-8; default = 8)
- * @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
- * @param stop_bits The number of stop bits (1 or 2; default = 1)
- */
- void format(int bits = 8, Parity parity = SerialBase::None, int stop_bits = 1);
-
- /** Determine if there is a character available to read
- *
- * @returns
- * 1 if there is a character available to read,
- * 0 otherwise
- */
- int readable();
-
- /** Determine if there is space available to write a character
- *
- * @returns
- * 1 if there is space to write a character,
- * 0 otherwise
- */
- int writeable();
-
- /** Attach a function to call whenever a serial interrupt is generated
- *
- * @param func A pointer to a void function, or 0 to set as none
- * @param type Which serial interrupt to attach the member function to (Serial::RxIrq for receive, TxIrq for transmit buffer empty)
- */
- void attach(Callback<void()> func, IrqType type = RxIrq);
-
- /** Attach a member function to call whenever a serial interrupt is generated
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Serial::RxIrq for receive, TxIrq for transmit buffer empty)
- * @deprecated
- * The attach function does not support cv-qualifiers. Replaced by
- * attach(callback(obj, method), type).
- */
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The attach function does not support cv-qualifiers. Replaced by "
- "attach(callback(obj, method), type).")
- void attach(T *obj, void (T::*method)(), IrqType type = RxIrq)
- {
- attach(callback(obj, method), type);
- }
-
- /** Attach a member function to call whenever a serial interrupt is generated
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @param type Which serial interrupt to attach the member function to (Serial::RxIrq for receive, TxIrq for transmit buffer empty)
- * @deprecated
- * The attach function does not support cv-qualifiers. Replaced by
- * attach(callback(obj, method), type).
- */
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The attach function does not support cv-qualifiers. Replaced by "
- "attach(callback(obj, method), type).")
- void attach(T *obj, void (*method)(T *), IrqType type = RxIrq)
- {
- attach(callback(obj, method), type);
- }
-
- /** Generate a break condition on the serial line
- * NOTE: Clear break needs to run at least one frame after set_break is called
- */
- void set_break();
-
- /** Clear a break condition on the serial line
- * NOTE: Should be run at least one frame after set_break is called
- */
- void clear_break();
-
- /** Generate a break condition on the serial line
- */
- void send_break();
-
-#if !defined(DOXYGEN_ONLY)
-protected:
-
- /** Acquire exclusive access to this serial port
- */
- virtual void lock(void);
-
- /** Release exclusive access to this serial port
- */
- virtual void unlock(void);
-#endif
-public:
-
-#if DEVICE_SERIAL_FC
- /** Set the flow control type on the serial port
- *
- * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
- * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
- * @param flow2 the second flow control pin (CTS for RTSCTS)
- */
- void set_flow_control(Flow type, PinName flow1 = NC, PinName flow2 = NC);
-#endif
-
- static void _irq_handler(uint32_t id, SerialIrq irq_type);
-
-#if DEVICE_SERIAL_ASYNCH
-
- /** Begin asynchronous write using 8bit buffer. The completion invokes registered TX event callback
- *
- * This function locks the deep sleep until any event has occurred
- *
- * @param buffer The buffer where received data will be stored
- * @param length The buffer length in bytes
- * @param callback The event callback function
- * @param event The logical OR of TX events
- */
- int write(const uint8_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_TX_COMPLETE);
-
- /** Begin asynchronous write using 16bit buffer. The completion invokes registered TX event callback
- *
- * This function locks the deep sleep until any event has occurred
- *
- * @param buffer The buffer where received data will be stored
- * @param length The buffer length in bytes
- * @param callback The event callback function
- * @param event The logical OR of TX events
- */
- int write(const uint16_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_TX_COMPLETE);
-
- /** Abort the on-going write transfer
- */
- void abort_write();
-
- /** Begin asynchronous reading using 8bit buffer. The completion invokes registered RX event callback.
- *
- * This function locks the deep sleep until any event has occurred
- *
- * @param buffer The buffer where received data will be stored
- * @param length The buffer length in bytes
- * @param callback The event callback function
- * @param event The logical OR of RX events
- * @param char_match The matching character
- */
- int read(uint8_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
-
- /** Begin asynchronous reading using 16bit buffer. The completion invokes registered RX event callback.
- *
- * This function locks the deep sleep until any event has occurred
- *
- * @param buffer The buffer where received data will be stored
- * @param length The buffer length in bytes
- * @param callback The event callback function
- * @param event The logical OR of RX events
- * @param char_match The matching character
- */
- int read(uint16_t *buffer, int length, const event_callback_t &callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
-
- /** Abort the on-going read transfer
- */
- void abort_read();
-
- /** Configure DMA usage suggestion for non-blocking TX transfers
- *
- * @param usage The usage DMA hint for peripheral
- * @return Zero if the usage was set, -1 if a transaction is on-going
- */
- int set_dma_usage_tx(DMAUsage usage);
-
- /** Configure DMA usage suggestion for non-blocking RX transfers
- *
- * @param usage The usage DMA hint for peripheral
- * @return Zero if the usage was set, -1 if a transaction is on-going
- */
- int set_dma_usage_rx(DMAUsage usage);
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t &callback, int event, unsigned char char_match);
- void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t &callback, int event);
- void interrupt_handler_asynch(void);
-#endif
-#endif
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- SerialBase(PinName tx, PinName rx, int baud);
- virtual ~SerialBase();
-
- int _base_getc();
- int _base_putc(int c);
-
-#if DEVICE_SERIAL_ASYNCH
- CThunk<SerialBase> _thunk_irq;
- DMAUsage _tx_usage;
- DMAUsage _rx_usage;
- event_callback_t _tx_callback;
- event_callback_t _rx_callback;
-#endif
-
- serial_t _serial;
- Callback<void()> _irq[IrqCnt];
- int _baud;
-#endif
-};
-
-} // namespace mbed
-
-#endif
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/SerialWireOutput.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_SERIALWIREOUTPUT_H
-#define MBED_SERIALWIREOUTPUT_H
-
-#if defined(DEVICE_ITM)
-
-#include "hal/itm_api.h"
-#include "platform/FileHandle.h"
-
-namespace mbed {
-
-class SerialWireOutput : public FileHandle {
-
-public:
-
- SerialWireOutput(void)
- {
- /* Initialize ITM using internal init function. */
- mbed_itm_init();
- }
-
- virtual ssize_t write(const void *buffer, size_t size)
- {
- mbed_itm_send_block(ITM_PORT_SWO, buffer, size);
-
- return size;
- }
-
- virtual ssize_t read(void *buffer, size_t size)
- {
- /* Reading is not supported by this file handle */
- return -EBADF;
- }
-
- virtual off_t seek(off_t offset, int whence = SEEK_SET)
- {
- /* Seeking is not support by this file handler */
- return -ESPIPE;
- }
-
- virtual off_t size()
- {
- /* Size is not defined for this file handle */
- return -EINVAL;
- }
-
- virtual int isatty()
- {
- /* File handle is used for terminal output */
- return true;
- }
-
- virtual int close()
- {
- return 0;
- }
-};
-
-} // namespace mbed
-
-#endif // DEVICE_ITM
-
-#endif // MBED_SERIALWIREOUTPUT_H
--- a/STM32F103C8T6_MPA/mbed/drivers/TableCRC.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef TABLE_CRC_H
-#define TABLE_CRC_H
-
-#include <stdint.h>
-
-namespace mbed {
-/** \addtogroup drivers */
-/** @{*/
-
-#define MBED_CRC_TABLE_SIZE 256
-#define MBED_OPTIMIZED_CRC_TABLE_SIZE 16
-
-extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE];
-extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE];
-extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE];
-extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE];
-extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE];
-extern const uint32_t Table_CRC_32bit_Rev_ANSI[MBED_OPTIMIZED_CRC_TABLE_SIZE];
-
-/** @}*/
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/Ticker.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,163 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_H
-#define MBED_TICKER_H
-
-#include "drivers/TimerEvent.h"
-#include "platform/Callback.h"
-#include "platform/mbed_toolchain.h"
-#include "platform/NonCopyable.h"
-#include "platform/mbed_power_mgmt.h"
-#include "hal/lp_ticker_api.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A Ticker is used to call a function at a recurring interval
- *
- * You can use as many separate Ticker objects as you require.
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Toggle the blinking LED after 5 seconds
- *
- * #include "mbed.h"
- *
- * Ticker timer;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * int flip = 0;
- *
- * void attime() {
- * flip = !flip;
- * }
- *
- * int main() {
- * timer.attach(&attime, 5);
- * while(1) {
- * if(flip == 0) {
- * led1 = !led1;
- * } else {
- * led2 = !led2;
- * }
- * wait(0.2);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class Ticker : public TimerEvent, private NonCopyable<Ticker> {
-
-public:
- Ticker() : TimerEvent(), _function(0), _lock_deepsleep(true)
- {
- }
-
- // When low power ticker is in use, then do not disable deep sleep.
- Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(true)
- {
-#if DEVICE_LPTICKER
- _lock_deepsleep = (data != get_lp_ticker_data());
-#endif
- }
-
- /** Attach a function to be called by the Ticker, specifying the interval in seconds
- *
- * @param func pointer to the function to be called
- * @param t the time between calls in seconds
- */
- void attach(Callback<void()> func, float t)
- {
- attach_us(func, t * 1000000.0f);
- }
-
- /** Attach a member function to be called by the Ticker, specifying the interval in seconds
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @param t the time between calls in seconds
- * @deprecated
- * The attach function does not support cv-qualifiers. Replaced by
- * attach(callback(obj, method), t).
- */
- template<typename T, typename M>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The attach function does not support cv-qualifiers. Replaced by "
- "attach(callback(obj, method), t).")
- void attach(T *obj, M method, float t)
- {
- attach(callback(obj, method), t);
- }
-
- /** Attach a function to be called by the Ticker, specifying the interval in microseconds
- *
- * @param func pointer to the function to be called
- * @param t the time between calls in micro-seconds
- *
- * @note setting @a t to a value shorter than it takes to process the ticker callback
- * causes the system to hang. Ticker callback is called constantly with no time
- * for threads scheduling.
- *
- */
- void attach_us(Callback<void()> func, us_timestamp_t t);
-
- /** Attach a member function to be called by the Ticker, specifying the interval in microseconds
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- * @param t the time between calls in microseconds
- * @deprecated
- * The attach_us function does not support cv-qualifiers. Replaced by
- * attach_us(callback(obj, method), t).
- */
- template<typename T, typename M>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The attach_us function does not support cv-qualifiers. Replaced by "
- "attach_us(callback(obj, method), t).")
- void attach_us(T *obj, M method, us_timestamp_t t)
- {
- attach_us(Callback<void()>(obj, method), t);
- }
-
- virtual ~Ticker()
- {
- detach();
- }
-
- /** Detach the function
- */
- void detach();
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- void setup(us_timestamp_t t);
- virtual void handler();
-
-protected:
- us_timestamp_t _delay; /**< Time delay (in microseconds) for resetting the multishot callback. */
- Callback<void()> _function; /**< Callback. */
- bool _lock_deepsleep; /**< Flag which indicates if deep sleep should be disabled. */
-#endif
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/Timeout.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,68 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEOUT_H
-#define MBED_TIMEOUT_H
-
-#include "drivers/Ticker.h"
-#include "platform/NonCopyable.h"
-#include "platform/mbed_power_mgmt.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A Timeout is used to call a function at a point in the future
- *
- * You can use as many separate Timeout objects as you require.
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Blink until timeout.
- *
- * #include "mbed.h"
- *
- * Timeout timeout;
- * DigitalOut led(LED1);
- *
- * int on = 1;
- *
- * void attimeout() {
- * on = 0;
- * }
- *
- * int main() {
- * timeout.attach(&attimeout, 5);
- * while(on) {
- * led = !led;
- * wait(0.2);
- * }
- * }
- * @endcode
- * @ingroup drivers
- */
-class Timeout : public Ticker, private NonCopyable<Timeout> {
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- virtual void handler();
-#endif
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/Timer.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMER_H
-#define MBED_TIMER_H
-
-#include "platform/platform.h"
-#include "hal/ticker_api.h"
-#include "platform/NonCopyable.h"
-#include "platform/mbed_power_mgmt.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** A general purpose timer
- *
- * @note Synchronization level: Interrupt safe
- *
- * Example:
- * @code
- * // Count the time to toggle an LED
- *
- * #include "mbed.h"
- *
- * Timer timer;
- * DigitalOut led(LED1);
- * int begin, end;
- *
- * int main() {
- * timer.start();
- * begin = timer.read_us();
- * led = !led;
- * end = timer.read_us();
- * printf("Toggle the led takes %d us", end - begin);
- * }
- * @endcode
- * @ingroup drivers
- */
-class Timer : private NonCopyable<Timer> {
-
-public:
- Timer();
- Timer(const ticker_data_t *data);
- ~Timer();
-
- /** Start the timer
- */
- void start();
-
- /** Stop the timer
- */
- void stop();
-
- /** Reset the timer to 0.
- *
- * If it was already running, it will continue
- */
- void reset();
-
- /** Get the time passed in seconds
- *
- * @returns Time passed in seconds
- */
- float read();
-
- /** Get the time passed in milliseconds
- *
- * @returns Time passed in milliseconds
- */
- int read_ms();
-
- /** Get the time passed in microseconds
- *
- * @returns Time passed in microseconds
- */
- int read_us();
-
- /** An operator shorthand for read()
- */
- operator float();
-
- /** Get in a high resolution type the time passed in microseconds.
- * Returns a 64 bit integer.
- */
- us_timestamp_t read_high_resolution_us();
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- us_timestamp_t slicetime();
- int _running; // whether the timer is running
- us_timestamp_t _start; // the start time of the latest slice
- us_timestamp_t _time; // any accumulated time from previous slices
- const ticker_data_t *_ticker_data;
- bool _lock_deepsleep; // flag that indicates if deep sleep should be disabled
-};
-#endif
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/TimerEvent.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,87 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEREVENT_H
-#define MBED_TIMEREVENT_H
-
-#include "hal/ticker_api.h"
-#include "hal/us_ticker_api.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup drivers */
-
-/** Base abstraction for timer interrupts
- *
- * @note Synchronization level: Interrupt safe
- * @ingroup drivers
- */
-class TimerEvent : private NonCopyable<TimerEvent> {
-public:
- TimerEvent();
- TimerEvent(const ticker_data_t *data);
-
- /** The handler registered with the underlying timer interrupt
- *
- * @param id Timer Event ID
- */
- static void irq(uint32_t id);
-
- /** Destruction removes it...
- */
- virtual ~TimerEvent();
-
-#if !defined(DOXYGEN_ONLY)
-protected:
- // The handler called to service the timer event of the derived class
- virtual void handler() = 0;
-
- /** Set relative timestamp of the internal event.
- * @param timestamp event's us timestamp
- *
- * @warning
- * Do not insert more than one timestamp.
- * The same @a event object is used for every @a insert/insert_absolute call.
- *
- * @warning
- * Ticker's present timestamp is used for reference. For timestamps
- * from the past the event is scheduled after ticker's overflow.
- * For reference @see convert_timestamp
- */
- void insert(timestamp_t timestamp);
-
- /** Set absolute timestamp of the internal event.
- * @param timestamp event's us timestamp
- *
- * @warning
- * Do not insert more than one timestamp.
- * The same @a event object is used for every @a insert/insert_absolute call.
- */
- void insert_absolute(us_timestamp_t timestamp);
-
- /** Remove timestamp.
- */
- void remove();
-
- ticker_event_t event;
-
- const ticker_data_t *_ticker_data;
-#endif
-};
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/drivers/UARTSerial.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,283 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_UARTSERIAL_H
-#define MBED_UARTSERIAL_H
-
-#include "platform/platform.h"
-
-#if (DEVICE_SERIAL && DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
-
-#include "platform/FileHandle.h"
-#include "SerialBase.h"
-#include "InterruptIn.h"
-#include "platform/PlatformMutex.h"
-#include "hal/serial_api.h"
-#include "platform/CircularBuffer.h"
-#include "platform/NonCopyable.h"
-
-#ifndef MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE
-#define MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE 256
-#endif
-
-#ifndef MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE
-#define MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE 256
-#endif
-
-namespace mbed {
-
-/** \addtogroup drivers */
-
-/** Class providing buffered UART communication functionality using separate circular buffer for send and receive channels
- *
- * @ingroup drivers
- */
-
-class UARTSerial : private SerialBase, public FileHandle, private NonCopyable<UARTSerial> {
-
-public:
-
- /** Create a UARTSerial port, connected to the specified transmit and receive pins, with a particular baud rate.
- * @param tx Transmit pin
- * @param rx Receive pin
- * @param baud The baud rate of the serial port (optional, defaults to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE)
- */
- UARTSerial(PinName tx, PinName rx, int baud = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
- virtual ~UARTSerial();
-
- /** Equivalent to POSIX poll(). Derived from FileHandle.
- * Provides a mechanism to multiplex input/output over a set of file handles.
- */
- virtual short poll(short events) const;
-
- /* Resolve ambiguities versus our private SerialBase
- * (for writable, spelling differs, but just in case)
- */
- using FileHandle::readable;
- using FileHandle::writable;
-
- /** Write the contents of a buffer to a file
- *
- * Follows POSIX semantics:
- *
- * * if blocking, block until all data is written
- * * if no data can be written, and non-blocking set, return -EAGAIN
- * * if some data can be written, and non-blocking set, write partial
- *
- * @param buffer The buffer to write from
- * @param length The number of bytes to write
- * @return The number of bytes written, negative error on failure
- */
- virtual ssize_t write(const void *buffer, size_t length);
-
- /** Read the contents of a file into a buffer
- *
- * Follows POSIX semantics:
- *
- * * if no data is available, and non-blocking set return -EAGAIN
- * * if no data is available, and blocking set, wait until data is available
- * * If any data is available, call returns immediately
- *
- * @param buffer The buffer to read in to
- * @param length The number of bytes to read
- * @return The number of bytes read, 0 at end of file, negative error on failure
- */
- virtual ssize_t read(void *buffer, size_t length);
-
- /** Close a file
- *
- * @return 0 on success, negative error code on failure
- */
- virtual int close();
-
- /** Check if the file in an interactive terminal device
- *
- * @return True if the file is a terminal
- * @return False if the file is not a terminal
- * @return Negative error code on failure
- */
- virtual int isatty();
-
- /** Move the file position to a given offset from from a given location
- *
- * Not valid for a device type FileHandle like UARTSerial.
- * In case of UARTSerial, returns ESPIPE
- *
- * @param offset The offset from whence to move to
- * @param whence The start of where to seek
- * SEEK_SET to start from beginning of file,
- * SEEK_CUR to start from current position in file,
- * SEEK_END to start from end of file
- * @return The new offset of the file, negative error code on failure
- */
- virtual off_t seek(off_t offset, int whence);
-
- /** Flush any buffers associated with the file
- *
- * @return 0 on success, negative error code on failure
- */
- virtual int sync();
-
- /** Set blocking or non-blocking mode
- * The default is blocking.
- *
- * @param blocking true for blocking mode, false for non-blocking mode.
- */
- virtual int set_blocking(bool blocking)
- {
- _blocking = blocking;
- return 0;
- }
-
- /** Check current blocking or non-blocking mode for file operations.
- *
- * @return true for blocking mode, false for non-blocking mode.
- */
- virtual bool is_blocking() const
- {
- return _blocking;
- }
-
- /** Register a callback on state change of the file.
- *
- * The specified callback will be called on state changes such as when
- * the file can be written to or read from.
- *
- * The callback may be called in an interrupt context and should not
- * perform expensive operations.
- *
- * Note! This is not intended as an attach-like asynchronous api, but rather
- * as a building block for constructing such functionality.
- *
- * The exact timing of when the registered function
- * is called is not guaranteed and susceptible to change. It should be used
- * as a cue to make read/write/poll calls to find the current state.
- *
- * @param func Function to call on state change
- */
- virtual void sigio(Callback<void()> func);
-
- /** Setup interrupt handler for DCD line
- *
- * If DCD line is connected, an IRQ handler will be setup.
- * Does nothing if DCD is NC, i.e., not connected.
- *
- * @param dcd_pin Pin-name for DCD
- * @param active_high a boolean set to true if DCD polarity is active low
- */
- void set_data_carrier_detect(PinName dcd_pin, bool active_high = false);
-
- /** Set the baud rate
- *
- * @param baud The baud rate
- */
- void set_baud(int baud);
-
- // Expose private SerialBase::Parity as UARTSerial::Parity
- using SerialBase::Parity;
- // In C++11, we wouldn't need to also have using directives for each value
- using SerialBase::None;
- using SerialBase::Odd;
- using SerialBase::Even;
- using SerialBase::Forced1;
- using SerialBase::Forced0;
-
- /** Set the transmission format used by the serial port
- *
- * @param bits The number of bits in a word (5-8; default = 8)
- * @param parity The parity used (None, Odd, Even, Forced1, Forced0; default = None)
- * @param stop_bits The number of stop bits (1 or 2; default = 1)
- */
- void set_format(int bits = 8, Parity parity = UARTSerial::None, int stop_bits = 1);
-
-#if DEVICE_SERIAL_FC
- // For now use the base enum - but in future we may have extra options
- // such as XON/XOFF or manual GPIO RTSCTS.
- using SerialBase::Flow;
- // In C++11, we wouldn't need to also have using directives for each value
- using SerialBase::Disabled;
- using SerialBase::RTS;
- using SerialBase::CTS;
- using SerialBase::RTSCTS;
-
- /** Set the flow control type on the serial port
- *
- * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
- * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
- * @param flow2 the second flow control pin (CTS for RTSCTS)
- */
- void set_flow_control(Flow type, PinName flow1 = NC, PinName flow2 = NC);
-#endif
-
-private:
-
- void wait_ms(uint32_t millisec);
-
- /** SerialBase lock override */
- virtual void lock(void);
-
- /** SerialBase unlock override */
- virtual void unlock(void);
-
- /** Acquire mutex */
- virtual void api_lock(void);
-
- /** Release mutex */
- virtual void api_unlock(void);
-
- /** Unbuffered write - invoked when write called from critical section */
- ssize_t write_unbuffered(const char *buf_ptr, size_t length);
-
- /** Software serial buffers
- * By default buffer size is 256 for TX and 256 for RX. Configurable through mbed_app.json
- */
- CircularBuffer<char, MBED_CONF_DRIVERS_UART_SERIAL_RXBUF_SIZE> _rxbuf;
- CircularBuffer<char, MBED_CONF_DRIVERS_UART_SERIAL_TXBUF_SIZE> _txbuf;
-
- PlatformMutex _mutex;
-
- Callback<void()> _sigio_cb;
-
- bool _blocking;
- bool _tx_irq_enabled;
- bool _rx_irq_enabled;
- InterruptIn *_dcd_irq;
-
- /** Device Hanged up
- * Determines if the device hanged up on us.
- *
- * @return True, if hanged up
- */
- bool hup() const;
-
- /** ISRs for serial
- * Routines to handle interrupts on serial pins.
- * Copies data into Circular Buffer.
- * Reports the state change to File handle.
- */
- void tx_irq(void);
- void rx_irq(void);
-
- void wake(void);
-
- void dcd_irq(void);
-
-};
-} //namespace mbed
-
-#endif //(DEVICE_SERIAL && DEVICE_INTERRUPTIN) || defined(DOXYGEN_ONLY)
-#endif //MBED_UARTSERIAL_H
--- a/STM32F103C8T6_MPA/mbed/hal/Driver_Common.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/*
- * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __DRIVER_COMMON_H
-#define __DRIVER_COMMON_H
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-/****** This file has been deprecated since mbed-os-5.5 *****/
-
-#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
-
-/**
-\brief Driver Version
-*/
-typedef struct _ARM_DRIVER_VERSION {
- uint16_t api; ///< API version
- uint16_t drv; ///< Driver version
-} ARM_DRIVER_VERSION;
-
-/* General return codes */
-#define ARM_DRIVER_OK 0 ///< Operation succeeded
-#define ARM_DRIVER_ERROR -1 ///< Unspecified error
-#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy
-#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred
-#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
-#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error
-#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors
-
-/**
-\brief General power states
-*/
-typedef enum _ARM_POWER_STATE {
- ARM_POWER_OFF, ///< Power off: no operation possible
- ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
- ARM_POWER_FULL ///< Power on: full operation at maximum performance
-} ARM_POWER_STATE;
-
-#endif /* __DRIVER_COMMON_H */
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/Driver_Storage.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,775 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/*
- * Copyright (c) 2006-2016, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __DRIVER_STORAGE_H
-#define __DRIVER_STORAGE_H
-
-#include <stdint.h>
-
-/****** This file has been deprecated since mbed-os-5.5 *****/
-
-#ifdef __cplusplus
-extern "C" {
-#endif // __cplusplus
-
-#include "Driver_Common.h"
-
-#define ARM_STORAGE_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,00) /* API version */
-
-
-#define _ARM_Driver_Storage_(n) Driver_Storage##n
-#define ARM_Driver_Storage_(n) _ARM_Driver_Storage_(n)
-
-#define ARM_STORAGE_INVALID_OFFSET (0xFFFFFFFFFFFFFFFFULL) ///< Invalid address (relative to a storage controller's
- ///< address space). A storage block may never start at this address.
-
-#define ARM_STORAGE_INVALID_ADDRESS (0xFFFFFFFFUL) ///< Invalid address within the processor's memory address space.
- ///< Refer to memory-mapped storage, i.e. < \ref ARM_DRIVER_STORAGE::ResolveAddress().
-
-/****** Storage specific error codes *****/
-#define ARM_STORAGE_ERROR_NOT_ERASABLE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Part (or all) of the range provided to Erase() isn't erasable.
-#define ARM_STORAGE_ERROR_NOT_PROGRAMMABLE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Part (or all) of the range provided to ProgramData() isn't programmable.
-#define ARM_STORAGE_ERROR_PROTECTED (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Part (or all) of the range to Erase() or ProgramData() is protected.
-#define ARM_STORAGE_ERROR_RUNTIME_OR_INTEGRITY_FAILURE (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Runtime or sanity-check failure.
-
-/**
- * \brief Attributes of the storage range within a storage block.
- */
-typedef struct _ARM_STORAGE_BLOCK_ATTRIBUTES {
- uint32_t erasable : 1; ///< Erasing blocks is permitted with a minimum granularity of 'erase_unit'.
- ///< @note: if 'erasable' is 0--i.e. the 'erase' operation isn't available--then
- ///< 'erase_unit' (see below) is immaterial and should be 0.
- uint32_t programmable : 1; ///< Writing to ranges is permitted with a minimum granularity of 'program_unit'.
- ///< Writes are typically achieved through the ProgramData operation (following an erase);
- ///< if storage isn't erasable (see 'erasable' above) but is memory-mapped
- ///< (i.e. 'memory_mapped'), it can be written directly using memory-store operations.
- uint32_t executable : 1; ///< This storage block can hold program data; the processor can fetch and execute code
- ///< sourced from it. Often this is accompanied with the device being 'memory_mapped' (see \ref ARM_STORAGE_INFO).
- uint32_t protectable : 1; ///< The entire block can be protected from program and erase operations. Once protection
- ///< is enabled for a block, its 'erasable' and 'programmable' bits are turned off.
- uint32_t reserved : 28;
- uint32_t erase_unit; ///< Minimum erase size in bytes.
- ///< The offset of the start of the erase-range should also be aligned with this value.
- ///< Applicable if the 'erasable' attribute is set for the block.
- ///< @note: if 'erasable' (see above) is 0--i.e. the 'erase' operation isn't available--then
- ///< 'erase_unit' is immaterial and should be 0.
- uint32_t protection_unit; ///< Minimum protectable size in bytes. Applicable if the 'protectable'
- ///< attribute is set for the block. This should be a divisor of the block's size. A
- ///< block can be considered to be made up of consecutive, individually-protectable fragments.
-} ARM_STORAGE_BLOCK_ATTRIBUTES;
-
-/**
- * \brief A storage block is a range of memory with uniform attributes. Storage blocks
- * combine to make up the address map of a storage controller.
- */
-typedef struct _ARM_STORAGE_BLOCK {
- uint64_t addr; ///< This is the start address of the storage block. It is
- ///< expressed as an offset from the start of the storage map
- ///< maintained by the owning storage controller.
- uint64_t size; ///< This is the size of the storage block, in units of bytes.
- ///< Together with addr, it describes a range [addr, addr+size).
- ARM_STORAGE_BLOCK_ATTRIBUTES attributes; ///< Attributes for this block.
-} ARM_STORAGE_BLOCK;
-
-/**
- * The check for a valid ARM_STORAGE_BLOCK.
- */
-#define ARM_STORAGE_VALID_BLOCK(BLK) (((BLK)->addr != ARM_STORAGE_INVALID_OFFSET) && ((BLK)->size != 0))
-
-/**
- * \brief Values for encoding storage memory-types with respect to programmability.
- *
- * Please ensure that the maximum of the following memory types doesn't exceed 16; we
- * encode this in a 4-bit field within ARM_STORAGE_INFO::programmability.
- */
-#define ARM_STORAGE_PROGRAMMABILITY_RAM (0x0)
-#define ARM_STORAGE_PROGRAMMABILITY_ROM (0x1) ///< Read-only memory.
-#define ARM_STORAGE_PROGRAMMABILITY_WORM (0x2) ///< write-once-read-only-memory (WORM).
-#define ARM_STORAGE_PROGRAMMABILITY_ERASABLE (0x3) ///< re-programmable based on erase. Supports multiple writes.
-
-/**
- * Values for encoding data-retention levels for storage blocks.
- *
- * Please ensure that the maximum of the following retention types doesn't exceed 16; we
- * encode this in a 4-bit field within ARM_STORAGE_INFO::retention_level.
- */
-#define ARM_RETENTION_WHILE_DEVICE_ACTIVE (0x0) ///< Data is retained only during device activity.
-#define ARM_RETENTION_ACROSS_SLEEP (0x1) ///< Data is retained across processor sleep.
-#define ARM_RETENTION_ACROSS_DEEP_SLEEP (0x2) ///< Data is retained across processor deep-sleep.
-#define ARM_RETENTION_BATTERY_BACKED (0x3) ///< Data is battery-backed. Device can be powered off.
-#define ARM_RETENTION_NVM (0x4) ///< Data is retained in non-volatile memory.
-
-/**
- * Device Data Security Protection Features. Applicable mostly to EXTERNAL_NVM.
- */
-typedef struct _ARM_STORAGE_SECURITY_FEATURES {
- uint32_t acls : 1; ///< Protection against internal software attacks using ACLs.
- uint32_t rollback_protection : 1; ///< Roll-back protection. Set to true if the creator of the storage
- ///< can ensure that an external attacker can't force an
- ///< older firmware to run or to revert back to a previous state.
- uint32_t tamper_proof : 1; ///< Tamper-proof memory (will be deleted on tamper-attempts using board level or chip level sensors).
- uint32_t internal_flash : 1; ///< Internal flash.
- uint32_t reserved1 : 12;
-
- /**
- * Encode support for hardening against various classes of attacks.
- */
- uint32_t software_attacks : 1; ///< device software (malware running on the device).
- uint32_t board_level_attacks : 1; ///< board level attacks (debug probes, copy protection fuses.)
- uint32_t chip_level_attacks : 1; ///< chip level attacks (tamper-protection).
- uint32_t side_channel_attacks : 1; ///< side channel attacks.
- uint32_t reserved2 : 12;
-} ARM_STORAGE_SECURITY_FEATURES;
-
-#define ARM_STORAGE_PROGRAM_CYCLES_INFINITE (0UL) /**< Infinite or unknown endurance for reprogramming. */
-
-/**
- * \brief Storage information. This contains device-metadata. It is the return
- * value from calling GetInfo() on the storage driver.
- *
- * \details These fields serve a different purpose than the ones contained in
- * \ref ARM_STORAGE_CAPABILITIES, which is another structure containing
- * device-level metadata. ARM_STORAGE_CAPABILITIES describes the API
- * capabilities, whereas ARM_STORAGE_INFO describes the device. Furthermore
- * ARM_STORAGE_CAPABILITIES fits within a single word, and is designed to be
- * passed around by value; ARM_STORAGE_INFO, on the other hand, contains
- * metadata which doesn't fit into a single word and requires the use of
- * pointers to be moved around.
- */
-typedef struct _ARM_STORAGE_INFO {
- uint64_t total_storage; ///< Total available storage, in bytes.
- uint32_t program_unit; ///< Minimum programming size in bytes.
- ///< The offset of the start of the program-range should also be aligned with this value.
- ///< Applicable only if the 'programmable' attribute is set for a block.
- ///< @note: setting program_unit to 0 has the effect of disabling the size and alignment
- ///< restrictions (setting it to 1 also has the same effect).
- uint32_t optimal_program_unit; ///< Optimal programming page-size in bytes. Some storage controllers
- ///< have internal buffers into which to receive data. Writing in chunks of
- ///< 'optimal_program_unit' would achieve maximum programming speed.
- ///< Applicable only if the 'programmable' attribute is set for the underlying block(s).
- uint32_t program_cycles; ///< A measure of endurance for reprogramming.
- ///< Use ARM_STORAGE_PROGRAM_CYCLES_INFINITE for infinite or unknown endurance.
- uint32_t erased_value : 1; ///< Contents of erased memory (usually 1 to indicate erased bytes with state 0xFF).
- uint32_t memory_mapped : 1; ///< This storage device has a mapping onto the processor's memory address space.
- ///< @note: For a memory-mapped block which isn't erasable but is programmable (i.e. if
- ///< 'erasable' is set to 0, but 'programmable' is 1), writes should be possible directly to
- ///< the memory-mapped storage without going through the ProgramData operation.
- uint32_t programmability : 4; ///< A value to indicate storage programmability.
- uint32_t retention_level : 4;
- uint32_t reserved : 22;
- ARM_STORAGE_SECURITY_FEATURES security; ///< \ref ARM_STORAGE_SECURITY_FEATURES
-} ARM_STORAGE_INFO;
-
-/**
-\brief Operating status of the storage controller.
-*/
-typedef struct _ARM_STORAGE_STATUS {
- uint32_t busy : 1; ///< Controller busy flag
- uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
-} ARM_STORAGE_STATUS;
-
-/**
- * \brief Storage Driver API Capabilities.
- *
- * This data structure is designed to fit within a single word so that it can be
- * fetched cheaply using a call to driver->GetCapabilities().
- */
-typedef struct _ARM_STORAGE_CAPABILITIES {
- uint32_t asynchronous_ops : 1; ///< Used to indicate if APIs like initialize,
- ///< read, erase, program, etc. can operate in asynchronous mode.
- ///< Setting this bit to 1 means that the driver is capable
- ///< of launching asynchronous operations; command completion is
- ///< signaled by the invocation of a completion callback. If
- ///< set to 1, drivers may still complete asynchronous
- ///< operations synchronously as necessary--in which case they
- ///< return a positive error code to indicate synchronous completion.
- uint32_t erase_all : 1; ///< Supports EraseAll operation.
- uint32_t reserved : 30;
-} ARM_STORAGE_CAPABILITIES;
-
-/**
- * Command opcodes for Storage. Completion callbacks use these codes to refer to
- * completing commands. Refer to \ref ARM_Storage_Callback_t.
- */
-typedef enum _ARM_STORAGE_OPERATION {
- ARM_STORAGE_OPERATION_GET_VERSION,
- ARM_STORAGE_OPERATION_GET_CAPABILITIES,
- ARM_STORAGE_OPERATION_INITIALIZE,
- ARM_STORAGE_OPERATION_UNINITIALIZE,
- ARM_STORAGE_OPERATION_POWER_CONTROL,
- ARM_STORAGE_OPERATION_READ_DATA,
- ARM_STORAGE_OPERATION_PROGRAM_DATA,
- ARM_STORAGE_OPERATION_ERASE,
- ARM_STORAGE_OPERATION_ERASE_ALL,
- ARM_STORAGE_OPERATION_GET_STATUS,
- ARM_STORAGE_OPERATION_GET_INFO,
- ARM_STORAGE_OPERATION_RESOLVE_ADDRESS,
- ARM_STORAGE_OPERATION_GET_NEXT_BLOCK,
- ARM_STORAGE_OPERATION_GET_BLOCK
-} ARM_STORAGE_OPERATION;
-
-/**
- * Declaration of the callback-type for command completion.
- *
- * @param [in] status
- * A code to indicate the status of the completed operation. For data
- * transfer operations, the status field is overloaded in case of
- * success to return the count of items successfully transferred; this
- * can be done safely because error codes are negative values.
- *
- * @param [in] operation
- * The command op-code. This value isn't essential for the callback in
- * the presence of the command instance-id, but it is expected that
- * this information could be a quick and useful filter.
- */
-typedef void (*ARM_Storage_Callback_t)(int32_t status, ARM_STORAGE_OPERATION operation);
-
-/**
- * This is the set of operations constituting the Storage driver. Their
- * implementation is platform-specific, and needs to be supplied by the
- * porting effort.
- *
- * Some APIs within `ARM_DRIVER_STORAGE` will always operate synchronously:
- * GetVersion, GetCapabilities, GetStatus, GetInfo, ResolveAddress,
- * GetNextBlock, and GetBlock. This means that control returns to the caller
- * with a relevant status code only after the completion of the operation (or
- * the discovery of a failure condition).
- *
- * The remainder of the APIs: Initialize, Uninitialize, PowerControl, ReadData,
- * ProgramData, Erase, EraseAll, can function asynchronously if the underlying
- * controller supports it--i.e. if ARM_STORAGE_CAPABILITIES::asynchronous_ops is
- * set. In the case of asynchronous operation, the invocation returns early
- * (with ARM_DRIVER_OK) and results in a completion callback later. If
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is not set, then all such APIs
- * execute synchronously, and control returns to the caller with a status code
- * only after the completion of the operation (or the discovery of a failure
- * condition).
- *
- * If ARM_STORAGE_CAPABILITIES::asynchronous_ops is set, a storage driver may
- * still choose to execute asynchronous operations in a synchronous manner. If
- * so, the driver returns a positive value to indicate successful synchronous
- * completion (or an error code in case of failure) and no further invocation of
- * completion callback should be expected. The expected return value for
- * synchronous completion of such asynchronous operations varies depending on
- * the operation. For operations involving data access, it often equals the
- * amount of data transferred or affected. For non data-transfer operations,
- * such as EraseAll or Initialize, it is usually 1.
- *
- * Here's a code snippet to suggest how asynchronous APIs might be used by
- * callers to handle both synchronous and asynchronous execution by the
- * underlying storage driver:
- * \code
- * ASSERT(ARM_DRIVER_OK == 0); // this is a precondition; it doesn't need to be put in code
- * int32_t returnValue = drv->asynchronousAPI(...);
- * if (returnValue < ARM_DRIVER_OK) {
- * // handle error.
- * } else if (returnValue == ARM_DRIVER_OK) {
- * ASSERT(drv->GetCapabilities().asynchronous_ops == 1);
- * // handle early return from asynchronous execution; remainder of the work is done in the callback handler.
- * } else {
- * ASSERT(returnValue == EXPECTED_RETURN_VALUE_FOR_SYNCHRONOUS_COMPLETION);
- * // handle synchronous completion.
- * }
- * \endcode
- */
-typedef struct _ARM_DRIVER_STORAGE {
- /**
- * \brief Get driver version.
- *
- * The function GetVersion() returns version information of the driver implementation in ARM_DRIVER_VERSION.
- *
- * - API version is the version of the CMSIS-Driver specification used to implement this driver.
- * - Driver version is source code version of the actual driver implementation.
- *
- * Example:
- * \code
- * extern ARM_DRIVER_STORAGE *drv_info;
- *
- * void read_version (void) {
- * ARM_DRIVER_VERSION version;
- *
- * version = drv_info->GetVersion ();
- * if (version.api < 0x10A) { // requires at minimum API version 1.10 or higher
- * // error handling
- * return;
- * }
- * }
- * \endcode
- *
- * @return \ref ARM_DRIVER_VERSION.
- *
- * @note This API returns synchronously--it does not result in an invocation
- * of a completion callback.
- *
- * @note The function GetVersion() can be called any time to obtain the
- * required information from the driver (even before initialization). It
- * always returns the same information.
- */
- ARM_DRIVER_VERSION (*GetVersion)(void);
-
- /**
- * \brief Get driver capabilities.
- *
- * \details The function GetCapabilities() returns information about
- * capabilities in this driver implementation. The data fields of the struct
- * ARM_STORAGE_CAPABILITIES encode various capabilities, for example if the device
- * is able to execute operations asynchronously.
- *
- * Example:
- * \code
- * extern ARM_DRIVER_STORAGE *drv_info;
- *
- * void read_capabilities (void) {
- * ARM_STORAGE_CAPABILITIES drv_capabilities;
- *
- * drv_capabilities = drv_info->GetCapabilities ();
- * // interrogate capabilities
- *
- * }
- * \endcode
- *
- * @return \ref ARM_STORAGE_CAPABILITIES.
- *
- * @note This API returns synchronously--it does not result in an invocation
- * of a completion callback.
- *
- * @note The function GetCapabilities() can be called any time to obtain the
- * required information from the driver (even before initialization). It
- * always returns the same information.
- */
- ARM_STORAGE_CAPABILITIES (*GetCapabilities)(void);
-
- /**
- * \brief Initialize the Storage Interface.
- *
- * The function Initialize is called when the middleware component starts
- * operation. In addition to bringing the controller to a ready state,
- * Initialize() receives a callback handler to be invoked upon completion of
- * asynchronous operations.
- *
- * Initialize() needs to be called explicitly before
- * powering the peripheral using PowerControl(), and before initiating other
- * accesses to the storage controller.
- *
- * The function performs the following operations:
- * - Initializes the resources needed for the Storage interface.
- * - Registers the \ref ARM_Storage_Callback_t callback function.
- *
- * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
- * drv->Initialize (...); // Allocate I/O pins
- * drv->PowerControl (ARM_POWER_FULL); // Power up peripheral, setup IRQ/DMA
- *
- * - Initialize() typically allocates the I/O resources (pins) for the
- * peripheral. The function can be called multiple times; if the I/O resources
- * are already initialized it performs no operation and just returns with
- * ARM_DRIVER_OK.
- *
- * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
- * interrupt (NVIC) and optionally DMA. The function can be called multiple
- * times; if the registers are already set it performs no operation and just
- * returns with ARM_DRIVER_OK.
- *
- * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
- * drv->PowerControl (ARM_POWER_OFF); // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
- * drv->Uninitialize (...); // Release I/O pins
- *
- * The functions PowerControl and Uninitialize always execute and can be used
- * to put the peripheral into a Safe State, for example after any data
- * transmission errors. To restart the peripheral in an error condition,
- * you should first execute the Stop Sequence and then the Start Sequence.
- *
- * @param [in] callback
- * Caller-defined callback to be invoked upon command completion
- * for asynchronous APIs (including the completion of
- * initialization). Use a NULL pointer when no callback
- * signals are required.
- *
- * @note This API may execute asynchronously if
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
- * execution is optional even if 'asynchronous_ops' is set.
- *
- * @return If asynchronous activity is launched, an invocation returns
- * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
- * future with a status value of ARM_DRIVER_OK or an error-code. In the
- * case of synchronous execution, control returns after completion with a
- * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
- */
- int32_t (*Initialize)(ARM_Storage_Callback_t callback);
-
- /**
- * \brief De-initialize the Storage Interface.
- *
- * The function Uninitialize() de-initializes the resources of Storage interface.
- *
- * It is called when the middleware component stops operation, and wishes to
- * release the software resources used by the interface.
- *
- * @note This API may execute asynchronously if
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
- * execution is optional even if 'asynchronous_ops' is set.
- *
- * @return If asynchronous activity is launched, an invocation returns
- * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
- * future with a status value of ARM_DRIVER_OK or an error-code. In the
- * case of synchronous execution, control returns after completion with a
- * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
- */
- int32_t (*Uninitialize)(void);
-
- /**
- * \brief Control the Storage interface power.
- *
- * The function \b ARM_Storage_PowerControl operates the power modes of the Storage interface.
- *
- * To start working with a peripheral the functions Initialize and PowerControl need to be called in this order:
- * drv->Initialize (...); // Allocate I/O pins
- * drv->PowerControl (ARM_POWER_FULL); // Power up peripheral, setup IRQ/DMA
- *
- * - Initialize() typically allocates the I/O resources (pins) for the
- * peripheral. The function can be called multiple times; if the I/O resources
- * are already initialized it performs no operation and just returns with
- * ARM_DRIVER_OK.
- *
- * - PowerControl (ARM_POWER_FULL) sets the peripheral registers including
- * interrupt (NVIC) and optionally DMA. The function can be called multiple
- * times; if the registers are already set it performs no operation and just
- * returns with ARM_DRIVER_OK.
- *
- * To stop working with a peripheral the functions PowerControl and Uninitialize need to be called in this order:
- *
- * drv->PowerControl (ARM_POWER_OFF); // Terminate any pending transfers, reset IRQ/DMA, power off peripheral
- * drv->Uninitialize (...); // Release I/O pins
- *
- * The functions PowerControl and Uninitialize always execute and can be used
- * to put the peripheral into a Safe State, for example after any data
- * transmission errors. To restart the peripheral in an error condition,
- * you should first execute the Stop Sequence and then the Start Sequence.
- *
- * @param state
- * \ref ARM_POWER_STATE. The target power-state for the storage controller.
- * The parameter state can have the following values:
- * - ARM_POWER_FULL : set-up peripheral for data transfers, enable interrupts
- * (NVIC) and optionally DMA. Can be called multiple times. If the peripheral
- * is already in this mode, then the function performs no operation and returns
- * with ARM_DRIVER_OK.
- * - ARM_POWER_LOW : may use power saving. Returns ARM_DRIVER_ERROR_UNSUPPORTED when not implemented.
- * - ARM_POWER_OFF : terminates any pending data transfers, disables peripheral, disables related interrupts and DMA.
- *
- * @note This API may execute asynchronously if
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
- * execution is optional even if 'asynchronous_ops' is set.
- *
- * @return If asynchronous activity is launched, an invocation returns
- * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
- * future with a status value of ARM_DRIVER_OK or an error-code. In the
- * case of synchronous execution, control returns after completion with a
- * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
- */
- int32_t (*PowerControl)(ARM_POWER_STATE state);
-
- /**
- * \brief read the contents of a given address range from the storage device.
- *
- * \details Read the contents of a range of storage memory into a buffer
- * supplied by the caller. The buffer is owned by the caller and should
- * remain accessible for the lifetime of this command.
- *
- * @param [in] addr
- * This specifies the address from where to read data.
- *
- * @param [out] data
- * The destination of the read operation. The buffer
- * is owned by the caller and should remain accessible for the
- * lifetime of this command.
- *
- * @param [in] size
- * The number of bytes requested to read. The data buffer
- * should be at least as large as this size.
- *
- * @note This API may execute asynchronously if
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
- * execution is optional even if 'asynchronous_ops' is set.
- *
- * @return If asynchronous activity is launched, an invocation returns
- * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
- * future with the number of successfully transferred bytes passed in as
- * the 'status' parameter. In the case of synchronous execution, control
- * returns after completion with a positive transfer-count. Return values
- * less than ARM_DRIVER_OK (0) signify errors.
- */
- int32_t (*ReadData)(uint64_t addr, void *data, uint32_t size);
-
- /**
- * \brief program (write into) the contents of a given address range of the storage device.
- *
- * \details Write the contents of a given memory buffer into a range of
- * storage memory. In the case of flash memory, the destination range in
- * storage memory typically has its contents in an erased state from a
- * preceding erase operation. The source memory buffer is owned by the
- * caller and should remain accessible for the lifetime of this command.
- *
- * @param [in] addr
- * This is the start address of the range to be written into. It
- * needs to be aligned to the device's \em program_unit
- * specified in \ref ARM_STORAGE_INFO.
- *
- * @param [in] data
- * The source of the write operation. The buffer is owned by the
- * caller and should remain accessible for the lifetime of this
- * command.
- *
- * @param [in] size
- * The number of bytes requested to be written. The buffer
- * should be at least as large as this size. \note 'size' should
- * be a multiple of the device's 'program_unit' (see \ref
- * ARM_STORAGE_INFO).
- *
- * @note It is best for the middleware to write in units of
- * 'optimal_program_unit' (\ref ARM_STORAGE_INFO) of the device.
- *
- * @note This API may execute asynchronously if
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
- * execution is optional even if 'asynchronous_ops' is set.
- *
- * @return If asynchronous activity is launched, an invocation returns
- * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
- * future with the number of successfully transferred bytes passed in as
- * the 'status' parameter. In the case of synchronous execution, control
- * returns after completion with a positive transfer-count. Return values
- * less than ARM_DRIVER_OK (0) signify errors.
- */
- int32_t (*ProgramData)(uint64_t addr, const void *data, uint32_t size);
-
- /**
- * @brief Erase Storage range.
- *
- * @details This function erases a range of storage specified by [addr, addr +
- * size). Both 'addr' and 'addr + size' should align with the
- * 'erase_unit'(s) of the respective owning storage block(s) (see \ref
- * ARM_STORAGE_BLOCK and \ref ARM_STORAGE_BLOCK_ATTRIBUTES). The range to
- * be erased will have its contents returned to the un-programmed state--
- * i.e. to 'erased_value' (see \ref ARM_STORAGE_BLOCK_ATTRIBUTES), which
- * is usually 1 to indicate the pattern of all ones: 0xFF.
- *
- * @param [in] addr
- * This is the start-address of the range to be erased. It must
- * start at an 'erase_unit' boundary of the underlying block.
- *
- * @param [in] size
- * Size (in bytes) of the range to be erased. 'addr + size'
- * must be aligned with the 'erase_unit' of the underlying
- * block.
- *
- * @note This API may execute asynchronously if
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
- * execution is optional even if 'asynchronous_ops' is set.
- *
- * @return
- * If the range to be erased doesn't align with the erase_units of the
- * respective start and end blocks, ARM_DRIVER_ERROR_PARAMETER is returned.
- * If any part of the range is protected, ARM_STORAGE_ERROR_PROTECTED is
- * returned. If any part of the range is not erasable,
- * ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All such sanity-check
- * failures result in the error code being returned synchronously and the
- * storage bytes within the range remain unaffected.
- * Otherwise the function executes in the following ways:
- * If asynchronous activity is launched, an invocation returns
- * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
- * future with the number of successfully erased bytes passed in as
- * the 'status' parameter. In the case of synchronous execution, control
- * returns after completion with a positive erase-count. Return values
- * less than ARM_DRIVER_OK (0) signify errors.
- *
- * @note Erase() may return a smaller (positive) value than the size of the
- * requested range. The returned value indicates the actual number of bytes
- * erased. It is the caller's responsibility to follow up with an appropriate
- * request to complete the operation.
- *
- * @note in the case of a failed erase (except when
- * ARM_DRIVER_ERROR_PARAMETER, ARM_STORAGE_ERROR_PROTECTED, or
- * ARM_STORAGE_ERROR_NOT_ERASABLE is returned synchronously), the
- * requested range should be assumed to be in an unknown state. The
- * previous contents may not be retained.
- */
- int32_t (*Erase)(uint64_t addr, uint32_t size);
-
- /**
- * @brief Erase complete storage. Optional function for faster erase of the complete device.
- *
- * This optional function erases the complete device. If the device does not
- * support global erase then the function returns the error value \ref
- * ARM_DRIVER_ERROR_UNSUPPORTED. The data field \em 'erase_all' = 1
- * of the structure \ref ARM_STORAGE_CAPABILITIES encodes that
- * ARM_STORAGE_EraseAll is supported.
- *
- * @note This API may execute asynchronously if
- * ARM_STORAGE_CAPABILITIES::asynchronous_ops is set. Asynchronous
- * execution is optional even if 'asynchronous_ops' is set.
- *
- * @return
- * If any part of the storage range is protected,
- * ARM_STORAGE_ERROR_PROTECTED is returned. If any part of the storage
- * range is not erasable, ARM_STORAGE_ERROR_NOT_ERASABLE is returned. All
- * such sanity-check failures result in the error code being returned
- * synchronously and the storage bytes within the range remain unaffected.
- * Otherwise the function executes in the following ways:
- * If asynchronous activity is launched, an invocation returns
- * ARM_DRIVER_OK, and the caller can expect to receive a callback in the
- * future with ARM_DRIVER_OK passed in as the 'status' parameter. In the
- * case of synchronous execution, control returns after completion with a
- * value of 1. Return values less than ARM_DRIVER_OK (0) signify errors.
- */
- int32_t (*EraseAll)(void);
-
- /**
- * @brief Get the status of the current (or previous) command executed by the
- * storage controller; stored in the structure \ref ARM_STORAGE_STATUS.
- *
- * @return
- * The status of the underlying controller.
- *
- * @note This API returns synchronously--it does not result in an invocation
- * of a completion callback.
- */
- ARM_STORAGE_STATUS (*GetStatus)(void);
-
- /**
- * @brief Get information about the Storage device; stored in the structure \ref ARM_STORAGE_INFO.
- *
- * @param [out] info
- * A caller-supplied buffer capable of being filled in with an
- * \ref ARM_STORAGE_INFO.
- *
- * @return ARM_DRIVER_OK if a ARM_STORAGE_INFO structure containing top level
- * metadata about the storage controller is filled into the supplied
- * buffer, else an appropriate error value.
- *
- * @note It is the caller's responsibility to ensure that the buffer passed in
- * is able to be initialized with a \ref ARM_STORAGE_INFO.
- *
- * @note This API returns synchronously--it does not result in an invocation
- * of a completion callback.
- */
- int32_t (*GetInfo)(ARM_STORAGE_INFO *info);
-
- /**
- * \brief For memory-mapped storage, resolve an address relative to
- * the storage controller into a memory address.
- *
- * @param addr
- * This is the address for which we want a resolution to the
- * processor's physical address space. It is an offset from the
- * start of the storage map maintained by the owning storage
- * controller.
- *
- * @return
- * The resolved address in the processor's address space; else
- * ARM_STORAGE_INVALID_ADDRESS, if no resolution is possible.
- *
- * @note This API returns synchronously. The invocation should return quickly,
- * and result in a resolved address.
- */
- uint32_t (*ResolveAddress)(uint64_t addr);
-
- /**
- * @brief Advance to the successor of the current block (iterator), or fetch
- * the first block (if 'prev_block' is passed in as NULL).
- *
- * @details This helper function fetches (an iterator to) the next block (or
- * the first block if 'prev_block' is passed in as NULL). In the failure
- * case, a terminating, invalid block iterator is filled into the out
- * parameter: 'next_block'. In combination with \ref
- * ARM_STORAGE_VALID_BLOCK(), it can be used to iterate over the sequence
- * of blocks within the storage map:
- *
- * \code
- * ARM_STORAGE_BLOCK block;
- * for (drv->GetNextBlock(NULL, &block); ARM_STORAGE_VALID_BLOCK(&block); drv->GetNextBlock(&block, &block)) {
- * // make use of block
- * }
- * \endcode
- *
- * @param[in] prev_block
- * An existing block (iterator) within the same storage
- * controller. The memory buffer holding this block is owned
- * by the caller. This pointer may be NULL; if so, the
- * invocation fills in the first block into the out parameter:
- * 'next_block'.
- *
- * @param[out] next_block
- * A caller-owned buffer large enough to be filled in with
- * the following ARM_STORAGE_BLOCK. It is legal to provide the
- * same buffer using 'next_block' as was passed in with 'prev_block'. It
- * is also legal to pass a NULL into this parameter if the
- * caller isn't interested in populating a buffer with the next
- * block--i.e. if the caller only wishes to establish the
- * presence of a next block.
- *
- * @return ARM_DRIVER_OK if a valid next block is found (or first block, if
- * prev_block is passed as NULL); upon successful operation, the contents
- * of the next (or first) block are filled into the buffer pointed to by
- * the parameter 'next_block' and ARM_STORAGE_VALID_BLOCK(next_block) is
- * guaranteed to be true. Upon reaching the end of the sequence of blocks
- * (iterators), or in case the driver is unable to fetch information about
- * the next (or first) block, an error (negative) value is returned and an
- * invalid StorageBlock is populated into the supplied buffer. If
- * prev_block is NULL, the first block is returned.
- *
- * @note This API returns synchronously--it does not result in an invocation
- * of a completion callback.
- */
- int32_t (*GetNextBlock)(const ARM_STORAGE_BLOCK* prev_block, ARM_STORAGE_BLOCK *next_block);
-
- /**
- * @brief Find the storage block (iterator) encompassing a given storage address.
- *
- * @param[in] addr
- * Storage address in bytes.
- *
- * @param[out] block
- * A caller-owned buffer large enough to be filled in with the
- * ARM_STORAGE_BLOCK encapsulating the given address. This value
- * can also be passed in as NULL if the caller isn't interested
- * in populating a buffer with the block--if the caller only
- * wishes to establish the presence of a containing storage
- * block.
- *
- * @return ARM_DRIVER_OK if a containing storage-block is found. In this case,
- * if block is non-NULL, the buffer pointed to by it is populated with
- * the contents of the storage block--i.e. if block is valid and a block is
- * found, ARM_STORAGE_VALID_BLOCK(block) would return true following this
- * call. If there is no storage block containing the given offset, or in
- * case the driver is unable to resolve an address to a storage-block, an
- * error (negative) value is returned and an invalid StorageBlock is
- * populated into the supplied buffer.
- *
- * @note This API returns synchronously--it does not result in an invocation
- * of a completion callback.
- */
- int32_t (*GetBlock)(uint64_t addr, ARM_STORAGE_BLOCK *block);
-} const ARM_DRIVER_STORAGE;
-
-#ifdef __cplusplus
-}
-#endif // __cplusplus
-
-#endif /* __DRIVER_STORAGE_H */
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/LowPowerTickerWrapper.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOW_POWER_TICKER_WRAPPER_H
-#define MBED_LOW_POWER_TICKER_WRAPPER_H
-
-#include "device.h"
-
-#include "hal/ticker_api.h"
-#include "hal/us_ticker_api.h"
-#include "drivers/Timeout.h"
-
-
-class LowPowerTickerWrapper {
-public:
-
-
- /**
- * Create a new wrapped low power ticker object
- *
- * @param data Low power ticker data to wrap
- * @param interface new ticker interface functions
- * @param min_cycles_between_writes The number of whole low power clock periods
- * which must complete before subsequent calls to set_interrupt
- * @param min_cycles_until_match The minimum number of whole low power clock periods
- * from the current time for which the match timestamp passed to set_interrupt is
- * guaranteed to fire.
- *
- * N = min_cycles_between_writes
- *
- * 0 1 N - 1 N N + 1 N + 2 N + 3
- * |-------|------...------|-------|-------|-------|-------|
- * ^ ^
- * | |
- * set_interrupt Next set_interrupt allowed
- *
- * N = min_cycles_until_match
- *
- * 0 1 N - 1 N N + 1 N + 2 N + 3
- * |-------|------...------|-------|-------|-------|-------|
- * ^ ^
- * | |
- * set_interrupt Earliest match timestamp allowed
- *
- *
- */
-
- LowPowerTickerWrapper(const ticker_data_t *data, const ticker_interface_t *interface, uint32_t min_cycles_between_writes, uint32_t min_cycles_until_match);
-
- /**
- * Interrupt handler called by the underlying driver/hardware
- *
- * @param handler The callback which would normally be called by the underlying driver/hardware
- */
- void irq_handler(ticker_irq_handler_type handler);
-
- /**
- * Suspend wrapper operation and pass through interrupts.
- *
- * This stops to wrapper layer from using the microsecond ticker.
- * This should be called before using the low power ticker APIs directly.
- *
- * @warning: Make sure to suspend the LP ticker first (call ticker_suspend()),
- * otherwise the behavior is undefined.
- */
- void suspend();
-
- /**
- * Resume wrapper operation and filter interrupts normally
- */
- void resume();
-
- /**
- * Check if a Timeout object is being used
- *
- * @return true if Timeout is used for scheduling false otherwise
- */
- bool timeout_pending();
-
- /*
- * Implementation of ticker_init
- */
- void init();
-
- /*
- * Implementation of free
- */
- void free();
-
- /*
- * Implementation of read
- */
- uint32_t read();
-
- /*
- * Implementation of set_interrupt
- */
- void set_interrupt(timestamp_t timestamp);
-
- /*
- * Implementation of disable_interrupt
- */
- void disable_interrupt();
-
- /*
- * Implementation of clear_interrupt
- */
- void clear_interrupt();
-
- /*
- * Implementation of fire_interrupt
- */
- void fire_interrupt();
-
- /*
- * Implementation of get_info
- */
- const ticker_info_t *get_info();
-
- ticker_data_t data;
-
-private:
- mbed::Timeout _timeout;
- const ticker_interface_t *const _intf;
-
- /*
- * The number of low power clock cycles which must pass between subsequent
- * calls to intf->set_interrupt
- */
- const uint32_t _min_count_between_writes;
-
- /*
- * The minimum number of low power clock cycles in the future that
- * a match value can be set to and still fire
- */
- const uint32_t _min_count_until_match;
-
- /*
- * Flag to indicate if the timer is suspended
- */
- bool _suspended;
-
- /*
- * _cur_match_time is valid and Timeout is scheduled to fire
- */
- bool _pending_timeout;
-
- /*
- * set_interrupt has been called and _cur_match_time is valid
- */
- bool _pending_match;
-
- /*
- * The function LowPowerTickerWrapper::fire_interrupt has been called
- * and an interrupt is expected.
- */
- bool _pending_fire_now;
-
- /*
- * It is safe to call intf->set_interrupt
- */
- bool _set_interrupt_allowed;
-
- /*
- * Last value written by LowPowerTickerWrapper::set_interrupt
- */
- timestamp_t _cur_match_time;
-
- /*
- * Time of last call to LowPowerTickerWrapper::set_interrupt
- */
- uint32_t _last_set_interrupt;
-
- /*
- * Time of last call to intf->set_interrupt
- */
- uint32_t _last_actual_set_interrupt;
-
- /*
- * Mask of valid bits from intf->read()
- */
- uint32_t _mask;
-
- /*
- * Microsecond per low power tick (rounded up)
- */
- uint32_t _us_per_tick;
-
-
- void _reset();
-
- /**
- * Set the low power ticker match time when hardware is ready
- *
- * This event is scheduled to set the lp timer after the previous write
- * has taken effect and it is safe to write a new value without blocking.
- * If the time has already passed then this function fires and interrupt
- * immediately.
- */
- void _timeout_handler();
-
- /*
- * Check match time has passed
- */
- bool _match_check(timestamp_t current);
-
- /*
- * Convert low power ticks to approximate microseconds
- *
- * This value is always larger or equal to exact value.
- */
- uint32_t _lp_ticks_to_us(uint32_t);
-
- /*
- * Schedule a match interrupt to fire at the correct time
- *
- * @param current The current low power ticker time
- */
- void _schedule_match(timestamp_t current);
-
-};
-
-#endif
-
-/** @}*/
-
-
--- a/STM32F103C8T6_MPA/mbed/hal/analogin_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_API_H
-#define MBED_ANALOGIN_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Analogin hal structure. analogin_s is declared in the target's hal
- */
-typedef struct analogin_s analogin_t;
-
-/**
- * \defgroup hal_analogin Analogin hal functions
- * @{
- */
-
-/** Initialize the analogin peripheral
- *
- * Configures the pin used by analogin.
- * @param obj The analogin object to initialize
- * @param pin The analogin pin name
- */
-void analogin_init(analogin_t *obj, PinName pin);
-
-/** Read the input voltage, represented as a float in the range [0.0, 1.0]
- *
- * @param obj The analogin object
- * @return A floating value representing the current input voltage
- */
-float analogin_read(analogin_t *obj);
-
-/** Read the value from analogin pin, represented as an unsigned 16bit value
- *
- * @param obj The analogin object
- * @return An unsigned 16bit value representing the current input voltage
- */
-uint16_t analogin_read_u16(analogin_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/analogout_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,94 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_API_H
-#define MBED_ANALOGOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Analogout hal structure. dac_s is declared in the target's hal
- */
-typedef struct dac_s dac_t;
-
-/**
- * \defgroup hal_analogout Analogout hal functions
- * @{
- */
-
-/** Initialize the analogout peripheral
- *
- * Configures the pin used by analogout.
- * @param obj The analogout object to initialize
- * @param pin The analogout pin name
- */
-void analogout_init(dac_t *obj, PinName pin);
-
-/** Release the analogout object
- *
- * Note: This is not currently used in the mbed-drivers
- * @param obj The analogout object
- */
-void analogout_free(dac_t *obj);
-
-/** Set the output voltage, specified as a percentage (float)
- *
- * @param obj The analogin object
- * @param value The floating-point output voltage to be set
- */
-void analogout_write(dac_t *obj, float value);
-
-/** Set the output voltage, specified as unsigned 16-bit
- *
- * @param obj The analogin object
- * @param value The unsigned 16-bit output voltage to be set
- */
-void analogout_write_u16(dac_t *obj, uint16_t value);
-
-/** Read the current voltage value on the pin
- *
- * @param obj The analogin object
- * @return A floating-point value representing the current voltage on the pin,
- * measured as a percentage
- */
-float analogout_read(dac_t *obj);
-
-/** Read the current voltage value on the pin, as a normalized unsigned 16bit value
- *
- * @param obj The analogin object
- * @return An unsigned 16-bit value representing the current voltage on the pin
- */
-uint16_t analogout_read_u16(dac_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/buffer.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2014-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUFFER_H
-#define MBED_BUFFER_H
-
-#include <stddef.h>
-
-/** Generic buffer structure
- */
-typedef struct buffer_s {
- void *buffer; /**< the pointer to a buffer */
- size_t length; /**< the buffer length */
- size_t pos; /**< actual buffer position */
- uint8_t width; /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
-} buffer_t;
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/can_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,87 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2016 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_API_H
-#define MBED_CAN_API_H
-
-#include "device.h"
-
-#if DEVICE_CAN
-
-#include "PinNames.h"
-#include "PeripheralNames.h"
-#include "hal/can_helper.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
- IRQ_RX,
- IRQ_TX,
- IRQ_ERROR,
- IRQ_OVERRUN,
- IRQ_WAKEUP,
- IRQ_PASSIVE,
- IRQ_ARB,
- IRQ_BUS,
- IRQ_READY
-} CanIrqType;
-
-
-typedef enum {
- MODE_RESET,
- MODE_NORMAL,
- MODE_SILENT,
- MODE_TEST_LOCAL,
- MODE_TEST_GLOBAL,
- MODE_TEST_SILENT
-} CanMode;
-
-typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
-
-typedef struct can_s can_t;
-
-void can_init(can_t *obj, PinName rd, PinName td);
-void can_init_freq(can_t *obj, PinName rd, PinName td, int hz);
-void can_free(can_t *obj);
-int can_frequency(can_t *obj, int hz);
-
-void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id);
-void can_irq_free(can_t *obj);
-void can_irq_set(can_t *obj, CanIrqType irq, uint32_t enable);
-
-int can_write(can_t *obj, CAN_Message, int cc);
-int can_read(can_t *obj, CAN_Message *msg, int handle);
-int can_mode(can_t *obj, CanMode mode);
-int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
-void can_reset(can_t *obj);
-unsigned char can_rderror(can_t *obj);
-unsigned char can_tderror(can_t *obj);
-void can_monitor(can_t *obj, int silent);
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif // MBED_CAN_API_H
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/can_helper.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_HELPER_H
-#define MBED_CAN_HELPER_H
-
-#if DEVICE_CAN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- *
- * \enum CANFormat
- *
- * \brief Values that represent CAN Format
-**/
-enum CANFormat {
- CANStandard = 0,
- CANExtended = 1,
- CANAny = 2
-};
-typedef enum CANFormat CANFormat;
-
-/**
- *
- * \enum CANType
- *
- * \brief Values that represent CAN Type
-**/
-enum CANType {
- CANData = 0,
- CANRemote = 1
-};
-typedef enum CANType CANType;
-
-/**
- *
- * \struct CAN_Message
- *
- * \brief Holder for single CAN message.
- *
-**/
-struct CAN_Message {
- unsigned int id; // 29 bit identifier
- unsigned char data[8]; // Data field
- unsigned char len; // Length of data field in bytes
- CANFormat format; // Format ::CANFormat
- CANType type; // Type ::CANType
-};
-typedef struct CAN_Message CAN_Message;
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif
-
-#endif // MBED_CAN_HELPER_H
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/crc_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,246 +0,0 @@
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CRC_HAL_API_H
-#define MBED_CRC_HAL_API_H
-
-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-/** CRC Polynomial value
- *
- * Different polynomial values supported
- */
-typedef enum crc_polynomial {
- POLY_OTHER = 0,
- POLY_8BIT_CCITT = 0x07, // x8+x2+x+1
- POLY_7BIT_SD = 0x9, // x7+x3+1;
- POLY_16BIT_CCITT = 0x1021, // x16+x12+x5+1
- POLY_16BIT_IBM = 0x8005, // x16+x15+x2+1
- POLY_32BIT_ANSI = 0x04C11DB7, // x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
- POLY_32BIT_REV_ANSI = 0xEDB88320
-} crc_polynomial_t;
-
-typedef struct crc_mbed_config {
- /** CRC Polynomial. Example polynomial: 0x21 = 0010_0011 = x^5+x+1 */
- uint32_t polynomial;
- /** CRC Bit Width */
- uint32_t width;
- /** Initial seed value for the computation. */
- uint32_t initial_xor;
- /** Final xor value for the computation. */
- uint32_t final_xor;
- /** Reflect bits on input. */
- bool reflect_in;
- /** Reflect bits in final result before returning. */
- bool reflect_out;
-} crc_mbed_config_t;
-
-#if DEVICE_CRC
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_crc Hardware CRC
- *
- * The Hardware CRC HAL API provides a low-level interface to the Hardware CRC
- * module of a target platform.
- *
- * # Defined behaviour
- *
- * * Function hal_crc_is_supported() returns true if platform supports hardware
- * CRC for the given polynomial/width - verified by test ::crc_is_supported_test.
- * * Function hal_crc_is_supported() returns false if platform does not support hardware
- * CRC for the given polynomial/width - verified by test ::crc_is_supported_test.
- * * Function hal_crc_is_supported() returns false if given pointer to configuration
- * structure is undefined (NULL) - verified by test ::crc_is_supported_invalid_param_test.
- * * If CRC module does not support one of the following settings: initial_xor, final_xor
- * reflect_in, reflect_out, then these operations should be handled by the driver
- * - Verified by test ::crc_calc_single_test.
- * * Platform which supports hardware CRC must be able to handle at least one of the predefined
- * polynomial/width configurations that can be constructed in the MbedCRC class: POLY_8BIT_CCITT,
- * POLY_7BIT_SD, POLY_16BIT_CCITT, POLY_16BIT_IBM, POLY_32BIT_ANSI
- * - verified by test ::crc_is_supported_test, ::crc_calc_single_test.
- * * Function hal_crc_compute_partial_start() configures CRC module with the given configuration
- * - Verified by test ::crc_calc_single_test.
- * * Calling hal_crc_compute_partial_start() without finalising the
- * CRC calculation overrides the current configuration - Verified by test ::crc_reconfigure_test.
- * * Function hal_crc_compute_partial() writes data to the CRC module - verified by test ::crc_calc_single_test.
- * * Function hal_crc_compute_partial() can be call multiple times in succession in order to
- * provide additional data to CRC module - verified by test ::crc_calc_multi_test.
- * * Function hal_crc_compute_partial() does nothing if pointer to buffer is undefined or
- * data length is equal to 0 - verified by test ::crc_compute_partial_invalid_param_test.
- * * Function hal_crc_get_result() returns the checksum result from the CRC module
- * - verified by tests ::crc_calc_single_test, ::crc_calc_multi_test, ::crc_reconfigure_test.
- *
- * # Undefined behaviour
- *
- * * Calling hal_crc_compute_partial_start() function with invalid (unsupported) polynomial.
- * * Calling hal_crc_compute_partial() or hal_crc_get_result() functions before hal_crc_compute_partial_start().
- * * Calling hal_crc_get_result() function multiple times.
- *
- * # Non-functional requirements
- *
- * * CRC configuration provides the following settings:
- * * polynomial - CRC Polynomial,
- * * width - CRC bit width,
- * * initial_xor - seed value for the computation,
- * * final_xor - final xor value for the computation,
- * * reflect_in - reflect bits on input,
- * * reflect_out - reflect bits in final result before returning.
- *
- * # Potential bugs
- *
- * @{
- */
-
-/**
- * \defgroup hal_crc_tests crc hal tests
- * The crc HAL tests ensure driver conformance to defined behaviour.
- *
- * To run the crc hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-crc*
- *
- */
-
-/** Determine if the current platform supports hardware CRC for given polynomial
- *
- * The purpose of this function is to inform the CRC Platform API whether the
- * current platform has a hardware CRC module and that it can support the
- * requested polynomial.
- *
- * Supported polynomials are restricted to the named polynomials that can be
- * constructed in the MbedCRC class, POLY_8BIT_CCITT, POLY_7BIT_SD,
- * POLY_16BIT_CCITT, POLY_16BIT_IBM and POLY_32BIT_ANSI.
- *
- * The current platform must support the given polynomials default parameters
- * in order to return a true response. These include: reflect in, reflect out,
- * initial xor and final xor. For example, POLY_32BIT_ANSI requires an initial
- * and final xor of 0xFFFFFFFF, and reflection of both input and output. If any
- * of these settings cannot be configured, the polynomial is not supported.
- *
- * This function is thread safe; it safe to call from multiple contexts if
- * required.
- *
- * \param config Contains CRC configuration parameters for initializing the
- * hardware CRC module. For example, polynomial and initial seed
- * values.
- *
- * \return True if running if the polynomial is supported, false if not.
- */
-bool hal_crc_is_supported(const crc_mbed_config_t *config);
-
-/** Initialize the hardware CRC module with the given polynomial
- *
- * After calling this function, the CRC HAL module is ready to receive data
- * using the hal_crc_compute_partial() function. The CRC module on the board
- * is configured internally with the specified configuration and is ready
- * to receive data.
- *
- * The platform configures itself based on the default configuration
- * parameters of the input polynomial.
- *
- * This function must be called before calling hal_crc_compute_partial().
- *
- * This function must be called with a valid polynomial supported by the
- * platform. The polynomial must be checked for support using the
- * hal_crc_is_supported() function.
- *
- * Calling hal_crc_compute_partial_start() multiple times without finalizing the
- * CRC calculation with hal_crc_get_result() overrides the current
- * configuration and state, and the intermediate result of the computation is
- * lost.
- *
- * This function is not thread safe. A CRC calculation must not be started from
- * two different threads or contexts at the same time; calling this function
- * from two different contexts may lead to configurations being overwritten and
- * results being lost.
- *
- * \param config Contains CRC configuration parameters for initializing the
- * hardware CRC module. For example, polynomial and initial seed
- * values.
- */
-void hal_crc_compute_partial_start(const crc_mbed_config_t *config);
-
-/** Writes data to the current CRC module.
- *
- * Writes input data buffer bytes to the CRC data register. The CRC module
- * must interpret the data as an array of bytes.
- *
- * The final transformations are not applied to the data; the CRC module must
- * retain the intermediate result so that additional calls to this function
- * can be made, appending the additional data to the calculation.
- *
- * To obtain the final result of the CRC calculation, hal_crc_get_result() is
- * called to apply the final transformations to the data.
- *
- * If the function is passed an undefined pointer, or the size of the buffer is
- * specified to be 0, this function does nothing and returns.
- *
- * This function can be called multiple times in succession. This can be used
- * to calculate the CRC result of streamed data.
- *
- * This function is not thread safe. There is only one instance of the CRC
- * module active at a time. Calling this function from multiple contexts
- * appends different data to the same, single instance of the module, which causes an
- * erroneous value to be calculated.
- *
- * \param data Input data stream to be written into the CRC calculation
- * \param size Size of the data stream in bytes
- */
-void hal_crc_compute_partial(const uint8_t *data, const size_t size);
-
-/* Reads the checksum result from the CRC module.
- *
- * Reads the final checksum result for the final checksum value. The returned
- * value is cast as an unsigned 32-bit integer. The actual size of the returned
- * result depends on the polynomial used to configure the CRC module.
- *
- * Additional transformations that are used in the default configuration of the
- * input polynomial are applied to the result before it is returned from this
- * function. These transformations include: the final xor being appended to the
- * calculation, and the result being reflected if required.
- *
- * Calling this function multiple times is undefined. The first call to this
- * function returns the final result of the CRC calculation. The return
- * value on successive calls is undefined because the contents of the register after
- * accessing them is platform-specific.
- *
- * This function is not thread safe. There is only one instance of the CRC
- * module active at a time. Calling this function from multiple contexts may
- * return incorrect data or affect the current state of the module.
- *
- * \return The final CRC checksum after the reflections and final calculations
- * have been applied.
- */
-uint32_t hal_crc_get_result(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif // DEVICE_CRC
-#endif // MBED_CRC_HAL_API_H
-
-/**@}*/
--- a/STM32F103C8T6_MPA/mbed/hal/critical_section_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,108 +0,0 @@
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CRITICAL_SECTION_API_H
-#define MBED_CRITICAL_SECTION_API_H
-
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_critical Critical Section HAL functions
- * @{
- */
-
-/**
- * Mark the start of a critical section
- *
- * This function will be called by core_util_critical_section_enter() each time
- * the application requests to enter a critical section. The purpose of the
- * critical section is to ensure mutual-exclusion synchronisation of the
- * processor by preventing any change in processor control, the default
- * behaviour requires storing the state of interrupts in the system before
- * disabling them.
- *
- * The critical section code supports nesting. When a thread has entered a
- * critical section it can make additional calls to
- * core_util_critical_section_enter() without deadlocking itself. The critical
- * section driver API tracks the number of nested calls to the critical section.
- * The critical section will only be exited when
- * core_util_critical_section_exit() has been called once for each time it
- * entered the critical section.
- *
- * On the first call to enter a critical section this function MUST store the
- * state of any interrupts or other application settings it will modify to
- * facilitate the critical section.
- *
- * Each successive call to enter the critical section MUST ignore storing or
- * modifying any application state.
- *
- * The default implementation of this function which will save the current state
- * of interrupts before disabling them. This implementation can be found in
- * mbed_critical_section_api.c. This behaviour is can be overridden on a per
- * platform basis by providing a different implementation within the correct
- * targets directory.
- */
-void hal_critical_section_enter(void);
-
-
-/** Mark the end of a critical section.
- *
- * The purpose of this function is to restore any state that was modified upon
- * entering the critical section, allowing other threads or interrupts to change
- * the processor control.
- *
- * This function will be called once by core_util_critical_section_exit() per
- * critical section on last call to exit. When called, the application MUST
- * restore the saved interrupt/application state that was saved when entering
- * the critical section.
- *
- * There is a default implementation of this function, it will restore the state
- * of interrupts that were previously saved when hal_critical_section_enter was
- * first called, this implementation can be found in
- * mbed_critical_section_api.c. This behaviour is overridable by providing a
- * different function implementation within the correct targets directory.
- */
-void hal_critical_section_exit(void);
-
-
-/** Determine if the application is currently running in a critical section
- *
- * The purpose of this function is to inform the caller whether or not the
- * application is running in a critical section. This is done by checking if
- * the current interrupt state has been saved in the underlying implementation,
- * this could also be done by checking the state of the interrupts at the time
- * of calling.
- *
- * @return True if running in a critical section, false if not.
- */
-bool hal_in_critical_section(void);
-
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // MBED_CRITICAL_SECTION_API_H
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/dma_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2014-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DMA_API_H
-#define MBED_DMA_API_H
-
-#include <stdint.h>
-
-#define DMA_ERROR_OUT_OF_CHANNELS (-1)
-
-typedef enum {
- DMA_USAGE_NEVER,
- DMA_USAGE_OPPORTUNISTIC,
- DMA_USAGE_ALWAYS,
- DMA_USAGE_TEMPORARY_ALLOCATED,
- DMA_USAGE_ALLOCATED
-} DMAUsage;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void dma_init(void);
-
-int dma_channel_allocate(uint32_t capabilities);
-
-int dma_channel_free(int channelid);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/ethernet_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_API_H
-#define MBED_ETHERNET_API_H
-
-#include "device.h"
-
-#if DEVICE_ETHERNET
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Connection constants
-
-int ethernet_init(void);
-void ethernet_free(void);
-
-// write size bytes from data to ethernet buffer
-// return num bytes written
-// or -1 if size is too big
-int ethernet_write(const char *data, int size);
-
-// send ethernet write buffer, returning the packet size sent
-int ethernet_send(void);
-
-// receive from ethernet buffer, returning packet size, or 0 if no packet
-int ethernet_receive(void);
-
-// read size bytes in to data, return actual num bytes read (0..size)
-// if data == NULL, throw the bytes away
-int ethernet_read(char *data, int size);
-
-// get the ethernet address
-void ethernet_address(char *mac);
-
-// see if the link is up
-int ethernet_link(void);
-
-// force link settings
-void ethernet_set_link(int speed, int duplex);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/flash_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,138 +0,0 @@
-/** \addtogroup hal */
-/** @{*/
-
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FLASH_API_H
-#define MBED_FLASH_API_H
-
-#include "device.h"
-#include <stdint.h>
-
-#if DEVICE_FLASH
-
-#define MBED_FLASH_INVALID_SIZE 0xFFFFFFFF
-
-typedef struct flash_s flash_t;
-
-#if TARGET_FLASH_CMSIS_ALGO
-#include "flash_data.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup flash_hal Flash HAL API
- * @{
- */
-
-/** Initialize the flash peripheral and the flash_t object
- *
- * @param obj The flash object
- * @return 0 for success, -1 for error
- */
-int32_t flash_init(flash_t *obj);
-
-/** Uninitialize the flash peripheral and the flash_t object
- *
- * @param obj The flash object
- * @return 0 for success, -1 for error
- */
-int32_t flash_free(flash_t *obj);
-
-/** Erase one sector starting at defined address
- *
- * The address should be at sector boundary. This function does not do any check for address alignments
- * @param obj The flash object
- * @param address The sector starting address
- * @return 0 for success, -1 for error
- */
-int32_t flash_erase_sector(flash_t *obj, uint32_t address);
-
-/** Read data starting at defined address
- *
- * This function has a WEAK implementation using memcpy for backwards compatibility.
- * @param obj The flash object
- * @param address Address to begin reading from
- * @param data The buffer to read data into
- * @param size The number of bytes to read
- * @return 0 for success, -1 for error
- */
-int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size);
-
-/** Program pages starting at defined address
- *
- * The pages should not cross multiple sectors.
- * This function does not do any check for address alignments or if size is aligned to a page size.
- * @param obj The flash object
- * @param address The sector starting address
- * @param data The data buffer to be programmed
- * @param size The number of bytes to program
- * @return 0 for success, -1 for error
- */
-int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size);
-
-/** Get sector size
- *
- * @param obj The flash object
- * @param address The sector starting address
- * @return The size of a sector
- */
-uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
-
-/** Get page size
- *
- * The page size defines the writable page size
- * @param obj The flash object
- * @return The size of a page
- */
-uint32_t flash_get_page_size(const flash_t *obj);
-
-/** Get start address for the flash region
- *
- * @param obj The flash object
- * @return The start address for the flash region
- */
-uint32_t flash_get_start_address(const flash_t *obj);
-
-/** Get the flash region size
- *
- * @param obj The flash object
- * @return The flash region size
- */
-uint32_t flash_get_size(const flash_t *obj);
-
-/** Get the flash erase value
- *
- * @param obj The flash object
- * @return The flash erase value
- */
-uint8_t flash_get_erase_value(const flash_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/flash_data.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,102 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FLASH_DATA_H
-#define MBED_FLASH_DATA_H
-
-#include <stdint.h>
-
-/** Target flash algorithm structure
- */
-typedef struct {
- const uint32_t init; /**< Init function address */
- const uint32_t uninit; /**< Uninit function address */
- const uint32_t erase_sector; /**< Erase sector function address */
- const uint32_t program_page; /**< Program page function address */
- const uint32_t static_base; /**< Static base address */
- uint32_t *algo_blob; /**< Pointer to flash algo binary blob */
-} flash_algo_t;
-
-/** Sector information structure
- */
-typedef struct {
- const uint32_t start; /**< Sector start address */
- const uint32_t size; /**< Sector size */
-} sector_info_t;
-
-/** Flash configuration structure
- */
-typedef struct {
- const uint32_t page_size; /**< The minimum program page size that can be written */
- const uint32_t flash_start; /**< Start address of the flash <0, flash_size) */
- const uint32_t flash_size; /**< Flash size. The size is accumulative sum of all sector sizes */
- const sector_info_t *sectors; /**< List of sectors - sector can vary in sizes */
- const uint32_t sector_info_count; /**< Number of sectors */
-} flash_target_config_t;
-
-/** Target flash configuration
- * For targets not supporting TrustZone, its flash_set_target_config must define target_config.
- * For targets supporting TrustZone, it has the following requirements:
- * -# Flash IAP H/W can only configure to secure. It can access both secure/non-secure flash.
- * -# Flash IAP port is for secure build only. It exports secure functions for non-secure build.
- * -# In Flash IAP port, flash_set_target_config must define both target_config/target_config_ns for secure/non-secure flash respectively.
- * -# Non-secure application can access its non-secure flash only through secure flash IAP functions. It cannot access secure flash.
- */
-struct flash_s {
- const flash_target_config_t *target_config; /**< Normal/secure flash configuration structure for targets not supporting/supporting TrustZone */
-#if defined(__CORTEX_M23) || defined(__CORTEX_M33)
- const flash_target_config_t *target_config_ns; /**< Non-secure flash configuration structure for targets supporting TrustZone */
-#endif
- const flash_algo_t *flash_algo;
-};
-
-/** Flash algo argument structure
- * Contains all registers that should be preserved
- */
-typedef struct {
- uint32_t r0;
- uint32_t r1;
- uint32_t r2;
- uint32_t r3;
- uint32_t r9;
- uint32_t pc;
-} args_t;
-
-typedef int32_t (*flash_algo_jump_t)(args_t *);
-
-// prototypes for flash algo CMSIS API
-
-typedef int (*CMSIS_Algo_Function_Init)(unsigned long adr, unsigned long clk, unsigned long fnc);
-typedef int (*CMSIS_Algo_Function_UnInit)(unsigned long fnc);
-typedef int (*CMSIS_Algo_Function_EraseSector)(unsigned long adr);
-typedef int (*CMSIS_Algo_Function_EraseChip)(void);
-typedef int (*CMSIS_Algo_Function_ProgramPage)(unsigned long adr, unsigned long sz, unsigned char *buf);
-typedef unsigned long (*CMSIS_Algo_Function_Verify)(unsigned long adr, unsigned long sz, unsigned char *buf);
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Set target configuration
- */
-void flash_set_target_config(flash_t *obj);
-
-#ifdef __cplusplus
-};
-#endif
-
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/hal/gpio_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,134 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_API_H
-#define MBED_GPIO_API_H
-
-#include <stdint.h>
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_gpio GPIO HAL functions
- * @{
- */
-
-/** Set the given pin as GPIO
- *
- * @param pin The pin to be set as GPIO
- * @return The GPIO port mask for this pin
- **/
-uint32_t gpio_set(PinName pin);
-/* Checks if gpio object is connected (pin was not initialized with NC)
- * @param pin The pin to be set as GPIO
- * @return 0 if port is initialized with NC
- **/
-int gpio_is_connected(const gpio_t *obj);
-
-/** Initialize the GPIO pin
- *
- * @param obj The GPIO object to initialize
- * @param pin The GPIO pin to initialize
- */
-void gpio_init(gpio_t *obj, PinName pin);
-
-/** Set the input pin mode
- *
- * @param obj The GPIO object
- * @param mode The pin mode to be set
- */
-void gpio_mode(gpio_t *obj, PinMode mode);
-
-/** Set the pin direction
- *
- * @param obj The GPIO object
- * @param direction The pin direction to be set
- */
-void gpio_dir(gpio_t *obj, PinDirection direction);
-
-/** Set the output value
- *
- * @param obj The GPIO object
- * @param value The value to be set
- */
-void gpio_write(gpio_t *obj, int value);
-
-/** Read the input value
- *
- * @param obj The GPIO object
- * @return An integer value 1 or 0
- */
-int gpio_read(gpio_t *obj);
-
-// the following functions are generic and implemented in the common gpio.c file
-// TODO: fix, will be moved to the common gpio header file
-
-/** Init the input pin and set mode to PullDefault
- *
- * @param gpio The GPIO object
- * @param pin The pin name
- */
-void gpio_init_in(gpio_t *gpio, PinName pin);
-
-/** Init the input pin and set the mode
- *
- * @param gpio The GPIO object
- * @param pin The pin name
- * @param mode The pin mode to be set
- */
-void gpio_init_in_ex(gpio_t *gpio, PinName pin, PinMode mode);
-
-/** Init the output pin as an output, with predefined output value 0
- *
- * @param gpio The GPIO object
- * @param pin The pin name
- * @return An integer value 1 or 0
- */
-void gpio_init_out(gpio_t *gpio, PinName pin);
-
-/** Init the pin as an output and set the output value
- *
- * @param gpio The GPIO object
- * @param pin The pin name
- * @param value The value to be set
- */
-void gpio_init_out_ex(gpio_t *gpio, PinName pin, int value);
-
-/** Init the pin to be in/out
- *
- * @param gpio The GPIO object
- * @param pin The pin name
- * @param direction The pin direction to be set
- * @param mode The pin mode to be set
- * @param value The value to be set for an output pin
- */
-void gpio_init_inout(gpio_t *gpio, PinName pin, PinDirection direction, PinMode mode, int value);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/gpio_irq_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_IRQ_API_H
-#define MBED_GPIO_IRQ_API_H
-
-#include "device.h"
-
-#if DEVICE_INTERRUPTIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** GPIO IRQ events
- */
-typedef enum {
- IRQ_NONE,
- IRQ_RISE,
- IRQ_FALL
-} gpio_irq_event;
-
-/** GPIO IRQ HAL structure. gpio_irq_s is declared in the target's HAL
- */
-typedef struct gpio_irq_s gpio_irq_t;
-
-typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
-
-/**
- * \defgroup hal_gpioirq GPIO IRQ HAL functions
- * @{
- */
-
-/** Initialize the GPIO IRQ pin
- *
- * @param obj The GPIO object to initialize
- * @param pin The GPIO pin name
- * @param handler The handler to be attached to GPIO IRQ
- * @param id The object ID (id != 0, 0 is reserved)
- * @return -1 if pin is NC, 0 otherwise
- */
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
-
-/** Release the GPIO IRQ PIN
- *
- * @param obj The gpio object
- */
-void gpio_irq_free(gpio_irq_t *obj);
-
-/** Enable/disable pin IRQ event
- *
- * @param obj The GPIO object
- * @param event The GPIO IRQ event
- * @param enable The enable flag
- */
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
-
-/** Enable GPIO IRQ
- *
- * This is target dependent, as it might enable the entire port or just a pin
- * @param obj The GPIO object
- */
-void gpio_irq_enable(gpio_irq_t *obj);
-
-/** Disable GPIO IRQ
- *
- * This is target dependent, as it might disable the entire port or just a pin
- * @param obj The GPIO object
- */
-void gpio_irq_disable(gpio_irq_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/i2c_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,255 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_API_H
-#define MBED_I2C_API_H
-
-#include "device.h"
-#include "hal/buffer.h"
-
-#if DEVICE_I2C_ASYNCH
-#include "hal/dma_api.h"
-#endif
-
-#if DEVICE_I2C
-
-/**
- * @defgroup hal_I2CEvents I2C Events Macros
- *
- * @{
- */
-#define I2C_EVENT_ERROR (1 << 1)
-#define I2C_EVENT_ERROR_NO_SLAVE (1 << 2)
-#define I2C_EVENT_TRANSFER_COMPLETE (1 << 3)
-#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
-#define I2C_EVENT_ALL (I2C_EVENT_ERROR | I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
-
-/**@}*/
-
-#if DEVICE_I2C_ASYNCH
-/** Asynch I2C HAL structure
- */
-typedef struct {
- struct i2c_s i2c; /**< Target specific I2C structure */
- struct buffer_s tx_buff; /**< Tx buffer */
- struct buffer_s rx_buff; /**< Rx buffer */
-} i2c_t;
-
-#else
-/** Non-asynch I2C HAL structure
- */
-typedef struct i2c_s i2c_t;
-
-#endif
-
-enum {
- I2C_ERROR_NO_SLAVE = -1,
- I2C_ERROR_BUS_BUSY = -2
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_GeneralI2C I2C Configuration Functions
- * @{
- */
-
-/** Initialize the I2C peripheral. It sets the default parameters for I2C
- * peripheral, and configures its specifieds pins.
- *
- * @param obj The I2C object
- * @param sda The sda pin
- * @param scl The scl pin
- */
-void i2c_init(i2c_t *obj, PinName sda, PinName scl);
-
-/** Configure the I2C frequency
- *
- * @param obj The I2C object
- * @param hz Frequency in Hz
- */
-void i2c_frequency(i2c_t *obj, int hz);
-
-/** Send START command
- *
- * @param obj The I2C object
- */
-int i2c_start(i2c_t *obj);
-
-/** Send STOP command
- *
- * @param obj The I2C object
- */
-int i2c_stop(i2c_t *obj);
-
-/** Blocking reading data
- *
- * @param obj The I2C object
- * @param address 7-bit address (last bit is 1)
- * @param data The buffer for receiving
- * @param length Number of bytes to read
- * @param stop Stop to be generated after the transfer is done
- * @return Number of read bytes
- */
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
-
-/** Blocking sending data
- *
- * @param obj The I2C object
- * @param address 7-bit address (last bit is 0)
- * @param data The buffer for sending
- * @param length Number of bytes to write
- * @param stop Stop to be generated after the transfer is done
- * @return
- * zero or non-zero - Number of written bytes
- * negative - I2C_ERROR_XXX status
- */
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
-
-/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop()
- *
- * @param obj The I2C object
- */
-void i2c_reset(i2c_t *obj);
-
-/** Read one byte
- *
- * @param obj The I2C object
- * @param last Acknoledge
- * @return The read byte
- */
-int i2c_byte_read(i2c_t *obj, int last);
-
-/** Write one byte
- *
- * @param obj The I2C object
- * @param data Byte to be written
- * @return 0 if NAK was received, 1 if ACK was received, 2 for timeout.
- */
-int i2c_byte_write(i2c_t *obj, int data);
-
-/**@}*/
-
-#if DEVICE_I2CSLAVE
-
-/**
- * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
- * @{
- */
-
-/** Configure I2C as slave or master.
- * @param obj The I2C object
- * @param enable_slave Enable i2c hardware so you can receive events with ::i2c_slave_receive
- * @return non-zero if a value is available
- */
-void i2c_slave_mode(i2c_t *obj, int enable_slave);
-
-/** Check to see if the I2C slave has been addressed.
- * @param obj The I2C object
- * @return The status - 1 - read addresses, 2 - write to all slaves,
- * 3 write addressed, 0 - the slave has not been addressed
- */
-int i2c_slave_receive(i2c_t *obj);
-
-/** Configure I2C as slave or master.
- * @param obj The I2C object
- * @param data The buffer for receiving
- * @param length Number of bytes to read
- * @return non-zero if a value is available
- */
-int i2c_slave_read(i2c_t *obj, char *data, int length);
-
-/** Configure I2C as slave or master.
- * @param obj The I2C object
- * @param data The buffer for sending
- * @param length Number of bytes to write
- * @return non-zero if a value is available
- */
-int i2c_slave_write(i2c_t *obj, const char *data, int length);
-
-/** Configure I2C address.
- * @param obj The I2C object
- * @param idx Currently not used
- * @param address The address to be set
- * @param mask Currently not used
- */
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
-
-#endif
-
-/**@}*/
-
-#if DEVICE_I2C_ASYNCH
-
-/**
- * \defgroup hal_AsynchI2C Asynchronous I2C Hardware Abstraction Layer
- * @{
- */
-
-/** Start I2C asynchronous transfer
- *
- * @param obj The I2C object
- * @param tx The transmit buffer
- * @param tx_length The number of bytes to transmit
- * @param rx The receive buffer
- * @param rx_length The number of bytes to receive
- * @param address The address to be set - 7bit or 9bit
- * @param stop If true, stop will be generated after the transfer is done
- * @param handler The I2C IRQ handler to be set
- * @param event Event mask for the transfer. See \ref hal_I2CEvents
- * @param hint DMA hint usage
- */
-void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** The asynchronous IRQ handler
- *
- * @param obj The I2C object which holds the transfer information
- * @return Event flags if a transfer termination condition was met, otherwise return 0.
- */
-uint32_t i2c_irq_handler_asynch(i2c_t *obj);
-
-/** Attempts to determine if the I2C peripheral is already in use
- *
- * @param obj The I2C object
- * @return Non-zero if the I2C module is active or zero if it is not
- */
-uint8_t i2c_active(i2c_t *obj);
-
-/** Abort asynchronous transfer
- *
- * This function does not perform any check - that should happen in upper layers.
- * @param obj The I2C object
- */
-void i2c_abort_asynch(i2c_t *obj);
-
-#endif
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/itm_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_ITM_API_H
-#define MBED_ITM_API_H
-
-#if DEVICE_ITM
-
-#include <stdint.h>
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup itm_hal Instrumented Trace Macrocell HAL API
- * @{
- */
-
-enum {
- ITM_PORT_SWO = 0
-};
-
-/**
- * @brief Target specific initialization function.
- * This function is responsible for initializing and configuring
- * the debug clock for the ITM and setting up the SWO pin for
- * debug output.
- *
- * The only Cortex-M register that should be modified is the clock
- * prescaler in TPI->ACPR.
- *
- * The generic mbed_itm_init initialization function will setup:
- *
- * ITM->LAR
- * ITM->TPR
- * ITM->TCR
- * ITM->TER
- * TPI->SPPR
- * TPI->FFCR
- * DWT->CTRL
- *
- * for SWO output on stimulus port 0.
- */
-void itm_init(void);
-
-/**
- * @brief Initialization function for both generic registers and target specific clock and pin.
- */
-void mbed_itm_init(void);
-
-/**
- * @brief Send data over ITM stimulus port.
- *
- * @param[in] port The stimulus port to send data over.
- * @param[in] data The 32-bit data to send.
- *
- * The data is written as a single 32-bit write to the port.
- *
- * @return value of data sent.
- */
-uint32_t mbed_itm_send(uint32_t port, uint32_t data);
-
-/**
- * @brief Send a block of data over ITM stimulus port.
- *
- * @param[in] port The stimulus port to send data over.
- * @param[in] data The block of data to send.
- * @param[in] len The number of bytes of data to send.
- *
- * The data is written using multiple appropriately-sized port accesses for
- * efficient transfer.
- */
-void mbed_itm_send_block(uint32_t port, const void *data, size_t len);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif /* MBED_ITM_API_H */
-
-/**@}*/
--- a/STM32F103C8T6_MPA/mbed/hal/lp_ticker_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,248 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LPTICKER_API_H
-#define MBED_LPTICKER_API_H
-
-#include "device.h"
-
-#if DEVICE_LPTICKER
-
-#include "hal/ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_lp_ticker Low Power Ticker
- * Low level interface to the low power ticker of a target
- *
- * # Defined behavior
- * * Has a reported frequency between 4KHz and 64KHz - verified by ::lp_ticker_info_test
- * * Has a counter that is at least 12 bits wide - verified by ::lp_ticker_info_test
- * * Continues operating in deep sleep mode - verified by ::lp_ticker_deepsleep_test
- * * All behavior defined by the @ref hal_ticker_shared "ticker specification"
- *
- * # Undefined behavior
- * * See the @ref hal_ticker_shared "ticker specification"
- * * Calling any function other than lp_ticker_init after calling lp_ticker_free
- *
- * # Potential bugs
- * * Glitches due to ripple counter - Verified by ::lp_ticker_glitch_test
- *
- * @see hal_lp_ticker_tests
- *
- * @{
- */
-
-/**
- * \defgroup hal_lp_ticker_tests Low Power Ticker tests
- * Tests to validate the proper implementation of the low power ticker
- *
- * To run the low power ticker hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*,tests-mbed_hal-lp_ticker*
- *
- */
-
-typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
-
-/** Set low power ticker IRQ handler
- *
- * @param ticker_irq_handler IRQ handler to be connected
- *
- * @return previous ticker IRQ handler
- *
- * @note by default IRQ handler is set to ::ticker_irq_handler
- * @note this function is primarily for testing purposes and it's not required part of HAL implementation
- *
- */
-ticker_irq_handler_type set_lp_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
-
-/** Get low power ticker's data
- *
- * @return The low power ticker data
- */
-const ticker_data_t *get_lp_ticker_data(void);
-
-/** The wrapper for ticker_irq_handler, to pass lp ticker's data
- *
- */
-void lp_ticker_irq_handler(void);
-
-/* HAL lp ticker */
-
-/** Initialize the low power ticker
- *
- * Initialize or re-initialize the ticker. This resets all the
- * clocking and prescaler registers, along with disabling
- * the compare interrupt.
- *
- * Pseudo Code:
- * @code
- * void lp_ticker_init()
- * {
- * // Enable clock gate so processor can read LPTMR registers
- * POWER_CTRL |= POWER_CTRL_LPTMR_Msk;
- *
- * // Disable the timer and ensure it is powered down
- * LPTMR_CTRL &= ~(LPTMR_CTRL_ENABLE_Msk | LPTMR_CTRL_COMPARE_ENABLE_Msk);
- *
- * // Configure divisors - no division necessary
- * LPTMR_PRESCALE = 0;
- * LPTMR_CTRL |= LPTMR_CTRL_ENABLE_Msk;
- *
- * // Install the interrupt handler
- * NVIC_SetVector(LPTMR_IRQn, (uint32_t)lp_ticker_irq_handler);
- * NVIC_EnableIRQ(LPTMR_IRQn);
- * }
- * @endcode
- */
-void lp_ticker_init(void);
-
-/** Deinitialize the lower power ticker
- *
- * Powerdown the lp ticker in preparation for sleep, powerdown, or reset.
- *
- * After calling this function no other ticker functions should be called except
- * lp_ticker_init(). Calling any function other than init after freeing is
- * undefined.
- *
- * @note This function stops the ticker from counting.
- */
-void lp_ticker_free(void);
-
-/** Read the current tick
- *
- * If no rollover has occurred, the seconds passed since lp_ticker_init()
- * was called can be found by dividing the ticks returned by this function
- * by the frequency returned by ::lp_ticker_get_info.
- *
- * @return The current timer's counter value in ticks
- *
- * Pseudo Code:
- * @code
- * uint32_t lp_ticker_read()
- * {
- * uint16_t count;
- * uint16_t last_count;
- *
- * // Loop until the same tick is read twice since this
- * // is ripple counter on a different clock domain.
- * count = LPTMR_COUNT;
- * do {
- * last_count = count;
- * count = LPTMR_COUNT;
- * } while (last_count != count);
- *
- * return count;
- * }
- * @endcode
- */
-uint32_t lp_ticker_read(void);
-
-/** Set interrupt for specified timestamp
- *
- * @param timestamp The time in ticks to be set
- *
- * @note no special handling needs to be done for times in the past
- * as the common timer code will detect this and call
- * lp_ticker_fire_interrupt() if this is the case
- *
- * @note calling this function with timestamp of more than the supported
- * number of bits returned by ::lp_ticker_get_info results in undefined
- * behavior.
- *
- * Pseudo Code:
- * @code
- * void lp_ticker_set_interrupt(timestamp_t timestamp)
- * {
- * LPTMR_COMPARE = timestamp;
- * LPTMR_CTRL |= LPTMR_CTRL_COMPARE_ENABLE_Msk;
- * }
- * @endcode
- */
-void lp_ticker_set_interrupt(timestamp_t timestamp);
-
-/** Disable low power ticker interrupt
- *
- * Pseudo Code:
- * @code
- * void lp_ticker_disable_interrupt(void)
- * {
- * // Disable the compare interrupt
- * LPTMR_CTRL &= ~LPTMR_CTRL_COMPARE_ENABLE_Msk;
- * }
- * @endcode
- */
-void lp_ticker_disable_interrupt(void);
-
-/** Clear the low power ticker interrupt
- *
- * Pseudo Code:
- * @code
- * void lp_ticker_clear_interrupt(void)
- * {
- * // Write to the ICR (interrupt clear register) of the LPTMR
- * LPTMR_ICR = LPTMR_ICR_COMPARE_Msk;
- * }
- * @endcode
- */
-void lp_ticker_clear_interrupt(void);
-
-/** Set pending interrupt that should be fired right away.
- *
- * Pseudo Code:
- * @code
- * void lp_ticker_fire_interrupt(void)
- * {
- * NVIC_SetPendingIRQ(LPTMR_IRQn);
- * }
- * @endcode
- */
-void lp_ticker_fire_interrupt(void);
-
-/** Get frequency and counter bits of this ticker.
- *
- * Pseudo Code:
- * @code
- * const ticker_info_t* lp_ticker_get_info()
- * {
- * static const ticker_info_t info = {
- * 32768, // 32KHz
- * 16 // 16 bit counter
- * };
- * return &info;
- * }
- * @endcode
- */
-const ticker_info_t *lp_ticker_get_info(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/mbed_lp_ticker_wrapper.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LP_TICKER_WRAPPER_H
-#define MBED_LP_TICKER_WRAPPER_H
-
-#include "device.h"
-
-#if DEVICE_LPTICKER
-
-#include "hal/ticker_api.h"
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
-
-/**
- * Interrupt handler for the wrapped lp ticker
- *
- * @param handler the function which would normally be called by the
- * lp ticker handler when it is not wrapped
- */
-void lp_ticker_wrapper_irq_handler(ticker_irq_handler_type handler);
-
-/**
- * Get wrapped lp ticker data
- *
- * @param data hardware low power ticker object
- * @return wrapped low power ticker object
- */
-const ticker_data_t *get_lp_ticker_wrapper_data(const ticker_data_t *data);
-
-/**
- * Suspend the wrapper layer code
- *
- * Pass through all interrupts to the low power ticker and stop using
- * the microsecond ticker.
- *
- * @warning: Make sure to suspend the LP ticker first (call ticker_suspend()),
- * otherwise the behavior is undefined.
- */
-void lp_ticker_wrapper_suspend(void);
-
-/**
- * Resume the wrapper layer code
- *
- * Resume operation of the wrapper layer. Interrupts will be filtered
- * as normal and the microsecond timer will be used for interrupts scheduled
- * too quickly back-to-back.
- */
-void lp_ticker_wrapper_resume(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/mpu_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,122 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2018-2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_MPU_API_H
-#define MBED_MPU_API_H
-
-#include "device.h"
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_MPU
-
-/**
- * \defgroup hal_mpu MPU hal
- *
- * The MPU hal provides a simple MPU API to enhance device security by preventing
- * execution from ram.
- *
- * # Defined behavior
- * * The function ::mbed_mpu_init is safe to call repeatedly - Verified by ::mpu_init_test
- * * The function ::mbed_mpu_free disables MPU protection - Verified by ::mpu_free_test
- * * Execution from RAM results in a fault when execute never is enabled.
- * This RAM includes heap, stack, data and zero init - Verified by ::mpu_fault_test_data,
- * ::mpu_fault_test_bss, ::mpu_fault_test_stack and ::mpu_fault_test_heap.
- * * Writing to ROM results in a fault when write never is enabled - Not verified
- *
- * # Undefined behavior
- * * Calling any function other than ::mbed_mpu_init before the initialization of the MPU.
- *
- * @see hal_mpu_tests
- *
- * @{
- */
-
-/**
- * \defgroup hal_mpu_tests MPU hal tests
- * The MPU test validates proper implementation of the MPU hal.
- *
- * To run the MPU hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-mpu*
- */
-
-
-/**
- * Initialize the MPU
- *
- * Initialize or re-initialize the memory protection unit.
- * After initialization or re-initialization, ROM and RAM protection
- * are both enabled.
- */
-void mbed_mpu_init(void);
-
-/**
- * Enable or disable ROM MPU protection
- *
- * This function is used to mark all of ROM as read and execute only.
- * When enabled writes to ROM cause a fault.
- *
- * By default writes to ROM are disabled.
- *
- * @param enable true to disable writes to ROM, false otherwise
- */
-void mbed_mpu_enable_rom_wn(bool enable);
-
-/**
- * Enable or disable ram MPU protection
- *
- * This function is used to mark all of RAM as execute never.
- * When enabled code is only allowed to execute from flash.
- *
- * By default execution from RAM is disabled.
- *
- * @param enable true to disable execution from RAM, false otherwise
- */
-void mbed_mpu_enable_ram_xn(bool enable);
-
-/** Deinitialize the MPU
- *
- * Powerdown the MPU in preparation for powerdown, reset or jumping to another application.
- */
-void mbed_mpu_free(void);
-
-/**@}*/
-
-#else
-
-#define mbed_mpu_init()
-
-#define mbed_mpu_enable_rom_wn(enable) (void)enable
-
-#define mbed_mpu_enable_ram_xn(enable) (void)enable
-
-#define mbed_mpu_free()
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/pinmap.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINMAP_H
-#define MBED_PINMAP_H
-
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
- PinName pin;
- int peripheral;
- int function;
-} PinMap;
-
-void pin_function(PinName pin, int function);
-void pin_mode(PinName pin, PinMode mode);
-
-uint32_t pinmap_peripheral(PinName pin, const PinMap *map);
-uint32_t pinmap_function(PinName pin, const PinMap *map);
-uint32_t pinmap_merge(uint32_t a, uint32_t b);
-void pinmap_pinout(PinName pin, const PinMap *map);
-uint32_t pinmap_find_peripheral(PinName pin, const PinMap *map);
-uint32_t pinmap_find_function(PinName pin, const PinMap *map);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/port_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,94 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTMAP_H
-#define MBED_PORTMAP_H
-
-#include "device.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Port HAL structure. port_s is declared in the target's HAL
- */
-typedef struct port_s port_t;
-
-/**
- * \defgroup hal_port Port HAL functions
- * @{
- */
-
-/** Get the pin name from the port's pin number
- *
- * @param port The port name
- * @param pin_n The pin number within the specified port
- * @return The pin name for the port's pin number
- */
-PinName port_pin(PortName port, int pin_n);
-
-/** Initilize the port
- *
- * @param obj The port object to initialize
- * @param port The port name
- * @param mask The bitmask to identify which bits in the port should be included (0 - ignore)
- * @param dir The port direction
- */
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir);
-
-/** Set the input port mode
- *
- * @param obj The port object
- * @param mode THe port mode to be set
- */
-void port_mode(port_t *obj, PinMode mode);
-
-/** Set port direction (in/out)
- *
- * @param obj The port object
- * @param dir The port direction to be set
- */
-void port_dir(port_t *obj, PinDirection dir);
-
-/** Write value to the port
- *
- * @param obj The port object
- * @param value The value to be set
- */
-void port_write(port_t *obj, int value);
-
-/** Read the current value on the port
- *
- * @param obj The port object
- * @return An integer with each bit corresponding to an associated port pin setting
- */
-int port_read(port_t *obj);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/pwmout_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_API_H
-#define MBED_PWMOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_PWMOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Pwmout hal structure. pwmout_s is declared in the target's hal
- */
-typedef struct pwmout_s pwmout_t;
-
-/**
- * \defgroup hal_pwmout Pwmout hal functions
- * @{
- */
-
-/** Initialize the pwm out peripheral and configure the pin
- *
- * @param obj The pwmout object to initialize
- * @param pin The pwmout pin to initialize
- */
-void pwmout_init(pwmout_t *obj, PinName pin);
-
-/** Deinitialize the pwmout object
- *
- * @param obj The pwmout object
- */
-void pwmout_free(pwmout_t *obj);
-
-/** Set the output duty-cycle in range <0.0f, 1.0f>
- *
- * Value 0.0f represents 0 percentage, 1.0f represents 100 percent.
- * @param obj The pwmout object
- * @param percent The floating-point percentage number
- */
-void pwmout_write(pwmout_t *obj, float percent);
-
-/** Read the current float-point output duty-cycle
- *
- * @param obj The pwmout object
- * @return A floating-point output duty-cycle
- */
-float pwmout_read(pwmout_t *obj);
-
-/** Set the PWM period specified in seconds, keeping the duty cycle the same
- *
- * Periods smaller than microseconds (the lowest resolution) are set to zero.
- * @param obj The pwmout object
- * @param seconds The floating-point seconds period
- */
-void pwmout_period(pwmout_t *obj, float seconds);
-
-/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
- *
- * @param obj The pwmout object
- * @param ms The milisecond period
- */
-void pwmout_period_ms(pwmout_t *obj, int ms);
-
-/** Set the PWM period specified in microseconds, keeping the duty cycle the same
- *
- * @param obj The pwmout object
- * @param us The microsecond period
- */
-void pwmout_period_us(pwmout_t *obj, int us);
-
-/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
- *
- * @param obj The pwmout object
- * @param seconds The floating-point pulsewidth in seconds
- */
-void pwmout_pulsewidth(pwmout_t *obj, float seconds);
-
-/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
- *
- * @param obj The pwmout object
- * @param ms The floating-point pulsewidth in miliseconds
- */
-void pwmout_pulsewidth_ms(pwmout_t *obj, int ms);
-
-/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
- *
- * @param obj The pwmout object
- * @param us The floating-point pulsewidth in microseconds
- */
-void pwmout_pulsewidth_us(pwmout_t *obj, int us);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/qspi_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,195 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_QSPI_API_H
-#define MBED_QSPI_API_H
-
-#include "device.h"
-#include <stdbool.h>
-
-#if DEVICE_QSPI
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_qspi QSPI HAL
- * @{
- */
-
-/** QSPI HAL object
- */
-typedef struct qspi_s qspi_t;
-
-/** QSPI Bus width
- *
- * Some parts of commands provide variable bus width
- */
-typedef enum qspi_bus_width {
- QSPI_CFG_BUS_SINGLE,
- QSPI_CFG_BUS_DUAL,
- QSPI_CFG_BUS_QUAD,
-} qspi_bus_width_t;
-
-/** Address size in bits
- */
-typedef enum qspi_address_size {
- QSPI_CFG_ADDR_SIZE_8,
- QSPI_CFG_ADDR_SIZE_16,
- QSPI_CFG_ADDR_SIZE_24,
- QSPI_CFG_ADDR_SIZE_32,
-} qspi_address_size_t;
-
-/** Alternative size in bits
- */
-typedef enum qspi_alt_size {
- QSPI_CFG_ALT_SIZE_8,
- QSPI_CFG_ALT_SIZE_16,
- QSPI_CFG_ALT_SIZE_24,
- QSPI_CFG_ALT_SIZE_32,
-} qspi_alt_size_t;
-
-/** QSPI command
- *
- * Defines a frame format. It consists of instruction, address, alternative, dummy count and data
- */
-typedef struct qspi_command {
- struct {
- qspi_bus_width_t bus_width; /**< Bus width for the instruction >*/
- uint8_t value; /**< Instruction value >*/
- bool disabled; /**< Instruction phase skipped if disabled is set to true >*/
- } instruction;
- struct {
- qspi_bus_width_t bus_width; /**< Bus width for the address >*/
- qspi_address_size_t size; /**< Address size >*/
- uint32_t value; /**< Address value >*/
- bool disabled; /**< Address phase skipped if disabled is set to true >*/
- } address;
- struct {
- qspi_bus_width_t bus_width; /**< Bus width for alternative >*/
- qspi_alt_size_t size; /**< Alternative size >*/
- uint32_t value; /**< Alternative value >*/
- bool disabled; /**< Alternative phase skipped if disabled is set to true >*/
- } alt;
- uint8_t dummy_count; /**< Dummy cycles count >*/
- struct {
- qspi_bus_width_t bus_width; /**< Bus width for data >*/
- } data;
-} qspi_command_t;
-
-/** QSPI return status
- */
-typedef enum qspi_status {
- QSPI_STATUS_ERROR = -1, /**< Generic error >*/
- QSPI_STATUS_INVALID_PARAMETER = -2, /**< The parameter is invalid >*/
- QSPI_STATUS_OK = 0, /**< Function executed sucessfully >*/
-} qspi_status_t;
-
-/** Initialize QSPI peripheral.
- *
- * It should initialize QSPI pins (io0-io3, sclk and ssel), set frequency, clock polarity and phase mode. The clock for the peripheral should be enabled
- *
- * @param obj QSPI object
- * @param io0 Data pin 0
- * @param io1 Data pin 1
- * @param io2 Data pin 2
- * @param io3 Data pin 3
- * @param sclk The clock pin
- * @param ssel The chip select pin
- * @param hz The bus frequency
- * @param mode Clock polarity and phase mode (0 - 3)
- * @return QSPI_STATUS_OK if initialisation successfully executed
- QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
- QSPI_STATUS_ERROR otherwise
- */
-qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode);
-
-/** Deinitilize QSPI peripheral
- *
- * It should release pins that are associated with the QSPI object, and disable clocks for QSPI peripheral module that was associated with the object
- *
- * @param obj QSPI object
- * @return QSPI_STATUS_OK if deinitialisation successfully executed
- QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
- QSPI_STATUS_ERROR otherwise
- */
-qspi_status_t qspi_free(qspi_t *obj);
-
-/** Set the QSPI baud rate
- *
- * Actual frequency may differ from the desired frequency due to available dividers and the bus clock
- * Configures the QSPI peripheral's baud rate
- * @param obj The SPI object to configure
- * @param hz The baud rate in Hz
- * @return QSPI_STATUS_OK if frequency was set
- QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
- QSPI_STATUS_ERROR otherwise
- */
-qspi_status_t qspi_frequency(qspi_t *obj, int hz);
-
-/** Send a command and block of data
- *
- * @param obj QSPI object
- * @param command QSPI command
- * @param data TX buffer
- * @param[in,out] length in - TX buffer length in bytes, out - number of bytes written
- * @return QSPI_STATUS_OK if the data has been succesfully sent
- QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
- QSPI_STATUS_ERROR otherwise
- */
-qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length);
-
-/** Send a command (and optionally data) and get the response. Can be used to send/receive device specific commands
- *
- * @param obj QSPI object
- * @param command QSPI command
- * @param tx_data TX buffer
- * @param tx_size TX buffer length in bytes
- * @param rx_data RX buffer
- * @param rx_size RX buffer length in bytes
- * @return QSPI_STATUS_OK if the data has been succesfully sent
- QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
- QSPI_STATUS_ERROR otherwise
- */
-qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size);
-
-/** Receive a command and block of data
- *
- * @param obj QSPI object
- * @param command QSPI command
- * @param data RX buffer
- * @param[in,out] length in - RX buffer length in bytes, out - number of bytes read
- * @return QSPI_STATUS_OK if data has been succesfully received
- QSPI_STATUS_INVALID_PARAMETER if invalid parameter found
- QSPI_STATUS_ERROR otherwise
- */
-qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/rtc_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,188 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/** \addtogroup hal */
-/** @{*/
-
-#ifndef MBED_RTC_API_H
-#define MBED_RTC_API_H
-
-#include "device.h"
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_rtc RTC hal
- *
- * The RTC hal provides a low level interface to the Real Time Counter (RTC) of a
- * target.
- *
- * # Defined behaviour
- * * The function ::rtc_init is safe to call repeatedly - Verified by test ::rtc_init_test.
- * * RTC accuracy is at least 10% - Verified by test ::rtc_accuracy_test.
- * * Init/free doesn't stop RTC from counting - Verified by test ::rtc_persist_test.
- * * Software reset doesn't stop RTC from counting - Verified by test ::rtc_reset_test.
- * * Sleep modes don't stop RTC from counting - Verified by test ::rtc_sleep_test.
- * * Shutdown mode doesn't stop RTC from counting - Not verified.
- * * The functions ::rtc_write/::rtc_read provides availability to set/get RTC time
- * - Verified by test ::rtc_write_read_test.
- * * The functions ::rtc_isenabled returns 1 if the RTC is counting and the time has been set,
- * 0 otherwise - Verified by test ::rtc_enabled_test.
- *
- * # Undefined behaviour
- * * Calling any function other than ::rtc_init before the initialisation of the RTC
- *
- * # Potential bugs
- * * Incorrect overflow handling - Verified by ::rtc_range_test
- * * Glitches due to ripple counter - Verified by ::rtc_glitch_test
- *
- * @see hal_rtc_tests
- *
- * @{
- */
-
-/**
- * \defgroup hal_rtc_tests RTC hal tests
- * The RTC test validate proper implementation of the RTC hal.
- *
- * To run the RTC hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-rtc*
- */
-
-
-/** Initialize the RTC peripheral
- *
- * Powerup the RTC in perpetration for access. This function must be called
- * before any other RTC functions ares called. This does not change the state
- * of the RTC. It just enables access to it.
- *
- * @note This function is safe to call repeatedly - Tested by ::rtc_init_test
- *
- * Example Implementation Pseudo Code:
- * @code
- * void rtc_init()
- * {
- * // Enable clock gate so processor can read RTC registers
- * POWER_CTRL |= POWER_CTRL_RTC_Msk;
- *
- * // See if the RTC is already setup
- * if (!(RTC_STATUS & RTC_STATUS_COUNTING_Msk)) {
- *
- * // Setup the RTC clock source
- * RTC_CTRL |= RTC_CTRL_CLK32_Msk;
- * }
- * }
- * @endcode
- */
-void rtc_init(void);
-
-/** Deinitialize RTC
- *
- * Powerdown the RTC in preparation for sleep, powerdown or reset. That should only
- * affect the CPU domain and not the time keeping logic.
- * After this function is called no other RTC functions should be called
- * except for ::rtc_init.
- *
- * @note This function does not stop the RTC from counting - Tested by ::rtc_persist_test
- *
- * Example Implementation Pseudo Code:
- * @code
- * void rtc_free()
- * {
- * // Disable clock gate since processor no longer needs to read RTC registers
- * POWER_CTRL &= ~POWER_CTRL_RTC_Msk;
- * }
- * @endcode
- */
-void rtc_free(void);
-
-/** Check if the RTC has the time set and is counting
- *
- * @retval 0 The time reported by the RTC is not valid
- * @retval 1 The time has been set the RTC is counting
- *
- * Example Implementation Pseudo Code:
- * @code
- * int rtc_isenabled()
- * {
- * if (RTC_STATUS & RTC_STATUS_COUNTING_Msk) {
- * return 1;
- * } else {
- * return 0;
- * }
- * }
- * @endcode
- */
-int rtc_isenabled(void);
-
-/** Get the current time from the RTC peripheral
- *
- * @return The current time in seconds
- *
- * @note Some RTCs are not synchronized with the main clock. If
- * this is the case with your RTC then you must read the RTC time
- * in a loop to prevent reading the wrong time due to a glitch.
- * The test ::rtc_glitch_test is intended to catch this bug.
- *
- * Example implementation for an unsynchronized ripple counter:
- * @code
- * time_t rtc_read()
- * {
- * uint32_t val;
- * uint32_t last_val;
- *
- * // Loop until the same value is read twice
- * val = RTC_SECONDS;
- * do {
- * last_val = val;
- * val = RTC_SECONDS;
- * } while (last_val != val);
- *
- * return (time_t)val;
- * }
- * @endcode
- */
-time_t rtc_read(void);
-
-/** Write the current time in seconds to the RTC peripheral
- *
- * @param t The current time to be set in seconds.
- *
- * Example Implementation Pseudo Code:
- * @code
- * void rtc_write(time_t t)
- * {
- * RTC_SECONDS = t;
- * }
- * @endcode
- */
-void rtc_write(time_t t);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/serial_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,308 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_API_H
-#define MBED_SERIAL_API_H
-
-#include "device.h"
-#include "hal/buffer.h"
-#include "hal/dma_api.h"
-
-#if DEVICE_SERIAL
-
-#define SERIAL_EVENT_TX_SHIFT (2)
-#define SERIAL_EVENT_RX_SHIFT (8)
-
-#define SERIAL_EVENT_TX_MASK (0x00FC)
-#define SERIAL_EVENT_RX_MASK (0x3F00)
-
-#define SERIAL_EVENT_ERROR (1 << 1)
-
-/**
- * @defgroup SerialTXEvents Serial TX Events Macros
- *
- * @{
- */
-#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
-#define SERIAL_EVENT_TX_ALL (SERIAL_EVENT_TX_COMPLETE)
-/**@}*/
-
-/**
- * @defgroup SerialRXEvents Serial RX Events Macros
- *
- * @{
- */
-#define SERIAL_EVENT_RX_COMPLETE (1 << (SERIAL_EVENT_RX_SHIFT + 0))
-#define SERIAL_EVENT_RX_OVERRUN_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 1))
-#define SERIAL_EVENT_RX_FRAMING_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 2))
-#define SERIAL_EVENT_RX_PARITY_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 3))
-#define SERIAL_EVENT_RX_OVERFLOW (1 << (SERIAL_EVENT_RX_SHIFT + 4))
-#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
-#define SERIAL_EVENT_RX_ALL (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
- SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
- SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
-/**@}*/
-
-#define SERIAL_RESERVED_CHAR_MATCH (255)
-
-typedef enum {
- ParityNone = 0,
- ParityOdd = 1,
- ParityEven = 2,
- ParityForced1 = 3,
- ParityForced0 = 4
-} SerialParity;
-
-typedef enum {
- RxIrq,
- TxIrq
-} SerialIrq;
-
-typedef enum {
- FlowControlNone,
- FlowControlRTS,
- FlowControlCTS,
- FlowControlRTSCTS
-} FlowControl;
-
-typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
-
-#if DEVICE_SERIAL_ASYNCH
-/** Asynch serial HAL structure
- */
-typedef struct {
- struct serial_s serial; /**< Target specific serial structure */
- struct buffer_s tx_buff; /**< TX buffer */
- struct buffer_s rx_buff; /**< RX buffer */
- uint8_t char_match; /**< Character to be matched */
- uint8_t char_found; /**< State of the matched character */
-} serial_t;
-
-#else
-/** Non-asynch serial HAL structure
- */
-typedef struct serial_s serial_t;
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_GeneralSerial Serial Configuration Functions
- * @{
- */
-
-/** Initialize the serial peripheral. It sets the default parameters for serial
- * peripheral, and configures its specifieds pins.
- *
- * @param obj The serial object
- * @param tx The TX pin name
- * @param rx The RX pin name
- */
-void serial_init(serial_t *obj, PinName tx, PinName rx);
-
-/** Release the serial peripheral, not currently invoked. It requires further
- * resource management.
- *
- * @param obj The serial object
- */
-void serial_free(serial_t *obj);
-
-/** Configure the baud rate
- *
- * @param obj The serial object
- * @param baudrate The baud rate to be configured
- */
-void serial_baud(serial_t *obj, int baudrate);
-
-/** Configure the format. Set the number of bits, parity and the number of stop bits
- *
- * @param obj The serial object
- * @param data_bits The number of data bits
- * @param parity The parity
- * @param stop_bits The number of stop bits
- */
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
-
-/** The serial interrupt handler registration
- *
- * @param obj The serial object
- * @param handler The interrupt handler which will be invoked when the interrupt fires
- * @param id The SerialBase object
- */
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
-
-/** Configure serial interrupt. This function is used for word-approach
- *
- * @param obj The serial object
- * @param irq The serial IRQ type (RX or TX)
- * @param enable Set to non-zero to enable events, or zero to disable them
- */
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
-
-/** Get character. This is a blocking call, waiting for a character
- *
- * @param obj The serial object
- */
-int serial_getc(serial_t *obj);
-
-/** Send a character. This is a blocking call, waiting for a peripheral to be available
- * for writing
- *
- * @param obj The serial object
- * @param c The character to be sent
- */
-void serial_putc(serial_t *obj, int c);
-
-/** Check if the serial peripheral is readable
- *
- * @param obj The serial object
- * @return Non-zero value if a character can be read, 0 if nothing to read
- */
-int serial_readable(serial_t *obj);
-
-/** Check if the serial peripheral is writable
- *
- * @param obj The serial object
- * @return Non-zero value if a character can be written, 0 otherwise.
- */
-int serial_writable(serial_t *obj);
-
-/** Clear the serial peripheral
- *
- * @param obj The serial object
- */
-void serial_clear(serial_t *obj);
-
-/** Set the break
- *
- * @param obj The serial object
- */
-void serial_break_set(serial_t *obj);
-
-/** Clear the break
- *
- * @param obj The serial object
- */
-void serial_break_clear(serial_t *obj);
-
-/** Configure the TX pin for UART function.
- *
- * @param tx The pin name used for TX
- */
-void serial_pinout_tx(PinName tx);
-
-/** Configure the serial for the flow control. It sets flow control in the hardware
- * if a serial peripheral supports it, otherwise software emulation is used.
- *
- * @param obj The serial object
- * @param type The type of the flow control. Look at the available FlowControl types.
- * @param rxflow The TX pin name
- * @param txflow The RX pin name
- */
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
-
-#if DEVICE_SERIAL_ASYNCH
-
-/**@}*/
-
-/**
- * \defgroup hal_AsynchSerial Asynchronous Serial Hardware Abstraction Layer
- * @{
- */
-
-/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
- * tx_buff
- *
- * @param obj The serial object
- * @param tx The transmit buffer
- * @param tx_length The number of bytes to transmit
- * @param tx_width Deprecated argument
- * @param handler The serial handler
- * @param event The logical OR of events to be registered
- * @param hint A suggestion for how to use DMA with this transfer
- * @return Returns number of data transfered, otherwise returns 0
- */
-int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** Begin asynchronous RX transfer (enable interrupt for data collecting)
- * The used buffer is specified in the serial object - rx_buff
- *
- * @param obj The serial object
- * @param rx The receive buffer
- * @param rx_length The number of bytes to receive
- * @param rx_width Deprecated argument
- * @param handler The serial handler
- * @param event The logical OR of events to be registered
- * @param handler The serial handler
- * @param char_match A character in range 0-254 to be matched
- * @param hint A suggestion for how to use DMA with this transfer
- */
-void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
-
-/** Attempts to determine if the serial peripheral is already in use for TX
- *
- * @param obj The serial object
- * @return Non-zero if the RX transaction is ongoing, 0 otherwise
- */
-uint8_t serial_tx_active(serial_t *obj);
-
-/** Attempts to determine if the serial peripheral is already in use for RX
- *
- * @param obj The serial object
- * @return Non-zero if the RX transaction is ongoing, 0 otherwise
- */
-uint8_t serial_rx_active(serial_t *obj);
-
-/** The asynchronous TX and RX handler.
- *
- * @param obj The serial object
- * @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0
- */
-int serial_irq_handler_asynch(serial_t *obj);
-
-/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
- * flushes the TX hardware buffer if TX FIFO is used
- *
- * @param obj The serial object
- */
-void serial_tx_abort_asynch(serial_t *obj);
-
-/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
- * flushes the RX hardware buffer if RX FIFO is used
- *
- * @param obj The serial object
- */
-void serial_rx_abort_asynch(serial_t *obj);
-
-/**@}*/
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/sleep_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SLEEP_API_H
-#define MBED_SLEEP_API_H
-
-#include "device.h"
-
-#if DEVICE_SLEEP
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_sleep sleep hal requirements
- * Low level interface to the sleep mode of a target.
- *
- * # Defined behaviour
- *
- * * Sleep mode
- * * wake-up time should be less than 10 us - Verified by sleep_usticker_test().
- * * the processor can be woken up by any internal peripheral interrupt - Verified by sleep_usticker_test().
- * * all peripherals operate as in run mode - not verified.
- * * the processor can be woken up by external pin interrupt - not verified.
- * * Deep sleep
- * * the wake-up time should be less than 10 ms - Verified by deepsleep_lpticker_test().
- * * lp ticker should wake up a target from this mode - Verified by deepsleep_lpticker_test().
- * * RTC should wake up a target from this mode - not verified.
- * * an external interrupt on a pin should wake up a target from this mode - not verified.
- * * a watchdog timer should wake up a target from this mode - not verified.
- * * High-speed clocks are turned off - Verified by deepsleep_high_speed_clocks_turned_off_test().
- * * RTC keeps time - Verified by rtc_sleep_test().
- *
- * # Undefined behaviour
- *
- * * peripherals aside from RTC, GPIO and lp ticker result in undefined behaviour in deep sleep.
- * @{
- */
-
-/**
- * \defgroup hal_sleep_tests sleep hal tests
- * The sleep HAL tests ensure driver conformance to defined behaviour.
- *
- * To run the sleep hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-sleep*
- *
- */
-
-/** Send the microcontroller to sleep
- *
- * The processor is setup ready for sleep, and sent to sleep. In this mode, the
- * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
- * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
- * memory state are maintained, and the peripherals continue to work and can generate interrupts.
- *
- * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
- *
- * The wake-up time shall be less than 10 us.
- *
- */
-void hal_sleep(void);
-
-/** Send the microcontroller to deep sleep
- *
- * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
- * has the same sleep features as sleep plus it powers down peripherals and high frequency clocks.
- * All state is still maintained.
- *
- * The processor can only be woken up by low power ticker, RTC, an external interrupt on a pin or a watchdog timer.
- *
- * The wake-up time shall be less than 10 ms.
- */
-void hal_deepsleep(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/**@}*/
--- a/STM32F103C8T6_MPA/mbed/hal/spi_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,239 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_API_H
-#define MBED_SPI_API_H
-
-#include "device.h"
-#include "hal/dma_api.h"
-#include "hal/buffer.h"
-
-#if DEVICE_SPI
-
-#define SPI_EVENT_ERROR (1 << 1)
-#define SPI_EVENT_COMPLETE (1 << 2)
-#define SPI_EVENT_RX_OVERFLOW (1 << 3)
-#define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
-
-#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
-
-#define SPI_FILL_WORD (0xFFFF)
-#define SPI_FILL_CHAR (0xFF)
-
-#if DEVICE_SPI_ASYNCH
-/** Asynch SPI HAL structure
- */
-typedef struct {
- struct spi_s spi; /**< Target specific SPI structure */
- struct buffer_s tx_buff; /**< Tx buffer */
- struct buffer_s rx_buff; /**< Rx buffer */
-} spi_t;
-
-#else
-/** Non-asynch SPI HAL structure
- */
-typedef struct spi_s spi_t;
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_GeneralSPI SPI Configuration Functions
- * @{
- */
-
-/** Initialize the SPI peripheral
- *
- * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
- * @param[out] obj The SPI object to initialize
- * @param[in] mosi The pin to use for MOSI
- * @param[in] miso The pin to use for MISO
- * @param[in] sclk The pin to use for SCLK
- * @param[in] ssel The pin to use for SSEL
- */
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
-/** Release a SPI object
- *
- * TODO: spi_free is currently unimplemented
- * This will require reference counting at the C++ level to be safe
- *
- * Return the pins owned by the SPI object to their reset state
- * Disable the SPI peripheral
- * Disable the SPI clock
- * @param[in] obj The SPI object to deinitialize
- */
-void spi_free(spi_t *obj);
-
-/** Configure the SPI format
- *
- * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
- * The default bit order is MSB.
- * @param[in,out] obj The SPI object to configure
- * @param[in] bits The number of bits per frame
- * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
- * @param[in] slave Zero for master mode or non-zero for slave mode
- */
-void spi_format(spi_t *obj, int bits, int mode, int slave);
-
-/** Set the SPI baud rate
- *
- * Actual frequency may differ from the desired frequency due to available dividers and bus clock
- * Configures the SPI peripheral's baud rate
- * @param[in,out] obj The SPI object to configure
- * @param[in] hz The baud rate in Hz
- */
-void spi_frequency(spi_t *obj, int hz);
-
-/**@}*/
-/**
- * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
- * @{
- */
-
-/** Write a byte out in master mode and receive a value
- *
- * @param[in] obj The SPI peripheral to use for sending
- * @param[in] value The value to send
- * @return Returns the value received during send
- */
-int spi_master_write(spi_t *obj, int value);
-
-/** Write a block out in master mode and receive a value
- *
- * The total number of bytes sent and received will be the maximum of
- * tx_length and rx_length. The bytes written will be padded with the
- * value 0xff.
- *
- * @param[in] obj The SPI peripheral to use for sending
- * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
- * @param[in] tx_length Number of bytes to write, may be zero
- * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
- * @param[in] rx_length Number of bytes to read, may be zero
- * @param[in] write_fill Default data transmitted while performing a read
- * @returns
- * The number of bytes written and read from the device. This is
- * maximum of tx_length and rx_length.
- */
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
-
-/** Check if a value is available to read
- *
- * @param[in] obj The SPI peripheral to check
- * @return non-zero if a value is available
- */
-int spi_slave_receive(spi_t *obj);
-
-/** Get a received value out of the SPI receive buffer in slave mode
- *
- * Blocks until a value is available
- * @param[in] obj The SPI peripheral to read
- * @return The value received
- */
-int spi_slave_read(spi_t *obj);
-
-/** Write a value to the SPI peripheral in slave mode
- *
- * Blocks until the SPI peripheral can be written to
- * @param[in] obj The SPI peripheral to write
- * @param[in] value The value to write
- */
-void spi_slave_write(spi_t *obj, int value);
-
-/** Checks if the specified SPI peripheral is in use
- *
- * @param[in] obj The SPI peripheral to check
- * @return non-zero if the peripheral is currently transmitting
- */
-int spi_busy(spi_t *obj);
-
-/** Get the module number
- *
- * @param[in] obj The SPI peripheral to check
- * @return The module number
- */
-uint8_t spi_get_module(spi_t *obj);
-
-/**@}*/
-
-#if DEVICE_SPI_ASYNCH
-/**
- * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
- * @{
- */
-
-/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
- *
- * @param[in] obj The SPI object that holds the transfer information
- * @param[in] tx The transmit buffer
- * @param[in] tx_length The number of bytes to transmit
- * @param[in] rx The receive buffer
- * @param[in] rx_length The number of bytes to receive
- * @param[in] bit_width The bit width of buffer words
- * @param[in] event The logical OR of events to be registered
- * @param[in] handler SPI interrupt handler
- * @param[in] hint A suggestion for how to use DMA with this transfer
- */
-void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** The asynchronous IRQ handler
- *
- * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
- * conditions, such as buffer overflows or transfer complete.
- * @param[in] obj The SPI object that holds the transfer information
- * @return Event flags if a transfer termination condition was met; otherwise 0.
- */
-uint32_t spi_irq_handler_asynch(spi_t *obj);
-
-/** Attempts to determine if the SPI peripheral is already in use
- *
- * If a temporary DMA channel has been allocated, peripheral is in use.
- * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
- * channel were allocated.
- * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
- * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
- * there are any bytes in the FIFOs.
- * @param[in] obj The SPI object to check for activity
- * @return Non-zero if the SPI port is active or zero if it is not.
- */
-uint8_t spi_active(spi_t *obj);
-
-/** Abort an SPI transfer
- *
- * @param obj The SPI peripheral to stop
- */
-void spi_abort_asynch(spi_t *obj);
-
-
-#endif
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif // __cplusplus
-
-#endif // SPI_DEVICE
-
-#endif // MBED_SPI_API_H
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/spm_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* Copyright (c) 2017-2018 ARM Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __SPM_API_H__
-#define __SPM_API_H__
-
-#include <stdint.h>
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/** @defgroup SPM-HAL SPM HAL API
- * The HAL functions for PSA SPM
- * @{
- */
-
-
-/* ------------------------------------ HAL-SPE API ------------------------- */
-
-
-#if defined(COMPONENT_SPE)
-/**
- * Start running the NSPE.
- *
- * Secure Processing Environment (SPE) expected to boot first. Once all
- * the initializations are done, Nonsecure Processing Environment (NSPE)
- * should be booted.
- *
- * @note The function must be implemented by target specific code.
- */
-void spm_hal_start_nspe(void);
-
-
-/**
- * Configure memory protection mechanism.
- *
- * Apply memory protection schemes to ensure secure memory can only be accessed
- * from secure-state.
- *
- * @note The function must be implemented by target specific code.
- *
- */
-void spm_hal_memory_protection_init(void);
-
-#endif // defined(COMPONENT_SPE)
-
-/* ---------------------------------- HAL-Mailbox API ----------------------- */
-
-#if defined(COMPONENT_SPM_MAILBOX)
-/**
- * @brief Wakeup mailbox dispatcher thread
- *
- * Arm implements this function, which is expected to be called by target-
- * specific Inter-Processor-Communication logic on mailbox interrupt handler.
- *
- */
-void spm_mailbox_irq_callback(void);
-
-/**
- * @brief Notify the peer processor about a general event occurrence.
- *
- * Wake up the peer processor waiting on the mailbox driver event.
- *
- * @note Implement the functions below with target-specific code.
- */
-void spm_hal_mailbox_notify(void);
-
-#endif // defined(COMPONENT_SPM_MAILBOX)
-
-/** @}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __SPM_API_H__
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/ticker_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,231 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_API_H
-#define MBED_TICKER_API_H
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "device.h"
-
-/**
- * Legacy format representing a timestamp in us.
- * Given it is modeled as a 32 bit integer, this type can represent timestamp
- * up to 4294 seconds (71 minutes).
- * Prefer using us_timestamp_t which store timestamp as 64 bits integer.
- */
-typedef uint32_t timestamp_t;
-
-/**
- * A us timestamp stored in a 64 bit integer.
- * Can store timestamp up to 584810 years.
- */
-typedef uint64_t us_timestamp_t;
-
-/** Ticker's event structure
- */
-typedef struct ticker_event_s {
- us_timestamp_t timestamp; /**< Event's timestamp */
- uint32_t id; /**< TimerEvent object */
- struct ticker_event_s *next; /**< Next event in the queue */
-} ticker_event_t;
-
-typedef void (*ticker_event_handler)(uint32_t id);
-
-/** Information about the ticker implementation
- */
-typedef struct {
- uint32_t frequency; /**< Frequency in Hz this ticker runs at */
- uint32_t bits; /**< Number of bits this ticker supports */
-} ticker_info_t;
-
-
-/** Ticker's interface structure - required API for a ticker
- */
-typedef struct {
- void (*init)(void); /**< Init function */
- uint32_t (*read)(void); /**< Read function */
- void (*disable_interrupt)(void); /**< Disable interrupt function */
- void (*clear_interrupt)(void); /**< Clear interrupt function */
- void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
- void (*fire_interrupt)(void); /**< Fire interrupt right-away */
- void (*free)(void); /**< Disable function */
- const ticker_info_t *(*get_info)(void); /**< Return info about this ticker's implementation */
-} ticker_interface_t;
-
-/** Ticker's event queue structure
- */
-typedef struct {
- ticker_event_handler event_handler; /**< Event handler */
- ticker_event_t *head; /**< A pointer to head */
- uint32_t frequency; /**< Frequency of the timer in Hz */
- uint32_t bitmask; /**< Mask to be applied to time values read */
- uint32_t max_delta; /**< Largest delta in ticks that can be used when scheduling */
- uint64_t max_delta_us; /**< Largest delta in us that can be used when scheduling */
- uint32_t tick_last_read; /**< Last tick read */
- uint64_t tick_remainder; /**< Ticks that have not been added to base_time */
- us_timestamp_t present_time; /**< Store the timestamp used for present time */
- bool initialized; /**< Indicate if the instance is initialized */
- bool dispatching; /**< The function ticker_irq_handler is dispatching */
- bool suspended; /**< Indicate if the instance is suspended */
- uint8_t frequency_shifts; /**< If frequency is a value of 2^n, this is n, otherwise 0 */
-} ticker_event_queue_t;
-
-/** Ticker's data structure
- */
-typedef struct {
- const ticker_interface_t *interface; /**< Ticker's interface */
- ticker_event_queue_t *queue; /**< Ticker's event queue */
-} ticker_data_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_ticker Ticker HAL functions
- * @{
- */
-
-/** Initialize a ticker and set the event handler
- *
- * @param ticker The ticker object.
- * @param handler A handler to be set
- */
-void ticker_set_handler(const ticker_data_t *const ticker, ticker_event_handler handler);
-
-/** IRQ handler that goes through the events to trigger overdue events.
- *
- * @param ticker The ticker object.
- */
-void ticker_irq_handler(const ticker_data_t *const ticker);
-
-/** Remove an event from the queue
- *
- * @param ticker The ticker object.
- * @param obj The event object to be removed from the queue
- */
-void ticker_remove_event(const ticker_data_t *const ticker, ticker_event_t *obj);
-
-/** Insert an event to the queue
- *
- * The event will be executed in timestamp - ticker_read().
- *
- * @warning This function does not consider timestamp in the past. If an event
- * is inserted with a timestamp less than the current timestamp then the event
- * will be executed in timestamp - ticker_read() us.
- * The internal counter wrap very quickly it is hard to decide weither an
- * event is in the past or in 1 hour.
- *
- * @note prefer the use of ticker_insert_event_us which allows registration of
- * absolute timestamp.
- *
- * @param ticker The ticker object.
- * @param obj The event object to be inserted to the queue
- * @param timestamp The event's timestamp
- * @param id The event object
- */
-void ticker_insert_event(const ticker_data_t *const ticker, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
-
-/** Insert an event to the queue
- *
- * The event will be executed in timestamp - ticker_read_us() us.
- *
- * @note If an event is inserted with a timestamp less than the current
- * timestamp then the event will be scheduled immediately resulting in
- * an instant call to event handler.
- *
- * @param ticker The ticker object.
- * @param obj The event object to be inserted to the queue
- * @param timestamp The event's timestamp
- * @param id The event object
- */
-void ticker_insert_event_us(const ticker_data_t *const ticker, ticker_event_t *obj, us_timestamp_t timestamp, uint32_t id);
-
-/** Read the current (relative) ticker's timestamp
- *
- * @warning Return a relative timestamp because the counter wrap every 4294
- * seconds.
- *
- * @param ticker The ticker object.
- * @return The current timestamp
- */
-timestamp_t ticker_read(const ticker_data_t *const ticker);
-
-/** Read the current (absolute) ticker's timestamp
- *
- * @warning Return an absolute timestamp counting from the initialization of the
- * ticker.
- *
- * @param ticker The ticker object.
- * @return The current timestamp
- */
-us_timestamp_t ticker_read_us(const ticker_data_t *const ticker);
-
-/** Read the next event's timestamp
- *
- * @param ticker The ticker object.
- * @param timestamp The timestamp object.
- * @return 1 if timestamp is pending event, 0 if there's no event pending
- */
-int ticker_get_next_timestamp(const ticker_data_t *const ticker, timestamp_t *timestamp);
-
-/** Suspend this ticker
- *
- * When suspended reads will always return the same time and no
- * events will be dispatched. When suspended the common layer
- * will only ever call the interface function clear_interrupt()
- * and that is only if ticker_irq_handler is called.
- *
- *
- * @param ticker The ticker object.
- */
-void ticker_suspend(const ticker_data_t *const ticker);
-
-/** Resume this ticker
- *
- * When resumed the ticker will ignore any time that has passed
- * and continue counting up where it left off.
- *
- * @param ticker The ticker object.
- */
-void ticker_resume(const ticker_data_t *const ticker);
-
-/* Private functions
- *
- * @cond PRIVATE
- *
- */
-
-int _ticker_match_interval_passed(timestamp_t prev_tick, timestamp_t cur_tick, timestamp_t match_tick);
-
-/*
- * @endcond PRIVATE
- *
- */
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/trng_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,73 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2016 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TRNG_API_H
-#define MBED_TRNG_API_H
-
-#include <stddef.h>
-#include "device.h"
-
-#if DEVICE_TRNG
-
-/** TRNG HAL structure. trng_s is declared in the target's HAL
- */
-typedef struct trng_s trng_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_trng TRNG hal functions
- * @{
- */
-
-/** Initialize the TRNG peripheral
- *
- * @param obj The TRNG object
- */
-void trng_init(trng_t *obj);
-
-/** Deinitialize the TRNG peripheral
- *
- * @param obj The TRNG object
- */
-void trng_free(trng_t *obj);
-
-/** Get random data from TRNG peripheral
- *
- * @param obj The TRNG object
- * @param output The pointer to an output array
- * @param length The size of output data, to avoid buffer overwrite
- * @param output_length The length of generated data
- * @return 0 success, -1 fail
- */
-int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/hal/us_ticker_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,302 +0,0 @@
-
-/** \addtogroup hal */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_US_TICKER_API_H
-#define MBED_US_TICKER_API_H
-
-#include <stdint.h>
-#include "hal/ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup hal_us_ticker Microsecond Ticker
- * Low level interface to the microsecond ticker of a target
- *
- * # Defined behavior
- * * Has a reported frequency between 250KHz and 8MHz - Verified by test ::us_ticker_info_test
- * * Has a counter that is at least 16 bits wide - Verified by test ::us_ticker_info_test
- * * All behavior defined by the @ref hal_ticker_shared "ticker specification"
- *
- * # Undefined behavior
- * * See the @ref hal_ticker_shared "ticker specification"
- *
- * @see hal_us_ticker_tests
- *
- * @{
- */
-
-/**
- * \defgroup hal_us_ticker_tests Microsecond Ticker tests
- * Tests to validate the proper implementation of the microsecond ticker
- *
- * To run the microsecond ticker hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*,tests-mbed_hal-us_ticker*
- *
- * @see hal_ticker_tests
- *
- */
-
-/**
- * \defgroup hal_ticker_shared Ticker Hal
- * Low level interface to the ticker of a target
- *
- * # Defined behavior
- * * The function ticker_init is safe to call repeatedly - Verified by test ::ticker_init_test
- * * The function ticker_init allows the ticker to keep counting and disables the ticker interrupt - Verified by test ::ticker_init_test
- * * Ticker frequency is non-zero and counter is at least 8 bits - Verified by ::ticker_info_test
- * * The ticker rolls over at (1 << bits) and continues counting starting from 0 - Verified by ::ticker_overflow_test
- * * The ticker counts at the specified frequency +- 10% - Verified by ::ticker_frequency_test
- * * The ticker increments by 1 each tick - Verified by ::ticker_increment_test
- * * The ticker interrupt fires only when the ticker times increments to or past the value set by ticker_set_interrupt.
- * Verified by ::ticker_interrupt_test and ::ticker_past_test
- * * It is safe to call ticker_set_interrupt repeatedly before the handler is called - Verified by ::ticker_repeat_reschedule_test
- * * The function ticker_fire_interrupt causes ticker_irq_handler to be called immediately from interrupt context -
- * Verified by ::ticker_fire_now_test
- * * The ticker operations ticker_read, ticker_clear_interrupt, ticker_set_interrupt and ticker_fire_interrupt
- * take less than 20us to complete - Verified by ::ticker_speed_test
- *
- * # Undefined behavior
- * * Calling any function other than ticker_init before the initialization of the ticker
- * * Whether ticker_irq_handler is called a second time if the time wraps and matches the value set by ticker_set_interrupt again
- * * Calling ticker_set_interrupt with a value that has more than the supported number of bits
- * * Calling any function other than us_ticker_init after calling us_ticker_free
- *
- * # Potential bugs
- * * Drift due to reschedule - Verified by ::ticker_repeat_reschedule_test
- * * Incorrect overflow handling of timers - Verified by ::ticker_overflow_test
- * * Interrupting at a time of 0 - Verified by ::ticker_overflow_test
- * * Interrupt triggered more than once - Verified by ::ticker_interrupt_test
- *
- * @ingroup hal_us_ticker
- * @ingroup hal_lp_ticker
- */
-
-/**
- * \defgroup hal_ticker_tests Ticker Tests
- * Tests to validate the proper implementation of a ticker
- *
- * To run the ticker hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-common_ticker*
- *
- * @ingroup hal_us_ticker
- * @ingroup hal_lp_ticker
- */
-
-
-typedef void (*ticker_irq_handler_type)(const ticker_data_t *const);
-
-/** Set ticker IRQ handler
- *
- * @param ticker_irq_handler IRQ handler to be connected
- *
- * @return previous ticker IRQ handler
- *
- * @note by default IRQ handler is set to ::ticker_irq_handler
- * @note this function is primarily for testing purposes and it's not required part of HAL implementation
- *
- */
-ticker_irq_handler_type set_us_ticker_irq_handler(ticker_irq_handler_type ticker_irq_handler);
-
-/** Get ticker's data
- *
- * @return The microsecond ticker data
- */
-const ticker_data_t *get_us_ticker_data(void);
-
-
-/** The wrapper for ticker_irq_handler, to pass us ticker's data
- *
- */
-void us_ticker_irq_handler(void);
-
-/* HAL us ticker */
-
-/** Initialize the ticker
- *
- * Initialize or re-initialize the ticker. This resets all the
- * clocking and prescaler registers, along with disabling
- * the compare interrupt.
- *
- * @note Initialization properties tested by ::ticker_init_test
- *
- * Pseudo Code:
- * @code
- * void us_ticker_init()
- * {
- * // Enable clock gate so processor can read TIMER registers
- * POWER_CTRL |= POWER_CTRL_TIMER_Msk;
- *
- * // Disable the timer and ensure it is powered down
- * TIMER_CTRL &= ~(TIMER_CTRL_ENABLE_Msk | TIMER_CTRL_COMPARE_ENABLE_Msk);
- *
- * // Configure divisors
- * uint32_t prescale = SystemCoreClock / 1000000;
- * TIMER_PRESCALE = prescale - 1;
- * TIMER_CTRL |= TIMER_CTRL_ENABLE_Msk;
- *
- * // Install the interrupt handler
- * NVIC_SetVector(TIMER_IRQn, (uint32_t)us_ticker_irq_handler);
- * NVIC_EnableIRQ(TIMER_IRQn);
- * }
- * @endcode
- */
-void us_ticker_init(void);
-
-/** Deinitialize the us ticker
- *
- * Powerdown the us ticker in preparation for sleep, powerdown, or reset.
- *
- * After this function is called, no other ticker functions should be called
- * except us_ticker_init(), calling any function other than init is undefined.
- *
- * @note This function stops the ticker from counting.
- *
- * Pseudo Code:
- * @code
- * uint32_t us_ticker_free()
- * {
- * // Disable timer
- * TIMER_CTRL &= ~TIMER_CTRL_ENABLE_Msk;
- *
- * // Disable the compare interrupt
- * TIMER_CTRL &= ~TIMER_CTRL_COMPARE_ENABLE_Msk;
- *
- * // Disable timer interrupt
- * NVIC_DisableIRQ(TIMER_IRQn);
- *
- * // Disable clock gate so processor cannot read TIMER registers
- * POWER_CTRL &= ~POWER_CTRL_TIMER_Msk;
- * }
- * @endcode
- *
- */
-void us_ticker_free(void);
-
-/** Read the current counter
- *
- * Read the current counter value without performing frequency conversions.
- * If no rollover has occurred, the seconds passed since us_ticker_init()
- * was called can be found by dividing the ticks returned by this function
- * by the frequency returned by ::us_ticker_get_info.
- *
- * @return The current timer's counter value in ticks
- *
- * Pseudo Code:
- * @code
- * uint32_t us_ticker_read()
- * {
- * return TIMER_COUNT;
- * }
- * @endcode
- */
-uint32_t us_ticker_read(void);
-
-/** Set interrupt for specified timestamp
- *
- * @param timestamp The time in ticks to be set
- *
- * @note no special handling needs to be done for times in the past
- * as the common timer code will detect this and call
- * us_ticker_fire_interrupt() if this is the case
- *
- * @note calling this function with timestamp of more than the supported
- * number of bits returned by ::us_ticker_get_info results in undefined
- * behavior.
- *
- * Pseudo Code:
- * @code
- * void us_ticker_set_interrupt(timestamp_t timestamp)
- * {
- * TIMER_COMPARE = timestamp;
- * TIMER_CTRL |= TIMER_CTRL_COMPARE_ENABLE_Msk;
- * }
- * @endcode
- */
-void us_ticker_set_interrupt(timestamp_t timestamp);
-
-/** Disable us ticker interrupt
- *
- * Pseudo Code:
- * @code
- * void us_ticker_disable_interrupt(void)
- * {
- * // Disable the compare interrupt
- * TIMER_CTRL &= ~TIMER_CTRL_COMPARE_ENABLE_Msk;
- * }
- * @endcode
- */
-void us_ticker_disable_interrupt(void);
-
-/** Clear us ticker interrupt
- *
- * Pseudo Code:
- * @code
- * void us_ticker_clear_interrupt(void)
- * {
- * // Write to the ICR (interrupt clear register) of the TIMER
- * TIMER_ICR = TIMER_ICR_COMPARE_Msk;
- * }
- * @endcode
- */
-void us_ticker_clear_interrupt(void);
-
-/** Set pending interrupt that should be fired right away.
- *
- * The ticker should be initialized prior calling this function.
- *
- * Pseudo Code:
- * @code
- * void us_ticker_fire_interrupt(void)
- * {
- * NVIC_SetPendingIRQ(TIMER_IRQn);
- * }
- * @endcode
- */
-void us_ticker_fire_interrupt(void);
-
-/** Get frequency and counter bits of this ticker.
- *
- * Pseudo Code:
- * @code
- * const ticker_info_t* us_ticker_get_info()
- * {
- * static const ticker_info_t info = {
- * 1000000, // 1 MHz
- * 32 // 32 bit counter
- * };
- * return &info;
- * }
- * @endcode
- */
-const ticker_info_t *us_ticker_get_info(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/mbed.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,112 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_H -#define MBED_H - -#include "platform/mbed_version.h" - -#if MBED_CONF_RTOS_PRESENT -#include "rtos/rtos.h" -#endif - -#if MBED_CONF_NSAPI_PRESENT -#include "netsocket/nsapi.h" -#include "netsocket/nsapi_ppp.h" -#endif - -#if MBED_CONF_EVENTS_PRESENT -#include "events/mbed_events.h" -#endif - -#if MBED_CONF_FILESYSTEM_PRESENT -#include "filesystem/mbed_filesystem.h" -#endif - -#include "platform/mbed_toolchain.h" -#include "platform/platform.h" -#include "platform/mbed_application.h" - -// Useful C libraries -#include <math.h> -#include <time.h> - -// mbed Debug libraries -#include "platform/mbed_error.h" -#include "platform/mbed_interface.h" -#include "platform/mbed_assert.h" -#include "platform/mbed_debug.h" - -// mbed Peripheral components -#include "drivers/DigitalIn.h" -#include "drivers/DigitalOut.h" -#include "drivers/DigitalInOut.h" -#include "drivers/BusIn.h" -#include "drivers/BusOut.h" -#include "drivers/BusInOut.h" -#include "drivers/PortIn.h" -#include "drivers/PortInOut.h" -#include "drivers/PortOut.h" -#include "drivers/AnalogIn.h" -#include "drivers/AnalogOut.h" -#include "drivers/PwmOut.h" -#include "drivers/Serial.h" -#include "drivers/SPI.h" -#include "drivers/SPISlave.h" -#include "drivers/I2C.h" -#include "drivers/I2CSlave.h" -#include "drivers/Ethernet.h" -#include "drivers/CAN.h" -#include "drivers/RawSerial.h" -#include "drivers/UARTSerial.h" -#include "drivers/FlashIAP.h" -#include "drivers/MbedCRC.h" -#include "drivers/QSPI.h" - -// mbed Internal components -#include "drivers/Timer.h" -#include "drivers/Ticker.h" -#include "drivers/Timeout.h" -#include "drivers/LowPowerTimeout.h" -#include "drivers/LowPowerTicker.h" -#include "drivers/LowPowerTimer.h" -#include "platform/LocalFileSystem.h" -#include "drivers/InterruptIn.h" -#include "platform/mbed_wait_api.h" -#include "hal/sleep_api.h" -#include "platform/mbed_power_mgmt.h" -#include "platform/mbed_rtc_time.h" -#include "platform/mbed_poll.h" -#include "platform/ATCmdParser.h" -#include "platform/FileSystemHandle.h" -#include "platform/FileHandle.h" -#include "platform/DirHandle.h" -#include "platform/CriticalSectionLock.h" -#include "platform/DeepSleepLock.h" -#include "platform/ScopedRomWriteLock.h" -#include "platform/ScopedRamExecutionLock.h" -#include "platform/mbed_stats.h" - -// mbed Non-hardware components -#include "platform/Callback.h" -#include "platform/FunctionPointer.h" -#include "platform/ScopedLock.h" - -#ifndef MBED_NO_GLOBAL_USING_DIRECTIVE -using namespace mbed; -using namespace std; -#endif - -#endif
--- a/STM32F103C8T6_MPA/mbed/platform/ATCmdParser.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,324 +0,0 @@
-/* Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * @section DESCRIPTION
- *
- * Parser for the AT command syntax
- *
- */
-#ifndef MBED_ATCMDPARSER_H
-#define MBED_ATCMDPARSER_H
-
-#include <cstdarg>
-#include "Callback.h"
-#include "NonCopyable.h"
-#include "FileHandle.h"
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_ATCmdParser ATCmdParser class
- * @{
- */
-
-/**
- * Parser class for parsing AT commands
- *
- * Here are some examples:
- * @code
- * UARTSerial serial = UARTSerial(D1, D0);
- * ATCmdParser at = ATCmdParser(&serial, "\r\n");
- * int value;
- * char buffer[100];
- *
- * at.send("AT") && at.recv("OK");
- * at.send("AT+CWMODE=%d", 3) && at.recv("OK");
- * at.send("AT+CWMODE?") && at.recv("+CWMODE:%d\r\nOK", &value);
- * at.recv("+IPD,%d:", &value);
- * at.read(buffer, value);
- * at.recv("OK");
- * @endcode
- */
-
-class ATCmdParser : private NonCopyable<ATCmdParser> {
-private:
- // File handle
- // Not owned by ATCmdParser
- FileHandle *_fh;
-
- int _buffer_size;
- char *_buffer;
- int _timeout;
-
- // Parsing information
- const char *_output_delimiter;
- int _output_delim_size;
- int _oob_cb_count;
- char _in_prev;
- bool _dbg_on;
- bool _aborted;
-
- struct oob {
- unsigned len;
- const char *prefix;
- mbed::Callback<void()> cb;
- oob *next;
- };
- oob *_oobs;
-
-public:
-
- /**
- * Constructor
- *
- * @param fh A FileHandle to the digital interface, used for AT commands
- * @param output_delimiter End of command-line termination
- * @param buffer_size Size of internal buffer for transaction
- * @param timeout Timeout of the connection
- * @param debug Turns on/off debug output for AT commands
- */
- ATCmdParser(FileHandle *fh, const char *output_delimiter = "\r",
- int buffer_size = 256, int timeout = 8000, bool debug = false)
- : _fh(fh), _buffer_size(buffer_size), _oob_cb_count(0), _in_prev(0), _oobs(NULL)
- {
- _buffer = new char[buffer_size];
- set_timeout(timeout);
- set_delimiter(output_delimiter);
- debug_on(debug);
- }
-
- /**
- * Destructor
- */
- ~ATCmdParser()
- {
- while (_oobs) {
- struct oob *oob = _oobs;
- _oobs = oob->next;
- delete oob;
- }
- delete[] _buffer;
- }
-
- /**
- * Allows timeout to be changed between commands
- *
- * @param timeout ATCmdParser APIs (read/write/send/recv ..etc) throw an
- * error if no response is received in `timeout` duration
- */
- void set_timeout(int timeout)
- {
- _timeout = timeout;
- }
-
- /**
- * For backward compatibility.
- * @deprecated Do not use this function. This function has been replaced with set_timeout for consistency.
- *
- * Please use set_timeout(int) API only from now on.
- * Allows timeout to be changed between commands
- *
- * @param timeout ATCmdParser APIs (read/write/send/recv ..etc) throw an
- * error if no response is received in `timeout` duration
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with set_timeout for consistency")
- void setTimeout(int timeout)
- {
- set_timeout(timeout);
- }
-
- /**
- * Sets string of characters to use as line delimiters
- *
- * @param output_delimiter String of characters to use as line delimiters
- */
- void set_delimiter(const char *output_delimiter)
- {
- _output_delimiter = output_delimiter;
- _output_delim_size = strlen(output_delimiter);
- }
-
- /**
- * For backwards compatibility.
- * @deprecated Do not use this function. This function has been replaced with set_delimiter for consistency.
- *
- * Please use set_delimiter(const char *) API only from now on.
- * Sets string of characters to use as line delimiters
- *
- * @param output_delimiter string of characters to use as line delimiters
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with set_delimiter for consistency")
- void setDelimiter(const char *output_delimiter)
- {
- set_delimiter(output_delimiter);
- }
-
- /**
- * Allows traces from modem to be turned on or off
- *
- * @param on Set as 1 to turn on traces and 0 to disable traces.
- */
- void debug_on(uint8_t on)
- {
- _dbg_on = (on) ? 1 : 0;
- }
-
- /**
- * For backward compatibility.
- * @deprecated Do not use this function. This function has been replaced with debug_on for consistency.
- *
- * Allows traces from modem to be turned on or off
- *
- * @param on Set as 1 to turn on traces and 0 to disable traces.
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.5.0", "Replaced with debug_on for consistency")
- void debugOn(uint8_t on)
- {
- debug_on(on);
- }
-
- /**
- * Sends an AT command
- *
- * Sends a formatted command using printf style formatting
- * @see printf
- *
- * @param command printf-like format string of command to send which
- * is appended with a newline
- * @param ... all printf-like arguments to insert into command
- * @return true only if command is successfully sent
- */
- bool send(const char *command, ...) MBED_PRINTF_METHOD(1, 2);
-
- bool vsend(const char *command, std::va_list args);
-
- /**
- * Receive an AT response
- *
- * Receives a formatted response using scanf style formatting
- * @see scanf
- *
- * Responses are parsed line at a time.
- * Any received data that does not match the response is ignored until
- * a timeout occurs.
- *
- * @param response scanf-like format string of response to expect
- * @param ... all scanf-like arguments to extract from response
- * @return true only if response is successfully matched
- */
- bool recv(const char *response, ...) MBED_SCANF_METHOD(1, 2);
-
- bool vrecv(const char *response, std::va_list args);
-
- /**
- * Write a single byte to the underlying stream
- *
- * @param c The byte to write
- * @return The byte that was written or -1 during a timeout
- */
- int putc(char c);
-
- /**
- * Get a single byte from the underlying stream
- *
- * @return The byte that was read or -1 during a timeout
- */
- int getc();
-
- /**
- * Write an array of bytes to the underlying stream
- *
- * @param data The array of bytes to write
- * @param size Number of bytes to write
- * @return number of bytes written or -1 on failure
- */
- int write(const char *data, int size);
-
- /**
- * Read an array of bytes from the underlying stream
- *
- * @param data The buffer for filling the read bytes
- * @param size Number of bytes to read
- * @return number of bytes read or -1 on failure
- */
- int read(char *data, int size);
-
- /**
- * Direct printf to underlying stream
- * @see printf
- *
- * @param format Format string to pass to printf
- * @param ... Variable arguments to printf
- * @return number of bytes written or -1 on failure
- */
- int printf(const char *format, ...) MBED_PRINTF_METHOD(1, 2);
-
- int vprintf(const char *format, std::va_list args);
-
- /**
- * Direct scanf on underlying stream
- * @see scanf
- *
- * @param format Format string to pass to scanf
- * @param ... Variable arguments to scanf
- * @return number of bytes read or -1 on failure
- */
- int scanf(const char *format, ...) MBED_SCANF_METHOD(1, 2);
-
- int vscanf(const char *format, std::va_list args);
-
- /**
- * Attach a callback for out-of-band data
- *
- * @param prefix String on when to initiate callback
- * @param func Callback to call when string is read
- * @note out-of-band data is only processed during a scanf call
- */
- void oob(const char *prefix, mbed::Callback<void()> func);
-
- /**
- * Flushes the underlying stream
- */
- void flush();
-
- /**
- * Abort current recv
- *
- * Can be called from out-of-band handler to interrupt the current
- * recv operation.
- */
- void abort();
-
- /**
- * Process out-of-band data
- *
- * Process out-of-band data in the receive buffer. This function
- * returns immediately if there is no data to process.
- *
- * @return true if out-of-band data processed, false otherwise
- */
- bool process_oob(void);
-};
-
-/**@}*/
-
-/**@}*/
-
-} //namespace mbed
-
-#endif //MBED_ATCMDPARSER_H
--- a/STM32F103C8T6_MPA/mbed/platform/CThunk.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,174 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_CThunk CThunk class
- * @{
- */
-/* General C++ Object Thunking class
- *
- * - allows direct callbacks to non-static C++ class functions
- * - keeps track for the corresponding class instance
- * - supports an optional context parameter for the called function
- * - ideally suited for class object receiving interrupts (NVIC_SetVector)
- *
- * Copyright (c) 2014-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* General C++ Object Thunking class
- *
- * - allows direct callbacks to non-static C++ class functions
- * - keeps track for the corresponding class instance
- * - supports an optional context parameter for the called function
- * - ideally suited for class object receiving interrupts (NVIC_SetVector)
- */
-
-#ifndef __CTHUNK_H__
-#define __CTHUNK_H__
-
-#include "CThunkBase.h"
-
-/**
- * Class for created a pointer with data bound to it
- *
- * @note Synchronization level: Not protected
- */
-template<class T>
-class CThunk: public CThunkBase {
-public:
- typedef void (T::*CCallbackSimple)(void);
- typedef void (T::*CCallback)(void *context);
-
- inline CThunk(T *instance)
- {
- init(instance, NULL, NULL);
- }
-
- inline CThunk(T *instance, CCallback callback)
- {
- init(instance, callback, NULL);
- }
-
- ~CThunk()
- {
- cthunk_free(_entry);
- _entry = NULL;
- }
-
- inline CThunk(T *instance, CCallbackSimple callback)
- {
- init(instance, (CCallback)callback, NULL);
- }
-
- inline CThunk(T &instance, CCallback callback)
- {
- init(instance, callback, NULL);
- }
-
- inline CThunk(T &instance, CCallbackSimple callback)
- {
- init(instance, (CCallback)callback, NULL);
- }
-
- inline CThunk(T &instance, CCallback callback, void *context)
- {
- init(instance, callback, context);
- }
-
- inline void callback(CCallback callback)
- {
- _callback = callback;
- }
-
- inline void callback(CCallbackSimple callback)
- {
- _callback_simple = callback;
- }
-
- inline void context(void *context)
- {
- _context = context;
- }
-
- inline void context(uint32_t context)
- {
- _context = (void *)context;
- }
-
- inline uint32_t entry(void)
- {
- if (_entry == NULL) {
- _entry = cthunk_alloc(this);
- }
- return (uint32_t)_entry;
- }
-
- /* get thunk entry point for connecting rhunk to an IRQ table */
- inline operator CThunkEntry(void)
- {
- return (CThunkEntry)entry();
- }
-
- /* get thunk entry point for connecting rhunk to an IRQ table */
- inline operator uint32_t(void)
- {
- return entry();
- }
-
- /* simple test function */
- inline void call(void)
- {
- (((CThunkEntry)(entry()))());
- }
-
-private:
- T *_instance;
- void *_context;
- union {
- CCallbackSimple _callback_simple;
- CCallback _callback;
- };
-
- CThunkEntry _entry;
-
- static void trampoline(CThunkBase *base)
- {
- CThunk<T> *self = static_cast<CThunk<T>*>(base);
- T *instance = self->_instance;
- void *context = self->_context;
- CCallback callback = self->_callback;
-
- if (instance && callback) {
- (instance->*callback)(context);
- }
- }
-
- inline void init(T *instance, CCallback callback, void *context)
- {
- _instance = instance;
- _context = context;
- _callback = callback;
- _trampoline = &trampoline;
- _entry = 0;
- }
-};
-
-/**@}*/
-
-/**@}*/
-
-#endif/*__CTHUNK_H__*/
-
--- a/STM32F103C8T6_MPA/mbed/platform/CThunkBase.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2018-2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CTHUNK_BASE_H__
-#define __CTHUNK_BASE_H__
-
-/* IRQ/Exception compatible thunk entry function */
-typedef void (*CThunkEntry)(void);
-
-class CThunkBase {
-protected:
- typedef void (*Trampoline)(CThunkBase *);
-
- Trampoline _trampoline;
-
- /*
- * Allocate a CThunkEntry which can be called without arguments
- *
- * Calling the CThunkEntry invokes the _trampoline of the
- * given cthunk. This function traps if there are no more
- * free thunks.
- */
- static CThunkEntry cthunk_alloc(CThunkBase *cthunk);
-
- /*
- * Free a cthunk_entry so it can be reused
- */
- static void cthunk_free(CThunkEntry cthunk_entry);
-
-private:
- typedef void (*CthunkFree)(CThunkEntry cthunk_entry);
-
- /*
- * Table of thunk functions
- */
- static const CThunkEntry _thunk_table[MBED_CONF_PLATFORM_CTHUNK_COUNT_MAX];
-
- /*
- * Table of active CThunk classes
- */
- static CThunkBase *_thunk_storage[MBED_CONF_PLATFORM_CTHUNK_COUNT_MAX];
-
- /*
- * Lazily initialized free function pointer
- */
- static CthunkFree _cthunk_free_real;
-
- /*
- * Actual free function
- */
- static void cthunk_free_real(CThunkEntry cthunk_entry);
-
- /*
- * Template function which stored in the _thunk_table
- */
- template<int N>
- static void thunk_entry()
- {
- _thunk_storage[N]->_trampoline(_thunk_storage[N]);
- }
-};
-
-#endif/*__CTHUNK_BASE_H__*/
-
--- a/STM32F103C8T6_MPA/mbed/platform/CallChain.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,265 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CALLCHAIN_H
-#define MBED_CALLCHAIN_H
-
-#include "platform/Callback.h"
-#include "platform/mbed_toolchain.h"
-#include "platform/NonCopyable.h"
-#include <string.h>
-
-namespace mbed {
-
-
-typedef Callback<void()> *pFunctionPointer_t;
-class CallChainLink;
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_CallChain CallChain class
- * @{
- */
-
-/** Group one or more functions in an instance of a CallChain, then call them in
- * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
- * but can be used for other purposes.
- *
- * @deprecated Do not use this class. This class is not part of the public API of mbed-os and is being removed in the future.
- * @note Synchronization level: Not protected
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * CallChain chain;
- *
- * void first(void) {
- * printf("'first' function.\n");
- * }
- *
- * void second(void) {
- * printf("'second' function.\n");
- * }
- *
- * class Test {
- * public:
- * void f(void) {
- * printf("A::f (class member).\n");
- * }
- * };
- *
- * int main() {
- * Test test;
- *
- * chain.add(second);
- * chain.add_front(first);
- * chain.add(&test, &Test::f);
- * chain.call();
- * }
- * @endcode
- */
-class CallChain : private NonCopyable<CallChain> {
-public:
- /** Create an empty chain
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param size (optional) Initial size of the chain
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- CallChain(int size = 4);
-
- /** Create an empty chain
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- virtual ~CallChain();
-
- /** Add a function at the end of the chain
- *
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param func A pointer to a void function
- *
- * @returns
- * The function object created for 'func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t add(Callback<void()> func);
-
- /** Add a function at the end of the chain
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- *
- * @returns
- * The function object created for 'obj' and 'method'
- *
- * @deprecated
- * The add function does not support cv-qualifiers. Replaced by
- * add(callback(obj, method)).
- */
- template<typename T, typename M>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The add function does not support cv-qualifiers. Replaced by "
- "add(callback(obj, method)).")
- pFunctionPointer_t add(T *obj, M method)
- {
- return add(callback(obj, method));
- }
-
- /** Add a function at the beginning of the chain
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- *
- * @param func A pointer to a void function
- *
- * @returns
- * The function object created for 'func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t add_front(Callback<void()> func);
-
- /** Add a function at the beginning of the chain
- *
- * @param obj pointer to the object to call the member function on
- * @param method pointer to the member function to be called
- *
- * @returns
- * The function object created for the object and method pointers
- *
- * @deprecated
- * The add_front function does not support cv-qualifiers. Replaced by
- * add_front(callback(obj, method)).
- */
- template<typename T, typename M>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "The add_front function does not support cv-qualifiers. Replaced by "
- "add_front(callback(obj, method)).")
- pFunctionPointer_t add_front(T *obj, M method)
- {
- return add_front(callback(obj, method));
- }
-
- /** Get the number of functions in the chain
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- int size() const;
-
- /** Get a function object from the chain
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param i function object index
- *
- * @returns
- * The function object at position 'i' in the chain
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t get(int i) const;
-
- /** Look for a function object in the call chain
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @param f the function object to search
- *
- * @returns
- * The index of the function object if found, -1 otherwise.
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- int find(pFunctionPointer_t f) const;
-
- /** Clear the call chain (remove all functions in the chain).
- * @deprecated Do not use this function. This class is not part of the public API of mbed-os and is being removed in the future.
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- void clear();
-
- /** Remove a function object from the chain
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- * @arg f the function object to remove
- *
- * @returns
- * true if the function object was found and removed, false otherwise.
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- bool remove(pFunctionPointer_t f);
-
- /** Call all the functions in the chain in sequence
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- void call();
-
- /**
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- void operator()(void)
- {
- call();
- }
-
- /**
- * @deprecated
- * Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
- "public API of mbed-os and is being removed in the future.")
- pFunctionPointer_t operator [](int i) const
- {
- return get(i);
- }
-
-private:
- CallChainLink *_chain;
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/platform/Callback.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,4939 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CALLBACK_H
-#define MBED_CALLBACK_H
-
-#include <string.h>
-#include <stdint.h>
-#include <new>
-#include "platform/mbed_assert.h"
-#include "platform/mbed_toolchain.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_Callback Callback class
- * @{
- */
-
-/** Callback class based on template specialization
- *
- * @note Synchronization level: Not protected
- */
-template <typename F>
-class Callback;
-
-// Internal sfinae declarations
-//
-// These are used to eliminate overloads based on type attributes
-// 1. Does a function object have a call operator
-// 2. Does a function object fit in the available storage
-//
-// These eliminations are handled cleanly by the compiler and avoid
-// massive and misleading error messages when confronted with an
-// invalid type (or worse, runtime failures)
-namespace detail {
-struct nil {};
-
-template <bool B, typename R = nil>
-struct enable_if {
- typedef R type;
-};
-
-template <typename R>
-struct enable_if<false, R> {};
-
-template <typename M, M>
-struct is_type {
- static const bool value = true;
-};
-}
-
-#define MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M) \
- typename detail::enable_if< \
- detail::is_type<M, &F::operator()>::value && \
- sizeof(F) <= sizeof(uintptr_t) \
- >::type = detail::nil()
-
-/** Callback class based on template specialization
- *
- * @note Synchronization level: Not protected
- */
-template <typename R>
-class Callback<R()> {
-public:
- /** Create a Callback with a static function
- * @param func Static function to attach
- */
- Callback(R(*func)() = 0)
- {
- if (!func) {
- memset(this, 0, sizeof(Callback));
- } else {
- generate(func);
- }
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- */
- Callback(const Callback<R()> &func)
- {
- if (func._ops) {
- func._ops->move(this, &func);
- }
- _ops = func._ops;
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(U *obj, R(T::*method)())
- {
- generate(method_context<T, R(T::*)()>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const U *obj, R(T::*method)() const)
- {
- generate(method_context<const T, R(T::*)() const>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(volatile U *obj, R(T::*method)() volatile)
- {
- generate(method_context<volatile T, R(T::*)() volatile>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const volatile U *obj, R(T::*method)() const volatile)
- {
- generate(method_context<const volatile T, R(T::*)() const volatile>(obj, method));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(T *), U *arg)
- {
- generate(function_context<R(*)(T *), T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const T *), const U *arg)
- {
- generate(function_context<R(*)(const T *), const T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(volatile T *), volatile U *arg)
- {
- generate(function_context<R(*)(volatile T *), volatile T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const volatile T *), const volatile U *arg)
- {
- generate(function_context<R(*)(const volatile T *), const volatile T>(func, arg));
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)()))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(U *obj, R(*func)(T *))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const U *obj, R(*func)(const T *))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(volatile U *obj, R(*func)(volatile T *))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const volatile U *obj, R(*func)(const volatile T *))
- {
- new (this) Callback(func, obj);
- }
-
- /** Destroy a callback
- */
- ~Callback()
- {
- if (_ops) {
- _ops->dtor(this);
- }
- }
-
- /** Attach a static function
- * @param func Static function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)())
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const Callback<R()> &func)
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(U *obj, R(T::*method)())
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const U *obj, R(T::*method)() const)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile U *obj, R(T::*method)() volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile U *obj, R(T::*method)() const volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(T *), U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const T *), const U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(volatile T *), volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const volatile T *), const volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)()))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)() const volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(U *obj, R(*func)(T *))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const U *obj, R(*func)(const T *))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(volatile U *obj, R(*func)(volatile T *))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const volatile U *obj, R(*func)(const volatile T *))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Assign a callback
- */
- Callback &operator=(const Callback &that)
- {
- if (this != &that) {
- this->~Callback();
- new (this) Callback(that);
- }
-
- return *this;
- }
-
- /** Call the attached function
- */
- R call() const
- {
- MBED_ASSERT(_ops);
- return _ops->call(this);
- }
-
- /** Call the attached function
- */
- R operator()() const
- {
- return call();
- }
-
- /** Test if function has been attached
- */
- operator bool() const
- {
- return _ops;
- }
-
- /** Test for equality
- */
- friend bool operator==(const Callback &l, const Callback &r)
- {
- return memcmp(&l, &r, sizeof(Callback)) == 0;
- }
-
- /** Test for inequality
- */
- friend bool operator!=(const Callback &l, const Callback &r)
- {
- return !(l == r);
- }
-
- /** Static thunk for passing as C-style function
- * @param func Callback to call passed as void pointer
- * @return the value as determined by func which is of
- * type and determined by the signature of func
- */
- static R thunk(void *func)
- {
- return static_cast<Callback *>(func)->call();
- }
-
-private:
- // Stored as pointer to function and pointer to optional object
- // Function pointer is stored as union of possible function types
- // to guarantee proper size and alignment
- struct _class;
- union {
- void (*_staticfunc)();
- void (*_boundfunc)(_class *);
- void (_class::*_methodfunc)();
- } _func;
- void *_obj;
-
- // Dynamically dispatched operations
- const struct ops {
- R(*call)(const void *);
- void (*move)(void *, const void *);
- void (*dtor)(void *);
- } *_ops;
-
- // Generate operations for function object
- template <typename F>
- void generate(const F &f)
- {
- static const ops ops = {
- &Callback::function_call<F>,
- &Callback::function_move<F>,
- &Callback::function_dtor<F>,
- };
-
- MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
- "Type F must not exceed the size of the Callback class");
- memset(this, 0, sizeof(Callback));
- new (this) F(f);
- _ops = &ops;
- }
-
- // Function attributes
- template <typename F>
- static R function_call(const void *p)
- {
- return (*(F *)p)();
- }
-
- template <typename F>
- static void function_move(void *d, const void *p)
- {
- new (d) F(*(F *)p);
- }
-
- template <typename F>
- static void function_dtor(void *p)
- {
- ((F *)p)->~F();
- }
-
- // Wrappers for functions with context
- template <typename O, typename M>
- struct method_context {
- M method;
- O *obj;
-
- method_context(O *obj, M method)
- : method(method), obj(obj) {}
-
- R operator()() const
- {
- return (obj->*method)();
- }
- };
-
- template <typename F, typename A>
- struct function_context {
- F func;
- A *arg;
-
- function_context(F func, A *arg)
- : func(func), arg(arg) {}
-
- R operator()() const
- {
- return func(arg);
- }
- };
-};
-
-/** Callback class based on template specialization
- *
- * @note Synchronization level: Not protected
- */
-template <typename R, typename A0>
-class Callback<R(A0)> {
-public:
- /** Create a Callback with a static function
- * @param func Static function to attach
- */
- Callback(R(*func)(A0) = 0)
- {
- if (!func) {
- memset(this, 0, sizeof(Callback));
- } else {
- generate(func);
- }
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- */
- Callback(const Callback<R(A0)> &func)
- {
- if (func._ops) {
- func._ops->move(this, &func);
- }
- _ops = func._ops;
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(U *obj, R(T::*method)(A0))
- {
- generate(method_context<T, R(T::*)(A0)>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const U *obj, R(T::*method)(A0) const)
- {
- generate(method_context<const T, R(T::*)(A0) const>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(volatile U *obj, R(T::*method)(A0) volatile)
- {
- generate(method_context<volatile T, R(T::*)(A0) volatile>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const volatile U *obj, R(T::*method)(A0) const volatile)
- {
- generate(method_context<const volatile T, R(T::*)(A0) const volatile>(obj, method));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(T *, A0), U *arg)
- {
- generate(function_context<R(*)(T *, A0), T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const T *, A0), const U *arg)
- {
- generate(function_context<R(*)(const T *, A0), const T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(volatile T *, A0), volatile U *arg)
- {
- generate(function_context<R(*)(volatile T *, A0), volatile T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const volatile T *, A0), const volatile U *arg)
- {
- generate(function_context<R(*)(const volatile T *, A0), const volatile T>(func, arg));
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0)))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(U *obj, R(*func)(T *, A0))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const U *obj, R(*func)(const T *, A0))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(volatile U *obj, R(*func)(volatile T *, A0))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const volatile U *obj, R(*func)(const volatile T *, A0))
- {
- new (this) Callback(func, obj);
- }
-
- /** Destroy a callback
- */
- ~Callback()
- {
- if (_ops) {
- _ops->dtor(this);
- }
- }
-
- /** Attach a static function
- * @param func Static function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(A0))
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const Callback<R(A0)> &func)
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(U *obj, R(T::*method)(A0))
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const U *obj, R(T::*method)(A0) const)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile U *obj, R(T::*method)(A0) volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile U *obj, R(T::*method)(A0) const volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(T *, A0), U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const T *, A0), const U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(volatile T *, A0), volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const volatile T *, A0), const volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0)))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0) const volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(U *obj, R(*func)(T *, A0))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const U *obj, R(*func)(const T *, A0))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(volatile U *obj, R(*func)(volatile T *, A0))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const volatile U *obj, R(*func)(const volatile T *, A0))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Assign a callback
- */
- Callback &operator=(const Callback &that)
- {
- if (this != &that) {
- this->~Callback();
- new (this) Callback(that);
- }
-
- return *this;
- }
-
- /** Call the attached function
- */
- R call(A0 a0) const
- {
- MBED_ASSERT(_ops);
- return _ops->call(this, a0);
- }
-
- /** Call the attached function
- */
- R operator()(A0 a0) const
- {
- return call(a0);
- }
-
- /** Test if function has been attached
- */
- operator bool() const
- {
- return _ops;
- }
-
- /** Test for equality
- */
- friend bool operator==(const Callback &l, const Callback &r)
- {
- return memcmp(&l, &r, sizeof(Callback)) == 0;
- }
-
- /** Test for inequality
- */
- friend bool operator!=(const Callback &l, const Callback &r)
- {
- return !(l == r);
- }
-
- /** Static thunk for passing as C-style function
- * @param func Callback to call passed as void pointer
- * @param a0 An argument to be called with function func
- * @return the value as determined by func which is of
- * type and determined by the signature of func
- */
- static R thunk(void *func, A0 a0)
- {
- return static_cast<Callback *>(func)->call(a0);
- }
-
-private:
- // Stored as pointer to function and pointer to optional object
- // Function pointer is stored as union of possible function types
- // to guarantee proper size and alignment
- struct _class;
- union {
- void (*_staticfunc)(A0);
- void (*_boundfunc)(_class *, A0);
- void (_class::*_methodfunc)(A0);
- } _func;
- void *_obj;
-
- // Dynamically dispatched operations
- const struct ops {
- R(*call)(const void *, A0);
- void (*move)(void *, const void *);
- void (*dtor)(void *);
- } *_ops;
-
- // Generate operations for function object
- template <typename F>
- void generate(const F &f)
- {
- static const ops ops = {
- &Callback::function_call<F>,
- &Callback::function_move<F>,
- &Callback::function_dtor<F>,
- };
-
- MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
- "Type F must not exceed the size of the Callback class");
- memset(this, 0, sizeof(Callback));
- new (this) F(f);
- _ops = &ops;
- }
-
- // Function attributes
- template <typename F>
- static R function_call(const void *p, A0 a0)
- {
- return (*(F *)p)(a0);
- }
-
- template <typename F>
- static void function_move(void *d, const void *p)
- {
- new (d) F(*(F *)p);
- }
-
- template <typename F>
- static void function_dtor(void *p)
- {
- ((F *)p)->~F();
- }
-
- // Wrappers for functions with context
- template <typename O, typename M>
- struct method_context {
- M method;
- O *obj;
-
- method_context(O *obj, M method)
- : method(method), obj(obj) {}
-
- R operator()(A0 a0) const
- {
- return (obj->*method)(a0);
- }
- };
-
- template <typename F, typename A>
- struct function_context {
- F func;
- A *arg;
-
- function_context(F func, A *arg)
- : func(func), arg(arg) {}
-
- R operator()(A0 a0) const
- {
- return func(arg, a0);
- }
- };
-};
-
-/** Callback class based on template specialization
- *
- * @note Synchronization level: Not protected
- */
-template <typename R, typename A0, typename A1>
-class Callback<R(A0, A1)> {
-public:
- /** Create a Callback with a static function
- * @param func Static function to attach
- */
- Callback(R(*func)(A0, A1) = 0)
- {
- if (!func) {
- memset(this, 0, sizeof(Callback));
- } else {
- generate(func);
- }
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- */
- Callback(const Callback<R(A0, A1)> &func)
- {
- if (func._ops) {
- func._ops->move(this, &func);
- }
- _ops = func._ops;
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(U *obj, R(T::*method)(A0, A1))
- {
- generate(method_context<T, R(T::*)(A0, A1)>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const U *obj, R(T::*method)(A0, A1) const)
- {
- generate(method_context<const T, R(T::*)(A0, A1) const>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(volatile U *obj, R(T::*method)(A0, A1) volatile)
- {
- generate(method_context<volatile T, R(T::*)(A0, A1) volatile>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const volatile U *obj, R(T::*method)(A0, A1) const volatile)
- {
- generate(method_context<const volatile T, R(T::*)(A0, A1) const volatile>(obj, method));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(T *, A0, A1), U *arg)
- {
- generate(function_context<R(*)(T *, A0, A1), T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const T *, A0, A1), const U *arg)
- {
- generate(function_context<R(*)(const T *, A0, A1), const T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(volatile T *, A0, A1), volatile U *arg)
- {
- generate(function_context<R(*)(volatile T *, A0, A1), volatile T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const volatile T *, A0, A1), const volatile U *arg)
- {
- generate(function_context<R(*)(const volatile T *, A0, A1), const volatile T>(func, arg));
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1)))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(U *obj, R(*func)(T *, A0, A1))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const U *obj, R(*func)(const T *, A0, A1))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(volatile U *obj, R(*func)(volatile T *, A0, A1))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1))
- {
- new (this) Callback(func, obj);
- }
-
- /** Destroy a callback
- */
- ~Callback()
- {
- if (_ops) {
- _ops->dtor(this);
- }
- }
-
- /** Attach a static function
- * @param func Static function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(A0, A1))
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const Callback<R(A0, A1)> &func)
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(U *obj, R(T::*method)(A0, A1))
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const U *obj, R(T::*method)(A0, A1) const)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile U *obj, R(T::*method)(A0, A1) volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile U *obj, R(T::*method)(A0, A1) const volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(T *, A0, A1), U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const T *, A0, A1), const U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(volatile T *, A0, A1), volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const volatile T *, A0, A1), const volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1)))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1) const volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(U *obj, R(*func)(T *, A0, A1))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const U *obj, R(*func)(const T *, A0, A1))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(volatile U *obj, R(*func)(volatile T *, A0, A1))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Assign a callback
- */
- Callback &operator=(const Callback &that)
- {
- if (this != &that) {
- this->~Callback();
- new (this) Callback(that);
- }
-
- return *this;
- }
-
- /** Call the attached function
- */
- R call(A0 a0, A1 a1) const
- {
- MBED_ASSERT(_ops);
- return _ops->call(this, a0, a1);
- }
-
- /** Call the attached function
- */
- R operator()(A0 a0, A1 a1) const
- {
- return call(a0, a1);
- }
-
- /** Test if function has been attached
- */
- operator bool() const
- {
- return _ops;
- }
-
- /** Test for equality
- */
- friend bool operator==(const Callback &l, const Callback &r)
- {
- return memcmp(&l, &r, sizeof(Callback)) == 0;
- }
-
- /** Test for inequality
- */
- friend bool operator!=(const Callback &l, const Callback &r)
- {
- return !(l == r);
- }
-
- /** Static thunk for passing as C-style function
- * @param func Callback to call passed as void pointer
- * @param a0 An argument to be called with function func
- * @param a1 An argument to be called with function func
- * @return the value as determined by func which is of
- * type and determined by the signature of func
- */
- static R thunk(void *func, A0 a0, A1 a1)
- {
- return static_cast<Callback *>(func)->call(a0, a1);
- }
-
-private:
- // Stored as pointer to function and pointer to optional object
- // Function pointer is stored as union of possible function types
- // to guarantee proper size and alignment
- struct _class;
- union {
- void (*_staticfunc)(A0, A1);
- void (*_boundfunc)(_class *, A0, A1);
- void (_class::*_methodfunc)(A0, A1);
- } _func;
- void *_obj;
-
- // Dynamically dispatched operations
- const struct ops {
- R(*call)(const void *, A0, A1);
- void (*move)(void *, const void *);
- void (*dtor)(void *);
- } *_ops;
-
- // Generate operations for function object
- template <typename F>
- void generate(const F &f)
- {
- static const ops ops = {
- &Callback::function_call<F>,
- &Callback::function_move<F>,
- &Callback::function_dtor<F>,
- };
-
- MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
- "Type F must not exceed the size of the Callback class");
- memset(this, 0, sizeof(Callback));
- new (this) F(f);
- _ops = &ops;
- }
-
- // Function attributes
- template <typename F>
- static R function_call(const void *p, A0 a0, A1 a1)
- {
- return (*(F *)p)(a0, a1);
- }
-
- template <typename F>
- static void function_move(void *d, const void *p)
- {
- new (d) F(*(F *)p);
- }
-
- template <typename F>
- static void function_dtor(void *p)
- {
- ((F *)p)->~F();
- }
-
- // Wrappers for functions with context
- template <typename O, typename M>
- struct method_context {
- M method;
- O *obj;
-
- method_context(O *obj, M method)
- : method(method), obj(obj) {}
-
- R operator()(A0 a0, A1 a1) const
- {
- return (obj->*method)(a0, a1);
- }
- };
-
- template <typename F, typename A>
- struct function_context {
- F func;
- A *arg;
-
- function_context(F func, A *arg)
- : func(func), arg(arg) {}
-
- R operator()(A0 a0, A1 a1) const
- {
- return func(arg, a0, a1);
- }
- };
-};
-
-/** Callback class based on template specialization
- *
- * @note Synchronization level: Not protected
- */
-template <typename R, typename A0, typename A1, typename A2>
-class Callback<R(A0, A1, A2)> {
-public:
- /** Create a Callback with a static function
- * @param func Static function to attach
- */
- Callback(R(*func)(A0, A1, A2) = 0)
- {
- if (!func) {
- memset(this, 0, sizeof(Callback));
- } else {
- generate(func);
- }
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- */
- Callback(const Callback<R(A0, A1, A2)> &func)
- {
- if (func._ops) {
- func._ops->move(this, &func);
- }
- _ops = func._ops;
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(U *obj, R(T::*method)(A0, A1, A2))
- {
- generate(method_context<T, R(T::*)(A0, A1, A2)>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const U *obj, R(T::*method)(A0, A1, A2) const)
- {
- generate(method_context<const T, R(T::*)(A0, A1, A2) const>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(volatile U *obj, R(T::*method)(A0, A1, A2) volatile)
- {
- generate(method_context<volatile T, R(T::*)(A0, A1, A2) volatile>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const volatile U *obj, R(T::*method)(A0, A1, A2) const volatile)
- {
- generate(method_context<const volatile T, R(T::*)(A0, A1, A2) const volatile>(obj, method));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(T *, A0, A1, A2), U *arg)
- {
- generate(function_context<R(*)(T *, A0, A1, A2), T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const T *, A0, A1, A2), const U *arg)
- {
- generate(function_context<R(*)(const T *, A0, A1, A2), const T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(volatile T *, A0, A1, A2), volatile U *arg)
- {
- generate(function_context<R(*)(volatile T *, A0, A1, A2), volatile T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const volatile T *, A0, A1, A2), const volatile U *arg)
- {
- generate(function_context<R(*)(const volatile T *, A0, A1, A2), const volatile T>(func, arg));
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2)))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(U *obj, R(*func)(T *, A0, A1, A2))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const U *obj, R(*func)(const T *, A0, A1, A2))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2))
- {
- new (this) Callback(func, obj);
- }
-
- /** Destroy a callback
- */
- ~Callback()
- {
- if (_ops) {
- _ops->dtor(this);
- }
- }
-
- /** Attach a static function
- * @param func Static function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(A0, A1, A2))
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const Callback<R(A0, A1, A2)> &func)
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(U *obj, R(T::*method)(A0, A1, A2))
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const U *obj, R(T::*method)(A0, A1, A2) const)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile U *obj, R(T::*method)(A0, A1, A2) volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile U *obj, R(T::*method)(A0, A1, A2) const volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(T *, A0, A1, A2), U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const T *, A0, A1, A2), const U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(volatile T *, A0, A1, A2), volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const volatile T *, A0, A1, A2), const volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2)))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2) const volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(U *obj, R(*func)(T *, A0, A1, A2))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const U *obj, R(*func)(const T *, A0, A1, A2))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(volatile U *obj, R(*func)(volatile T *, A0, A1, A2))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Assign a callback
- */
- Callback &operator=(const Callback &that)
- {
- if (this != &that) {
- this->~Callback();
- new (this) Callback(that);
- }
-
- return *this;
- }
-
- /** Call the attached function
- */
- R call(A0 a0, A1 a1, A2 a2) const
- {
- MBED_ASSERT(_ops);
- return _ops->call(this, a0, a1, a2);
- }
-
- /** Call the attached function
- */
- R operator()(A0 a0, A1 a1, A2 a2) const
- {
- return call(a0, a1, a2);
- }
-
- /** Test if function has been attached
- */
- operator bool() const
- {
- return _ops;
- }
-
- /** Test for equality
- */
- friend bool operator==(const Callback &l, const Callback &r)
- {
- return memcmp(&l, &r, sizeof(Callback)) == 0;
- }
-
- /** Test for inequality
- */
- friend bool operator!=(const Callback &l, const Callback &r)
- {
- return !(l == r);
- }
-
- /** Static thunk for passing as C-style function
- * @param func Callback to call passed as void pointer
- * @param a0 An argument to be called with function func
- * @param a1 An argument to be called with function func
- * @param a2 An argument to be called with function func
- * @return the value as determined by func which is of
- * type and determined by the signature of func
- */
- static R thunk(void *func, A0 a0, A1 a1, A2 a2)
- {
- return static_cast<Callback *>(func)->call(a0, a1, a2);
- }
-
-private:
- // Stored as pointer to function and pointer to optional object
- // Function pointer is stored as union of possible function types
- // to guarantee proper size and alignment
- struct _class;
- union {
- void (*_staticfunc)(A0, A1, A2);
- void (*_boundfunc)(_class *, A0, A1, A2);
- void (_class::*_methodfunc)(A0, A1, A2);
- } _func;
- void *_obj;
-
- // Dynamically dispatched operations
- const struct ops {
- R(*call)(const void *, A0, A1, A2);
- void (*move)(void *, const void *);
- void (*dtor)(void *);
- } *_ops;
-
- // Generate operations for function object
- template <typename F>
- void generate(const F &f)
- {
- static const ops ops = {
- &Callback::function_call<F>,
- &Callback::function_move<F>,
- &Callback::function_dtor<F>,
- };
-
- MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
- "Type F must not exceed the size of the Callback class");
- memset(this, 0, sizeof(Callback));
- new (this) F(f);
- _ops = &ops;
- }
-
- // Function attributes
- template <typename F>
- static R function_call(const void *p, A0 a0, A1 a1, A2 a2)
- {
- return (*(F *)p)(a0, a1, a2);
- }
-
- template <typename F>
- static void function_move(void *d, const void *p)
- {
- new (d) F(*(F *)p);
- }
-
- template <typename F>
- static void function_dtor(void *p)
- {
- ((F *)p)->~F();
- }
-
- // Wrappers for functions with context
- template <typename O, typename M>
- struct method_context {
- M method;
- O *obj;
-
- method_context(O *obj, M method)
- : method(method), obj(obj) {}
-
- R operator()(A0 a0, A1 a1, A2 a2) const
- {
- return (obj->*method)(a0, a1, a2);
- }
- };
-
- template <typename F, typename A>
- struct function_context {
- F func;
- A *arg;
-
- function_context(F func, A *arg)
- : func(func), arg(arg) {}
-
- R operator()(A0 a0, A1 a1, A2 a2) const
- {
- return func(arg, a0, a1, a2);
- }
- };
-};
-
-/** Callback class based on template specialization
- *
- * @note Synchronization level: Not protected
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3>
-class Callback<R(A0, A1, A2, A3)> {
-public:
- /** Create a Callback with a static function
- * @param func Static function to attach
- */
- Callback(R(*func)(A0, A1, A2, A3) = 0)
- {
- if (!func) {
- memset(this, 0, sizeof(Callback));
- } else {
- generate(func);
- }
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- */
- Callback(const Callback<R(A0, A1, A2, A3)> &func)
- {
- if (func._ops) {
- func._ops->move(this, &func);
- }
- _ops = func._ops;
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(U *obj, R(T::*method)(A0, A1, A2, A3))
- {
- generate(method_context<T, R(T::*)(A0, A1, A2, A3)>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const U *obj, R(T::*method)(A0, A1, A2, A3) const)
- {
- generate(method_context<const T, R(T::*)(A0, A1, A2, A3) const>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3) volatile)
- {
- generate(method_context<volatile T, R(T::*)(A0, A1, A2, A3) volatile>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3) const volatile)
- {
- generate(method_context<const volatile T, R(T::*)(A0, A1, A2, A3) const volatile>(obj, method));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(T *, A0, A1, A2, A3), U *arg)
- {
- generate(function_context<R(*)(T *, A0, A1, A2, A3), T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const T *, A0, A1, A2, A3), const U *arg)
- {
- generate(function_context<R(*)(const T *, A0, A1, A2, A3), const T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(volatile T *, A0, A1, A2, A3), volatile U *arg)
- {
- generate(function_context<R(*)(volatile T *, A0, A1, A2, A3), volatile T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const volatile T *, A0, A1, A2, A3), const volatile U *arg)
- {
- generate(function_context<R(*)(const volatile T *, A0, A1, A2, A3), const volatile T>(func, arg));
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3)))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(U *obj, R(*func)(T *, A0, A1, A2, A3))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3))
- {
- new (this) Callback(func, obj);
- }
-
- /** Destroy a callback
- */
- ~Callback()
- {
- if (_ops) {
- _ops->dtor(this);
- }
- }
-
- /** Attach a static function
- * @param func Static function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(A0, A1, A2, A3))
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const Callback<R(A0, A1, A2, A3)> &func)
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(U *obj, R(T::*method)(A0, A1, A2, A3))
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const U *obj, R(T::*method)(A0, A1, A2, A3) const)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile U *obj, R(T::*method)(A0, A1, A2, A3) volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile U *obj, R(T::*method)(A0, A1, A2, A3) const volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(T *, A0, A1, A2, A3), U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const T *, A0, A1, A2, A3), const U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(volatile T *, A0, A1, A2, A3), volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const volatile T *, A0, A1, A2, A3), const volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3)))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3) const volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(U *obj, R(*func)(T *, A0, A1, A2, A3))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const U *obj, R(*func)(const T *, A0, A1, A2, A3))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Assign a callback
- */
- Callback &operator=(const Callback &that)
- {
- if (this != &that) {
- this->~Callback();
- new (this) Callback(that);
- }
-
- return *this;
- }
-
- /** Call the attached function
- */
- R call(A0 a0, A1 a1, A2 a2, A3 a3) const
- {
- MBED_ASSERT(_ops);
- return _ops->call(this, a0, a1, a2, a3);
- }
-
- /** Call the attached function
- */
- R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const
- {
- return call(a0, a1, a2, a3);
- }
-
- /** Test if function has been attached
- */
- operator bool() const
- {
- return _ops;
- }
-
- /** Test for equality
- */
- friend bool operator==(const Callback &l, const Callback &r)
- {
- return memcmp(&l, &r, sizeof(Callback)) == 0;
- }
-
- /** Test for inequality
- */
- friend bool operator!=(const Callback &l, const Callback &r)
- {
- return !(l == r);
- }
-
- /** Static thunk for passing as C-style function
- * @param func Callback to call passed as void pointer
- * @param a0 An argument to be called with function func
- * @param a1 An argument to be called with function func
- * @param a2 An argument to be called with function func
- * @param a3 An argument to be called with function func
- * @return the value as determined by func which is of
- * type and determined by the signature of func
- */
- static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3)
- {
- return static_cast<Callback *>(func)->call(a0, a1, a2, a3);
- }
-
-private:
- // Stored as pointer to function and pointer to optional object
- // Function pointer is stored as union of possible function types
- // to guarantee proper size and alignment
- struct _class;
- union {
- void (*_staticfunc)(A0, A1, A2, A3);
- void (*_boundfunc)(_class *, A0, A1, A2, A3);
- void (_class::*_methodfunc)(A0, A1, A2, A3);
- } _func;
- void *_obj;
-
- // Dynamically dispatched operations
- const struct ops {
- R(*call)(const void *, A0, A1, A2, A3);
- void (*move)(void *, const void *);
- void (*dtor)(void *);
- } *_ops;
-
- // Generate operations for function object
- template <typename F>
- void generate(const F &f)
- {
- static const ops ops = {
- &Callback::function_call<F>,
- &Callback::function_move<F>,
- &Callback::function_dtor<F>,
- };
-
- MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
- "Type F must not exceed the size of the Callback class");
- memset(this, 0, sizeof(Callback));
- new (this) F(f);
- _ops = &ops;
- }
-
- // Function attributes
- template <typename F>
- static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3)
- {
- return (*(F *)p)(a0, a1, a2, a3);
- }
-
- template <typename F>
- static void function_move(void *d, const void *p)
- {
- new (d) F(*(F *)p);
- }
-
- template <typename F>
- static void function_dtor(void *p)
- {
- ((F *)p)->~F();
- }
-
- // Wrappers for functions with context
- template <typename O, typename M>
- struct method_context {
- M method;
- O *obj;
-
- method_context(O *obj, M method)
- : method(method), obj(obj) {}
-
- R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const
- {
- return (obj->*method)(a0, a1, a2, a3);
- }
- };
-
- template <typename F, typename A>
- struct function_context {
- F func;
- A *arg;
-
- function_context(F func, A *arg)
- : func(func), arg(arg) {}
-
- R operator()(A0 a0, A1 a1, A2 a2, A3 a3) const
- {
- return func(arg, a0, a1, a2, a3);
- }
- };
-};
-
-/** Callback class based on template specialization
- *
- * @note Synchronization level: Not protected
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-class Callback<R(A0, A1, A2, A3, A4)> {
-public:
- /** Create a Callback with a static function
- * @param func Static function to attach
- */
- Callback(R(*func)(A0, A1, A2, A3, A4) = 0)
- {
- if (!func) {
- memset(this, 0, sizeof(Callback));
- } else {
- generate(func);
- }
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- */
- Callback(const Callback<R(A0, A1, A2, A3, A4)> &func)
- {
- if (func._ops) {
- func._ops->move(this, &func);
- }
- _ops = func._ops;
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(U *obj, R(T::*method)(A0, A1, A2, A3, A4))
- {
- generate(method_context<T, R(T::*)(A0, A1, A2, A3, A4)>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const U *obj, R(T::*method)(A0, A1, A2, A3, A4) const)
- {
- generate(method_context<const T, R(T::*)(A0, A1, A2, A3, A4) const>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) volatile)
- {
- generate(method_context<volatile T, R(T::*)(A0, A1, A2, A3, A4) volatile>(obj, method));
- }
-
- /** Create a Callback with a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- */
- template<typename T, typename U>
- Callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) const volatile)
- {
- generate(method_context<const volatile T, R(T::*)(A0, A1, A2, A3, A4) const volatile>(obj, method));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(T *, A0, A1, A2, A3, A4), U *arg)
- {
- generate(function_context<R(*)(T *, A0, A1, A2, A3, A4), T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const T *, A0, A1, A2, A3, A4), const U *arg)
- {
- generate(function_context<R(*)(const T *, A0, A1, A2, A3, A4), const T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(volatile T *, A0, A1, A2, A3, A4), volatile U *arg)
- {
- generate(function_context<R(*)(volatile T *, A0, A1, A2, A3, A4), volatile T>(func, arg));
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- */
- template<typename T, typename U>
- Callback(R(*func)(const volatile T *, A0, A1, A2, A3, A4), const volatile U *arg)
- {
- generate(function_context<R(*)(const volatile T *, A0, A1, A2, A3, A4), const volatile T>(func, arg));
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4)))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- */
- template <typename F>
- Callback(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const volatile))
- {
- generate(f);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(U *obj, R(*func)(T *, A0, A1, A2, A3, A4))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3, A4))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3, A4))
- {
- new (this) Callback(func, obj);
- }
-
- /** Create a Callback with a static function and bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to Callback(func, arg)
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to Callback(func, arg)")
- Callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3, A4))
- {
- new (this) Callback(func, obj);
- }
-
- /** Destroy a callback
- */
- ~Callback()
- {
- if (_ops) {
- _ops->dtor(this);
- }
- }
-
- /** Attach a static function
- * @param func Static function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(A0, A1, A2, A3, A4))
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a Callback
- * @param func The Callback to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const Callback<R(A0, A1, A2, A3, A4)> &func)
- {
- this->~Callback();
- new (this) Callback(func);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(U *obj, R(T::*method)(A0, A1, A2, A3, A4))
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const U *obj, R(T::*method)(A0, A1, A2, A3, A4) const)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a member function
- * @param obj Pointer to object to invoke member function on
- * @param method Member function to attach
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template<typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) const volatile)
- {
- this->~Callback();
- new (this) Callback(obj, method);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(T *, A0, A1, A2, A3, A4), U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const T *, A0, A1, A2, A3, A4), const U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(volatile T *, A0, A1, A2, A3, A4), volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a static function with a bound pointer
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(R(*func)(const volatile T *, A0, A1, A2, A3, A4), const volatile U *arg)
- {
- this->~Callback();
- new (this) Callback(func, arg);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4)))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a function object
- * @param f Function object to attach
- * @note The function object is limited to a single word of storage
- * @deprecated
- * Replaced by simple assignment 'Callback cb = func'
- */
- template <typename F>
- MBED_DEPRECATED_SINCE("mbed-os-5.4",
- "Replaced by simple assignment 'Callback cb = func")
- void attach(const volatile F f, MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, R(F::*)(A0, A1, A2, A3, A4) const volatile))
- {
- this->~Callback();
- new (this) Callback(f);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(U *obj, R(*func)(T *, A0, A1, A2, A3, A4))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const U *obj, R(*func)(const T *, A0, A1, A2, A3, A4))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3, A4))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Attach a static function with a bound pointer
- * @param obj Pointer to object to bind to function
- * @param func Static function to attach
- * @deprecated
- * Arguments to callback have been reordered to attach(func, arg)
- */
- template <typename T, typename U>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to attach(func, arg)")
- void attach(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3, A4))
- {
- this->~Callback();
- new (this) Callback(func, obj);
- }
-
- /** Assign a callback
- */
- Callback &operator=(const Callback &that)
- {
- if (this != &that) {
- this->~Callback();
- new (this) Callback(that);
- }
-
- return *this;
- }
-
- /** Call the attached function
- */
- R call(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
- {
- MBED_ASSERT(_ops);
- return _ops->call(this, a0, a1, a2, a3, a4);
- }
-
- /** Call the attached function
- */
- R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
- {
- return call(a0, a1, a2, a3, a4);
- }
-
- /** Test if function has been attached
- */
- operator bool() const
- {
- return _ops;
- }
-
- /** Test for equality
- */
- friend bool operator==(const Callback &l, const Callback &r)
- {
- return memcmp(&l, &r, sizeof(Callback)) == 0;
- }
-
- /** Test for inequality
- */
- friend bool operator!=(const Callback &l, const Callback &r)
- {
- return !(l == r);
- }
-
- /** Static thunk for passing as C-style function
- * @param func Callback to call passed as void pointer
- * @param a0 An argument to be called with function func
- * @param a1 An argument to be called with function func
- * @param a2 An argument to be called with function func
- * @param a3 An argument to be called with function func
- * @param a4 An argument to be called with function func
- * @return the value as determined by func which is of
- * type and determined by the signature of func
- */
- static R thunk(void *func, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4)
- {
- return static_cast<Callback *>(func)->call(a0, a1, a2, a3, a4);
- }
-
-private:
- // Stored as pointer to function and pointer to optional object
- // Function pointer is stored as union of possible function types
- // to guarantee proper size and alignment
- struct _class;
- union {
- void (*_staticfunc)(A0, A1, A2, A3, A4);
- void (*_boundfunc)(_class *, A0, A1, A2, A3, A4);
- void (_class::*_methodfunc)(A0, A1, A2, A3, A4);
- } _func;
- void *_obj;
-
- // Dynamically dispatched operations
- const struct ops {
- R(*call)(const void *, A0, A1, A2, A3, A4);
- void (*move)(void *, const void *);
- void (*dtor)(void *);
- } *_ops;
-
- // Generate operations for function object
- template <typename F>
- void generate(const F &f)
- {
- static const ops ops = {
- &Callback::function_call<F>,
- &Callback::function_move<F>,
- &Callback::function_dtor<F>,
- };
-
- MBED_STATIC_ASSERT(sizeof(Callback) - sizeof(_ops) >= sizeof(F),
- "Type F must not exceed the size of the Callback class");
- memset(this, 0, sizeof(Callback));
- new (this) F(f);
- _ops = &ops;
- }
-
- // Function attributes
- template <typename F>
- static R function_call(const void *p, A0 a0, A1 a1, A2 a2, A3 a3, A4 a4)
- {
- return (*(F *)p)(a0, a1, a2, a3, a4);
- }
-
- template <typename F>
- static void function_move(void *d, const void *p)
- {
- new (d) F(*(F *)p);
- }
-
- template <typename F>
- static void function_dtor(void *p)
- {
- ((F *)p)->~F();
- }
-
- // Wrappers for functions with context
- template <typename O, typename M>
- struct method_context {
- M method;
- O *obj;
-
- method_context(O *obj, M method)
- : method(method), obj(obj) {}
-
- R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
- {
- return (obj->*method)(a0, a1, a2, a3, a4);
- }
- };
-
- template <typename F, typename A>
- struct function_context {
- F func;
- A *arg;
-
- function_context(F func, A *arg)
- : func(func), arg(arg) {}
-
- R operator()(A0 a0, A1 a1, A2 a2, A3 a3, A4 a4) const
- {
- return func(arg, a0, a1, a2, a3, a4);
- }
- };
-};
-
-// Internally used event type
-typedef Callback<void(int)> event_callback_t;
-
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R>
-Callback<R()> callback(R(*func)() = 0)
-{
- return Callback<R()>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R>
-Callback<R()> callback(const Callback<R()> &func)
-{
- return Callback<R()>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R>
-Callback<R()> callback(U *obj, R(T::*method)())
-{
- return Callback<R()>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R>
-Callback<R()> callback(const U *obj, R(T::*method)() const)
-{
- return Callback<R()>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R>
-Callback<R()> callback(volatile U *obj, R(T::*method)() volatile)
-{
- return Callback<R()>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R>
-Callback<R()> callback(const volatile U *obj, R(T::*method)() const volatile)
-{
- return Callback<R()>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R>
-Callback<R()> callback(R(*func)(T *), U *arg)
-{
- return Callback<R()>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R>
-Callback<R()> callback(R(*func)(const T *), const U *arg)
-{
- return Callback<R()>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R>
-Callback<R()> callback(R(*func)(volatile T *), volatile U *arg)
-{
- return Callback<R()>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R>
-Callback<R()> callback(R(*func)(const volatile T *), const volatile U *arg)
-{
- return Callback<R()>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R()> callback(U *obj, R(*func)(T *))
-{
- return Callback<R()>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R()> callback(const U *obj, R(*func)(const T *))
-{
- return Callback<R()>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R()> callback(volatile U *obj, R(*func)(volatile T *))
-{
- return Callback<R()>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R()> callback(const volatile U *obj, R(*func)(const volatile T *))
-{
- return Callback<R()>(func, obj);
-}
-
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0>
-Callback<R(A0)> callback(R(*func)(A0) = 0)
-{
- return Callback<R(A0)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0>
-Callback<R(A0)> callback(const Callback<R(A0)> &func)
-{
- return Callback<R(A0)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(U *obj, R(T::*method)(A0))
-{
- return Callback<R(A0)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(const U *obj, R(T::*method)(A0) const)
-{
- return Callback<R(A0)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(volatile U *obj, R(T::*method)(A0) volatile)
-{
- return Callback<R(A0)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(const volatile U *obj, R(T::*method)(A0) const volatile)
-{
- return Callback<R(A0)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(R(*func)(T *, A0), U *arg)
-{
- return Callback<R(A0)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(R(*func)(const T *, A0), const U *arg)
-{
- return Callback<R(A0)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(R(*func)(volatile T *, A0), volatile U *arg)
-{
- return Callback<R(A0)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0>
-Callback<R(A0)> callback(R(*func)(const volatile T *, A0), const volatile U *arg)
-{
- return Callback<R(A0)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0)> callback(U *obj, R(*func)(T *, A0))
-{
- return Callback<R(A0)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0)> callback(const U *obj, R(*func)(const T *, A0))
-{
- return Callback<R(A0)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0)> callback(volatile U *obj, R(*func)(volatile T *, A0))
-{
- return Callback<R(A0)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0)> callback(const volatile U *obj, R(*func)(const volatile T *, A0))
-{
- return Callback<R(A0)>(func, obj);
-}
-
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(R(*func)(A0, A1) = 0)
-{
- return Callback<R(A0, A1)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(const Callback<R(A0, A1)> &func)
-{
- return Callback<R(A0, A1)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(U *obj, R(T::*method)(A0, A1))
-{
- return Callback<R(A0, A1)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(const U *obj, R(T::*method)(A0, A1) const)
-{
- return Callback<R(A0, A1)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(volatile U *obj, R(T::*method)(A0, A1) volatile)
-{
- return Callback<R(A0, A1)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(const volatile U *obj, R(T::*method)(A0, A1) const volatile)
-{
- return Callback<R(A0, A1)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(R(*func)(T *, A0, A1), U *arg)
-{
- return Callback<R(A0, A1)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(R(*func)(const T *, A0, A1), const U *arg)
-{
- return Callback<R(A0, A1)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(R(*func)(volatile T *, A0, A1), volatile U *arg)
-{
- return Callback<R(A0, A1)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-Callback<R(A0, A1)> callback(R(*func)(const volatile T *, A0, A1), const volatile U *arg)
-{
- return Callback<R(A0, A1)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1)> callback(U *obj, R(*func)(T *, A0, A1))
-{
- return Callback<R(A0, A1)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1)> callback(const U *obj, R(*func)(const T *, A0, A1))
-{
- return Callback<R(A0, A1)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1))
-{
- return Callback<R(A0, A1)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1))
-{
- return Callback<R(A0, A1)>(func, obj);
-}
-
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(R(*func)(A0, A1, A2) = 0)
-{
- return Callback<R(A0, A1, A2)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(const Callback<R(A0, A1, A2)> &func)
-{
- return Callback<R(A0, A1, A2)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(U *obj, R(T::*method)(A0, A1, A2))
-{
- return Callback<R(A0, A1, A2)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(const U *obj, R(T::*method)(A0, A1, A2) const)
-{
- return Callback<R(A0, A1, A2)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(volatile U *obj, R(T::*method)(A0, A1, A2) volatile)
-{
- return Callback<R(A0, A1, A2)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2) const volatile)
-{
- return Callback<R(A0, A1, A2)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(R(*func)(T *, A0, A1, A2), U *arg)
-{
- return Callback<R(A0, A1, A2)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(R(*func)(const T *, A0, A1, A2), const U *arg)
-{
- return Callback<R(A0, A1, A2)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(R(*func)(volatile T *, A0, A1, A2), volatile U *arg)
-{
- return Callback<R(A0, A1, A2)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-Callback<R(A0, A1, A2)> callback(R(*func)(const volatile T *, A0, A1, A2), const volatile U *arg)
-{
- return Callback<R(A0, A1, A2)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2)> callback(U *obj, R(*func)(T *, A0, A1, A2))
-{
- return Callback<R(A0, A1, A2)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2)> callback(const U *obj, R(*func)(const T *, A0, A1, A2))
-{
- return Callback<R(A0, A1, A2)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2))
-{
- return Callback<R(A0, A1, A2)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2))
-{
- return Callback<R(A0, A1, A2)>(func, obj);
-}
-
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(R(*func)(A0, A1, A2, A3) = 0)
-{
- return Callback<R(A0, A1, A2, A3)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(const Callback<R(A0, A1, A2, A3)> &func)
-{
- return Callback<R(A0, A1, A2, A3)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(U *obj, R(T::*method)(A0, A1, A2, A3))
-{
- return Callback<R(A0, A1, A2, A3)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(const U *obj, R(T::*method)(A0, A1, A2, A3) const)
-{
- return Callback<R(A0, A1, A2, A3)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3) volatile)
-{
- return Callback<R(A0, A1, A2, A3)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3) const volatile)
-{
- return Callback<R(A0, A1, A2, A3)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(R(*func)(T *, A0, A1, A2, A3), U *arg)
-{
- return Callback<R(A0, A1, A2, A3)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(R(*func)(const T *, A0, A1, A2, A3), const U *arg)
-{
- return Callback<R(A0, A1, A2, A3)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(R(*func)(volatile T *, A0, A1, A2, A3), volatile U *arg)
-{
- return Callback<R(A0, A1, A2, A3)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-Callback<R(A0, A1, A2, A3)> callback(R(*func)(const volatile T *, A0, A1, A2, A3), const volatile U *arg)
-{
- return Callback<R(A0, A1, A2, A3)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3)> callback(U *obj, R(*func)(T *, A0, A1, A2, A3))
-{
- return Callback<R(A0, A1, A2, A3)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3)> callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3))
-{
- return Callback<R(A0, A1, A2, A3)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3))
-{
- return Callback<R(A0, A1, A2, A3)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3))
-{
- return Callback<R(A0, A1, A2, A3)>(func, obj);
-}
-
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(A0, A1, A2, A3, A4) = 0)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @return Callback with inferred type
- */
-template <typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(const Callback<R(A0, A1, A2, A3, A4)> &func)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R(T::*method)(A0, A1, A2, A3, A4))
-{
- return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R(T::*method)(A0, A1, A2, A3, A4) const)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) volatile)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param method Member function to attach
- * @return Callback with inferred type
- */
-template<typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R(T::*method)(A0, A1, A2, A3, A4) const volatile)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(obj, method);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(T *, A0, A1, A2, A3, A4), U *arg)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(const T *, A0, A1, A2, A3, A4), const U *arg)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(volatile T *, A0, A1, A2, A3, A4), volatile U *arg)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param func Static function to attach
- * @param arg Pointer argument to function
- * @return Callback with inferred type
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-Callback<R(A0, A1, A2, A3, A4)> callback(R(*func)(const volatile T *, A0, A1, A2, A3, A4), const volatile U *arg)
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, arg);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3, A4)> callback(U *obj, R(*func)(T *, A0, A1, A2, A3, A4))
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3, A4)> callback(const U *obj, R(*func)(const T *, A0, A1, A2, A3, A4))
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3, A4)> callback(volatile U *obj, R(*func)(volatile T *, A0, A1, A2, A3, A4))
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
-}
-
-/** Create a callback class with type inferred from the arguments
- *
- * @param obj Optional pointer to object to bind to function
- * @param func Static function to attach
- * @return Callback with inferred type
- * @deprecated
- * Arguments to callback have been reordered to callback(func, arg)
- */
-template <typename T, typename U, typename R, typename A0, typename A1, typename A2, typename A3, typename A4>
-MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "Arguments to callback have been reordered to callback(func, arg)")
-Callback<R(A0, A1, A2, A3, A4)> callback(const volatile U *obj, R(*func)(const volatile T *, A0, A1, A2, A3, A4))
-{
- return Callback<R(A0, A1, A2, A3, A4)>(func, obj);
-}
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/CircularBuffer.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,215 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CIRCULARBUFFER_H
-#define MBED_CIRCULARBUFFER_H
-
-#include "platform/mbed_critical.h"
-#include "platform/mbed_assert.h"
-
-namespace mbed {
-
-namespace internal {
-/* Detect if CounterType of the Circular buffer is of unsigned type. */
-template<typename T>
-struct is_unsigned {
- static const bool value = false;
-};
-template<>
-struct is_unsigned<unsigned char> {
- static const bool value = true;
-};
-template<>
-struct is_unsigned<unsigned short> {
- static const bool value = true;
-};
-template<>
-struct is_unsigned<unsigned int> {
- static const bool value = true;
-};
-template<>
-struct is_unsigned<unsigned long> {
- static const bool value = true;
-};
-template<>
-struct is_unsigned<unsigned long long> {
- static const bool value = true;
-};
-};
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_CircularBuffer CircularBuffer functions
- * @{
- */
-
-/** Templated Circular buffer class
- *
- * @note Synchronization level: Interrupt safe
- * @note CounterType must be unsigned and consistent with BufferSize
- */
-template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
-class CircularBuffer {
-public:
- CircularBuffer() : _head(0), _tail(0), _full(false)
- {
- MBED_STATIC_ASSERT(
- internal::is_unsigned<CounterType>::value,
- "CounterType must be unsigned"
- );
-
- MBED_STATIC_ASSERT(
- (sizeof(CounterType) >= sizeof(uint32_t)) ||
- (BufferSize < (((uint64_t) 1) << (sizeof(CounterType) * 8))),
- "Invalid BufferSize for the CounterType"
- );
- }
-
- ~CircularBuffer()
- {
- }
-
- /** Push the transaction to the buffer. This overwrites the buffer if it's
- * full
- *
- * @param data Data to be pushed to the buffer
- */
- void push(const T &data)
- {
- core_util_critical_section_enter();
- if (full()) {
- _tail++;
- if (_tail == BufferSize) {
- _tail = 0;
- }
- }
- _pool[_head++] = data;
- if (_head == BufferSize) {
- _head = 0;
- }
- if (_head == _tail) {
- _full = true;
- }
- core_util_critical_section_exit();
- }
-
- /** Pop the transaction from the buffer
- *
- * @param data Data to be popped from the buffer
- * @return True if the buffer is not empty and data contains a transaction, false otherwise
- */
- bool pop(T &data)
- {
- bool data_popped = false;
- core_util_critical_section_enter();
- if (!empty()) {
- data = _pool[_tail++];
- if (_tail == BufferSize) {
- _tail = 0;
- }
- _full = false;
- data_popped = true;
- }
- core_util_critical_section_exit();
- return data_popped;
- }
-
- /** Check if the buffer is empty
- *
- * @return True if the buffer is empty, false if not
- */
- bool empty() const
- {
- core_util_critical_section_enter();
- bool is_empty = (_head == _tail) && !_full;
- core_util_critical_section_exit();
- return is_empty;
- }
-
- /** Check if the buffer is full
- *
- * @return True if the buffer is full, false if not
- */
- bool full() const
- {
- core_util_critical_section_enter();
- bool full = _full;
- core_util_critical_section_exit();
- return full;
- }
-
- /** Reset the buffer
- *
- */
- void reset()
- {
- core_util_critical_section_enter();
- _head = 0;
- _tail = 0;
- _full = false;
- core_util_critical_section_exit();
- }
-
- /** Get the number of elements currently stored in the circular_buffer */
- CounterType size() const
- {
- core_util_critical_section_enter();
- CounterType elements;
- if (!_full) {
- if (_head < _tail) {
- elements = BufferSize + _head - _tail;
- } else {
- elements = _head - _tail;
- }
- } else {
- elements = BufferSize;
- }
- core_util_critical_section_exit();
- return elements;
- }
-
- /** Peek into circular buffer without popping
- *
- * @param data Data to be peeked from the buffer
- * @return True if the buffer is not empty and data contains a transaction, false otherwise
- */
- bool peek(T &data) const
- {
- bool data_updated = false;
- core_util_critical_section_enter();
- if (!empty()) {
- data = _pool[_tail];
- data_updated = true;
- }
- core_util_critical_section_exit();
- return data_updated;
- }
-
-private:
- T _pool[BufferSize];
- CounterType _head;
- CounterType _tail;
- bool _full;
-};
-
-/**@}*/
-
-/**@}*/
-
-}
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/CriticalSectionLock.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_CRITICALSECTIONLOCK_H
-#define MBED_CRITICALSECTIONLOCK_H
-
-#include "platform/mbed_critical.h"
-#include "platform/mbed_toolchain.h"
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_CriticalSectionLock CriticalSectionLock functions
- * @{
- */
-
-/** RAII object for disabling, then restoring, interrupt state
- * Usage:
- * @code
- *
- * // RAII style usage
- * unsigned int atomic_counter_increment(unsigned int &counter) {
- * CriticalSectionLock lock;
- * // Code in this block will run with interrupts disabled
- * // Interrupts will be restored to their previous state automatically
- * // at the end of function scope
- * return ++counter;
- * }
- *
- * // free locking usage
- * unsigned int atomic_counter_decrement(unsigned int &counter) {
- * CriticalSectionLock::enable();
- * // Code in this block will run with interrupts disabled
- * counter--;
- * CriticalSectionLock::disable(); // need explicitly to disable critical section lock
- * // interrupts will be restored to their previous state here
- * return counter;
- * }
- *
- * @endcode
- */
-class CriticalSectionLock {
-public:
- CriticalSectionLock()
- {
- core_util_critical_section_enter();
- }
-
- ~CriticalSectionLock()
- {
- core_util_critical_section_exit();
- }
-
- /** Mark the start of a critical section
- * @deprecated This function is inconsistent with RAII and is being removed in the future. Replaced by static function CriticalSectionLock::enable.
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.8",
- "This function is inconsistent with RAII and is being removed in the future."
- "Replaced by static function CriticalSectionLock::enable.")
- void lock()
- {
- core_util_critical_section_enter();
- }
-
- /** Mark the end of a critical section
- * @deprecated This function is inconsistent with RAII and is being removed in the future. Replaced by static function CriticalSectionLock::enable.
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.8",
- "This function is inconsistent with RAII and is being removed in the future."
- "Replaced by static function CriticalSectionLock::disable.")
- void unlock()
- {
- core_util_critical_section_exit();
- }
-
- /** Mark the start of a critical section
- */
- static void enable()
- {
- core_util_critical_section_enter();
- }
-
- /** Mark the end of a critical section
- */
- static void disable()
- {
- core_util_critical_section_exit();
- }
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/DeepSleepLock.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,99 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEEPSLEEPLOCK_H
-#define MBED_DEEPSLEEPLOCK_H
-
-#include <limits.h>
-#include "platform/mbed_power_mgmt.h"
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_DeepSleepLock DeepSleepLock functions
- * @{
- */
-
-/** RAII object for disabling, then restoring the deep sleep mode
- * Usage:
- * @code
- *
- * void f() {
- * // some code here
- * {
- * DeepSleepLock lock;
- * // Code in this block will run with the deep sleep mode locked
- * }
- * // deep sleep mode will be restored to their previous state
- * }
- * @endcode
- */
-class DeepSleepLock {
-private:
- uint16_t _lock_count;
-
-public:
- DeepSleepLock(): _lock_count(1)
- {
- sleep_manager_lock_deep_sleep();
- }
-
- ~DeepSleepLock()
- {
- if (_lock_count) {
- sleep_manager_unlock_deep_sleep();
- }
- }
-
- /** Mark the start of a locked deep sleep section
- */
- void lock()
- {
- uint16_t count = core_util_atomic_incr_u16(&_lock_count, 1);
- if (1 == count) {
- sleep_manager_lock_deep_sleep();
- }
- if (0 == count) {
- MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_OVERFLOW), "DeepSleepLock overflow (> USHRT_MAX)", count);
- }
- }
-
- /** Mark the end of a locked deep sleep section
- */
- void unlock()
- {
- uint16_t count = core_util_atomic_decr_u16(&_lock_count, 1);
- if (count == 0) {
- sleep_manager_unlock_deep_sleep();
- }
- if (count == USHRT_MAX) {
- core_util_critical_section_exit();
- MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_PLATFORM, MBED_ERROR_CODE_UNDERFLOW), "DeepSleepLock underflow (< 0)", count);
- }
- }
-};
-
-/**@}*/
-
-/**@}*/
-
-
-}
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/DirHandle.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,178 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIRHANDLE_H
-#define MBED_DIRHANDLE_H
-
-#include <stdint.h>
-#include "platform/platform.h"
-#include "platform/FileHandle.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_DirHandle DirHandle functions
- * @{
- */
-
-
-/** Represents a directory stream. An opendir function returns
- * objects of this type. The core functions are read and seek,
- * but only a subset needs to be provided.
- *
- * If a FileSystemLike class defines the opendir method, then you
- * can access the directories of an object of that type by either:
- * @code
- * DIR *d = opendir("/example/directory");
- * @endcode
- * or
- * @code
- * DIR *d = opendir("/example");
- * @endcode
- * to open the root of the file system.
- *
- * The root directory is considered to contain all FileHandle and
- * FileSystem objects, so the DIR pointer returned by opendir("/")
- * reflects this.
- *
- * @note to create a directory, @see Dir
- * @note Synchronization level: Set by subclass
- */
-class DirHandle : private NonCopyable<DirHandle> {
-public:
- virtual ~DirHandle() {}
-
- /** Read the next directory entry
- *
- * @param ent The directory entry to fill out
- * @return 1 on reading a filename, 0 at end of directory, negative error on failure
- */
- virtual ssize_t read(struct dirent *ent) = 0;
-
- /** Close a directory
- *
- * @return 0 on success, negative error code on failure
- */
- virtual int close() = 0;
-
- /** Set the current position of the directory
- *
- * @param offset Offset of the location to seek to,
- * must be a value returned from tell
- */
- virtual void seek(off_t offset) = 0;
-
- /** Get the current position of the directory
- *
- * @return Position of the directory that can be passed to rewind
- */
- virtual off_t tell() = 0;
-
- /** Rewind the current position to the beginning of the directory
- */
- virtual void rewind() = 0;
-
- /** Get the sizeof the directory
- *
- * @return Number of files in the directory
- */
- virtual size_t size()
- {
- off_t off = tell();
- size_t size = 0;
- struct dirent *ent = new struct dirent;
-
- rewind();
- while (read(ent) > 0) {
- size += 1;
- }
- seek(off);
-
- delete ent;
- return size;
- }
-
- /** Closes the directory.
- *
- * @returns
- * 0 on success,
- * -1 on error.
- * @deprecated Replaced by `int DirHandle::close()'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::close")
- virtual int closedir()
- {
- return close();
- };
-
- /** Returns the directory entry at the current position, and
- * advances the position to the next entry.
- *
- * @returns
- * A pointer to a dirent structure representing the
- * directory entry at the current position, or NULL on reaching
- * end of directory or error.
- * @deprecated Replaced by `ssize_t DirHandle::read(struct dirent *ent)
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::read")
- virtual struct dirent *readdir()
- {
- static struct dirent ent;
- return (read(&ent) > 0) ? &ent : NULL;
- }
-
- /** Resets the position to the beginning of the directory.
- * @deprecated Replaced by `void DirHandle::rewind()'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::rewind")
- virtual void rewinddir()
- {
- rewind();
- }
-
- /** Returns the current position of the DirHandle.
- *
- * @returns
- * the current position,
- * -1 on error.
- * @deprecated Replaced by `off_t DirHandle::tell()'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::tell")
- virtual off_t telldir()
- {
- return tell();
- }
-
- /** Sets the position of the DirHandle.
- *
- * @param location The location to seek to. Must be a value returned by telldir.
- * @deprecated Replaced by `void DirHandle::seek(off_t offset)'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by DirHandle::seek")
- virtual void seekdir(off_t location)
- {
- seek(location);
- }
-};
-
-/**@}*/
-
-/**@}*/
-} // namespace mbed
-
-#endif /* MBED_DIRHANDLE_H */
--- a/STM32F103C8T6_MPA/mbed/platform/FileBase.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEBASE_H
-#define MBED_FILEBASE_H
-
-typedef int FILEHANDLE;
-
-#include "platform/platform.h"
-#include "platform/SingletonPtr.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-
-typedef enum {
- FilePathType,
- FileSystemPathType
-} PathType;
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_FileBase FileBase class
- * @{
- */
-/** Class FileBase
- *
- */
-
-class FileBase : private NonCopyable<FileBase> {
-public:
- FileBase(const char *name, PathType t);
- virtual ~FileBase();
-
- const char *getName(void);
- PathType getPathType(void);
-
- static FileBase *lookup(const char *name, unsigned int len);
-
- static FileBase *get(int n);
-
- void set_as_default();
-
-private:
- static FileBase *_head;
- static FileBase *_default;
- static SingletonPtr<PlatformMutex> _mutex;
-
- FileBase *_next;
- const char *const _name;
- const PathType _path_type;
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/platform/FileHandle.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,276 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEHANDLE_H
-#define MBED_FILEHANDLE_H
-
-typedef int FILEHANDLE;
-
-#include <cstdio>
-#include "Callback.h"
-#include "platform/mbed_poll.h"
-#include "platform/platform.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_FileHandle FileHandle functions
- * @{
- */
-
-
-/** Class FileHandle
- *
- * An abstract interface that represents operations on a file-like
- * object. The core functions are read, write and seek, but only
- * a subset of these operations can be provided.
- *
- * @note to create a file, @see File
- * @note Synchronization level: Set by subclass
- */
-class FileHandle : private NonCopyable<FileHandle> {
-public:
- virtual ~FileHandle() {}
-
- /** Read the contents of a file into a buffer
- *
- * Devices acting as FileHandles should follow POSIX semantics:
- *
- * * if no data is available, and nonblocking set, return -EAGAIN
- * * if no data is available, and blocking set, wait until some data is available
- * * If any data is available, call returns immediately
- *
- * @param buffer The buffer to read in to
- * @param size The number of bytes to read
- * @return The number of bytes read, 0 at end of file, negative error on failure
- */
- virtual ssize_t read(void *buffer, size_t size) = 0;
-
- /** Write the contents of a buffer to a file
- *
- * Devices acting as FileHandles should follow POSIX semantics:
- *
- * * if blocking, block until all data is written
- * * if no data can be written, and nonblocking set, return -EAGAIN
- * * if some data can be written, and nonblocking set, write partial
- *
- * @param buffer The buffer to write from
- * @param size The number of bytes to write
- * @return The number of bytes written, negative error on failure
- */
- virtual ssize_t write(const void *buffer, size_t size) = 0;
-
- /** Move the file position to a given offset from from a given location
- *
- * @param offset The offset from whence to move to
- * @param whence The start of where to seek
- * SEEK_SET to start from beginning of file,
- * SEEK_CUR to start from current position in file,
- * SEEK_END to start from end of file
- * @return The new offset of the file, negative error code on failure
- */
- virtual off_t seek(off_t offset, int whence = SEEK_SET) = 0;
-
- /** Close a file
- *
- * @return 0 on success, negative error code on failure
- */
- virtual int close() = 0;
-
- /** Flush any buffers associated with the file
- *
- * @return 0 on success, negative error code on failure
- */
- virtual int sync()
- {
- return 0;
- }
-
- /** Check if the file in an interactive terminal device
- *
- * @return True if the file is a terminal
- * @return False if the file is not a terminal
- * @return Negative error code on failure
- */
- virtual int isatty()
- {
- return false;
- }
-
- /** Get the file position of the file
- *
- * @note This is equivalent to seek(0, SEEK_CUR)
- *
- * @return The current offset in the file, negative error code on failure
- */
- virtual off_t tell()
- {
- return seek(0, SEEK_CUR);
- }
-
- /** Rewind the file position to the beginning of the file
- *
- * @note This is equivalent to seek(0, SEEK_SET)
- */
- virtual void rewind()
- {
- seek(0, SEEK_SET);
- }
-
- /** Get the size of the file
- *
- * @return Size of the file in bytes
- */
- virtual off_t size();
-
- /** Move the file position to a given offset from a given location.
- *
- * @param offset The offset from whence to move to
- * @param whence SEEK_SET for the start of the file, SEEK_CUR for the
- * current file position, or SEEK_END for the end of the file.
- *
- * @returns
- * new file position on success,
- * -1 on failure or unsupported
- * @deprecated Replaced by `off_t FileHandle::seek(off_t offset, int whence = SEEK_SET)'
- *
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::seek")
- virtual off_t lseek(off_t offset, int whence)
- {
- return seek(offset, whence);
- }
-
- /** Flush any buffers associated with the FileHandle, ensuring it
- * is up to date on disk
- *
- * @returns
- * 0 on success or un-needed,
- * -1 on error
- * @deprecated Replaced by `int FileHandle::sync()'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::sync")
- virtual int fsync()
- {
- return sync();
- }
-
- /** Find the length of the file
- *
- * @returns
- * Length of the file
- * @deprecated Replaced by `off_t FileHandle::size()'
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.4", "Replaced by FileHandle::size")
- virtual off_t flen()
- {
- return size();
- }
-
- /** Set blocking or nonblocking mode of the file operation like read/write.
- * Definition depends on the subclass implementing FileHandle.
- * The default is blocking.
- *
- * @param blocking true for blocking mode, false for nonblocking mode.
- *
- * @return 0 on success
- * @return Negative error code on failure
- */
- virtual int set_blocking(bool blocking)
- {
- return blocking ? 0 : -ENOTTY;
- }
-
- /** Check current blocking or nonblocking mode for file operations.
- *
- * @return true for blocking mode, false for nonblocking mode.
- */
- virtual bool is_blocking() const
- {
- return true;
- }
-
- /** Check for poll event flags
- * You can use or ignore the input parameter. You can return all events
- * or check just the events listed in events.
- * Call is nonblocking - returns instantaneous state of events.
- * Whenever an event occurs, the derived class should call the sigio() callback).
- *
- * @param events bitmask of poll events we're interested in - POLLIN/POLLOUT etc.
- *
- * @returns bitmask of poll events that have occurred.
- */
- virtual short poll(short events) const
- {
- // Possible default for real files
- return POLLIN | POLLOUT;
- }
-
- /** Definition depends on the subclass implementing FileHandle.
- * For example, if the FileHandle is of type Stream, writable() could return
- * true when there is ample buffer space available for write() calls.
- *
- * @returns true if the FileHandle is writable.
- */
- bool writable() const
- {
- return poll(POLLOUT) & POLLOUT;
- }
-
- /** Definition depends on the subclass implementing FileHandle.
- * For example, if the FileHandle is of type Stream, readable() could return
- * true when there is something available to read.
- *
- * @returns true when there is something available to read.
- */
- bool readable() const
- {
- return poll(POLLIN) & POLLIN;
- }
-
- /** Register a callback on state change of the file.
- *
- * The specified callback will be called on state changes such as when
- * the file can be written to or read from.
- *
- * The callback may be called in an interrupt context and should not
- * perform expensive operations.
- *
- * Note! This is not intended as an attach-like asynchronous API, but rather
- * as a building block for constructing such functionality.
- *
- * The exact timing of when the registered function
- * is called is not guaranteed and is susceptible to change. It should be used
- * as a cue to make read/write/poll calls to find the current state.
- *
- * @param func Function to call on state change
- */
- virtual void sigio(Callback<void()> func)
- {
- //Default for real files. Do nothing for real files.
- }
-};
-
-/**@}*/
-
-/**@}*/
-
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/FileLike.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILELIKE_H
-#define MBED_FILELIKE_H
-
-#include "platform/mbed_toolchain.h"
-#include "platform/FileBase.h"
-#include "platform/FileHandle.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_FileLike FileLike class
- * @{
- */
-/** Class FileLike
- *
- * A file-like object is one that can be opened with fopen by
- * fopen("/name", mode).
- *
- * @note Synchronization level: Set by subclass
- */
-class FileLike : public FileHandle, public FileBase, private NonCopyable<FileLike> {
-public:
- /** Constructor FileLike
- *
- * @param name The name to use to open the file.
- */
- FileLike(const char *name = NULL) : FileBase(name, FilePathType) {}
- virtual ~FileLike() {}
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/FilePath.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEPATH_H
-#define MBED_FILEPATH_H
-
-#include "platform/platform.h"
-
-#include "platform/FileSystemLike.h"
-#include "platform/FileLike.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_FilePath FilePath class
- * @{
- */
-
-class FileSystem;
-/** Class FilePath
- *
- */
-
-class FilePath {
-public:
- /** Constructor FilePath
- *
- * @param file_path The path of file.
- */
- FilePath(const char *file_path);
-
- const char *fileName(void);
-
- bool isFileSystem(void);
- FileSystemLike *fileSystem(void);
-
- bool isFile(void);
- FileLike *file(void);
- bool exists(void);
-
-private:
- const char *file_name;
- FileBase *fb;
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/FileSystemHandle.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILESYSTEMHANDLE_H
-#define MBED_FILESYSTEMHANDLE_H
-
-#include "platform/platform.h"
-
-#include "platform/FileBase.h"
-#include "platform/FileHandle.h"
-#include "platform/DirHandle.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_FileSystemHandle FileSystemHandle functions
- * @{
- */
-
-
-/** A filesystem-like object is one that can be used to open file-like
- * objects though it by fopen("/name/filename", mode)
- *
- * Implementations must define at least open (the default definitions
- * of the rest of the functions just return error values).
- *
- * @note Synchronization level: Set by subclass
- */
-class FileSystemHandle : private NonCopyable<FileSystemHandle> {
-public:
- /** FileSystemHandle lifetime
- */
- virtual ~FileSystemHandle() {}
-
- /** Open a file on the filesystem
- *
- * @param file Destination for the handle to a newly created file
- * @param filename The name of the file to open
- * @param flags The flags to open the file in, one of O_RDONLY, O_WRONLY, O_RDWR,
- * bitwise or'd with one of O_CREAT, O_TRUNC, O_APPEND
- * @return 0 on success, negative error code on failure
- */
- virtual int open(FileHandle **file, const char *filename, int flags) = 0;
-
- /** Open a directory on the filesystem
- *
- * @param dir Destination for the handle to the directory
- * @param path Name of the directory to open
- * @return 0 on success, negative error code on failure
- */
- virtual int open(DirHandle **dir, const char *path);
-
- /** Remove a file from the filesystem.
- *
- * @param path The name of the file to remove.
- * @return 0 on success, negative error code on failure
- */
- virtual int remove(const char *path);
-
- /** Rename a file in the filesystem.
- *
- * @param path The name of the file to rename.
- * @param newpath The name to rename it to
- * @return 0 on success, negative error code on failure
- */
- virtual int rename(const char *path, const char *newpath);
-
- /** Store information about the file in a stat structure
- *
- * @param path The name of the file to find information about
- * @param st The stat buffer to write to
- * @return 0 on success, negative error code on failure
- */
- virtual int stat(const char *path, struct stat *st);
-
- /** Create a directory in the filesystem.
- *
- * @param path The name of the directory to create.
- * @param mode The permissions with which to create the directory
- * @return 0 on success, negative error code on failure
- */
- virtual int mkdir(const char *path, mode_t mode);
-
- /** Store information about the mounted filesystem in a statvfs structure
- *
- * @param path The name of the file to find information about
- * @param buf The stat buffer to write to
- * @return 0 on success, negative error code on failure
- */
- virtual int statvfs(const char *path, struct statvfs *buf);
-};
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/FileSystemLike.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILESYSTEMLIKE_H
-#define MBED_FILESYSTEMLIKE_H
-
-#include "platform/platform.h"
-
-#include "platform/FileSystemHandle.h"
-#include "platform/FileHandle.h"
-#include "platform/DirHandle.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_FileSystemLike FileSystemLike functions
- * @{
- */
-
-
-/** A filesystem-like object is one that can be used to open file-like
- * objects though it by fopen("/name/filename", mode)
- *
- * Implementations must define at least open (the default definitions
- * of the rest of the functions just return error values).
- *
- * @note Synchronization level: Set by subclass
- */
-class FileSystemLike : public FileSystemHandle, public FileBase, private NonCopyable<FileSystemLike> {
-public:
- /** FileSystemLike lifetime
- */
- FileSystemLike(const char *name = NULL) : FileBase(name, FileSystemPathType) {}
- virtual ~FileSystemLike() {}
-
- // Inherited functions with name conflicts
- using FileSystemHandle::open;
-
- /** Open a file on the filesystem
- *
- * @param path The name of the file to open
- * @param flags The flags to open the file in, one of O_RDONLY, O_WRONLY, O_RDWR,
- * bitwise or'd with one of O_CREAT, O_TRUNC, O_APPEND
- * @return A file handle on success, NULL on failure
- * @deprecated Replaced by `int open(FileHandle **, ...)` for propagating error codes
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.5",
- "Replaced by `int open(FileHandle **, ...)` for propagating error codes")
- FileHandle *open(const char *path, int flags)
- {
- FileHandle *file;
- int err = open(&file, path, flags);
- return err ? NULL : file;
- }
-
- /** Open a directory on the filesystem
- *
- * @param path Name of the directory to open
- * @return A directory handle on success, NULL on failure
- * @deprecated Replaced by `int open(DirHandle **, ...)` for propagating error codes
- */
- MBED_DEPRECATED_SINCE("mbed-os-5.5",
- "Replaced by `int open(DirHandle **, ...)` for propagating error codes")
- DirHandle *opendir(const char *path)
- {
- DirHandle *dir;
- int err = open(&dir, path);
- return err ? NULL : dir;
- }
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/FunctionPointer.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,112 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FUNCTIONPOINTER_H
-#define MBED_FUNCTIONPOINTER_H
-
-#include "platform/Callback.h"
-#include "platform/mbed_toolchain.h"
-#include <string.h>
-#include <stdint.h>
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_FunctionPointer FunctionPointer class
- * @{
- */
-
-// Declarations for backwards compatibility
-// To be foward compatible, code should adopt the Callback class
-template <typename R, typename A1>
-class FunctionPointerArg1 : public Callback<R(A1)> {
-public:
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
- FunctionPointerArg1(R(*function)(A1) = 0)
- : Callback<R(A1)>(function) {}
-
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "FunctionPointerArg1<R, A> has been replaced by Callback<R(A)>")
- FunctionPointerArg1(T *object, R(T::*member)(A1))
- : Callback<R(A1)>(object, member) {}
-
- R(*get_function())(A1)
- {
- return *reinterpret_cast<R(* *)(A1)>(this);
- }
-
- R call(A1 a1) const
- {
- if (!Callback<R(A1)>::operator bool()) {
- return (R)0;
- }
-
- return Callback<R(A1)>::call(a1);
- }
-
- R operator()(A1 a1) const
- {
- return Callback<R(A1)>::call(a1);
- }
-};
-
-template <typename R>
-class FunctionPointerArg1<R, void> : public Callback<R()> {
-public:
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "FunctionPointer has been replaced by Callback<void()>")
- FunctionPointerArg1(R(*function)() = 0)
- : Callback<R()>(function) {}
-
- template<typename T>
- MBED_DEPRECATED_SINCE("mbed-os-5.1",
- "FunctionPointer has been replaced by Callback<void()>")
- FunctionPointerArg1(T *object, R(T::*member)())
- : Callback<R()>(object, member) {}
-
- R(*get_function())()
- {
- return *reinterpret_cast<R(* *)()>(this);
- }
-
- R call() const
- {
- if (!Callback<R()>::operator bool()) {
- return (R)0;
- }
-
- return Callback<R()>::call();
- }
-
- R operator()() const
- {
- return Callback<R()>::call();
- }
-};
-
-typedef FunctionPointerArg1<void, void> FunctionPointer;
-
-/**@}*/
-
-/**@}*/
-
-
-} // namespace mbed
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/LocalFileSystem.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,129 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOCALFILESYSTEM_H
-#define MBED_LOCALFILESYSTEM_H
-
-#include "platform/platform.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "platform/FileSystemLike.h"
-#include "platform/PlatformMutex.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_LocalFileSystem LocalFileSystem functions
- * @{
- */
-
-FILEHANDLE local_file_open(const char *name, int flags);
-
-/**
- * @class LocalFileHandle
- * @ingroup platform
- */
-class LocalFileHandle : public FileHandle, private NonCopyable<LocalFileHandle> {
-
-public:
- LocalFileHandle(FILEHANDLE fh);
-
- virtual int close();
-
- virtual ssize_t write(const void *buffer, size_t length);
-
- virtual ssize_t read(void *buffer, size_t length);
-
- virtual int isatty();
-
- virtual off_t seek(off_t position, int whence);
-
- virtual int sync();
-
- virtual off_t size();
-
-protected:
- virtual void lock();
- virtual void unlock();
- FILEHANDLE _fh;
- int pos;
- PlatformMutex _mutex;
-};
-
-/** A filesystem for accessing the local mbed Microcontroller USB disk drive
- *
- * This allows programs to read and write files on the same disk drive that is used to program the
- * mbed Microcontroller. Once created, the standard C file access functions are used to open,
- * read and write files.
- *
- * @note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * LocalFileSystem local("local"); // Create the local filesystem under the name "local"
- *
- * int main() {
- * FILE *fp = fopen("/local/out.txt", "w"); // Open "out.txt" on the local file system for writing
- * fprintf(fp, "Hello World!");
- * fclose(fp);
- * remove("/local/out.txt"); // Removes the file "out.txt" from the local file system
- *
- * DIR *d = opendir("/local"); // Opens the root directory of the local file system
- * struct dirent *p;
- * while((p = readdir(d)) != NULL) { // Print the names of the files in the local file system
- * printf("%s\n", p->d_name); // to stdout.
- * }
- * closedir(d);
- * }
- * @endcode
- *
- * @note
- * If the microcontroller program makes an access to the local drive, it will be marked as "removed"
- * on the Host computer. This means it is no longer accessible from the Host Computer.
- *
- * The drive will only re-appear when the microcontroller program exists. Note that if the program does
- * not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
- * @ingroup platform
- */
-class LocalFileSystem : public FileSystemLike, private NonCopyable<LocalFileSystem> {
- // No modifiable state
-
-public:
- LocalFileSystem(const char *n) : FileSystemLike(n)
- {
-
- }
-
- virtual int open(FileHandle **file, const char *path, int flags);
- virtual int open(DirHandle **dir, const char *name);
- virtual int remove(const char *filename);
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/platform/NonCopyable.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,235 +0,0 @@
-/* Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_NONCOPYABLE_H_
-#define MBED_NONCOPYABLE_H_
-
-#if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0))
-#include "mbed_toolchain.h"
-#include "mbed_debug.h"
-#endif
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_NonCopyable NonCopyable class
- * @{
- */
-
-/**
- * Prevents generation of copy constructor and copy assignment operator in
- * derived classes.
- *
- * @par Usage
- *
- * To prevent generation of copy constructor and copy assignment operator,
- * inherit privately from the NonCopyable class.
- *
- * @code
- * class Resource : NonCopyable<Resource> { };
- *
- * Resource r;
- * // generates compile time error:
- * Resource r2 = r;
- * @endcode
- *
- * @par Background information
- *
- * Instances of polymorphic classes are not meant to be copied. The
- * C++ standards generate a default copy constructor and copy assignment
- * function if these functions have not been defined in the class.
- *
- * Consider the following example:
- *
- * @code
- * // base class representing a connection
- * struct Connection {
- * Connection();
- * virtual ~Connection();
- * virtual void open() = 0;
- * }
- *
- * class SerialConnection : public Connection {
- * public:
- * SerialConnection(Serial*);
- *
- * private:
- * Serial* _serial;
- * };
- *
- * Connection& get_connection() {
- * static SerialConnection serial_connection;
- * return serial_connection;
- * }
- *
- * Connection connection = get_connection();
- * @endcode
- *
- * There is a subtle bug in this code, the function get_connection returns a
- * reference to a Connection which is captured by value instead of reference.
- *
- * When `get_connection` returns a reference to serial_connection it is copied into
- * the local variable connection. The vtable and others members defined in Connection
- * are copied, but members defined in SerialConnection are left apart. This can cause
- * severe crashes or bugs if the virtual functions captured use members not present
- * in the base declaration.
- *
- * To solve that problem, the copy constructor and assignment operator have to
- * be declared (but don't need to be defined) in the private section of the
- * Connection class:
- *
- * @code
- * struct Connection {
- * private:
- * Connection(const Connection&);
- * Connection& operator=(const Connection&);
- * }
- * @endcode
- *
- * Although manually declaring private copy constructor and assignment functions
- * works, it is not ideal. These declarations are usually easy to forget,
- * not immediately visible, and may be obscure to uninformed programmers.
- *
- * Using the NonCopyable class reduces the boilerplate required and expresses
- * the intent because class inheritance appears right after the class name
- * declaration.
- *
- * @code
- * struct Connection : private NonCopyable<Connection> {
- * // regular declarations
- * }
- * @endcode
- *
- *
- * @par Implementation details
- *
- * Using a template type prevents cases where the empty base optimization cannot
- * be applied and therefore ensures that the cost of the NonCopyable semantic
- * sugar is null.
- *
- * As an example, the empty base optimization is prohibited if one of the empty
- * base classes is also a base type of the first nonstatic data member:
- *
- * @code
- * struct A { };
- * struct B : A {
- * int foo;
- * };
- * // thanks to empty base optimization, sizeof(B) == sizeof(int)
- *
- * struct C : A {
- * B b;
- * };
- *
- * // empty base optimization cannot be applied here because A from C and A from
- * // B have a different address. In that case, with the alignment
- * // sizeof(C) == 2* sizeof(int)
- * @endcode
- *
- * The solution to that problem is to templatize the empty class to make it
- * unique to the type it is applied to:
- *
- * @code
- * template<typename T>
- * struct A<T> { };
- * struct B : A<B> {
- * int foo;
- * };
- * struct C : A<C> {
- * B b;
- * };
- *
- * // empty base optimization can be applied B and C does not refer to the same
- * // kind of A. sizeof(C) == sizeof(B) == sizeof(int).
- * @endcode
- *
- * @tparam T The type that should be made noncopyable.
- *
- * @note Compile time errors are disabled if you use the develop or release profile.
- * To override this behavior and force compile time errors in all profiles,
- * set the configuration parameter "platform.force-non-copyable-error" to true.
- */
-template<typename T>
-class NonCopyable {
-#ifndef DOXYGEN_ONLY
-protected:
- /**
- * Disallow construction of NonCopyable objects from outside of its hierarchy.
- */
- NonCopyable() { }
- /**
- * Disallow destruction of NonCopyable objects from outside of its hierarchy.
- */
- ~NonCopyable() { }
-
-#if (!defined(MBED_DEBUG) && (MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR == 0))
- /**
- * NonCopyable copy constructor.
- *
- * A compile time warning is issued when this function is used, and a runtime
- * warning is printed when the copy construction of the noncopyable happens.
- *
- * If you see this warning, your code is probably doing something unspecified.
- * Copying of noncopyable resources can lead to resource leak and random error.
- */
- MBED_DEPRECATED("Invalid copy construction of a NonCopyable resource.")
- NonCopyable(const NonCopyable &)
- {
- debug("Invalid copy construction of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION);
- }
-
- /**
- * NonCopyable copy assignment operator.
- *
- * A compile time warning is issued when this function is used, and a runtime
- * warning is printed when the copy construction of the noncopyable happens.
- *
- * If you see this warning, your code is probably doing something unspecified.
- * Copying of noncopyable resources can lead to resource leak and random error.
- */
- MBED_DEPRECATED("Invalid copy assignment of a NonCopyable resource.")
- NonCopyable &operator=(const NonCopyable &)
- {
- debug("Invalid copy assignment of a NonCopyable resource: %s\r\n", MBED_PRETTY_FUNCTION);
- return *this;
- }
-
-#else
-private:
- /**
- * Declare copy constructor as private. Any attempt to copy construct
- * a NonCopyable will fail at compile time.
- */
- NonCopyable(const NonCopyable &);
-
- /**
- * Declare copy assignment operator as private. Any attempt to copy assign
- * a NonCopyable will fail at compile time.
- */
- NonCopyable &operator=(const NonCopyable &);
-#endif
-#endif
-};
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif /* MBED_NONCOPYABLE_H_ */
--- a/STM32F103C8T6_MPA/mbed/platform/PlatformMutex.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,92 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef PLATFORM_MUTEX_H
-#define PLATFORM_MUTEX_H
-
-#include "platform/NonCopyable.h"
-
-/** \addtogroup platform
- * @{
- */
-
-/** \defgroup platform_PlatformMutex PlatformMutex class
- * @{
- */
-
-/** The PlatformMutex class is used to synchronize the execution of threads.
- *
- * Mbed drivers use the PlatformMutex class instead of rtos::Mutex.
- * This enables the use of drivers when the Mbed OS is compiled without the RTOS.
- *
- * @note
- * - When the RTOS is present, the PlatformMutex becomes a typedef for rtos::Mutex.
- * - When the RTOS is absent, all methods are defined as noop.
- */
-
-#ifdef MBED_CONF_RTOS_PRESENT
-
-#include "rtos/Mutex.h"
-typedef rtos::Mutex PlatformMutex;
-
-#else
-
-class PlatformMutex: private mbed::NonCopyable<PlatformMutex> {
-public:
- /** Create a PlatformMutex object.
- *
- * @note When the RTOS is present, this is an alias for rtos::Mutex::Mutex().
- */
- PlatformMutex()
- {
- }
-
- /** PlatformMutex destructor.
- *
- * @note When the RTOS is present, this is an alias for rtos::Mutex::~Mutex().
- */
- ~PlatformMutex()
- {
- }
-
- /** Wait until a PlatformMutex becomes available.
- *
- * @note
- * - When the RTOS is present, this is an alias for rtos::Mutex::lock().
- * - When the RTOS is absent, this is a noop.
- */
- void lock()
- {
- }
-
- /** Unlock a PlatformMutex that the same thread has previously locked.
- *
- * @note
- * - When the RTOS is present, this is an alias for rtos::Mutex::unlock().
- * - When the RTOS is absent, this is a noop.
- */
- void unlock()
- {
- }
-};
-
-#endif
-
-#endif
-
-/**@}*/
-
-/**@}*/
--- a/STM32F103C8T6_MPA/mbed/platform/ScopedLock.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SCOPEDLOCK_H
-#define MBED_SCOPEDLOCK_H
-
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_ScopedLock ScopedLock functions
- * @{
- */
-
-/** RAII-style mechanism for owning a lock of Lockable object for the duration of a scoped block
- *
- * @tparam Lockable The type implementing BasicLockable concept
- *
- * @note For type Lockable to be BasicLockable, the following conditions have to be satisfied:
- * - has public member function @a lock which blocks until a lock can be obtained for the current execution context
- * - has public member function @a unlock which releases the lock
- *
- * Usage:
- *
- * Example with rtos::Mutex
- *
- * @code
- * void foo(Mutex &m) {
- * ScopedLock<Mutex> lock(m);
- * // Mutex lock protects code in this block
- * }
- * @endcode
- *
- *
- * More generic example
- *
- * @code
- * template<typename Lockable>
- * void foo(Lockable& lockable) {
- * ScopedLock<Lockable> lock(lockable);
- * // Code in this block runs under lock
- * }
- * @endcode
- */
-template <typename Lockable>
-class ScopedLock : private NonCopyable<ScopedLock<Lockable> > {
-public:
- /** Locks given lockable object
- *
- * @param lockable reference to the instance of Lockable object
- * @note lockable object should outlive the ScopedLock object
- */
- ScopedLock(Lockable &lockable): _lockable(lockable)
- {
- _lockable.lock();
- }
-
- ~ScopedLock()
- {
- _lockable.unlock();
- }
-private:
- Lockable &_lockable;
-};
-
-/**@}*/
-
-/**@}*/
-
-} // embed
-
-#endif // MBED_SCOPEDLOCK_H
--- a/STM32F103C8T6_MPA/mbed/platform/ScopedRamExecutionLock.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SCOPEDRAMEXECUTIONLOCK_H
-#define MBED_SCOPEDRAMEXECUTIONLOCK_H
-
-#include "platform/mbed_mpu_mgmt.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-
-/** RAII object for disabling, then restoring RAM execute never mode
- * Usage:
- * @code
- *
- * void f() {
- * // some code here
- * {
- * ScopedRamExecutionLock make_ram_executable;
- * // Code in this block is allowed to call functions in RAM
- * }
- * // Execution from RAM is no longer allowed
- * }
- * @endcode
- */
-class ScopedRamExecutionLock : private mbed::NonCopyable<ScopedRamExecutionLock> {
-public:
-
- /**
- * Allow execution from RAM
- *
- * Increment the execute never lock to ensure code can
- * be executed from RAM. This class uses RAII to allow
- * execution from ram while it is in scope.
- */
- ScopedRamExecutionLock()
- {
- mbed_mpu_manager_lock_ram_execution();
- }
-
- /**
- * Restore previous execution from RAM settings
- *
- * Decrement the execute never lock to return execute from RAM
- * to its prior state.
- */
- ~ScopedRamExecutionLock()
- {
- mbed_mpu_manager_unlock_ram_execution();
- }
-};
-
-/**@}*/
-
-}
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/ScopedRomWriteLock.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,72 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SCOPEDROMWRITELOCK_H
-#define MBED_SCOPEDROMWRITELOCK_H
-
-#include "platform/mbed_mpu_mgmt.h"
-#include "platform/NonCopyable.h"
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-
-/** RAII object for disabling, then restoring ROM write never mode
- * Usage:
- * @code
- *
- * void f() {
- * // some code here
- * {
- * ScopedRomWriteLock make_ram_executable;
- * // Code in this block is allowed to write to ROM
- * }
- * // Writing to ROM is no longer allowed
- * }
- * @endcode
- */
-class ScopedRomWriteLock : private mbed::NonCopyable<ScopedRomWriteLock> {
-public:
-
- /**
- * Allow writing to ROM
- *
- * Increment the ROM write lock to ensure code can
- * write to ROM. This class uses RAII to allow
- * writing to ROM while it is in scope.
- */
- ScopedRomWriteLock()
- {
- mbed_mpu_manager_lock_rom_write();
- }
-
- /**
- * Restore previous write to ROM settings
- *
- * Decrement the ROM write lock to return ROM write
- * to its prior state.
- */
- ~ScopedRomWriteLock()
- {
- mbed_mpu_manager_unlock_rom_write();
- }
-};
-
-/**@}*/
-
-}
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/SharedPtr.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,300 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __SHAREDPTR_H__
-#define __SHAREDPTR_H__
-
-#include <stdlib.h>
-
-#include <stdint.h>
-#include <stddef.h>
-
-#include "platform/mbed_critical.h"
-
-namespace mbed {
-
-/** Shared pointer class.
- *
- * A shared pointer is a "smart" pointer that retains ownership of an object using
- * reference counting across all smart pointers referencing that object.
- *
- * @code
- * #include "platform/SharedPtr.h"
- *
- * void test() {
- * struct MyStruct { int a; };
- *
- * // Create shared pointer
- * SharedPtr<MyStruct> ptr( new MyStruct );
- *
- * // Increase reference count
- * SharedPtr<MyStruct> ptr2( ptr );
- *
- * ptr = NULL; // Reference to the struct instance is still held by ptr2
- *
- * ptr2 = NULL; // The raw pointer is freed
- * }
- * @endcode
- *
- *
- * It is similar to the std::shared_ptr class introduced in C++11;
- * however, this is not a compatible implementation (no weak pointer, no make_shared, no custom deleters and so on.)
- *
- * Usage: SharedPtr<Class> ptr(new Class())
- *
- * When ptr is passed around by value, the copy constructor and
- * destructor manages the reference count of the raw pointer.
- * If the counter reaches zero, delete is called on the raw pointer.
- *
- * To avoid loops, use "weak" references by calling the original
- * pointer directly through ptr.get().
- */
-
-template <class T>
-class SharedPtr {
-public:
- /**
- * @brief Create empty SharedPtr not pointing to anything.
- * @details Used for variable declaration.
- */
- SharedPtr(): _ptr(NULL), _counter(NULL)
- {
- }
-
- /**
- * @brief Create new SharedPtr
- * @param ptr Pointer to take control over
- */
- SharedPtr(T *ptr): _ptr(ptr), _counter(NULL)
- {
- // Allocate counter on the heap, so it can be shared
- if (_ptr != NULL) {
- _counter = new uint32_t;
- *_counter = 1;
- }
- }
-
- /**
- * @brief Destructor.
- * @details Decrement reference counter, and delete object if no longer pointed to.
- */
- ~SharedPtr()
- {
- decrement_counter();
- }
-
- /**
- * @brief Copy constructor.
- * @details Create new SharedPtr from other SharedPtr by
- * copying pointer to original object and pointer to counter.
- * @param source Object being copied from.
- */
- SharedPtr(const SharedPtr &source): _ptr(source._ptr), _counter(source._counter)
- {
- // Increment reference counter
- if (_ptr != NULL) {
- core_util_atomic_incr_u32(_counter, 1);
- }
- }
-
- /**
- * @brief Assignment operator.
- * @details Cleanup previous reference and assign new pointer and counter.
- * @param source Object being assigned from.
- * @return Object being assigned.
- */
- SharedPtr operator=(const SharedPtr &source)
- {
- if (this != &source) {
- // Clean up by decrementing counter
- decrement_counter();
-
- // Assign new values
- _ptr = source.get();
- _counter = source.get_counter();
-
- // Increment new counter
- if (_ptr != NULL) {
- core_util_atomic_incr_u32(_counter, 1);
- }
- }
-
- return *this;
- }
-
- /**
- * @brief Replaces the managed pointer with a new unmanaged pointer.
- * @param[in] ptr the new raw pointer to manage.
- */
- void reset(T *ptr)
- {
- // Clean up by decrementing counter
- decrement_counter();
-
- _ptr = ptr;
- if (ptr != NULL) {
- // Allocate counter on the heap, so it can be shared
- _counter = new uint32_t;
- *_counter = 1;
- } else {
- _counter = NULL;
- }
- }
-
- /**
- * @brief Replace the managed pointer with a NULL pointer.
- */
- void reset()
- {
- reset(NULL);
- }
-
- /**
- * @brief Raw pointer accessor.
- * @details Get raw pointer to object pointed to.
- * @return Pointer.
- */
- T *get() const
- {
- return _ptr;
- }
-
- /**
- * @brief Reference count accessor.
- * @return Reference count.
- */
- uint32_t use_count() const
- {
- if (_ptr != NULL) {
- core_util_critical_section_enter();
- uint32_t current_counter = *_counter;
- core_util_critical_section_exit();
- return current_counter;
- } else {
- return 0;
- }
- }
-
- /**
- * @brief Dereference object operator.
- * @details Override to return the object pointed to.
- */
- T &operator*() const
- {
- return *_ptr;
- }
-
- /**
- * @brief Dereference object member operator.
- * @details Override to return return member in object pointed to.
- */
- T *operator->() const
- {
- return _ptr;
- }
-
- /**
- * @brief Boolean conversion operator.
- * @return Whether or not the pointer is NULL.
- */
- operator bool() const
- {
- return (_ptr != NULL);
- }
-
-private:
- /**
- * @brief Get pointer to reference counter.
- * @return Pointer to reference counter.
- */
- uint32_t *get_counter() const
- {
- return _counter;
- }
-
- /**
- * @brief Decrement reference counter.
- * @details If count reaches zero, free counter and delete object pointed to.
- * Does not modify our own pointers - assumption is they will be overwritten
- * or destroyed immediately afterwards.
- */
- void decrement_counter()
- {
- if (_ptr != NULL) {
- uint32_t new_value = core_util_atomic_decr_u32(_counter, 1);
- if (new_value == 0) {
- delete _counter;
- delete _ptr;
- }
- }
- }
-
-private:
- // Pointer to shared object
- T *_ptr;
-
- // Pointer to shared reference counter
- uint32_t *_counter;
-};
-
-/** Non-member relational operators.
- */
-template <class T, class U>
-bool operator== (const SharedPtr<T> &lhs, const SharedPtr<U> &rhs)
-{
- return (lhs.get() == rhs.get());
-}
-
-template <class T, typename U>
-bool operator== (const SharedPtr<T> &lhs, U rhs)
-{
- return (lhs.get() == (T *) rhs);
-}
-
-template <class T, typename U>
-bool operator== (U lhs, const SharedPtr<T> &rhs)
-{
- return ((T *) lhs == rhs.get());
-}
-
-/** Non-member relational operators.
- */
-template <class T, class U>
-bool operator!= (const SharedPtr<T> &lhs, const SharedPtr<U> &rhs)
-{
- return (lhs.get() != rhs.get());
-}
-
-template <class T, typename U>
-bool operator!= (const SharedPtr<T> &lhs, U rhs)
-{
- return (lhs.get() != (T *) rhs);
-}
-
-template <class T, typename U>
-bool operator!= (U lhs, const SharedPtr<T> &rhs)
-{
- return ((T *) lhs != rhs.get());
-}
-
-} /* namespace mbed */
-
-#ifndef MBED_NO_GLOBAL_USING_DIRECTIVE
-using mbed::SharedPtr;
-#endif
-
-#endif // __SHAREDPTR_H__
--- a/STM32F103C8T6_MPA/mbed/platform/SingletonPtr.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,142 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_SingletonPtr SingletonPtr class
- * @{
- */
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef SINGLETONPTR_H
-#define SINGLETONPTR_H
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <new>
-#include "platform/mbed_assert.h"
-#ifdef MBED_CONF_RTOS_PRESENT
-#include "cmsis_os2.h"
-#endif
-
-#ifdef MBED_CONF_RTOS_PRESENT
-extern osMutexId_t singleton_mutex_id;
-#endif
-
-/** Lock the singleton mutex
- *
- * This function is typically used to provide
- * exclusive access when initializing a
- * global object.
- */
-inline static void singleton_lock(void)
-{
-#ifdef MBED_CONF_RTOS_PRESENT
- if (!singleton_mutex_id) {
- // RTOS has not booted yet so no mutex is needed
- return;
- }
- osMutexAcquire(singleton_mutex_id, osWaitForever);
-#endif
-}
-
-/** Unlock the singleton mutex
- *
- * This function is typically used to provide
- * exclusive access when initializing a
- * global object.
- */
-inline static void singleton_unlock(void)
-{
-#ifdef MBED_CONF_RTOS_PRESENT
- if (!singleton_mutex_id) {
- // RTOS has not booted yet so no mutex is needed
- return;
- }
- osMutexRelease(singleton_mutex_id);
-#endif
-}
-
-/** Utility class for creating an using a singleton
- *
- * @note Synchronization level: Thread safe
- *
- * @note: This class must only be used in a static context -
- * this class must never be allocated or created on the
- * stack.
- *
- * @note: This class is lazily initialized on first use.
- * This class is a POD type so if it is not used it will
- * be garbage collected.
- */
-template <class T>
-struct SingletonPtr {
-
- /** Get a pointer to the underlying singleton
- *
- * @returns
- * A pointer to the singleton
- */
- T *get() const
- {
- if (NULL == _ptr) {
- singleton_lock();
- if (NULL == _ptr) {
- _ptr = new (_data) T();
- }
- singleton_unlock();
- }
- // _ptr was not zero initialized or was
- // corrupted if this assert is hit
- MBED_ASSERT(_ptr == (T *)&_data);
- return _ptr;
- }
-
- /** Get a pointer to the underlying singleton
- *
- * @returns
- * A pointer to the singleton
- */
- T *operator->() const
- {
- return get();
- }
-
- /** Get a reference to the underlying singleton
- *
- * @returns
- * A reference to the singleton
- */
- T &operator*() const
- {
- return *get();
- }
-
- // This is zero initialized when in global scope
- mutable T *_ptr;
-#if __cplusplus >= 201103L
- // Align data appropriately
- alignas(T) mutable char _data[sizeof(T)];
-#else
- // Force data to be 8 byte aligned
- mutable uint64_t _data[(sizeof(T) + sizeof(uint64_t) - 1) / sizeof(uint64_t)];
-#endif
-};
-
-#endif
-/**@}*/
-
-/**@}*/
--- a/STM32F103C8T6_MPA/mbed/platform/Span.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1025 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2018-2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_PLATFORM_SPAN_H_
-#define MBED_PLATFORM_SPAN_H_
-
-#include <algorithm>
-#include <stddef.h>
-#include <stdint.h>
-
-#include "platform/mbed_assert.h"
-
-namespace mbed {
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_Span Span class
- * @{
- */
-
-// Internal details of Span
-// It is used construct Span from Span of convertible types (non const -> const)
-namespace span_detail {
-
-// If From type is convertible to To type, then the compilation constant value is
-// true; otherwise, it is false.
-template<typename From, typename To>
-class is_convertible {
- struct true_type {
- char x[512];
- };
- struct false_type { };
-
- static const From &generator();
- static true_type sink(const To &);
- static false_type sink(...);
-
-public:
- static const bool value = sizeof(true_type) == sizeof(sink(generator()));
-};
-
-}
-
-#if defined(DOXYGEN_ONLY)
-/**
- * Special value for the Extent parameter of Span.
- * If the type uses this value, then the size of the array is stored in the object
- * at runtime.
- *
- * @relates Span
- */
-const ptrdiff_t SPAN_DYNAMIC_EXTENT = -1;
-#else
-#define SPAN_DYNAMIC_EXTENT -1
-#endif
-
-/**
- * Nonowning view to a sequence of contiguous elements.
- *
- * Spans encapsulate a pointer to a sequence of contiguous elements and its size
- * into a single object. Span can replace the traditional pair of pointer and
- * size arguments passed as array definitions in function calls.
- *
- * @par Operations
- *
- * Span objects can be copied and assigned like regular value types with the help
- * of the copy constructor or the copy assignment (=) operator.
- *
- * You can retrieve elements of the object with the subscript ([]) operator. You can access the
- * pointer to the first element of the sequence viewed with data().
- * The function size() returns the number of elements in the sequence, and
- * empty() informs whether there is any element in the sequence.
- *
- * You can slice Span from the beginning of the sequence (first()), from the end
- * of the sequence (last()) or from an arbitrary point of the sequence (subspan()).
- *
- * @par Size encoding
- *
- * The size of the sequence can be encoded in the type itself or in the value of
- * the instance with the help of the template parameter Extent:
- *
- * - Span<uint8_t, 6>: Span over a sequence of 6 elements.
- * - Span<uint8_t>: Span over an arbitrary long sequence.
- *
- * When the size is encoded in the type itself, it is guaranteed that the Span
- * view is a valid sequence (not empty() and not NULL) - unless Extent equals 0.
- * The type system also prevents automatic conversion from Span of different
- * sizes. Finally, the Span object is internally represented as a single pointer.
- *
- * When the size of the sequence viewed is encoded in the Span value, Span
- * instances can view an empty sequence. The function empty() helps client code
- * decide whether Span is viewing valid content or not.
- *
- * @par Example
- *
- * - Encoding fixed size array: Array values in parameter decays automatically
- * to pointer, which leaves room for subtitle bugs:
- *
- * @code
- typedef uint8_t mac_address_t[6];
- void process_mac(mac_address_t);
-
- // compile just fine
- uint8_t *invalid_value = NULL;
- process_mac(invalid_value);
-
-
- // correct way
- typedef Span<uint8_t, 6> mac_address_t;
- void process_mac(mac_address_t);
-
- // compilation error
- uint8_t *invalid_value = NULL;
- process_mac(invalid_value);
-
- // compilation ok
- uint8_t valid_value[6];
- process_mac(valid_value);
- * @endcode
- *
- * - Arbitrary buffer: When dealing with multiple buffers, it becomes painful to
- * keep track of every buffer size and pointer.
- *
- * @code
- const uint8_t options_tag[OPTIONS_TAG_SIZE];
-
- struct parsed_value_t {
- uint8_t *header;
- uint8_t *options;
- uint8_t *payload;
- size_t payload_size;
- }
-
- parsed_value_t parse(uint8_t *buffer, size_t buffer_size)
- {
- parsed_value_t parsed_value { 0 };
-
- if (buffer != NULL && buffer_size <= MINIMAL_BUFFER_SIZE) {
- return parsed_value;
- }
-
- parsed_value.header = buffer;
- parsed_value.header_size = BUFFER_HEADER_SIZE;
-
- if (memcmp(buffer + HEADER_OPTIONS_INDEX, options_tag, sizeof(options_tag)) == 0) {
- options = buffer + BUFFER_HEADER_SIZE;
- payload = buffer + BUFFER_HEADER_SIZE + OPTIONS_SIZE;
- payload_size = buffer_size - BUFFER_HEADER_SIZE + OPTIONS_SIZE;
- } else {
- payload = buffer + BUFFER_HEADER_SIZE;
- payload_size = buffer_size - BUFFER_HEADER_SIZE;
- }
-
- return parsed_value;
- }
-
-
- //with Span
- struct parsed_value_t {
- Span<uint8_t> header;
- Span<uint8_t> options;
- Span<uint8_t> payload;
- }
-
- parsed_value_t parse(const Span<uint8_t> &buffer)
- {
- parsed_value_t parsed_value;
-
- if (buffer.size() <= MINIMAL_BUFFER_SIZE) {
- return parsed_value;
- }
-
- parsed_value.header = buffer.first(BUFFER_HEADER_SIZE);
-
- if (buffer.subspan<HEADER_OPTIONS_INDEX, sizeof(options_tag)>() == option_tag) {
- options = buffer.supspan(parsed_value.header.size(), OPTIONS_SIZE);
- }
-
- payload = buffer.subspan(parsed_value.header.size() + parsed_value.options.size());
-
- return parsed_value;
- }
- * @endcode
- *
- * @note You can create Span instances with the help of the function template
- * make_Span() and make_const_Span().
- *
- * @note Span<T, Extent> objects can be implicitly converted to Span<T> objects
- * where required.
- *
- * @tparam ElementType type of objects the Span views.
- *
- * @tparam Extent The size of the contiguous sequence viewed. The default value
- * SPAN_DYNAMIC_SIZE is special because it allows construction of Span objects of
- * any size (set at runtime).
- */
-template<typename ElementType, ptrdiff_t Extent = SPAN_DYNAMIC_EXTENT>
-struct Span {
-
- /**
- * Type of the element contained
- */
- typedef ElementType element_type;
-
- /**
- * Type of the index.
- */
- typedef ptrdiff_t index_type;
-
- /**
- * Pointer to an ElementType
- */
- typedef element_type *pointer;
-
- /**
- * Reference to an ElementType
- */
- typedef element_type &reference;
-
- /**
- * Size of the Extent; -1 if dynamic.
- */
- static const index_type extent = Extent;
-
- MBED_STATIC_ASSERT(Extent >= 0, "Invalid extent for a Span");
-
- /**
- * Construct an empty Span.
- *
- * @post a call to size() returns 0, and data() returns NULL.
- *
- * @note This function is not accessible if Extent != SPAN_DYNAMIC_EXTENT or
- * Extent != 0 .
- */
- Span() :
- _data(NULL)
- {
- MBED_STATIC_ASSERT(
- Extent == 0,
- "Cannot default construct a static-extent Span (unless Extent is 0)"
- );
- }
-
- /**
- * Construct a Span from a pointer to a buffer and its size.
- *
- * @param ptr Pointer to the beginning of the data viewed.
- *
- * @param count Number of elements viewed.
- *
- * @pre [ptr, ptr + count) must be be a valid range.
- * @pre count must be equal to Extent.
- *
- * @post a call to size() returns Extent, and data() returns @p ptr.
- */
- Span(pointer ptr, index_type count) :
- _data(ptr)
- {
- MBED_ASSERT(count == Extent);
- MBED_ASSERT(Extent == 0 || ptr != NULL);
- }
-
- /**
- * Construct a Span from the range [first, last).
- *
- * @param first Pointer to the beginning of the data viewed.
- * @param last End of the range (element after the last element).
- *
- * @pre [first, last) must be be a valid range.
- * @pre first <= last.
- * @pre last - first must be equal to Extent.
- *
- * @post a call to size() returns Extent, and data() returns @p first.
- */
- Span(pointer first, pointer last) :
- _data(first)
- {
- MBED_ASSERT(first <= last);
- MBED_ASSERT((last - first) == Extent);
- MBED_ASSERT(Extent == 0 || first != NULL);
- }
-
- // AStyle ignore, not handling correctly below
- // *INDENT-OFF*
- /**
- * Construct a Span from the reference to an array.
- *
- * @param elements Reference to the array viewed.
- *
- * @post a call to size() returns Extent, and data() returns a
- * pointer to elements.
- */
- Span(element_type (&elements)[Extent]):
- _data(elements) { }
-
- /**
- * Construct a Span object from another Span of the same size.
- *
- * @param other The Span object used to construct this.
- *
- * @note For Span with a positive extent, this function is not accessible.
- *
- * @note OtherElementType(*)[] must be convertible to ElementType(*)[].
- */
- template<typename OtherElementType>
- Span(const Span<OtherElementType, Extent> &other):
- _data(other.data())
- {
- MBED_STATIC_ASSERT(
- (span_detail::is_convertible<OtherElementType (*)[1], ElementType (*)[1]>::value),
- "OtherElementType(*)[] should be convertible to ElementType (*)[]"
- );
- }
- // *INDENT-ON*
-
- /**
- * Return the size of the sequence viewed.
- *
- * @return The size of the sequence viewed.
- */
- index_type size() const
- {
- return Extent;
- }
-
- /**
- * Return if the sequence is empty or not.
- *
- * @return true if the sequence is empty and false otherwise.
- */
- bool empty() const
- {
- return size() == 0;
- }
-
- /**
- * Returns a reference to the element at position @p index.
- *
- * @param index Index of the element to access.
- *
- * @return A reference to the element at the index specified in input.
- *
- * @pre 0 <= index < Extent.
- */
- reference operator[](index_type index) const
- {
-#ifdef MBED_DEBUG
- MBED_ASSERT(0 <= index && index < Extent);
-#endif
- return _data[index];
- }
-
- /**
- * Return a pointer to the first element of the sequence or NULL if the Span
- * is empty().
- *
- * @return The pointer to the first element of the Span.
- */
- pointer data() const
- {
- return _data;
- }
-
- /**
- * Create a new Span over the first @p Count elements of the existing view.
- *
- * @tparam Count The number of element viewed by the new Span
- *
- * @return A new Span over the first @p Count elements.
- *
- * @pre Count >= 0 && Count <= size().
- */
- template<ptrdiff_t Count>
- Span<element_type, Count> first() const
- {
- MBED_STATIC_ASSERT(
- (0 <= Count) && (Count <= Extent),
- "Invalid subspan extent"
- );
- return Span<element_type, Count>(_data, Count);
- }
-
- /**
- * Create a new Span over the last @p Count elements of the existing view.
- *
- * @tparam Count The number of element viewed by the new Span.
- *
- * @return A new Span over the last @p Count elements.
- *
- * @pre Count >= 0 && Count <= size().
- */
- template<ptrdiff_t Count>
- Span<element_type, Count> last() const
- {
- MBED_STATIC_ASSERT(
- (0 <= Count) && (Count <= Extent),
- "Invalid subspan extent"
- );
- return Span<element_type, Count>(_data + (Extent - Count), Count);
- }
-
- // AStyle ignore, not handling correctly below
- // *INDENT-OFF*
- /**
- * Create a subspan that is a view of other Count elements; the view starts at
- * element Offset.
- *
- * @tparam Offset The offset of the first element viewed by the subspan.
- *
- * @tparam Count The number of elements present in the subspan. If Count
- * is equal to SPAN_DYNAMIC_EXTENT, then a Span starting at offset and
- * containing the rest of the elements is returned.
- *
- * @return A subspan of this starting at Offset and Count long.
- */
- template<std::ptrdiff_t Offset, std::ptrdiff_t Count>
- Span<element_type, Count == SPAN_DYNAMIC_EXTENT ? Extent - Offset : Count>
- subspan() const
- {
- MBED_STATIC_ASSERT(
- 0 <= Offset && Offset <= Extent,
- "Invalid subspan offset"
- );
- MBED_STATIC_ASSERT(
- (Count == SPAN_DYNAMIC_EXTENT) ||
- (0 <= Count && (Count + Offset) <= Extent),
- "Invalid subspan count"
- );
- return Span<element_type, Count == SPAN_DYNAMIC_EXTENT ? Extent - Offset : Count>(
- _data + Offset,
- Count == SPAN_DYNAMIC_EXTENT ? Extent - Offset : Count
- );
- }
- // *INDENT-ON*
-
- /**
- * Create a new Span over the first @p count elements of the existing view.
- *
- * @param count The number of element viewed by the new Span.
- *
- * @return A new Span over the first @p count elements.
- */
- Span<element_type, SPAN_DYNAMIC_EXTENT> first(index_type count) const
- {
- MBED_ASSERT(0 <= count && count <= Extent);
- return Span<element_type, SPAN_DYNAMIC_EXTENT>(_data, count);
- }
-
- /**
- * Create a new Span over the last @p count elements of the existing view.
- *
- * @param count The number of elements viewed by the new Span.
- *
- * @return A new Span over the last @p count elements.
- */
- Span<element_type, SPAN_DYNAMIC_EXTENT> last(index_type count) const
- {
- MBED_ASSERT(0 <= count && count <= Extent);
- return Span<element_type, SPAN_DYNAMIC_EXTENT>(
- _data + (Extent - count),
- count
- );
- }
-
- /**
- * Create a subspan that is a view of other count elements; the view starts at
- * element offset.
- *
- * @param offset The offset of the first element viewed by the subspan.
- *
- * @param count The number of elements present in the subspan. If Count
- * is equal to SPAN_DYNAMIC_EXTENT, then a span starting at offset and
- * containing the rest of the elements is returned.
- *
- * @return
- */
- Span<element_type, SPAN_DYNAMIC_EXTENT> subspan(
- index_type offset, index_type count = SPAN_DYNAMIC_EXTENT
- ) const
- {
- MBED_ASSERT(0 <= offset && offset <= Extent);
- MBED_ASSERT(
- (count == SPAN_DYNAMIC_EXTENT) ||
- (0 <= count && (count + offset) <= Extent)
- );
- return Span<element_type, SPAN_DYNAMIC_EXTENT>(
- _data + offset,
- count == SPAN_DYNAMIC_EXTENT ? Extent - offset : count
- );
- }
-
-private:
- pointer _data;
-};
-
-/**
- * Span specialization that handle dynamic size.
- */
-template<typename ElementType>
-struct Span<ElementType, SPAN_DYNAMIC_EXTENT> {
- /**
- * Type of the element contained.
- */
- typedef ElementType element_type;
-
- /**
- * Type of the index.
- */
- typedef ptrdiff_t index_type;
-
- /**
- * Pointer to an ElementType.
- */
- typedef element_type *pointer;
-
- /**
- * Reference to an ElementType.
- */
- typedef element_type &reference;
-
- /**
- * Size of the Extent; -1 if dynamic.
- */
- static const index_type extent = SPAN_DYNAMIC_EXTENT;
-
- /**
- * Construct an empty Span.
- *
- * @post a call to size() returns 0, and data() returns NULL.
- *
- * @note This function is not accessible if Extent != SPAN_DYNAMIC_EXTENT or
- * Extent != 0 .
- */
- Span() :
- _data(NULL), _size(0) { }
-
- /**
- * Construct a Span from a pointer to a buffer and its size.
- *
- * @param ptr Pointer to the beginning of the data viewed.
- *
- * @param count Number of elements viewed.
- *
- * @pre [ptr, ptr + count) must be be a valid range.
- * @pre count must be equal to extent.
- *
- * @post a call to size() returns count, and data() returns @p ptr.
- */
- Span(pointer ptr, index_type count) :
- _data(ptr), _size(count)
- {
- MBED_ASSERT(count >= 0);
- MBED_ASSERT(ptr != NULL || count == 0);
- }
-
- /**
- * Construct a Span from the range [first, last).
- *
- * @param first Pointer to the beginning of the data viewed.
- * @param last End of the range (element after the last element).
- *
- * @pre [first, last) must be be a valid range.
- * @pre first <= last.
- *
- * @post a call to size() returns the result of (last - first), and
- * data() returns @p first.
- */
- Span(pointer first, pointer last) :
- _data(first), _size(last - first)
- {
- MBED_ASSERT(first <= last);
- MBED_ASSERT(first != NULL || (last - first) == 0);
- }
-
- // AStyle ignore, not handling correctly below
- // *INDENT-OFF*
- /**
- * Construct a Span from the reference to an array.
- *
- * @param elements Reference to the array viewed.
- *
- * @tparam Count Number of elements of T presents in the array.
- *
- * @post a call to size() returns Count, and data() returns a
- * pointer to elements.
- */
- template<size_t Count>
- Span(element_type (&elements)[Count]):
- _data(elements), _size(Count) { }
-
- /**
- * Construct a Span object from another Span.
- *
- * @param other The Span object used to construct this.
- *
- * @note For Span with a positive extent, this function is not accessible.
- *
- * @note OtherElementType(*)[] must be convertible to ElementType(*)[].
- */
- template<typename OtherElementType, ptrdiff_t OtherExtent>
- Span(const Span<OtherElementType, OtherExtent> &other):
- _data(other.data()), _size(other.size())
- {
- MBED_STATIC_ASSERT(
- (span_detail::is_convertible<OtherElementType (*)[1], ElementType (*)[1]>::value),
- "OtherElementType(*)[] should be convertible to ElementType (*)[]"
- );
- }
- // *INDENT-ON*
-
- /**
- * Return the size of the array viewed.
- *
- * @return The number of elements present in the array viewed.
- */
- index_type size() const
- {
- return _size;
- }
-
- /**
- * Return if the sequence viewed is empty or not.
- *
- * @return true if the sequence is empty and false otherwise.
- */
- bool empty() const
- {
- return size() == 0;
- }
-
- /**
- * Access to an element of the sequence.
- *
- * @param index Element index to access.
- *
- * @return A reference to the element at the index specified in input.
- *
- * @pre index is less than size().
- */
- reference operator[](index_type index) const
- {
-#ifdef MBED_DEBUG
- MBED_ASSERT(0 <= index && index < _size);
-#endif
- return _data[index];
- }
-
- /**
- * Get the raw pointer to the sequence viewed.
- *
- * @return The raw pointer to the first element viewed.
- */
- pointer data() const
- {
- return _data;
- }
-
- /**
- * Create a new Span over the first @p Count elements of the existing view.
- *
- * @tparam Count The number of elements viewed by the new Span.
- *
- * @return A new Span over the first @p Count elements.
- *
- * @pre Count >= 0 && Count <= size().
- */
- template<ptrdiff_t Count>
- Span<element_type, Count> first() const
- {
- MBED_ASSERT((Count >= 0) && (Count <= _size));
- return Span<element_type, Count>(_data, Count);
- }
-
- /**
- * Create a new Span over the last @p Count elements of the existing view.
- *
- * @tparam Count The number of elements viewed by the new Span.
- *
- * @return A new Span over the last @p Count elements.
- *
- * @pre Count >= 0 && Count <= size().
- */
- template<ptrdiff_t Count>
- Span<element_type, Count> last() const
- {
- MBED_ASSERT((0 <= Count) && (Count <= _size));
- return Span<element_type, Count>(_data + (_size - Count), Count);
- }
-
- /**
- * Create a subspan that is a view other Count elements; the view starts at
- * element Offset.
- *
- * @tparam Offset The offset of the first element viewed by the subspan.
- *
- * @tparam Count The number of elements present in the subspan. If Count
- * is equal to SPAN_DYNAMIC_EXTENT, then a Span starting at offset and
- * containing the rest of the elements is returned.
- *
- * @return A subspan of this starting at Offset and Count long.
- */
- template<std::ptrdiff_t Offset, std::ptrdiff_t Count>
- Span<element_type, Count>
- subspan() const
- {
- MBED_ASSERT(0 <= Offset && Offset <= _size);
- MBED_ASSERT(
- (Count == SPAN_DYNAMIC_EXTENT) ||
- (0 <= Count && (Count + Offset) <= _size)
- );
- return Span<element_type, Count>(
- _data + Offset,
- Count == SPAN_DYNAMIC_EXTENT ? _size - Offset : Count
- );
- }
-
- /**
- * Create a new Span over the first @p count elements of the existing view.
- *
- * @param count The number of elements viewed by the new Span.
- *
- * @return A new Span over the first @p count elements.
- */
- Span<element_type, SPAN_DYNAMIC_EXTENT> first(index_type count) const
- {
- MBED_ASSERT(0 <= count && count <= _size);
- return Span<element_type, SPAN_DYNAMIC_EXTENT>(_data, count);
- }
-
- /**
- * Create a new Span over the last @p count elements of the existing view.
- *
- * @param count The number of elements viewed by the new Span.
- *
- * @return A new Span over the last @p count elements.
- */
- Span<element_type, SPAN_DYNAMIC_EXTENT> last(index_type count) const
- {
- MBED_ASSERT(0 <= count && count <= _size);
- return Span<element_type, SPAN_DYNAMIC_EXTENT>(
- _data + (_size - count),
- count
- );
- }
-
- /**
- * Create a subspan that is a view of other count elements; the view starts at
- * element offset.
- *
- * @param offset The offset of the first element viewed by the subspan.
- *
- * @param count The number of elements present in the subspan. If Count
- * is equal to SPAN_DYNAMIC_EXTENT, then a Span starting at offset and
- * containing the rest of the elements is returned.
- *
- * @return A subspan of this starting at offset and count long.
- */
- Span<element_type, SPAN_DYNAMIC_EXTENT> subspan(
- index_type offset, index_type count = SPAN_DYNAMIC_EXTENT
- ) const
- {
- MBED_ASSERT(0 <= offset && offset <= _size);
- MBED_ASSERT(
- (count == SPAN_DYNAMIC_EXTENT) ||
- (0 <= count && (count + offset) <= _size)
- );
- return Span<element_type, SPAN_DYNAMIC_EXTENT>(
- _data + offset,
- count == SPAN_DYNAMIC_EXTENT ? _size - offset : count
- );
- }
-
-private:
- pointer _data;
- index_type _size;
-};
-
-/**
- * Equality operator between two Span objects.
- *
- * @param lhs Left side of the binary operation.
- * @param rhs Right side of the binary operation.
- *
- * @return True if Spans in input have the same size and the same content and
- * false otherwise.
- *
- * @relates Span
- */
-template<typename T, typename U, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
-bool operator==(const Span<T, LhsExtent> &lhs, const Span<U, RhsExtent> &rhs)
-{
- if (lhs.size() != rhs.size()) {
- return false;
- }
-
- if (lhs.data() == rhs.data()) {
- return true;
- }
-
- return std::equal(lhs.data(), lhs.data() + lhs.size(), rhs.data());
-}
-
-// AStyle ignore, not handling correctly below
-// *INDENT-OFF*
-/**
- * Equality operation between a Span and a reference to a C++ array.
- *
- * @param lhs Left side of the binary operation.
- * @param rhs Right side of the binary operation.
- *
- * @return True if elements in input have the same size and the same content and
- * false otherwise.
- */
-template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
-bool operator==(const Span<T, LhsExtent> &lhs, T (&rhs)[RhsExtent])
-{
- return lhs == Span<T>(rhs);
-}
-
-/**
- * Equality operation between a Span and a reference to a C++ array.
- *
- * @param lhs Left side of the binary operation.
- * @param rhs Right side of the binary operation.
- *
- * @return True if elements in input have the same size and the same content
- * and false otherwise.
- */
-template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
-bool operator==(T (&lhs)[LhsExtent], const Span<T, RhsExtent> &rhs)
-{
- return Span<T>(lhs) == rhs;
-}
-
-/**
- * Not equal operator
- *
- * @param lhs Left side of the binary operation.
- * @param rhs Right side of the binary operation.
- *
- * @return True if arrays in input do not have the same size or the same content
- * and false otherwise.
- *
- * @relates Span
- */
-template<typename T, typename U, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
-bool operator!=(const Span<T, LhsExtent> &lhs, const Span<U, RhsExtent> &rhs)
-{
- return !(lhs == rhs);
-}
-
-/**
- * Not Equal operation between a Span and a reference to a C++ array.
- *
- * @param lhs Left side of the binary operation.
- * @param rhs Right side of the binary operation.
- *
- * @return True if elements in input have the same size and the same content
- * and false otherwise.
- */
-template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
-bool operator!=(const Span<T, LhsExtent> &lhs, T (&rhs)[RhsExtent])
-{
- return !(lhs == Span<T, RhsExtent>(rhs));
-}
-
-/**
- * Not Equal operation between a Span and a reference to a C++ array.
- *
- * @param lhs Left side of the binary operation.
- * @param rhs Right side of the binary operation.
- *
- * @return True if elements in input have the same size and the same content
- * and false otherwise.
- */
-template<typename T, ptrdiff_t LhsExtent, ptrdiff_t RhsExtent>
-bool operator!=(T (&lhs)[LhsExtent], const Span<T, RhsExtent> &rhs)
-{
- return !(Span<T, LhsExtent>(lhs) == rhs);
-}
-
-/**
- * Generate a Span from a reference to a C/C++ array.
- *
- * @tparam T Type of elements held in elements.
- * @tparam Extent Number of items held in elements.
- *
- * @param elements The reference to the array viewed.
- *
- * @return The Span to elements.
- *
- * @note This helper avoids the typing of template parameter when Span is
- * created 'inline'.
- *
- * @relates Span
- */
-template<typename T, size_t Size>
-Span<T, Size> make_Span(T (&elements)[Size])
-{
- return Span<T, Size>(elements);
-}
-
-/**
- * Generate a Span from a pointer to a C/C++ array.
- *
- * @tparam Extent Number of items held in elements.
- * @tparam T Type of elements held in elements.
- *
- * @param elements The reference to the array viewed.
- *
- * @return The Span to elements.
- *
- * @note This helper avoids the typing of template parameter when Span is
- * created 'inline'.
- */
-template<ptrdiff_t Extent, typename T>
-Span<T, Extent> make_Span(T *elements)
-{
- return Span<T, Extent>(elements, Extent);
-}
-
-/**
- * Generate a Span from a C/C++ pointer and the size of the array.
- *
- * @tparam T Type of elements held in array_ptr.
- *
- * @param array_ptr The pointer to the array viewed.
- * @param array_size The number of T elements in the array.
- *
- * @return The Span to array_ptr with a size of array_size.
- *
- * @note This helper avoids the typing of template parameter when Span is
- * created 'inline'.
- *
- * @relates Span
- */
-template<typename T>
-Span<T> make_Span(T *array_ptr, ptrdiff_t array_size)
-{
- return Span<T>(array_ptr, array_size);
-}
-
-/**
- * Generate a Span to a const content from a reference to a C/C++ array.
- *
- * @tparam T Type of elements held in elements.
- * @tparam Extent Number of items held in elements.
- *
- * @param elements The array viewed.
- * @return The Span to elements.
- *
- * @note This helper avoids the typing of template parameter when Span is
- * created 'inline'.
- */
-template<typename T, size_t Extent>
-Span<const T, Extent> make_const_Span(const T (&elements)[Extent])
-{
- return Span<const T, Extent>(elements);
-}
-// *INDENT-ON*
-/**
- * Generate a Span to a const content from a pointer to a C/C++ array.
- *
- * @tparam Extent Number of items held in elements.
- * @tparam T Type of elements held in elements.
- *
- * @param elements The reference to the array viewed.
- *
- * @return The Span to elements.
- *
- * @note This helper avoids the typing of template parameter when Span is
- * created 'inline'.
- *
- * @relates Span
- */
-template<size_t Extent, typename T>
-Span<const T, Extent> make_const_Span(const T *elements)
-{
- return Span<const T, Extent>(elements, Extent);
-}
-
-/**
- * Generate a Span to a const content from a C/C++ pointer and the size of the
- * array.
- *
- * @tparam T Type of elements held in array_ptr.
- *
- * @param array_ptr The pointer to the array to viewed.
- * @param array_size The number of T elements in the array.
- *
- * @return The Span to array_ptr with a size of array_size.
- *
- * @note This helper avoids the typing of template parameter when Span is
- * created 'inline'.
- *
- * @relates Span
- */
-template<typename T>
-Span<const T> make_const_Span(T *array_ptr, size_t array_size)
-{
- return Span<const T>(array_ptr, array_size);
-}
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif /* MBED_PLATFORM_SPAN_H_ */
--- a/STM32F103C8T6_MPA/mbed/platform/Stream.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_STREAM_H
-#define MBED_STREAM_H
-
-#include "platform/platform.h"
-#include "platform/FileLike.h"
-#include "platform/FileHandle.h"
-#include "platform/NonCopyable.h"
-#include "mbed_toolchain.h"
-#include <cstdio>
-#include <cstdarg>
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_Stream Stream class
- * @{
- */
-
-extern void mbed_set_unbuffered_stream(std::FILE *_file);
-
-/** File stream
- *
- * @note Synchronization level: Set by subclass
- */
-class Stream : public FileLike, private NonCopyable<Stream> {
-
-public:
- Stream(const char *name = NULL);
- virtual ~Stream();
-
- int putc(int c);
- int puts(const char *s);
- int getc();
- char *gets(char *s, int size);
- int printf(const char *format, ...) MBED_PRINTF_METHOD(1, 2);
- int scanf(const char *format, ...) MBED_SCANF_METHOD(1, 2);
- int vprintf(const char *format, std::va_list args) MBED_PRINTF_METHOD(1, 0);
- int vscanf(const char *format, std::va_list args) MBED_SCANF_METHOD(1, 0);
-
- operator std::FILE *()
- {
- return _file;
- }
-
-protected:
- virtual int close();
- virtual ssize_t write(const void *buffer, size_t length);
- virtual ssize_t read(void *buffer, size_t length);
- virtual off_t seek(off_t offset, int whence);
- virtual off_t tell();
- virtual void rewind();
- virtual int isatty();
- virtual int sync();
- virtual off_t size();
-
- virtual int _putc(int c) = 0;
- virtual int _getc() = 0;
-
- std::FILE *_file;
-
- /** Acquire exclusive access to this object.
- */
- virtual void lock()
- {
- // Stub
- }
-
- /** Release exclusive access to this object.
- */
- virtual void unlock()
- {
- // Stub
- }
-};
-/**@}*/
-
-/**@}*/
-} // namespace mbed
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/platform/Transaction.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,89 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TRANSACTION_H
-#define MBED_TRANSACTION_H
-
-#include "platform/platform.h"
-#include "platform/FunctionPointer.h"
-
-namespace mbed {
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_Transaction Transaction class
- * @{
- */
-
-/** Transaction structure
- */
-typedef struct {
- void *tx_buffer; /**< Tx buffer */
- size_t tx_length; /**< Length of Tx buffer*/
- void *rx_buffer; /**< Rx buffer */
- size_t rx_length; /**< Length of Rx buffer */
- uint32_t event; /**< Event for a transaction */
- event_callback_t callback; /**< User's callback */
- uint8_t width; /**< Buffer's word width (8, 16, 32, 64) */
-} transaction_t;
-
-/** Transaction class defines a transaction.
- *
- * @note Synchronization level: Not protected
- */
-template<typename Class>
-class Transaction {
-public:
- Transaction(Class *tpointer, const transaction_t &transaction) : _obj(tpointer), _data(transaction)
- {
- }
-
- Transaction() : _obj(), _data()
- {
- }
-
- ~Transaction()
- {
- }
-
- /** Get object's instance for the transaction
- *
- * @return The object which was stored
- */
- Class *get_object()
- {
- return _obj;
- }
-
- /** Get the transaction
- *
- * @return The transaction which was stored
- */
- transaction_t *get_transaction()
- {
- return &_data;
- }
-
-private:
- Class *_obj;
- transaction_t _data;
-};
-/**@}*/
-
-/**@}*/
-}
-
-#endif
--- a/STM32F103C8T6_MPA/mbed/platform/critical.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_OLD_CRITICAL_H -#define MBED_OLD_CRITICAL_H - -#warning critical.h has been replaced by mbed_critical.h, please update to mbed_critical.h [since mbed-os-5.3] -#include "platform/mbed_critical.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_application.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017-2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_APPLICATION_H
-#define MBED_APPLICATION_H
-
-#include<stdint.h>
-
-#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7)\
- || defined(__CORTEX_M23) || defined(__CORTEX_A9)
-#define MBED_APPLICATION_SUPPORT 1
-#else
-#define MBED_APPLICATION_SUPPORT 0
-#endif
-
-#if MBED_APPLICATION_SUPPORT
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * Start the application at the given address. This function does
- * not return. It is the applications responsibility for flushing to
- * or powering down external components such as filesystems or
- * socket connections before calling this function. For Cortex-M
- * devices this function powers down generic system components such as
- * the NVIC and set the vector table to that of the new image followed
- * by jumping to the reset handler of the new image.
- *
- * @param address Starting address of next application to run
- */
-void mbed_start_application(uintptr_t address);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_assert.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,135 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_Assert Assert macros
- * @{
- */
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ASSERT_H
-#define MBED_ASSERT_H
-
-#include "mbed_preprocessor.h"
-#include "mbed_toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Internal mbed assert function which is invoked when MBED_ASSERT macro fails.
- * This function is active only if NDEBUG is not defined prior to including this
- * assert header file.
- * In case of MBED_ASSERT failing condition, error() is called with the assertation message.
- * @param expr Expression to be checked.
- * @param file File where assertation failed.
- * @param line Failing assertation line number.
- */
-MBED_NORETURN void mbed_assert_internal(const char *expr, const char *file, int line);
-
-#ifdef __cplusplus
-}
-#endif
-
-/** MBED_ASSERT
- * Declare runtime assertions: results in runtime error if condition is false
- *
- * @note
- * Use of MBED_ASSERT is limited to Debug and Develop builds.
- *
- * @code
- *
- * int Configure(serial_t *obj) {
- * MBED_ASSERT(obj);
- * }
- * @endcode
- */
-#ifdef NDEBUG
-#define MBED_ASSERT(expr) ((void)0)
-
-#else
-#define MBED_ASSERT(expr) \
-do { \
- if (!(expr)) { \
- mbed_assert_internal(#expr, __FILE__, __LINE__); \
- } \
-} while (0)
-#endif
-
-
-/** MBED_STATIC_ASSERT
- * Declare compile-time assertions, results in compile-time error if condition is false
- *
- * The assertion acts as a declaration that can be placed at file scope, in a
- * code block (except after a label), or as a member of a C++ class/struct/union.
- *
- * @note
- * Use of MBED_STATIC_ASSERT as a member of a struct/union is limited:
- * - In C++, MBED_STATIC_ASSERT is valid in class/struct/union scope.
- * - In C, MBED_STATIC_ASSERT is not valid in struct/union scope, and
- * MBED_STRUCT_STATIC_ASSERT is provided as an alternative that is valid
- * in C and C++ class/struct/union scope.
- *
- * @code
- * MBED_STATIC_ASSERT(MBED_LIBRARY_VERSION >= 120,
- * "The mbed library must be at least version 120");
- *
- * int main() {
- * MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char),
- * "An int must be larger than a char");
- * }
- * @endcode
- */
-#if defined(__cplusplus) && (__cplusplus >= 201103L || __cpp_static_assert >= 200410L)
-#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
-#elif !defined(__cplusplus) && __STDC_VERSION__ >= 201112L
-#define MBED_STATIC_ASSERT(expr, msg) _Static_assert(expr, msg)
-#elif defined(__cplusplus) && defined(__GNUC__) && defined(__GXX_EXPERIMENTAL_CXX0X__) \
- && (__GNUC__*100 + __GNUC_MINOR__) > 403L
-#define MBED_STATIC_ASSERT(expr, msg) __extension__ static_assert(expr, msg)
-#elif !defined(__cplusplus) && defined(__GNUC__) && !defined(__CC_ARM) \
- && (__GNUC__*100 + __GNUC_MINOR__) > 406L
-#define MBED_STATIC_ASSERT(expr, msg) __extension__ _Static_assert(expr, msg)
-#elif defined(__ICCARM__)
-#define MBED_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
-#else
-#define MBED_STATIC_ASSERT(expr, msg) \
- enum {MBED_CONCAT(MBED_ASSERTION_AT_, __LINE__) = sizeof(char[(expr) ? 1 : -1])}
-#endif
-
-/** MBED_STRUCT_STATIC_ASSERT
- * Declare compile-time assertions, results in compile-time error if condition is false
- *
- * Unlike MBED_STATIC_ASSERT, MBED_STRUCT_STATIC_ASSERT can and must be used
- * as a member of a C/C++ class/struct/union.
- *
- * @code
- * struct thing {
- * MBED_STATIC_ASSERT(2 + 2 == 4,
- * "Hopefully the universe is mathematically consistent");
- * };
- * @endcode
- */
-#define MBED_STRUCT_STATIC_ASSERT(expr, msg) int : (expr) ? 0 : -1
-
-
-#endif
-
-/**@}*/
-
-/**@}*/
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_crash_data_offsets.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,58 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CRASH_DATA_INFO_H
-#define MBED_CRASH_DATA_INFO_H
-
-#include "platform/mbed_retarget.h"
-#include "platform/mbed_toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED
-#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-extern uint32_t Image$$RW_m_crash_data$$ZI$$Base[];
-extern uint32_t Image$$RW_m_crash_data$$ZI$$Size;
-#define __CRASH_DATA_RAM_START__ Image$$RW_m_crash_data$$ZI$$Base
-#define __CRASH_DATA_RAM_SIZE__ Image$$RW_m_crash_data$$ZI$$Size
-#elif defined(__ICCARM__)
-extern uint32_t __CRASH_DATA_RAM_START__[];
-extern uint32_t __CRASH_DATA_RAM_END__[];
-#define __CRASH_DATA_RAM_SIZE__ (__CRASH_DATA_RAM_END__ - __CRASH_DATA_RAM_START__)
-#elif defined(__GNUC__)
-extern uint32_t __CRASH_DATA_RAM_START__[];
-extern uint32_t __CRASH_DATA_RAM_END__[];
-#define __CRASH_DATA_RAM_SIZE__ (__CRASH_DATA_RAM_END__ - __CRASH_DATA_RAM_START__)
-#endif /* defined(__CC_ARM) */
-
-/* Offset definitions for context capture */
-#define FAULT_CONTEXT_OFFSET (0x0)
-#define FAULT_CONTEXT_SIZE (0x80 / 4) //32 words(128 bytes) for Fault Context
-#define ERROR_CONTEXT_OFFSET (FAULT_CONTEXT_OFFSET + FAULT_CONTEXT_SIZE)
-#define ERROR_CONTEXT_SIZE (0x80 / 4) //32 words(128 bytes) bytes for Error Context
-#define FAULT_CONTEXT_LOCATION (__CRASH_DATA_RAM_START__ + FAULT_CONTEXT_OFFSET)
-#define ERROR_CONTEXT_LOCATION (__CRASH_DATA_RAM_START__ + ERROR_CONTEXT_OFFSET)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_critical.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,437 +0,0 @@
-
-/*
- * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __MBED_UTIL_CRITICAL_H__
-#define __MBED_UTIL_CRITICAL_H__
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_critical critical section function
- * @{
- */
-
-/** Determine the current interrupts enabled state
- *
- * This function can be called to determine whether or not interrupts are currently enabled.
- * @note
- * NOTE:
- * This function works for both cortex-A and cortex-M, although the underlying implementation
- * differs.
- * @return true if interrupts are enabled, false otherwise
- */
-bool core_util_are_interrupts_enabled(void);
-
-/** Determine if this code is executing from an interrupt
- *
- * This function can be called to determine if the code is running on interrupt context.
- * @note
- * NOTE:
- * This function works for both cortex-A and cortex-M, although the underlying implementation
- * differs.
- * @return true if in an isr, false otherwise
- */
-bool core_util_is_isr_active(void);
-
-/** Mark the start of a critical section
- *
- * This function should be called to mark the start of a critical section of code.
- * @note
- * NOTES:
- * 1) The use of this style of critical section is targetted at C based implementations.
- * 2) These critical sections can be nested.
- * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
- * section) will be preserved on exit from the section.
- * 4) This implementation will currently only work on code running in privileged mode.
- */
-void core_util_critical_section_enter(void);
-
-/** Mark the end of a critical section
- *
- * This function should be called to mark the end of a critical section of code.
- * @note
- * NOTES:
- * 1) The use of this style of critical section is targetted at C based implementations.
- * 2) These critical sections can be nested.
- * 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
- * section) will be preserved on exit from the section.
- * 4) This implementation will currently only work on code running in privileged mode.
- */
-void core_util_critical_section_exit(void);
-
-/**
- * Determine if we are currently in a critical section
- *
- * @return true if in a critical section, false otherwise.
- */
-bool core_util_in_critical_section(void);
-
-/**
- * A lock-free, primitive atomic flag.
- *
- * Emulate C11's atomic_flag. The flag is initially in an indeterminate state
- * unless explicitly initialized with CORE_UTIL_ATOMIC_FLAG_INIT.
- */
-typedef struct core_util_atomic_flag {
- uint8_t _flag;
-} core_util_atomic_flag;
-
-/**
- * Initializer for a core_util_atomic_flag.
- *
- * Example:
- * ~~~
- * core_util_atomic_flag in_progress = CORE_UTIL_ATOMIC_FLAG_INIT;
- * ~~~
- */
-#define CORE_UTIL_ATOMIC_FLAG_INIT { 0 }
-
-/**
- * Atomic test and set.
- *
- * Atomically tests then sets the flag to true, returning the previous value.
- *
- * @param flagPtr Target flag being tested and set.
- * @return The previous value.
- */
-bool core_util_atomic_flag_test_and_set(volatile core_util_atomic_flag *flagPtr);
-
-/**
- * Atomic clear.
- *
- * @param flagPtr Target flag being cleared.
- */
-void core_util_atomic_flag_clear(volatile core_util_atomic_flag *flagPtr);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param ptr The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- * expected current value of the data being set atomically.
- * The computed 'desiredValue' should be a function of this current value.
- * @note: This is an in-out parameter. In the
- * failure case of atomic_cas (where the
- * destination isn't set), the pointee of expectedCurrentValue is
- * updated with the current value.
- * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
- *
- * @return true if the memory location was atomically
- * updated with the desired value (after verifying
- * that it contained the expectedCurrentValue),
- * false otherwise. In the failure case,
- * exepctedCurrentValue is updated with the new
- * value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- * if *p != *old {
- * *old = *p
- * return false
- * }
- * *p = new
- * return true
- * }
- *
- * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is instead updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- * done = false
- * value = *p // This fetch operation need not be atomic.
- * while not done {
- * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- * }
- * return value + a
- * }
- *
- * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
- * always succeeds if the current value is expected, as per the pseudocode
- * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
- */
-bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param ptr The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- * expected current value of the data being set atomically.
- * The computed 'desiredValue' should be a function of this current value.
- * @note: This is an in-out parameter. In the
- * failure case of atomic_cas (where the
- * destination isn't set), the pointee of expectedCurrentValue is
- * updated with the current value.
- * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
- *
- * @return true if the memory location was atomically
- * updated with the desired value (after verifying
- * that it contained the expectedCurrentValue),
- * false otherwise. In the failure case,
- * exepctedCurrentValue is updated with the new
- * value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- * if *p != *old {
- * *old = *p
- * return false
- * }
- * *p = new
- * return true
- * }
- *
- * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is instead updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- * done = false
- * value = *p // This fetch operation need not be atomic.
- * while not done {
- * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- * }
- * return value + a
- * }
- *
- * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
- * always succeeds if the current value is expected, as per the pseudocode
- * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
- */
-bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param ptr The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- * expected current value of the data being set atomically.
- * The computed 'desiredValue' should be a function of this current value.
- * @note: This is an in-out parameter. In the
- * failure case of atomic_cas (where the
- * destination isn't set), the pointee of expectedCurrentValue is
- * updated with the current value.
- * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
- *
- * @return true if the memory location was atomically
- * updated with the desired value (after verifying
- * that it contained the expectedCurrentValue),
- * false otherwise. In the failure case,
- * exepctedCurrentValue is updated with the new
- * value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- * if *p != *old {
- * *old = *p
- * return false
- * }
- * *p = new
- * return true
- * }
- *
- * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is instead updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- * done = false
- * value = *p // This fetch operation need not be atomic.
- * while not done {
- * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- * }
- * return value + a
- *
- * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
- * always succeeds if the current value is expected, as per the pseudocode
- * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
- * }
- */
-bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
-
-/**
- * Atomic compare and set. It compares the contents of a memory location to a
- * given value and, only if they are the same, modifies the contents of that
- * memory location to a given new value. This is done as a single atomic
- * operation. The atomicity guarantees that the new value is calculated based on
- * up-to-date information; if the value had been updated by another thread in
- * the meantime, the write would fail due to a mismatched expectedCurrentValue.
- *
- * Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
- * you to the article on compare-and swap].
- *
- * @param ptr The target memory location.
- * @param[in,out] expectedCurrentValue A pointer to some location holding the
- * expected current value of the data being set atomically.
- * The computed 'desiredValue' should be a function of this current value.
- * @note: This is an in-out parameter. In the
- * failure case of atomic_cas (where the
- * destination isn't set), the pointee of expectedCurrentValue is
- * updated with the current value.
- * @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
- *
- * @return true if the memory location was atomically
- * updated with the desired value (after verifying
- * that it contained the expectedCurrentValue),
- * false otherwise. In the failure case,
- * exepctedCurrentValue is updated with the new
- * value of the target memory location.
- *
- * pseudocode:
- * function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
- * if *p != *old {
- * *old = *p
- * return false
- * }
- * *p = new
- * return true
- * }
- *
- * @note: In the failure case (where the destination isn't set), the value
- * pointed to by expectedCurrentValue is instead updated with the current value.
- * This property helps writing concise code for the following incr:
- *
- * function incr(p : pointer to int, a : int) returns int {
- * done = false
- * value = *p // This fetch operation need not be atomic.
- * while not done {
- * done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
- * }
- * return value + a
- * }
- *
- * @note: This corresponds to the C11 "atomic_compare_exchange_strong" - it
- * always succeeds if the current value is expected, as per the pseudocode
- * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
- */
-bool core_util_atomic_cas_ptr(void *volatile *ptr, void **expectedCurrentValue, void *desiredValue);
-
-/**
- * Atomic increment.
- * @param valuePtr Target memory location being incremented.
- * @param delta The amount being incremented.
- * @return The new incremented value.
- */
-uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta);
-
-/**
- * Atomic increment.
- * @param valuePtr Target memory location being incremented.
- * @param delta The amount being incremented.
- * @return The new incremented value.
- */
-uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta);
-
-/**
- * Atomic increment.
- * @param valuePtr Target memory location being incremented.
- * @param delta The amount being incremented.
- * @return The new incremented value.
- */
-uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta);
-
-/**
- * Atomic increment.
- * @param valuePtr Target memory location being incremented.
- * @param delta The amount being incremented in bytes.
- * @return The new incremented value.
- *
- * @note The type of the pointer argument is not taken into account
- * and the pointer is incremented by bytes.
- */
-void *core_util_atomic_incr_ptr(void *volatile *valuePtr, ptrdiff_t delta);
-
-/**
- * Atomic decrement.
- * @param valuePtr Target memory location being decremented.
- * @param delta The amount being decremented.
- * @return The new decremented value.
- */
-uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta);
-
-/**
- * Atomic decrement.
- * @param valuePtr Target memory location being decremented.
- * @param delta The amount being decremented.
- * @return The new decremented value.
- */
-uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta);
-
-/**
- * Atomic decrement.
- * @param valuePtr Target memory location being decremented.
- * @param delta The amount being decremented.
- * @return The new decremented value.
- */
-uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta);
-
-/**
- * Atomic decrement.
- * @param valuePtr Target memory location being decremented.
- * @param delta The amount being decremented in bytes.
- * @return The new decremented value.
- *
- * @note The type of the pointer argument is not taken into account
- * and the pointer is decremented by bytes
- */
-void *core_util_atomic_decr_ptr(void *volatile *valuePtr, ptrdiff_t delta);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-/**@}*/
-
-/**@}*/
-
-#endif // __MBED_UTIL_CRITICAL_H__
-
-
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_debug.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,85 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_debug Debug functions
- * @{
- */
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEBUG_H
-#define MBED_DEBUG_H
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#include <stdarg.h>
-#endif
-#include "mbed_toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static inline void debug(const char *format, ...) MBED_PRINTF(1, 2);
-static inline void debug_if(int condition, const char *format, ...) MBED_PRINTF(2, 3);
-
-/** Output a debug message
- *
- * @param format printf-style format string, followed by variables
- */
-static inline void debug(const char *format, ...)
-{
-#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
- va_list args;
- va_start(args, format);
- vfprintf(stderr, format, args);
- va_end(args);
-#endif
-}
-
-
-/** Conditionally output a debug message
- *
- * NOTE: If the condition is constant false (== 0) and the compiler optimization
- * level is greater than 0, then the whole function will be compiled away.
- *
- * @param condition output only if condition is true (!= 0)
- * @param format printf-style format string, followed by variables
- */
-static inline void debug_if(int condition, const char *format, ...)
-{
-#if DEVICE_STDIO_MESSAGES && !defined(NDEBUG)
- if (condition) {
- va_list args;
- va_start(args, format);
- vfprintf(stderr, format, args);
- va_end(args);
- }
-#endif
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/**@}*/
-
-/**@}*/
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_error.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1158 +0,0 @@
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_error Error functions
- * @{
- */
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ERROR_H
-#define MBED_ERROR_H
-
-#include "platform/mbed_retarget.h"
-#include "platform/mbed_toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Define this macro to include filenames in error context. For release builds, do not include filename to save memory.
- * MBED_PLATFORM_CONF_ERROR_FILENAME_CAPTURE_ENABLED
- */
-
-/** Define this macro to enable error history
- * MBED_PLATFORM_CONF_ERROR_HIST_ENABLED
- */
-
-#ifndef MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
-#define MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN 16
-#else //MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
-#if MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN > 64
-//We have to limit this to 64 bytes since we use mbed_error_printf for error reporting
-//and mbed_error_vprintf uses 128bytes internal buffer which may not be sufficient for anything
-//longer that 64 bytes with the current implementation.
-#error "Unsupported error filename buffer length detected, max supported length is 64 chars. Please change MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN or max-error-filename-len in configuration."
-#endif
-#endif
-
-#define MBED_ERROR_STATUS_CODE_MASK (0x0000FFFF)
-#define MBED_ERROR_STATUS_CODE_POS (0)
-#define MBED_ERROR_STATUS_CODE_FIELD_SIZE (16)
-
-#define MBED_ERROR_STATUS_MODULE_MASK (0x00FF0000)
-#define MBED_ERROR_STATUS_MODULE_POS (16)
-#define MBED_ERROR_STATUS_MODULE_FIELD_SIZE (8)
-
-#define MBED_ERROR_STATUS_TYPE_MASK (0x60000000)
-#define MBED_ERROR_STATUS_TYPE_POS (29)
-#define MBED_ERROR_STATUS_TYPE_FIELD_SIZE (2)
-
-/* mbed_error_status_t Status Encoding */
-//|31(1 bit) Always Negative|30-29(2 bits) |28-24 | 23-16(8 bits) | 15-0(16 bits) |
-//|-1 |TYPE |(unused/reserved) | MODULE TYPE | ERROR CODE |
-
-#define MAKE_MBED_ERROR(type, module, error_code) (mbed_error_status_t) \
- ((0x80000000) | \
- (MBED_ERROR_STATUS_CODE_MASK & (error_code << MBED_ERROR_STATUS_CODE_POS)) | \
- (MBED_ERROR_STATUS_MODULE_MASK & (module << MBED_ERROR_STATUS_MODULE_POS)) | \
- (MBED_ERROR_STATUS_TYPE_MASK & (type << MBED_ERROR_STATUS_TYPE_POS)))
-
-#define MBED_GET_ERROR_TYPE( error_status ) ((error_status & MBED_ERROR_STATUS_TYPE_MASK) >> MBED_ERROR_STATUS_TYPE_POS)
-#define MBED_GET_ERROR_MODULE( error_status ) ((error_status & MBED_ERROR_STATUS_MODULE_MASK) >> MBED_ERROR_STATUS_MODULE_POS)
-#define MBED_GET_ERROR_CODE( error_status ) (int)((MBED_GET_ERROR_TYPE( error_status ) == MBED_ERROR_TYPE_POSIX)?(-error_status):((error_status & MBED_ERROR_STATUS_CODE_MASK) >> MBED_ERROR_STATUS_CODE_POS))
-
-/** mbed_error_status_t description
- *
- * mbed_error_status_t type represents the error status values under MbedOS. mbed_error_status_t values are signed integers and always be negative.\n
- * Internally its encoded as below with bit-fields representing error type, module and error code:\n\n
- * mbed_error_status_t Status Encoding:\n
- *
- \verbatim
- | 31 Always Negative | 30-29(2 bits) | 28-24 | 23-16(8 bits) | 15-0(16 bits) |
- | -1 | TYPE | (unused/reserved) | MODULE TYPE | ERROR CODE |
- \endverbatim
- *
- * The error status value range for each error type is as follows:\n
- * POSIX Error Status-es - 0xFFFFFFFF to 0xFFFFFF01(-1 -255) - This corresponds to POSIX error codes represented as negative.\n
- * System Error Status-es - 0x80XX0100 to 0x80XX0FFF - This corresponds to System error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n
- * Custom Error Status-es - 0xA0XX1000 to 0xA0XXFFFF - This corresponds to Custom error codes range(all values are negative). Bits 23-16 will be module type(marked with XX)\n\n
- *
- * The ERROR CODE(values encoded into ERROR CODE bit-field in mbed_error_status_t) value range for each error type is also separated as below:\n
- * POSIX Error Codes - 1 to 255.\n
- * System Error Codes - 256 to 4095.\n
- * Custom Error Codes - 4096 to 65535.\n
- *
- * @note POSIX error codes are always encoded as negative of their actual value. For example, EPERM is encoded as -EPERM.
- * And, the MODULE TYPE for POSIX error codes are always encoded as MBED_MODULE_UNKNOWN.\n
- * This is to enable easy injection of POSIX error codes into MbedOS error handling system without altering the actual POSIX error values.\n
- * Accordingly, POSIX error codes are represented as -1 to -255 under MbedOS error status representation.
- */
-typedef int mbed_error_status_t;
-
-/**
- * Macro for defining a POSIX error status. This macro is mainly used to define POSIX error values in mbed_error_code_t enumeration.
- * @param error_name Name of the error without the ERROR_ prefix
- * @param error_code Error code value to be used, must be between 1 and 255(inclusive).
- *
- */
-#define MBED_DEFINE_POSIX_ERROR( error_name, error_code ) \
- MBED_ERROR_CODE_##error_name = error_code, \
- MBED_ERROR_##error_name = -(MBED_POSIX_ERROR_BASE + error_code)
-
-/**
- * Macro for defining a System error status. This macro is used to define System error values in mbed_error_code_t enumeration.
- * @param error_name Name of the error without the ERROR_ prefix
- * @param error_code Error code value to be used, must be between 256 and 4096(inclusive).
- *
- */
-#define MBED_DEFINE_SYSTEM_ERROR( error_name, error_code ) \
- MBED_ERROR_CODE_##error_name = MBED_SYSTEM_ERROR_BASE + error_code, \
- MBED_ERROR_##error_name = MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_##error_name)
-
-/**
- * Macro for defining a Custom error status. This macro is used to define custom error values in mbed_error_code_t enumeration.
- * @param error_name Name of the error without the ERROR_ prefix
- * @param error_code Error code value to be used, must be between 4097 and 65535(inclusive).
- *
- */
-#define MBED_DEFINE_CUSTOM_ERROR( error_name, error_code ) \
- MBED_ERROR_CODE_##error_name = MBED_CUSTOM_ERROR_BASE + error_code, \
- MBED_ERROR_##error_name = MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, MBED_MODULE_UNKNOWN, MBED_ERROR_CODE_##error_name)
-
-
-/**
- * Macros for setting a system warning. These macros will log the error, Its a wrapper for calling mbed_warning API.
- * There are 2 versions of this macro. MBED_WARNING takes status and message. MBED_WARNING1 takes an additional context specific argument
- * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
- * @param error_msg The error message to be printed out to STDIO/Serial.
- * @param error_value Value associated with the error status. This would depend on error code/error scenario.
- *
- * @code
- *
- * MBED_WARNING( ERROR_INVALID_SIZE, "MyDriver: Invalid size in read" )
- * MBED_WARNING1( ERROR_INVALID_SIZE, "MyDriver: Invalid size in read", size_val )
- *
- * @endcode
- * @note The macro calls mbed_warning API with filename and line number info without caller explicitly passing them.
- * Since this macro is a wrapper for mbed_warning API callers should process the return value from this macro which is the return value from calling mbed_error API.
- *
- */
-#ifdef NDEBUG
-#define MBED_WARNING1( error_status, error_msg, error_value ) mbed_warning( error_status, (const char *)NULL, (uint32_t)error_value, NULL, 0 )
-#define MBED_WARNING( error_status, error_msg ) mbed_warning( error_status, (const char *)NULL, (uint32_t)0, NULL, 0 )
-#else //NDEBUG
-#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
-#define MBED_WARNING1( error_status, error_msg, error_value ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)error_value, (const char *)MBED_FILENAME, __LINE__ )
-#define MBED_WARNING( error_status, error_msg ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)0 , (const char *)MBED_FILENAME, __LINE__ )
-#else //MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
-#define MBED_WARNING1( error_status, error_msg, error_value ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)error_value, NULL, 0 )
-#define MBED_WARNING( error_status, error_msg ) mbed_warning( error_status, (const char *)error_msg, (uint32_t)0, NULL, 0 )
-#endif
-#endif
-
-/**
- * Macros for setting a fatal system error. These macros will log the error, prints the error report and halts the system. Its a wrapper for calling mbed_error API.
- * There are 2 versions of this macro. MBED_ERROR takes status and message. MBED_ERROR1 takes an additional context specific argument
- * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
- * @param error_msg The error message to be printed out to STDIO/Serial.
- * @param error_value Value associated with the error status. This would depend on error code/error scenario. Only available with MBED_ERROR1
- * @return Does not return
- *
- * @code
- *
- * MBED_ERROR( MBED_ERROR_MUTEX_LOCK_FAILED, "MyDriver: Can't lock driver Mutex" )
- * MBED_ERROR1( MBED_ERROR_MUTEX_LOCK_FAILED, "MyDriver: Can't lock driver Mutex", &my_mutex )
- *
- * @endcode
- * @note The macro calls mbed_error API with filename and line number info without caller explicitly passing them.
- * Since this macro is a wrapper for mbed_error API callers should process the return value from this macro which is the return value from calling mbed_error API.
- *
- */
-#ifdef NDEBUG
-#define MBED_ERROR1( error_status, error_msg, error_value ) mbed_error( error_status, (const char *)NULL, (uint32_t)error_value, NULL, 0 )
-#define MBED_ERROR( error_status, error_msg ) mbed_error( error_status, (const char *)NULL, (uint32_t)0 , NULL, 0 )
-#else //NDEBUG
-#if MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
-#define MBED_ERROR1( error_status, error_msg, error_value ) mbed_error( error_status, (const char *)error_msg, (uint32_t)error_value, (const char *)MBED_FILENAME, __LINE__ )
-#define MBED_ERROR( error_status, error_msg ) mbed_error( error_status, (const char *)error_msg, (uint32_t)0 , (const char *)MBED_FILENAME, __LINE__ )
-#else //MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED
-#define MBED_ERROR1( error_status, error_msg, error_value ) mbed_error( error_status, (const char *)error_msg, (uint32_t)error_value, NULL, 0 )
-#define MBED_ERROR( error_status, error_msg ) mbed_error( error_status, (const char *)error_msg, (uint32_t)0 , NULL, 0 )
-#endif
-#endif
-
-//Error Type definition
-/** mbed_error_type_t definition
- * @note
- * This enumeration defines the Error types supported. The value of these enum values will be encoded into mbed_error_status_t TYPE field.\n
- * See mbed_error_status_t description for more info.\n
- * MBED_ERROR_TYPE_SYSTEM - Used to indicate that the error status is of System defined Error type.\n
- * MBED_ERROR_TYPE_CUSTOM - Used to indicate that the error status is of Custom defined Error type.\n
- * MBED_ERROR_TYPE_POSIX - Used to indicate that the error status is of POSIX error type.\n
- *
- */
-typedef enum _mbed_error_type_t {
- MBED_ERROR_TYPE_SYSTEM = 0,
- MBED_ERROR_TYPE_CUSTOM = 1,
- //2 is reserved
- //Use 3 for POSIX because we are mapping -1 to -255 to POSIX error codes
- //and thus we must use 3 to match the type bits in error status representation which are from 0xFFFFFFFF to 0xFFFFFF00
- MBED_ERROR_TYPE_POSIX = 3
-} mbed_error_type_t;
-
-//Module type/id definitions
-/** mbed_module_type_t definition
- * @note
- * This enumeration defines the module types. The value of these enum values will be encoded into mbed_error_status_t MODULE field.\n\n
- * See mbed_error_status_t description for more info.\n
- * MBED_MODULE_UNKNOWN - This module type can be used if caller of the mbed_error/mbed_warning doesn't know who is the actual originator of the error.\n
- * Other module values can be used to provide more info on who/where the error originated from.\n\n
- * For example, if I2C driver is the component originating the error you can use MBED_MODULE_DRIVER_I2C to provide more info.\n
- * Its used in call to MBED_MAKE_ERROR/MBED_MAKE_SYSTEM_ERROR/MBED_MAKE_CUSTOM_ERROR macros.\n
- *
- * @code
- * Example: mbed_error_status_t i2c_driver_error = MBED_MAKE_ERROR( MBED_MODULE_DRIVER_I2C, MBED_ERROR_CONFIG_UNSUPPORTED );
- * @endcode
- *
- * @note
- * \n Below are the module code mappings:\n
- \verbatim
- MBED_MODULE_APPLICATION 0 Application
- MBED_MODULE_PLATFORM 1 Platform
- MBED_MODULE_KERNEL 2 RTX Kernel
- MBED_MODULE_NETWORK_STACK 3 Network stack
- MBED_MODULE_HAL 4 HAL - Hardware Abstraction Layer
- MBED_MODULE_MEMORY_SUBSYSTEM 5 Memory Subsystem
- MBED_MODULE_FILESYSTEM 6 Filesystem
- MBED_MODULE_BLOCK_DEVICE 7 Block device
- MBED_MODULE_DRIVER 8 Driver
- MBED_MODULE_DRIVER_SERIAL 9 Serial Driver
- MBED_MODULE_DRIVER_RTC 10 RTC Driver
- MBED_MODULE_DRIVER_I2C 11 I2C Driver
- MBED_MODULE_DRIVER_SPI 12 SPI Driver
- MBED_MODULE_DRIVER_GPIO 13 GPIO Driver
- MBED_MODULE_DRIVER_ANALOG 14 Analog Driver
- MBED_MODULE_DRIVER_DIGITAL 15 DigitalIO Driver
- MBED_MODULE_DRIVER_CAN 16 CAN Driver
- MBED_MODULE_DRIVER_ETHERNET 17 Ethernet Driver
- MBED_MODULE_DRIVER_CRC 18 CRC Module
- MBED_MODULE_DRIVER_PWM 19 PWM Driver
- MBED_MODULE_DRIVER_QSPI 20 QSPI Driver
- MBED_MODULE_DRIVER_USB 21 USB Driver
- MBED_MODULE_TARGET_SDK 22 SDK
- MBED_MODULE_BLE 23 BLE
- MBED_MODULE_NETWORK_STATS 24 Network Statistics
-
- MBED_MODULE_UNKNOWN 255 Unknown module
- \endverbatim
- *
- */
-typedef enum _mbed_module_type {
- MBED_MODULE_APPLICATION = 0,
- MBED_MODULE_PLATFORM,
- MBED_MODULE_KERNEL,
- MBED_MODULE_NETWORK_STACK,
- MBED_MODULE_HAL,
- MBED_MODULE_MEMORY_SUBSYSTEM,
- MBED_MODULE_FILESYSTEM,
- MBED_MODULE_BLOCK_DEVICE,
- MBED_MODULE_DRIVER,
- MBED_MODULE_DRIVER_SERIAL,
- MBED_MODULE_DRIVER_RTC,
- MBED_MODULE_DRIVER_I2C,
- MBED_MODULE_DRIVER_SPI,
- MBED_MODULE_DRIVER_GPIO,
- MBED_MODULE_DRIVER_ANALOG,
- MBED_MODULE_DRIVER_DIGITAL,
- MBED_MODULE_DRIVER_CAN,
- MBED_MODULE_DRIVER_ETHERNET,
- MBED_MODULE_DRIVER_CRC,
- MBED_MODULE_DRIVER_PWM,
- MBED_MODULE_DRIVER_QSPI,
- MBED_MODULE_DRIVER_USB,
- MBED_MODULE_TARGET_SDK,
- MBED_MODULE_BLE,
- MBED_MODULE_NETWORK_STATS,
- /* Add More entities here as required */
-
- MBED_MODULE_UNKNOWN = 255,
- MBED_MODULE_MAX = MBED_MODULE_UNKNOWN
-} mbed_module_type_t;
-
-//Use MBED_SUCCESS(=0) or any positive number for successful returns
-#define MBED_SUCCESS 0
-
-#define MBED_POSIX_ERROR_BASE 0
-#define MBED_SYSTEM_ERROR_BASE 256
-#define MBED_CUSTOM_ERROR_BASE 4096
-
-//Error Code definitions
-/** mbed_error_code_t definition
- *
- * mbed_error_code_t enumeration defines the Error codes and Error status values for MBED_MODULE_UNKNOWN.\n
- * It defines all of POSIX Error Codes/Statuses and Mbed System Error Codes/Statuses.\n\n
- *
- * @note
- * POSIX Error codes are defined using the macro MBED_DEFINE_POSIX_ERROR\n
- * For example MBED_DEFINE_POSIX_ERROR( EPERM, EPERM ). This effectively defines the following values:\n
- * ERROR_CODE_EPERM = EPERM\n
- * ERROR_EPERM = -EPERM\n
- *
- * POSIX Error codes are defined using the macro MBED_DEFINE_POSIX_ERROR\n
- * For example MBED_DEFINE_POSIX_ERROR( EPERM, EPERM ). This macro defines the following values:\n
- * ERROR_CODE_EPERM = MBED_POSIX_ERROR_BASE+EPERM\n
- * ERROR_EPERM = -(MBED_POSIX_ERROR_BASE+EPERM)\n
- * Its effectively equivalent to:\n
- * ERROR_CODE_EPERM = 1\n
- * ERROR_EPERM = -1\n
- * All POSIX error codes currently supported by MbedOS(defined in mbed_retarget.h) are defined using the MBED_DEFINE_POSIX_ERROR macro.\n\n
- * Below are the POSIX error codes and the description:\n
- * \verbatim
- EPERM 1 Operation not permitted
- ENOENT 2 No such file or directory
- ESRCH 3 No such process
- EINTR 4 Interrupted system call
- EIO 5 I/O error
- ENXIO 6 No such device or address
- E2BIG 7 Argument list too long
- ENOEXEC 8 Exec format error
- EBADF 9 Bad file number
- ECHILD 10 No child processes
- EAGAIN 11 Try again
- ENOMEM 12 Out of memory
- EACCES 13 Permission denied
- EFAULT 14 Bad address
- ENOTBLK 15 Block device required
- EBUSY 16 Device or resource busy
- EEXIST 17 File exists
- EXDEV 18 Cross-device link
- ENODEV 19 No such device
- ENOTDIR 20 Not a directory
- EISDIR 21 Is a directory
- EINVAL 22 Invalid argument
- ENFILE 23 File table overflow
- EMFILE 24 Too many open files
- ENOTTY 25 Not a typewriter
- ETXTBSY 26 Text file busy
- EFBIG 27 File too large
- ENOSPC 28 No space left on device
- ESPIPE 29 Illegal seek
- EROFS 30 Read-only file system
- EMLINK 31 Too many links
- EPIPE 32 Broken pipe
- EDOM 33 Math argument out of domain of func
- ERANGE 34 Math result not representable
- EDEADLK 35 Resource deadlock would occur
- ENAMETOOLONG 36 File name too long
- ENOLCK 37 No record locks available
- ENOSYS 38 Function not implemented
- ENOTEMPTY 39 Directory not empty
- ELOOP 40 Too many symbolic links encountered
- EWOULDBLOCK EAGAIN Operation would block
- ENOMSG 42 No message of desired type
- EIDRM 43 Identifier removed
- ECHRNG 44 Channel number out of range
- EL2NSYNC 45 Level 2 not synchronized
- EL3HLT 46 Level 3 halted
- EL3RST 47 Level 3 reset
- ELNRNG 48 Link number out of range
- EUNATCH 49 Protocol driver not attached
- ENOCSI 50 No CSI structure available
- EL2HLT 51 Level 2 halted
- EBADE 52 Invalid exchange
- EBADR 53 Invalid request descriptor
- EXFULL 54 Exchange full
- ENOANO 55 No anode
- EBADRQC 56 Invalid request code
- EBADSLT 57 Invalid slot
- EDEADLOCK EDEADLK Resource deadlock would occur
- EBFONT 59 Bad font file format
- ENOSTR 60 Device not a stream
- ENODATA 61 No data available
- ETIME 62 Timer expired
- ENOSR 63 Out of streams resources
- ENONET 64 Machine is not on the network
- ENOPKG 65 Package not installed
- EREMOTE 66 Object is remote
- ENOLINK 67 Link has been severed
- EADV 68 Advertise error
- ESRMNT 69 Srmount error
- ECOMM 70 Communication error on send
- EPROTO 71 Protocol error
- EMULTIHOP 72 Multihop attempted
- EDOTDOT 73 RFS specific error
- EBADMSG 74 Not a data message
- EOVERFLOW 75 Value too large for defined data type
- ENOTUNIQ 76 Name not unique on network
- EBADFD 77 File descriptor in bad state
- EREMCHG 78 Remote address changed
- ELIBACC 79 Can not access a needed shared library
- ELIBBAD 80 Accessing a corrupted shared library
- ELIBSCN 81 .lib section in a.out corrupted
- ELIBMAX 82 Attempting to link in too many shared libraries
- ELIBEXEC 83 Cannot exec a shared library directly
- EILSEQ 84 Illegal byte sequence
- ERESTART 85 Interrupted system call should be restarted
- ESTRPIPE 86 Streams pipe error
- EUSERS 87 Too many users
- ENOTSOCK 88 Socket operation on non-socket
- EDESTADDRREQ 89 Destination address required
- EMSGSIZE 90 Message too long
- EPROTOTYPE 91 Protocol wrong type for socket
- ENOPROTOOPT 92 Protocol not available
- EPROTONOSUPPORT 93 Protocol not supported
- ESOCKTNOSUPPORT 94 Socket type not supported
- EOPNOTSUPP 95 Operation not supported on transport endpoint
- EPFNOSUPPORT 96 Protocol family not supported
- EAFNOSUPPORT 97 Address family not supported by protocol
- EADDRINUSE 98 Address already in use
- EADDRNOTAVAIL 99 Cannot assign requested address
- ENETDOWN 100 Network is down
- ENETUNREACH 101 Network is unreachable
- ENETRESET 102 Network dropped connection because of reset
- ECONNABORTED 103 Software caused connection abort
- ECONNRESET 104 Connection reset by peer
- ENOBUFS 105 No buffer space available
- EISCONN 106 Transport endpoint is already connected
- ENOTCONN 107 Transport endpoint is not connected
- ESHUTDOWN 108 Cannot send after transport endpoint shutdown
- ETOOMANYREFS 109 Too many references: cannot splice
- ETIMEDOUT 110 Connection timed out
- ECONNREFUSED 111 Connection refused
- EHOSTDOWN 112 Host is down
- EHOSTUNREACH 113 No route to host
- EALREADY 114 Operation already in progress
- EINPROGRESS 115 Operation now in progress
- ESTALE 116 Stale NFS file handle
- EUCLEAN 117 Structure needs cleaning
- ENOTNAM 118 Not a XENIX named type file
- ENAVAIL 119 No XENIX semaphores available
- EISNAM 120 Is a named type file
- EREMOTEIO 121 Remote I/O error
- EDQUOT 122 Quota exceeded
- ENOMEDIUM 123 No medium found
- EMEDIUMTYPE 124 Wrong medium type
- ECANCELED 125 Operation Canceled
- ENOKEY 126 Required key not available
- EKEYEXPIRED 127 Key has expired
- EKEYREVOKED 128 Key has been revoked
- EKEYREJECTED 129 Key was rejected by service
- EOWNERDEAD 130 Owner died
- ENOTRECOVERABLE 131 State not recoverable
- \endverbatim
- *
- * @note
- * MbedOS System Error codes are defined using the macro MBED_DEFINE_SYSTEM_ERROR\n
- * For example MBED_DEFINE_SYSTEM_ERROR( INVALID_ARGUMENT ,1 ) macro defines the following values:\n
- * ERROR_CODE_INVALID_ARGUMENT = MBED_SYSTEM_ERROR_BASE+1\n
- * ERROR_INVALID_ARGUMENT = MAKE_MBED_ERROR(ERROR_TYPE_SYSTEM, MBED_MODULE_UNKNOWN, ERROR_CODE_INVALID_ARGUMENT)\n
- * Its effectively equivalent to:\n
- * ERROR_CODE_INVALID_ARGUMENT = 1\n
- * ERROR_INVALID_ARGUMENT = 0x80FF0001\n (Note that MODULE field is set to MBED_MODULE_UNKNOWN)
- * New System Error codes should be defined using MBED_DEFINE_SYSTEM_ERROR macro and must have an unique error code value\n
- * passed as the second argument in the MBED_DEFINE_SYSTEM_ERROR macro.\n\n
- * Below are the Mbed System error codes and the description:
- * \verbatim
- UNKNOWN 256 Unknown error
- INVALID_ARGUMENT 257 Invalid Argument
- INVALID_DATA 258 Invalid data
- INVALID_FORMAT 259 Invalid format
- INVALID_INDEX 260 Invalid Index
- INVALID_SIZE 261 Invalid Size
- INVALID_OPERATION 262 Invalid Operation
- NOT_FOUND 263 Not Found
- ACCESS_DENIED 264 Access Denied
- NOT_SUPPORTED 265 Not supported
- BUFFER_FULL 266 Buffer Full
- MEDIA_FULL 267 Media/Disk Full
- ALREADY_IN_USE 268 Already in use
- TIMEOUT 269 Timeout error
- NOT_READY 270 Not Ready
- FAILED_OPERATION 271 Requested Operation failed
- OPERATION_PROHIBITED 272 Operation prohibited
- OPERATION_ABORTED 273 Operation failed
- WRITE_PROTECTED 274 Attempt to write to write-protected resource
- NO_RESPONSE 275 No response
- SEMAPHORE_LOCK_FAILED 276 Semaphore lock failed
- MUTEX_LOCK_FAILED 277 Mutex lock failed
- SEMAPHORE_UNLOCK_FAILED 278 Semaphore unlock failed
- MUTEX_UNLOCK_FAILED 279 Mutex unlock failed
- CRC_ERROR 280 CRC error or mismatch
- OPEN_FAILED 281 Open failed
- CLOSE_FAILED 282 Close failed
- READ_FAILED 283 Read failed
- WRITE_FAILED 284 Write failed
- INITIALIZATION_FAILED 285 Initialization failed
- BOOT_FAILURE 286 Boot failure
- OUT_OF_MEMORY 287 Out of memory
- OUT_OF_RESOURCES 288 Out of resources
- ALLOC_FAILED 289 Alloc failed
- FREE_FAILED 290 Free failed
- OVERFLOW 291 Overflow error
- UNDERFLOW 292 Underflow error
- STACK_OVERFLOW 293 Stack overflow error
- ISR_QUEUE_OVERFLOW 294 ISR queue overflow
- TIMER_QUEUE_OVERFLOW 295 Timer Queue overflow
- CLIB_SPACE_UNAVAILABLE 296 Standard library error - Space unavailable
- CLIB_EXCEPTION 297 Standard library error - Exception
- CLIB_MUTEX_INIT_FAILURE 298 Standard library error - Mutex Init failure
- CREATE_FAILED 299 Create failed
- DELETE_FAILED 300 Delete failed
- THREAD_CREATE_FAILED 301 Thread Create failed
- THREAD_DELETE_FAILED 302 Thread Delete failed
- PROHIBITED_IN_ISR_CONTEXT 303 Operation Prohibited in ISR context
- PINMAP_INVALID 304 Pinmap Invalid
- RTOS_EVENT 305 Unknown Rtos Error
- RTOS_THREAD_EVENT 306 Rtos Thread Error
- RTOS_MUTEX_EVENT 307 Rtos Mutex Error
- RTOS_SEMAPHORE_EVENT 308 Rtos Semaphore Error
- RTOS_MEMORY_POOL_EVENT 309 Rtos Memory Pool Error
- RTOS_TIMER_EVENT 310 Rtos Timer Error
- RTOS_EVENT_FLAGS_EVENT 311 Rtos Event flags Error
- RTOS_MESSAGE_QUEUE_EVENT 312 Rtos Message queue Error
- DEVICE_BUSY 313 Device Busy
- CONFIG_UNSUPPORTED 314 Configuration not supported
- CONFIG_MISMATCH 315 Configuration mismatch
- ALREADY_INITIALIZED 316 Already initialized
- HARDFAULT_EXCEPTION 317 HardFault exception
- MEMMANAGE_EXCEPTION 318 MemManage exception
- BUSFAULT_EXCEPTION 319 BusFault exception
- USAGEFAULT_EXCEPTION 320 UsageFault exception
- BLE_NO_FRAME_INITIALIZED, 321 BLE No frame initialized
- BLE_BACKEND_CREATION_FAILED 322 BLE Backend creation failed
- BLE_BACKEND_NOT_INITIALIZED 323 BLE Backend not initialized
- ASSERTION_FAILED 324 Assertion Failed
- AUTHENTICATION_FAILED 325 Authentication Failed
- RBP_AUTHENTICATION_FAILED 326 Rollback Protect Authentication Failed
- \endverbatim
- *
- * @note
- * Custom Error codes can be defined using the macro DEFINE_CUSTOM_ERROR\n
- * This is mainly meant to capture non-generic error codes specific to a device.
- * For example DEFINE_CUSTOM_ERROR( MY_CUSTOM_ERROR ,1 ) macro defines the following values:\n
- * ERROR_CODE_MY_CUSTOM_ERROR = MBED_CUSTOM_ERROR_BASE+1\n
- * ERROR_MY_CUSTOM_ERROR = MAKE_MBED_ERROR(ERROR_TYPE_CUSTOM, MBED_MODULE_UNKNOWN, ERROR_CODE_MY_CUSTOM_ERROR)\n
- * Its effectively equivalent to:\n
- * ERROR_CODE_MY_CUSTOM_ERROR = 4097\n
- * ERROR_MY_CUSTOM_ERROR = 0xA0FF1001\n (Note that MODULE field is set to MBED_MODULE_UNKNOWN) \n\n
- *
- * @note
- * **Using error codes:** \n
- * POSIX error codes may be used in modules/functions currently using POSIX error codes and switching them to Mbed-OS error codes
- * may cause interoperability issues. For example, some of the filesystem, network stack implementations may need to use
- * POSIX error codes in order to keep them compatible with other modules interfacing with them, and may continue to use POSIX error codes.
- *
- * In all other cases, like for any native development of Mbed-OS modules Mbed-OS error codes should be used.
- * This makes it easy to use Mbed-OS error reporting/logging infrastructure and makes debugging error scenarios
- * much more efficient.
- *
- * @note
- * **Searching for error codes in mbed-os source tree:** \n
- * If you get an error report as below which you want to search for in mbed-os source tree, first take note of "Error Code" number. \n
- * For example, the below error report has an error code of \b 259. Find the error name associated with the error code and in this case its \b INVALID_FORMAT. \n
- * Use that error name(\b INVALID_FORMAT) to search the source tree for code locations setting that specific error code. \n
- * If the Error module reported is not 255(which indicates unknown module), you can also use that to narrow down to the specific component reporting the error.
- * See mbed_module_type_t enum above for module mapping. \n
- *
- * \verbatim
- ++ MbedOS Error Info ++
- Error Status: 0x80FF013D Code: 317 Module: 255
- Error Message: Fault exception
- Location: 0x5CD1
- Error Value: 0x4A2A
- Current Thread: Id: 0x20001E80 Entry: 0x5EB1 StackSize: 0x1000 StackMem: 0x20000E80 SP: 0x2002FF90
- For more info, visit: https://mbed.com/s/error?error=0x80FF013D&mbedos=999999&core=0x410FC241&compile=1&ver=5060528
- -- MbedOS Error Info --
- \endverbatim
- */
-
-typedef enum _mbed_error_code {
- //Below are POSIX ERROR CODE definitions, which starts at MBED_POSIX_ERROR_BASE(=0)
- //POSIX ERROR CODE definitions starts at offset 0(MBED_POSIX_ERROR_BASE) to align them with actual POSIX Error Code
- //defintions in mbed_retarget.h
- // Error Name Error Code
- MBED_DEFINE_POSIX_ERROR(EPERM, EPERM), /* 1 Operation not permitted */
- MBED_DEFINE_POSIX_ERROR(ENOENT, ENOENT), /* 2 No such file or directory */
- MBED_DEFINE_POSIX_ERROR(ESRCH, ESRCH), /* 3 No such process */
- MBED_DEFINE_POSIX_ERROR(EINTR, EINTR), /* 4 Interrupted system call */
- MBED_DEFINE_POSIX_ERROR(EIO, EIO), /* 5 I/O error */
- MBED_DEFINE_POSIX_ERROR(ENXIO, ENXIO), /* 6 No such device or address */
- MBED_DEFINE_POSIX_ERROR(E2BIG, E2BIG), /* 7 Argument list too long */
- MBED_DEFINE_POSIX_ERROR(ENOEXEC, ENOEXEC), /* 8 Exec format error */
- MBED_DEFINE_POSIX_ERROR(EBADF, EBADF), /* 9 Bad file number */
- MBED_DEFINE_POSIX_ERROR(ECHILD, ECHILD), /* 10 No child processes */
- MBED_DEFINE_POSIX_ERROR(EAGAIN, EAGAIN), /* 11 Try again */
- MBED_DEFINE_POSIX_ERROR(ENOMEM, ENOMEM), /* 12 Out of memory */
- MBED_DEFINE_POSIX_ERROR(EACCES, EACCES), /* 13 Permission denied */
- MBED_DEFINE_POSIX_ERROR(EFAULT, EFAULT), /* 14 Bad address */
- MBED_DEFINE_POSIX_ERROR(ENOTBLK, ENOTBLK), /* 15 Block device required */
- MBED_DEFINE_POSIX_ERROR(EBUSY, EBUSY), /* 16 Device or resource busy */
- MBED_DEFINE_POSIX_ERROR(EEXIST, EEXIST), /* 17 File exists */
- MBED_DEFINE_POSIX_ERROR(EXDEV, EXDEV), /* 18 Cross-device link */
- MBED_DEFINE_POSIX_ERROR(ENODEV, ENODEV), /* 19 No such device */
- MBED_DEFINE_POSIX_ERROR(ENOTDIR, ENOTDIR), /* 20 Not a directory */
- MBED_DEFINE_POSIX_ERROR(EISDIR, EISDIR), /* 21 Is a directory */
- MBED_DEFINE_POSIX_ERROR(EINVAL, EINVAL), /* 22 Invalid argument */
- MBED_DEFINE_POSIX_ERROR(ENFILE, ENFILE), /* 23 File table overflow */
- MBED_DEFINE_POSIX_ERROR(EMFILE, EMFILE), /* 24 Too many open files */
- MBED_DEFINE_POSIX_ERROR(ENOTTY, ENOTTY), /* 25 Not a typewriter */
- MBED_DEFINE_POSIX_ERROR(ETXTBSY, ETXTBSY), /* 26 Text file busy */
- MBED_DEFINE_POSIX_ERROR(EFBIG, EFBIG), /* 27 File too large */
- MBED_DEFINE_POSIX_ERROR(ENOSPC, ENOSPC), /* 28 No space left on device */
- MBED_DEFINE_POSIX_ERROR(ESPIPE, ESPIPE), /* 29 Illegal seek */
- MBED_DEFINE_POSIX_ERROR(EROFS, EROFS), /* 30 Read-only file system */
- MBED_DEFINE_POSIX_ERROR(EMLINK, EMLINK), /* 31 Too many links */
- MBED_DEFINE_POSIX_ERROR(EPIPE, EPIPE), /* 32 Broken pipe */
- MBED_DEFINE_POSIX_ERROR(EDOM, EDOM), /* 33 Math argument out of domain of func */
- MBED_DEFINE_POSIX_ERROR(ERANGE, ERANGE), /* 34 Math result not representable */
- MBED_DEFINE_POSIX_ERROR(EDEADLK, EDEADLK), /* 35 Resource deadlock would occur */
- MBED_DEFINE_POSIX_ERROR(ENAMETOOLONG, ENAMETOOLONG), /* 36 File name too long */
- MBED_DEFINE_POSIX_ERROR(ENOLCK, ENOLCK), /* 37 No record locks available */
- MBED_DEFINE_POSIX_ERROR(ENOSYS, ENOSYS), /* 38 Function not implemented */
- MBED_DEFINE_POSIX_ERROR(ENOTEMPTY, ENOTEMPTY), /* 39 Directory not empty */
- MBED_DEFINE_POSIX_ERROR(ELOOP, ELOOP), /* 40 Too many symbolic links encountered */
- MBED_DEFINE_POSIX_ERROR(EWOULDBLOCK, EAGAIN), /* EAGAIN Operation would block */
- MBED_DEFINE_POSIX_ERROR(ENOMSG, ENOMSG), /* 42 No message of desired type */
- MBED_DEFINE_POSIX_ERROR(EIDRM, EIDRM), /* 43 Identifier removed */
- MBED_DEFINE_POSIX_ERROR(ECHRNG, ECHRNG), /* 44 Channel number out of range */
- MBED_DEFINE_POSIX_ERROR(EL2NSYNC, EL2NSYNC), /* 45 Level 2 not synchronized */
- MBED_DEFINE_POSIX_ERROR(EL3HLT, EL3HLT), /* 46 Level 3 halted */
- MBED_DEFINE_POSIX_ERROR(EL3RST, EL3RST), /* 47 Level 3 reset */
- MBED_DEFINE_POSIX_ERROR(ELNRNG, ELNRNG), /* 48 Link number out of range */
- MBED_DEFINE_POSIX_ERROR(EUNATCH, EUNATCH), /* 49 Protocol driver not attached */
- MBED_DEFINE_POSIX_ERROR(ENOCSI, ENOCSI), /* 50 No CSI structure available */
- MBED_DEFINE_POSIX_ERROR(EL2HLT, EL2HLT), /* 51 Level 2 halted */
- MBED_DEFINE_POSIX_ERROR(EBADE, EBADE), /* 52 Invalid exchange */
- MBED_DEFINE_POSIX_ERROR(EBADR, EBADR), /* 53 Invalid request descriptor */
- MBED_DEFINE_POSIX_ERROR(EXFULL, EXFULL), /* 54 Exchange full */
- MBED_DEFINE_POSIX_ERROR(ENOANO, ENOANO), /* 55 No anode */
- MBED_DEFINE_POSIX_ERROR(EBADRQC, EBADRQC), /* 56 Invalid request code */
- MBED_DEFINE_POSIX_ERROR(EBADSLT, EBADSLT), /* 57 Invalid slot */
- MBED_DEFINE_POSIX_ERROR(EDEADLOCK, EDEADLK), /* EDEADLK Resource deadlock would occur */
- MBED_DEFINE_POSIX_ERROR(EBFONT, EBFONT), /* 59 Bad font file format */
- MBED_DEFINE_POSIX_ERROR(ENOSTR, ENOSTR), /* 60 Device not a stream */
- MBED_DEFINE_POSIX_ERROR(ENODATA, ENODATA), /* 61 No data available */
- MBED_DEFINE_POSIX_ERROR(ETIME, ETIME), /* 62 Timer expired */
- MBED_DEFINE_POSIX_ERROR(ENOSR, ENOSR), /* 63 Out of streams resources */
- MBED_DEFINE_POSIX_ERROR(ENONET, ENONET), /* 64 Machine is not on the network */
- MBED_DEFINE_POSIX_ERROR(ENOPKG, ENOPKG), /* 65 Package not installed */
- MBED_DEFINE_POSIX_ERROR(EREMOTE, EREMOTE), /* 66 Object is remote */
- MBED_DEFINE_POSIX_ERROR(ENOLINK, ENOLINK), /* 67 Link has been severed */
- MBED_DEFINE_POSIX_ERROR(EADV, EADV), /* 68 Advertise error */
- MBED_DEFINE_POSIX_ERROR(ESRMNT, ESRMNT), /* 69 Srmount error */
- MBED_DEFINE_POSIX_ERROR(ECOMM, ECOMM), /* 70 Communication error on send */
- MBED_DEFINE_POSIX_ERROR(EPROTO, EPROTO), /* 71 Protocol error */
- MBED_DEFINE_POSIX_ERROR(EMULTIHOP, EMULTIHOP), /* 72 Multihop attempted */
- MBED_DEFINE_POSIX_ERROR(EDOTDOT, EDOTDOT), /* 73 RFS specific error */
- MBED_DEFINE_POSIX_ERROR(EBADMSG, EBADMSG), /* 74 Not a data message */
- MBED_DEFINE_POSIX_ERROR(EOVERFLOW, EOVERFLOW), /* 75 Value too large for defined data type */
- MBED_DEFINE_POSIX_ERROR(ENOTUNIQ, ENOTUNIQ), /* 76 Name not unique on network */
- MBED_DEFINE_POSIX_ERROR(EBADFD, EBADFD), /* 77 File descriptor in bad state */
- MBED_DEFINE_POSIX_ERROR(EREMCHG, EREMCHG), /* 78 Remote address changed */
- MBED_DEFINE_POSIX_ERROR(ELIBACC, ELIBACC), /* 79 Can not access a needed shared library */
- MBED_DEFINE_POSIX_ERROR(ELIBBAD, ELIBBAD), /* 80 Accessing a corrupted shared library */
- MBED_DEFINE_POSIX_ERROR(ELIBSCN, ELIBSCN), /* 81 .lib section in a.out corrupted */
- MBED_DEFINE_POSIX_ERROR(ELIBMAX, ELIBMAX), /* 82 Attempting to link in too many shared libraries */
- MBED_DEFINE_POSIX_ERROR(ELIBEXEC, ELIBEXEC), /* 83 Cannot exec a shared library directly */
- MBED_DEFINE_POSIX_ERROR(EILSEQ, EILSEQ), /* 84 Illegal byte sequence */
- MBED_DEFINE_POSIX_ERROR(ERESTART, ERESTART), /* 85 Interrupted system call should be restarted */
- MBED_DEFINE_POSIX_ERROR(ESTRPIPE, ESTRPIPE), /* 86 Streams pipe error */
- MBED_DEFINE_POSIX_ERROR(EUSERS, EUSERS), /* 87 Too many users */
- MBED_DEFINE_POSIX_ERROR(ENOTSOCK, ENOTSOCK), /* 88 Socket operation on non-socket */
- MBED_DEFINE_POSIX_ERROR(EDESTADDRREQ, EDESTADDRREQ), /* 89 Destination address required */
- MBED_DEFINE_POSIX_ERROR(EMSGSIZE, EMSGSIZE), /* 90 Message too long */
- MBED_DEFINE_POSIX_ERROR(EPROTOTYPE, EPROTOTYPE), /* 91 Protocol wrong type for socket */
- MBED_DEFINE_POSIX_ERROR(ENOPROTOOPT, ENOPROTOOPT), /* 92 Protocol not available */
- MBED_DEFINE_POSIX_ERROR(EPROTONOSUPPORT, EPROTONOSUPPORT), /* 93 Protocol not supported */
- MBED_DEFINE_POSIX_ERROR(ESOCKTNOSUPPORT, ESOCKTNOSUPPORT), /* 94 Socket type not supported */
- MBED_DEFINE_POSIX_ERROR(EOPNOTSUPP, EOPNOTSUPP), /* 95 Operation not supported on transport endpoint */
- MBED_DEFINE_POSIX_ERROR(EPFNOSUPPORT, EPFNOSUPPORT), /* 96 Protocol family not supported */
- MBED_DEFINE_POSIX_ERROR(EAFNOSUPPORT, EAFNOSUPPORT), /* 97 Address family not supported by protocol */
- MBED_DEFINE_POSIX_ERROR(EADDRINUSE, EADDRINUSE), /* 98 Address already in use */
- MBED_DEFINE_POSIX_ERROR(EADDRNOTAVAIL, EADDRNOTAVAIL), /* 99 Cannot assign requested address */
- MBED_DEFINE_POSIX_ERROR(ENETDOWN, ENETDOWN), /* 100 Network is down */
- MBED_DEFINE_POSIX_ERROR(ENETUNREACH, ENETUNREACH), /* 101 Network is unreachable */
- MBED_DEFINE_POSIX_ERROR(ENETRESET, ENETRESET), /* 102 Network dropped connection because of reset */
- MBED_DEFINE_POSIX_ERROR(ECONNABORTED, ECONNABORTED), /* 103 Software caused connection abort */
- MBED_DEFINE_POSIX_ERROR(ECONNRESET, ECONNRESET), /* 104 Connection reset by peer */
- MBED_DEFINE_POSIX_ERROR(ENOBUFS, ENOBUFS), /* 105 No buffer space available */
- MBED_DEFINE_POSIX_ERROR(EISCONN, EISCONN), /* 106 Transport endpoint is already connected */
- MBED_DEFINE_POSIX_ERROR(ENOTCONN, ENOTCONN), /* 107 Transport endpoint is not connected */
- MBED_DEFINE_POSIX_ERROR(ESHUTDOWN, ESHUTDOWN), /* 108 Cannot send after transport endpoint shutdown */
- MBED_DEFINE_POSIX_ERROR(ETOOMANYREFS, ETOOMANYREFS), /* 109 Too many references: cannot splice */
- MBED_DEFINE_POSIX_ERROR(ETIMEDOUT, ETIMEDOUT), /* 110 Connection timed out */
- MBED_DEFINE_POSIX_ERROR(ECONNREFUSED, ECONNREFUSED), /* 111 Connection refused */
- MBED_DEFINE_POSIX_ERROR(EHOSTDOWN, EHOSTDOWN), /* 112 Host is down */
- MBED_DEFINE_POSIX_ERROR(EHOSTUNREACH, EHOSTUNREACH), /* 113 No route to host */
- MBED_DEFINE_POSIX_ERROR(EALREADY, EALREADY), /* 114 Operation already in progress */
- MBED_DEFINE_POSIX_ERROR(EINPROGRESS, EINPROGRESS), /* 115 Operation now in progress */
- MBED_DEFINE_POSIX_ERROR(ESTALE, ESTALE), /* 116 Stale NFS file handle */
- MBED_DEFINE_POSIX_ERROR(EUCLEAN, EUCLEAN), /* 117 Structure needs cleaning */
- MBED_DEFINE_POSIX_ERROR(ENOTNAM, ENOTNAM), /* 118 Not a XENIX named type file */
- MBED_DEFINE_POSIX_ERROR(ENAVAIL, ENAVAIL), /* 119 No XENIX semaphores available */
- MBED_DEFINE_POSIX_ERROR(EISNAM, EISNAM), /* 120 Is a named type file */
- MBED_DEFINE_POSIX_ERROR(EREMOTEIO, EREMOTEIO), /* 121 Remote I/O error */
- MBED_DEFINE_POSIX_ERROR(EDQUOT, EDQUOT), /* 122 Quota exceeded */
- MBED_DEFINE_POSIX_ERROR(ENOMEDIUM, ENOMEDIUM), /* 123 No medium found */
- MBED_DEFINE_POSIX_ERROR(EMEDIUMTYPE, EMEDIUMTYPE), /* 124 Wrong medium type */
- MBED_DEFINE_POSIX_ERROR(ECANCELED, ECANCELED), /* 125 Operation Canceled */
- MBED_DEFINE_POSIX_ERROR(ENOKEY, ENOKEY), /* 126 Required key not available */
- MBED_DEFINE_POSIX_ERROR(EKEYEXPIRED, EKEYEXPIRED), /* 127 Key has expired */
- MBED_DEFINE_POSIX_ERROR(EKEYREVOKED, EKEYREVOKED), /* 128 Key has been revoked */
- MBED_DEFINE_POSIX_ERROR(EKEYREJECTED, EKEYREJECTED), /* 129 Key was rejected by service */
- MBED_DEFINE_POSIX_ERROR(EOWNERDEAD, EOWNERDEAD), /* 130 Owner died */
- MBED_DEFINE_POSIX_ERROR(ENOTRECOVERABLE, ENOTRECOVERABLE), /* 131 State not recoverable */
-
- //Below are MBED SYSTEM ERROR CODE definitions
- //MBED SYSTEM ERROR CODE definitions starts at offset MBED_SYSTEM_ERROR_BASE, see above.
- // Error Name Error Offset Error Code
- MBED_DEFINE_SYSTEM_ERROR(UNKNOWN, 0), /* 256 Unknown error */
- MBED_DEFINE_SYSTEM_ERROR(INVALID_ARGUMENT, 1), /* 257 Invalid Argument */
- MBED_DEFINE_SYSTEM_ERROR(INVALID_DATA_DETECTED, 2), /* 258 Invalid data detected */
- MBED_DEFINE_SYSTEM_ERROR(INVALID_FORMAT, 3), /* 259 Invalid format */
- MBED_DEFINE_SYSTEM_ERROR(INVALID_INDEX, 4), /* 260 Invalid Index */
- MBED_DEFINE_SYSTEM_ERROR(INVALID_SIZE, 5), /* 261 Invalid Size */
- MBED_DEFINE_SYSTEM_ERROR(INVALID_OPERATION, 6), /* 262 Invalid Operation */
- MBED_DEFINE_SYSTEM_ERROR(ITEM_NOT_FOUND, 7), /* 263 Item Not Found */
- MBED_DEFINE_SYSTEM_ERROR(ACCESS_DENIED, 8), /* 264 Access Denied */
- MBED_DEFINE_SYSTEM_ERROR(UNSUPPORTED, 9), /* 265 Unsupported */
- MBED_DEFINE_SYSTEM_ERROR(BUFFER_FULL, 10), /* 266 Buffer Full */
- MBED_DEFINE_SYSTEM_ERROR(MEDIA_FULL, 11), /* 267 Media/Disk Full */
- MBED_DEFINE_SYSTEM_ERROR(ALREADY_IN_USE, 12), /* 268 Already in use */
- MBED_DEFINE_SYSTEM_ERROR(TIME_OUT, 13), /* 269 Timeout error */
- MBED_DEFINE_SYSTEM_ERROR(NOT_READY, 14), /* 270 Not Ready */
- MBED_DEFINE_SYSTEM_ERROR(FAILED_OPERATION, 15), /* 271 Requested Operation failed */
- MBED_DEFINE_SYSTEM_ERROR(OPERATION_PROHIBITED, 16), /* 272 Operation prohibited */
- MBED_DEFINE_SYSTEM_ERROR(OPERATION_ABORTED, 17), /* 273 Operation failed */
- MBED_DEFINE_SYSTEM_ERROR(WRITE_PROTECTED, 18), /* 274 Attempt to write to write-protected resource */
- MBED_DEFINE_SYSTEM_ERROR(NO_RESPONSE, 19), /* 275 No response */
- MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_LOCK_FAILED, 20), /* 276 Semaphore lock failed */
- MBED_DEFINE_SYSTEM_ERROR(MUTEX_LOCK_FAILED, 21), /* 277 Mutex lock failed */
- MBED_DEFINE_SYSTEM_ERROR(SEMAPHORE_UNLOCK_FAILED, 22), /* 278 Semaphore unlock failed */
- MBED_DEFINE_SYSTEM_ERROR(MUTEX_UNLOCK_FAILED, 23), /* 279 Mutex unlock failed */
- MBED_DEFINE_SYSTEM_ERROR(CRC_ERROR, 24), /* 280 CRC error or mismatch */
- MBED_DEFINE_SYSTEM_ERROR(OPEN_FAILED, 25), /* 281 Open failed */
- MBED_DEFINE_SYSTEM_ERROR(CLOSE_FAILED, 26), /* 282 Close failed */
- MBED_DEFINE_SYSTEM_ERROR(READ_FAILED, 27), /* 283 Read failed */
- MBED_DEFINE_SYSTEM_ERROR(WRITE_FAILED, 28), /* 284 Write failed */
- MBED_DEFINE_SYSTEM_ERROR(INITIALIZATION_FAILED, 29), /* 285 Initialization failed */
- MBED_DEFINE_SYSTEM_ERROR(BOOT_FAILURE, 30), /* 286 Boot failure */
- MBED_DEFINE_SYSTEM_ERROR(OUT_OF_MEMORY, 31), /* 287 Out of memory */
- MBED_DEFINE_SYSTEM_ERROR(OUT_OF_RESOURCES, 32), /* 288 Out of resources */
- MBED_DEFINE_SYSTEM_ERROR(ALLOC_FAILED, 33), /* 289 Alloc failed */
- MBED_DEFINE_SYSTEM_ERROR(FREE_FAILED, 34), /* 290 Free failed */
- MBED_DEFINE_SYSTEM_ERROR(OVERFLOW, 35), /* 291 Overflow error */
- MBED_DEFINE_SYSTEM_ERROR(UNDERFLOW, 36), /* 292 Underflow error */
- MBED_DEFINE_SYSTEM_ERROR(STACK_OVERFLOW, 37), /* 293 Stack overflow error */
- MBED_DEFINE_SYSTEM_ERROR(ISR_QUEUE_OVERFLOW, 38), /* 294 ISR queue overflow */
- MBED_DEFINE_SYSTEM_ERROR(TIMER_QUEUE_OVERFLOW, 39), /* 295 Timer Queue overflow */
- MBED_DEFINE_SYSTEM_ERROR(CLIB_SPACE_UNAVAILABLE, 40), /* 296 Standard library error - Space unavailable */
- MBED_DEFINE_SYSTEM_ERROR(CLIB_EXCEPTION, 41), /* 297 Standard library error - Exception */
- MBED_DEFINE_SYSTEM_ERROR(CLIB_MUTEX_INIT_FAILURE, 42), /* 298 Standard library error - Mutex Init failure */
- MBED_DEFINE_SYSTEM_ERROR(CREATE_FAILED, 43), /* 299 Create failed */
- MBED_DEFINE_SYSTEM_ERROR(DELETE_FAILED, 44), /* 300 Delete failed */
- MBED_DEFINE_SYSTEM_ERROR(THREAD_CREATE_FAILED, 45), /* 301 Thread Create failed */
- MBED_DEFINE_SYSTEM_ERROR(THREAD_DELETE_FAILED, 46), /* 302 Thread Delete failed */
- MBED_DEFINE_SYSTEM_ERROR(PROHIBITED_IN_ISR_CONTEXT, 47), /* 303 Operation Prohibited in ISR context */
- MBED_DEFINE_SYSTEM_ERROR(PINMAP_INVALID, 48), /* 304 Pinmap Invalid */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_EVENT, 49), /* 305 Unknown Rtos Error */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_THREAD_EVENT, 50), /* 306 Rtos Thread Error */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_MUTEX_EVENT, 51), /* 307 Rtos Mutex Error */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_SEMAPHORE_EVENT, 52), /* 308 Rtos Semaphore Error */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_MEMORY_POOL_EVENT, 53), /* 309 Rtos Memory Pool Error */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_TIMER_EVENT, 54), /* 310 Rtos Timer Error */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_EVENT_FLAGS_EVENT, 55), /* 311 Rtos Event flags Error */
- MBED_DEFINE_SYSTEM_ERROR(RTOS_MESSAGE_QUEUE_EVENT, 56), /* 312 Rtos Message queue Error */
- MBED_DEFINE_SYSTEM_ERROR(DEVICE_BUSY, 57), /* 313 Device Busy */
- MBED_DEFINE_SYSTEM_ERROR(CONFIG_UNSUPPORTED, 58), /* 314 Configuration not supported */
- MBED_DEFINE_SYSTEM_ERROR(CONFIG_MISMATCH, 59), /* 315 Configuration mismatch */
- MBED_DEFINE_SYSTEM_ERROR(ALREADY_INITIALIZED, 60), /* 316 Already initialized */
- MBED_DEFINE_SYSTEM_ERROR(HARDFAULT_EXCEPTION, 61), /* 317 HardFault exception */
- MBED_DEFINE_SYSTEM_ERROR(MEMMANAGE_EXCEPTION, 62), /* 318 MemManage exception */
- MBED_DEFINE_SYSTEM_ERROR(BUSFAULT_EXCEPTION, 63), /* 319 BusFault exception */
- MBED_DEFINE_SYSTEM_ERROR(USAGEFAULT_EXCEPTION, 64), /* 320 UsageFault exception*/
- MBED_DEFINE_SYSTEM_ERROR(BLE_NO_FRAME_INITIALIZED, 65), /* 321 BLE No frame initialized */
- MBED_DEFINE_SYSTEM_ERROR(BLE_BACKEND_CREATION_FAILED, 66), /* 322 BLE Backend creation failed */
- MBED_DEFINE_SYSTEM_ERROR(BLE_BACKEND_NOT_INITIALIZED, 67), /* 323 BLE Backend not initialized */
- MBED_DEFINE_SYSTEM_ERROR(ASSERTION_FAILED, 68), /* 324 Assertion Failed */
- MBED_DEFINE_SYSTEM_ERROR(AUTHENTICATION_FAILED, 69), /* 325 Authentication Failed */
- MBED_DEFINE_SYSTEM_ERROR(RBP_AUTHENTICATION_FAILED, 70), /* 326 Rollback Protection Authentication Failed */
- MBED_DEFINE_SYSTEM_ERROR(BLE_USE_INCOMPATIBLE_API, 71), /* 327 Concurrent use of incompatible versions of a BLE API */
- MBED_DEFINE_SYSTEM_ERROR(BLE_ILLEGAL_STATE, 72), /* 328 BLE stack entered illegal state */
-
- //Everytime you add a new system error code, you must update
- //Error documentation under Handbook to capture the info on
- //the new error status/codes
-
- //MBED CUSTOM ERROR CODE definitions starts at offset MBED_CUSTOM_ERROR_BASE, see above.
- /* Add More/Custom Error Codes here, See example below */
- //DEFINE_CUSTOM_ERROR( MY_CUSTOM_ERROR , 1 ),
-
-} mbed_error_code_t;
-
-/** mbed_error_ctx struct
- *
- * This struct captures the context information at the time of error.\n
- * It primarily contains information about the thread where the error originated,\n
- * filename/line number of the source file where the error occurred, a context specific error value(error_value)\n
- * and the address where the error originated.\n
- *
- * @note
- * Below are the members of mbed_error_ctx struct\n
- * error_status mbed_error_status_t value for this error\n
- * error_function_address Address where the error occurred\n
- * thread_id ID of the thread which generated the error\n
- * thread_entry_address Entry function of the thread which generated the error\n
- * thread_stack_size Stack Size of the thread which generated the error\n
- * thread_stack_mem Stack Top of the thread which generated the error\n
- * thread_current_sp Current Stack Pointer of the thread which generated the error\n
- * error_value A context/error specific value associated with this error\n
- * error_filename Filename where the error originated\n
- * error_line_number Line number in error_filename where the error originated\n
- */
-typedef struct _mbed_error_ctx {
- mbed_error_status_t error_status;
- uint32_t error_address;
- uint32_t error_value;
- uint32_t thread_id;
- uint32_t thread_entry_address;
- uint32_t thread_stack_size;
- uint32_t thread_stack_mem;
- uint32_t thread_current_sp;
-#ifdef MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN
- char error_filename[MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN];
- uint32_t error_line_number;
-#endif
-#if MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED
- int32_t error_reboot_count;//everytime we write this struct we increment this value by 1, irrespective of time between reboots. Note that the data itself might change, but everytime we reboot due to error we update this count by 1
- int32_t is_error_processed;//once this error is processed set this value to 1
- uint32_t crc_error_ctx;//crc_error_ctx should always be the last member in this struct
-#endif
-} mbed_error_ctx;
-
-/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
- *
- * @param format C string that contains data stream to be printed.
- * Code snippets below show valid format.
- *
- * @code
- * #error "That shouldn't have happened!"
- * @endcode
- *
- * If the compiler evaluates this line, it will report the error and stop the compile.
- *
- * For example, you could use this to check some user-defined compile-time variables:
- *
- * @code
- * #define NUM_PORTS 7
- * #if (NUM_PORTS > 4)
- * #error "NUM_PORTS must be less than 4"
- * #endif
- * @endcode
- *
- * Reporting Run-Time Errors:
- * To generate a fatal run-time error, you can use the mbed error() function.
- *
- * @code
- * error("That shouldn't have happened!");
- * @endcode
- *
- * If the mbed running the program executes this function, it will print the
- * message via the USB serial port, and then die with the blue lights of death!
- *
- * The message can use printf-style formatting, so you can report variables in the
- * message too. For example, you could use this to check a run-time condition:
- *
- * @code
- * if(x >= 5) {
- * error("expected x to be less than 5, but got %d", x);
- * }
- * @endcode
- *
- *
- */
-
-MBED_NORETURN void error(const char *format, ...) MBED_PRINTF(1, 2);
-
-/**
- * Call this Macro to generate a mbed_error_status_t value for a System error
- * @param module Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
- * @param error_code The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
- *
- * @code
- *
- * mbed_error_status_t driver_error = MBED_MAKE_SYSTEM_ERROR( MODULE_DRIVER_USB, MBED_ERROR_CODE_INITIALIZATION_FAILED )
- *
- * @endcode
- * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_SYSTEM
- *
- */
-#define MBED_MAKE_SYSTEM_ERROR(module, error_code) MAKE_MBED_ERROR(MBED_ERROR_TYPE_SYSTEM, module, error_code)
-
-/**
- * Call this Macro to generate a mbed_error_status_t value for a Custom error
- * @param module Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
- * @param error_code The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
- *
- * @code
- *
- * mbed_error_status_t custom_error = MBED_MAKE_CUSTOM_ERROR( MBED_MODULE_APPLICATION, 0xDEAD//16-bit custom error code )
- *
- * @endcode
- * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_CUSTOM
- *
- */
-#define MBED_MAKE_CUSTOM_ERROR(module, error_code) MAKE_MBED_ERROR(MBED_ERROR_TYPE_CUSTOM, module, error_code)
-
-/**
- * Call this Macro to generate a mbed_error_status_t value for a System error
- * @param module Module generating the error code. If its unknown, pass MBED_MODULE_UNKNOWN. See mbed_module_type_t for module types.
- * @param error_code The mbed_error_code_t code to be used in generating the mbed_error_status_t. See mbed_error_code_t for error codes.
- *
- * @code
- *
- * mbed_error_status_t new_error = MBED_MAKE_ERROR( MODULE_DRIVER_USB, MBED_ERROR_INITIALIZATION_FAILED )
- *
- * @endcode
- * @note This macro generate mbed_error_status_t-es with error type set to MBED_ERROR_TYPE_SYSTEM
- *
- */
-#define MBED_MAKE_ERROR(module, error_code) MBED_MAKE_SYSTEM_ERROR(module, error_code)
-
-/**
- * Callback/Error hook function prototype. Applications needing a callback when an error is reported can use mbed_set_error_hook function
- * to register a callback/error hook function using the following prototype. When an error happens in the system error handling
- * implementation will invoke this callback with the mbed_error_status_t reported and the error context at the time of error.
- * @param error_ctx Error context structure associated with this error.
- * @return void
- *
- */
-typedef void (*mbed_error_hook_t)(const mbed_error_ctx *error_ctx);
-
-
-/**
- * Callback function for reporting error context during boot up. When MbedOS error handling system detects a fatal error
- * it will auto-reboot the system(if MBED_CONF_PLATFORM_FATAL_ERROR_AUTO_REBOOT_ENABLED is enabled) after capturing the
- * error info in special crash data RAM region. Once rebooted, MbedOS initialization routines will call this function with a pointer to
- * the captured mbed_error_ctx structure. If application implementation needs to receive this callback, mbed_error_reboot_callback
- * function should be overridden with custom implementation. By default it's defined as a WEAK function in mbed_error.c.
- * Note that this callback will be invoked before the system starts executing main() function. So the implementation of
- * the callback should be aware any resource limitations/availability of resources which are yet to be initialized by application main().
- *
- * @param error_ctx Error context structure associated with this error.
- * @return void
- *
- */
-void mbed_error_reboot_callback(mbed_error_ctx *error_context);
-
-/**
- * Initialize error handling system, this is called by the mbed-os boot sequence. This is not required to be called by Application unless the boot sequence is overridden by the system implementation.
- * NOTE: If MBED_CONF_PLATFORM_FATAL_ERROR_AUTO_REBOOT_ENABLED is enabled and if the current reboot count exceeds MBED_CONF_PLATFORM_ERROR_REBOOT_MAX the system will halt when this function is called,
- * and in such cases the caller will not get the control back. Also note that calling this function may trigger mbed_error_reboot_callback() if application side overides mbed_error_reboot_callback().
- * @return MBED_SUCCESS on success.
- *
- */
-
-mbed_error_status_t mbed_error_initialize(void);
-
-/**
- * Call this function to retrieve the error context after a fatal error which triggered a system reboot. The function retrieves the error context stored in crash-report ram area which is preserved over reboot.
- * @param error_info Pointer to mbed_error_ctx struct allocated by the caller. This is the mbed_error_ctx info captured as part of the fatal error which triggered the reboot.
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_INVALID_ARGUMENT in case of invalid error_info pointer
- * MBED_ERROR_ITEM_NOT_FOUND if no reboot context is currently captured by the system
- *
- */
-mbed_error_status_t mbed_get_reboot_error_info(mbed_error_ctx *error_info);
-
-/**
- * Calling this function resets the current reboot context captured by the system(stored in special crash data RAM region).
- * @return MBED_SUCCESS on success.
- * MBED_ERROR_ITEM_NOT_FOUND if no reboot context is currently captured by the system
- */
-mbed_error_status_t mbed_reset_reboot_error_info(void);
-
-/**
- * Calling this function resets the current reboot count stored as part of error context captured in special crash data RAM region.
- * The function will also update the CRC value stored as part of error context accordingly.
- * @return MBED_SUCCESS on success.
- * MBED_ERROR_ITEM_NOT_FOUND if no reboot context is currently captured by the system
- */
-mbed_error_status_t mbed_reset_reboot_count(void);
-
-/**
- * Call this function to set a system error/warning. This function will log the error status with the context info and return to caller.
- *
- * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
- * @param error_msg The error message to be printed out to STDIO/Serial.
- * @param error_value Value associated with the error status. This would depend on error code/error scenario.
- * @param filename Name of the source file originating the error( Most callers can pass __FILE__ here ).
- * @param line_number The line number of the source file originating the error( Most callers can pass __LINE__ here ) .
- * @return 0 or MBED_SUCCESS.
- * MBED_ERROR_INVALID_ARGUMENT if called with invalid error status/codes
- *
- * @code
- *
- * mbed_error( ERROR_OUT_OF_MEMORY, "Out of memory error", 0, __FILE__, __LINE__ )
- *
- * @endcode
- *
- * @note See MBED_WARNING/MBED_ERROR macros which provides a wrapper on this API
- */
-mbed_error_status_t mbed_warning(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number);
-
-/**
- * Returns the first system error reported.
- * @return mbed_error_status_t code logged for the first error or MBED_SUCCESS if no errors are logged.
- *
- */
-mbed_error_status_t mbed_get_first_error(void);
-
-/**
- * Returns the most recent system error reported.
- * @return mbed_error_status_t code logged for the last error or MBED_SUCCESS if no errors are logged.
- *
- */
-mbed_error_status_t mbed_get_last_error(void);
-
-/**
- * Returns the number of system errors reported after boot.
- * @return int Number of errors reported.
- *
- */
-int mbed_get_error_count(void);
-
-/**
- * Call this function to set a fatal system error and halt the system. This function will log the fatal error with the context info and prints the error report and halts the system.
- *
- * @param error_status mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
- * @param error_msg The error message to be printed out to STDIO/Serial.
- * @param error_value Value associated with the error status. This would depend on error code/error scenario.
- * @param filename Name of the source file originating the error( Most callers can pass __FILE__ here ).
- * @param line_number The line number of the source file originating the error( Most callers can pass __LINE__ here ) .
- * @return Does not return.
- *
- * @code
- *
- * mbed_error( MBED_ERROR_PROHIBITED_OPERATION, "Prohibited operation tried", 0, __FILE__, __LINE__ )
- *
- * @endcode
- *
- * @note See MBED_WARNING/MBED_ERROR macros which provides a wrapper on this API
- */
-MBED_NORETURN mbed_error_status_t mbed_error(mbed_error_status_t error_status, const char *error_msg, unsigned int error_value, const char *filename, int line_number);
-
-/**
- * Registers an application defined error callback with the error handling system.
- * This function will be called with error context info whenever system handles a mbed_error/mbed_warning call
- * NOTE: This function should be implemented for re-entrancy as multiple threads may invoke mbed_error which may cause error hook to be called.
- * @param custom_error_hook mbed_error_status_t status to be set(See mbed_error_status_t enum above for available error status values).
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_INVALID_ARGUMENT in case of NULL for custom_error_hook
- *
- * @code
- *
- * mbed_error_status_t my_custom_error_hook(mbed_error_status_t error_status, const mbed_error_ctx *error_ctx) {
- * //Do something with the error_status or error_ctx
- * }
- *
- * mbed_set_error_hook( my_custom_error_hook )
- *
- * @endcode
- * @note The erro hook function implementation should be re-entrant.
- *
- */
-mbed_error_status_t mbed_set_error_hook(mbed_error_hook_t custom_error_hook);
-
-/**
- * Reads the first error context information captured.
- * @param error_info This is the mbed_error_context info captured as part of the first mbed_error call. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_INVALID_ARGUMENT in case of invalid index
- *
- */
-mbed_error_status_t mbed_get_first_error_info(mbed_error_ctx *error_info);
-
-/**
- * Reads the last error context information captured.
- * @param error_info This is the mbed_error_context info captured as part of the last mbed_error call. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
- * @return 0 or MBED_ERROR_SUCCESS on success.
- * MBED_ERROR_INVALID_ARGUMENT in case of invalid index
- *
- */
-mbed_error_status_t mbed_get_last_error_info(mbed_error_ctx *error_info);
-
-/**
- * Clears the last error, first error, error count and all entries in the error history.
- * @return 0 or MBED_SUCCESS on success.
- *
- */
-mbed_error_status_t mbed_clear_all_errors(void);
-
-/**
- * Generates a mbed_error_status_t value based on passed in values for type, module and error code.
- * @param error_type Error type based on mbed_error_type_t enum.
- * @param module Module type based on mbed_module_type_t enum.
- * @param error_code Error codes defined by mbed_error_code_t enum
- * @return 0 or MBED_ERROR_SUCCESS on success.
- *
- */
-mbed_error_status_t mbed_make_error(mbed_error_type_t error_type, mbed_module_type_t module, mbed_error_code_t error_code);
-
-/**
- * Returns the current number of entries in the error history, if there has been more than max number of errors logged the number returned will be max depth of error history.
- * @return Current number of entries in the error history.
- *
- */
-int mbed_get_error_hist_count(void);
-
-/**
- * Reads the error context information for a specific error from error history, specified by the index.
- *
- * @param index index of the error context entry in the history to be retrieved.\n
- * The number of entries in the error history is configured during build and the max index depends on max depth of error history.\n
- * index = 0 points to the oldest entry in the history, and index = (max history depth - 1) points to the latest entry in the error history.\n
- * @param error_info This is the mbed_error_context info captured as part of the error history. The caller should pass a pointer to mbed_error_context struct allocated by the caller.
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_INVALID_ARGUMENT in case of invalid index
- *
- */
-mbed_error_status_t mbed_get_error_hist_info(int index, mbed_error_ctx *error_info);
-
-/**
- * Saves the error history information to a file
- *
- * @param path path to the file in the filesystem
- * @return 0 or MBED_ERROR_SUCCESS on success.
- * MBED_ERROR_WRITE_FAILED if writing to file failed
- * MBED_ERROR_INVALID_ARGUMENT if path is not valid
- *
- * @note Filesystem support is required in order for this function to work.
- *
- */
-mbed_error_status_t mbed_save_error_hist(const char *path);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
-/** @}*/
-
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_error_hist.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ERROR_HIST_H
-#define MBED_ERROR_HIST_H
-
-#ifndef MBED_CONF_PLATFORM_ERROR_HIST_SIZE
-#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE 4
-#else
-#if MBED_CONF_PLATFORM_ERROR_HIST_SIZE == 0
-#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE 1
-#endif
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-/*
- * Puts/Adds an error entry into the error history list
- *
- * @param error_ctx pointer to the mbed_error_ctx struct with the error context
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_WRITE_FAILED if writing to file failed
- * MBED_ERROR_INVALID_ARGUMENT if path is not valid
- *
- *
- */
-mbed_error_status_t mbed_error_hist_put(mbed_error_ctx *error_ctx);
-
-/*
- * Reads the error entry from the error list with the specified index
- *
- * @param index Index of the error context to be retrieved. It starts from 0 and 0 is the oldest.
- * @param error_ctx pointer to the mbed_error_ctx struct where the error context will be filled, this should be allocated by the caller
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_WRITE_FAILED if writing to file failed
- * MBED_ERROR_INVALID_ARGUMENT if path is not valid
- *
- *
- */
-mbed_error_status_t mbed_error_hist_get(int index, mbed_error_ctx *error_ctx);
-
-/*
- * Gets a reference to the next error entry in the error log where in the error ctx can be filled in.
- * Its like reserving the next error entry to fill in the error info
- *
- * @return Returns the pointer to the next error ctx entry
- *
- *
- */
-mbed_error_ctx *mbed_error_hist_get_entry(void);
-
-/*
- * Reads the last(latest) error entry from the error history
- *
- * @param error_ctx pointer to the mbed_error_ctx struct where the error context will be filled, this should be allocated by the caller
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_WRITE_FAILED if writing to file failed
- * MBED_ERROR_INVALID_ARGUMENT if path is not valid
- *
- *
- */
-mbed_error_status_t mbed_error_hist_get_last_error(mbed_error_ctx *error_ctx);
-
-/*
- * Returns the number of error entries in the error history list
- *
- * @return Number of entries in the history list
- *
- *
- */
-int mbed_error_hist_get_count(void);
-
-/*
- * Resets the error log by resetting the number of errors to 0 and clears all previous errors in the history list
- *
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_WRITE_FAILED if writing to file failed
- * MBED_ERROR_INVALID_ARGUMENT if path is not valid
- *
- *
- */
-mbed_error_status_t mbed_error_hist_reset(void);
-
-/*
- * Saves the error log information to a file
- *
- * @param path path to the file in the filesystem
- * @return 0 or MBED_SUCCESS on success.
- * MBED_ERROR_WRITE_FAILED if writing to file failed
- * MBED_ERROR_INVALID_ARGUMENT if path is not valid
- *
- * @note Filesystem support is required in order for this function to work.
- *
- */
-mbed_error_status_t mbed_save_error_hist(const char *path);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_interface.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_interface Network interface and other utility functions
- * @{
- */
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERFACE_H
-#define MBED_INTERFACE_H
-
-#include <stdarg.h>
-
-#include "mbed_toolchain.h"
-#include "device.h"
-
-/* Mbed interface mac address
- * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
- * otherwise MAC_ADD_x are used.
- */
-#define MBED_MAC_ADDR_INTERFACE 0x00
-#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-/**
- * \defgroup platform_interface interface functions
- * @{
- */
-
-/** Functions to control the mbed interface
- *
- * mbed Microcontrollers have a built-in interface to provide functionality such as
- * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
- * system. These functions provide means to control the interface suing semihost
- * calls it supports.
- */
-
-/** Determine whether the mbed interface is connected, based on whether debug is enabled
- *
- * @returns
- * 1 if interface is connected,
- * 0 otherwise
- */
-int mbed_interface_connected(void);
-
-/** Instruct the mbed interface to reset, as if the reset button had been pressed
- *
- * @returns
- * 1 if successful,
- * 0 otherwise (e.g. interface not present)
- */
-int mbed_interface_reset(void);
-
-/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
- * The interface will still support the USB serial aspect
- *
- * @returns
- * 0 if successful,
- * -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_disconnect(void);
-
-/** This will disconnect the debug aspect of the interface, and if the USB cable is not
- * connected, also power down the interface. If the USB cable is connected, the interface
- * will remain powered up and visible to the host
- *
- * @returns
- * 0 if successful,
- * -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_powerdown(void);
-
-/** This returns a string containing the 32-character UID of the mbed interface
- * This is a weak function that can be overwritten if required
- *
- * @param uid A 33-byte array to write the null terminated 32-byte string
- *
- * @returns
- * 0 if successful,
- * -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_uid(char *uid);
-
-#endif
-
-/** This returns a unique 6-byte MAC address, based on the interface UID
- * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
- *
- * This is a weak function that can be overwritten if you want to provide your own mechanism to
- * provide a MAC address.
- *
- * @param mac A 6-byte array to write the MAC address
- */
-void mbed_mac_address(char *mac);
-
-/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
- */
-MBED_NORETURN void mbed_die(void);
-
-/** Print out an error message. This is typically called when
- * handling a crash.
- *
- * @note Synchronization level: Interrupt safe
- * @note This uses an internal 128-byte buffer to format the string,
- * so the output may be truncated. If you need to write a potentially
- * long string, use mbed_error_puts.
- *
- * @param format C string that contains data stream to be printed.
- * Code snippets below show valid format.
- *
- * @code
- * mbed_error_printf("Failed: %s, file: %s, line %d \n", expr, file, line);
- * @endcode
- *
- */
-void mbed_error_printf(const char *format, ...) MBED_PRINTF(1, 2);
-
-/** Print out an error message. Similar to mbed_error_printf
- * but uses a va_list.
- *
- * @note Synchronization level: Interrupt safe
- *
- * @param format C string that contains data stream to be printed.
- * @param arg Variable arguments list
- *
- */
-void mbed_error_vprintf(const char *format, va_list arg) MBED_PRINTF(1, 0);
-
-/** Print out an error message. This is typically called when
- * handling a crash.
- *
- * Unlike mbed_error_printf, there is no limit to the maximum output
- * length. Unlike standard puts, but like standard fputs, this does not
- * append a '\n' character.
- *
- * @note Synchronization level: Interrupt safe
- *
- * @param str C string that contains data stream to be printed.
- *
- */
-void mbed_error_puts(const char *str);
-
-/** @deprecated Renamed to mbed_error_vprintf to match functionality */
-MBED_DEPRECATED_SINCE("mbed-os-5.11",
- "Renamed to mbed_error_vprintf to match functionality.")
-void mbed_error_vfprintf(const char *format, va_list arg) MBED_PRINTF(1, 0);
-/** @}*/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_mem_trace.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,175 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2016 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __MBED_MEM_TRACE_H__
-#define __MBED_MEM_TRACE_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stddef.h>
-
-/**
- * enum Memory operation types for tracer
- */
-enum {
- MBED_MEM_TRACE_MALLOC, /**< Identifier for malloc operation */
- MBED_MEM_TRACE_REALLOC, /**< Identifier for realloc operation */
- MBED_MEM_TRACE_CALLOC, /**< Identifier for calloc operation */
- MBED_MEM_TRACE_FREE /**< Identifier for free operation */
-};
-
-/**
- * \defgroup platform_mem_trace mem_trace functions
- * @{
- */
-
-/* Prefix for the output of the default tracer */
-#define MBED_MEM_DEFAULT_TRACER_PREFIX "#"
-
-/**
- * Type of the callback used by the memory tracer. This callback is called when a memory
- * allocation operation (malloc, realloc, calloc, free) is called and tracing is enabled
- * for that memory allocation function.
- *
- * @param op the ID of the operation (MBED_MEM_TRACE_MALLOC, MBED_MEM_TRACE_REALLOC,
- * MBED_MEM_TRACE_CALLOC or MBED_MEM_TRACE_FREE).
- * @param res the result that the memory operation returned (NULL for 'free').
- * @param caller the caller of the memory operation. Note that the value of 'caller' might be
- * unreliable.
- *
- * The rest of the parameters passed 'mbed_mem_trace_cb_t' are the same as the memory operations
- * that triggered its call (see 'man malloc' for details):
- *
- * - for malloc: cb(MBED_MEM_TRACE_MALLOC, res, caller, size).
- * - for realloc: cb(MBED_MEM_TRACE_REALLOC, res, caller, ptr, size).
- * - for calloc: cb(MBED_MEM_TRACE_CALLOC, res, caller, nmemb, size).
- * - for free: cb(MBED_MEM_TRACE_FREE, NULL, caller, ptr).
- */
-typedef void (*mbed_mem_trace_cb_t)(uint8_t op, void *res, void *caller, ...);
-
-/**
- * Set the callback used by the memory tracer (use NULL for disable tracing).
- *
- * @param cb the callback to call on each memory operation.
- */
-void mbed_mem_trace_set_callback(mbed_mem_trace_cb_t cb);
-
-/**
- * Disable the memory trace output by disabling the callback function
- */
-void mbed_mem_trace_disable();
-
-/**
- * Re-enable the memory trace output with the cb in use when disable was called
- */
-void mbed_mem_trace_enable();
-
-/**
- * Trace lock.
- * @note Locking prevent recursive tracing of malloc/free inside realloc/calloc
- */
-void mbed_mem_trace_lock();
-
-/**
- * Trace unlock.
- */
-void mbed_mem_trace_unlock();
-
-/**
- * Trace a call to 'malloc'.
- * @param res the result of running 'malloc'.
- * @param size the 'size' argument given to 'malloc'.
- * @param caller the caller of the memory operation.
- * @return 'res' (the first argument).
- */
-void *mbed_mem_trace_malloc(void *res, size_t size, void *caller);
-
-/**
- * Trace a call to 'realloc'.
- * @param res the result of running 'realloc'.
- * @param ptr the 'ptr' argument given to 'realloc'.
- * @param size the 'size' argument given to 'realloc'.
- * @param caller the caller of the memory operation.
- * @return 'res' (the first argument).
- */
-void *mbed_mem_trace_realloc(void *res, void *ptr, size_t size, void *caller);
-
-/**
- * Trace a call to 'calloc'.
- * @param res the result of running 'calloc'.
- * @param num the 'nmemb' argument given to 'calloc'.
- * @param size the 'size' argument given to 'calloc'.
- * @param caller the caller of the memory operation.
- * @return 'res' (the first argument).
- */
-void *mbed_mem_trace_calloc(void *res, size_t num, size_t size, void *caller);
-
-/**
- * Trace a call to 'free'.
- * @param ptr the 'ptr' argument given to 'free'.
- * @param caller the caller of the memory operation.
- */
-void mbed_mem_trace_free(void *ptr, void *caller);
-
-/**
- * Default memory trace callback. DO NOT CALL DIRECTLY. It is meant to be used
- * as the second argument of 'mbed_mem_trace_setup'.
- *
- * The default callback outputs trace data using 'printf', in a format that's
- * easily parsable by an external tool. For each memory operation, the callback
- * outputs a line that begins with "#<op>:<0xresult>;<0xcaller>-":
- *
- * @param op identifies the memory operation ('m' for 'malloc', 'r' for 'realloc',
- * 'c' for 'calloc' and 'f' for 'free').
- * @param res (base 16) is the result of the memory operation. This is always NULL
- * for 'free', since 'free' doesn't return anything.
- * @param caller (base 16) is the caller of the memory operation. Note that the value
- * of 'caller' might be unreliable.
- *
- * The rest of the output depends on the operation being traced:
- *
- * - for 'malloc': 'size', where 'size' is the original argument to 'malloc'.
- * - for 'realloc': '0xptr;size', where 'ptr' (base 16) and 'size' are the original arguments to 'realloc'.
- * - for 'calloc': 'nmemb;size', where 'nmemb' and 'size' are the original arguments to 'calloc'.
- * - for 'free': '0xptr', where 'ptr' (base 16) is the original argument to 'free'.
- *
- * Examples:
- *
- * - "#m:0x20003240;0x600d-50" encodes a 'malloc' that returned 0x20003240, was called
- * by the instruction at 0x600D with a the 'size' argument equal to 50.
- * - "#f:0x0;0x602f-0x20003240" encodes a 'free' that was called by the instruction at
- * 0x602f with the 'ptr' argument equal to 0x20003240.
- */
-void mbed_mem_trace_default_callback(uint8_t op, void *res, void *caller, ...);
-
-/** @}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif// #ifndef __MBED_MEM_TRACE_H__
-
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_mktime.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,132 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2017-2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_MKTIME_H
-#define MBED_MKTIME_H
-
-#include <time.h>
-#include <stdbool.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup platform_mktime mktime functions
- * @{
- */
-
-/* Time range across the whole 32-bit range should be supported which means that years in range 1970 - 2106 can be
- * encoded. We have two types of RTC devices:
- * a) RTCs which handles all leap years in the mentioned year range correctly. Leap year is determined by checking if
- * the year counter value is divisible by 400, 100, and 4. No problem here.
- * b) RTCs which handles leap years correctly up to 2100. The RTC does a simple bit comparison to see if the two
- * lowest order bits of the year counter are zero. In this case 2100 year will be considered
- * incorrectly as a leap year, so the last valid point in time will be 28.02.2100 23:59:59 and next day will be
- * 29.02.2100 (invalid). So after 28.02.2100 the day counter will be off by a day.
- */
-typedef enum {
- RTC_FULL_LEAP_YEAR_SUPPORT,
- RTC_4_YEAR_LEAP_YEAR_SUPPORT
-} rtc_leap_year_support_t;
-
-/** Compute if a year is a leap year or not.
- *
- * @param year The year to test it shall be in the range [70:206]. Year 0 is
- * translated into year 1900 CE.
- * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
- * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
- *
- * @return true if the year in input is a leap year and false otherwise.
- *
- * @note For use by the HAL only
- * @note Year 2100 is treated differently for devices with full leap year support and devices with
- * partial leap year support. Devices with partial leap year support treats 2100 as a leap year.
- */
-bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support);
-
-/* Convert a calendar time into time since UNIX epoch as a time_t.
- *
- * This function is a thread safe (partial) replacement for mktime. It is
- * tailored around RTC peripherals needs and is not by any mean a complete
- * replacement of mktime.
- *
- * @param time The calendar time to convert into a time_t since epoch.
- * The fields from tm used for the computation are:
- * - tm_sec
- * - tm_min
- * - tm_hour
- * - tm_mday
- * - tm_mon
- * - tm_year
- * Other fields are ignored and won't be renormalized by a call to this function.
- * A valid calendar time is comprised between:
- * the 1st of January 1970 at 00:00:00 to the 7th of February 2106 at 06:28:15.
- * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
- * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
- * @param seconds holder for the result - calendar time as seconds since UNIX epoch.
- *
- * @return true on success, false if conversion error occurred.
- *
- * @note Leap seconds are not supported.
- * @note Values in output range from 0 to UINT_MAX.
- * @note Full and partial leap years support.
- * @note For use by the HAL only
- */
-bool _rtc_maketime(const struct tm *time, time_t *seconds, rtc_leap_year_support_t leap_year_support);
-
-/* Convert a given time in seconds since epoch into calendar time.
- *
- * This function is a thread safe (partial) replacement for localtime. It is
- * tailored around RTC peripherals specification and is not by any means a
- * complete of localtime.
- *
- * @param timestamp The time (in seconds) to convert into calendar time. Valid
- * input are in the range [0 : UINT32_MAX].
- * @param calendar_time Pointer to the object which will contain the result of
- * the conversion. The tm fields filled by this function are:
- * - tm_sec
- * - tm_min
- * - tm_hour
- * - tm_mday
- * - tm_mon
- * - tm_year
- * - tm_wday
- * - tm_yday
- * The object remains untouched if the time in input is invalid.
- * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
- * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
- * @return true if the conversion was successful, false otherwise.
- *
- * @note For use by the HAL only.
- * @note Full and partial leap years support.
- */
-bool _rtc_localtime(time_t timestamp, struct tm *time_info, rtc_leap_year_support_t leap_year_support);
-
-/** @}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MBED_MKTIME_H */
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_mpu_mgmt.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,111 +0,0 @@
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_mpu_mgmt MPU management functions
- * @{
- */
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2018 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_MPU_MGMT_H
-#define MBED_MPU_MGMT_H
-
-#include "mbed_toolchain.h"
-#include "hal/mpu_api.h"
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if (DEVICE_MPU && MBED_CONF_PLATFORM_USE_MPU) || defined(DOXYGEN_ONLY)
-
-#define mbed_mpu_manager_init() mbed_mpu_init()
-
-#define mbed_mpu_manager_deinit() mbed_mpu_free()
-
-/** Lock ram execute never mode off
- *
- * This disables the MPU's execute never ram protection and allows
- * functions to run from RAM. Execution directly from ram will be
- * allowed if this function is invoked at least once (the internal
- * counter is non-zero).
- *
- * Use this locking mechanism for code which needs to execute from
- * ram such as flash programming algorithms and ram thunks.
- *
- * The lock is a counter, can be locked up to USHRT_MAX
- * This function is IRQ and thread safe
- */
-void mbed_mpu_manager_lock_ram_execution(void);
-
-/** Unlock ram execute never mode
- *
- * Use unlocking in pair with mbed_mpu_manager_lock_ram_execution().
- *
- * The lock is a counter, should be equally unlocked as locked
- * This function is IRQ and thread safe
- */
-void mbed_mpu_manager_unlock_ram_execution(void);
-
-/** Lock rom write never mode off
- *
- * This disables the MPU's read only ROM protection and allows
- * ROM to be written to. Writing to ROM will not result in an MPU
- * fault if this function is invoked at least once (the internal
- * counter is non-zero).
- *
- * Use this locking mechanism for code which needs to write to
- * ROM such as flash programming algorithms.
- *
- * The lock is a counter, can be locked up to USHRT_MAX
- * This function is IRQ and thread safe
- */
-void mbed_mpu_manager_lock_rom_write(void);
-
-/** Unlock rom write never mode
- *
- * Use unlocking in pair with mbed_mpu_manager_lock_rom_write().
- *
- * The lock is a counter, should be equally unlocked as locked
- * This function is IRQ and thread safe
- */
-void mbed_mpu_manager_unlock_rom_write(void);
-
-#else
-
-#define mbed_mpu_manager_init() (void)0
-
-#define mbed_mpu_manager_deinit() (void)0
-
-#define mbed_mpu_manager_lock_ram_execution() (void)0
-
-#define mbed_mpu_manager_unlock_ram_execution() (void)0
-
-#define mbed_mpu_manager_lock_rom_write() (void)0
-
-#define mbed_mpu_manager_unlock_rom_write() (void)0
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_poll.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_POLL_H
-#define MBED_POLL_H
-
-#define POLLIN 0x0001 ///< Data may be read without blocking
-#define POLLOUT 0x0010 ///< Data may be written without blocking
-#define POLLERR 0x1000 ///< An error has occurred on the device or stream
-#define POLLHUP 0x2000 ///< The device has been disconnected
-#define POLLNVAL 0x4000 ///< The specified file handle value is invalid
-
-namespace mbed {
-
-class FileHandle;
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_poll poll functions
- * @{
- */
-
-struct pollfh {
- FileHandle *fh;
- short events;
- short revents;
-};
-
-/** A mechanism to multiplex input/output over a set of file handles(file descriptors).
- * For every file handle provided, poll() examines it for any events registered for that particular
- * file handle.
- *
- * @param fhs an array of PollFh struct carrying a FileHandle and bitmasks of events
- * @param nfhs number of file handles
- * @param timeout timer value to timeout or -1 for loop forever
- *
- * @return number of file handles selected (for which revents is non-zero). 0 if timed out with nothing selected. -1 for error.
- */
-int poll(pollfh fhs[], unsigned nfhs, int timeout);
-
-/**@}*/
-
-/**@}*/
-
-} // namespace mbed
-
-#endif //MBED_POLL_H
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_power_mgmt.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,277 +0,0 @@
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_power_mgmt Power management functions
- * @{
- */
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_POWER_MGMT_H
-#define MBED_POWER_MGMT_H
-
-#include "hal/sleep_api.h"
-#include "mbed_toolchain.h"
-#include "hal/ticker_api.h"
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup hal_sleep_manager Sleep manager API
- * The sleep manager provides API to automatically select sleep mode.
- *
- * There are two sleep modes:
- * - sleep
- * - deepsleep
- *
- * Use locking/unlocking deepsleep for drivers that depend on features that
- * are not allowed (=disabled) during the deepsleep. For instance, high frequency
- * clocks.
- *
- * # Defined behavior
- * * The lock is a counter
- * * The lock can be locked up to USHRT_MAX - Verified by ::test_lock_eq_ushrt_max
- * * The lock has to be equally unlocked as locked - Verified by ::test_lock_eq_ushrt_max
- * * The function sleep_manager_lock_deep_sleep_internal() locks the automatic deep mode selection - Verified by ::test_lock_unlock
- * * The function sleep_manager_unlock_deep_sleep_internal() unlocks the automatic deep mode selection - Verified by ::test_lock_unlock
- * * The function sleep_manager_sleep_auto() chooses the sleep or deep sleep modes based on the lock - Verified by ::test_sleep_auto
- * * The function sleep_manager_lock_deep_sleep_internal() is IRQ and thread safe - Verified by ::sleep_manager_multithread_test and ::sleep_manager_irq_test
- * * The function sleep_manager_unlock_deep_sleep_internal() is IRQ and thread safe - Verified by ::sleep_manager_multithread_test and ::sleep_manager_irq_test
- * * The function sleep_manager_sleep_auto() is IRQ and thread safe
- *
- * Example:
- * @code
- *
- * void driver::handler()
- * {
- * if (_sensor.get_event()) {
- * // any event - we are finished, unlock the deepsleep
- * sleep_manager_unlock_deep_sleep();
- * _callback();
- * }
- * }
- *
- * int driver::measure(event_t event, callback_t& callback)
- * {
- * _callback = callback;
- * sleep_manager_lock_deep_sleep();
- * // start async transaction, we are waiting for an event
- * return _sensor.start(event, callback);
- * }
- * @endcode
- * @{
- */
-
-/**
- * @defgroup hal_sleep_manager_tests Sleep manager API tests
- * Tests to validate the proper implementation of the sleep manager
- *
- * To run the sleep manager hal tests use the command:
- *
- * mbed test -t <toolchain> -m <target> -n tests-mbed_hal-sleep_manager*
- *
- */
-
-#ifdef MBED_SLEEP_TRACING_ENABLED
-
-void sleep_tracker_lock(const char *const filename, int line);
-void sleep_tracker_unlock(const char *const filename, int line);
-
-#define sleep_manager_lock_deep_sleep() \
- do \
- { \
- sleep_manager_lock_deep_sleep_internal(); \
- sleep_tracker_lock(MBED_FILENAME, __LINE__); \
- } while (0);
-
-#define sleep_manager_unlock_deep_sleep() \
- do \
- { \
- sleep_manager_unlock_deep_sleep_internal(); \
- sleep_tracker_unlock(MBED_FILENAME, __LINE__); \
- } while (0);
-
-#else
-
-#define sleep_manager_lock_deep_sleep() \
- sleep_manager_lock_deep_sleep_internal()
-
-#define sleep_manager_unlock_deep_sleep() \
- sleep_manager_unlock_deep_sleep_internal()
-
-#endif // MBED_SLEEP_TRACING_ENABLED
-
-/** Lock the deep sleep mode
- *
- * This locks the automatic deep mode selection.
- * sleep_manager_sleep_auto() will ignore deepsleep mode if
- * this function is invoked at least once (the internal counter is non-zero)
- *
- * Use this locking mechanism for interrupt driven API that are
- * running in the background and deepsleep could affect their functionality
- *
- * The lock is a counter, can be locked up to USHRT_MAX
- * This function is IRQ and thread safe
- */
-void sleep_manager_lock_deep_sleep_internal(void);
-
-/** Unlock the deep sleep mode
- *
- * Use unlocking in pair with sleep_manager_lock_deep_sleep().
- *
- * The lock is a counter, should be equally unlocked as locked
- * This function is IRQ and thread safe
- */
-void sleep_manager_unlock_deep_sleep_internal(void);
-
-/** Get the status of deep sleep allowance for a target
- *
- * @return true if a target can go to deepsleep, false otherwise
- */
-bool sleep_manager_can_deep_sleep(void);
-
-/** Check if the target can deep sleep within a period of time
- *
- * This function in intended for use in testing. The amount
- * of time this functions waits for deeps sleep to be available
- * is currently 2ms. This may change in the future depending
- * on testing requirements.
- *
- * @return true if a target can go to deepsleep, false otherwise
- */
-bool sleep_manager_can_deep_sleep_test_check(void);
-
-/** Enter auto selected sleep mode. It chooses the sleep or deepsleep modes based
- * on the deepsleep locking counter
- *
- * This function is IRQ and thread safe
- *
- * @note
- * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
- * to be active for debug modes.
- *
- */
-void sleep_manager_sleep_auto(void);
-
-/** Send the microcontroller to sleep
- *
- * @note This function can be a noop if not implemented by the platform.
- * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
- * @note This function will be a noop if the following conditions are met:
- * - The RTOS is present
- * - The processor turn off the Systick clock during sleep
- * - The target does not implement tickless mode
- *
- * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
- * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
- * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
- * memory state are maintained, and the peripherals continue to work and can generate interrupts.
- *
- * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
- *
- * @note
- * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-static inline void sleep(void)
-{
-#if DEVICE_SLEEP
-#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_SYSTICK_CLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
- sleep_manager_sleep_auto();
-#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_SYSTICK_CLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
-#endif /* DEVICE_SLEEP */
-}
-
-/** Send the microcontroller to deep sleep
- *
- * @deprecated
- * Do not use this function. Applications should use sleep() API which puts the system in deepsleep mode if supported.
- *
- * @note This function can be a noop if not implemented by the platform.
- * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
- *
- * This processor is setup ready for deep sleep, and sent to sleep. This mode
- * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
- * is still maintained.
- *
- * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
- *
- * @note
- * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-
-MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
-static inline void deepsleep(void)
-{
-#if DEVICE_SLEEP
- sleep_manager_sleep_auto();
-#endif /* DEVICE_SLEEP */
-}
-
-/** Provides the time spent in sleep mode since boot.
- *
- * @return Time spent in sleep
- * @note Works only if platform supports LP ticker.
- */
-us_timestamp_t mbed_time_sleep(void);
-
-/** Provides the time spent in deep sleep mode since boot.
- *
- * @return Time spent in deep sleep
- * @note Works only if platform supports LP ticker.
- */
-us_timestamp_t mbed_time_deepsleep(void);
-
-/** Provides the time spent in idle mode since boot.
- *
- * @return Idle thread time.
- * @note Works only if platform supports LP ticker.
- */
-us_timestamp_t mbed_time_idle(void);
-
-/** Provides the time since the system is up i.e. boot.
- *
- * @return System uptime.
- * @note Works only if platform supports LP ticker.
- */
-us_timestamp_t mbed_uptime(void);
-
-/** @}*/
-
-/** Resets the processor and most of the sub-system
- *
- * @note Does not affect the debug sub-system
- */
-MBED_NORETURN static inline void system_reset(void)
-{
- NVIC_SystemReset();
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_preprocessor.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,87 +0,0 @@
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_preprocessor preprocessor macros
- * @{
- */
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PREPROCESSOR_H
-#define MBED_PREPROCESSOR_H
-
-
-/** MBED_CONCAT
- * Concatenate tokens together
- *
- * @note
- * Expands tokens before concatenation
- *
- * @code
- * // Creates a unique label based on the line number
- * int MBED_CONCAT(UNIQUE_LABEL_, __LINE__) = 1;
- * @endcode
- */
-#define MBED_CONCAT(a, b) MBED_CONCAT_(a, b)
-#define MBED_CONCAT_(a, b) a##b
-
-/** MBED_STRINGIFY
- * Converts tokens into strings
- *
- * @note
- * Expands tokens before stringification
- *
- * @code
- * // Creates a string based on the parameters
- * const char *c = MBED_STRINGIFY(This is a ridiculous way to create a string)
- * @endcode
- */
-#define MBED_STRINGIFY(a) MBED_STRINGIFY_(a)
-#define MBED_STRINGIFY_(a) #a
-
-/** MBED_STRLEN
- * Reports string token length
- *
- * @note
- * Expands tokens before calculating length
- *
- * @code
- * // Get string length
- * const int len = MBED_STRLEN("Get the length")
- * @endcode
- */
-#define MBED_STRLEN(a) MBED_STRLEN_(a)
-#define MBED_STRLEN_(a) (sizeof(a) - 1)
-
-/** MBED_COUNT_VA_ARGS(...)
- * Reports number of tokens passed
- *
- * @note
- * Token limit is 16
- *
- * @code
- * // Get number of arguments
- * const int count = MBED_COUNT_VA_ARGS("Address 0x%x, Data[0] = %d Data[1] = %d", 0x20001234, 10, 20)
- * @endcode
- */
-#define MBED_COUNT_VA_ARGS(...) GET_NTH_ARG_(__VA_ARGS__, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1)
-#define GET_NTH_ARG_(_1, _2, _3, _4, _5, _6, _7, _8, _9, _10, _11, _12, _13, _14, _15, N, ...) N
-
-#endif
-
-/** @}*/
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_retarget.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,583 +0,0 @@
-/*
- * mbed Microcontroller Library
- * Copyright (c) 2006-2016 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- */
-
-#ifndef RETARGET_H
-#define RETARGET_H
-
-#if __cplusplus
-#include <cstdio>
-#else
-#include <stdio.h>
-#endif //__cplusplus
-#include <stdint.h>
-#include <stddef.h>
-
-/* Include logic for errno so we can get errno defined but not bring in error_t,
- * including errno here prevents an include later, which would redefine our
- * error codes
- */
-#ifndef __error_t_defined
-#define __error_t_defined 1
-#include <errno.h>
-#undef __error_t_defined
-#else
-#include <errno.h>
-#endif
-
-/* We can get the following standard types from sys/types for gcc, but we
- * need to define the types ourselves for the other compilers that normally
- * target embedded systems */
-typedef signed int ssize_t; ///< Signed size type, usually encodes negative errors
-typedef signed long off_t; ///< Offset in a data stream
-typedef unsigned int nfds_t; ///< Number of file descriptors
-typedef unsigned long long fsblkcnt_t; ///< Count of file system blocks
-#if defined(__ARMCC_VERSION) || !defined(__GNUC__)
-typedef unsigned int mode_t; ///< Mode for opening files
-typedef unsigned int dev_t; ///< Device ID type
-typedef unsigned long ino_t; ///< File serial number
-typedef unsigned int nlink_t; ///< Number of links to a file
-typedef unsigned int uid_t; ///< User ID
-typedef unsigned int gid_t; ///< Group ID
-#endif
-
-/* Flags for open() and fcntl(GETFL/SETFL)
- * At present, fcntl only supports reading and writing O_NONBLOCK
- */
-#define O_RDONLY 0 ///< Open for reading
-#define O_WRONLY 1 ///< Open for writing
-#define O_RDWR 2 ///< Open for reading and writing
-#define O_NONBLOCK 0x0004 ///< Non-blocking mode
-#define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write
-#define O_CREAT 0x0200 ///< Create file if it does not exist
-#define O_TRUNC 0x0400 ///< Truncate file to zero length
-#define O_EXCL 0x0800 ///< Fail if file exists
-#define O_BINARY 0x8000 ///< Open file in binary mode
-
-#define O_ACCMODE (O_RDONLY|O_WRONLY|O_RDWR)
-
-#define NAME_MAX 255 ///< Maximum size of a name in a file path
-
-#define STDIN_FILENO 0
-#define STDOUT_FILENO 1
-#define STDERR_FILENO 2
-
-#include <time.h>
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_retarget Retarget functions
- * @{
- */
-
-/* DIR declarations must also be here */
-#if __cplusplus
-namespace mbed {
-
-class FileHandle;
-class DirHandle;
-
-/** Targets may implement this to change stdin, stdout, stderr.
- *
- * If the application hasn't provided mbed_override_console, this is called
- * to give the target a chance to specify a FileHandle for the console.
- *
- * If this is not provided or returns NULL, the console will be:
- * - UARTSerial if configuration option "platform.stdio-buffered-serial" is
- * true and the target has DEVICE_SERIAL;
- * - Raw HAL serial via serial_getc and serial_putc if
- * "platform.stdio-buffered-serial" is false and the target has DEVICE_SERIAL;
- * - stdout/stderr will be a sink and stdin will input a stream of 0s if the
- * target does not have DEVICE_SERIAL.
- *
- * @param fd file descriptor - STDIN_FILENO, STDOUT_FILENO or STDERR_FILENO
- * @return pointer to FileHandle to override normal stream otherwise NULL
- */
-FileHandle *mbed_target_override_console(int fd);
-
-/** Applications may implement this to change stdin, stdout, stderr.
- *
- * This hook gives the application a chance to specify a custom FileHandle
- * for the console.
- *
- * If this is not provided or returns NULL, the console will be specified
- * by mbed_target_override_console, else will default to serial - see
- * mbed_target_override_console for more details.
- *
- * Example:
- * @code
- * FileHandle* mbed::mbed_override_console(int) {
- * static UARTSerial my_serial(D0, D1);
- * return &my_serial;
- * }
- * @endcode
-
- * @param fd file descriptor - STDIN_FILENO, STDOUT_FILENO or STDERR_FILENO
- * @return pointer to FileHandle to override normal stream otherwise NULL
- */
-FileHandle *mbed_override_console(int fd);
-
-}
-
-typedef mbed::DirHandle DIR;
-#else
-typedef struct Dir DIR;
-#endif
-
-/* The intent of this section is to unify the errno error values to match
- * the POSIX definitions for the GCC_ARM, ARMCC and IAR compilers. This is
- * necessary because the ARMCC/IAR errno.h, or sys/stat.h are missing some
- * symbol definitions used by the POSIX filesystem API to return errno codes.
- * Note also that ARMCC errno.h defines some symbol values differently from
- * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against
- * this and future changes by changing the symbol definition as shown below.
- */
-#undef EPERM
-#define EPERM 1 /* Operation not permitted */
-#undef ENOENT
-#define ENOENT 2 /* No such file or directory */
-#undef ESRCH
-#define ESRCH 3 /* No such process */
-#undef EINTR
-#define EINTR 4 /* Interrupted system call */
-#undef EIO
-#define EIO 5 /* I/O error */
-#undef ENXIO
-#define ENXIO 6 /* No such device or address */
-#undef E2BIG
-#define E2BIG 7 /* Argument list too long */
-#undef ENOEXEC
-#define ENOEXEC 8 /* Exec format error */
-#undef EBADF
-#define EBADF 9 /* Bad file number */
-#undef ECHILD
-#define ECHILD 10 /* No child processes */
-#undef EAGAIN
-#define EAGAIN 11 /* Try again */
-#undef ENOMEM
-#define ENOMEM 12 /* Out of memory */
-#undef EACCES
-#define EACCES 13 /* Permission denied */
-#undef EFAULT
-#define EFAULT 14 /* Bad address */
-#undef ENOTBLK
-#define ENOTBLK 15 /* Block device required */
-#undef EBUSY
-#define EBUSY 16 /* Device or resource busy */
-#undef EEXIST
-#define EEXIST 17 /* File exists */
-#undef EXDEV
-#define EXDEV 18 /* Cross-device link */
-#undef ENODEV
-#define ENODEV 19 /* No such device */
-#undef ENOTDIR
-#define ENOTDIR 20 /* Not a directory */
-#undef EISDIR
-#define EISDIR 21 /* Is a directory */
-#undef EINVAL
-#define EINVAL 22 /* Invalid argument */
-#undef ENFILE
-#define ENFILE 23 /* File table overflow */
-#undef EMFILE
-#define EMFILE 24 /* Too many open files */
-#undef ENOTTY
-#define ENOTTY 25 /* Not a typewriter */
-#undef ETXTBSY
-#define ETXTBSY 26 /* Text file busy */
-#undef EFBIG
-#define EFBIG 27 /* File too large */
-#undef ENOSPC
-#define ENOSPC 28 /* No space left on device */
-#undef ESPIPE
-#define ESPIPE 29 /* Illegal seek */
-#undef EROFS
-#define EROFS 30 /* Read-only file system */
-#undef EMLINK
-#define EMLINK 31 /* Too many links */
-#undef EPIPE
-#define EPIPE 32 /* Broken pipe */
-#undef EDOM
-#define EDOM 33 /* Math argument out of domain of func */
-#undef ERANGE
-#define ERANGE 34 /* Math result not representable */
-#undef EDEADLK
-#define EDEADLK 35 /* Resource deadlock would occur */
-#undef ENAMETOOLONG
-#define ENAMETOOLONG 36 /* File name too long */
-#undef ENOLCK
-#define ENOLCK 37 /* No record locks available */
-#undef ENOSYS
-#define ENOSYS 38 /* Function not implemented */
-#undef ENOTEMPTY
-#define ENOTEMPTY 39 /* Directory not empty */
-#undef ELOOP
-#define ELOOP 40 /* Too many symbolic links encountered */
-#undef EWOULDBLOCK
-#define EWOULDBLOCK EAGAIN /* Operation would block */
-#undef ENOMSG
-#define ENOMSG 42 /* No message of desired type */
-#undef EIDRM
-#define EIDRM 43 /* Identifier removed */
-#undef ECHRNG
-#define ECHRNG 44 /* Channel number out of range */
-#undef EL2NSYNC
-#define EL2NSYNC 45 /* Level 2 not synchronized */
-#undef EL3HLT
-#define EL3HLT 46 /* Level 3 halted */
-#undef EL3RST
-#define EL3RST 47 /* Level 3 reset */
-#undef ELNRNG
-#define ELNRNG 48 /* Link number out of range */
-#undef EUNATCH
-#define EUNATCH 49 /* Protocol driver not attached */
-#undef ENOCSI
-#define ENOCSI 50 /* No CSI structure available */
-#undef EL2HLT
-#define EL2HLT 51 /* Level 2 halted */
-#undef EBADE
-#define EBADE 52 /* Invalid exchange */
-#undef EBADR
-#define EBADR 53 /* Invalid request descriptor */
-#undef EXFULL
-#define EXFULL 54 /* Exchange full */
-#undef ENOANO
-#define ENOANO 55 /* No anode */
-#undef EBADRQC
-#define EBADRQC 56 /* Invalid request code */
-#undef EBADSLT
-#define EBADSLT 57 /* Invalid slot */
-#undef EDEADLOCK
-#define EDEADLOCK EDEADLK /* Resource deadlock would occur */
-#undef EBFONT
-#define EBFONT 59 /* Bad font file format */
-#undef ENOSTR
-#define ENOSTR 60 /* Device not a stream */
-#undef ENODATA
-#define ENODATA 61 /* No data available */
-#undef ETIME
-#define ETIME 62 /* Timer expired */
-#undef ENOSR
-#define ENOSR 63 /* Out of streams resources */
-#undef ENONET
-#define ENONET 64 /* Machine is not on the network */
-#undef ENOPKG
-#define ENOPKG 65 /* Package not installed */
-#undef EREMOTE
-#define EREMOTE 66 /* Object is remote */
-#undef ENOLINK
-#define ENOLINK 67 /* Link has been severed */
-#undef EADV
-#define EADV 68 /* Advertise error */
-#undef ESRMNT
-#define ESRMNT 69 /* Srmount error */
-#undef ECOMM
-#define ECOMM 70 /* Communication error on send */
-#undef EPROTO
-#define EPROTO 71 /* Protocol error */
-#undef EMULTIHOP
-#define EMULTIHOP 72 /* Multihop attempted */
-#undef EDOTDOT
-#define EDOTDOT 73 /* RFS specific error */
-#undef EBADMSG
-#define EBADMSG 74 /* Not a data message */
-#undef EOVERFLOW
-#define EOVERFLOW 75 /* Value too large for defined data type */
-#undef ENOTUNIQ
-#define ENOTUNIQ 76 /* Name not unique on network */
-#undef EBADFD
-#define EBADFD 77 /* File descriptor in bad state */
-#undef EREMCHG
-#define EREMCHG 78 /* Remote address changed */
-#undef ELIBACC
-#define ELIBACC 79 /* Can not access a needed shared library */
-#undef ELIBBAD
-#define ELIBBAD 80 /* Accessing a corrupted shared library */
-#undef ELIBSCN
-#define ELIBSCN 81 /* .lib section in a.out corrupted */
-#undef ELIBMAX
-#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
-#undef ELIBEXEC
-#define ELIBEXEC 83 /* Cannot exec a shared library directly */
-#undef EILSEQ
-#define EILSEQ 84 /* Illegal byte sequence */
-#undef ERESTART
-#define ERESTART 85 /* Interrupted system call should be restarted */
-#undef ESTRPIPE
-#define ESTRPIPE 86 /* Streams pipe error */
-#undef EUSERS
-#define EUSERS 87 /* Too many users */
-#undef ENOTSOCK
-#define ENOTSOCK 88 /* Socket operation on non-socket */
-#undef EDESTADDRREQ
-#define EDESTADDRREQ 89 /* Destination address required */
-#undef EMSGSIZE
-#define EMSGSIZE 90 /* Message too long */
-#undef EPROTOTYPE
-#define EPROTOTYPE 91 /* Protocol wrong type for socket */
-#undef ENOPROTOOPT
-#define ENOPROTOOPT 92 /* Protocol not available */
-#undef EPROTONOSUPPORT
-#define EPROTONOSUPPORT 93 /* Protocol not supported */
-#undef ESOCKTNOSUPPORT
-#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
-#undef EOPNOTSUPP
-#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
-#undef EPFNOSUPPORT
-#define EPFNOSUPPORT 96 /* Protocol family not supported */
-#undef EAFNOSUPPORT
-#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
-#undef EADDRINUSE
-#define EADDRINUSE 98 /* Address already in use */
-#undef EADDRNOTAVAIL
-#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
-#undef ENETDOWN
-#define ENETDOWN 100 /* Network is down */
-#undef ENETUNREACH
-#define ENETUNREACH 101 /* Network is unreachable */
-#undef ENETRESET
-#define ENETRESET 102 /* Network dropped connection because of reset */
-#undef ECONNABORTED
-#define ECONNABORTED 103 /* Software caused connection abort */
-#undef ECONNRESET
-#define ECONNRESET 104 /* Connection reset by peer */
-#undef ENOBUFS
-#define ENOBUFS 105 /* No buffer space available */
-#undef EISCONN
-#define EISCONN 106 /* Transport endpoint is already connected */
-#undef ENOTCONN
-#define ENOTCONN 107 /* Transport endpoint is not connected */
-#undef ESHUTDOWN
-#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
-#undef ETOOMANYREFS
-#define ETOOMANYREFS 109 /* Too many references: cannot splice */
-#undef ETIMEDOUT
-#define ETIMEDOUT 110 /* Connection timed out */
-#undef ECONNREFUSED
-#define ECONNREFUSED 111 /* Connection refused */
-#undef EHOSTDOWN
-#define EHOSTDOWN 112 /* Host is down */
-#undef EHOSTUNREACH
-#define EHOSTUNREACH 113 /* No route to host */
-#undef EALREADY
-#define EALREADY 114 /* Operation already in progress */
-#undef EINPROGRESS
-#define EINPROGRESS 115 /* Operation now in progress */
-#undef ESTALE
-#define ESTALE 116 /* Stale NFS file handle */
-#undef EUCLEAN
-#define EUCLEAN 117 /* Structure needs cleaning */
-#undef ENOTNAM
-#define ENOTNAM 118 /* Not a XENIX named type file */
-#undef ENAVAIL
-#define ENAVAIL 119 /* No XENIX semaphores available */
-#undef EISNAM
-#define EISNAM 120 /* Is a named type file */
-#undef EREMOTEIO
-#define EREMOTEIO 121 /* Remote I/O error */
-#undef EDQUOT
-#define EDQUOT 122 /* Quota exceeded */
-#undef ENOMEDIUM
-#define ENOMEDIUM 123 /* No medium found */
-#undef EMEDIUMTYPE
-#define EMEDIUMTYPE 124 /* Wrong medium type */
-#undef ECANCELED
-#define ECANCELED 125 /* Operation Canceled */
-#undef ENOKEY
-#define ENOKEY 126 /* Required key not available */
-#undef EKEYEXPIRED
-#define EKEYEXPIRED 127 /* Key has expired */
-#undef EKEYREVOKED
-#define EKEYREVOKED 128 /* Key has been revoked */
-#undef EKEYREJECTED
-#define EKEYREJECTED 129 /* Key was rejected by service */
-#undef EOWNERDEAD
-#define EOWNERDEAD 130 /* Owner died */
-#undef ENOTRECOVERABLE
-#define ENOTRECOVERABLE 131 /* State not recoverable */
-
-/* Missing stat.h defines.
- * The following are sys/stat.h definitions not currently present in the ARMCC
- * errno.h. Note, ARMCC errno.h defines some symbol values differing from
- * GCC_ARM/IAR/standard POSIX definitions. Guard against this and future
- * changes by changing the symbol definition for filesystem use.
- */
-#define _IFMT 0170000 //< type of file
-#define _IFSOCK 0140000 //< socket
-#define _IFLNK 0120000 //< symbolic link
-#define _IFREG 0100000 //< regular
-#define _IFBLK 0060000 //< block special
-#define _IFDIR 0040000 //< directory
-#define _IFCHR 0020000 //< character special
-#define _IFIFO 0010000 //< fifo special
-
-#define S_IFMT _IFMT //< type of file
-#define S_IFSOCK _IFSOCK //< socket
-#define S_IFLNK _IFLNK //< symbolic link
-#define S_IFREG _IFREG //< regular
-#define S_IFBLK _IFBLK //< block special
-#define S_IFDIR _IFDIR //< directory
-#define S_IFCHR _IFCHR //< character special
-#define S_IFIFO _IFIFO //< fifo special
-
-#define S_IRWXU (S_IRUSR | S_IWUSR | S_IXUSR)
-#define S_IRUSR 0000400 ///< read permission, owner
-#define S_IWUSR 0000200 ///< write permission, owner
-#define S_IXUSR 0000100 ///< execute/search permission, owner
-#define S_IRWXG (S_IRGRP | S_IWGRP | S_IXGRP)
-#define S_IRGRP 0000040 ///< read permission, group
-#define S_IWGRP 0000020 ///< write permission, group
-#define S_IXGRP 0000010 ///< execute/search permission, group
-#define S_IRWXO (S_IROTH | S_IWOTH | S_IXOTH)
-#define S_IROTH 0000004 ///< read permission, other
-#define S_IWOTH 0000002 ///< write permission, other
-#define S_IXOTH 0000001 ///< execute/search permission, other
-
-/* Refer to sys/stat standard
- * Note: Not all fields may be supported by the underlying filesystem
- */
-struct stat {
- dev_t st_dev; ///< Device ID containing file
- ino_t st_ino; ///< File serial number
- mode_t st_mode; ///< Mode of file
- nlink_t st_nlink; ///< Number of links to file
-
- uid_t st_uid; ///< User ID
- gid_t st_gid; ///< Group ID
-
- off_t st_size; ///< Size of file in bytes
-
- time_t st_atime; ///< Time of last access
- time_t st_mtime; ///< Time of last data modification
- time_t st_ctime; ///< Time of last status change
-};
-
-struct statvfs {
- unsigned long f_bsize; ///< Filesystem block size
- unsigned long f_frsize; ///< Fragment size (block size)
-
- fsblkcnt_t f_blocks; ///< Number of blocks
- fsblkcnt_t f_bfree; ///< Number of free blocks
- fsblkcnt_t f_bavail; ///< Number of free blocks for unprivileged users
-
- unsigned long f_fsid; ///< Filesystem ID
-
- unsigned long f_namemax; ///< Maximum filename length
-};
-
-/* The following are dirent.h definitions are declared here to guarantee
- * consistency where structure may be different with different toolchains
- */
-struct dirent {
- char d_name[NAME_MAX + 1]; ///< Name of file
- uint8_t d_type; ///< Type of file
-};
-
-enum {
- DT_UNKNOWN, ///< The file type could not be determined.
- DT_FIFO, ///< This is a named pipe (FIFO).
- DT_CHR, ///< This is a character device.
- DT_DIR, ///< This is a directory.
- DT_BLK, ///< This is a block device.
- DT_REG, ///< This is a regular file.
- DT_LNK, ///< This is a symbolic link.
- DT_SOCK, ///< This is a UNIX domain socket.
-};
-
-/* fcntl.h defines */
-#define F_GETFL 3
-#define F_SETFL 4
-
-struct pollfd {
- int fd;
- short events;
- short revents;
-};
-
-/* POSIX-compatible I/O functions */
-#if __cplusplus
-extern "C" {
-#endif
- int open(const char *path, int oflag, ...);
-#ifndef __IAR_SYSTEMS_ICC__ /* IAR provides fdopen itself */
-#if __cplusplus
- std::FILE *fdopen(int fildes, const char *mode);
-#else
- FILE *fdopen(int fildes, const char *mode);
-#endif
-#endif
- ssize_t write(int fildes, const void *buf, size_t nbyte);
- ssize_t read(int fildes, void *buf, size_t nbyte);
- off_t lseek(int fildes, off_t offset, int whence);
- int isatty(int fildes);
- int fsync(int fildes);
- int fstat(int fildes, struct stat *st);
- int fcntl(int fildes, int cmd, ...);
- int poll(struct pollfd fds[], nfds_t nfds, int timeout);
- int close(int fildes);
- int stat(const char *path, struct stat *st);
- int statvfs(const char *path, struct statvfs *buf);
- DIR *opendir(const char *);
- struct dirent *readdir(DIR *);
- int closedir(DIR *);
- void rewinddir(DIR *);
- long telldir(DIR *);
- void seekdir(DIR *, long);
- int mkdir(const char *name, mode_t n);
-#if __cplusplus
-}; // extern "C"
-
-namespace mbed {
-
-/** This call is an analogue to POSIX fdopen().
- *
- * It associates a C stream to an already-opened FileHandle, to allow you to
- * use C printf/scanf/fwrite etc. The provided FileHandle must remain open -
- * it will be closed by the C library when fclose(FILE) is called.
- *
- * The net effect is fdopen(bind_to_fd(fh), mode), with error handling.
- *
- * @param fh a pointer to an opened FileHandle
- * @param mode operation upon the file descriptor, e.g., "w+"
- *
- * @returns a pointer to FILE
- */
-std::FILE *fdopen(mbed::FileHandle *fh, const char *mode);
-
-/** Bind an mbed FileHandle to a POSIX file descriptor
- *
- * This is similar to fdopen, but only operating at the POSIX layer - it
- * associates a POSIX integer file descriptor with a FileHandle, to allow you
- * to use POSIX read/write calls etc. The provided FileHandle must remain open -
- * it will be closed when close(int) is called.
- *
- * @param fh a pointer to an opened FileHandle
- *
- * @return an integer file descriptor, or negative if no descriptors available
- */
-int bind_to_fd(mbed::FileHandle *fh);
-
-} // namespace mbed
-
-#endif // __cplusplus
-
-/**@}*/
-
-/**@}*/
-
-#endif /* RETARGET_H */
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_rtc_time.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_rtc_time rtc_time functions
- * @{
- */
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Implementation of the C time.h functions
- *
- * Provides mechanisms to set and read the current time, based
- * on the microcontroller Real-Time Clock (RTC), plus some
- * standard C manipulation and formatting functions.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37
- *
- * while (true) {
- * time_t seconds = time(NULL);
- *
- * printf("Time as seconds since January 1, 1970 = %u\n", (unsigned int)seconds);
- *
- * printf("Time as a basic string = %s", ctime(&seconds));
- *
- * char buffer[32];
- * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
- * printf("Time as a custom formatted string = %s", buffer);
- *
- * wait(1);
- * }
- * }
- * @endcode
- */
-
-/** Set the current time
- *
- * Initializes and sets the time of the microcontroller Real-Time Clock (RTC)
- * to the time represented by the number of seconds since January 1, 1970
- * (the UNIX timestamp).
- *
- * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
- *
- * @note Synchronization level: Thread safe
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
- * }
- * @endcode
- */
-void set_time(time_t t);
-
-/** Attach an external RTC to be used for the C time functions
- *
- * @note Synchronization level: Thread safe
- *
- * @param read_rtc pointer to function which returns current UNIX timestamp
- * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
- * @param init_rtc pointer to function which initializes RTC, can be NULL
- * @param isenabled_rtc pointer to function which returns if the RTC is enabled, can be NULL
- */
-void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
-
-#ifdef __cplusplus
-}
-#endif
-
-/** @}*/
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_semihost_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,99 +0,0 @@
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SEMIHOST_H
-#define MBED_SEMIHOST_H
-
-#include "device.h"
-#include "platform/mbed_toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-#if !defined(__CC_ARM) && !defined(__ARMCC_VERSION)
-
-#if defined(__ICCARM__)
-static inline int __semihost(int reason, const void *arg)
-{
- return __semihosting(reason, (void *)arg);
-}
-#else
-
-#ifdef __thumb__
-# define AngelSWI 0xAB
-# define AngelSWIInsn "bkpt"
-# define AngelSWIAsm bkpt
-#else
-# define AngelSWI 0x123456
-# define AngelSWIInsn "swi"
-# define AngelSWIAsm swi
-#endif
-
-static inline int __semihost(int reason, const void *arg)
-{
- int value;
-
- asm volatile(
- "mov r0, %1" "\n\t"
- "mov r1, %2" "\n\t"
- AngelSWIInsn " %a3" "\n\t"
- "mov %0, r0"
- : "=r"(value) /* output operands */
- : "r"(reason), "r"(arg), "i"(AngelSWI) /* input operands */
- : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */
- );
-
- return value;
-}
-#endif
-#endif
-
-#if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char *name, int openmode);
-int semihost_close(FILEHANDLE fh);
-int semihost_read(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode);
-int semihost_write(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode);
-int semihost_ensure(FILEHANDLE fh);
-long semihost_flen(FILEHANDLE fh);
-int semihost_seek(FILEHANDLE fh, long position);
-int semihost_istty(FILEHANDLE fh);
-
-int semihost_remove(const char *name);
-int semihost_rename(const char *old_name, const char *new_name);
-#endif
-
-int semihost_uid(char *uid);
-int semihost_reset(void);
-int semihost_vbus(void);
-int semihost_powerdown(void);
-int semihost_exit(void);
-
-int semihost_connected(void);
-int semihost_disabledebug(void);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_sleep.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_MBED_SLEEP_H -#define MBED_MBED_SLEEP_H - -#warning mbed_sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8] -#include "platform/mbed_power_mgmt.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_stats.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,184 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_stats stats functions
- * @{
- */
-/* mbed Microcontroller Library
- * Copyright (c) 2016-2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_STATS_H
-#define MBED_STATS_H
-#include <stdint.h>
-#include <stddef.h>
-#include "hal/ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifdef MBED_ALL_STATS_ENABLED
-
-#ifndef MBED_SYS_STATS_ENABLED
-#define MBED_SYS_STATS_ENABLED 1
-#endif
-#ifndef MBED_STACK_STATS_ENABLED
-#define MBED_STACK_STATS_ENABLED 1
-#endif
-#ifndef MBED_CPU_STATS_ENABLED
-#define MBED_CPU_STATS_ENABLED 1
-#endif
-#ifndef MBED_HEAP_STATS_ENABLED
-#define MBED_HEAP_STATS_ENABLED 1
-#endif
-#ifndef MBED_THREAD_STATS_ENABLED
-#define MBED_THREAD_STATS_ENABLED 1
-#endif
-
-#endif // MBED_ALL_STATS_ENABLED
-
-/** Maximum memory regions reported by mbed-os memory statistics */
-#define MBED_MAX_MEM_REGIONS 4
-
-/**
- * struct mbed_stats_heap_t definition
- */
-typedef struct {
- uint32_t current_size; /**< Bytes currently allocated on the heap */
- uint32_t max_size; /**< Maximum bytes allocated on the heap at one time since reset */
- uint32_t total_size; /**< Cumulative sum of bytes allocated on the heap that have not been freed */
- uint32_t reserved_size; /**< Current number of bytes reserved for the heap */
- uint32_t alloc_cnt; /**< Current number of allocations that have not been freed since reset */
- uint32_t alloc_fail_cnt; /**< Number of failed allocations since reset */
- uint32_t overhead_size; /**< Number of bytes used to store heap statistics. This overhead takes up space on the heap, reducing the available heap space */
-} mbed_stats_heap_t;
-
-/**
- * Fill the passed in heap stat structure with the heap statistics.
- *
- * @param stats A pointer to the mbed_stats_heap_t structure to fill
- */
-void mbed_stats_heap_get(mbed_stats_heap_t *stats);
-
-/**
- * struct mbed_stats_stack_t definition
- */
-typedef struct {
- uint32_t thread_id; /**< Identifier for the thread that owns the stack or 0 if representing accumulated statistics */
- uint32_t max_size; /**< Maximum number of bytes used on the stack since the thread was started */
- uint32_t reserved_size; /**< Current number of bytes reserved for the stack */
- uint32_t stack_cnt; /**< The number of stacks represented in the accumulated statistics or 1 if representing a single stack */
-} mbed_stats_stack_t;
-
-/**
- * Fill the passed in structure with stack statistics accumulated for all threads. The thread_id will be 0
- * and stack_cnt will represent number of threads.
- *
- * @param stats A pointer to the mbed_stats_stack_t structure to fill
- */
-void mbed_stats_stack_get(mbed_stats_stack_t *stats);
-
-/**
- * Fill the passed array of structures with the stack statistics for each available thread.
- *
- * @param stats A pointer to an array of mbed_stats_stack_t structures to fill
- * @param count The number of mbed_stats_stack_t structures in the provided array
- * @return The number of mbed_stats_stack_t structures that have been filled.
- * If the number of stacks on the system is less than or equal to count, it will equal the number of stacks on the system.
- * If the number of stacks on the system is greater than count, it will equal count.
- */
-size_t mbed_stats_stack_get_each(mbed_stats_stack_t *stats, size_t count);
-
-/**
- * struct mbed_stats_cpu_t definition
- */
-typedef struct {
- us_timestamp_t uptime; /**< Time since the system has started */
- us_timestamp_t idle_time; /**< Time spent in the idle thread since the system has started */
- us_timestamp_t sleep_time; /**< Time spent in sleep since the system has started */
- us_timestamp_t deep_sleep_time; /**< Time spent in deep sleep since the system has started */
-} mbed_stats_cpu_t;
-
-/**
- * Fill the passed in CPU stat structure with CPU statistics.
- *
- * @param stats A pointer to the mbed_stats_cpu_t structure to fill
- */
-void mbed_stats_cpu_get(mbed_stats_cpu_t *stats);
-
-/**
- * struct mbed_stats_thread_t definition
- */
-typedef struct {
- uint32_t id; /**< ID of the thread */
- uint32_t state; /**< State of the thread */
- uint32_t priority; /**< Priority of the thread (higher number indicates higher priority) */
- uint32_t stack_size; /**< Current number of bytes reserved for the stack */
- uint32_t stack_space; /**< Current number of free bytes remaining on the stack */
- const char *name; /**< Name of the thread */
-} mbed_stats_thread_t;
-
-/**
- * Fill the passed array of stat structures with the thread statistics for each available thread.
- *
- * @param stats A pointer to an array of mbed_stats_thread_t structures to fill
- * @param count The number of mbed_stats_thread_t structures in the provided array
- * @return The number of mbed_stats_thread_t structures that have been filled.
- * If the number of threads on the system is less than or equal to count, it will equal the number of threads on the system.
- * If the number of threads on the system is greater than count, it will equal count.
- */
-size_t mbed_stats_thread_get_each(mbed_stats_thread_t *stats, size_t count);
-
-/**
- * enum mbed_compiler_id_t definition
- */
-typedef enum {
- ARM = 1, /**< ARM */
- GCC_ARM, /**< GNU ARM */
- IAR /**< IAR */
-} mbed_compiler_id_t;
-
-/**
- * struct mbed_stats_sys_t definition
- */
-typedef struct {
- uint32_t os_version; /**< Mbed OS version (populated only for tagged releases) */
- uint32_t cpu_id; /**< CPUID register data (Cortex-M only supported) */
- mbed_compiler_id_t compiler_id; /**< Compiler ID \ref mbed_compiler_id_t */
- uint32_t compiler_version; /**< Compiler version */
- uint32_t ram_start[MBED_MAX_MEM_REGIONS]; /**< Start addresses of all internal RAM memories */
- uint32_t ram_size[MBED_MAX_MEM_REGIONS]; /**< Size of all internal RAM memories in target */
- uint32_t rom_start[MBED_MAX_MEM_REGIONS]; /**< Start addresses of all internal ROM memories */
- uint32_t rom_size[MBED_MAX_MEM_REGIONS]; /**< Size of all internal ROM memories in target */
-} mbed_stats_sys_t;
-
-/**
- * Fill the passed in system stat structure with system statistics.
- *
- * @param stats A pointer to the mbed_stats_sys_t structure to fill
- */
-void mbed_stats_sys_get(mbed_stats_sys_t *stats);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_toolchain.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,442 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_toolchain Toolchain functions
- * @{
- */
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TOOLCHAIN_H
-#define MBED_TOOLCHAIN_H
-
-#include "mbed_preprocessor.h"
-
-
-// Warning for unsupported compilers
-#if !defined(__GNUC__) /* GCC */ \
- && !defined(__CC_ARM) /* ARMCC */ \
- && !defined(__clang__) /* LLVM/Clang */ \
- && !defined(__ICCARM__) /* IAR */
-#warning "This compiler is not yet supported."
-#endif
-
-
-// Attributes
-
-/** MBED_PACKED
- * Pack a structure, preventing any padding from being added between fields.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_PACKED(struct) foo {
- * char x;
- * int y;
- * };
- * @endcode
- */
-#ifndef MBED_PACKED
-#if defined(__ICCARM__)
-#define MBED_PACKED(struct) __packed struct
-#else
-#define MBED_PACKED(struct) struct __attribute__((packed))
-#endif
-#endif
-
-/** MBED_ALIGN(N)
- * Declare a variable to be aligned on an N-byte boundary.
- *
- * @note
- * IAR does not support alignment greater than word size on the stack
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_ALIGN(16) char a;
- * @endcode
- */
-#ifndef MBED_ALIGN
-#if defined(__ICCARM__)
-#define MBED_ALIGN(N) _Pragma(MBED_STRINGIFY(data_alignment=N))
-#else
-#define MBED_ALIGN(N) __attribute__((aligned(N)))
-#endif
-#endif
-
-/** MBED_UNUSED
- * Declare a function argument to be unused, suppressing compiler warnings
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * void foo(MBED_UNUSED int arg) {
- *
- * }
- * @endcode
- */
-#ifndef MBED_UNUSED
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_UNUSED __attribute__((__unused__))
-#else
-#define MBED_UNUSED
-#endif
-#endif
-
-/** MBED_USED
- * Inform the compiler that a static variable is to be retained in the object file, even if it is unreferenced.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_USED int foo;
- *
- * @endcode
- */
-#ifndef MBED_USED
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_USED __attribute__((used))
-#elif defined(__ICCARM__)
-#define MBED_USED __root
-#else
-#define MBED_USED
-#endif
-#endif
-
-/** MBED_WEAK
- * Mark a function as being weak.
- *
- * @note
- * Functions should only be marked as weak in the source file. The header file
- * should contain a regular function declaration to insure the function is emitted.
- * A function marked weak will not be emitted if an alternative non-weak
- * implementation is defined.
- *
- * @note
- * Weak functions are not friendly to making code re-usable, as they can only
- * be overridden once (and if they are multiply overridden the linker will emit
- * no warning). You should not normally use weak symbols as part of the API to
- * re-usable modules.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_WEAK void foo() {
- * // a weak implementation of foo that can be overriden by a definition
- * // without __weak
- * }
- * @endcode
- */
-#ifndef MBED_WEAK
-#if defined(__ICCARM__)
-#define MBED_WEAK __weak
-#elif defined(__MINGW32__)
-#define MBED_WEAK
-#else
-#define MBED_WEAK __attribute__((weak))
-#endif
-#endif
-
-/** MBED_PURE
- * Hint to the compiler that a function depends only on parameters
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_PURE int foo(int arg){
- * // no access to global variables
- * }
- * @endcode
- */
-#ifndef MBED_PURE
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_PURE __attribute__((const))
-#else
-#define MBED_PURE
-#endif
-#endif
-
-/** MBED_NOINLINE
- * Declare a function that must not be inlined.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_NOINLINE void foo() {
- *
- * }
- * @endcode
- */
-#ifndef MBED_NOINLINE
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_NOINLINE __attribute__((noinline))
-#elif defined(__ICCARM__)
-#define MBED_NOINLINE _Pragma("inline=never")
-#else
-#define MBED_NOINLINE
-#endif
-#endif
-
-/** MBED_FORCEINLINE
- * Declare a function that must always be inlined. Failure to inline
- * such a function will result in an error.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_FORCEINLINE void foo() {
- *
- * }
- * @endcode
- */
-#ifndef MBED_FORCEINLINE
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_FORCEINLINE static inline __attribute__((always_inline))
-#elif defined(__ICCARM__)
-#define MBED_FORCEINLINE _Pragma("inline=forced") static
-#else
-#define MBED_FORCEINLINE static inline
-#endif
-#endif
-
-/** MBED_NORETURN
- * Declare a function that will never return.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_NORETURN void foo() {
- * // must never return
- * while (1) {}
- * }
- * @endcode
- */
-#ifndef MBED_NORETURN
-#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM)
-#define MBED_NORETURN __attribute__((noreturn))
-#elif defined(__ICCARM__)
-#define MBED_NORETURN __noreturn
-#else
-#define MBED_NORETURN
-#endif
-#endif
-
-/** MBED_UNREACHABLE
- * An unreachable statement. If the statement is reached,
- * behavior is undefined. Useful in situations where the compiler
- * cannot deduce if the code is unreachable.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * void foo(int arg) {
- * switch (arg) {
- * case 1: return 1;
- * case 2: return 2;
- * ...
- * }
- * MBED_UNREACHABLE;
- * }
- * @endcode
- */
-#ifndef MBED_UNREACHABLE
-#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
-#define MBED_UNREACHABLE __builtin_unreachable()
-#else
-#define MBED_UNREACHABLE while (1)
-#endif
-#endif
-
-/** MBED_DEPRECATED("message string")
- * Mark a function declaration as deprecated, if it used then a warning will be
- * issued by the compiler possibly including the provided message. Note that not
- * all compilers are able to display the message.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_DEPRECATED("don't foo any more, bar instead")
- * void foo(int arg);
- * @endcode
- */
-#ifndef MBED_DEPRECATED
-#if defined(__CC_ARM)
-#define MBED_DEPRECATED(M) __attribute__((deprecated))
-#elif defined(__GNUC__) || defined(__clang__)
-#define MBED_DEPRECATED(M) __attribute__((deprecated(M)))
-#else
-#define MBED_DEPRECATED(M)
-#endif
-#endif
-
-/** MBED_DEPRECATED_SINCE("version", "message string")
- * Mark a function declaration as deprecated, noting that the declaration was
- * deprecated on the specified version. If the function is used then a warning
- * will be issued by the compiler possibly including the provided message.
- * Note that not all compilers are able to display this message.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_DEPRECATED_SINCE("mbed-os-5.1", "don't foo any more, bar instead")
- * void foo(int arg);
- * @endcode
- */
-#define MBED_DEPRECATED_SINCE(D, M) MBED_DEPRECATED(M " [since " D "]")
-
-/** MBED_CALLER_ADDR()
- * Returns the caller of the current function.
- *
- * @note
- * This macro is only implemented for GCC and ARMCC.
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * printf("This function was called from %p", MBED_CALLER_ADDR());
- * @endcode
- *
- * @return Address of the calling function
- */
-#ifndef MBED_CALLER_ADDR
-#if (defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM)
-#define MBED_CALLER_ADDR() __builtin_extract_return_addr(__builtin_return_address(0))
-#elif defined(__CC_ARM)
-#define MBED_CALLER_ADDR() __builtin_return_address(0)
-#else
-#define MBED_CALLER_ADDR() (NULL)
-#endif
-#endif
-
-#ifndef MBED_SECTION
-#if (defined(__GNUC__) || defined(__clang__)) || defined(__CC_ARM)
-#define MBED_SECTION(name) __attribute__ ((section (name)))
-#elif defined(__ICCARM__)
-#define MBED_SECTION(name) _Pragma(MBED_STRINGIFY(location=name))
-#else
-#error "Missing MBED_SECTION directive"
-#endif
-#endif
-
-/**
- * Macro expanding to a string literal of the enclosing function name.
- *
- * The string returned takes into account language specificity and yield human
- * readable content.
- *
- * As an example, if the macro is used within a C++ function then the string
- * literal containing the function name will contain the complete signature of
- * the function - including template parameters - and namespace qualifications.
- */
-#ifndef MBED_PRETTY_FUNCTION
-#define MBED_PRETTY_FUNCTION __PRETTY_FUNCTION__
-#endif
-
-#ifndef MBED_PRINTF
-#if defined(__GNUC__) || defined(__CC_ARM)
-#define MBED_PRINTF(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx, first_param_idx)))
-#else
-#define MBED_PRINTF(format_idx, first_param_idx)
-#endif
-#endif
-
-#ifndef MBED_PRINTF_METHOD
-#if defined(__GNUC__) || defined(__CC_ARM)
-#define MBED_PRINTF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__printf__, format_idx+1, first_param_idx == 0 ? 0 : first_param_idx+1)))
-#else
-#define MBED_PRINTF_METHOD(format_idx, first_param_idx)
-#endif
-#endif
-
-#ifndef MBED_SCANF
-#if defined(__GNUC__) || defined(__CC_ARM)
-#define MBED_SCANF(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx, first_param_idx)))
-#else
-#define MBED_SCANF(format_idx, first_param_idx)
-#endif
-#endif
-
-#ifndef MBED_SCANF_METHOD
-#if defined(__GNUC__) || defined(__CC_ARM)
-#define MBED_SCANF_METHOD(format_idx, first_param_idx) __attribute__ ((__format__(__scanf__, format_idx+1, first_param_idx == 0 ? 0 : first_param_idx+1)))
-#else
-#define MBED_SCANF_METHOD(format_idx, first_param_idx)
-#endif
-#endif
-
-// Macro containing the filename part of the value of __FILE__. Defined as
-// string literal.
-#ifndef MBED_FILENAME
-#if defined(__CC_ARM)
-#define MBED_FILENAME __MODULE__
-#elif defined(__GNUC__)
-#define MBED_FILENAME (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__)
-#elif defined(__ICCARM__)
-#define MBED_FILENAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : strrchr(__FILE__, '\\') ? strrchr(__FILE__, '\\') + 1 : __FILE__)
-#else
-#define MBED_FILENAME __FILE__
-#endif
-#endif // #ifndef MBED_FILENAME
-
-// FILEHANDLE declaration
-#if defined(TOOLCHAIN_ARM)
-#include <rt_sys.h>
-#endif
-
-#ifndef FILEHANDLE
-typedef int FILEHANDLE;
-#endif
-
-// Backwards compatibility
-#ifndef WEAK
-#define WEAK MBED_WEAK
-#endif
-
-#ifndef PACKED
-#define PACKED MBED_PACKED()
-#endif
-
-#ifndef EXTERN
-#define EXTERN extern
-#endif
-
-/** MBED_NONSECURE_ENTRY
- * Declare a function that can be called from non-secure world or secure world
- *
- * @code
- * #include "mbed_toolchain.h"
- *
- * MBED_NONSECURE_ENTRY void foo() {
- *
- * }
- * @endcode
- */
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L)
-#if defined (__ICCARM__)
-#define MBED_NONSECURE_ENTRY __cmse_nonsecure_entry
-#else
-#define MBED_NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry))
-#endif
-#else
-#define MBED_NONSECURE_ENTRY
-#endif
-
-#endif
-
-/** @}*/
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_version.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_version Version macros
- * @{
- */
-/* mbed Microcontroller Library
- * Copyright (c) 2018 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_VERSION_H
-#define MBED_VERSION_H
-
-#define MBED_LIBRARY_VERSION 165
-
-/** MBED_MAJOR_VERSION
- * Mbed 2 major version
- */
-#define MBED_MAJOR_VERSION 2
-
-/** MBED_MINOR_VERSION
- * Mbed 2 minor version
- */
-#define MBED_MINOR_VERSION 0
-
-/** MBED_PATCH_VERSION
- * Mbed 2 patch version
- */
-#define MBED_PATCH_VERSION 165
-
-#define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch))
-
-#define MBED_VERSION MBED_ENCODE_VERSION(MBED_MAJOR_VERSION, MBED_MINOR_VERSION, MBED_PATCH_VERSION)
-
-#define MBED_VERSION_CHECK(major, minor, patch) do { \
- MBED_STATIC_ASSERT((MBED_VERSION >= MBED_ENCODE_VERSION((major),(minor),(patch))), "Incompatible mbed-os version detected!!"); \
- } while(0)
-
-#endif
-
-/** @}*/
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/mbed_wait_api.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_wait_api wait_api functions
- * @{
- */
-
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_WAIT_API_H
-#define MBED_WAIT_API_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Generic wait functions.
- *
- * These provide simple NOP type wait capabilities.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * DigitalOut heartbeat(LED1);
- *
- * int main() {
- * while (1) {
- * heartbeat = 1;
- * wait(0.5);
- * heartbeat = 0;
- * wait(0.5);
- * }
- * }
- * @endcode
- */
-
-/** Waits for a number of seconds, with microsecond resolution (within
- * the accuracy of single precision floating point).
- *
- * @param s number of seconds to wait
- *
- * @note
- * If the RTOS is present, this function spins to get the exact number of microseconds for
- * microsecond precision up to 10 milliseconds. If delay is larger than 10 milliseconds and not in ISR, it is the same as
- * `wait_ms`. We recommend `wait_us` and `wait_ms` over `wait`.
- */
-void wait(float s);
-
-/** Waits a number of milliseconds.
- *
- * @param ms the whole number of milliseconds to wait
- *
- * @note
- * If the RTOS is present, it calls ThisThread::sleep_for(), which is same as CMSIS osDelay().
- * You can't call this from interrupts, and it doesn't lock hardware sleep.
- */
-void wait_ms(int ms);
-
-/** Waits a number of microseconds.
- *
- * @param us the whole number of microseconds to wait
- *
- * @note
- * This function always spins to get the exact number of microseconds.
- * If RTOS is present, this will affect power (by preventing deep sleep) and
- * multithread performance. Therefore, spinning for millisecond wait is not recommended.
- */
-void wait_us(int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-/** @}*/
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/platform.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PLATFORM_H
-#define MBED_PLATFORM_H
-
-#include <cstddef>
-#include <cstdlib>
-#include <cstdio>
-#include <cstring>
-
-#include "platform/mbed_retarget.h"
-#include "platform/mbed_toolchain.h"
-#include "device.h"
-#include "PinNames.h"
-#include "PeripheralNames.h"
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/rtc_time.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_OLD_RTC_TIME_H -#define MBED_OLD_RTC_TIME_H - -#warning rtc_time.h has been replaced by mbed_rtc_time.h, please update to mbed_rtc_time.h [since mbed-os-5.3] -#include "platform/mbed_rtc_time.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/platform/semihost_api.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_OLD_SEMIHOST_API_H -#define MBED_OLD_SEMIHOST_API_H - -#warning semihost_api.h has been replaced by mbed_semihost_api.h, please update to mbed_semihost_api.h [since mbed-os-5.3] -#include "platform/mbed_semihost_api.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/platform/sleep.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_OLD_SLEEP_H -#define MBED_OLD_SLEEP_H - -#warning sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8] -#include "platform/mbed_power_mgmt.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/platform/toolchain.h Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,29 +0,0 @@
-
-/** \addtogroup platform */
-/** @{*/
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef MBED_OLD_TOOLCHAIN_H
-#define MBED_OLD_TOOLCHAIN_H
-
-#warning toolchain.h has been replaced by mbed_toolchain.h, please update to mbed_toolchain.h [since mbed-os-5.3]
-#include "platform/mbed_toolchain.h"
-
-#endif
-
-/** @}*/
--- a/STM32F103C8T6_MPA/mbed/platform/wait_api.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef MBED_OLD_WAIT_API_H -#define MBED_OLD_WAIT_API_H - -#warning wait_api.h has been replaced by mbed_wait_api.h, please update to mbed_wait_api.h [since mbed-os-5.3] -#include "platform/mbed_wait_api.h" - -#endif
--- a/STM32F103C8T6_MPA/mbed/targets.json Mon Mar 18 22:36:03 2019 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,8203 +0,0 @@
-{
- "Target": {
- "core": null,
- "default_toolchain": "ARM",
- "supported_toolchains": null,
- "extra_labels": [],
- "components": ["PSA_SRV_IMPL", "PSA_SRV_EMUL", "NSPE"],
- "is_disk_virtual": false,
- "macros": [],
- "device_has": [],
- "features": [],
- "detect_code": [],
- "public": false,
- "default_lib": "std",
- "bootloader_supported": false,
- "static_memory_defines": true,
- "config": {
- "console-uart-flow-control": {
- "help": "Console hardware flow control. Options: null, RTS, CTS, RTSCTS.",
- "value": null
- },
- "network-default-interface-type": {
- "help": "Default network interface type. Typical options: null, ETHERNET, WIFI, CELLULAR, MESH",
- "value": null
- },
- "deep-sleep-latency": {
- "help": "Time in ms required to go to and wake up from deep sleep (max 10)",
- "value": 0
- },
- "boot-stack-size": {
- "help": "Define the boot stack size in bytes. This value must be a multiple of 8",
- "value": "0x1000"
- },
- "mpu-rom-end": {
- "help": "Last address of ROM protected by the MPU",
- "value": "0x0fffffff"
- }
- }
- },
- "PSA_Target": {
- "public": false,
- "config": {
- "secure-rom-start": {
- "help": "Starting address of Secure ROM",
- "value": null,
- "macro_name": "PSA_SECURE_ROM_START",
- "conflicts": ["target.mbed_rom_start"]
- },
- "secure-rom-size": {
- "help": "Size in bytes of Secure ROM",
- "value": null,
- "macro_name": "PSA_SECURE_ROM_SIZE",
- "conflicts": ["target.mbed_rom_size"]
- },
- "non-secure-rom-start": {
- "help": "Starting address of Non-secure ROM",
- "value": null,
- "macro_name": "PSA_NON_SECURE_ROM_START",
- "conflicts": ["target.mbed_rom_start"]
- },
- "non-secure-rom-size": {
- "help": "Size in bytes of Non-secure ROM",
- "value": null,
- "macro_name": "PSA_NON_SECURE_ROM_SIZE",
- "conflicts": ["target.mbed_rom_size"]
- },
- "secure-ram-start": {
- "help": "Starting address of Secure RAM",
- "value": null,
- "macro_name": "PSA_SECURE_RAM_START",
- "conflicts": ["target.mbed_ram_start"]
- },
- "secure-ram-size": {
- "help": "Size in bytes of Secure RAM",
- "value": null,
- "macro_name": "PSA_SECURE_RAM_SIZE",
- "conflicts": ["target.mbed_ram_size"]
- },
- "non-secure-ram-start": {
- "help": "Starting address of Non-secure RAM",
- "value": null,
- "macro_name": "PSA_NON_SECURE_RAM_START",
- "conflicts": ["target.mbed_ram_start"]
- },
- "non-secure-ram-size": {
- "help": "Size in bytes of Non-secure RAM",
- "value": null,
- "macro_name": "PSA_NON_SECURE_RAM_SIZE",
- "conflicts": ["target.mbed_ram_size"]
- },
- "shared-ram-start": {
- "help": "Starting address of Shared RAM between Secure and Non-secure worlds",
- "value": null,
- "macro_name": "PSA_SHARED_RAM_START"
- },
- "shared-ram-size": {
- "help": "Size in bytes of Shared RAM between Secure and Non-secure worlds",
- "value": null,
- "macro_name": "PSA_SHARED_RAM_SIZE"
- }
- }
- },
- "NSPE_Target": {
- "inherits": ["PSA_Target"],
- "components": ["PSA_SRV_IPC", "NSPE"],
- "device_has_add": ["TRNG"],
- "public": false
- },
- "SPE_Target": {
- "inherits": ["PSA_Target"],
- "components": ["PSA_SRV_IMPL", "PSA_SRV_IPC", "SPE"],
- "public": false
- },
- "CM4_UARM": {
- "inherits": ["Target"],
- "core": "Cortex-M4",
- "default_toolchain": "uARM",
- "public": false,
- "supported_toolchains": ["uARM"],
- "default_lib": "small"
- },
- "CM4_ARM": {
- "inherits": ["Target"],
- "core": "Cortex-M4",
- "public": false,
- "supported_toolchains": ["ARM"]
- },
- "CM4F_UARM": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "default_toolchain": "uARM",
- "public": false,
- "supported_toolchains": ["uARM"],
- "default_lib": "small"
- },
- "CM4F_ARM": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "public": false,
- "supported_toolchains": ["ARM"]
- },
- "LPCTarget": {
- "inherits": ["Target"],
- "post_binary_hook": { "function": "LPCTargetCode.lpc_patch" },
- "public": false
- },
- "LPC11C24": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
- "OUTPUT_EXT": "hex",
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "CAN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "device_name": "LPC11C24FBD48/301"
- },
- "LPC1114": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC1114FN28/102"
- },
- "LPC11U24": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "detect_code": ["1040"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "LOCALFILESYSTEM",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC11U24FBD48/401"
- },
- "OC_MBUINO": {
- "inherits": ["LPC11U24"],
- "macros": [
- "TARGET_LPC11U24",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "extra_labels": ["NXP", "LPC11UXX"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2"]
- },
- "LPC11U24_301": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "extra_labels": ["NXP", "LPC11UXX"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "LOCALFILESYSTEM",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "device_name": "LPC11U24FHI33/301"
- },
- "LPC11U34_421": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "device_name": "LPC11U34FBD48/311"
- },
- "MICRONFCBOARD": {
- "inherits": ["LPC11U34_421"],
- "macros_add": ["LPC11U34_421", "APPNEARME_MICRONFCBOARD"],
- "extra_labels_add": ["APPNEARME_MICRONFCBOARD"],
- "release_versions": ["2"],
- "device_name": "LPC11U34FBD48/311"
- },
- "LPC11U35_401": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC11U35FBD48/401"
- },
- "LPC11U35_501": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC11U35FHI33/501"
- },
- "LPC11U35_501_IBDAP": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "device_name": "LPC11U35FHI33/501"
- },
- "XADOW_M0": {
- "inherits": ["LPC11U35_501"]
- },
- "LPC11U35_Y5_MBUG": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "device_name": "LPC11U35FHI33/501"
- },
- "LPC11U37_501": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "default_lib": "small",
- "device_name": "LPC11U37FBD64/501"
- },
- "LPCCAPPUCCINO": {
- "inherits": ["LPC11U37_501"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "device_name": "LPC11U37FBD64/501"
- },
- "ARCH_GPRS": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "inherits": ["LPCTarget"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC11U37FBD64/501"
- },
- "LPC11U68": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11U6X"],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "inherits": ["LPCTarget"],
- "detect_code": ["1168"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC11U68JBD100"
- },
- "LPC1347": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M3",
- "extra_labels": ["NXP", "LPC13XX"],
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2"],
- "device_name": "LPC1347FBD48"
- },
- "LPC1549": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M3",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC15XX"],
- "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
- "inherits": ["LPCTarget"],
- "detect_code": ["1549"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "CAN",
- "I2C",
- "INTERRUPTIN",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC1549JBD64"
- },
- "LPC1768": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M3",
- "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768", "NXP_EMAC"],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "detect_code": ["1010"],
- "device_has": [
- "RTC",
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "CAN",
- "DEBUG_AWARENESS",
- "EMAC",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "LOCALFILESYSTEM",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "LPC1768",
- "bootloader_supported": true,
- "config": {
- "us-ticker-timer": {
- "help": "Chooses which timer (0-3) to use for us_ticker.c",
- "value": 3
- }
- },
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "LPC1769": {
- "inherits": ["LPC1768"],
- "device_name": "LPC1769"
- },
- "ARCH_PRO": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M3",
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
- "macros": ["TARGET_LPC1768"],
- "inherits": ["LPCTarget"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "CAN",
- "DEBUG_AWARENESS",
- "EMAC",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "LPC1768",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "UBLOX_C027": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M3",
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "extra_labels": ["NXP", "LPC176X", "NXP_EMAC"],
- "config": {
- "modem_is_on_board": {
- "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD"
- },
- "modem_data_connection_type": {
- "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD_UART"
- }
- },
- "macros": ["TARGET_LPC1768"],
- "inherits": ["LPCTarget"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "CAN",
- "DEBUG_AWARENESS",
- "EMAC",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "LPC1768",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "CELLULAR"
- }
- },
- "XBED_LPC1768": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M3",
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "extra_labels": ["NXP", "LPC176X", "XBED_LPC1768"],
- "macros": ["TARGET_LPC1768"],
- "detect_code": ["1010"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "CAN",
- "DEBUG_AWARENESS",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "LOCALFILESYSTEM",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH",
- "MPU"
- ],
- "device_name": "LPC1768"
- },
- "LPC810": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC81X"],
- "is_disk_virtual": true,
- "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
- "device_has": [
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "device_name": "LPC810M021FN8"
- },
- "LPC812": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC81X"],
- "is_disk_virtual": true,
- "supported_toolchains": ["uARM", "IAR", "GCC_ARM"],
- "inherits": ["LPCTarget"],
- "detect_code": ["1050"],
- "device_has": [
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC812M101JDH20"
- },
- "LPC824": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC82X"],
- "is_disk_virtual": true,
- "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
- "inherits": ["LPCTarget"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC824M201JDH20"
- },
- "SSCI824": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC82X"],
- "is_disk_virtual": true,
- "supported_toolchains": ["uARM", "GCC_ARM"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"]
- },
- "MCU_LPC4088": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M4F",
- "extra_labels": ["NXP", "LPC408X", "NXP_EMAC"],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "post_binary_hook": {
- "function": "LPC4088Code.binary_hook"
- },
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "CAN",
- "DEBUG_AWARENESS",
- "EMAC",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "device_name": "LPC4088FBD144",
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "LPC4088": {
- "inherits": ["MCU_LPC4088"],
- "release_versions": ["2", "5"]
- },
- "LPC4088_DM": {
- "inherits": ["MCU_LPC4088"],
- "release_versions": ["2", "5"]
- },
- "LPC4330_M4": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M4F",
- "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
- "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "DEBUG_AWARENESS",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "device_name": "LPC4330"
- },
- "LPC4330_M0": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M0",
- "extra_labels": ["NXP", "LPC43XX", "LPC4330"],
- "supported_toolchains": ["ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "DEBUG_AWARENESS",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ]
- },
- "LPC4337": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M4F",
- "extra_labels": ["NXP", "LPC43XX", "LPC4337"],
- "supported_toolchains": ["ARM"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "DEBUG_AWARENESS",
- "ETHERNET",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "release_versions": ["2"],
- "device_name": "LPC4337"
- },
- "LPC1800": {
- "inherits": ["LPCTarget"],
- "core": "Cortex-M3",
- "extra_labels": ["NXP", "LPC43XX"],
- "public": false,
- "supported_toolchains": ["ARM", "IAR"]
- },
- "LPC11U37H_401": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC11UXX"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
- "inherits": ["LPCTarget"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "LPC11U37HFBD64/401"
- },
- "ELEKTOR_COCORICO": {
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "extra_labels": ["NXP", "LPC81X"],
- "supported_toolchains": ["uARM", "GCC_ARM", "IAR"],
- "inherits": ["LPCTarget"],
- "is_disk_virtual": true,
- "detect_code": ["C000"],
- "default_lib": "small",
- "device_name": "LPC812M101JDH16"
- },
- "KL05Z": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "extra_labels": ["Freescale", "KLXX"],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "inherits": ["Target"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "MKL05Z32xxx4"
- },
- "KL25Z": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "extra_labels": ["Freescale", "KLXX"],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "inherits": ["Target"],
- "detect_code": ["0200"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MKL25Z128xxx4"
- },
- "KL26Z": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "extra_labels": ["Freescale", "KLXX"],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "inherits": ["Target"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "device_name": "MKL26Z128xxx4"
- },
- "KL46Z": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "extra_labels": ["Freescale", "KLXX", "FLASH_CMSIS_ALGO"],
- "is_disk_virtual": true,
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "inherits": ["Target"],
- "detect_code": ["0220"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MKL46Z256xxx4",
- "bootloader_supported": true
- },
- "K20D50M": {
- "inherits": ["Target"],
- "core": "Cortex-M4",
- "extra_labels": ["Freescale", "K20XX"],
- "is_disk_virtual": true,
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "detect_code": ["0230"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2"],
- "device_name": "MK20DX128xxx5"
- },
- "TEENSY3_1": {
- "inherits": ["Target"],
- "core": "Cortex-M4",
- "extra_labels": ["Freescale", "K20XX", "K20DX256"],
- "OUTPUT_EXT": "hex",
- "is_disk_virtual": true,
- "supported_toolchains": ["GCC_ARM", "ARM"],
- "post_binary_hook": {
- "function": "TEENSY3_1Code.binary_hook",
- "toolchains": ["ARM_STD", "ARM_MICRO", "GCC_ARM"]
- },
- "detect_code": ["0230"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2"],
- "device_name": "MK20DX256xxx7"
- },
- "MCU_K22F512": {
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "MCU_K22F",
- "MCU_K22F512",
- "FRDM",
- "KPSDK_MCUS",
- "KPSDK_CODE"
- ],
- "is_disk_virtual": true,
- "public": false,
- "macros": ["CPU_MK22FN512VLH12", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "detect_code": ["0231"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH"
- ],
- "device_name": "MK22DN512xxx5"
- },
- "K22F": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_K22F512"],
- "release_versions": ["2", "5"],
- "extra_labels_add": ["FRDM"]
- },
- "KL27Z": {
- "inherits": ["Target"],
- "core": "Cortex-M0+",
- "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
- "macros": ["CPU_MKL27Z64VLH4", "FSL_RTOS_MBED"],
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "supported_form_factors": ["ARDUINO"],
- "is_disk_virtual": true,
- "default_toolchain": "ARM",
- "detect_code": ["0261"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "default_lib": "std",
- "release_versions": ["2"],
- "device_name": "MKL27Z64xxx4"
- },
- "KL43Z": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
- "macros": ["CPU_MKL43Z256VLH4", "FSL_RTOS_MBED"],
- "is_disk_virtual": true,
- "inherits": ["Target"],
- "detect_code": ["0262"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MKL43Z256xxx4"
- },
- "KL82Z": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
- "macros": ["CPU_MKL82Z128VLK7", "FSL_RTOS_MBED"],
- "is_disk_virtual": true,
- "inherits": ["Target"],
- "detect_code": ["0218"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SEMIHOST",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH",
- "QSPI"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MKL82Z128xxx7"
- },
- "USENSE": {
- "inherits": ["KL82Z"],
- "extra_labels_remove": ["FRDM"],
- "device_has_remove": ["QSPI"],
- "supported_form_factors": []
- },
- "KW24D": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
- "is_disk_virtual": true,
- "macros": ["CPU_MKW24D512VHA5", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "detect_code": ["0250"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH",
- "802_15_4_PHY"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MKW24D512xxx5",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "MESH"
- }
- },
- "KW41Z": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0+",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM", "FRAMEWORK_5_3_3", "NXP"],
- "is_disk_virtual": true,
- "macros": ["CPU_MKW41Z512VHT4", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "detect_code": ["0201"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "TRNG",
- "STDIO_MESSAGES",
- "FLASH",
- "802_15_4_PHY"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MKW41Z512xxx4",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "MESH"
- }
- },
- "MCU_K24F1M": {
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "MCU_K24F",
- "KPSDK_MCUS",
- "KPSDK_CODE"
- ],
- "is_disk_virtual": true,
- "public": false,
- "macros": ["CPU_MK24FN1M0VDC12", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH"
- ],
- "device_name": "MK24FN1M0xxx12"
- },
- "RO359B": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_K24F1M"],
- "detect_code": ["1022"],
- "release_versions": ["2", "5"]
- },
- "K64F": {
- "supported_form_factors": ["ARDUINO"],
- "components_add": ["SD", "FLASHIAP"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "FRDM",
- "KPSDK_MCUS",
- "KPSDK_CODE",
- "MCU_K64F",
- "Freescale_EMAC",
- "PSA"
- ],
- "is_disk_virtual": true,
- "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "MBEDTLS_PSA_CRYPTO_C"],
- "inherits": ["Target"],
- "detect_code": ["0240"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "CRC",
- "ANALOGIN",
- "ANALOGOUT",
- "EMAC",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "STORAGE",
- "TRNG",
- "FLASH"
- ],
- "features": ["STORAGE"],
- "release_versions": ["2", "5"],
- "device_name": "MK64FN1M0xxx12",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "SDT64B": {
- "inherits": ["K64F"],
- "extra_labels_add": ["K64F"],
- "extra_labels_remove": ["FRDM"],
- "components_remove": ["SD"],
- "supported_form_factors": [],
- "detect_code": ["3105"]
- },
- "EV_COG_AD4050LZ": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"],
- "extra_labels": [
- "Analog_Devices",
- "ADUCM4X50",
- "ADUCM4050",
- "EV_COG_AD4050LZ",
- "FLASH_CMSIS_ALGO"
- ],
- "device_has": [
- "FLASH",
- "USTICKER",
- "RTC",
- "SERIAL",
- "STDIO_MESSAGES",
- "TRNG",
- "SLEEP",
- "INTERRUPTIN",
- "SPI",
- "I2C",
- "ANALOGIN",
- "MPU"
- ],
- "device_name": "ADuCM4050",
- "detect_code": ["0603"],
- "release_versions": ["5"],
- "bootloader_supported": true
- },
- "EV_COG_AD3029LZ": {
- "inherits": ["Target"],
- "core": "Cortex-M3",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "macros": ["__ADUCM3029__", "EV_COG_AD3029LZ"],
- "extra_labels": [
- "Analog_Devices",
- "ADUCM302X",
- "ADUCM3029",
- "EV_COG_AD3029LZ",
- "FLASH_CMSIS_ALGO"
- ],
- "device_has": [
- "FLASH",
- "USTICKER",
- "RTC",
- "SERIAL",
- "STDIO_MESSAGES",
- "TRNG",
- "SLEEP",
- "INTERRUPTIN",
- "SPI",
- "I2C",
- "ANALOGIN",
- "MPU"
- ],
- "device_name": "ADuCM3029",
- "detect_code": ["0602"],
- "release_versions": ["5"],
- "bootloader_supported": true
- },
- "MTS_GAMBIT": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "GCC_ARM"],
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "KPSDK_MCUS",
- "KPSDK_CODE",
- "MCU_K64F"
- ],
- "is_disk_virtual": true,
- "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH"
- ],
- "device_name": "MK64FN1M0xxx12"
- },
- "HEXIWEAR": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "MCU_K64F"
- ],
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "macros": ["CPU_MK64FN1M0VMD12", "FSL_RTOS_MBED", "TARGET_K64F"],
- "is_disk_virtual": true,
- "default_toolchain": "ARM",
- "detect_code": ["0214"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH"
- ],
- "default_lib": "std",
- "release_versions": ["2", "5"],
- "device_name": "MK64FN1M0xxx12",
- "bootloader_supported": true
- },
- "RAPIDIOT": {
- "inherits": ["Target"],
- "public": false,
- "core": "null",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "macros": ["FSL_RTOS_MBED", "USE_EXTERNAL_RTC"],
- "default_toolchain": "ARM",
- "default_lib": "std",
- "forced_reset_timeout": 7,
- "release_versions": ["2", "5"]
- },
- "RAPIDIOT_K64F": {
- "inherits": ["RAPIDIOT"],
- "core": "Cortex-M4F",
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "MCU_K64F"
- ],
- "macros_add": ["CPU_MK64FN1M0VMD12", "TARGET_K64F"],
- "is_disk_virtual": true,
- "mbed_rom_start": "0x00014000",
- "mbed_rom_size": "0xEC000",
- "detect_code": ["0228"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH"
- ],
- "device_name": "MK64FN1M0xxx12",
- "bootloader_supported": true
- },
- "RAPIDIOT_KW41Z": {
- "inherits": ["RAPIDIOT"],
- "core": "Cortex-M0+",
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "KW41Z"
- ],
- "macros_add": ["CPU_MKW41Z512VHT4"],
- "is_disk_virtual": true,
- "mbed_rom_start": "0x00004000",
- "mbed_rom_size": "0x7C000",
- "detect_code": ["0234"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "TRNG",
- "STDIO_MESSAGES",
- "FLASH"
- ],
- "device_name": "MKW41Z512xxx4",
- "bootloader_supported": true
- },
- "K66F": {
- "supported_form_factors": ["ARDUINO"],
- "components_add": ["SD", "FLASHIAP"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": [
- "Freescale",
- "MCUXpresso_MCUS",
- "KSDK2_MCUS",
- "FRDM",
- "Freescale_EMAC",
- "PSA"
- ],
- "is_disk_virtual": true,
- "macros": ["CPU_MK66FN2M0VMD18", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "detect_code": ["0311"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "EMAC",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MK66FN2M0xxx18",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "K82F": {
- "supported_form_factors": ["ARDUINO"],
- "components_add": ["SPIF", "FLASHIAP"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": ["Freescale", "MCUXpresso_MCUS", "KSDK2_MCUS", "FRDM"],
- "is_disk_virtual": true,
- "macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "detect_code": ["0217"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH",
- "QSPI"
- ],
- "release_versions": ["2", "5"],
- "device_name": "MK82FN256xxx15"
- },
- "UBRIDGE": {
- "inherits": ["K82F"],
- "extra_labels_remove": ["FRDM"],
- "components_remove": ["SPIF"],
- "device_has_remove": ["QSPI"],
- "supported_form_factors": []
- },
- "FAMILY_STM32": {
- "inherits": ["Target"],
- "public": false,
- "extra_labels": ["STM"],
- "supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
- "macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
- "config": {
- "lse_available": {
- "help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LSI) will be used",
- "value": "1"
- },
- "lpuart_clock_source": {
- "help": "Define the LPUART clock source. Mask values: USE_LPUART_CLK_LSE, USE_LPUART_CLK_PCLK1, USE_LPUART_CLK_HSI",
- "value": "USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1"
- },
- "stdio_uart_tx": {
- "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden"
- },
- "stdio_uart_rx": {
- "help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden"
- },
- "lpticker_delay_ticks": {
- "help": "https://os.mbed.com/docs/latest/porting/low-power-ticker.html",
- "value": 1,
- "macro_name": "LPTICKER_DELAY_TICKS"
- },
- "lpticker_lptim_clock": {
- "help": "Default value for LPTIM clock (lpticker_lptim == 1). Value is the dividing factor. Choose 1, 2 or 4",
- "value": 1
- }
- },
- "overrides": {
- "deep-sleep-latency": 3
- },
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES"
- ]
- },
- "MIMXRT1050_EVK": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M7FD",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": ["NXP", "MCUXpresso_MCUS", "EVK", "MIMXRT1050", "IMX", "NXP_EMAC"],
- "is_disk_virtual": true,
- "macros": [
- "CPU_MIMXRT1052DVL6B",
- "FSL_RTOS_MBED",
- "XIP_BOOT_HEADER_ENABLE=1",
- "XIP_EXTERNAL_FLASH=1",
- "XIP_BOOT_HEADER_DCD_ENABLE=1",
- "SKIP_SYSCLK_INIT",
- "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE",
- "SDRAM_IS_SHAREABLE",
- "MBED_MPU_CUSTOM"
- ],
- "inherits": ["Target"],
- "detect_code": ["0227"],
- "device_has": [
- "RTC",
- "SLEEP",
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "EMAC",
- "I2C",
- "I2CSLAVE",
- "ERROR_RED",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2", "5"],
- "features": ["LWIP"],
- "device_name": "MIMXRT1052",
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "LPC54114": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
- "extra_labels": [
- "NXP",
- "MCUXpresso_MCUS",
- "LPC54114_M4",
- "LPCXpresso",
- "LPC"
- ],
- "is_disk_virtual": true,
- "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "detect_code": ["1054"],
- "device_has": [
- "USTICKER",
- "RTC",
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "post_binary_hook": { "function": "LPCTargetCode.lpc_patch" },
- "device_name": "LPC54114J256BD64"
- },
- "MCU_LPC546XX": {
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
- "extra_labels": [
- "NXP",
- "MCUXpresso_MCUS",
- "LPC",
- "NXP_EMAC"
- ],
- "is_disk_virtual": true,
- "public": false,
- "macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"],
- "inherits": ["Target"],
- "device_has": [
- "USTICKER",
- "RTC",
- "ANALOGIN",
- "EMAC",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES",
- "FLASH",
- "TRNG",
- "QSPI",
- "MPU"
- ],
- "device_name": "LPC54628J512ET180",
- "post_binary_hook": { "function": "LPCTargetCode.lpc_patch" },
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "LPC546XX": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_LPC546XX"],
- "extra_labels_add": ["LPCXpresso"],
- "detect_code": ["1056"],
- "release_versions": ["2", "5"],
- "components_add": ["QSPIF"]
- },
- "FF_LPC546XX": {
- "inherits": ["MCU_LPC546XX"],
- "detect_code": ["8081"],
- "device_has_remove": ["QSPI"],
- "release_versions": ["2", "5"]
- },
- "NUCLEO_F030R8": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M0",
- "extra_labels_add": ["STM32F0", "STM32F030R8"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0725"],
- "macros_add": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has_add": ["CRC"],
- "device_has_remove": ["LPTICKER"],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32F030R8"
- },
- "NUCLEO_F031K6": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels_add": ["STM32F0", "STM32F031K6"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0791"],
- "overrides": { "lse_available": 0 },
- "macros_add": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has_add": ["CRC"],
- "device_has_remove": ["LPTICKER"],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32F031K6"
- },
- "NUCLEO_F042K6": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0",
- "default_toolchain": "uARM",
- "extra_labels_add": ["STM32F0", "STM32F042K6"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0785"],
- "overrides": { "lse_available": 0 },
- "macros_add": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has_add": [
- "CAN",
- "CRC"
- ],
- "device_has_remove": ["LPTICKER"],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32F042K6"
- },
- "NUCLEO_F070RB": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M0",
- "extra_labels_add": ["STM32F0", "STM32F070RB"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0755"],
- "macros_add": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has_add": [
- "CRC",
- "SERIAL_ASYNCH",
- "FLASH"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F070RB"
- },
- "NUCLEO_F072RB": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M0",
- "extra_labels_add": ["STM32F0", "STM32F072RB"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0730"],
- "macros_add": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "FLASH"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F072RB"
- },
- "NUCLEO_F091RC": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M0",
- "extra_labels_add": ["STM32F0", "STM32F091RC"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0750"],
- "macros_add": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "FLASH"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F091RC"
- },
- "NUCLEO_F103RB": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M3",
- "extra_labels_add": ["STM32F1", "STM32F103RB"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (SYSCLK=72 MHz) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI (SYSCLK=64 MHz)",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "clock_source_usb": {
- "help": "In case of HSI clock source, to get 48 Mhz USB, SYSCLK has to be reduced from 64 to 48 MHz (set 0 for the max SYSCLK value)",
- "value": "0",
- "macro_name": "CLOCK_SOURCE_USB"
- }
- },
- "detect_code": ["0700"],
- "device_has_add": [
- "CAN",
- "SERIAL_ASYNCH",
- "FLASH"
- ],
- "device_has_remove": ["LPTICKER"],
- "release_versions": ["2", "5"],
- "device_name": "STM32F103RB"
- },
- "NUCLEO_F207ZG": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M3",
- "extra_labels_add": ["STM32F2", "STM32F207ZG", "STM_EMAC"],
- "config": {
- "d11_configuration": {
- "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
- "value": "PA_7",
- "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0835"],
- "macros_add": ["USBHOST_OTHER"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "EMAC",
- "SERIAL_ASYNCH",
- "FLASH",
- "TRNG",
- "MPU"
- ],
- "device_has_remove": ["LPTICKER"],
- "release_versions": ["2", "5"],
- "device_name": "STM32F207ZG",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NUCLEO_F302R8": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F3", "STM32F302x8", "STM32F302R8"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0705"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32F302R8"
- },
- "NUCLEO_F303K8": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F3", "STM32F303x8", "STM32F303K8"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "overrides": { "lse_available": 0 },
- "detect_code": ["0775"],
- "default_lib": "small",
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC"
- ],
- "release_versions": ["2"],
- "device_name": "STM32F303K8"
- },
- "NUCLEO_F303RE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303RE"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0745"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "bootloader_supported": true,
- "device_name": "STM32F303RE"
- },
- "NUCLEO_F303ZE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F3", "STM32F303xE", "STM32F303ZE"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0747"],
- "device_has_add": ["ANALOGOUT", "CAN", "CRC", "FLASH", "MPU"],
- "release_versions": ["2", "5"],
- "device_name": "STM32F303ZE"
- },
- "NUCLEO_F334R8": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F3", "STM32F334x8", "STM32F334R8"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0735"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32F334R8"
- },
- "NUCLEO_F401RE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401RE"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0720"],
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F401RE"
- },
- "STEVAL_3DP001V1": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401VE"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "HSE_VALUE=25000000"],
- "device_has_add": [
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "overrides": { "lse_available": 0 },
- "release_versions": ["2", "5"],
- "device_name": "STM32F401VE"
- },
- "NUCLEO_F410RB": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F410RB",
- "STM32F410xB",
- "STM32F410Rx"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0744"],
- "device_has_add": [
- "ANALOGOUT",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F410RB"
- },
- "NUCLEO_F411RE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE", "PSA"],
- "components_add": ["FLASHIAP"],
- "detect_code": ["0740"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "clock_source_usb": {
- "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 100 to 96 MHz (set 0 for the max SYSCLK value)",
- "value": "0",
- "macro_name": "CLOCK_SOURCE_USB"
- }
- },
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F411RE",
- "bootloader_supported": true
- },
- "NUCLEO_F412ZG": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F412xG", "STM32F412ZG"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0826"],
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "CAN",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F412ZG",
- "bootloader_supported": true
- },
- "MTB_MXCHIP_EMW3166": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F412xG",
- "STM32F412ZG",
- "WICED",
- "CYW43362"
- ],
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "CAN",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["5"],
- "device_name": "STM32F412ZG",
- "bootloader_supported": true,
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "USI_WM_BN_BM_22": {
- "inherits": ["FAMILY_STM32"],
- "components_add": ["SPIF", "FLASHIAP"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F412xG",
- "STM32F412ZG",
- "WICED",
- "CYW4343X",
- "CORDIO"
- ],
- "features": ["BLE", "STORAGE"],
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["5"],
- "device_name": "STM32F412ZG",
- "bootloader_supported": true,
- "public": false,
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "MTB_USI_WM_BN_BM_22": {
- "overrides": {
- "lse_available": 0
- },
- "inherits": ["USI_WM_BN_BM_22"]
- },
- "MTB_ADV_WISE_1530": {
- "inherits": ["USI_WM_BN_BM_22"],
- "config": {
- "led1": "PA_4",
- "led2": "PC_12",
- "led3": "NC"
- },
- "overrides": {
- "stdio_uart_tx": "PB_10",
- "stdio_uart_rx": "PC_11"
- }
- },
- "DISCO_F413ZH": {
- "components_add": ["QSPIF"],
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F413xx",
- "STM32F413ZH",
- "STM32F413xH"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0743"],
- "macros_add": [
- "MBED_TICKLESS",
- "USB_STM_HAL",
- "USBHOST_OTHER"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "QSPI",
- "MPU"
- ],
- "bootloader_supported": true,
- "release_versions": ["2", "5"],
- "device_name": "STM32F413ZH"
- },
- "NUCLEO_F413ZH": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F413xx",
- "STM32F413ZH",
- "STM32F413xH"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0743"],
- "macros_add": [
- "MBED_TICKLESS",
- "USB_STM_HAL",
- "USBHOST_OTHER"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "bootloader_supported": true,
- "release_versions": ["2", "5"],
- "device_name": "STM32F413ZH"
- },
- "ELMO_F411RE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "default_toolchain": "uARM",
- "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
- "detect_code": ["----"],
- "device_has_add": ["MPU"],
- "device_has_remove": ["SERIAL_FC"],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32F411RE"
- },
- "NUCLEO_F429ZI": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "config": {
- "d11_configuration": {
- "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
- "value": "PA_7",
- "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "clock_source_usb": {
- "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
- "value": "1",
- "macro_name": "CLOCK_SOURCE_USB"
- }
- },
- "extra_labels_add": [
- "STM32F4",
- "STM32F429",
- "STM32F429ZI",
- "STM32F429xx",
- "STM32F429xI",
- "STM_EMAC",
- "PSA"
- ],
- "components_add": ["FLASHIAP"],
- "macros_add": [
- "USB_STM_HAL",
- "USBHOST_OTHER"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "EMAC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "detect_code": ["0796"],
- "release_versions": ["2", "5"],
- "device_name": "STM32F429ZI",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NUCLEO_F439ZI": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "config": {
- "d11_configuration": {
- "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
- "value": "PA_7",
- "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "clock_source_usb": {
- "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
- "value": "1",
- "macro_name": "CLOCK_SOURCE_USB"
- }
- },
- "extra_labels_add": [
- "STM32F4",
- "STM32F439",
- "STM32F439ZI",
- "STM32F439xx",
- "STM32F439xI",
- "STM_EMAC"
- ],
- "macros_add": [
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "USB_STM_HAL",
- "USBHOST_OTHER"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "EMAC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "detect_code": ["0797"],
- "release_versions": ["2", "5"],
- "device_name": "STM32F439ZI",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NUCLEO_F446RE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446RE"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0777"],
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F446RE",
- "bootloader_supported": true
- },
- "NUCLEO_F446ZE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446ZE"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0778"],
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F446ZE"
- },
- "B96B_F446VE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F446xE", "STM32F446VE"],
- "detect_code": ["0840"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F446VE"
- },
- "NUCLEO_F746ZG": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M7F",
- "extra_labels_add": [
- "STM32F7",
- "STM32F746",
- "STM32F746xG",
- "STM32F746ZG",
- "STM_EMAC"
- ],
- "config": {
- "d11_configuration": {
- "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
- "value": "PA_7",
- "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS",
- "USBHOST_OTHER"
- ],
- "supported_form_factors": ["ARDUINO"],
- "detect_code": ["0816"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "EMAC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F746ZG",
- "bootloader_supported": true,
- "overrides": {
- "lpticker_delay_ticks": 4,
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NUCLEO_F756ZG": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M7F",
- "extra_labels_add": [
- "STM32F7",
- "STM32F756",
- "STM32F756xG",
- "STM32F756ZG",
- "STM_EMAC"
- ],
- "config": {
- "d11_configuration": {
- "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
- "value": "PA_7",
- "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS",
- "USBHOST_OTHER",
- "MBEDTLS_CONFIG_HW_SUPPORT"
- ],
- "supported_form_factors": ["ARDUINO"],
- "detect_code": ["0819"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "EMAC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F756ZG",
- "overrides": {
- "lpticker_delay_ticks": 4,
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NUCLEO_F767ZI": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M7FD",
- "extra_labels_add": [
- "STM32F7",
- "STM32F767",
- "STM32F767xI",
- "STM32F767ZI",
- "STM_EMAC"
- ],
- "config": {
- "flash_dual_bank": {
- "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
- "value": "0"
- },
- "d11_configuration": {
- "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
- "value": "PA_7",
- "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "supported_form_factors": ["ARDUINO"],
- "macros_add": [
- "MBED_TICKLESS",
- "USBHOST_OTHER"
- ],
- "detect_code": ["0818"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "EMAC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F767ZI",
- "bootloader_supported": true,
- "overrides": {
- "lpticker_delay_ticks": 4,
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NUCLEO_H743ZI": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M7FD",
- "extra_labels_add": [
- "STM32H7",
- "STM32H743",
- "STM32H743xI",
- "STM32H743ZI"
- ],
- "config": {
- "d11_configuration": {
- "help": "Value: PA_7 for the default board configuration, PB_5 in case of solder bridge update (SB121 off/ SB122 on)",
- "value": "PA_7",
- "macro_name": "STM32_D11_SPI_ETHERNET_PIN"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- },
- "hse_value": {
- "help": "HSE default value is 25MHz in HAL",
- "value": "8000000",
- "macro_name": "HSE_VALUE"
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "supported_form_factors": ["ARDUINO"],
- "detect_code": ["0813"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32H743ZI",
- "bootloader_supported": true
- },
- "NUCLEO_L011K4": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0+",
- "extra_labels_add": ["STM32L0", "STM32L011K4"],
- "supported_toolchains": ["uARM"],
- "default_toolchain": "uARM",
- "supported_form_factors": ["ARDUINO"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0780"],
- "device_has_add": [
- "CRC",
- "FLASH"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32L011K4"
- },
- "NUCLEO_L031K6": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0+",
- "extra_labels_add": ["STM32L0", "STM32L031K6"],
- "default_toolchain": "uARM",
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0790"],
- "device_has_add": [
- "CRC",
- "FLASH"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32L031K6"
- },
- "NUCLEO_L053R8": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M0+",
- "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053R8"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0715"],
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32L053R8"
- },
- "NUCLEO_L073RZ": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M0+",
- "extra_labels_add": ["STM32L0", "STM32L073RZ", "STM32L073xx"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0760"],
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L073RZ"
- },
- "NUCLEO_L152RE": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M3",
- "extra_labels_add": ["STM32L1", "STM32L152RE"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0710"],
- "device_has_add": [
- "ANALOGOUT",
- "SERIAL_ASYNCH",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L152RE"
- },
- "NUCLEO_L432KC": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L432xC", "STM32L432KC"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0770"],
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "SERIAL_ASYNCH",
- "CAN",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L432KC",
- "bootloader_supported": true
- },
- "NUCLEO_L433RC_P": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L433xC", "STM32L433RC"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0779"],
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "SERIAL_ASYNCH",
- "CAN",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L433RC",
- "bootloader_supported": true
- },
- "MTB_ADV_WISE_1510": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L443xC", "STM32L443RC"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "overrides": { "lse_available": 0 },
- "release_versions": ["5"],
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "SERIAL_ASYNCH",
- "CAN",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "device_has_remove": ["LPTICKER"],
- "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
- "device_name": "STM32L443RC",
- "detect_code": ["0458"],
- "bootloader_supported": true
- },
- "NUCLEO_L476RG": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L476RG", "STM32L476xG"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0765"],
- "macros_add": [
- "MBED_TICKLESS",
- "USBHOST_OTHER",
- "TWO_RAM_REGIONS"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L476RG",
- "bootloader_supported": true
- },
- "SILICA_SENSOR_NODE": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "default_toolchain": "GCC_ARM",
- "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476JG"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0766"],
- "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["5"],
- "device_name": "STM32L476JG"
- },
- "NUCLEO_L486RG": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0827"],
- "macros_add": [
- "MBED_TICKLESS",
- "USBHOST_OTHER",
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "TWO_RAM_REGIONS"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L486RG"
- },
- "MTB_ADV_WISE_1570": {
- "components_add": ["FLASHIAP"],
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32L4",
- "STM32L486RG",
- "STM32L486xG",
- "WISE_1570"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_HSE_XTAL",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "overrides": { "lpuart_clock_source": "USE_LPUART_CLK_HSI" },
- "detect_code": ["0460"],
- "macros_add": [
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "WISE_1570",
- "TWO_RAM_REGIONS"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "device_has_remove": ["LPTICKER"],
- "release_versions": ["5"],
- "device_name": "STM32L486RG",
- "bootloader_supported": true,
- "OUTPUT_EXT": "hex"
- },
- "ARCH_MAX": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "program_cycle_s": 2,
- "extra_labels_add": [
- "STM32F4",
- "STM32F407",
- "STM32F407xG",
- "STM32F407VG",
- "STM_EMAC"
- ],
- "device_has_add": ["ANALOGOUT", "TRNG", "FLASH", "EMAC", "MPU"],
- "device_has_remove": [
- "LPTICKER",
- "SERIAL_FC"
- ],
- "macros_add": ["USB_STM_HAL"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_HSE_XTAL",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "release_versions": ["2", "5"],
- "overrides": {"lse_available": 0},
- "device_name": "STM32F407VG",
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "WIO_3G": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "clock_source_usb": {
- "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
- "value": "1",
- "macro_name": "CLOCK_SOURCE_USB"
- },
- "modem_is_on_board": {
- "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD"
- },
- "modem_data_connection_type": {
- "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD_UART"
- }
- },
- "extra_labels_add": [
- "STM32F4",
- "STM32F439",
- "STM32F439VI",
- "STM32F439xx",
- "STM32F439xI"
- ],
- "macros_add": [
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "USB_STM_HAL",
- "USBHOST_OTHER"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "detect_code": ["9014"],
- "release_versions": ["2", "5"],
- "device_name" : "STM32F439VI",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "CELLULAR"
- }
- },
- "WIO_BG96": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "clock_source_usb": {
- "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
- "value": "0",
- "macro_name": "CLOCK_SOURCE_USB"
- },
- "modem_is_on_board": {
- "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD"
- },
- "modem_data_connection_type": {
- "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD_UART"
- }
- },
- "extra_labels_add": ["STM32F4", "STM32F439", "STM32F439VI", "STM32F439xx", "STM32F439xI"],
- "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT"],
- "device_has_add": [
- "ANALOGOUT",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "detect_code": ["9015"],
- "release_versions": ["2", "5"],
- "device_name" : "STM32F439VI",
- "components_add": ["SD"],
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "CELLULAR"
- }
- },
- "DISCO_F051R8": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0",
- "extra_labels_add": ["STM32F0", "STM32F051", "STM32F051R8"],
- "supported_toolchains": ["GCC_ARM"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "macros_add": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has_add": [
- "CRC",
- "MPU"
- ],
- "device_has_remove": ["LPTICKER"],
- "device_name": "STM32F051R8"
- },
- "DISCO_F100RB": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M3",
- "extra_labels_add": ["STM32F1", "STM32F100RB"],
- "supported_toolchains": ["GCC_ARM"],
- "device_has_add": [],
- "device_has_remove": ["LPTICKER"],
- "device_name": "STM32F100RB"
- },
- "DISCO_F303VC": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F3",
- "STM32F303",
- "STM32F303xC",
- "STM32F303VC"
- ],
- "overrides": { "lse_available": 0 },
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "MPU"
- ],
- "device_name": "STM32F303VC"
- },
- "DISCO_F334C8": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F3", "STM32F334x8", "STM32F334C8"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "overrides": { "lse_available": 0 },
- "detect_code": ["0810"],
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "SERIAL_ASYNCH"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32F334C8"
- },
- "DISCO_F407VG": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F407",
- "STM32F407xG",
- "STM32F407VG"
- ],
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "macros_add": ["USB_STM_HAL"],
- "overrides": { "lse_available": 0 },
- "device_has_add": ["ANALOGOUT", "TRNG", "FLASH", "MPU"],
- "release_versions": ["2", "5"],
- "device_name": "STM32F407VG"
- },
- "DISCO_F429ZI": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F429",
- "STM32F429ZI",
- "STM32F429xI",
- "STM32F429xx"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "clock_source_usb": {
- "help": "As 48 Mhz clock is configured for USB, SYSCLK has to be reduced from 180 to 168 MHz (set 0 for the max SYSCLK value)",
- "value": "1",
- "macro_name": "CLOCK_SOURCE_USB"
- }
- },
- "overrides": { "lse_available": 0 },
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F429ZI",
- "bootloader_supported": true
- },
- "DISCO_F469NI": {
- "components_add": ["QSPIF"],
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F469",
- "STM32F469NI",
- "STM32F469xI",
- "STM32F469xx"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "detect_code": ["0788"],
- "macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "TRNG",
- "FLASH",
- "QSPI",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F469NI",
- "bootloader_supported": true
- },
- "DISCO_L053C8": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0+",
- "extra_labels_add": ["STM32L0", "STM32L053x8", "STM32L053C8"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": {
- "lse_available": 0,
- "lpticker_delay_ticks": 4
- },
- "device_has_add": [
- "ANALOGOUT",
- "CRC",
- "FLASH",
- "MPU"
- ],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "STM32L053C8"
- },
- "DISCO_L072CZ_LRWAN1": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0+",
- "extra_labels_add": [
- "STM32L0",
- "STM32L072CZ",
- "STM32L072xZ",
- "STM32L072xx"
- ],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0833"],
- "device_has_add": [
- "ANALOGOUT",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L072CZ"
- },
- "MTB_MURATA_ABZ": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M0+",
- "extra_labels_add": [
- "STM32L0",
- "STM32L0x2xZ",
- "STM32L082CZ",
- "STM32L082xx"
- ],
- "detect_code": ["0456"],
- "device_has_add": [
- "ANALOGOUT",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "device_has_remove": ["LPTICKER"],
- "release_versions": ["5"],
- "device_name": "STM32L082CZ"
- },
- "DISCO_F746NG": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M7F",
- "extra_labels_add": [
- "STM32F7",
- "STM32F746",
- "STM32F746xG",
- "STM32F746NG",
- "STM_EMAC"
- ],
- "components_add": ["QSPIF"],
- "supported_form_factors": ["ARDUINO"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "usb_speed": {
- "help": "Select the USB speed/connector (0=FullSpeed, 1=HighSpeed)",
- "value": "1"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "detect_code": ["0815"],
- "macros_add": [
- "MBED_TICKLESS",
- "USB_STM_HAL",
- "USBHOST_OTHER"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "EMAC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "QSPI",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F746NG",
- "bootloader_supported": true,
- "overrides": {
- "lpticker_delay_ticks": 4,
- "network-default-interface-type": "ETHERNET"
- }
- },
- "DISCO_F769NI": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M7FD",
- "extra_labels_add": [
- "STM32F7",
- "STM32F769",
- "STM32F769xI",
- "STM32F769NI",
- "STM_EMAC"
- ],
- "components_add": ["QSPIF"],
- "supported_form_factors": ["ARDUINO"],
- "config": {
- "flash_dual_bank": {
- "help": "Default board configuration is Single Bank Flash. If you enable Dual Bank with ST Link Utility, set value to 1",
- "value": "0"
- },
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
- "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "detect_code": ["0817"],
- "macros_add": [
- "MBED_TICKLESS",
- "USB_STM_HAL",
- "USBHOST_OTHER"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "EMAC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU",
- "QSPI"
- ],
- "bootloader_supported": true,
- "release_versions": ["2", "5"],
- "device_name": "STM32F769NI",
- "overrides": {
- "lpticker_delay_ticks": 4,
- "network-default-interface-type": "ETHERNET"
- }
- },
- "DISCO_L475VG_IOT01A": {
- "components_add": ["QSPIF", "FLASHIAP"],
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "supported_form_factors": ["ARDUINO"],
- "detect_code": ["0764"],
- "macros_add": [
- "MBED_TICKLESS",
- "USBHOST_OTHER",
- "TWO_RAM_REGIONS"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "TRNG",
- "FLASH",
- "QSPI",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L475VG",
- "bootloader_supported": true
- },
- "DISCO_L476VG": {
- "components_add": ["QSPIF", "FLASHIAP"],
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0820"],
- "macros_add": [
- "MBED_TICKLESS",
- "USBHOST_OTHER",
- "TWO_RAM_REGIONS"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "TRNG",
- "FLASH",
- "QSPI",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L476VG",
- "bootloader_supported": true
- },
- "MTS_MDOT_F405RG": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F405RG"],
- "is_disk_virtual": true,
- "macros_add": ["HSE_VALUE=26000000"],
- "device_has_add": ["ANALOGOUT", "MPU"],
- "release_versions": ["2"],
- "device_name": "STM32F405RG"
- },
- "MTS_MDOT_F411RE": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F411RE"],
- "macros_add": [
- "HSE_VALUE=26000000",
- "USE_PLL_HSE_EXTC=0",
- "VECT_TAB_OFFSET=0x00010000"
- ],
- "post_binary_hook": {
- "function": "MTSCode.combine_bins_mts_dot",
- "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
- },
- "device_has_add": ["MPU"],
- "device_has_remove": [
- "SERIAL_FC"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F411RE"
- },
- "MTS_DRAGONFLY_F411RE": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F411RE"],
- "config": {
- "modem_is_on_board": {
- "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD"
- },
- "modem_data_connection_type": {
- "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD_UART"
- }
- },
- "overrides": { "lse_available": 0 },
- "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
- "post_binary_hook": {
- "function": "MTSCode.combine_bins_mts_dragonfly",
- "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
- },
- "device_has_add": ["MPU"],
- "device_has_remove": [
- "SERIAL_FC"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32F411RE"
- },
- "MTS_DRAGONFLY_L471QG": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32L4",
- "STM32L471QG",
- "STM32L471xG",
- "STM32L471xx"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "modem_is_on_board": {
- "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD"
- },
- "modem_data_connection_type": {
- "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD_UART"
- }
- },
- "macros_add": ["TWO_RAM_REGIONS"],
- "detect_code": ["0312"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L471QG",
- "bootloader_supported": true
- },
- "MTB_MTS_DRAGONFLY": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F411RE"],
- "config": {
- "modem_is_on_board": {
- "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD"
- },
- "modem_data_connection_type": {
- "help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD_UART"
- }
- },
- "overrides": {
- "lse_available": 0
- },
- "macros_add": ["HSE_VALUE=26000000", "VECT_TAB_OFFSET=0x08010000"],
- "device_has_add": ["MPU"],
- "device_has_remove": [
- "SERIAL_FC"
- ],
- "post_binary_hook": {
- "function": "MTSCode.combine_bins_mtb_mts_dragonfly",
- "toolchains": ["GCC_ARM", "ARM_STD", "ARM_MICRO", "IAR"]
- },
- "release_versions": ["2", "5"],
- "device_name": "STM32F411RE",
- "bootloader_supported": true
- },
- "XDOT_L151CC": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M3",
- "default_toolchain": "ARM",
- "extra_labels_add": ["STM32L1", "STM32L151CC"],
- "config": {
- "hse_value": {
- "value": "24000000",
- "macro_name": "HSE_VALUE"
- }
- },
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "device_has_add": ["ANALOGOUT", "FLASH", "MPU"],
- "device_has_remove": [
- "SERIAL_FC"
- ],
- "release_versions": ["5"],
- "device_name": "STM32L151CC",
- "bootloader_supported": true
- },
- "FF1705_L151CC": {
- "inherits": ["XDOT_L151CC"],
- "detect_code": ["8080"]
- },
- "MTB_MTS_XDOT": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M3",
- "default_toolchain": "ARM",
- "extra_labels_add": ["STM32L1", "STM32L151CC"],
- "config": {
- "hse_value": {
- "value": "24000000",
- "macro_name": "HSE_VALUE"
- }
- },
- "overrides": {
- "stdio_uart_tx": "PA_2",
- "stdio_uart_rx": "PA_3"
- },
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "device_has_add": ["ANALOGOUT", "FLASH", "MPU"],
- "device_has_remove": [
- "SERIAL_FC"
- ],
- "release_versions": ["5"],
- "device_name": "STM32L151CC",
- "bootloader_supported": true
- },
- "MTB_RAK811": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M3",
- "default_toolchain": "ARM",
- "extra_labels_add": ["STM32L1", "STM32L151xBA", "STM32L151CBA"],
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "device_has_add": ["ANALOGOUT", "MPU"],
- "device_has_remove": [
- "SERIAL_FC"
- ],
- "release_versions": ["5"],
- "device_name": "STM32L151CBxxA",
- "bootloader_supported": true
- },
- "MOTE_L152RC": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M3",
- "default_toolchain": "ARM",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels_add": ["STM32L1", "STM32L152RC"],
- "detect_code": ["4100"],
- "device_has_add": ["ANALOGOUT", "SERIAL_ASYNCH", "FLASH", "MPU"],
- "device_has_remove": ["SERIAL_FC"],
- "release_versions": ["2", "5"],
- "device_name": "STM32L152RC"
- },
- "DISCO_F401VC": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "default_toolchain": "GCC_ARM",
- "extra_labels_add": [
- "STM32F4",
- "STM32F401",
- "STM32F401xC",
- "STM32F401VC"
- ],
- "supported_toolchains": ["GCC_ARM"],
- "device_has_add": ["MPU"],
- "device_name": "STM32F401VC"
- },
- "MODULE_UBLOX_ODIN_W2": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M4F",
- "extra_labels_add": [
- "STM32F4",
- "STM32F439",
- "STM32F439ZI",
- "STM32F439xx",
- "STM32F439xI",
- "STM_EMAC",
- "CORDIO",
- "CORDIO_ODIN_W2"
- ],
- "macros": [
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "HSE_VALUE=24000000",
- "HSE_STARTUP_TIMEOUT=5000",
- "CB_INTERFACE_SDIO",
- "CB_CHIP_WL18XX",
- "SUPPORT_80211D_ALWAYS",
- "WLAN_ENABLED",
- "CB_FEATURE_802DOT11W",
- "CB_FEATURE_802DOT11R",
- "MBEDTLS_ARC4_C",
- "MBEDTLS_DES_C",
- "MBEDTLS_MD4_C",
- "MBEDTLS_MD5_C",
- "MBEDTLS_SHA1_C",
- "MBED_MPU_CUSTOM"
- ],
- "device_has_add": [
- "CAN",
- "EMAC",
- "TRNG",
- "FLASH",
- "WIFI",
- "SERIAL"
- ],
- "features": ["BLE"],
- "device_has_remove": [],
- "device_name": "STM32F439ZI",
- "public": false,
- "bootloader_supported": true,
- "config": {
- "BLE_STACK_UBX": {
- "help": "It should be set to true to enable ublox ODIN own stack/driver rather than CORDIO",
- "value": false,
- "macro_name": "BLE_STACK_UBX"
- }
- },
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "UBLOX_EVK_ODIN_W2": {
- "inherits": ["MODULE_UBLOX_ODIN_W2"],
- "supported_form_factors": ["ARDUINO"],
- "release_versions": ["5"],
- "device_has_remove": [],
- "extra_labels_add": ["PSA"],
- "components_add": ["FLASHIAP"],
- "config": {
- "stdio_uart_tx_help": {
- "help": "Value: D8(default) or D1"
- },
- "stdio_uart_rx_help": {
- "help": "Value: D2(default) or D0"
- }
- },
- "overrides": {
- "stdio_uart_tx": "D8",
- "stdio_uart_rx": "D2"
- }
- },
- "MBED_CONNECT_ODIN": {
- "inherits": ["MODULE_UBLOX_ODIN_W2"],
- "release_versions": ["5"],
- "config": {
- "stdio_uart_tx_help": {
- "help": "Value: PA_9(default) or PD_8"
- },
- "stdio_uart_rx_help": {
- "help": "Value: PA_10(default) or PD_9"
- }
- },
- "overrides": {
- "stdio_uart_tx": "PA_9",
- "stdio_uart_rx": "PA_10"
- }
- },
- "MTB_UBLOX_ODIN_W2": {
- "inherits": ["MODULE_UBLOX_ODIN_W2"],
- "device_has_add": [],
- "overrides": {"lse_available": 0},
- "release_versions": ["5"]
- },
- "UBLOX_C030": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "extra_labels_add": [
- "STM32F4",
- "STM32F437",
- "STM32F437VG",
- "STM32F437xx",
- "STM32F437xG",
- "STM_EMAC"
- ],
- "config": {
- "modem_is_on_board": {
- "help": "Value: Tells the build system that the modem is on-board as oppose to a plug-in shield/module.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD"
- },
- "modem_data_connection_type": {
- "help": "Value: Defines how the modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
- "value": 1,
- "macro_name": "MODEM_ON_BOARD_UART"
- }
- },
- "macros_add": [
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "HSE_VALUE=12000000",
- "GNSSBAUD=9600"
- ],
- "device_has_add": [
- "ANALOGOUT",
- "EMAC",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "public": false,
- "device_name": "STM32F437VG",
- "bootloader_supported": true,
- "overrides": {
- "lse_available": 0,
- "network-default-interface-type": "ETHERNET"
- }
- },
- "UBLOX_C030_U201": {
- "inherits": ["UBLOX_C030"],
- "release_versions": ["5"]
- },
- "UBLOX_C030_N211": {
- "inherits": ["UBLOX_C030"],
- "release_versions": ["5"]
- },
- "UBLOX_C030_R41XM": {
- "inherits": ["UBLOX_C030"],
- "release_versions": ["5"]
- },
- "UBLOX_C030_R410M": {
- "inherits": ["UBLOX_C030_R41XM"],
- "release_versions": ["5"]
- },
- "UBLOX_C030_R412M": {
- "inherits": ["UBLOX_C030_R41XM"],
- "release_versions": ["5"]
- },
- "NZ32_SC151": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M3",
- "default_toolchain": "uARM",
- "program_cycle_s": 1.5,
- "extra_labels_add": ["STM32L1", "STM32L151RC"],
- "overrides": { "lse_available": 0 },
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
- "device_has_add": ["ANALOGOUT", "MPU"],
- "default_lib": "small",
- "device_name": "STM32L151RC"
- },
- "MCU_NRF51": {
- "inherits": ["Target"],
- "core": "Cortex-M0",
- "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
- "macros": [
- "NRF51",
- "NRF5x",
- "TARGET_NRF51822",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "MERGE_BOOTLOADER": false,
- "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822"],
- "OUTPUT_EXT": "hex",
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "GCC_ARM"],
- "public": false,
- "MERGE_SOFT_DEVICE": true,
- "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
- {
- "boot": "s130_nrf51_1.0.0_bootloader.hex",
- "name": "s130_nrf51_1.0.0_softdevice.hex",
- "offset": 114688
- },
- {
- "boot": "s110_nrf51822_8.0.0_bootloader.hex",
- "name": "s110_nrf51822_8.0.0_softdevice.hex",
- "offset": 98304
- },
- {
- "boot": "s110_nrf51822_7.1.0_bootloader.hex",
- "name": "s110_nrf51822_7.1.0_softdevice.hex",
- "offset": 90112
- },
- {
- "boot": "s110_nrf51822_7.0.0_bootloader.hex",
- "name": "s110_nrf51822_7.0.0_softdevice.hex",
- "offset": 90112
- },
- {
- "boot": "s110_nrf51822_6.0.0_bootloader.hex",
- "name": "s110_nrf51822_6.0.0_softdevice.hex",
- "offset": 81920
- }
- ],
- "detect_code": ["1070"],
- "post_binary_hook": {
- "function": "MCU_NRF51Code.binary_hook",
- "toolchains": ["ARM_STD", "GCC_ARM"]
- },
- "program_cycle_s": 6,
- "features": ["BLE"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ]
- },
- "MCU_NRF51_16K_BASE": {
- "inherits": ["MCU_NRF51"],
- "extra_labels_add": ["MCU_NORDIC_16K", "MCU_NRF51_16K"],
- "macros_add": ["TARGET_MCU_NORDIC_16K", "TARGET_MCU_NRF51_16K"],
- "public": false,
- "default_lib": "small"
- },
- "MCU_NRF51_16K_BOOT_BASE": {
- "inherits": ["MCU_NRF51_16K_BASE"],
- "MERGE_BOOTLOADER": true,
- "extra_labels_add": ["MCU_NRF51_16K_BOOT"],
- "macros_add": ["TARGET_MCU_NRF51_16K_BOOT", "TARGET_OTA_ENABLED"],
- "public": false
- },
- "MCU_NRF51_16K_OTA_BASE": {
- "inherits": ["MCU_NRF51_16K_BASE"],
- "public": false,
- "extra_labels_add": ["MCU_NRF51_16K_OTA"],
- "macros_add": ["TARGET_MCU_NRF51_16K_OTA", "TARGET_OTA_ENABLED"],
- "MERGE_SOFT_DEVICE": false
- },
- "MCU_NRF51_16K": {
- "inherits": ["MCU_NRF51_16K_BASE"],
- "extra_labels_add": ["MCU_NRF51_16K_S130"],
- "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
- "public": false
- },
- "MCU_NRF51_S110": {
- "extra_labels_add": ["MCU_NRF51_16K_S110"],
- "macros_add": ["TARGET_MCU_NRF51_16K_S110"],
- "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
- {
- "name": "s110_nrf51822_8.0.0_softdevice.hex",
- "boot": "s110_nrf51822_8.0.0_bootloader.hex",
- "offset": 98304
- },
- {
- "name": "s110_nrf51822_7.1.0_softdevice.hex",
- "boot": "s110_nrf51822_7.1.0_bootloader.hex",
- "offset": 90112
- }
- ],
- "public": false
- },
- "MCU_NRF51_16K_S110": {
- "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BASE"],
- "public": false
- },
- "MCU_NRF51_16K_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT_BASE"],
- "extra_labels_add": ["MCU_NRF51_16K_S130"],
- "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
- "public": false
- },
- "MCU_NRF51_16K_BOOT_S110": {
- "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_BOOT_BASE"],
- "public": false
- },
- "MCU_NRF51_16K_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA_BASE"],
- "extra_labels_add": ["MCU_NRF51_16K_S130"],
- "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
- "public": false
- },
- "MCU_NRF51_16K_OTA_S110": {
- "inherits": ["MCU_NRF51_S110", "MCU_NRF51_16K_OTA_BASE"],
- "public": false
- },
- "MCU_NRF51_32K": {
- "inherits": ["MCU_NRF51"],
- "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
- "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
- "public": false
- },
- "MCU_NRF51_32K_BOOT": {
- "inherits": ["MCU_NRF51_32K"],
- "MERGE_BOOTLOADER": true,
- "extra_labels_add": ["MCU_NRF51_32K_BOOT"],
- "macros_add": ["TARGET_MCU_NRF51_32K_BOOT", "TARGET_OTA_ENABLED"],
- "public": false
- },
- "MCU_NRF51_32K_OTA": {
- "inherits": ["MCU_NRF51_32K"],
- "public": false,
- "extra_labels_add": ["MCU_NRF51_32K_OTA"],
- "macros_add": ["TARGET_MCU_NRF51_32K_OTA", "TARGET_OTA_ENABLED"],
- "MERGE_SOFT_DEVICE": false
- },
- "NRF51822": {
- "inherits": ["MCU_NRF51_16K"],
- "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
- "macros_add": ["TARGET_NRF51822_MKIT"],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "NRF51822_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
- "macros_add": ["TARGET_NRF51822_MKIT"]
- },
- "NRF51822_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
- "macros_add": ["TARGET_NRF51822_MKIT"]
- },
- "ARCH_BLE": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K"],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "ARCH_BLE_BOOT": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["ARCH_BLE"],
- "macros_add": ["TARGET_ARCH_BLE"]
- },
- "ARCH_BLE_OTA": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["ARCH_BLE"],
- "macros_add": ["TARGET_ARCH_BLE"]
- },
- "ARCH_LINK": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K"],
- "extra_labels_add": ["ARCH_BLE"],
- "macros_add": ["TARGET_ARCH_BLE"]
- },
- "ARCH_LINK_BOOT": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
- "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
- },
- "ARCH_LINK_OTA": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
- "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
- },
- "SEEED_TINY_BLE": {
- "inherits": ["MCU_NRF51_16K"],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "SEEED_TINY_BLE_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["SEEED_TINY_BLE"],
- "macros_add": ["TARGET_SEEED_TINY_BLE"]
- },
- "SEEED_TINY_BLE_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["SEEED_TINY_BLE"],
- "macros_add": ["TARGET_SEEED_TINY_BLE"]
- },
- "HRM1017": {
- "inherits": ["MCU_NRF51_16K"],
- "macros_add": ["TARGET_NRF_LFCLK_RC"],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "HRM1017_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["HRM1017"],
- "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
- },
- "HRM1017_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["HRM1017"],
- "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
- },
- "RBLAB_NRF51822": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K"],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "RBLAB_NRF51822_BOOT": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["RBLAB_NRF51822"],
- "macros_add": ["TARGET_RBLAB_NRF51822"]
- },
- "RBLAB_NRF51822_OTA": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["RBLAB_NRF51822"],
- "macros_add": ["TARGET_RBLAB_NRF51822"]
- },
- "RBLAB_BLENANO": {
- "inherits": ["MCU_NRF51_16K"],
- "release_versions": ["2"]
- },
- "RBLAB_BLENANO_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["RBLAB_BLENANO"],
- "macros_add": ["TARGET_RBLAB_BLENANO"]
- },
- "RBLAB_BLENANO_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["RBLAB_BLENANO"],
- "macros_add": ["TARGET_RBLAB_BLENANO"]
- },
- "RBLAB_BLENANO2": {
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "NRF51822_Y5_MBUG": {
- "inherits": ["MCU_NRF51_16K"]
- },
- "WALLBOT_BLE": {
- "inherits": ["MCU_NRF51_16K"],
- "release_versions": ["2"]
- },
- "WALLBOT_BLE_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["WALLBOT_BLE"],
- "macros_add": ["TARGET_WALLBOT_BLE"]
- },
- "WALLBOT_BLE_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["WALLBOT_BLE"],
- "macros_add": ["TARGET_WALLBOT_BLE"]
- },
- "DELTA_DFCM_NNN40": {
- "inherits": ["MCU_NRF51_32K"],
- "program_cycle_s": 10,
- "macros_add": ["TARGET_NRF_LFCLK_RC"],
- "device_has": [
- "ANALOGIN",
- "DEBUG_AWARENESS",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "DELTA_DFCM_NNN40_BOOT": {
- "inherits": ["MCU_NRF51_32K_BOOT"],
- "program_cycle_s": 10,
- "extra_labels_add": ["DELTA_DFCM_NNN40"],
- "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
- },
- "DELTA_DFCM_NNN40_OTA": {
- "inherits": ["MCU_NRF51_32K_OTA"],
- "program_cycle_s": 10,
- "extra_labels_add": ["DELTA_DFCM_NNN40"],
- "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
- },
- "DELTA_DFCM_NNN50": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE"
- ],
- "device_name": "nRF51822_xxAC"
- },
- "DELTA_DFCM_NNN50_BOOT": {
- "supported_form_factors": ["ARDUINO"],
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- "extra_labels_add": ["DELTA_DFCM_NNN50"],
- "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
- },
- "DELTA_DFCM_NNN50_OTA": {
- "supported_form_factors": ["ARDUINO"],
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- "extra_labels_add": ["DELTA_DFCM_NNN50"],
- "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
- },
- "NRF51_DK_LEGACY": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K"],
- "extra_labels_add": ["NRF51_DK"]
- },
- "NRF51_DK_BOOT": {
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- "inherits": ["MCU_NRF51_32K_BOOT"],
- "extra_labels_add": ["NRF51_DK"],
- "macros_add": ["TARGET_NRF51_DK"]
- },
- "NRF51_DK_OTA": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K_OTA"],
- "extra_labels_add": ["NRF51_DK"],
- "macros_add": ["TARGET_NRF51_DK"]
- },
- "NRF51_DONGLE_LEGACY": {
- "inherits": ["MCU_NRF51_32K"],
- "extra_labels_add": ["NRF51_DONGLE"],
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- "device_name": "nRF51822_xxAA"
- },
- "NRF51_DONGLE_BOOT": {
- "inherits": ["MCU_NRF51_32K_BOOT"],
- "extra_labels_add": ["NRF51_DONGLE"],
- "macros_add": ["TARGET_NRF51_DONGLE"]
- },
- "NRF51_DONGLE_OTA": {
- "inherits": ["MCU_NRF51_32K_OTA"],
- "extra_labels_add": ["NRF51_DONGLE"],
- "macros_add": ["TARGET_NRF51_DONGLE"]
- },
- "NRF51_MICROBIT": {
- "inherits": ["MCU_NRF51_16K_S110"],
- "macros_add": ["TARGET_NRF_LFCLK_RC"],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "NRF51_MICROBIT_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT_S110"],
- "extra_labels_add": ["NRF51_MICROBIT"],
- "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
- },
- "NRF51_MICROBIT_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA_S110"],
- "extra_labels_add": ["NRF51_MICROBIT"],
- "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
- },
- "NRF51_MICROBIT_B": {
- "inherits": ["MCU_NRF51_16K"],
- "extra_labels_add": ["NRF51_MICROBIT"],
- "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"],
- "release_versions": ["2"]
- },
- "NRF51_MICROBIT_B_BOOT": {
- "inherits": ["MCU_NRF51_16K_BOOT"],
- "extra_labels_add": ["NRF51_MICROBIT"],
- "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
- },
- "NRF51_MICROBIT_B_OTA": {
- "inherits": ["MCU_NRF51_16K_OTA"],
- "extra_labels_add": ["NRF51_MICROBIT"],
- "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
- },
- "MTM_MTCONNECT04S": {
- "inherits": ["MCU_NRF51_32K"],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAA"
- },
- "MTM_MTCONNECT04S_BOOT": {
- "inherits": ["MCU_NRF51_32K_BOOT"],
- "extra_labels_add": ["MTM_CONNECT04S"],
- "macros_add": ["TARGET_MTM_CONNECT04S"]
- },
- "MTM_MTCONNECT04S_OTA": {
- "inherits": ["MCU_NRF51_32K_OTA"],
- "extra_labels_add": ["MTM_CONNECT04S"],
- "macros_add": ["TARGET_MTM_CONNECT04S"]
- },
- "MTB_LAIRD_BL600": {
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
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- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE"
- ],
- "device_name": "nRF51822_xxAA",
- "release_versions": ["5"],
- "extra_labels_add": ["MTB_LAIRD_BL600"],
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- "usb_tx": {
- "help": "Value SIO_21",
- "value": "SIO_21"
- },
- "usb_rx": {
- "help": "Value SIO_22",
- "value": "SIO_22"
- },
- "stdio_uart": {
- "help": "Value: UART_0",
- "value": "UART_0",
- "macro_name": "STDIO_UART"
- }
- },
- "overrides": {
- "uart_hwfc": 0
- }
- },
- "TY51822R3": {
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
- "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE"
- ],
- "detect_code": ["1019"],
- "release_versions": ["2", "5"],
- "overrides": { "uart_hwfc": 0 },
- "device_name": "nRF51822_xxAA"
- },
- "TY51822R3_BOOT": {
- "inherits": ["MCU_NRF51_32K_BOOT"],
- "extra_labels_add": ["TY51822R3"],
- "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
- },
- "TY51822R3_OTA": {
- "inherits": ["MCU_NRF51_32K_OTA"],
- "extra_labels_add": ["NRF51_DK"],
- "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
- },
- "ARM_MPS2_Target": {
- "inherits": ["Target"],
- "public": false,
- "device_has": [
- "AACI",
- "ANALOGIN",
- "CLCD",
- "ETHERNET",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SERIAL_FC",
- "SPI",
- "SPISLAVE",
- "TSC"
- ]
- },
- "ARM_MPS2_M0": {
- "inherits": ["ARM_MPS2_Target"],
- "core": "Cortex-M0",
- "supported_toolchains": ["ARM"],
- "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
- "macros": [
- "CMSDK_CM0",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "device_has": [
- "AACI",
- "ANALOGIN",
- "CLCD",
- "ETHERNET",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "MPU"
- ],
- "release_versions": ["2"]
- },
- "ARM_MPS2_M0P": {
- "inherits": ["ARM_MPS2_Target"],
- "core": "Cortex-M0+",
- "supported_toolchains": ["ARM"],
- "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0P"],
- "macros": ["CMSDK_CM0plus"],
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- "AACI",
- "ANALOGIN",
- "CLCD",
- "ETHERNET",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "MPU"
- ],
- "release_versions": ["2"]
- },
- "ARM_MPS2_M3": {
- "inherits": ["ARM_MPS2_Target"],
- "core": "Cortex-M3",
- "supported_toolchains": ["ARM"],
- "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M3"],
- "macros": ["CMSDK_CM3"],
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- "AACI",
- "ANALOGIN",
- "CLCD",
- "ETHERNET",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "MPU"
- ],
- "release_versions": ["2"]
- },
- "ARM_MPS2_M4": {
- "inherits": ["ARM_MPS2_Target"],
- "core": "Cortex-M4F",
- "supported_toolchains": ["ARM"],
- "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M4"],
- "macros": ["CMSDK_CM4"],
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- "AACI",
- "ANALOGIN",
- "CLCD",
- "ETHERNET",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "MPU"
- ],
- "release_versions": ["2"]
- },
- "ARM_MPS2_M7": {
- "inherits": ["ARM_MPS2_Target"],
- "core": "Cortex-M7",
- "supported_toolchains": ["ARM"],
- "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M7"],
- "macros": ["CMSDK_CM7"],
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- "AACI",
- "ANALOGIN",
- "CLCD",
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- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "MPU"
- ],
- "release_versions": ["2"]
- },
- "ARM_IOTSS_Target": {
- "inherits": ["Target"],
- "public": false,
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- "AACI",
- "ANALOGIN",
- "CLCD",
- "ETHERNET",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "MPU"
- ]
- },
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- "inherits": ["ARM_IOTSS_Target"],
- "core": "Cortex-M3",
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- "macros": ["CMSDK_BEID"],
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- "AACI",
- "ANALOGIN",
- "CLCD",
- "ETHERNET",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "MPU"
- ],
- "release_versions": ["2"]
- },
- "ARM_CM3DS_MPS2": {
- "inherits": ["ARM_IOTSS_Target"],
- "core": "Cortex-M3",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "components_add": ["SMSC9220"],
- "extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
- "OUTPUT_EXT": "elf",
- "macros": ["CMSDK_CM3DS"],
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- "ANALOGIN",
- "EMAC",
- "FLASH",
- "I2C",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "RTC",
- "SERIAL",
- "SLEEP",
- "SPI",
- "TRNG",
- "USTICKER",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "copy_method": "mps2",
- "reset_method": "reboot.txt",
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- "target.network-default-interface-type": "ETHERNET"
- }
- },
- "ARM_BEETLE_SOC": {
- "inherits": ["ARM_IOTSS_Target"],
- "core": "Cortex-M3",
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- "default_toolchain": "ARM",
- "extra_labels": ["ARM_SSG", "BEETLE"],
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- "CMSDK_BEETLE",
- "WSF_MS_PER_TICK=20",
- "WSF_TOKEN_ENABLED=FALSE",
- "WSF_TRACE_ENABLED=TRUE",
- "WSF_ASSERT_ENABLED=FALSE",
- "WSF_PRINTF_MAX_LEN=128",
- "ASIC",
- "CONFIG_HOST_REV=0x20",
- "CONFIG_ALLOW_DEEP_SLEEP=FALSE",
- "HCI_VS_TARGET",
- "CONFIG_ALLOW_SETTING_WRITE=TRUE",
- "WSF_MAX_HANDLERS=20",
- "NO_LEDS"
- ],
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- "CLCD",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "MPU"
- ],
- "features": ["BLE"],
- "release_versions": ["2", "5"]
- },
- "RZ_A1XX": {
- "inherits": ["Target"],
- "core": "Cortex-A9",
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "extra_labels": ["RENESAS", "RZ_A1XX"],
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- "SLEEP",
- "USTICKER",
- "RTC",
- "ANALOGIN",
- "CAN",
- "ETHERNET",
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- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES"
- ],
- "program_cycle_s": 2,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "RZ_A1H": {
- "inherits": ["RZ_A1XX"],
- "supported_form_factors": ["ARDUINO"],
- "extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"],
- "components_add": ["SD"],
- "device_has_add": ["EMAC", "FLASH", "LPTICKER"],
- "release_versions": ["2", "5"],
- "device_name": "R7S72100",
- "bootloader_supported": true
- },
- "VK_RZ_A1H": {
- "inherits": ["RZ_A1XX"],
- "extra_labels_add": ["RZA1H", "VKRZA1H", "RZ_A1_EMAC"],
- "device_has_add": ["EMAC"],
- "release_versions": ["2", "5"]
- },
- "GR_LYCHEE": {
- "inherits": ["RZ_A1XX"],
- "supported_form_factors": ["ARDUINO"],
- "extra_labels_add": ["RZA1UL", "MBRZA1LU"],
- "components_add": ["SD"],
- "device_has_add": ["TRNG", "FLASH", "LPTICKER"],
- "device_has_remove": ["ETHERNET"],
- "release_versions": ["2", "5"],
- "device_name": "R7S72103",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": null
- }
- },
- "MAXWSNENV": {
- "inherits": ["Target"],
- "core": "Cortex-M3",
- "macros": ["__SYSTEM_HFX=24000000"],
- "extra_labels": ["Maxim", "MAX32610"],
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "STDIO_MESSAGES"
- ],
- "features": ["BLE"],
- "release_versions": []
- },
- "MAX32600MBED": {
- "inherits": ["Target"],
- "core": "Cortex-M3",
- "macros": ["__SYSTEM_HFX=24000000"],
- "extra_labels": ["Maxim", "MAX32600"],
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2", "5"]
- },
- "MAX32620HSP": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "extra_labels": ["Maxim", "MAX32620"],
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "STDIO_MESSAGES"
- ],
- "features": ["BLE"],
- "release_versions": []
- },
- "MAX32620FTHR": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "macros": [
- "__SYSTEM_HFX=96000000",
- "TARGET=MAX32620",
- "TARGET_REV=0x4332",
- "OPEN_DRAIN_LEDS"
- ],
- "extra_labels": ["Maxim", "MAX32620C"],
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": [
- "ANALOGIN",
- "FLASH",
- "I2C",
- "INTERRUPTIN",
- "LPTICKER",
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- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "STDIO_MESSAGES",
- "USTICKER"
- ],
- "release_versions": ["2", "5"]
- },
- "SDT32620B": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "macros": [
- "__SYSTEM_HFX=96000000",
- "TARGET=MAX32620",
- "TARGET_REV=0x4332",
- "OPEN_DRAIN_LEDS"
- ],
- "detect_code": ["3101"],
- "extra_labels": ["Maxim", "MAX32620C"],
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": [
- "ANALOGIN",
- "FLASH",
- "I2C",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "STDIO_MESSAGES",
- "USTICKER"
- ],
- "release_versions": ["2", "5"]
- },
- "MAX32625_BASE": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "macros": ["TARGET=MAX32625", "TARGET_REV=0x4132", "OPEN_DRAIN_LEDS"],
- "extra_labels": ["Maxim", "MAX32625"],
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "STDIO_MESSAGES",
- "USTICKER"
- ],
- "device_name": "MAX32625",
- "release_versions": ["2", "5"],
- "public": false
- },
- "MAX32625MBED": {
- "inherits": ["MAX32625_BASE"],
- "extra_labels_add": ["MAX32625_NO_BOOT"]
- },
- "SDT32625B": {
- "inherits": ["MAX32625_BASE"],
- "extra_labels_add": ["MAX32625_NO_BOOT"],
- "detect_code": ["3102"]
- },
- "MAX32625PICO": {
- "inherits": ["MAX32625_BASE"],
- "extra_labels_add": ["MAX32625_BOOT"],
- "bootloader_supported": true
- },
- "MAX32625NEXPAQ": {
- "inherits": ["MAX32625_BASE"]
- },
- "MAX32630FTHR": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "macros": [
- "__SYSTEM_HFX=96000000",
- "TARGET=MAX32630",
- "TARGET_REV=0x4132",
- "BLE_HCI_UART",
- "OPEN_DRAIN_LEDS"
- ],
- "extra_labels": ["Maxim", "MAX32630"],
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SPI",
- "STDIO_MESSAGES",
- "USTICKER",
- "MPU"
- ],
- "features": ["BLE"],
- "release_versions": ["2", "5"]
- },
- "EFM32": {
- "inherits": ["Target"],
- "extra_labels": ["Silicon_Labs", "EFM32"],
- "macros": [
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "MBED_TICKLESS",
- "EM_MSC_RUN_FROM_FLASH"
- ],
- "public": false
- },
- "EFM32GG990F1024": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
- "core": "Cortex-M3",
- "macros_add": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFM32GG990F1024",
- "public": false,
- "bootloader_supported": true
- },
- "EFM32GG_STK3700": {
- "inherits": ["EFM32GG990F1024"],
- "progen": { "target": "efm32gg-stk" },
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- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "FLASH",
- "ITM",
- "MPU"
- ],
- "forced_reset_timeout": 2,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "48000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "21000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
- "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PF7",
- "macro_name": "EFM_BC_EN"
- }
- }
- },
- "EFM32LG990F256": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
- "core": "Cortex-M3",
- "macros_add": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFM32LG990F256",
- "public": false,
- "bootloader_supported": true
- },
- "EFM32LG_STK3600": {
- "inherits": ["EFM32LG990F256"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 2,
- "device_name": "EFM32LG990F256",
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "48000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "21000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
- "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PF7",
- "macro_name": "EFM_BC_EN"
- }
- }
- },
- "EFM32WG990F256": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
- "core": "Cortex-M4F",
- "macros_add": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFM32WG990F256",
- "public": false,
- "bootloader_supported": true
- },
- "EFM32WG_STK3800": {
- "inherits": ["EFM32WG990F256"],
- "progen": { "target": "efm32wg-stk" },
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 2,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "48000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "21000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
- "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PF7",
- "macro_name": "EFM_BC_EN"
- }
- }
- },
- "EFM32ZG222F32": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "macros_add": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
- "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "EFM32ZG222F32",
- "public": false
- },
- "EFM32ZG_STK3200": {
- "inherits": ["EFM32ZG222F32"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER"
- ],
- "forced_reset_timeout": 2,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "24000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "21000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
- "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PA9",
- "macro_name": "EFM_BC_EN"
- }
- }
- },
- "EFM32HG322F64": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
- "core": "Cortex-M0+",
- "default_toolchain": "uARM",
- "macros_add": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
- "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
- "default_lib": "small",
- "release_versions": ["2"],
- "device_name": "EFM32HG322F64",
- "public": false
- },
- "EFM32HG_STK3400": {
- "inherits": ["EFM32HG322F64"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER"
- ],
- "forced_reset_timeout": 2,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "24000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "21000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
- "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PA9",
- "macro_name": "EFM_BC_EN"
- }
- }
- },
- "EFM32PG1B100F256GM32": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
- "core": "Cortex-M4F",
- "macros_add": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFM32PG1B100F256GM32",
- "public": false,
- "bootloader_supported": true
- },
- "EFM32PG_STK3401": {
- "inherits": ["EFM32PG1B100F256GM32"],
- "device_has": [
- "ANALOGIN",
- "CRC",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 2,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "40000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "32000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
- "value": "cmuHFRCOFreq_32M0Hz",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PA5",
- "macro_name": "EFM_BC_EN"
- }
- }
- },
- "EFR32MG1P132F256GM48": {
- "inherits": ["EFM32"],
- "extra_labels_add": [
- "EFR32MG1",
- "EFR32_1",
- "256K",
- "SL_RAIL",
- "SL_CRYPTO"
- ],
- "core": "Cortex-M4F",
- "macros_add": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFR32MG1P132F256GM48",
- "public": false,
- "bootloader_supported": true
- },
- "EFR32MG1P233F256GM48": {
- "inherits": ["EFM32"],
- "extra_labels_add": [
- "EFR32MG1",
- "EFR32_1",
- "256K",
- "SL_RAIL",
- "SL_CRYPTO"
- ],
- "core": "Cortex-M4F",
- "macros_add": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "public": false,
- "bootloader_supported": true
- },
- "EFR32MG1_BRD4150": {
- "inherits": ["EFR32MG1P132F256GM48"],
- "device_has": [
- "802_15_4_PHY",
- "ANALOGIN",
- "CRC",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 2,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "38400000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "32000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
- "value": "cmuHFRCOFreq_32M0Hz",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PA5",
- "macro_name": "EFM_BC_EN"
- }
- },
- "overrides": {
- "network-default-interface-type": "MESH"
- },
- "public": false
- },
- "TB_SENSE_1": {
- "inherits": ["EFR32MG1P233F256GM48"],
- "device_has": [
- "802_15_4_PHY",
- "ANALOGIN",
- "CRC",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 5,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "38400000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "32000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
- "value": "cmuHFRCOFreq_32M0Hz",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- }
- },
- "overrides": {
- "network-default-interface-type": "MESH"
- }
- },
- "EFM32PG12B500F1024GL125": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
- "core": "Cortex-M4F",
- "macros_add": [
- "EFM32PG12B500F1024GL125",
- "TRANSACTION_QUEUE_SIZE_SPI=4"
- ],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFM32PG12B500F1024GL125",
- "public": false,
- "bootloader_supported": true
- },
- "EFM32PG12_STK3402": {
- "inherits": ["EFM32PG12B500F1024GL125"],
- "device_has": [
- "ANALOGIN",
- "CRC",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 2,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "40000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "32000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
- "value": "cmuHFRCOFreq_32M0Hz",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PA5",
- "macro_name": "EFM_BC_EN"
- }
- }
- },
- "EFR32MG12P332F1024GL125": {
- "inherits": ["EFM32"],
- "extra_labels_add": [
- "EFR32MG12",
- "EFR32_12",
- "1024K",
- "SL_RAIL",
- "SL_CRYPTO"
- ],
- "core": "Cortex-M4F",
- "macros_add": [
- "EFR32MG12P332F1024GL125",
- "TRANSACTION_QUEUE_SIZE_SPI=4"
- ],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFR32MG12P332F1024GL125",
- "public": false,
- "bootloader_supported": true
- },
- "TB_SENSE_12": {
- "inherits": ["EFR32MG12P332F1024GL125"],
- "device_name": "EFR32MG12P332F1024GL125",
- "device_has": [
- "802_15_4_PHY",
- "ANALOGIN",
- "CRC",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 5,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "38400000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "32000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
- "value": "cmuHFRCOFreq_32M0Hz",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- }
- },
- "overrides": {
- "network-default-interface-type": "MESH"
- }
- },
- "EFM32GG11B820F2048GL192": {
- "inherits": ["EFM32"],
- "extra_labels_add": ["EFM32GG11", "2048K", "SL_CRYPTO"],
- "core": "Cortex-M4F",
- "macros_add": [
- "EFM32GG11B820F2048GL192",
- "TRANSACTION_QUEUE_SIZE_SPI=4"
- ],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
- "release_versions": ["2", "5"],
- "device_name": "EFM32GG11B820F2048GL192",
- "public": false,
- "bootloader_supported": true
- },
- "EFM32GG11_STK3701": {
- "inherits": ["EFM32GG11B820F2048GL192"],
- "device_name": "EFM32GG11B820F2048GL192",
- "device_has": [
- "ANALOGIN",
- "CRC",
- "EMAC",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "QSPI",
- "RTC",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "USTICKER",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "forced_reset_timeout": 5,
- "config": {
- "hf_clock_src": {
- "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
- "value": "HFXO",
- "macro_name": "CORE_CLOCK_SOURCE"
- },
- "hfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "50000000",
- "macro_name": "HFXO_FREQUENCY"
- },
- "lf_clock_src": {
- "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
- "value": "LFXO",
- "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
- },
- "lfxo_clock_freq": {
- "help": "Value: External crystal frequency in hertz",
- "value": "32768",
- "macro_name": "LFXO_FREQUENCY"
- },
- "hfrco_clock_freq": {
- "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
- "value": "32000000",
- "macro_name": "HFRCO_FREQUENCY"
- },
- "hfrco_band_select": {
- "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
- "value": "cmuHFRCOFreq_32M0Hz",
- "macro_name": "HFRCO_FREQUENCY_ENUM"
- },
- "board_controller_enable": {
- "help": "Pin to pull high for enabling the USB serial port",
- "value": "PE1",
- "macro_name": "EFM_BC_EN"
- },
- "qspi_flash_enable": {
- "help": "Pin to pull high for enabling the on-board QSPI flash",
- "value": "PG13",
- "macro_name": "QSPI_FLASH_EN"
- }
- },
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "WIZWIKI_W7500": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0",
- "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
- "inherits": ["Target"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2", "5"]
- },
- "WIZWIKI_W7500P": {
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M0",
- "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
- "inherits": ["Target"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2", "5"]
- },
- "WIZWIKI_W7500ECO": {
- "inherits": ["Target"],
- "core": "Cortex-M0",
- "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["uARM", "ARM", "GCC_ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "STDIO_MESSAGES"
- ],
- "release_versions": ["2", "5"]
- },
- "SAMR21G18A": {
- "inherits": ["Target"],
- "core": "Cortex-M0+",
- "macros": [
- "__SAMR21G18A__",
- "I2C_MASTER_CALLBACK_MODE=true",
- "EXTINT_CALLBACK_MODE=true",
- "USART_CALLBACK_MODE=true",
- "TC_ASYNC=true"
- ],
- "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMR21"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH"
- ],
- "release_versions": ["2"],
- "device_name": "ATSAMR21G18A"
- },
- "SAMD21J18A": {
- "inherits": ["Target"],
- "core": "Cortex-M0+",
- "macros": [
- "__SAMD21J18A__",
- "I2C_MASTER_CALLBACK_MODE=true",
- "EXTINT_CALLBACK_MODE=true",
- "USART_CALLBACK_MODE=true",
- "TC_ASYNC=true"
- ],
- "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH"
- ],
- "release_versions": ["2"],
- "device_name": "ATSAMD21J18A"
- },
- "SAMD21G18A": {
- "inherits": ["Target"],
- "core": "Cortex-M0+",
- "macros": [
- "__SAMD21G18A__",
- "I2C_MASTER_CALLBACK_MODE=true",
- "EXTINT_CALLBACK_MODE=true",
- "USART_CALLBACK_MODE=true",
- "TC_ASYNC=true"
- ],
- "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH"
- ],
- "release_versions": ["2"],
- "device_name": "ATSAMD21G18A"
- },
- "SAML21J18A": {
- "inherits": ["Target"],
- "core": "Cortex-M0+",
- "macros": [
- "__SAML21J18A__",
- "I2C_MASTER_CALLBACK_MODE=true",
- "EXTINT_CALLBACK_MODE=true",
- "USART_CALLBACK_MODE=true",
- "TC_ASYNC=true"
- ],
- "extra_labels": ["Atmel", "SAM_CortexM0P", "SAML21"],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH"
- ],
- "device_name": "ATSAML21J18A"
- },
- "SAMG55J19": {
- "inherits": ["Target"],
- "core": "Cortex-M4",
- "extra_labels": ["Atmel", "SAM_CortexM4", "SAMG55"],
- "macros": [
- "__SAMG55J19__",
- "BOARD=75",
- "I2C_MASTER_CALLBACK_MODE=true",
- "EXTINT_CALLBACK_MODE=true",
- "USART_CALLBACK_MODE=true",
- "TC_ASYNC=true"
- ],
- "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
- "default_toolchain": "ARM",
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "MPU"
- ],
- "default_lib": "std",
- "device_name": "ATSAMG55J19"
- },
- "MCU_NRF51_UNIFIED": {
- "inherits": ["Target"],
- "core": "Cortex-M0",
- "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
- "macros": [
- "BOARD_PCA10028",
- "NRF51",
- "TARGET_NRF51822",
- "BLE_STACK_SUPPORT_REQD",
- "SOFTDEVICE_PRESENT",
- "S130",
- "TARGET_MCU_NRF51822",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
- "NO_SYSTICK",
- "MBED_TICKLESS"
- ],
- "MERGE_BOOTLOADER": false,
- "extra_labels": [
- "NORDIC",
- "MCU_NRF51",
- "MCU_NRF51822_UNIFIED",
- "NRF5x",
- "NRF51",
- "SDK_11",
- "NORDIC_SOFTDEVICE"
- ],
- "OUTPUT_EXT": "hex",
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "public": false,
- "MERGE_SOFT_DEVICE": true,
- "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
- {
- "boot": "",
- "name": "s130_nrf51_2.0.0_softdevice.hex",
- "offset": 110592
- }
- ],
- "detect_code": ["1070"],
- "post_binary_hook": {
- "function": "MCU_NRF51Code.binary_hook",
- "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
- },
- "program_cycle_s": 6,
- "features": ["BLE"],
- "config": {
- "lf_clock_src": {
- "value": "NRF_LF_SRC_XTAL",
- "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
- },
- "uart_hwfc": {
- "help": "Value: 1 for enable, 0 for disable",
- "value": 1,
- "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
- }
- },
- "device_has": [
- "ANALOGIN",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ]
- },
- "MCU_NRF51_16K_UNIFIED_S130": {
- "inherits": ["MCU_NRF51_UNIFIED"],
- "extra_labels_add": [
- "MCU_NORDIC_16K",
- "MCU_NRF51_16K_S130",
- "MCU_NRF51_16K"
- ],
- "macros_add": [
- "TARGET_MCU_NORDIC_16K",
- "TARGET_MCU_NRF51_16K_S130",
- "TARGET_MCU_NRF51_16K"
- ],
- "public": false
- },
- "MCU_NRF51_32K_UNIFIED": {
- "inherits": ["MCU_NRF51_UNIFIED"],
- "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
- "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
- "public": false
- },
- "NRF51_DK": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE"
- ],
- "release_versions": ["2", "5"],
- "device_name": "nRF51822_xxAA"
- },
- "SDT51822B": {
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE"
- ],
- "detect_code": ["3103"],
- "release_versions": ["2", "5"],
- "device_name": "nRF51822_xxAA"
- },
- "NRF51_DONGLE": {
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
- "progen": { "target": "nrf51-dongle" },
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE"
- ],
- "release_versions": ["2", "5"]
- },
- "OSHCHIP": {
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
- "overrides": { "lf_clock_src": "NRF_LF_SRC_RC" },
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE"
- ],
- "device_name": "nRF51822_xxAC"
- },
- "MCU_NRF52832": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "static_memory_defines": false,
- "macros": [
- "BOARD_PCA10040",
- "NRF52",
- "TARGET_NRF52832",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
- "MBED_TICKLESS",
- "MBED_MPU_CUSTOM"
- ],
- "device_has": [
- "ANALOGIN",
- "FLASH",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "ITM",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SYSTICK_CLK_OFF_DURING_SLEEP",
- "TRNG",
- "USTICKER"
- ],
- "extra_labels": [
- "NORDIC",
- "NRF5x",
- "NRF52",
- "SDK_14_2",
- "NORDIC_SOFTDEVICE",
- "SOFTDEVICE_COMMON",
- "SOFTDEVICE_S132_FULL"
- ],
- "config": {
- "lf_clock_src": {
- "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
- "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
- "value": "NRF_LF_SRC_XTAL"
- },
- "lf_clock_rc_calib_timer_interval": {
- "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
- "value": 16
- },
- "lf_clock_rc_calib_mode_config": {
- "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
- "value": 0
- }
- },
- "OUTPUT_EXT": "hex",
- "is_disk_virtual": true,
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "public": false,
- "detect_code": ["1101"],
- "program_cycle_s": 6,
- "bootloader_supported": true
- },
- "NRF52_DK": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA",
- "macros_add": [
- "WSF_MAX_HANDLERS=10"
- ]
- },
- "SDT52832B": {
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "detect_code": ["3104"],
- "device_name": "nRF52832_xxAA"
- },
- "UBLOX_EVA_NINA": {
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "UBLOX_EVK_NINA_B1": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "MTB_UBLOX_NINA_B1": {
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "MTB_LAIRD_BL652": {
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "MTB_MURATA_WSM_BL241": {
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA",
- "detect_code": ["0466"]
- },
- "MTB_ACONNO_ACN52832": {
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "DELTA_DFBM_NQ620": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "MCU_NRF52840": {
- "inherits": ["Target"],
- "components_add": ["QSPIF"],
- "core": "Cortex-M4F",
- "static_memory_defines": false,
- "macros": [
- "BOARD_PCA10056",
- "NRF52840_XXAA",
- "TARGET_NRF52840",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
- "MBED_TICKLESS",
- "MBEDTLS_CONFIG_HW_SUPPORT",
- "WSF_MAX_HANDLERS=10",
- "MBED_MPU_CUSTOM"
- ],
- "features": ["CRYPTOCELL310"],
- "device_has": [
- "ANALOGIN",
- "FLASH",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "ITM",
- "LPTICKER",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SYSTICK_CLK_OFF_DURING_SLEEP",
- "TRNG",
- "USTICKER",
- "QSPI"
- ],
- "extra_labels": [
- "NORDIC",
- "NRF5x",
- "NRF52",
- "SDK_14_2",
- "NORDIC_SOFTDEVICE",
- "SOFTDEVICE_COMMON",
- "SOFTDEVICE_S140_FULL"
- ],
- "config": {
- "lf_clock_src": {
- "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC",
- "help": "Select Low Frequency clock source. Options: NRF_LF_SRC_XTAL, NRF_LF_SRC_SYNTH, and NRF_LF_SRC_RC",
- "value": "NRF_LF_SRC_XTAL"
- },
- "lf_clock_rc_calib_timer_interval": {
- "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL",
- "value": 16
- },
- "lf_clock_rc_calib_mode_config": {
- "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG",
- "value": 0
- }
- },
- "overrides": {
- "mpu-rom-end": "0x1fffffff"
- },
- "OUTPUT_EXT": "hex",
- "is_disk_virtual": true,
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "public": false,
- "detect_code": ["1101"],
- "program_cycle_s": 6,
- "bootloader_supported": true
- },
- "NRF52840_DK": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF52840"],
- "release_versions": ["5"],
- "device_name": "nRF52840_xxAA"
- },
- "MTB_LAIRD_BL654": {
- "inherits": ["MCU_NRF52840"],
- "release_versions": ["5"],
- "device_name": "nRF52840_xxAA",
- "detect_code": ["0465"],
- "features_remove": ["CRYPTOCELL310"],
- "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"],
- "overrides": {
- "lf_clock_src": "NRF_LF_SRC_RC"
- }
- },
- "BLUEPILL_F103C8": {
- "inherits": ["FAMILY_STM32"],
- "core": "Cortex-M3",
- "default_toolchain": "GCC_ARM",
- "extra_labels_add": ["STM32F1", "STM32F103C8"],
- "supported_toolchains": ["GCC_ARM"],
- "device_has_add": [
- "CAN",
- "SERIAL_ASYNCH",
- "FLASH"
- ],
- "device_has_remove": ["STDIO_MESSAGES", "LPTICKER"]
- },
- "NUMAKER_PFM_NUC472": {
- "core": "Cortex-M4F",
- "default_toolchain": "ARM",
- "extra_labels": [
- "NUVOTON",
- "NUC472",
- "NU_XRAM_SUPPORTED",
- "FLASH_CMSIS_ALGO",
- "NUVOTON_EMAC"
- ],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "config": {
- "gpio-irq-debounce-enable": {
- "help": "Enable GPIO IRQ debounce",
- "value": 0
- },
- "gpio-irq-debounce-enable-list": {
- "help": "Comma separated pin list to enable GPIO IRQ debounce",
- "value": "NC"
- },
- "gpio-irq-debounce-clock-source": {
- "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K",
- "value": "GPIO_DBCTL_DBCLKSRC_IRC10K"
- },
- "gpio-irq-debounce-sample-rate": {
- "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
- "value": "GPIO_DBCTL_DBCLKSEL_16"
- }
- },
- "inherits": ["Target"],
- "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "STDIO_MESSAGES",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "TRNG",
- "CAN",
- "FLASH",
- "EMAC",
- "MPU"
- ],
- "release_versions": ["5"],
- "device_name": "NUC472HI8AE",
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NCS36510": {
- "inherits": ["Target"],
- "core": "Cortex-M3",
- "extra_labels": ["ONSEMI"],
- "config": {
- "mac-addr-low": {
- "help": "Lower 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
- "value": "0xFFFFFFFF"
- },
- "mac-addr-high": {
- "help": "Higher 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
- "value": "0xFFFFFFFF"
- },
- "32KHz-clk-trim": {
- "help": "32KHz clock trim",
- "value": "0x39"
- },
- "32MHz-clk-trim": {
- "help": "32MHz clock trim",
- "value": "0x17"
- },
- "rssi-trim": {
- "help": "RSSI trim",
- "value": "0x3D"
- },
- "txtune-trim": {
- "help": "TX tune trim",
- "value": "0xFFFFFFFF"
- }
- },
- "OUTPUT_EXT": "hex",
- "post_binary_hook": {
- "function": "NCS36510TargetCode.ncs36510_addfib"
- },
- "macros": [
- "CM3",
- "CPU_NCS36510",
- "TARGET_NCS36510",
- "LOAD_ADDRESS=0x3000"
- ],
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "SERIAL",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "TRNG",
- "SPISLAVE",
- "802_15_4_PHY",
- "MPU"
- ],
- "release_versions": ["2", "5"]
- },
- "NUMAKER_PFM_M453": {
- "core": "Cortex-M4F",
- "default_toolchain": "ARM",
- "extra_labels": [
- "NUVOTON",
- "M451",
- "NUMAKER_PFM_M453",
- "FLASH_CMSIS_ALGO"
- ],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "config": {
- "gpio-irq-debounce-enable": {
- "help": "Enable GPIO IRQ debounce",
- "value": 0
- },
- "gpio-irq-debounce-enable-list": {
- "help": "Comma separated pin list to enable GPIO IRQ debounce",
- "value": "NC"
- },
- "gpio-irq-debounce-clock-source": {
- "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
- "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
- },
- "gpio-irq-debounce-sample-rate": {
- "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
- "value": "GPIO_DBCTL_DBCLKSEL_16"
- }
- },
- "inherits": ["Target"],
- "macros_add": ["LPTICKER_DELAY_TICKS=3"],
- "progen": { "target": "numaker-pfm-m453" },
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "STDIO_MESSAGES",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "CAN",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "M453VG6AE",
- "bootloader_supported": true
- },
- "NUMAKER_PFM_NANO130": {
- "core": "Cortex-M0",
- "default_toolchain": "ARM",
- "extra_labels": ["NUVOTON", "NANO100", "NANO130KE3BN"],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "config": {
- "gpio-irq-debounce-enable": {
- "help": "Enable GPIO IRQ debounce",
- "value": 0
- },
- "gpio-irq-debounce-enable-list": {
- "help": "Comma separated pin list to enable GPIO IRQ debounce",
- "value": "NC"
- },
- "gpio-irq-debounce-clock-source": {
- "help": "Select GPIO IRQ debounce clock source: GPIO_DBCLKSRC_HCLK or GPIO_DBCLKSRC_IRC10K",
- "value": "GPIO_DBCLKSRC_IRC10K"
- },
- "gpio-irq-debounce-sample-rate": {
- "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCLKSEL_1, GPIO_DBCLKSEL_2, GPIO_DBCLKSEL_4, ..., or GPIO_DBCLKSEL_32768",
- "value": "GPIO_DBCLKSEL_16"
- },
- "clock-pll": {
- "help": "Choose clock source to clock PLL: NU_HXT_PLL or NU_HIRC_PLL",
- "macro_name": "NU_CLOCK_PLL",
- "value": "NU_HIRC_PLL"
- }
- },
- "inherits": ["Target"],
- "macros": [
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"",
- "MBED_FAULT_HANDLER_DISABLED",
- "LPTICKER_DELAY_TICKS=3"
- ],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "STDIO_MESSAGES",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH"
- ],
- "release_versions": ["5"],
- "device_name": "NANO130KE3BN"
- },
- "HI2110": {
- "inherits": ["Target"],
- "core": "Cortex-M0",
- "default_toolchain": "GCC_ARM",
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "extra_labels": ["ublox"],
- "macros": [
- "TARGET_PROCESSOR_FAMILY_BOUDICA",
- "BOUDICA_SARA",
- "NDEBUG=1",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "public": false,
- "target_overrides": {
- "*": {
- "core.stdio-flush-at-exit": false
- }
- },
- "device_has": [
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SLEEP",
- "STDIO_MESSAGES"
- ],
- "default_lib": "std",
- "release_versions": []
- },
- "SARA_NBIOT": {
- "inherits": ["HI2110"],
- "extra_labels": ["ublox", "HI2110"],
- "public": false
- },
- "SARA_NBIOT_EVK": {
- "inherits": ["SARA_NBIOT"],
- "extra_labels": ["ublox", "HI2110", "SARA_NBIOT"]
- },
- "MCU_RTL8195A": {
- "core": "Cortex-M3",
- "default_toolchain": "GCC_ARM",
- "macros": [
- "__RTL8195A__",
- "CONFIG_PLATFORM_8195A",
- "CONFIG_MBED_ENABLED",
- "PLATFORM_CMSIS_RTOS",
- "MBED_FAULT_HANDLER_DISABLED",
- "MBED_MPU_CUSTOM"
- ],
- "inherits": ["Target"],
- "extra_labels": ["Realtek", "AMEBA", "RTW_EMAC"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SPI",
- "TRNG",
- "FLASH"
- ],
- "public": false,
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "post_binary_hook": {
- "function": "RTL8195ACode.binary_hook",
- "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
- },
- "release_versions": ["5"],
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "REALTEK_RTL8195AM": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_RTL8195A"],
- "detect_code": ["4600"],
- "extra_labels_add": ["RTL8195A"]
- },
- "VBLUNO51_LEGACY": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K"],
- "detect_code": ["C006"],
- "overrides": { "uart_hwfc": 0 },
- "extra_labels_add": ["VBLUNO51"]
- },
- "VBLUNO51_BOOT": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K_BOOT"],
- "detect_code": ["C006"],
- "overrides": { "uart_hwfc": 0 },
- "extra_labels_add": ["VBLUNO51"],
- "macros_add": ["TARGET_VBLUNO51"]
- },
- "VBLUNO51_OTA": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K_OTA"],
- "detect_code": ["C006"],
- "overrides": { "uart_hwfc": 0 },
- "extra_labels_add": ["VBLUNO51"],
- "macros_add": ["TARGET_VBLUNO51"]
- },
- "VBLUNO51": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF51_32K_UNIFIED"],
- "detect_code": ["C006"],
- "overrides": { "uart_hwfc": 0 },
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "ANALOGIN",
- "I2C",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "SLEEP",
- "SPI",
- "SPI_ASYNCH",
- "SPISLAVE"
- ],
- "release_versions": ["2"],
- "device_name": "nRF51822_xxAC"
- },
- "DISCO_L496AG": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"],
- "components_add": ["QSPIF"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0822"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU",
- "QSPI"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L496AG",
- "bootloader_supported": true
- },
- "NUCLEO_L496ZG": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L496ZG", "STM32L496xG"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0823"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L496ZG",
- "bootloader_supported": true
- },
- "NUCLEO_L496ZG_P": {
- "inherits": ["NUCLEO_L496ZG"],
- "detect_code": ["0828"]
- },
- "NUCLEO_L4R5ZI": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": ["ARDUINO", "MORPHO"],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32L4", "STM32L4R5ZI", "STM32L4R5xI"],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
- "value": "USE_PLL_MSI",
- "macro_name": "CLOCK_SOURCE"
- },
- "lpticker_lptim": {
- "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
- "value": 1
- }
- },
- "macros_add": [
- "MBED_TICKLESS"
- ],
- "overrides": { "lpticker_delay_ticks": 4 },
- "detect_code": ["0776"],
- "device_has_add": [
- "ANALOGOUT",
- "CAN",
- "CRC",
- "SERIAL_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "release_versions": ["2", "5"],
- "device_name": "STM32L4R5ZI",
- "bootloader_supported": true
- },
- "NUCLEO_L4R5ZI_P": {
- "inherits": ["NUCLEO_L4R5ZI"],
- "detect_code": ["0781"]
- },
- "VBLUNO52": {
- "supported_form_factors": ["ARDUINO"],
- "inherits": ["MCU_NRF52832"],
- "release_versions": ["5"],
- "device_name": "nRF52832_xxAA"
- },
- "MCU_M480": {
- "core": "Cortex-M4F",
- "default_toolchain": "ARM",
- "public": false,
- "extra_labels": ["NUVOTON", "M480", "FLASH_CMSIS_ALGO", "NUVOTON_EMAC"],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
- "config": {
- "gpio-irq-debounce-enable": {
- "help": "Enable GPIO IRQ debounce",
- "value": 0
- },
- "gpio-irq-debounce-enable-list": {
- "help": "Comma separated pin list to enable GPIO IRQ debounce",
- "value": "NC"
- },
- "gpio-irq-debounce-clock-source": {
- "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
- "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
- },
- "gpio-irq-debounce-sample-rate": {
- "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
- "value": "GPIO_DBCTL_DBCLKSEL_16"
- },
- "usb-device-hsusbd": {
- "help": "Select high-speed USB device or not",
- "value": 1
- },
- "ctrl01-enable": {
- "help": "Enable control_01",
- "value": 0
- }
- },
- "inherits": ["Target"],
- "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "LPTICKER_DELAY_TICKS=3"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "STDIO_MESSAGES",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "TRNG",
- "FLASH",
- "CAN",
- "EMAC",
- "MPU"
- ],
- "release_versions": ["5"],
- "bootloader_supported": true,
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "NUMAKER_PFM_M487": {
- "inherits": ["MCU_M480"],
- "device_name": "M487JIDAE"
- },
- "NUMAKER_IOT_M487": {
- "inherits": ["MCU_M480"],
- "device_name": "M487JIDAE"
- },
- "TMPM066": {
- "inherits": ["Target"],
- "core": "Cortex-M0",
- "is_disk_virtual": true,
- "extra_labels": ["TOSHIBA"],
- "macros": [
- "__TMPM066__",
- "CMSIS_VECTAB_VIRTUAL",
- "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""
- ],
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SLEEP",
- "I2C",
- "I2CSLAVE",
- "STDIO_MESSAGES",
- "PWMOUT"
- ],
- "device_name": "TMPM066FWUG",
- "detect_code": ["7011"],
- "release_versions": ["5"]
- },
- "SAKURAIO_EVB_01": {
- "inherits": ["FAMILY_STM32"],
- "supported_form_factors": [],
- "core": "Cortex-M4F",
- "extra_labels_add": ["STM32F4", "STM32F411xE", "STM32F411RE"],
- "device_has": [
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "config": {
- "clock_source": {
- "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
- "value": "USE_PLL_HSI",
- "macro_name": "CLOCK_SOURCE"
- }
- },
- "device_has_add": [
- "SERIAL_ASYNCH",
- "FLASH"
- ],
- "release_versions": ["2"],
- "device_name": "STM32F411RE"
- },
- "TMPM46B": {
- "inherits": ["Target"],
- "core": "Cortex-M4",
- "is_disk_virtual": true,
- "extra_labels": ["TOSHIBA"],
- "macros": ["__TMPM46B__"],
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_FC",
- "SPI",
- "I2C",
- "STDIO_MESSAGES",
- "TRNG",
- "FLASH",
- "SLEEP"
- ],
- "device_name": "TMPM46BF10FG",
- "detect_code": ["7013"],
- "release_versions": ["5"],
- "bootloader_supported": true
- },
- "ARM_FM": {
- "inherits": ["Target"],
- "public": false,
- "macros": ["__ARM_FM"],
- "extra_labels": ["ARM_FM"]
- },
- "FVP_MPS2": {
- "inherits": ["ARM_FM"],
- "public": false,
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "OUTPUT_EXT": "elf",
- "device_has": [
- "AACI",
- "ANALOGIN",
- "CLCD",
- "EMAC",
- "FLASH",
- "I2C",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "SERIAL",
- "SPI",
- "SPISLAVE",
- "TSC",
- "USTICKER"
- ],
- "release_versions": ["5"],
- "components_add": ["LAN91C111"],
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "FVP_MPS2_M0": {
- "inherits": ["FVP_MPS2"],
- "core": "Cortex-M0",
- "macros_add": ["CMSDK_CM0"]
- },
- "FVP_MPS2_M0P": {
- "inherits": ["FVP_MPS2"],
- "core": "Cortex-M0+",
- "macros_add": ["CMSDK_CM0plus"],
- "device_has_add": ["MPU"]
- },
- "FVP_MPS2_M3": {
- "inherits": ["FVP_MPS2"],
- "core": "Cortex-M3",
- "macros_add": ["CMSDK_CM3"],
- "device_has_add": ["MPU"]
- },
- "FVP_MPS2_M4": {
- "inherits": ["FVP_MPS2"],
- "core": "Cortex-M4",
- "macros_add": ["CMSDK_CM4"],
- "device_has_add": ["MPU"]
- },
- "FVP_MPS2_M7": {
- "inherits": ["FVP_MPS2"],
- "core": "Cortex-M7",
- "macros_add": ["CMSDK_CM7"],
- "device_has_add": ["MPU"]
- },
- "NUMAKER_PFM_M2351": {
- "core": "Cortex-M23-NS",
- "default_toolchain": "ARMC6",
- "extra_labels": [
- "NUVOTON",
- "M2351",
- "M2351KIAAEES",
- "FLASH_CMSIS_ALGO"
- ],
- "OUTPUT_EXT": "hex",
- "macros": [
- "MBED_FAULT_HANDLER_DISABLED",
- "MBED_TZ_DEFAULT_ACCESS=1",
- "LPTICKER_DELAY_TICKS=3"
- ],
- "is_disk_virtual": true,
- "supported_toolchains": ["ARMC6"],
- "config": {
- "gpio-irq-debounce-enable": {
- "help": "Enable GPIO IRQ debounce",
- "value": 0
- },
- "gpio-irq-debounce-enable-list": {
- "help": "Comma separated pin list to enable GPIO IRQ debounce",
- "value": "NC"
- },
- "gpio-irq-debounce-clock-source": {
- "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC",
- "value": "GPIO_DBCTL_DBCLKSRC_LIRC"
- },
- "gpio-irq-debounce-sample-rate": {
- "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768",
- "value": "GPIO_DBCTL_DBCLKSEL_16"
- }
- },
- "overrides": {
- "mpu-rom-end": "0x1fffffff"
- },
- "inherits": ["Target"],
- "device_has": [
- "USTICKER",
- "LPTICKER",
- "RTC",
- "ANALOGIN",
- "I2C",
- "I2CSLAVE",
- "I2C_ASYNCH",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "STDIO_MESSAGES",
- "SLEEP",
- "SPI",
- "SPISLAVE",
- "SPI_ASYNCH",
- "TRNG",
- "FLASH",
- "MPU"
- ],
- "detect_code": ["1305"],
- "release_versions": ["5"],
- "device_name": "M2351KIAAEES",
- "bootloader_supported": true
- },
- "TMPM3H6": {
- "inherits": ["Target"],
- "core": "Cortex-M3",
- "is_disk_virtual": true,
- "extra_labels": ["TOSHIBA"],
- "macros": ["__TMPM3H6__"],
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "I2C",
- "I2CSLAVE",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "device_name": "TMPM3H6FWFG",
- "detect_code": ["7012"],
- "release_versions": ["5"]
- },
- "TMPM4G9": {
- "inherits": ["Target"],
- "core": "Cortex-M4",
- "is_disk_virtual": true,
- "extra_labels": ["TOSHIBA"],
- "macros": ["__TMPM4G9__"],
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "ANALOGOUT",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SPI",
- "I2C",
- "I2CSLAVE",
- "STDIO_MESSAGES",
- "FLASH",
- "SLEEP",
- "USTICKER",
- "MPU"
- ],
- "device_name": "TMPM4G9F15FG",
- "detect_code": ["7015"],
- "release_versions": ["5"],
- "bootloader_supported": true
- },
- "MCU_PSOC6": {
- "inherits": ["Target"],
- "macros": ["MBED_MPU_CUSTOM"],
- "default_toolchain": "GCC_ARM",
- "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
- "core": "Cortex-M4F",
- "OUTPUT_EXT": "hex",
- "device_has": [
- "USTICKER",
- "INTERRUPTIN",
- "SERIAL",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "PORTIN",
- "PORTOUT",
- "PORTINOUT",
- "RTC",
- "PWMOUT",
- "ANALOGIN",
- "ANALOGOUT",
- "I2C",
- "I2C_ASYNCH",
- "SPI",
- "SPI_ASYNCH",
- "STDIO_MESSAGES",
- "LPTICKER",
- "SLEEP",
- "FLASH",
- "TRNG",
- "CRC"
- ],
- "release_versions": ["5"],
- "extra_labels": ["Cypress", "PSOC6"],
- "public": false
- },
- "MCU_PSOC6_M0": {
- "inherits": ["MCU_PSOC6"],
- "core": "Cortex-M0+",
- "macros_add": ["MCU_PSOC6_M0"],
- "public": false
- },
- "MCU_PSOC6_M4": {
- "inherits": ["MCU_PSOC6"],
- "macros_add": ["MCU_PSOC6_M4"],
- "public": false
- },
- "CY8CKIT_062_WIFI_BT": {
- "inherits": ["MCU_PSOC6_M4"],
- "features": ["BLE"],
- "supported_form_factors": ["ARDUINO"],
- "extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
- "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
- "detect_code": ["1900"],
- "hex_filename": "psoc6_01_cm0p_sleep.hex",
- "post_binary_hook": {
- "function": "PSOC6Code.complete"
- },
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "CY8CMOD_062_4343W": {
- "inherits": ["MCU_PSOC6_M4"],
- "features": ["BLE"],
- "device_has_remove": ["ANALOGOUT"],
- "extra_labels_add": ["PSOC6_02", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
- "macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"],
- "public": false,
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "CY8CPROTO_062_4343W": {
- "inherits": ["CY8CMOD_062_4343W"],
- "detect_code": ["1901"],
- "hex_filename": "psoc6_02_cm0p_sleep.hex",
- "post_binary_hook": {
- "function": "PSOC6Code.complete"
- }
- },
- "CY8CKIT_062_BLE": {
- "inherits": ["MCU_PSOC6_M4"],
- "supported_form_factors": ["ARDUINO"],
- "extra_labels_add": ["PSOC6_01"],
- "macros_add": ["CY8C6347BZI_BLD53", "PSOC6_DYNSRM_DISABLE=1"],
- "detect_code": ["1902"],
- "hex_filename": "psoc6_01_cm0p_sleep.hex",
- "post_binary_hook": {
- "function": "PSOC6Code.complete"
- }
- },
- "CY8CKIT_062_4343W": {
- "inherits": ["MCU_PSOC6_M4"],
- "features": ["BLE"],
- "supported_form_factors": ["ARDUINO"],
- "device_has_remove": ["ANALOGOUT"],
- "extra_labels_add": ["PSOC6_02", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
- "macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"],
- "detect_code": ["1905"],
- "hex_filename": "psoc6_02_cm0p_sleep.hex",
- "post_binary_hook": {
- "function": "PSOC6Code.complete"
- },
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "CYW943012P6EVB_01": {
- "inherits": ["MCU_PSOC6_M4"],
- "features": ["BLE"],
- "extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW43012", "CORDIO"],
- "macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
- "detect_code": ["1906"],
- "hex_filename": "psoc6_01_cm0p_sleep.hex",
- "post_binary_hook": {
- "function": "PSOC6Code.complete"
- },
- "overrides": {
- "network-default-interface-type": "WIFI"
- }
- },
- "FUTURE_SEQUANA_M0": {
- "inherits": ["MCU_PSOC6_M0"],
- "supported_form_factors": ["ARDUINO"],
- "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "FUTURE_SEQUANA"],
- "extra_labels_remove": ["PSOC6"],
- "device_has_remove": ["TRNG", "CRC"],
- "macros_add": ["CY8C6347BZI_BLD53"],
- "detect_code": ["6000"],
- "post_binary_hook": {
- "function": "PSOC6Code.complete"
- },
- "config": {
- "system-clock": {
- "help": "Desired frequency of main clock (Hz)",
- "value": "100000000UL",
- "macro_name": "CY_CLK_HFCLK0_FREQ_HZ"
- },
- "peri-clock": {
- "help": "Desired frequency of peripheral clock (Hz)",
- "value": "50000000UL",
- "macro_name": "CY_CLK_PERICLK_FREQ_HZ"
- },
- "m0-clock": {
- "help": "Desired frequency of M0+ core clock (Hz)",
- "value": "50000000UL",
- "macro_name": "CY_CLK_SLOWCLK_FREQ_HZ"
- }
- }
- },
- "FUTURE_SEQUANA": {
- "inherits": ["MCU_PSOC6_M4"],
- "supported_form_factors": ["ARDUINO"],
- "extra_labels_add": ["PSOC6_FUTURE", "CY8C63XX", "CORDIO"],
- "extra_labels_remove": ["PSOC6"],
- "device_has_remove": ["TRNG", "CRC"],
- "macros_add": ["CY8C6347BZI_BLD53"],
- "detect_code": ["6000"],
- "hex_filename": "psoc63_m0_default_1.02.hex",
- "post_binary_hook": {
- "function": "PSOC6Code.complete"
- },
- "config": {
- "system-clock": {
- "help": "Desired frequency of main clock (Hz)",
- "value": "100000000UL",
- "macro_name": "CY_CLK_HFCLK0_FREQ_HZ"
- },
- "peri-clock": {
- "help": "Desired frequency of peripheral clock (Hz)",
- "value": "50000000UL",
- "macro_name": "CY_CLK_PERICLK_FREQ_HZ"
- },
- "m0-clock": {
- "help": "Desired frequency of M0+ core clock (Hz)",
- "value": "50000000UL",
- "macro_name": "CY_CLK_SLOWCLK_FREQ_HZ"
- }
- }
- },
- "FUTURE_SEQUANA_M0_PSA": {
- "inherits": ["SPE_Target", "FUTURE_SEQUANA_M0"],
- "components_add": ["SPM_MAILBOX", "FLASHIAP"],
- "extra_labels_add": ["PSA"],
- "macros_add": [
- "PSOC6_DYNSRM_DISABLE=1",
- "MBEDTLS_PSA_CRYPTO_SPM",
- "MBEDTLS_PSA_CRYPTO_C",
- "MBEDTLS_ENTROPY_NV_SEED",
- "MBEDTLS_PLATFORM_NV_SEED_READ_MACRO=mbed_default_seed_read",
- "MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO=mbed_default_seed_write"
- ],
- "deliver_to_target": "FUTURE_SEQUANA_PSA",
- "overrides": {
- "secure-rom-start": "0x10000000",
- "secure-rom-size": "0x80000",
- "non-secure-rom-start": "0x10080000",
- "non-secure-rom-size": "0x78000",
- "secure-ram-start": "0x08000000",
- "secure-ram-size": "0x10000",
- "non-secure-ram-start": "0x08010000",
- "non-secure-ram-size": "0x37700",
- "shared-ram-start": "0x08047700",
- "shared-ram-size": "0x100"
- }
- },
- "FUTURE_SEQUANA_PSA": {
- "inherits": ["NSPE_Target", "FUTURE_SEQUANA"],
- "extra_labels_add": ["PSA"],
- "extra_labels_remove": ["CORDIO"],
- "components_add": ["SPM_MAILBOX"],
- "macros_add": ["PSOC6_DYNSRM_DISABLE=1", "MBEDTLS_PSA_CRYPTO_C"],
- "hex_filename": "psa_release_1.0.hex",
- "overrides": {
- "secure-rom-start": "0x10000000",
- "secure-rom-size": "0x80000",
- "non-secure-rom-start": "0x10080000",
- "non-secure-rom-size": "0x78000",
- "secure-ram-start": "0x08000000",
- "secure-ram-size": "0x10000",
- "non-secure-ram-start": "0x08010000",
- "non-secure-ram-size": "0x37700",
- "shared-ram-start": "0x08047700",
- "shared-ram-size": "0x100"
- }
- },
- "TMPM3HQ": {
- "inherits": ["Target"],
- "core": "Cortex-M3",
- "is_disk_virtual": true,
- "extra_labels": ["TOSHIBA"],
- "macros": ["__TMPM3HQ__"],
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "ANALOGOUT",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "I2C",
- "I2CSLAVE",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "device_name": "TMPM3HQFDFG",
- "detect_code": ["7014"],
- "release_versions": ["5"]
- },
- "RDA5981X": {
- "inherits": ["Target"],
- "core": "Cortex-M4F",
- "public": true,
- "extra_labels": ["RDA", "UNO_91H", "FLASH_CMSIS_ALGO"],
- "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
- "macros": ["TWO_RAM_REGIONS", "CMSIS_NVIC_VIRTUAL", "CMSIS_NVIC_VIRTUAL_HEADER_FILE=\"RDA5981_nvic_virtual.h\""],
- "device_has": [
- "USTICKER",
- "PORTIN",
- "PORTOUT",
- "PORTINOUT",
- "INTERRUPTIN",
- "SERIAL",
- "STDIO_MESSAGES",
- "PWMOUT",
- "SPI",
- "SLEEP",
- "ANALOGIN",
- "FLASH",
- "TRNG"
- ],
- "release_versions": ["2", "5"]
- },
- "UNO_91H": {
- "inherits": ["RDA5981X"],
- "detect_code": ["8001"]
- },
- "GD32_Target": {
- "inherits": ["Target"],
- "public": false,
- "extra_labels": ["GigaDevice"],
- "supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
- "device_has": [
- "USTICKER",
- "ANALOGIN",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL"
- ]
- },
- "GD32_F307VG": {
- "inherits": ["GD32_Target"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4",
- "extra_labels_add": ["GD32F30X", "GD32F307VG", "GD_EMAC"],
- "device_has_add": [
- "RTC",
- "I2C",
- "CAN",
- "I2CSLAVE",
- "ANALOGOUT",
- "SPI",
- "SPISLAVE",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "EMAC",
- "FLASH",
- "SLEEP",
- "MPU"
- ],
- "detect_code": ["1701"],
- "macros_add": ["GD32F30X_CL"],
- "release_versions": ["5"],
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "TT_M3HQ": {
- "inherits": ["Target"],
- "core": "Cortex-M3",
- "is_disk_virtual": true,
- "extra_labels": ["TT"],
- "macros": ["__TT_M3HQ__"],
- "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
- "device_has": [
- "ANALOGIN",
- "USTICKER",
- "ANALOGOUT",
- "INTERRUPTIN",
- "PORTIN",
- "PORTINOUT",
- "PORTOUT",
- "PWMOUT",
- "SERIAL",
- "SLEEP",
- "SPI",
- "I2C",
- "I2CSLAVE",
- "STDIO_MESSAGES",
- "MPU"
- ],
- "device_name": "TMPM3HQFDFG",
- "detect_code": ["8012"],
- "release_versions": ["5"]
- },
- "GD32_F450ZI": {
- "inherits": ["GD32_Target"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4",
- "extra_labels_add": ["GD32F4XX", "GD32F450ZI", "GD_EMAC"],
- "device_has_add": [
- "RTC",
- "I2C",
- "CAN",
- "I2CSLAVE",
- "ANALOGOUT",
- "SPI",
- "SPISLAVE",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "EMAC",
- "FLASH",
- "SLEEP",
- "MPU",
- "TRNG"
- ],
- "device_name": "GD32F450ZI",
- "detect_code": ["1702"],
- "macros_add": ["GD32F450"],
- "release_versions": ["5"],
- "overrides": {
- "network-default-interface-type": "ETHERNET"
- }
- },
- "GD32_E103VB": {
- "inherits": ["GD32_Target"],
- "supported_form_factors": ["ARDUINO"],
- "core": "Cortex-M4",
- "extra_labels_add": ["GD32E10X", "GD32E103VB"],
- "device_has_add": [
- "RTC",
- "I2C",
- "CAN",
- "I2CSLAVE",
- "ANALOGOUT",
- "SPI",
- "SPISLAVE",
- "SERIAL_ASYNCH",
- "SERIAL_FC",
- "FLASH",
- "SLEEP"
- ],
- "detect_code": ["1703"],
- "macros_add": ["GD32E10X"],
- "release_versions": ["5"]
- }
-}
--- a/STM32F103C8T6_MPA/mbed_config.h Mon Mar 18 22:36:03 2019 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,54 +0,0 @@ -/* - * mbed SDK - * Copyright (c) 2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -// Automatically generated configuration file. -// DO NOT EDIT, content will be overwritten. - -#ifndef __MBED_CONFIG_DATA__ -#define __MBED_CONFIG_DATA__ - -// Configuration parameters -#define CLOCK_SOURCE USE_PLL_HSE_EXTC|USE_PLL_HSI // set by target:NUCLEO_F103RB -#define CLOCK_SOURCE_USB 0 // set by target:NUCLEO_F103RB -#define LPTICKER_DELAY_TICKS 1 // set by target:FAMILY_STM32 -#define MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED 0 // set by library:platform -#define MBED_CONF_PLATFORM_CTHUNK_COUNT_MAX 8 // set by library:platform -#define MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE 9600 // set by library:platform -#define MBED_CONF_PLATFORM_ERROR_ALL_THREADS_INFO 0 // set by library:platform -#define MBED_CONF_PLATFORM_ERROR_DECODE_HTTP_URL_STR "\nFor more info, visit: https://armmbed.github.io/mbedos-error/?error=0x%08X" // set by library:platform -#define MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED 0 // set by library:platform -#define MBED_CONF_PLATFORM_ERROR_HIST_ENABLED 0 // set by library:platform -#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE 4 // set by library:platform -#define MBED_CONF_PLATFORM_ERROR_REBOOT_MAX 1 // set by library:platform -#define MBED_CONF_PLATFORM_FATAL_ERROR_AUTO_REBOOT_ENABLED 0 // set by library:platform -#define MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR 0 // set by library:platform -#define MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN 16 // set by library:platform -#define MBED_CONF_PLATFORM_POLL_USE_LOWPOWER_TIMER 0 // set by library:platform -#define MBED_CONF_PLATFORM_STDIO_BAUD_RATE 9600 // set by library:platform -#define MBED_CONF_PLATFORM_STDIO_BUFFERED_SERIAL 0 // set by library:platform -#define MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES 0 // set by library:platform -#define MBED_CONF_PLATFORM_STDIO_CONVERT_TTY_NEWLINES 0 // set by library:platform -#define MBED_CONF_PLATFORM_STDIO_FLUSH_AT_EXIT 1 // set by library:platform -#define MBED_CONF_PLATFORM_USE_MPU 1 // set by library:platform -#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x1000 // set by target:Target -#define MBED_CONF_TARGET_DEEP_SLEEP_LATENCY 3 // set by target:FAMILY_STM32 -#define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:FAMILY_STM32 -#define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1 // set by target:FAMILY_STM32 -#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:FAMILY_STM32 -#define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target - -#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X.cpp Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,5554 @@
+/**
+ ******************************************************************************
+ * @file VL53L0X_class.cpp
+ * @author IMG
+ * @version V0.0.1
+ * @date 28-June-2016
+ * @brief Implementation file for the VL53L0X driver class
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+*/
+
+/* Includes */
+#include <stdlib.h>
+
+#include "VL53L0X.h"
+
+//#include "VL53L0X_api_core.h"
+//#include "VL53L0X_api_calibration.h"
+//#include "VL53L0X_api_strings.h"
+#include "VL53L0X_interrupt_threshold_settings.h"
+#include "VL53L0X_tuning.h"
+#include "VL53L0X_types.h"
+
+
+/****************** define for i2c configuration *******************************/
+
+#define TEMP_BUF_SIZE 64
+
+/** Maximum buffer size to be used in i2c */
+#define VL53L0X_MAX_I2C_XFER_SIZE 64 /* Maximum buffer size to be used in i2c */
+#define VL53L0X_I2C_USER_VAR /* none but could be for a flag var to get/pass to mutex interruptible return flags and try again */
+
+
+#define LOG_FUNCTION_START(fmt, ...) \
+ _LOG_FUNCTION_START(TRACE_MODULE_API, fmt, ##__VA_ARGS__)
+#define LOG_FUNCTION_END(status, ...) \
+ _LOG_FUNCTION_END(TRACE_MODULE_API, status, ##__VA_ARGS__)
+#define LOG_FUNCTION_END_FMT(status, fmt, ...) \
+ _LOG_FUNCTION_END_FMT(TRACE_MODULE_API, status, fmt, ##__VA_ARGS__)
+
+#ifdef VL53L0X_LOG_ENABLE
+#define trace_print(level, ...) trace_print_module_function(TRACE_MODULE_API, \
+ level, TRACE_FUNCTION_NONE, ##__VA_ARGS__)
+#endif
+
+#define REF_ARRAY_SPAD_0 0
+#define REF_ARRAY_SPAD_5 5
+#define REF_ARRAY_SPAD_10 10
+
+uint32_t refArrayQuadrants[4] = {REF_ARRAY_SPAD_10, REF_ARRAY_SPAD_5,
+ REF_ARRAY_SPAD_0, REF_ARRAY_SPAD_5
+ };
+
+
+
+
+VL53L0X_Error VL53L0X::VL53L0X_device_read_strobe(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t strobe;
+ uint32_t loop_nb;
+ LOG_FUNCTION_START("");
+
+ status |= VL53L0X_write_byte(dev, 0x83, 0x00);
+
+ /* polling
+ * use timeout to avoid deadlock*/
+ if (status == VL53L0X_ERROR_NONE) {
+ loop_nb = 0;
+ do {
+ status = VL53L0X_read_byte(dev, 0x83, &strobe);
+ if ((strobe != 0x00) || status != VL53L0X_ERROR_NONE) {
+ break;
+ }
+
+ loop_nb = loop_nb + 1;
+ } while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
+
+ if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
+ status = VL53L0X_ERROR_TIME_OUT;
+ }
+ }
+
+ status |= VL53L0X_write_byte(dev, 0x83, 0x01);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_info_from_device(VL53L0X_DEV dev, uint8_t option)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t byte;
+ uint32_t tmp_dword;
+ uint8_t module_id;
+ uint8_t revision;
+ uint8_t reference_spad_count = 0;
+ uint8_t reference_spad_type = 0;
+ uint32_t part_uid_upper = 0;
+ uint32_t part_uid_lower = 0;
+ uint32_t offset_fixed1104_mm = 0;
+ int16_t offset_micro_meters = 0;
+ uint32_t dist_meas_tgt_fixed1104_mm = 400 << 4;
+ uint32_t dist_meas_fixed1104_400_mm = 0;
+ uint32_t signal_rate_meas_fixed1104_400_mm = 0;
+ char product_id[19];
+ char *product_id_tmp;
+ uint8_t read_data_from_device_done;
+ FixPoint1616_t signal_rate_meas_fixed400_mm_fix = 0;
+ uint8_t nvm_ref_good_spad_map[VL53L0X_REF_SPAD_BUFFER_SIZE];
+ int i;
+
+
+ LOG_FUNCTION_START("");
+
+ read_data_from_device_done = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
+ ReadDataFromDeviceDone);
+
+ /* This access is done only once after that a GetDeviceInfo or
+ * datainit is done*/
+ if (read_data_from_device_done != 7) {
+
+ status |= VL53L0X_write_byte(dev, 0x80, 0x01);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x00);
+
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x06);
+ status |= VL53L0X_read_byte(dev, 0x83, &byte);
+ status |= VL53L0X_write_byte(dev, 0x83, byte | 4);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x07);
+ status |= VL53L0X_write_byte(dev, 0x81, 0x01);
+
+ status |= VL53L0X_polling_delay(dev);
+
+ status |= VL53L0X_write_byte(dev, 0x80, 0x01);
+
+ if (((option & 1) == 1) &&
+ ((read_data_from_device_done & 1) == 0)) {
+ status |= VL53L0X_write_byte(dev, 0x94, 0x6b);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ reference_spad_count = (uint8_t)((tmp_dword >> 8) & 0x07f);
+ reference_spad_type = (uint8_t)((tmp_dword >> 15) & 0x01);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x24);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+
+ nvm_ref_good_spad_map[0] = (uint8_t)((tmp_dword >> 24)
+ & 0xff);
+ nvm_ref_good_spad_map[1] = (uint8_t)((tmp_dword >> 16)
+ & 0xff);
+ nvm_ref_good_spad_map[2] = (uint8_t)((tmp_dword >> 8)
+ & 0xff);
+ nvm_ref_good_spad_map[3] = (uint8_t)(tmp_dword & 0xff);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x25);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ nvm_ref_good_spad_map[4] = (uint8_t)((tmp_dword >> 24)
+ & 0xff);
+ nvm_ref_good_spad_map[5] = (uint8_t)((tmp_dword >> 16)
+ & 0xff);
+ }
+
+ if (((option & 2) == 2) &&
+ ((read_data_from_device_done & 2) == 0)) {
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x02);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_byte(dev, 0x90, &module_id);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x7B);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_byte(dev, 0x90, &revision);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x77);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ product_id[0] = (char)((tmp_dword >> 25) & 0x07f);
+ product_id[1] = (char)((tmp_dword >> 18) & 0x07f);
+ product_id[2] = (char)((tmp_dword >> 11) & 0x07f);
+ product_id[3] = (char)((tmp_dword >> 4) & 0x07f);
+
+ byte = (uint8_t)((tmp_dword & 0x00f) << 3);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x78);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ product_id[4] = (char)(byte +
+ ((tmp_dword >> 29) & 0x07f));
+ product_id[5] = (char)((tmp_dword >> 22) & 0x07f);
+ product_id[6] = (char)((tmp_dword >> 15) & 0x07f);
+ product_id[7] = (char)((tmp_dword >> 8) & 0x07f);
+ product_id[8] = (char)((tmp_dword >> 1) & 0x07f);
+
+ byte = (uint8_t)((tmp_dword & 0x001) << 6);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x79);
+
+ status |= VL53L0X_device_read_strobe(dev);
+
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ product_id[9] = (char)(byte +
+ ((tmp_dword >> 26) & 0x07f));
+ product_id[10] = (char)((tmp_dword >> 19) & 0x07f);
+ product_id[11] = (char)((tmp_dword >> 12) & 0x07f);
+ product_id[12] = (char)((tmp_dword >> 5) & 0x07f);
+
+ byte = (uint8_t)((tmp_dword & 0x01f) << 2);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x7A);
+
+ status |= VL53L0X_device_read_strobe(dev);
+
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ product_id[13] = (char)(byte +
+ ((tmp_dword >> 30) & 0x07f));
+ product_id[14] = (char)((tmp_dword >> 23) & 0x07f);
+ product_id[15] = (char)((tmp_dword >> 16) & 0x07f);
+ product_id[16] = (char)((tmp_dword >> 9) & 0x07f);
+ product_id[17] = (char)((tmp_dword >> 2) & 0x07f);
+ product_id[18] = '\0';
+
+ }
+
+ if (((option & 4) == 4) &&
+ ((read_data_from_device_done & 4) == 0)) {
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x7B);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &part_uid_upper);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x7C);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &part_uid_lower);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x73);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ signal_rate_meas_fixed1104_400_mm = (tmp_dword &
+ 0x0000000ff) << 8;
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x74);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ signal_rate_meas_fixed1104_400_mm |= ((tmp_dword &
+ 0xff000000) >> 24);
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x75);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ dist_meas_fixed1104_400_mm = (tmp_dword & 0x0000000ff)
+ << 8;
+
+ status |= VL53L0X_write_byte(dev, 0x94, 0x76);
+ status |= VL53L0X_device_read_strobe(dev);
+ status |= VL53L0X_read_dword(dev, 0x90, &tmp_dword);
+
+ dist_meas_fixed1104_400_mm |= ((tmp_dword & 0xff000000)
+ >> 24);
+ }
+
+ status |= VL53L0X_write_byte(dev, 0x81, 0x00);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x06);
+ status |= VL53L0X_read_byte(dev, 0x83, &byte);
+ status |= VL53L0X_write_byte(dev, 0x83, byte & 0xfb);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x01);
+
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
+ status |= VL53L0X_write_byte(dev, 0x80, 0x00);
+ }
+
+ if ((status == VL53L0X_ERROR_NONE) &&
+ (read_data_from_device_done != 7)) {
+ /* Assign to variable if status is ok */
+ if (((option & 1) == 1) &&
+ ((read_data_from_device_done & 1) == 0)) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadCount, reference_spad_count);
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadType, reference_spad_type);
+
+ for (i = 0; i < VL53L0X_REF_SPAD_BUFFER_SIZE; i++) {
+ dev->Data.SpadData.RefGoodSpadMap[i] =
+ nvm_ref_good_spad_map[i];
+ }
+ }
+
+ if (((option & 2) == 2) &&
+ ((read_data_from_device_done & 2) == 0)) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ ModuleId, module_id);
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ Revision, revision);
+
+ product_id_tmp = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
+ ProductId);
+ VL53L0X_COPYSTRING(product_id_tmp, product_id);
+
+ }
+
+ if (((option & 4) == 4) &&
+ ((read_data_from_device_done & 4) == 0)) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ PartUIDUpper, part_uid_upper);
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ PartUIDLower, part_uid_lower);
+
+ signal_rate_meas_fixed400_mm_fix =
+ VL53L0X_FIXPOINT97TOFIXPOINT1616(
+ signal_rate_meas_fixed1104_400_mm);
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ SignalRateMeasFixed400mm,
+ signal_rate_meas_fixed400_mm_fix);
+
+ offset_micro_meters = 0;
+ if (dist_meas_fixed1104_400_mm != 0) {
+ offset_fixed1104_mm =
+ dist_meas_fixed1104_400_mm -
+ dist_meas_tgt_fixed1104_mm;
+ offset_micro_meters = (offset_fixed1104_mm
+ * 1000) >> 4;
+ offset_micro_meters *= -1;
+ }
+
+ PALDevDataSet(dev,
+ Part2PartOffsetAdjustmentNVMMicroMeter,
+ offset_micro_meters);
+ }
+ byte = (uint8_t)(read_data_from_device_done | option);
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev, ReadDataFromDeviceDone,
+ byte);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t *p_offset_calibration_data_micro_meter)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint16_t range_offset_register;
+ int16_t c_max_offset = 2047;
+ int16_t c_offset_range = 4096;
+
+ /* Note that offset has 10.2 format */
+
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
+ &range_offset_register);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ range_offset_register = (range_offset_register & 0x0fff);
+
+ /* Apply 12 bit 2's compliment conversion */
+ if (range_offset_register > c_max_offset) {
+ *p_offset_calibration_data_micro_meter =
+ (int16_t)(range_offset_register - c_offset_range)
+ * 250;
+ } else {
+ *p_offset_calibration_data_micro_meter =
+ (int16_t)range_offset_register * 250;
+ }
+
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t *p_offset_calibration_data_micro_meter)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_get_offset_calibration_data_micro_meter(dev,
+ p_offset_calibration_data_micro_meter);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t offset_calibration_data_micro_meter)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ int32_t c_max_offset_micro_meter = 511000;
+ int32_t c_min_offset_micro_meter = -512000;
+ int16_t c_offset_range = 4096;
+ uint32_t encoded_offset_val;
+
+ LOG_FUNCTION_START("");
+
+ if (offset_calibration_data_micro_meter > c_max_offset_micro_meter) {
+ offset_calibration_data_micro_meter = c_max_offset_micro_meter;
+ } else {
+ if (offset_calibration_data_micro_meter < c_min_offset_micro_meter) {
+ offset_calibration_data_micro_meter = c_min_offset_micro_meter;
+ }
+ }
+
+ /* The offset register is 10.2 format and units are mm
+ * therefore conversion is applied by a division of
+ * 250.
+ */
+ if (offset_calibration_data_micro_meter >= 0) {
+ encoded_offset_val =
+ offset_calibration_data_micro_meter / 250;
+ } else {
+ encoded_offset_val =
+ c_offset_range +
+ offset_calibration_data_micro_meter / 250;
+ }
+
+ status = VL53L0X_write_word(dev,
+ VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM,
+ encoded_offset_val);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t offset_calibration_data_micro_meter)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_set_offset_calibration_data_micro_meter(dev,
+ offset_calibration_data_micro_meter);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_apply_offset_adjustment(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ int32_t corrected_offset_micro_meters;
+ int32_t current_offset_micro_meters;
+
+ /* if we run on this function we can read all the NVM info
+ * used by the API */
+ status = VL53L0X_get_info_from_device(dev, 7);
+
+ /* Read back current device offset */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_offset_calibration_data_micro_meter(dev,
+ ¤t_offset_micro_meters);
+ }
+
+ /* Apply Offset Adjustment derived from 400mm measurements */
+ if (status == VL53L0X_ERROR_NONE) {
+
+ /* Store initial device offset */
+ PALDevDataSet(dev, Part2PartOffsetNVMMicroMeter,
+ current_offset_micro_meters);
+
+ corrected_offset_micro_meters = current_offset_micro_meters +
+ (int32_t)PALDevDataGet(dev,
+ Part2PartOffsetAdjustmentNVMMicroMeter);
+
+ status = VL53L0X_set_offset_calibration_data_micro_meter(dev,
+ corrected_offset_micro_meters);
+
+ /* store current, adjusted offset */
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETPARAMETERFIELD(dev, RangeOffsetMicroMeters,
+ corrected_offset_micro_meters);
+ }
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_device_mode(VL53L0X_DEV dev,
+ VL53L0X_DeviceModes *p_device_mode)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ VL53L0X_GETPARAMETERFIELD(dev, DeviceMode, *p_device_mode);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_inter_measurement_period_milli_seconds(VL53L0X_DEV dev,
+ uint32_t *p_inter_measurement_period_milli_seconds)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint16_t osc_calibrate_val;
+ uint32_t im_period_milli_seconds;
+
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_read_word(dev, VL53L0X_REG_OSC_CALIBRATE_VAL,
+ &osc_calibrate_val);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_dword(dev,
+ VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD,
+ &im_period_milli_seconds);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (osc_calibrate_val != 0) {
+ *p_inter_measurement_period_milli_seconds =
+ im_period_milli_seconds / osc_calibrate_val;
+ }
+ VL53L0X_SETPARAMETERFIELD(dev,
+ InterMeasurementPeriodMilliSeconds,
+ *p_inter_measurement_period_milli_seconds);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_x_talk_compensation_rate_mega_cps(VL53L0X_DEV dev,
+ FixPoint1616_t *p_xtalk_compensation_rate_mega_cps)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint16_t value;
+ FixPoint1616_t temp_fix1616;
+
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS, (uint16_t *)&value);
+ if (status == VL53L0X_ERROR_NONE) {
+ if (value == 0) {
+ /* the Xtalk is disabled return value from memory */
+ VL53L0X_GETPARAMETERFIELD(dev,
+ XTalkCompensationRateMegaCps, temp_fix1616);
+ *p_xtalk_compensation_rate_mega_cps = temp_fix1616;
+ VL53L0X_SETPARAMETERFIELD(dev, XTalkCompensationEnable,
+ 0);
+ } else {
+ temp_fix1616 = VL53L0X_FIXPOINT313TOFIXPOINT1616(value);
+ *p_xtalk_compensation_rate_mega_cps = temp_fix1616;
+ VL53L0X_SETPARAMETERFIELD(dev,
+ XTalkCompensationRateMegaCps, temp_fix1616);
+ VL53L0X_SETPARAMETERFIELD(dev, XTalkCompensationEnable,
+ 1);
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
+ FixPoint1616_t *p_limit_check_value)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t enable_zero_value = 0;
+ uint16_t temp16;
+ FixPoint1616_t temp_fix1616;
+
+ LOG_FUNCTION_START("");
+
+ switch (limit_check_id) {
+
+ case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+ /* internal computation: */
+ VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, temp_fix1616);
+ enable_zero_value = 0;
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
+ &temp16);
+ if (status == VL53L0X_ERROR_NONE) {
+ temp_fix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(temp16);
+ }
+
+
+ enable_zero_value = 1;
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+ /* internal computation: */
+ VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, temp_fix1616);
+ enable_zero_value = 0;
+ break;
+
+ case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+ /* internal computation: */
+ VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, temp_fix1616);
+ enable_zero_value = 0;
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
+ &temp16);
+ if (status == VL53L0X_ERROR_NONE) {
+ temp_fix1616 = VL53L0X_FIXPOINT97TOFIXPOINT1616(temp16);
+ }
+
+
+ enable_zero_value = 0;
+ break;
+
+ default:
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+
+ if (enable_zero_value == 1) {
+
+ if (temp_fix1616 == 0) {
+ /* disabled: return value from memory */
+ VL53L0X_GETARRAYPARAMETERFIELD(dev,
+ LimitChecksValue, limit_check_id,
+ temp_fix1616);
+ *p_limit_check_value = temp_fix1616;
+ VL53L0X_SETARRAYPARAMETERFIELD(dev,
+ LimitChecksEnable, limit_check_id, 0);
+ } else {
+ *p_limit_check_value = temp_fix1616;
+ VL53L0X_SETARRAYPARAMETERFIELD(dev,
+ LimitChecksValue, limit_check_id,
+ temp_fix1616);
+ VL53L0X_SETARRAYPARAMETERFIELD(dev,
+ LimitChecksEnable, limit_check_id, 1);
+ }
+ } else {
+ *p_limit_check_value = temp_fix1616;
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
+ uint8_t *p_limit_check_enable)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t temp8;
+
+ LOG_FUNCTION_START("");
+
+ if (limit_check_id >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ *p_limit_check_enable = 0;
+ } else {
+ VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
+ limit_check_id, temp8);
+ *p_limit_check_enable = temp8;
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_wrap_around_check_enable(VL53L0X_DEV dev,
+ uint8_t *p_wrap_around_check_enable)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t data;
+
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, &data);
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, SequenceConfig, data);
+ if (data & (0x01 << 7)) {
+ *p_wrap_around_check_enable = 0x01;
+ } else {
+ *p_wrap_around_check_enable = 0x00;
+ }
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETPARAMETERFIELD(dev, WrapAroundCheckEnable,
+ *p_wrap_around_check_enable);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::sequence_step_enabled(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_config,
+ uint8_t *p_sequence_step_enabled)
+{
+ VL53L0X_Error Status = VL53L0X_ERROR_NONE;
+ *p_sequence_step_enabled = 0;
+ LOG_FUNCTION_START("");
+
+ switch (sequence_step_id) {
+ case VL53L0X_SEQUENCESTEP_TCC:
+ *p_sequence_step_enabled = (sequence_config & 0x10) >> 4;
+ break;
+ case VL53L0X_SEQUENCESTEP_DSS:
+ *p_sequence_step_enabled = (sequence_config & 0x08) >> 3;
+ break;
+ case VL53L0X_SEQUENCESTEP_MSRC:
+ *p_sequence_step_enabled = (sequence_config & 0x04) >> 2;
+ break;
+ case VL53L0X_SEQUENCESTEP_PRE_RANGE:
+ *p_sequence_step_enabled = (sequence_config & 0x40) >> 6;
+ break;
+ case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
+ *p_sequence_step_enabled = (sequence_config & 0x80) >> 7;
+ break;
+ default:
+ Status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+
+ LOG_FUNCTION_END(status);
+ return Status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_sequence_step_enables(VL53L0X_DEV dev,
+ VL53L0X_SchedulerSequenceSteps_t *p_scheduler_sequence_steps)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t sequence_config = 0;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+ &sequence_config);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = sequence_step_enabled(dev,
+ VL53L0X_SEQUENCESTEP_TCC, sequence_config,
+ &p_scheduler_sequence_steps->TccOn);
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ status = sequence_step_enabled(dev,
+ VL53L0X_SEQUENCESTEP_DSS, sequence_config,
+ &p_scheduler_sequence_steps->DssOn);
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ status = sequence_step_enabled(dev,
+ VL53L0X_SEQUENCESTEP_MSRC, sequence_config,
+ &p_scheduler_sequence_steps->MsrcOn);
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ status = sequence_step_enabled(dev,
+ VL53L0X_SEQUENCESTEP_PRE_RANGE, sequence_config,
+ &p_scheduler_sequence_steps->PreRangeOn);
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ status = sequence_step_enabled(dev,
+ VL53L0X_SEQUENCESTEP_FINAL_RANGE, sequence_config,
+ &p_scheduler_sequence_steps->FinalRangeOn);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+uint8_t VL53L0X::VL53L0X_decode_vcsel_period(uint8_t vcsel_period_reg)
+{
+ /*!
+ * Converts the encoded VCSEL period register value into the real
+ * period in PLL clocks
+ */
+
+ uint8_t vcsel_period_pclks = 0;
+
+ vcsel_period_pclks = (vcsel_period_reg + 1) << 1;
+
+ return vcsel_period_pclks;
+}
+
+uint8_t VL53L0X::lv53l0x_encode_vcsel_period(uint8_t vcsel_period_pclks)
+{
+ /*!
+ * Converts the encoded VCSEL period register value into the real period
+ * in PLL clocks
+ */
+
+ uint8_t vcsel_period_reg = 0;
+
+ vcsel_period_reg = (vcsel_period_pclks >> 1) - 1;
+
+ return vcsel_period_reg;
+}
+
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period_pclk)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t vcsel_period_reg;
+ uint8_t min_pre_vcsel_period_pclk = 12;
+ uint8_t max_pre_vcsel_period_pclk = 18;
+ uint8_t min_final_vcsel_period_pclk = 8;
+ uint8_t max_final_vcsel_period_pclk = 14;
+ uint32_t measurement_timing_budget_micro_seconds;
+ uint32_t final_range_timeout_micro_seconds;
+ uint32_t pre_range_timeout_micro_seconds;
+ uint32_t msrc_timeout_micro_seconds;
+ uint8_t phase_cal_int = 0;
+
+ /* Check if valid clock period requested */
+
+ if ((vcsel_pulse_period_pclk % 2) != 0) {
+ /* Value must be an even number */
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ } else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_PRE_RANGE &&
+ (vcsel_pulse_period_pclk < min_pre_vcsel_period_pclk ||
+ vcsel_pulse_period_pclk > max_pre_vcsel_period_pclk)) {
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ } else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_FINAL_RANGE &&
+ (vcsel_pulse_period_pclk < min_final_vcsel_period_pclk ||
+ vcsel_pulse_period_pclk > max_final_vcsel_period_pclk)) {
+
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+
+ /* Apply specific settings for the requested clock period */
+
+ if (status != VL53L0X_ERROR_NONE) {
+ return status;
+ }
+
+
+ if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_PRE_RANGE) {
+
+ /* Set phase check limits */
+ if (vcsel_pulse_period_pclk == 12) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x18);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+ } else if (vcsel_pulse_period_pclk == 14) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x30);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+ } else if (vcsel_pulse_period_pclk == 16) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x40);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+ } else if (vcsel_pulse_period_pclk == 18) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x50);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+ }
+ } else if (vcsel_period_type == VL53L0X_VCSEL_PERIOD_FINAL_RANGE) {
+
+ if (vcsel_pulse_period_pclk == 8) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x10);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x02);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x0C);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x01);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_LIM,
+ 0x30);
+ status |= VL53L0X_write_byte(dev, 0xff, 0x00);
+ } else if (vcsel_pulse_period_pclk == 10) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x28);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x09);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x01);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_LIM,
+ 0x20);
+ status |= VL53L0X_write_byte(dev, 0xff, 0x00);
+ } else if (vcsel_pulse_period_pclk == 12) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x38);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x08);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x01);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_LIM,
+ 0x20);
+ status |= VL53L0X_write_byte(dev, 0xff, 0x00);
+ } else if (vcsel_pulse_period_pclk == 14) {
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH,
+ 0x048);
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW,
+ 0x08);
+
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT, 0x07);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x01);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_ALGO_PHASECAL_LIM,
+ 0x20);
+ status |= VL53L0X_write_byte(dev, 0xff, 0x00);
+ }
+ }
+
+
+ /* Re-calculate and apply timeouts, in macro periods */
+
+ if (status == VL53L0X_ERROR_NONE) {
+ vcsel_period_reg = lv53l0x_encode_vcsel_period((uint8_t)
+ vcsel_pulse_period_pclk);
+
+ /* When the VCSEL period for the pre or final range is changed,
+ * the corresponding timeout must be read from the device using
+ * the current VCSEL period, then the new VCSEL period can be
+ * applied. The timeout then must be written back to the device
+ * using the new VCSEL period.
+ *
+ * For the MSRC timeout, the same applies - this timeout being
+ * dependant on the pre-range vcsel period.
+ */
+ switch (vcsel_period_type) {
+ case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_PRE_RANGE,
+ &pre_range_timeout_micro_seconds);
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_MSRC,
+ &msrc_timeout_micro_seconds);
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
+ vcsel_period_reg);
+
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = set_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_PRE_RANGE,
+ pre_range_timeout_micro_seconds);
+
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = set_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_MSRC,
+ msrc_timeout_micro_seconds);
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ PreRangeVcselPulsePeriod,
+ vcsel_pulse_period_pclk);
+ break;
+ case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+ &final_range_timeout_micro_seconds);
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
+ vcsel_period_reg);
+
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = set_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+ final_range_timeout_micro_seconds);
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ FinalRangeVcselPulsePeriod,
+ vcsel_pulse_period_pclk);
+ break;
+ default:
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ }
+
+ /* Finally, the timing budget must be re-applied */
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_GETPARAMETERFIELD(dev,
+ MeasurementTimingBudgetMicroSeconds,
+ measurement_timing_budget_micro_seconds);
+
+ status = VL53L0X_set_measurement_timing_budget_micro_seconds(dev,
+ measurement_timing_budget_micro_seconds);
+ }
+
+ /* Perform the phase calibration. This is needed after changing on
+ * vcsel period.
+ * get_data_enable = 0, restore_config = 1 */
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_perform_phase_calibration(
+ dev, &phase_cal_int, 0, 1);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_set_vcsel_pulse_period(dev, vcsel_period_type,
+ vcsel_pulse_period);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t vcsel_period_reg;
+
+ switch (vcsel_period_type) {
+ case VL53L0X_VCSEL_PERIOD_PRE_RANGE:
+ status = VL53L0X_read_byte(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD,
+ &vcsel_period_reg);
+ break;
+ case VL53L0X_VCSEL_PERIOD_FINAL_RANGE:
+ status = VL53L0X_read_byte(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD,
+ &vcsel_period_reg);
+ break;
+ default:
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+
+ if (status == VL53L0X_ERROR_NONE)
+ *p_vcsel_pulse_period_pclk =
+ VL53L0X_decode_vcsel_period(vcsel_period_reg);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_get_vcsel_pulse_period(dev, vcsel_period_type,
+ p_vcsel_pulse_period_pclk);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+uint32_t VL53L0X::VL53L0X_decode_timeout(uint16_t encoded_timeout)
+{
+ /*!
+ * Decode 16-bit timeout register value - format (LSByte * 2^MSByte) + 1
+ */
+
+ uint32_t timeout_macro_clks = 0;
+
+ timeout_macro_clks = ((uint32_t)(encoded_timeout & 0x00FF)
+ << (uint32_t)((encoded_timeout & 0xFF00) >> 8)) + 1;
+
+ return timeout_macro_clks;
+}
+
+uint32_t VL53L0X::VL53L0X_calc_macro_period_ps(VL53L0X_DEV dev, uint8_t vcsel_period_pclks)
+{
+ uint64_t pll_period_ps;
+ uint32_t macro_period_vclks;
+ uint32_t macro_period_ps;
+
+ LOG_FUNCTION_START("");
+
+ /* The above calculation will produce rounding errors,
+ therefore set fixed value
+ */
+ pll_period_ps = 1655;
+
+ macro_period_vclks = 2304;
+ macro_period_ps = (uint32_t)(macro_period_vclks
+ * vcsel_period_pclks * pll_period_ps);
+
+ LOG_FUNCTION_END("");
+ return macro_period_ps;
+}
+
+/* To convert register value into us */
+uint32_t VL53L0X::VL53L0X_calc_timeout_us(VL53L0X_DEV dev,
+ uint16_t timeout_period_mclks,
+ uint8_t vcsel_period_pclks)
+{
+ uint32_t macro_period_ps;
+ uint32_t macro_period_ns;
+ uint32_t actual_timeout_period_us = 0;
+
+ macro_period_ps = VL53L0X_calc_macro_period_ps(dev, vcsel_period_pclks);
+ macro_period_ns = (macro_period_ps + 500) / 1000;
+
+ actual_timeout_period_us =
+ ((timeout_period_mclks * macro_period_ns) + 500) / 1000;
+
+ return actual_timeout_period_us;
+}
+
+VL53L0X_Error VL53L0X::get_sequence_step_timeout(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id,
+ uint32_t *p_time_out_micro_secs)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t current_vcsel_pulse_period_p_clk;
+ uint8_t encoded_time_out_byte = 0;
+ uint32_t timeout_micro_seconds = 0;
+ uint16_t pre_range_encoded_time_out = 0;
+ uint16_t msrc_time_out_m_clks;
+ uint16_t pre_range_time_out_m_clks;
+ uint16_t final_range_time_out_m_clks = 0;
+ uint16_t final_range_encoded_time_out;
+ VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
+
+ if ((sequence_step_id == VL53L0X_SEQUENCESTEP_TCC) ||
+ (sequence_step_id == VL53L0X_SEQUENCESTEP_DSS) ||
+ (sequence_step_id == VL53L0X_SEQUENCESTEP_MSRC)) {
+
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_byte(dev,
+ VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
+ &encoded_time_out_byte);
+ }
+ msrc_time_out_m_clks = VL53L0X_decode_timeout(encoded_time_out_byte);
+
+ timeout_micro_seconds = VL53L0X_calc_timeout_us(dev,
+ msrc_time_out_m_clks,
+ current_vcsel_pulse_period_p_clk);
+ } else if (sequence_step_id == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
+ /* Retrieve PRE-RANGE VCSEL Period */
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+
+ /* Retrieve PRE-RANGE Timeout in Macro periods (MCLKS) */
+ if (status == VL53L0X_ERROR_NONE) {
+
+ /* Retrieve PRE-RANGE VCSEL Period */
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+ &pre_range_encoded_time_out);
+ }
+
+ pre_range_time_out_m_clks = VL53L0X_decode_timeout(
+ pre_range_encoded_time_out);
+
+ timeout_micro_seconds = VL53L0X_calc_timeout_us(dev,
+ pre_range_time_out_m_clks,
+ current_vcsel_pulse_period_p_clk);
+ }
+ } else if (sequence_step_id == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
+
+ VL53L0X_get_sequence_step_enables(dev, &scheduler_sequence_steps);
+ pre_range_time_out_m_clks = 0;
+
+ if (scheduler_sequence_steps.PreRangeOn) {
+ /* Retrieve PRE-RANGE VCSEL Period */
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+
+ /* Retrieve PRE-RANGE Timeout in Macro periods
+ * (MCLKS) */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+ &pre_range_encoded_time_out);
+ pre_range_time_out_m_clks = VL53L0X_decode_timeout(
+ pre_range_encoded_time_out);
+ }
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Retrieve FINAL-RANGE VCSEL Period */
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+ }
+
+ /* Retrieve FINAL-RANGE Timeout in Macro periods (MCLKS) */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+ &final_range_encoded_time_out);
+ final_range_time_out_m_clks = VL53L0X_decode_timeout(
+ final_range_encoded_time_out);
+ }
+
+ final_range_time_out_m_clks -= pre_range_time_out_m_clks;
+ timeout_micro_seconds = VL53L0X_calc_timeout_us(dev,
+ final_range_time_out_m_clks,
+ current_vcsel_pulse_period_p_clk);
+ }
+
+ *p_time_out_micro_secs = timeout_micro_seconds;
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t *p_measurement_timing_budget_micro_seconds)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
+ uint32_t final_range_timeout_micro_seconds;
+ uint32_t msrc_dcc_tcc_timeout_micro_seconds = 2000;
+ uint32_t start_overhead_micro_seconds = 1910;
+ uint32_t end_overhead_micro_seconds = 960;
+ uint32_t msrc_overhead_micro_seconds = 660;
+ uint32_t tcc_overhead_micro_seconds = 590;
+ uint32_t dss_overhead_micro_seconds = 690;
+ uint32_t pre_range_overhead_micro_seconds = 660;
+ uint32_t final_range_overhead_micro_seconds = 550;
+ uint32_t pre_range_timeout_micro_seconds = 0;
+
+ LOG_FUNCTION_START("");
+
+ /* Start and end overhead times always present */
+ *p_measurement_timing_budget_micro_seconds
+ = start_overhead_micro_seconds + end_overhead_micro_seconds;
+
+ status = VL53L0X_get_sequence_step_enables(dev, &scheduler_sequence_steps);
+
+ if (status != VL53L0X_ERROR_NONE) {
+ LOG_FUNCTION_END(status);
+ return status;
+ }
+
+
+ if (scheduler_sequence_steps.TccOn ||
+ scheduler_sequence_steps.MsrcOn ||
+ scheduler_sequence_steps.DssOn) {
+
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_MSRC,
+ &msrc_dcc_tcc_timeout_micro_seconds);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (scheduler_sequence_steps.TccOn) {
+ *p_measurement_timing_budget_micro_seconds +=
+ msrc_dcc_tcc_timeout_micro_seconds +
+ tcc_overhead_micro_seconds;
+ }
+
+ if (scheduler_sequence_steps.DssOn) {
+ *p_measurement_timing_budget_micro_seconds +=
+ 2 * (msrc_dcc_tcc_timeout_micro_seconds +
+ dss_overhead_micro_seconds);
+ } else if (scheduler_sequence_steps.MsrcOn) {
+ *p_measurement_timing_budget_micro_seconds +=
+ msrc_dcc_tcc_timeout_micro_seconds +
+ msrc_overhead_micro_seconds;
+ }
+ }
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (scheduler_sequence_steps.PreRangeOn) {
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_PRE_RANGE,
+ &pre_range_timeout_micro_seconds);
+ *p_measurement_timing_budget_micro_seconds +=
+ pre_range_timeout_micro_seconds +
+ pre_range_overhead_micro_seconds;
+ }
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (scheduler_sequence_steps.FinalRangeOn) {
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+ &final_range_timeout_micro_seconds);
+ *p_measurement_timing_budget_micro_seconds +=
+ (final_range_timeout_micro_seconds +
+ final_range_overhead_micro_seconds);
+ }
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETPARAMETERFIELD(dev,
+ MeasurementTimingBudgetMicroSeconds,
+ *p_measurement_timing_budget_micro_seconds);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t *p_measurement_timing_budget_micro_seconds)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(dev,
+ p_measurement_timing_budget_micro_seconds);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_device_parameters(VL53L0X_DEV dev,
+ VL53L0X_DeviceParameters_t *p_device_parameters)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ int i;
+
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_get_device_mode(dev, &(p_device_parameters->DeviceMode));
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_get_inter_measurement_period_milli_seconds(dev,
+ &(p_device_parameters->InterMeasurementPeriodMilliSeconds));
+
+
+ if (status == VL53L0X_ERROR_NONE) {
+ p_device_parameters->XTalkCompensationEnable = 0;
+ }
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_get_x_talk_compensation_rate_mega_cps(dev,
+ &(p_device_parameters->XTalkCompensationRateMegaCps));
+
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_get_offset_calibration_data_micro_meter(dev,
+ &(p_device_parameters->RangeOffsetMicroMeters));
+
+
+ if (status == VL53L0X_ERROR_NONE) {
+ for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
+ /* get first the values, then the enables.
+ * VL53L0X_GetLimitCheckValue will modify the enable
+ * flags
+ */
+ if (status == VL53L0X_ERROR_NONE) {
+ status |= VL53L0X_get_limit_check_value(dev, i,
+ &(p_device_parameters->LimitChecksValue[i]));
+ } else {
+ break;
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ status |= VL53L0X_get_limit_check_enable(dev, i,
+ &(p_device_parameters->LimitChecksEnable[i]));
+ } else {
+ break;
+ }
+ }
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_wrap_around_check_enable(dev,
+ &(p_device_parameters->WrapAroundCheckEnable));
+ }
+
+ /* Need to be done at the end as it uses VCSELPulsePeriod */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_measurement_timing_budget_micro_seconds(dev,
+ &(p_device_parameters->MeasurementTimingBudgetMicroSeconds));
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
+ FixPoint1616_t limit_check_value)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t temp8;
+
+ LOG_FUNCTION_START("");
+
+ VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksEnable, limit_check_id,
+ temp8);
+
+ if (temp8 == 0) { /* disabled write only internal value */
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ limit_check_id, limit_check_value);
+ } else {
+
+ switch (limit_check_id) {
+
+ case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+ /* internal computation: */
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+ limit_check_value);
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+
+ status = VL53L0X_write_word(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
+ VL53L0X_FIXPOINT1616TOFIXPOINT97(
+ limit_check_value));
+
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+
+ /* internal computation: */
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+ limit_check_value);
+
+ break;
+
+ case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+
+ /* internal computation: */
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+ limit_check_value);
+
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+
+ status = VL53L0X_write_word(dev,
+ VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT,
+ VL53L0X_FIXPOINT1616TOFIXPOINT97(
+ limit_check_value));
+
+ break;
+
+ default:
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ limit_check_id, limit_check_value);
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_data_init(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ VL53L0X_DeviceParameters_t CurrentParameters;
+ int i;
+ uint8_t StopVariable;
+
+ LOG_FUNCTION_START("");
+
+ /* by default the I2C is running at 1V8 if you want to change it you
+ * need to include this define at compilation level. */
+#ifdef USE_I2C_2V8
+#if ORIGINAL
+ Status = VL53L0X_UpdateByte(Dev,
+ VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
+ 0xFE,
+ 0x01);
+#else
+ status = VL53L0X_update_byte(dev,
+ VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
+ 0xFE,
+ 0x01);
+#endif
+#endif
+
+ /* Set I2C standard mode */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0x88, 0x00);
+ }
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev, ReadDataFromDeviceDone, 0);
+
+#ifdef USE_IQC_STATION
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_apply_offset_adjustment(Dev);
+ }
+#endif
+
+ /* Default value is 1000 for Linearity Corrective Gain */
+ PALDevDataSet(dev, LinearityCorrectiveGain, 1000);
+
+ /* Dmax default Parameter */
+ PALDevDataSet(dev, DmaxCalRangeMilliMeter, 400);
+ PALDevDataSet(dev, DmaxCalSignalRateRtnMegaCps,
+ (FixPoint1616_t)((0x00016B85))); /* 1.42 No Cover Glass*/
+
+ /* Set Default static parameters
+ *set first temporary values 9.44MHz * 65536 = 618660 */
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev, OscFrequencyMHz, 618660);
+
+ /* Set Default XTalkCompensationRateMegaCps to 0 */
+ VL53L0X_SETPARAMETERFIELD(dev, XTalkCompensationRateMegaCps, 0);
+
+ /* Get default parameters */
+ status = VL53L0X_get_device_parameters(dev, &CurrentParameters);
+ if (status == VL53L0X_ERROR_NONE) {
+ /* initialize PAL values */
+ CurrentParameters.DeviceMode = VL53L0X_DEVICEMODE_SINGLE_RANGING;
+ CurrentParameters.HistogramMode = VL53L0X_HISTOGRAMMODE_DISABLED;
+ PALDevDataSet(dev, CurrentParameters, CurrentParameters);
+ }
+
+ /* Sigma estimator variable */
+ PALDevDataSet(dev, SigmaEstRefArray, 100);
+ PALDevDataSet(dev, SigmaEstEffPulseWidth, 900);
+ PALDevDataSet(dev, SigmaEstEffAmbWidth, 500);
+ PALDevDataSet(dev, targetRefRate, 0x0A00); /* 20 MCPS in 9:7 format */
+
+ /* Use internal default settings */
+ PALDevDataSet(dev, UseInternalTuningSettings, 1);
+
+ status |= VL53L0X_write_byte(dev, 0x80, 0x01);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x00);
+ status |= VL53L0X_read_byte(dev, 0x91, &StopVariable);
+ PALDevDataSet(dev, StopVariable, StopVariable);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x01);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
+ status |= VL53L0X_write_byte(dev, 0x80, 0x00);
+
+ /* Enable all check */
+ for (i = 0; i < VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS; i++) {
+ if (status == VL53L0X_ERROR_NONE) {
+ status |= VL53L0X_set_limit_check_enable(dev, i, 1);
+ } else {
+ break;
+ }
+
+ }
+
+ /* Disable the following checks */
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_set_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, 0);
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_set_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD, 0);
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_set_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC, 0);
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_set_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE, 0);
+
+ /* Limit default values */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_set_limit_check_value(dev,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+ (FixPoint1616_t)(18 * 65536));
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_set_limit_check_value(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
+ (FixPoint1616_t)(25 * 65536 / 100));
+ /* 0.25 * 65536 */
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_set_limit_check_value(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+ (FixPoint1616_t)(35 * 65536));
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_set_limit_check_value(dev,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+ (FixPoint1616_t)(0 * 65536));
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+
+ PALDevDataSet(dev, SequenceConfig, 0xFF);
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+ 0xFF);
+
+ /* Set PAL state to tell that we are waiting for call to
+ * VL53L0X_StaticInit */
+ PALDevDataSet(dev, PalState, VL53L0X_STATE_WAIT_STATICINIT);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev, RefSpadsInitialised, 0);
+ }
+
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_check_part_used(VL53L0X_DEV dev,
+ uint8_t *revision,
+ VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t module_id_int;
+ char *product_id_tmp;
+
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_get_info_from_device(dev, 2);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ module_id_int = VL53L0X_GETDEVICESPECIFICPARAMETER(dev, ModuleId);
+
+ if (module_id_int == 0) {
+ *revision = 0;
+ VL53L0X_COPYSTRING(p_VL53L0X_device_info->ProductId, "");
+ } else {
+ *revision = VL53L0X_GETDEVICESPECIFICPARAMETER(dev, Revision);
+ product_id_tmp = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
+ ProductId);
+ VL53L0X_COPYSTRING(p_VL53L0X_device_info->ProductId, product_id_tmp);
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_get_device_info(VL53L0X_DEV dev,
+ VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t revision_id;
+ uint8_t revision;
+
+ status = VL53L0X_check_part_used(dev, &revision, p_VL53L0X_device_info);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (revision == 0) {
+ VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
+ VL53L0X_STRING_DEVICE_INFO_NAME_TS0);
+ } else if ((revision <= 34) && (revision != 32)) {
+ VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
+ VL53L0X_STRING_DEVICE_INFO_NAME_TS1);
+ } else if (revision < 39) {
+ VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
+ VL53L0X_STRING_DEVICE_INFO_NAME_TS2);
+ } else {
+ VL53L0X_COPYSTRING(p_VL53L0X_device_info->Name,
+ VL53L0X_STRING_DEVICE_INFO_NAME_ES1);
+ }
+
+ VL53L0X_COPYSTRING(p_VL53L0X_device_info->Type,
+ VL53L0X_STRING_DEVICE_INFO_TYPE);
+
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_byte(dev, VL53L0X_REG_IDENTIFICATION_MODEL_ID,
+ &p_VL53L0X_device_info->ProductType);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_byte(dev,
+ VL53L0X_REG_IDENTIFICATION_REVISION_ID,
+ &revision_id);
+ p_VL53L0X_device_info->ProductRevisionMajor = 1;
+ p_VL53L0X_device_info->ProductRevisionMinor =
+ (revision_id & 0xF0) >> 4;
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_device_info(VL53L0X_DEV dev,
+ VL53L0X_DeviceInfo_t *p_VL53L0X_device_info)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_get_device_info(dev, p_VL53L0X_device_info);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_interrupt_mask_status(VL53L0X_DEV dev,
+ uint32_t *p_interrupt_mask_status)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t byte;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_read_byte(dev, VL53L0X_REG_RESULT_INTERRUPT_STATUS, &byte);
+ *p_interrupt_mask_status = byte & 0x07;
+
+ if (byte & 0x18) {
+ status = VL53L0X_ERROR_RANGE_ERROR;
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_measurement_data_ready(VL53L0X_DEV dev,
+ uint8_t *p_measurement_data_ready)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t sys_range_status_register;
+ uint8_t interrupt_config;
+ uint32_t interrupt_mask;
+ LOG_FUNCTION_START("");
+
+ interrupt_config = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
+ Pin0GpioFunctionality);
+
+ if (interrupt_config ==
+ VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY) {
+ status = VL53L0X_get_interrupt_mask_status(dev, &interrupt_mask);
+ if (interrupt_mask ==
+ VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY) {
+ *p_measurement_data_ready = 1;
+ } else {
+ *p_measurement_data_ready = 0;
+ }
+ } else {
+ status = VL53L0X_read_byte(dev, VL53L0X_REG_RESULT_RANGE_STATUS,
+ &sys_range_status_register);
+ if (status == VL53L0X_ERROR_NONE) {
+ if (sys_range_status_register & 0x01) {
+ *p_measurement_data_ready = 1;
+ } else {
+ *p_measurement_data_ready = 0;
+ }
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_polling_delay(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+
+ // do nothing
+ VL53L0X_OsDelay();
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_measurement_poll_for_completion(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t new_data_ready = 0;
+ uint32_t loop_nb;
+
+ LOG_FUNCTION_START("");
+
+ loop_nb = 0;
+
+ do {
+ status = VL53L0X_get_measurement_data_ready(dev, &new_data_ready);
+ if (status != 0) {
+ break; /* the error is set */
+ }
+
+ if (new_data_ready == 1) {
+ break; /* done note that status == 0 */
+ }
+
+ loop_nb++;
+ if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
+ status = VL53L0X_ERROR_TIME_OUT;
+ break;
+ }
+
+ VL53L0X_polling_delay(dev);
+ } while (1);
+
+ LOG_FUNCTION_END(status);
+
+ return status;
+}
+
+/* Group PAL Interrupt Functions */
+VL53L0X_Error VL53L0X::VL53L0X_clear_interrupt_mask(VL53L0X_DEV dev, uint32_t interrupt_mask)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t loop_count;
+ uint8_t byte;
+ LOG_FUNCTION_START("");
+
+ /* clear bit 0 range interrupt, bit 1 error interrupt */
+ loop_count = 0;
+ do {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR, 0x01);
+ status |= VL53L0X_write_byte(dev,
+ VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR, 0x00);
+ status |= VL53L0X_read_byte(dev,
+ VL53L0X_REG_RESULT_INTERRUPT_STATUS, &byte);
+ loop_count++;
+ } while (((byte & 0x07) != 0x00)
+ && (loop_count < 3)
+ && (status == VL53L0X_ERROR_NONE));
+
+
+ if (loop_count >= 3) {
+ status = VL53L0X_ERROR_INTERRUPT_NOT_CLEARED;
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_perform_single_ref_calibration(VL53L0X_DEV dev,
+ uint8_t vhv_init_byte)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START,
+ VL53L0X_REG_SYSRANGE_MODE_START_STOP |
+ vhv_init_byte);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_measurement_poll_for_completion(dev);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_clear_interrupt_mask(dev, 0);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START, 0x00);
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_ref_calibration_io(VL53L0X_DEV dev, uint8_t read_not_write,
+ uint8_t vhv_settings, uint8_t phase_cal,
+ uint8_t *p_vhv_settings, uint8_t *p_phase_cal,
+ const uint8_t vhv_enable, const uint8_t phase_enable)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t phase_calint = 0;
+
+ /* Read VHV from device */
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x00);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
+
+ if (read_not_write) {
+ if (vhv_enable) {
+ status |= VL53L0X_read_byte(dev, 0xCB, p_vhv_settings);
+ }
+ if (phase_enable) {
+ status |= VL53L0X_read_byte(dev, 0xEE, &phase_calint);
+ }
+ } else {
+ if (vhv_enable) {
+ status |= VL53L0X_write_byte(dev, 0xCB, vhv_settings);
+ }
+ if (phase_enable) {
+ status |= VL53L0X_update_byte(dev, 0xEE, 0x80, phase_cal);
+ }
+ }
+
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x01);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
+
+ *p_phase_cal = (uint8_t)(phase_calint & 0xEF);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_perform_vhv_calibration(VL53L0X_DEV dev,
+ uint8_t *p_vhv_settings, const uint8_t get_data_enable,
+ const uint8_t restore_config)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t sequence_config = 0;
+ uint8_t vhv_settings = 0;
+ uint8_t phase_cal = 0;
+ uint8_t phase_cal_int = 0;
+
+ /* store the value of the sequence config,
+ * this will be reset before the end of the function
+ */
+
+ if (restore_config) {
+ sequence_config = PALDevDataGet(dev, SequenceConfig);
+ }
+
+ /* Run VHV */
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0x01);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_perform_single_ref_calibration(dev, 0x40);
+ }
+
+ /* Read VHV from device */
+ if ((status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
+ status = VL53L0X_ref_calibration_io(dev, 1,
+ vhv_settings, phase_cal, /* Not used here */
+ p_vhv_settings, &phase_cal_int,
+ 1, 0);
+ } else {
+ *p_vhv_settings = 0;
+ }
+
+
+ if ((status == VL53L0X_ERROR_NONE) && restore_config) {
+ /* restore the previous Sequence Config */
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+ sequence_config);
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, SequenceConfig, sequence_config);
+ }
+
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_perform_phase_calibration(VL53L0X_DEV dev,
+ uint8_t *p_phase_cal, const uint8_t get_data_enable,
+ const uint8_t restore_config)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t sequence_config = 0;
+ uint8_t vhv_settings = 0;
+ uint8_t phase_cal = 0;
+ uint8_t vhv_settingsint;
+
+ /* store the value of the sequence config,
+ * this will be reset before the end of the function
+ */
+
+ if (restore_config) {
+ sequence_config = PALDevDataGet(dev, SequenceConfig);
+ }
+
+ /* Run PhaseCal */
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0x02);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_perform_single_ref_calibration(dev, 0x0);
+ }
+
+ /* Read PhaseCal from device */
+ if ((status == VL53L0X_ERROR_NONE) && (get_data_enable == 1)) {
+ status = VL53L0X_ref_calibration_io(dev, 1,
+ vhv_settings, phase_cal, /* Not used here */
+ &vhv_settingsint, p_phase_cal,
+ 0, 1);
+ } else {
+ *p_phase_cal = 0;
+ }
+
+
+ if ((status == VL53L0X_ERROR_NONE) && restore_config) {
+ /* restore the previous Sequence Config */
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+ sequence_config);
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, SequenceConfig, sequence_config);
+ }
+
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_perform_ref_calibration(VL53L0X_DEV dev,
+ uint8_t *p_vhv_settings, uint8_t *p_phase_cal, uint8_t get_data_enable)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t sequence_config = 0;
+
+ /* store the value of the sequence config,
+ * this will be reset before the end of the function
+ */
+
+ sequence_config = PALDevDataGet(dev, SequenceConfig);
+
+ /* In the following function we don't save the config to optimize
+ * writes on device. Config is saved and restored only once. */
+ status = VL53L0X_perform_vhv_calibration(
+ dev, p_vhv_settings, get_data_enable, 0);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_perform_phase_calibration(
+ dev, p_phase_cal, get_data_enable, 0);
+ }
+
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* restore the previous Sequence Config */
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+ sequence_config);
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, SequenceConfig, sequence_config);
+ }
+
+ }
+
+ return status;
+}
+
+void VL53L0X::get_next_good_spad(uint8_t good_spad_array[], uint32_t size,
+ uint32_t curr, int32_t *p_next)
+{
+ uint32_t start_index;
+ uint32_t fine_offset;
+ uint32_t c_spads_per_byte = 8;
+ uint32_t coarse_index;
+ uint32_t fine_index;
+ uint8_t data_byte;
+ uint8_t success = 0;
+
+ /*
+ * Starting with the current good spad, loop through the array to find
+ * the next. i.e. the next bit set in the sequence.
+ *
+ * The coarse index is the byte index of the array and the fine index is
+ * the index of the bit within each byte.
+ */
+
+ *p_next = -1;
+
+ start_index = curr / c_spads_per_byte;
+ fine_offset = curr % c_spads_per_byte;
+
+ for (coarse_index = start_index; ((coarse_index < size) && !success);
+ coarse_index++) {
+ fine_index = 0;
+ data_byte = good_spad_array[coarse_index];
+
+ if (coarse_index == start_index) {
+ /* locate the bit position of the provided current
+ * spad bit before iterating */
+ data_byte >>= fine_offset;
+ fine_index = fine_offset;
+ }
+
+ while (fine_index < c_spads_per_byte) {
+ if ((data_byte & 0x1) == 1) {
+ success = 1;
+ *p_next = coarse_index * c_spads_per_byte + fine_index;
+ break;
+ }
+ data_byte >>= 1;
+ fine_index++;
+ }
+ }
+}
+
+uint8_t VL53L0X::is_aperture(uint32_t spad_index)
+{
+ /*
+ * This function reports if a given spad index is an aperture SPAD by
+ * deriving the quadrant.
+ */
+ uint32_t quadrant;
+ uint8_t is_aperture = 1;
+ quadrant = spad_index >> 6;
+ if (refArrayQuadrants[quadrant] == REF_ARRAY_SPAD_0) {
+ is_aperture = 0;
+ }
+
+ return is_aperture;
+}
+
+VL53L0X_Error VL53L0X::enable_spad_bit(uint8_t spad_array[], uint32_t size,
+ uint32_t spad_index)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint32_t c_spads_per_byte = 8;
+ uint32_t coarse_index;
+ uint32_t fine_index;
+
+ coarse_index = spad_index / c_spads_per_byte;
+ fine_index = spad_index % c_spads_per_byte;
+ if (coarse_index >= size) {
+ status = VL53L0X_ERROR_REF_SPAD_INIT;
+ } else {
+ spad_array[coarse_index] |= (1 << fine_index);
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::set_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array)
+{
+ VL53L0X_Error status = VL53L0X_write_multi(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
+ p_ref_spad_array, 6);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::get_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array)
+{
+ VL53L0X_Error status = VL53L0X_read_multi(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0,
+ p_ref_spad_array,
+ 6);
+// VL53L0X_Error status = VL53L0X_ERROR_NONE;
+// uint8_t count=0;
+
+// for (count = 0; count < 6; count++)
+// status = VL53L0X_RdByte(Dev, (VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 + count), &refSpadArray[count]);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::enable_ref_spads(VL53L0X_DEV dev,
+ uint8_t aperture_spads,
+ uint8_t good_spad_array[],
+ uint8_t spad_array[],
+ uint32_t size,
+ uint32_t start,
+ uint32_t offset,
+ uint32_t spad_count,
+ uint32_t *p_last_spad)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint32_t index;
+ uint32_t i;
+ int32_t next_good_spad = offset;
+ uint32_t current_spad;
+ uint8_t check_spad_array[6];
+
+ /*
+ * This function takes in a spad array which may or may not have SPADS
+ * already enabled and appends from a given offset a requested number
+ * of new SPAD enables. The 'good spad map' is applied to
+ * determine the next SPADs to enable.
+ *
+ * This function applies to only aperture or only non-aperture spads.
+ * Checks are performed to ensure this.
+ */
+
+ current_spad = offset;
+ for (index = 0; index < spad_count; index++) {
+ get_next_good_spad(good_spad_array, size, current_spad,
+ &next_good_spad);
+
+ if (next_good_spad == -1) {
+ status = VL53L0X_ERROR_REF_SPAD_INIT;
+ break;
+ }
+
+ /* Confirm that the next good SPAD is non-aperture */
+ if (is_aperture(start + next_good_spad) != aperture_spads) {
+ /* if we can't get the required number of good aperture
+ * spads from the current quadrant then this is an error
+ */
+ status = VL53L0X_ERROR_REF_SPAD_INIT;
+ break;
+ }
+ current_spad = (uint32_t)next_good_spad;
+ enable_spad_bit(spad_array, size, current_spad);
+ current_spad++;
+ }
+ *p_last_spad = current_spad;
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = set_ref_spad_map(dev, spad_array);
+ }
+
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = get_ref_spad_map(dev, check_spad_array);
+
+ i = 0;
+
+ /* Compare spad maps. If not equal report error. */
+ while (i < size) {
+ if (spad_array[i] != check_spad_array[i]) {
+ status = VL53L0X_ERROR_REF_SPAD_INIT;
+ break;
+ }
+ i++;
+ }
+ }
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_device_mode(VL53L0X_DEV dev, VL53L0X_DeviceModes device_mode)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+
+ LOG_FUNCTION_START("%d", (int)DeviceMode);
+
+ switch (device_mode) {
+ case VL53L0X_DEVICEMODE_SINGLE_RANGING:
+ case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
+ case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
+ case VL53L0X_DEVICEMODE_GPIO_DRIVE:
+ case VL53L0X_DEVICEMODE_GPIO_OSC:
+ /* Supported modes */
+ VL53L0X_SETPARAMETERFIELD(dev, DeviceMode, device_mode);
+ break;
+ default:
+ /* Unsupported mode */
+ status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_interrupt_thresholds(VL53L0X_DEV dev,
+ VL53L0X_DeviceModes device_mode, FixPoint1616_t threshold_low,
+ FixPoint1616_t threshold_high)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint16_t threshold16;
+ LOG_FUNCTION_START("");
+
+ /* no dependency on DeviceMode for Ewok */
+ /* Need to divide by 2 because the FW will apply a x2 */
+ threshold16 = (uint16_t)((threshold_low >> 17) & 0x00fff);
+ status = VL53L0X_write_word(dev, VL53L0X_REG_SYSTEM_THRESH_LOW, threshold16);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Need to divide by 2 because the FW will apply a x2 */
+ threshold16 = (uint16_t)((threshold_high >> 17) & 0x00fff);
+ status = VL53L0X_write_word(dev, VL53L0X_REG_SYSTEM_THRESH_HIGH,
+ threshold16);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_interrupt_thresholds(VL53L0X_DEV dev,
+ VL53L0X_DeviceModes device_mode, FixPoint1616_t *p_threshold_low,
+ FixPoint1616_t *p_threshold_high)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint16_t threshold16;
+ LOG_FUNCTION_START("");
+
+ /* no dependency on DeviceMode for Ewok */
+
+ status = VL53L0X_read_word(dev, VL53L0X_REG_SYSTEM_THRESH_LOW, &threshold16);
+ /* Need to multiply by 2 because the FW will apply a x2 */
+ *p_threshold_low = (FixPoint1616_t)((0x00fff & threshold16) << 17);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_word(dev, VL53L0X_REG_SYSTEM_THRESH_HIGH,
+ &threshold16);
+ /* Need to multiply by 2 because the FW will apply a x2 */
+ *p_threshold_high =
+ (FixPoint1616_t)((0x00fff & threshold16) << 17);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_load_tuning_settings(VL53L0X_DEV dev,
+ uint8_t *p_tuning_setting_buffer)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ int i;
+ int index;
+ uint8_t msb;
+ uint8_t lsb;
+ uint8_t select_param;
+ uint8_t number_of_writes;
+ uint8_t address;
+ uint8_t local_buffer[4]; /* max */
+ uint16_t temp16;
+
+ LOG_FUNCTION_START("");
+
+ index = 0;
+
+ while ((*(p_tuning_setting_buffer + index) != 0) &&
+ (status == VL53L0X_ERROR_NONE)) {
+ number_of_writes = *(p_tuning_setting_buffer + index);
+ index++;
+ if (number_of_writes == 0xFF) {
+ /* internal parameters */
+ select_param = *(p_tuning_setting_buffer + index);
+ index++;
+ switch (select_param) {
+ case 0: /* uint16_t SigmaEstRefArray -> 2 bytes */
+ msb = *(p_tuning_setting_buffer + index);
+ index++;
+ lsb = *(p_tuning_setting_buffer + index);
+ index++;
+ temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+ PALDevDataSet(dev, SigmaEstRefArray, temp16);
+ break;
+ case 1: /* uint16_t SigmaEstEffPulseWidth -> 2 bytes */
+ msb = *(p_tuning_setting_buffer + index);
+ index++;
+ lsb = *(p_tuning_setting_buffer + index);
+ index++;
+ temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+ PALDevDataSet(dev, SigmaEstEffPulseWidth,
+ temp16);
+ break;
+ case 2: /* uint16_t SigmaEstEffAmbWidth -> 2 bytes */
+ msb = *(p_tuning_setting_buffer + index);
+ index++;
+ lsb = *(p_tuning_setting_buffer + index);
+ index++;
+ temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+ PALDevDataSet(dev, SigmaEstEffAmbWidth, temp16);
+ break;
+ case 3: /* uint16_t targetRefRate -> 2 bytes */
+ msb = *(p_tuning_setting_buffer + index);
+ index++;
+ lsb = *(p_tuning_setting_buffer + index);
+ index++;
+ temp16 = VL53L0X_MAKEUINT16(lsb, msb);
+ PALDevDataSet(dev, targetRefRate, temp16);
+ break;
+ default: /* invalid parameter */
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+
+ } else if (number_of_writes <= 4) {
+ address = *(p_tuning_setting_buffer + index);
+ index++;
+
+ for (i = 0; i < number_of_writes; i++) {
+ local_buffer[i] = *(p_tuning_setting_buffer +
+ index);
+ index++;
+ }
+
+ status = VL53L0X_write_multi(dev, address, local_buffer,
+ number_of_writes);
+
+ } else {
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_check_and_load_interrupt_settings(VL53L0X_DEV dev,
+ uint8_t start_not_stopflag)
+{
+ uint8_t interrupt_config;
+ FixPoint1616_t threshold_low;
+ FixPoint1616_t threshold_high;
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+
+ interrupt_config = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
+ Pin0GpioFunctionality);
+
+ if ((interrupt_config ==
+ VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW) ||
+ (interrupt_config ==
+ VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH) ||
+ (interrupt_config ==
+ VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT)) {
+
+ status = VL53L0X_get_interrupt_thresholds(dev,
+ VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
+ &threshold_low, &threshold_high);
+
+ if (((threshold_low > 255 * 65536) ||
+ (threshold_high > 255 * 65536)) &&
+ (status == VL53L0X_ERROR_NONE)) {
+
+ if (start_not_stopflag != 0) {
+ status = VL53L0X_load_tuning_settings(dev,
+ InterruptThresholdSettings);
+ } else {
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x04);
+ status |= VL53L0X_write_byte(dev, 0x70, 0x00);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
+ status |= VL53L0X_write_byte(dev, 0x80, 0x00);
+ }
+
+ }
+
+
+ }
+
+ return status;
+
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_start_measurement(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ VL53L0X_DeviceModes device_mode;
+ uint8_t byte;
+ uint8_t start_stop_byte = VL53L0X_REG_SYSRANGE_MODE_START_STOP;
+ uint32_t loop_nb;
+ LOG_FUNCTION_START("");
+
+ /* Get Current DeviceMode */
+ VL53L0X_get_device_mode(dev, &device_mode);
+
+ status = VL53L0X_write_byte(dev, 0x80, 0x01);
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status = VL53L0X_write_byte(dev, 0x00, 0x00);
+ status = VL53L0X_write_byte(dev, 0x91, PALDevDataGet(dev, StopVariable));
+ status = VL53L0X_write_byte(dev, 0x00, 0x01);
+ status = VL53L0X_write_byte(dev, 0xFF, 0x00);
+ status = VL53L0X_write_byte(dev, 0x80, 0x00);
+
+ switch (device_mode) {
+ case VL53L0X_DEVICEMODE_SINGLE_RANGING:
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START, 0x01);
+
+ byte = start_stop_byte;
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Wait until start bit has been cleared */
+ loop_nb = 0;
+ do {
+ if (loop_nb > 0)
+ status = VL53L0X_read_byte(dev,
+ VL53L0X_REG_SYSRANGE_START, &byte);
+ loop_nb = loop_nb + 1;
+ } while (((byte & start_stop_byte) == start_stop_byte)
+ && (status == VL53L0X_ERROR_NONE)
+ && (loop_nb < VL53L0X_DEFAULT_MAX_LOOP));
+
+ if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
+ status = VL53L0X_ERROR_TIME_OUT;
+ }
+
+ }
+
+ break;
+ case VL53L0X_DEVICEMODE_CONTINUOUS_RANGING:
+ /* Back-to-back mode */
+
+ /* Check if need to apply interrupt settings */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_check_and_load_interrupt_settings(dev, 1);
+ }
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_SYSRANGE_START,
+ VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK);
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Set PAL State to Running */
+ PALDevDataSet(dev, PalState, VL53L0X_STATE_RUNNING);
+ }
+ break;
+ case VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING:
+ /* Continuous mode */
+ /* Check if need to apply interrupt settings */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_check_and_load_interrupt_settings(dev, 1);
+ }
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_SYSRANGE_START,
+ VL53L0X_REG_SYSRANGE_MODE_TIMED);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Set PAL State to Running */
+ PALDevDataSet(dev, PalState, VL53L0X_STATE_RUNNING);
+ }
+ break;
+ default:
+ /* Selected mode not supported */
+ status = VL53L0X_ERROR_MODE_NOT_SUPPORTED;
+ }
+
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+/* Group PAL Measurement Functions */
+VL53L0X_Error VL53L0X::VL53L0X_perform_single_measurement(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ VL53L0X_DeviceModes device_mode;
+
+ LOG_FUNCTION_START("");
+
+ /* Get Current DeviceMode */
+ status = VL53L0X_get_device_mode(dev, &device_mode);
+
+ /* Start immediately to run a single ranging measurement in case of
+ * single ranging or single histogram */
+ if (status == VL53L0X_ERROR_NONE
+ && device_mode == VL53L0X_DEVICEMODE_SINGLE_RANGING) {
+ status = VL53L0X_start_measurement(dev);
+ }
+
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_measurement_poll_for_completion(dev);
+ }
+
+
+ /* Change PAL State in case of single ranging or single histogram */
+ if (status == VL53L0X_ERROR_NONE
+ && device_mode == VL53L0X_DEVICEMODE_SINGLE_RANGING) {
+ PALDevDataSet(dev, PalState, VL53L0X_STATE_IDLE);
+ }
+
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_x_talk_compensation_enable(VL53L0X_DEV dev,
+ uint8_t *p_x_talk_compensation_enable)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t temp8;
+ LOG_FUNCTION_START("");
+
+ VL53L0X_GETPARAMETERFIELD(dev, XTalkCompensationEnable, temp8);
+ *p_x_talk_compensation_enable = temp8;
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_total_xtalk_rate(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ FixPoint1616_t *p_total_xtalk_rate_mcps)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+
+ uint8_t xtalk_comp_enable;
+ FixPoint1616_t total_xtalk_mega_cps;
+ FixPoint1616_t xtalk_per_spad_mega_cps;
+
+ *p_total_xtalk_rate_mcps = 0;
+
+ status = VL53L0X_get_x_talk_compensation_enable(dev, &xtalk_comp_enable);
+ if (status == VL53L0X_ERROR_NONE) {
+
+ if (xtalk_comp_enable) {
+
+ VL53L0X_GETPARAMETERFIELD(
+ dev,
+ XTalkCompensationRateMegaCps,
+ xtalk_per_spad_mega_cps);
+
+ /* FixPoint1616 * FixPoint 8:8 = FixPoint0824 */
+ total_xtalk_mega_cps =
+ p_ranging_measurement_data->EffectiveSpadRtnCount *
+ xtalk_per_spad_mega_cps;
+
+ /* FixPoint0824 >> 8 = FixPoint1616 */
+ *p_total_xtalk_rate_mcps =
+ (total_xtalk_mega_cps + 0x80) >> 8;
+ }
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_total_signal_rate(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ FixPoint1616_t *p_total_signal_rate_mcps)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ FixPoint1616_t total_xtalk_mega_cps;
+
+ LOG_FUNCTION_START("");
+
+ *p_total_signal_rate_mcps =
+ p_ranging_measurement_data->SignalRateRtnMegaCps;
+
+ status = VL53L0X_get_total_xtalk_rate(
+ dev, p_ranging_measurement_data, &total_xtalk_mega_cps);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ *p_total_signal_rate_mcps += total_xtalk_mega_cps;
+ }
+
+ return status;
+}
+
+/* To convert ms into register value */
+uint32_t VL53L0X::VL53L0X_calc_timeout_mclks(VL53L0X_DEV dev,
+ uint32_t timeout_period_us,
+ uint8_t vcsel_period_pclks)
+{
+ uint32_t macro_period_ps;
+ uint32_t macro_period_ns;
+ uint32_t timeout_period_mclks = 0;
+
+ macro_period_ps = VL53L0X_calc_macro_period_ps(dev, vcsel_period_pclks);
+ macro_period_ns = (macro_period_ps + 500) / 1000;
+
+ timeout_period_mclks =
+ (uint32_t)(((timeout_period_us * 1000)
+ + (macro_period_ns / 2)) / macro_period_ns);
+
+ return timeout_period_mclks;
+}
+
+uint32_t VL53L0X::VL53L0X_isqrt(uint32_t num)
+{
+ /*
+ * Implements an integer square root
+ *
+ * From: http://en.wikipedia.org/wiki/Methods_of_computing_square_roots
+ */
+
+ uint32_t res = 0;
+ uint32_t bit = 1 << 30;
+ /* The second-to-top bit is set:
+ * 1 << 14 for 16-bits, 1 << 30 for 32 bits */
+
+ /* "bit" starts at the highest power of four <= the argument. */
+ while (bit > num) {
+ bit >>= 2;
+ }
+
+
+ while (bit != 0) {
+ if (num >= res + bit) {
+ num -= res + bit;
+ res = (res >> 1) + bit;
+ } else {
+ res >>= 1;
+ }
+
+ bit >>= 2;
+ }
+
+ return res;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_calc_dmax(
+ VL53L0X_DEV dev,
+ FixPoint1616_t total_signal_rate_mcps,
+ FixPoint1616_t total_corr_signal_rate_mcps,
+ FixPoint1616_t pw_mult,
+ uint32_t sigma_estimate_p1,
+ FixPoint1616_t sigma_estimate_p2,
+ uint32_t peak_vcsel_duration_us,
+ uint32_t *pd_max_mm)
+{
+ const uint32_t c_sigma_limit = 18;
+ const FixPoint1616_t c_signal_limit = 0x4000; /* 0.25 */
+ const FixPoint1616_t c_sigma_est_ref = 0x00000042; /* 0.001 */
+ const uint32_t c_amb_eff_width_sigma_est_ns = 6;
+ const uint32_t c_amb_eff_width_d_max_ns = 7;
+ uint32_t dmax_cal_range_mm;
+ FixPoint1616_t dmax_cal_signal_rate_rtn_mcps;
+ FixPoint1616_t min_signal_needed;
+ FixPoint1616_t min_signal_needed_p1;
+ FixPoint1616_t min_signal_needed_p2;
+ FixPoint1616_t min_signal_needed_p3;
+ FixPoint1616_t min_signal_needed_p4;
+ FixPoint1616_t sigma_limit_tmp;
+ FixPoint1616_t sigma_est_sq_tmp;
+ FixPoint1616_t signal_limit_tmp;
+ FixPoint1616_t signal_at0_mm;
+ FixPoint1616_t dmax_dark;
+ FixPoint1616_t dmax_ambient;
+ FixPoint1616_t dmax_dark_tmp;
+ FixPoint1616_t sigma_est_p2_tmp;
+ uint32_t signal_rate_temp_mcps;
+
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+
+ LOG_FUNCTION_START("");
+
+ dmax_cal_range_mm =
+ PALDevDataGet(dev, DmaxCalRangeMilliMeter);
+
+ dmax_cal_signal_rate_rtn_mcps =
+ PALDevDataGet(dev, DmaxCalSignalRateRtnMegaCps);
+
+ /* uint32 * FixPoint1616 = FixPoint1616 */
+ signal_at0_mm = dmax_cal_range_mm * dmax_cal_signal_rate_rtn_mcps;
+
+ /* FixPoint1616 >> 8 = FixPoint2408 */
+ signal_at0_mm = (signal_at0_mm + 0x80) >> 8;
+ signal_at0_mm *= dmax_cal_range_mm;
+
+ min_signal_needed_p1 = 0;
+ if (total_corr_signal_rate_mcps > 0) {
+
+ /* Shift by 10 bits to increase resolution prior to the
+ * division */
+ signal_rate_temp_mcps = total_signal_rate_mcps << 10;
+
+ /* Add rounding value prior to division */
+ min_signal_needed_p1 = signal_rate_temp_mcps +
+ (total_corr_signal_rate_mcps / 2);
+
+ /* FixPoint0626/FixPoint1616 = FixPoint2210 */
+ min_signal_needed_p1 /= total_corr_signal_rate_mcps;
+
+ /* Apply a factored version of the speed of light.
+ Correction to be applied at the end */
+ min_signal_needed_p1 *= 3;
+
+ /* FixPoint2210 * FixPoint2210 = FixPoint1220 */
+ min_signal_needed_p1 *= min_signal_needed_p1;
+
+ /* FixPoint1220 >> 16 = FixPoint2804 */
+ min_signal_needed_p1 = (min_signal_needed_p1 + 0x8000) >> 16;
+ }
+
+ min_signal_needed_p2 = pw_mult * sigma_estimate_p1;
+
+ /* FixPoint1616 >> 16 = uint32 */
+ min_signal_needed_p2 = (min_signal_needed_p2 + 0x8000) >> 16;
+
+ /* uint32 * uint32 = uint32 */
+ min_signal_needed_p2 *= min_signal_needed_p2;
+
+ /* Check sigmaEstimateP2
+ * If this value is too high there is not enough signal rate
+ * to calculate dmax value so set a suitable value to ensure
+ * a very small dmax.
+ */
+ sigma_est_p2_tmp = (sigma_estimate_p2 + 0x8000) >> 16;
+ sigma_est_p2_tmp = (sigma_est_p2_tmp + c_amb_eff_width_sigma_est_ns / 2) /
+ c_amb_eff_width_sigma_est_ns;
+ sigma_est_p2_tmp *= c_amb_eff_width_d_max_ns;
+
+ if (sigma_est_p2_tmp > 0xffff) {
+ min_signal_needed_p3 = 0xfff00000;
+ } else {
+
+ /* DMAX uses a different ambient width from sigma, so apply
+ * correction.
+ * Perform division before multiplication to prevent overflow.
+ */
+ sigma_estimate_p2 = (sigma_estimate_p2 + c_amb_eff_width_sigma_est_ns / 2) /
+ c_amb_eff_width_sigma_est_ns;
+ sigma_estimate_p2 *= c_amb_eff_width_d_max_ns;
+
+ /* FixPoint1616 >> 16 = uint32 */
+ min_signal_needed_p3 = (sigma_estimate_p2 + 0x8000) >> 16;
+
+ min_signal_needed_p3 *= min_signal_needed_p3;
+
+ }
+
+ /* FixPoint1814 / uint32 = FixPoint1814 */
+ sigma_limit_tmp = ((c_sigma_limit << 14) + 500) / 1000;
+
+ /* FixPoint1814 * FixPoint1814 = FixPoint3628 := FixPoint0428 */
+ sigma_limit_tmp *= sigma_limit_tmp;
+
+ /* FixPoint1616 * FixPoint1616 = FixPoint3232 */
+ sigma_est_sq_tmp = c_sigma_est_ref * c_sigma_est_ref;
+
+ /* FixPoint3232 >> 4 = FixPoint0428 */
+ sigma_est_sq_tmp = (sigma_est_sq_tmp + 0x08) >> 4;
+
+ /* FixPoint0428 - FixPoint0428 = FixPoint0428 */
+ sigma_limit_tmp -= sigma_est_sq_tmp;
+
+ /* uint32_t * FixPoint0428 = FixPoint0428 */
+ min_signal_needed_p4 = 4 * 12 * sigma_limit_tmp;
+
+ /* FixPoint0428 >> 14 = FixPoint1814 */
+ min_signal_needed_p4 = (min_signal_needed_p4 + 0x2000) >> 14;
+
+ /* uint32 + uint32 = uint32 */
+ min_signal_needed = (min_signal_needed_p2 + min_signal_needed_p3);
+
+ /* uint32 / uint32 = uint32 */
+ min_signal_needed += (peak_vcsel_duration_us / 2);
+ min_signal_needed /= peak_vcsel_duration_us;
+
+ /* uint32 << 14 = FixPoint1814 */
+ min_signal_needed <<= 14;
+
+ /* FixPoint1814 / FixPoint1814 = uint32 */
+ min_signal_needed += (min_signal_needed_p4 / 2);
+ min_signal_needed /= min_signal_needed_p4;
+
+ /* FixPoint3200 * FixPoint2804 := FixPoint2804*/
+ min_signal_needed *= min_signal_needed_p1;
+
+ /* Apply correction by dividing by 1000000.
+ * This assumes 10E16 on the numerator of the equation
+ * and 10E-22 on the denominator.
+ * We do this because 32bit fix point calculation can't
+ * handle the larger and smaller elements of this equation,
+ * i.e. speed of light and pulse widths.
+ */
+ min_signal_needed = (min_signal_needed + 500) / 1000;
+ min_signal_needed <<= 4;
+
+ min_signal_needed = (min_signal_needed + 500) / 1000;
+
+ /* FixPoint1616 >> 8 = FixPoint2408 */
+ signal_limit_tmp = (c_signal_limit + 0x80) >> 8;
+
+ /* FixPoint2408/FixPoint2408 = uint32 */
+ if (signal_limit_tmp != 0) {
+ dmax_dark_tmp = (signal_at0_mm + (signal_limit_tmp / 2))
+ / signal_limit_tmp;
+ } else {
+ dmax_dark_tmp = 0;
+ }
+
+ dmax_dark = VL53L0X_isqrt(dmax_dark_tmp);
+
+ /* FixPoint2408/FixPoint2408 = uint32 */
+ if (min_signal_needed != 0) {
+ dmax_ambient = (signal_at0_mm + min_signal_needed / 2)
+ / min_signal_needed;
+ } else {
+ dmax_ambient = 0;
+ }
+
+ dmax_ambient = VL53L0X_isqrt(dmax_ambient);
+
+ *pd_max_mm = dmax_dark;
+ if (dmax_dark > dmax_ambient) {
+ *pd_max_mm = dmax_ambient;
+ }
+
+ LOG_FUNCTION_END(status);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_calc_sigma_estimate(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ FixPoint1616_t *p_sigma_estimate,
+ uint32_t *p_dmax_mm)
+{
+ /* Expressed in 100ths of a ns, i.e. centi-ns */
+ const uint32_t c_pulse_effective_width_centi_ns = 800;
+ /* Expressed in 100ths of a ns, i.e. centi-ns */
+ const uint32_t c_ambient_effective_width_centi_ns = 600;
+ const FixPoint1616_t c_dflt_final_range_integration_time_milli_secs = 0x00190000; /* 25ms */
+ const uint32_t c_vcsel_pulse_width_ps = 4700; /* pico secs */
+ const FixPoint1616_t c_sigma_est_max = 0x028F87AE;
+ const FixPoint1616_t c_sigma_est_rtn_max = 0xF000;
+ const FixPoint1616_t c_amb_to_signal_ratio_max = 0xF0000000 /
+ c_ambient_effective_width_centi_ns;
+ /* Time Of Flight per mm (6.6 pico secs) */
+ const FixPoint1616_t c_tof_per_mm_ps = 0x0006999A;
+ const uint32_t c_16bit_rounding_param = 0x00008000;
+ const FixPoint1616_t c_max_x_talk_kcps = 0x00320000;
+ const uint32_t c_pll_period_ps = 1655;
+
+ uint32_t vcsel_total_events_rtn;
+ uint32_t final_range_timeout_micro_secs;
+ uint32_t pre_range_timeout_micro_secs;
+ uint32_t final_range_integration_time_milli_secs;
+ FixPoint1616_t sigma_estimate_p1;
+ FixPoint1616_t sigma_estimate_p2;
+ FixPoint1616_t sigma_estimate_p3;
+ FixPoint1616_t delta_t_ps;
+ FixPoint1616_t pw_mult;
+ FixPoint1616_t sigma_est_rtn;
+ FixPoint1616_t sigma_estimate;
+ FixPoint1616_t x_talk_correction;
+ FixPoint1616_t ambient_rate_kcps;
+ FixPoint1616_t peak_signal_rate_kcps;
+ FixPoint1616_t x_talk_comp_rate_mcps;
+ uint32_t x_talk_comp_rate_kcps;
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ FixPoint1616_t diff1_mcps;
+ FixPoint1616_t diff2_mcps;
+ FixPoint1616_t sqr1;
+ FixPoint1616_t sqr2;
+ FixPoint1616_t sqr_sum;
+ FixPoint1616_t sqrt_result_centi_ns;
+ FixPoint1616_t sqrt_result;
+ FixPoint1616_t total_signal_rate_mcps;
+ FixPoint1616_t corrected_signal_rate_mcps;
+ FixPoint1616_t sigma_est_ref;
+ uint32_t vcsel_width;
+ uint32_t final_range_macro_pclks;
+ uint32_t pre_range_macro_pclks;
+ uint32_t peak_vcsel_duration_us;
+ uint8_t final_range_vcsel_pclks;
+ uint8_t pre_range_vcsel_pclks;
+ /*! \addtogroup calc_sigma_estimate
+ * @{
+ *
+ * Estimates the range sigma
+ */
+
+ LOG_FUNCTION_START("");
+
+ VL53L0X_GETPARAMETERFIELD(dev, XTalkCompensationRateMegaCps,
+ x_talk_comp_rate_mcps);
+
+ /*
+ * We work in kcps rather than mcps as this helps keep within the
+ * confines of the 32 Fix1616 type.
+ */
+
+ ambient_rate_kcps =
+ (p_ranging_measurement_data->AmbientRateRtnMegaCps * 1000) >> 16;
+
+ corrected_signal_rate_mcps =
+ p_ranging_measurement_data->SignalRateRtnMegaCps;
+
+
+ status = VL53L0X_get_total_signal_rate(
+ dev, p_ranging_measurement_data, &total_signal_rate_mcps);
+ status = VL53L0X_get_total_xtalk_rate(
+ dev, p_ranging_measurement_data, &x_talk_comp_rate_mcps);
+
+
+ /* Signal rate measurement provided by device is the
+ * peak signal rate, not average.
+ */
+ peak_signal_rate_kcps = (total_signal_rate_mcps * 1000);
+ peak_signal_rate_kcps = (peak_signal_rate_kcps + 0x8000) >> 16;
+
+ x_talk_comp_rate_kcps = x_talk_comp_rate_mcps * 1000;
+
+ if (x_talk_comp_rate_kcps > c_max_x_talk_kcps) {
+ x_talk_comp_rate_kcps = c_max_x_talk_kcps;
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+
+ /* Calculate final range macro periods */
+ final_range_timeout_micro_secs = VL53L0X_GETDEVICESPECIFICPARAMETER(
+ dev, FinalRangeTimeoutMicroSecs);
+
+ final_range_vcsel_pclks = VL53L0X_GETDEVICESPECIFICPARAMETER(
+ dev, FinalRangeVcselPulsePeriod);
+
+ final_range_macro_pclks = VL53L0X_calc_timeout_mclks(
+ dev, final_range_timeout_micro_secs, final_range_vcsel_pclks);
+
+ /* Calculate pre-range macro periods */
+ pre_range_timeout_micro_secs = VL53L0X_GETDEVICESPECIFICPARAMETER(
+ dev, PreRangeTimeoutMicroSecs);
+
+ pre_range_vcsel_pclks = VL53L0X_GETDEVICESPECIFICPARAMETER(
+ dev, PreRangeVcselPulsePeriod);
+
+ pre_range_macro_pclks = VL53L0X_calc_timeout_mclks(
+ dev, pre_range_timeout_micro_secs, pre_range_vcsel_pclks);
+
+ vcsel_width = 3;
+ if (final_range_vcsel_pclks == 8) {
+ vcsel_width = 2;
+ }
+
+
+ peak_vcsel_duration_us = vcsel_width * 2048 *
+ (pre_range_macro_pclks + final_range_macro_pclks);
+ peak_vcsel_duration_us = (peak_vcsel_duration_us + 500) / 1000;
+ peak_vcsel_duration_us *= c_pll_period_ps;
+ peak_vcsel_duration_us = (peak_vcsel_duration_us + 500) / 1000;
+
+ /* Fix1616 >> 8 = Fix2408 */
+ total_signal_rate_mcps = (total_signal_rate_mcps + 0x80) >> 8;
+
+ /* Fix2408 * uint32 = Fix2408 */
+ vcsel_total_events_rtn = total_signal_rate_mcps *
+ peak_vcsel_duration_us;
+
+ /* Fix2408 >> 8 = uint32 */
+ vcsel_total_events_rtn = (vcsel_total_events_rtn + 0x80) >> 8;
+
+ /* Fix2408 << 8 = Fix1616 = */
+ total_signal_rate_mcps <<= 8;
+ }
+
+ if (status != VL53L0X_ERROR_NONE) {
+ LOG_FUNCTION_END(status);
+ return status;
+ }
+
+ if (peak_signal_rate_kcps == 0) {
+ *p_sigma_estimate = c_sigma_est_max;
+ PALDevDataSet(dev, SigmaEstimate, c_sigma_est_max);
+ *p_dmax_mm = 0;
+ } else {
+ if (vcsel_total_events_rtn < 1) {
+ vcsel_total_events_rtn = 1;
+ }
+
+ sigma_estimate_p1 = c_pulse_effective_width_centi_ns;
+
+ /* ((FixPoint1616 << 16)* uint32)/uint32 = FixPoint1616 */
+ sigma_estimate_p2 = (ambient_rate_kcps << 16) / peak_signal_rate_kcps;
+ if (sigma_estimate_p2 > c_amb_to_signal_ratio_max) {
+ /* Clip to prevent overflow. Will ensure safe
+ * max result. */
+ sigma_estimate_p2 = c_amb_to_signal_ratio_max;
+ }
+ sigma_estimate_p2 *= c_ambient_effective_width_centi_ns;
+
+ sigma_estimate_p3 = 2 * VL53L0X_isqrt(vcsel_total_events_rtn * 12);
+
+ /* uint32 * FixPoint1616 = FixPoint1616 */
+ delta_t_ps = p_ranging_measurement_data->RangeMilliMeter *
+ c_tof_per_mm_ps;
+
+ /*
+ * vcselRate - xtalkCompRate
+ * (uint32 << 16) - FixPoint1616 = FixPoint1616.
+ * Divide result by 1000 to convert to mcps.
+ * 500 is added to ensure rounding when integer division
+ * truncates.
+ */
+ diff1_mcps = (((peak_signal_rate_kcps << 16) -
+ 2 * x_talk_comp_rate_kcps) + 500) / 1000;
+
+ /* vcselRate + xtalkCompRate */
+ diff2_mcps = ((peak_signal_rate_kcps << 16) + 500) / 1000;
+
+ /* Shift by 8 bits to increase resolution prior to the
+ * division */
+ diff1_mcps <<= 8;
+
+ /* FixPoint0824/FixPoint1616 = FixPoint2408 */
+// xTalkCorrection = abs(diff1_mcps/diff2_mcps);
+// abs is causing compiler overloading isue in C++, but unsigned types. So, redundant call anyway!
+ x_talk_correction = diff1_mcps / diff2_mcps;
+
+ /* FixPoint2408 << 8 = FixPoint1616 */
+ x_talk_correction <<= 8;
+
+ if (p_ranging_measurement_data->RangeStatus != 0) {
+ pw_mult = 1 << 16;
+ } else {
+ /* FixPoint1616/uint32 = FixPoint1616 */
+ pw_mult = delta_t_ps / c_vcsel_pulse_width_ps; /* smaller than 1.0f */
+
+ /*
+ * FixPoint1616 * FixPoint1616 = FixPoint3232, however both
+ * values are small enough such that32 bits will not be
+ * exceeded.
+ */
+ pw_mult *= ((1 << 16) - x_talk_correction);
+
+ /* (FixPoint3232 >> 16) = FixPoint1616 */
+ pw_mult = (pw_mult + c_16bit_rounding_param) >> 16;
+
+ /* FixPoint1616 + FixPoint1616 = FixPoint1616 */
+ pw_mult += (1 << 16);
+
+ /*
+ * At this point the value will be 1.xx, therefore if we square
+ * the value this will exceed 32 bits. To address this perform
+ * a single shift to the right before the multiplication.
+ */
+ pw_mult >>= 1;
+ /* FixPoint1715 * FixPoint1715 = FixPoint3430 */
+ pw_mult = pw_mult * pw_mult;
+
+ /* (FixPoint3430 >> 14) = Fix1616 */
+ pw_mult >>= 14;
+ }
+
+ /* FixPoint1616 * uint32 = FixPoint1616 */
+ sqr1 = pw_mult * sigma_estimate_p1;
+
+ /* (FixPoint1616 >> 16) = FixPoint3200 */
+ sqr1 = (sqr1 + 0x8000) >> 16;
+
+ /* FixPoint3200 * FixPoint3200 = FixPoint6400 */
+ sqr1 *= sqr1;
+
+ sqr2 = sigma_estimate_p2;
+
+ /* (FixPoint1616 >> 16) = FixPoint3200 */
+ sqr2 = (sqr2 + 0x8000) >> 16;
+
+ /* FixPoint3200 * FixPoint3200 = FixPoint6400 */
+ sqr2 *= sqr2;
+
+ /* FixPoint64000 + FixPoint6400 = FixPoint6400 */
+ sqr_sum = sqr1 + sqr2;
+
+ /* SQRT(FixPoin6400) = FixPoint3200 */
+ sqrt_result_centi_ns = VL53L0X_isqrt(sqr_sum);
+
+ /* (FixPoint3200 << 16) = FixPoint1616 */
+ sqrt_result_centi_ns <<= 16;
+
+ /*
+ * Note that the Speed Of Light is expressed in um per 1E-10
+ * seconds (2997) Therefore to get mm/ns we have to divide by
+ * 10000
+ */
+ sigma_est_rtn = (((sqrt_result_centi_ns + 50) / 100) /
+ sigma_estimate_p3);
+ sigma_est_rtn *= VL53L0X_SPEED_OF_LIGHT_IN_AIR;
+
+ /* Add 5000 before dividing by 10000 to ensure rounding. */
+ sigma_est_rtn += 5000;
+ sigma_est_rtn /= 10000;
+
+ if (sigma_est_rtn > c_sigma_est_rtn_max) {
+ /* Clip to prevent overflow. Will ensure safe
+ * max result. */
+ sigma_est_rtn = c_sigma_est_rtn_max;
+ }
+ final_range_integration_time_milli_secs =
+ (final_range_timeout_micro_secs + pre_range_timeout_micro_secs + 500) / 1000;
+
+ /* sigmaEstRef = 1mm * 25ms/final range integration time (inc pre-range)
+ * sqrt(FixPoint1616/int) = FixPoint2408)
+ */
+ sigma_est_ref =
+ VL53L0X_isqrt((c_dflt_final_range_integration_time_milli_secs +
+ final_range_integration_time_milli_secs / 2) /
+ final_range_integration_time_milli_secs);
+
+ /* FixPoint2408 << 8 = FixPoint1616 */
+ sigma_est_ref <<= 8;
+ sigma_est_ref = (sigma_est_ref + 500) / 1000;
+
+ /* FixPoint1616 * FixPoint1616 = FixPoint3232 */
+ sqr1 = sigma_est_rtn * sigma_est_rtn;
+ /* FixPoint1616 * FixPoint1616 = FixPoint3232 */
+ sqr2 = sigma_est_ref * sigma_est_ref;
+
+ /* sqrt(FixPoint3232) = FixPoint1616 */
+ sqrt_result = VL53L0X_isqrt((sqr1 + sqr2));
+ /*
+ * Note that the Shift by 4 bits increases resolution prior to
+ * the sqrt, therefore the result must be shifted by 2 bits to
+ * the right to revert back to the FixPoint1616 format.
+ */
+
+ sigma_estimate = 1000 * sqrt_result;
+
+ if ((peak_signal_rate_kcps < 1) || (vcsel_total_events_rtn < 1) ||
+ (sigma_estimate > c_sigma_est_max)) {
+ sigma_estimate = c_sigma_est_max;
+ }
+
+ *p_sigma_estimate = (uint32_t)(sigma_estimate);
+ PALDevDataSet(dev, SigmaEstimate, *p_sigma_estimate);
+ status = VL53L0X_calc_dmax(
+ dev,
+ total_signal_rate_mcps,
+ corrected_signal_rate_mcps,
+ pw_mult,
+ sigma_estimate_p1,
+ sigma_estimate_p2,
+ peak_vcsel_duration_us,
+ p_dmax_mm);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_pal_range_status(VL53L0X_DEV dev,
+ uint8_t device_range_status,
+ FixPoint1616_t signal_rate,
+ uint16_t effective_spad_rtn_count,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ uint8_t *p_pal_range_status)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t none_flag;
+ uint8_t sigma_limitflag = 0;
+ uint8_t signal_ref_clipflag = 0;
+ uint8_t range_ignore_thresholdflag = 0;
+ uint8_t sigma_limit_check_enable = 0;
+ uint8_t signal_rate_final_range_limit_check_enable = 0;
+ uint8_t signal_ref_clip_limit_check_enable = 0;
+ uint8_t range_ignore_threshold_limit_check_enable = 0;
+ FixPoint1616_t sigma_estimate;
+ FixPoint1616_t sigma_limit_value;
+ FixPoint1616_t signal_ref_clip_value;
+ FixPoint1616_t range_ignore_threshold_value;
+ FixPoint1616_t signal_rate_per_spad;
+ uint8_t device_range_status_internal = 0;
+ uint16_t tmp_word = 0;
+ uint8_t temp8;
+ uint32_t dmax_mm = 0;
+ FixPoint1616_t last_signal_ref_mcps;
+
+ LOG_FUNCTION_START("");
+
+
+ /*
+ * VL53L0X has a good ranging when the value of the
+ * DeviceRangeStatus = 11. This function will replace the value 0 with
+ * the value 11 in the DeviceRangeStatus.
+ * In addition, the SigmaEstimator is not included in the VL53L0X
+ * DeviceRangeStatus, this will be added in the PalRangeStatus.
+ */
+
+ device_range_status_internal = ((device_range_status & 0x78) >> 3);
+
+ if (device_range_status_internal == 0 ||
+ device_range_status_internal == 5 ||
+ device_range_status_internal == 7 ||
+ device_range_status_internal == 12 ||
+ device_range_status_internal == 13 ||
+ device_range_status_internal == 14 ||
+ device_range_status_internal == 15
+ ) {
+ none_flag = 1;
+ } else {
+ none_flag = 0;
+ }
+
+ /*
+ * Check if Sigma limit is enabled, if yes then do comparison with limit
+ * value and put the result back into pPalRangeStatus.
+ */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+ &sigma_limit_check_enable);
+ }
+
+ if ((sigma_limit_check_enable != 0) && (status == VL53L0X_ERROR_NONE)) {
+ /*
+ * compute the Sigma and check with limit
+ */
+ status = VL53L0X_calc_sigma_estimate(
+ dev,
+ p_ranging_measurement_data,
+ &sigma_estimate,
+ &dmax_mm);
+ if (status == VL53L0X_ERROR_NONE) {
+ p_ranging_measurement_data->RangeDMaxMilliMeter = dmax_mm;
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_limit_check_value(dev,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+ &sigma_limit_value);
+
+ if ((sigma_limit_value > 0) &&
+ (sigma_estimate > sigma_limit_value)) {
+ /* Limit Fail */
+ sigma_limitflag = 1;
+ }
+ }
+ }
+
+ /*
+ * Check if Signal ref clip limit is enabled, if yes then do comparison
+ * with limit value and put the result back into pPalRangeStatus.
+ */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+ &signal_ref_clip_limit_check_enable);
+ }
+
+ if ((signal_ref_clip_limit_check_enable != 0) &&
+ (status == VL53L0X_ERROR_NONE)) {
+
+ status = VL53L0X_get_limit_check_value(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+ &signal_ref_clip_value);
+
+ /* Read LastSignalRefMcps from device */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
+ &tmp_word);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x00);
+ }
+
+ last_signal_ref_mcps = VL53L0X_FIXPOINT97TOFIXPOINT1616(tmp_word);
+ PALDevDataSet(dev, LastSignalRefMcps, last_signal_ref_mcps);
+
+ if ((signal_ref_clip_value > 0) &&
+ (last_signal_ref_mcps > signal_ref_clip_value)) {
+ /* Limit Fail */
+ signal_ref_clipflag = 1;
+ }
+ }
+
+ /*
+ * Check if Signal ref clip limit is enabled, if yes then do comparison
+ * with limit value and put the result back into pPalRangeStatus.
+ * EffectiveSpadRtnCount has a format 8.8
+ * If (Return signal rate < (1.5 x Xtalk x number of Spads)) : FAIL
+ */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+ &range_ignore_threshold_limit_check_enable);
+ }
+
+ if ((range_ignore_threshold_limit_check_enable != 0) &&
+ (status == VL53L0X_ERROR_NONE)) {
+
+ /* Compute the signal rate per spad */
+ if (effective_spad_rtn_count == 0) {
+ signal_rate_per_spad = 0;
+ } else {
+ signal_rate_per_spad = (FixPoint1616_t)((256 * signal_rate)
+ / effective_spad_rtn_count);
+ }
+
+ status = VL53L0X_get_limit_check_value(dev,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+ &range_ignore_threshold_value);
+
+ if ((range_ignore_threshold_value > 0) &&
+ (signal_rate_per_spad < range_ignore_threshold_value)) {
+ /* Limit Fail add 2^6 to range status */
+ range_ignore_thresholdflag = 1;
+ }
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (none_flag == 1) {
+ *p_pal_range_status = 255; /* NONE */
+ } else if (device_range_status_internal == 1 ||
+ device_range_status_internal == 2 ||
+ device_range_status_internal == 3) {
+ *p_pal_range_status = 5; /* HW fail */
+ } else if (device_range_status_internal == 6 ||
+ device_range_status_internal == 9) {
+ *p_pal_range_status = 4; /* Phase fail */
+ } else if (device_range_status_internal == 8 ||
+ device_range_status_internal == 10 ||
+ signal_ref_clipflag == 1) {
+ *p_pal_range_status = 3; /* Min range */
+ } else if (device_range_status_internal == 4 ||
+ range_ignore_thresholdflag == 1) {
+ *p_pal_range_status = 2; /* Signal Fail */
+ } else if (sigma_limitflag == 1) {
+ *p_pal_range_status = 1; /* Sigma Fail */
+ } else {
+ *p_pal_range_status = 0; /* Range Valid */
+ }
+ }
+
+ /* DMAX only relevant during range error */
+ if (*p_pal_range_status == 0) {
+ p_ranging_measurement_data->RangeDMaxMilliMeter = 0;
+ }
+
+ /* fill the Limit Check Status */
+
+ status = VL53L0X_get_limit_check_enable(dev,
+ VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
+ &signal_rate_final_range_limit_check_enable);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if ((sigma_limit_check_enable == 0) || (sigma_limitflag == 1)) {
+ temp8 = 1;
+ } else {
+ temp8 = 0;
+ }
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, temp8);
+
+ if ((device_range_status_internal == 4) ||
+ (signal_rate_final_range_limit_check_enable == 0)) {
+ temp8 = 1;
+ } else {
+ temp8 = 0;
+ }
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
+ VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE,
+ temp8);
+
+ if ((signal_ref_clip_limit_check_enable == 0) ||
+ (signal_ref_clipflag == 1)) {
+ temp8 = 1;
+ } else {
+ temp8 = 0;
+ }
+
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP, temp8);
+
+ if ((range_ignore_threshold_limit_check_enable == 0) ||
+ (range_ignore_thresholdflag == 1)) {
+ temp8 = 1;
+ } else {
+ temp8 = 0;
+ }
+
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksStatus,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+ temp8);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_ranging_measurement_data(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t device_range_status;
+ uint8_t range_fractional_enable;
+ uint8_t pal_range_status;
+ uint8_t x_talk_compensation_enable;
+ uint16_t ambient_rate;
+ FixPoint1616_t signal_rate;
+ uint16_t x_talk_compensation_rate_mega_cps;
+ uint16_t effective_spad_rtn_count;
+ uint16_t tmpuint16;
+ uint16_t xtalk_range_milli_meter;
+ uint16_t linearity_corrective_gain;
+ uint8_t localBuffer[12];
+ VL53L0X_RangingMeasurementData_t last_range_data_buffer;
+
+ LOG_FUNCTION_START("");
+
+ /*
+ * use multi read even if some registers are not useful, result will
+ * be more efficient
+ * start reading at 0x14 dec20
+ * end reading at 0x21 dec33 total 14 bytes to read
+ */
+ status = VL53L0X_read_multi(dev, 0x14, localBuffer, 12);
+
+ if (status == VL53L0X_ERROR_NONE) {
+
+ p_ranging_measurement_data->ZoneId = 0; /* Only one zone */
+ p_ranging_measurement_data->TimeStamp = 0; /* Not Implemented */
+
+ tmpuint16 = VL53L0X_MAKEUINT16(localBuffer[11], localBuffer[10]);
+ /* cut1.1 if SYSTEM__RANGE_CONFIG if 1 range is 2bits fractional
+ *(format 11.2) else no fractional
+ */
+
+ p_ranging_measurement_data->MeasurementTimeUsec = 0;
+
+ signal_rate = VL53L0X_FIXPOINT97TOFIXPOINT1616(
+ VL53L0X_MAKEUINT16(localBuffer[7], localBuffer[6]));
+ /* peak_signal_count_rate_rtn_mcps */
+ p_ranging_measurement_data->SignalRateRtnMegaCps = signal_rate;
+
+ ambient_rate = VL53L0X_MAKEUINT16(localBuffer[9], localBuffer[8]);
+ p_ranging_measurement_data->AmbientRateRtnMegaCps =
+ VL53L0X_FIXPOINT97TOFIXPOINT1616(ambient_rate);
+
+ effective_spad_rtn_count = VL53L0X_MAKEUINT16(localBuffer[3],
+ localBuffer[2]);
+ /* EffectiveSpadRtnCount is 8.8 format */
+ p_ranging_measurement_data->EffectiveSpadRtnCount =
+ effective_spad_rtn_count;
+
+ device_range_status = localBuffer[0];
+
+ /* Get Linearity Corrective Gain */
+ linearity_corrective_gain = PALDevDataGet(dev,
+ LinearityCorrectiveGain);
+
+ /* Get ranging configuration */
+ range_fractional_enable = PALDevDataGet(dev,
+ RangeFractionalEnable);
+
+ if (linearity_corrective_gain != 1000) {
+
+ tmpuint16 = (uint16_t)((linearity_corrective_gain
+ * tmpuint16 + 500) / 1000);
+
+ /* Implement Xtalk */
+ VL53L0X_GETPARAMETERFIELD(dev,
+ XTalkCompensationRateMegaCps,
+ x_talk_compensation_rate_mega_cps);
+ VL53L0X_GETPARAMETERFIELD(dev, XTalkCompensationEnable,
+ x_talk_compensation_enable);
+
+ if (x_talk_compensation_enable) {
+
+ if ((signal_rate
+ - ((x_talk_compensation_rate_mega_cps
+ * effective_spad_rtn_count) >> 8))
+ <= 0) {
+ if (range_fractional_enable) {
+ xtalk_range_milli_meter = 8888;
+ } else {
+ xtalk_range_milli_meter = 8888 << 2;
+ }
+ } else {
+ xtalk_range_milli_meter =
+ (tmpuint16 * signal_rate)
+ / (signal_rate
+ - ((x_talk_compensation_rate_mega_cps
+ * effective_spad_rtn_count)
+ >> 8));
+ }
+
+ tmpuint16 = xtalk_range_milli_meter;
+ }
+
+ }
+
+ if (range_fractional_enable) {
+ p_ranging_measurement_data->RangeMilliMeter =
+ (uint16_t)((tmpuint16) >> 2);
+ p_ranging_measurement_data->RangeFractionalPart =
+ (uint8_t)((tmpuint16 & 0x03) << 6);
+ } else {
+ p_ranging_measurement_data->RangeMilliMeter = tmpuint16;
+ p_ranging_measurement_data->RangeFractionalPart = 0;
+ }
+
+ /*
+ * For a standard definition of RangeStatus, this should
+ * return 0 in case of good result after a ranging
+ * The range status depends on the device so call a device
+ * specific function to obtain the right Status.
+ */
+ status |= VL53L0X_get_pal_range_status(dev, device_range_status,
+ signal_rate, effective_spad_rtn_count,
+ p_ranging_measurement_data, &pal_range_status);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ p_ranging_measurement_data->RangeStatus = pal_range_status;
+ }
+
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Copy last read data into Dev buffer */
+ last_range_data_buffer = PALDevDataGet(dev, LastRangeMeasure);
+
+ last_range_data_buffer.RangeMilliMeter =
+ p_ranging_measurement_data->RangeMilliMeter;
+ last_range_data_buffer.RangeFractionalPart =
+ p_ranging_measurement_data->RangeFractionalPart;
+ last_range_data_buffer.RangeDMaxMilliMeter =
+ p_ranging_measurement_data->RangeDMaxMilliMeter;
+ last_range_data_buffer.MeasurementTimeUsec =
+ p_ranging_measurement_data->MeasurementTimeUsec;
+ last_range_data_buffer.SignalRateRtnMegaCps =
+ p_ranging_measurement_data->SignalRateRtnMegaCps;
+ last_range_data_buffer.AmbientRateRtnMegaCps =
+ p_ranging_measurement_data->AmbientRateRtnMegaCps;
+ last_range_data_buffer.EffectiveSpadRtnCount =
+ p_ranging_measurement_data->EffectiveSpadRtnCount;
+ last_range_data_buffer.RangeStatus =
+ p_ranging_measurement_data->RangeStatus;
+
+ PALDevDataSet(dev, LastRangeMeasure, last_range_data_buffer);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_perform_single_ranging_measurement(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+
+ LOG_FUNCTION_START("");
+
+ /* This function will do a complete single ranging
+ * Here we fix the mode! */
+ status = VL53L0X_set_device_mode(dev, VL53L0X_DEVICEMODE_SINGLE_RANGING);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_perform_single_measurement(dev);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_ranging_measurement_data(dev,
+ p_ranging_measurement_data);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_clear_interrupt_mask(dev, 0);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::perform_ref_signal_measurement(VL53L0X_DEV dev,
+ uint16_t *p_ref_signal_rate)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ VL53L0X_RangingMeasurementData_t ranging_measurement_data;
+
+ uint8_t sequence_config = 0;
+
+ /* store the value of the sequence config,
+ * this will be reset before the end of the function
+ */
+
+ sequence_config = PALDevDataGet(dev, SequenceConfig);
+
+ /*
+ * This function performs a reference signal rate measurement.
+ */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, 0xC0);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_perform_single_ranging_measurement(dev,
+ &ranging_measurement_data);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_word(dev,
+ VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF,
+ p_ref_signal_rate);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x00);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* restore the previous Sequence Config */
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+ sequence_config);
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, SequenceConfig, sequence_config);
+ }
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
+ uint32_t *ref_spad_count,
+ uint8_t *is_aperture_spads)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t last_spad_array[6];
+ uint8_t start_select = 0xB4;
+ uint32_t minimum_spad_count = 3;
+ uint32_t max_spad_count = 44;
+ uint32_t current_spad_index = 0;
+ uint32_t last_spad_index = 0;
+ int32_t next_good_spad = 0;
+ uint16_t target_ref_rate = 0x0A00; /* 20 MCPS in 9:7 format */
+ uint16_t peak_signal_rate_ref;
+ uint32_t need_apt_spads = 0;
+ uint32_t index = 0;
+ uint32_t spad_array_size = 6;
+ uint32_t signal_rate_diff = 0;
+ uint32_t last_signal_rate_diff = 0;
+ uint8_t complete = 0;
+ uint8_t vhv_settings = 0;
+ uint8_t phase_cal = 0;
+ uint32_t ref_spad_count_int = 0;
+ uint8_t is_aperture_spads_int = 0;
+
+ /*
+ * The reference SPAD initialization procedure determines the minimum
+ * amount of reference spads to be enables to achieve a target reference
+ * signal rate and should be performed once during initialization.
+ *
+ * Either aperture or non-aperture spads are applied but never both.
+ * Firstly non-aperture spads are set, begining with 5 spads, and
+ * increased one spad at a time until the closest measurement to the
+ * target rate is achieved.
+ *
+ * If the target rate is exceeded when 5 non-aperture spads are enabled,
+ * initialization is performed instead with aperture spads.
+ *
+ * When setting spads, a 'Good Spad Map' is applied.
+ *
+ * This procedure operates within a SPAD window of interest of a maximum
+ * 44 spads.
+ * The start point is currently fixed to 180, which lies towards the end
+ * of the non-aperture quadrant and runs in to the adjacent aperture
+ * quadrant.
+ */
+ target_ref_rate = PALDevDataGet(dev, targetRefRate);
+
+ /*
+ * Initialize Spad arrays.
+ * Currently the good spad map is initialised to 'All good'.
+ * This is a short term implementation. The good spad map will be
+ * provided as an input.
+ * Note that there are 6 bytes. Only the first 44 bits will be used to
+ * represent spads.
+ */
+ for (index = 0; index < spad_array_size; index++) {
+ dev->Data.SpadData.RefSpadEnables[index] = 0;
+ }
+
+
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x00);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
+ start_select);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE, 0);
+ }
+
+ /* Perform ref calibration */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_perform_ref_calibration(dev, &vhv_settings,
+ &phase_cal, 0);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Enable Minimum NON-APERTURE Spads */
+ current_spad_index = 0;
+ last_spad_index = current_spad_index;
+ need_apt_spads = 0;
+ status = enable_ref_spads(dev,
+ need_apt_spads,
+ dev->Data.SpadData.RefGoodSpadMap,
+ dev->Data.SpadData.RefSpadEnables,
+ spad_array_size,
+ start_select,
+ current_spad_index,
+ minimum_spad_count,
+ &last_spad_index);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ current_spad_index = last_spad_index;
+
+ status = perform_ref_signal_measurement(dev,
+ &peak_signal_rate_ref);
+ if ((status == VL53L0X_ERROR_NONE) &&
+ (peak_signal_rate_ref > target_ref_rate)) {
+ /* Signal rate measurement too high,
+ * switch to APERTURE SPADs */
+
+ for (index = 0; index < spad_array_size; index++) {
+ dev->Data.SpadData.RefSpadEnables[index] = 0;
+ }
+
+
+ /* Increment to the first APERTURE spad */
+ while ((is_aperture(start_select + current_spad_index)
+ == 0) && (current_spad_index < max_spad_count)) {
+ current_spad_index++;
+ }
+
+ need_apt_spads = 1;
+
+ status = enable_ref_spads(dev,
+ need_apt_spads,
+ dev->Data.SpadData.RefGoodSpadMap,
+ dev->Data.SpadData.RefSpadEnables,
+ spad_array_size,
+ start_select,
+ current_spad_index,
+ minimum_spad_count,
+ &last_spad_index);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ current_spad_index = last_spad_index;
+ status = perform_ref_signal_measurement(dev,
+ &peak_signal_rate_ref);
+
+ if ((status == VL53L0X_ERROR_NONE) &&
+ (peak_signal_rate_ref > target_ref_rate)) {
+ /* Signal rate still too high after
+ * setting the minimum number of
+ * APERTURE spads. Can do no more
+ * therefore set the min number of
+ * aperture spads as the result.
+ */
+ is_aperture_spads_int = 1;
+ ref_spad_count_int = minimum_spad_count;
+ }
+ }
+ } else {
+ need_apt_spads = 0;
+ }
+ }
+
+ if ((status == VL53L0X_ERROR_NONE) &&
+ (peak_signal_rate_ref < target_ref_rate)) {
+ /* At this point, the minimum number of either aperture
+ * or non-aperture spads have been set. Proceed to add
+ * spads and perform measurements until the target
+ * reference is reached.
+ */
+ is_aperture_spads_int = need_apt_spads;
+ ref_spad_count_int = minimum_spad_count;
+
+ memcpy(last_spad_array, dev->Data.SpadData.RefSpadEnables,
+ spad_array_size);
+ last_signal_rate_diff = abs(peak_signal_rate_ref -
+ target_ref_rate);
+ complete = 0;
+
+ while (!complete) {
+ get_next_good_spad(
+ dev->Data.SpadData.RefGoodSpadMap,
+ spad_array_size, current_spad_index,
+ &next_good_spad);
+
+ if (next_good_spad == -1) {
+ status = VL53L0X_ERROR_REF_SPAD_INIT;
+ break;
+ }
+
+ /* Cannot combine Aperture and Non-Aperture spads, so
+ * ensure the current spad is of the correct type.
+ */
+ if (is_aperture((uint32_t)start_select + next_good_spad) !=
+ need_apt_spads) {
+ /* At this point we have enabled the maximum
+ * number of Aperture spads.
+ */
+ complete = 1;
+ break;
+ }
+
+ (ref_spad_count_int)++;
+
+ current_spad_index = next_good_spad;
+ status = enable_spad_bit(
+ dev->Data.SpadData.RefSpadEnables,
+ spad_array_size, current_spad_index);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ current_spad_index++;
+ /* Proceed to apply the additional spad and
+ * perform measurement. */
+ status = set_ref_spad_map(dev,
+ dev->Data.SpadData.RefSpadEnables);
+ }
+
+ if (status != VL53L0X_ERROR_NONE) {
+ break;
+ }
+
+ status = perform_ref_signal_measurement(dev,
+ &peak_signal_rate_ref);
+
+ if (status != VL53L0X_ERROR_NONE) {
+ break;
+ }
+
+ signal_rate_diff = abs(peak_signal_rate_ref - target_ref_rate);
+
+ if (peak_signal_rate_ref > target_ref_rate) {
+ /* Select the spad map that provides the
+ * measurement closest to the target rate,
+ * either above or below it.
+ */
+ if (signal_rate_diff > last_signal_rate_diff) {
+ /* Previous spad map produced a closer
+ * measurement, so choose this. */
+ status = set_ref_spad_map(dev,
+ last_spad_array);
+ memcpy(
+ dev->Data.SpadData.RefSpadEnables,
+ last_spad_array, spad_array_size);
+
+ (ref_spad_count_int)--;
+ }
+ complete = 1;
+ } else {
+ /* Continue to add spads */
+ last_signal_rate_diff = signal_rate_diff;
+ memcpy(last_spad_array,
+ dev->Data.SpadData.RefSpadEnables,
+ spad_array_size);
+ }
+
+ } /* while */
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ *ref_spad_count = ref_spad_count_int;
+ *is_aperture_spads = is_aperture_spads_int;
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev, RefSpadsInitialised, 1);
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadCount, (uint8_t)(*ref_spad_count));
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadType, *is_aperture_spads);
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_reference_spads(VL53L0X_DEV dev,
+ uint32_t count, uint8_t is_aperture_spads)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint32_t current_spad_index = 0;
+ uint8_t start_select = 0xB4;
+ uint32_t spad_array_size = 6;
+ uint32_t max_spad_count = 44;
+ uint32_t last_spad_index;
+ uint32_t index;
+
+ /*
+ * This function applies a requested number of reference spads, either
+ * aperture or
+ * non-aperture, as requested.
+ * The good spad map will be applied.
+ */
+
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x00);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT,
+ start_select);
+ }
+
+ for (index = 0; index < spad_array_size; index++) {
+ dev->Data.SpadData.RefSpadEnables[index] = 0;
+ }
+
+ if (is_aperture_spads) {
+ /* Increment to the first APERTURE spad */
+ while ((is_aperture(start_select + current_spad_index) == 0) &&
+ (current_spad_index < max_spad_count)) {
+ current_spad_index++;
+ }
+ }
+ status = enable_ref_spads(dev,
+ is_aperture_spads,
+ dev->Data.SpadData.RefGoodSpadMap,
+ dev->Data.SpadData.RefSpadEnables,
+ spad_array_size,
+ start_select,
+ current_spad_index,
+ count,
+ &last_spad_index);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev, RefSpadsInitialised, 1);
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadCount, (uint8_t)(count));
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadType, is_aperture_spads);
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_wait_device_booted(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NOT_IMPLEMENTED;
+ LOG_FUNCTION_START("");
+
+ /* not implemented on VL53L0X */
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_perform_ref_calibration(VL53L0X_DEV dev, uint8_t *p_vhv_settings,
+ uint8_t *p_phase_cal)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_perform_ref_calibration(dev, p_vhv_settings,
+ p_phase_cal, 1);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
+ uint32_t *ref_spad_count, uint8_t *is_aperture_spads)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_perform_ref_spad_management(dev, ref_spad_count,
+ is_aperture_spads);
+
+ LOG_FUNCTION_END(status);
+
+ return status;
+}
+
+/* Group PAL Init Functions */
+VL53L0X_Error VL53L0X::VL53L0X_set_device_address(VL53L0X_DEV dev, uint8_t device_address)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS,
+ device_address / 2);
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_gpio_config(VL53L0X_DEV dev, uint8_t pin,
+ VL53L0X_DeviceModes device_mode, VL53L0X_GpioFunctionality functionality,
+ VL53L0X_InterruptPolarity polarity)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t data;
+
+ LOG_FUNCTION_START("");
+
+ if (pin != 0) {
+ status = VL53L0X_ERROR_GPIO_NOT_EXISTING;
+ } else if (device_mode == VL53L0X_DEVICEMODE_GPIO_DRIVE) {
+ if (polarity == VL53L0X_INTERRUPTPOLARITY_LOW) {
+ data = 0x10;
+ } else {
+ data = 1;
+ }
+
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH, data);
+
+ } else {
+ if (device_mode == VL53L0X_DEVICEMODE_GPIO_OSC) {
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x00);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x00);
+ status |= VL53L0X_write_byte(dev, 0x80, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x85, 0x02);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x04);
+ status |= VL53L0X_write_byte(dev, 0xcd, 0x00);
+ status |= VL53L0X_write_byte(dev, 0xcc, 0x11);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x07);
+ status |= VL53L0X_write_byte(dev, 0xbe, 0x00);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x06);
+ status |= VL53L0X_write_byte(dev, 0xcc, 0x09);
+
+ status |= VL53L0X_write_byte(dev, 0xff, 0x00);
+ status |= VL53L0X_write_byte(dev, 0xff, 0x01);
+ status |= VL53L0X_write_byte(dev, 0x00, 0x00);
+
+ } else {
+
+ if (status == VL53L0X_ERROR_NONE) {
+ switch (functionality) {
+ case VL53L0X_GPIOFUNCTIONALITY_OFF:
+ data = 0x00;
+ break;
+ case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW:
+ data = 0x01;
+ break;
+ case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH:
+ data = 0x02;
+ break;
+ case VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT:
+ data = 0x03;
+ break;
+ case VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY:
+ data = 0x04;
+ break;
+ default:
+ status =
+ VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED;
+ }
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO, data);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (polarity == VL53L0X_INTERRUPTPOLARITY_LOW) {
+ data = 0;
+ } else {
+ data = (uint8_t)(1 << 4);
+ }
+ status = VL53L0X_update_byte(dev,
+ VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH, 0xEF, data);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ Pin0GpioFunctionality, functionality);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_clear_interrupt_mask(dev, 0);
+ }
+ }
+ }
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_fraction_enable(VL53L0X_DEV dev, uint8_t *p_enabled)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_RANGE_CONFIG, p_enabled);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ *p_enabled = (*p_enabled & 1);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+uint16_t VL53L0X::VL53L0X_encode_timeout(uint32_t timeout_macro_clks)
+{
+ /*!
+ * Encode timeout in macro periods in (LSByte * 2^MSByte) + 1 format
+ */
+
+ uint16_t encoded_timeout = 0;
+ uint32_t ls_byte = 0;
+ uint16_t ms_byte = 0;
+
+ if (timeout_macro_clks > 0) {
+ ls_byte = timeout_macro_clks - 1;
+
+ while ((ls_byte & 0xFFFFFF00) > 0) {
+ ls_byte = ls_byte >> 1;
+ ms_byte++;
+ }
+
+ encoded_timeout = (ms_byte << 8)
+ + (uint16_t)(ls_byte & 0x000000FF);
+ }
+
+ return encoded_timeout;
+
+}
+
+VL53L0X_Error VL53L0X::set_sequence_step_timeout(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id,
+ uint32_t timeout_micro_secs)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t current_vcsel_pulse_period_p_clk;
+ uint8_t msrc_encoded_time_out;
+ uint16_t pre_range_encoded_time_out;
+ uint16_t pre_range_time_out_m_clks;
+ uint16_t msrc_range_time_out_m_clks;
+ uint32_t final_range_time_out_m_clks;
+ uint16_t final_range_encoded_time_out;
+ VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
+
+ if ((sequence_step_id == VL53L0X_SEQUENCESTEP_TCC) ||
+ (sequence_step_id == VL53L0X_SEQUENCESTEP_DSS) ||
+ (sequence_step_id == VL53L0X_SEQUENCESTEP_MSRC)) {
+
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ msrc_range_time_out_m_clks = VL53L0X_calc_timeout_mclks(dev,
+ timeout_micro_secs,
+ (uint8_t)current_vcsel_pulse_period_p_clk);
+
+ if (msrc_range_time_out_m_clks > 256) {
+ msrc_encoded_time_out = 255;
+ } else {
+ msrc_encoded_time_out =
+ (uint8_t)msrc_range_time_out_m_clks - 1;
+ }
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ LastEncodedTimeout,
+ msrc_encoded_time_out);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP,
+ msrc_encoded_time_out);
+ }
+ } else {
+
+ if (sequence_step_id == VL53L0X_SEQUENCESTEP_PRE_RANGE) {
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+ pre_range_time_out_m_clks =
+ VL53L0X_calc_timeout_mclks(dev,
+ timeout_micro_secs,
+ (uint8_t)current_vcsel_pulse_period_p_clk);
+ pre_range_encoded_time_out = VL53L0X_encode_timeout(
+ pre_range_time_out_m_clks);
+
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev,
+ LastEncodedTimeout,
+ pre_range_encoded_time_out);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_word(dev,
+ VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
+ pre_range_encoded_time_out);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ PreRangeTimeoutMicroSecs,
+ timeout_micro_secs);
+ }
+ } else if (sequence_step_id == VL53L0X_SEQUENCESTEP_FINAL_RANGE) {
+
+ /* For the final range timeout, the pre-range timeout
+ * must be added. To do this both final and pre-range
+ * timeouts must be expressed in macro periods MClks
+ * because they have different vcsel periods.
+ */
+
+ VL53L0X_get_sequence_step_enables(dev,
+ &scheduler_sequence_steps);
+ pre_range_time_out_m_clks = 0;
+ if (scheduler_sequence_steps.PreRangeOn) {
+
+ /* Retrieve PRE-RANGE VCSEL Period */
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+
+ /* Retrieve PRE-RANGE Timeout in Macro periods
+ * (MCLKS) */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_word(dev, 0x51,
+ &pre_range_encoded_time_out);
+ pre_range_time_out_m_clks =
+ VL53L0X_decode_timeout(
+ pre_range_encoded_time_out);
+ }
+ }
+
+ /* Calculate FINAL RANGE Timeout in Macro Periods
+ * (MCLKS) and add PRE-RANGE value
+ */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_vcsel_pulse_period(dev,
+ VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
+ ¤t_vcsel_pulse_period_p_clk);
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ final_range_time_out_m_clks =
+ VL53L0X_calc_timeout_mclks(dev,
+ timeout_micro_secs,
+ (uint8_t) current_vcsel_pulse_period_p_clk);
+
+ final_range_time_out_m_clks += pre_range_time_out_m_clks;
+
+ final_range_encoded_time_out =
+ VL53L0X_encode_timeout(final_range_time_out_m_clks);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_word(dev, 0x71,
+ final_range_encoded_time_out);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ FinalRangeTimeoutMicroSecs,
+ timeout_micro_secs);
+ }
+ }
+ } else {
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+
+ }
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t measurement_timing_budget_micro_seconds)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint32_t final_range_timing_budget_micro_seconds;
+ VL53L0X_SchedulerSequenceSteps_t scheduler_sequence_steps;
+ uint32_t msrc_dcc_tcc_timeout_micro_seconds = 2000;
+ uint32_t start_overhead_micro_seconds = 1910;
+ uint32_t end_overhead_micro_seconds = 960;
+ uint32_t msrc_overhead_micro_seconds = 660;
+ uint32_t tcc_overhead_micro_seconds = 590;
+ uint32_t dss_overhead_micro_seconds = 690;
+ uint32_t pre_range_overhead_micro_seconds = 660;
+ uint32_t final_range_overhead_micro_seconds = 550;
+ uint32_t pre_range_timeout_micro_seconds = 0;
+ uint32_t c_min_timing_budget_micro_seconds = 20000;
+ uint32_t sub_timeout = 0;
+
+ LOG_FUNCTION_START("");
+
+ if (measurement_timing_budget_micro_seconds
+ < c_min_timing_budget_micro_seconds) {
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ return status;
+ }
+
+ final_range_timing_budget_micro_seconds =
+ measurement_timing_budget_micro_seconds -
+ (start_overhead_micro_seconds + end_overhead_micro_seconds);
+
+ status = VL53L0X_get_sequence_step_enables(dev, &scheduler_sequence_steps);
+
+ if (status == VL53L0X_ERROR_NONE &&
+ (scheduler_sequence_steps.TccOn ||
+ scheduler_sequence_steps.MsrcOn ||
+ scheduler_sequence_steps.DssOn)) {
+
+ /* TCC, MSRC and DSS all share the same timeout */
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_MSRC,
+ &msrc_dcc_tcc_timeout_micro_seconds);
+
+ /* Subtract the TCC, MSRC and DSS timeouts if they are
+ * enabled. */
+
+ if (status != VL53L0X_ERROR_NONE) {
+ return status;
+ }
+
+ /* TCC */
+ if (scheduler_sequence_steps.TccOn) {
+
+ sub_timeout = msrc_dcc_tcc_timeout_micro_seconds
+ + tcc_overhead_micro_seconds;
+
+ if (sub_timeout <
+ final_range_timing_budget_micro_seconds) {
+ final_range_timing_budget_micro_seconds -=
+ sub_timeout;
+ } else {
+ /* Requested timeout too big. */
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ }
+
+ if (status != VL53L0X_ERROR_NONE) {
+ LOG_FUNCTION_END(status);
+ return status;
+ }
+
+ /* DSS */
+ if (scheduler_sequence_steps.DssOn) {
+
+ sub_timeout = 2 * (msrc_dcc_tcc_timeout_micro_seconds +
+ dss_overhead_micro_seconds);
+
+ if (sub_timeout < final_range_timing_budget_micro_seconds) {
+ final_range_timing_budget_micro_seconds
+ -= sub_timeout;
+ } else {
+ /* Requested timeout too big. */
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ } else if (scheduler_sequence_steps.MsrcOn) {
+ /* MSRC */
+ sub_timeout = msrc_dcc_tcc_timeout_micro_seconds +
+ msrc_overhead_micro_seconds;
+
+ if (sub_timeout < final_range_timing_budget_micro_seconds) {
+ final_range_timing_budget_micro_seconds
+ -= sub_timeout;
+ } else {
+ /* Requested timeout too big. */
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ }
+
+ }
+
+ if (status != VL53L0X_ERROR_NONE) {
+ LOG_FUNCTION_END(status);
+ return status;
+ }
+
+ if (scheduler_sequence_steps.PreRangeOn) {
+
+ /* Subtract the Pre-range timeout if enabled. */
+
+ status = get_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_PRE_RANGE,
+ &pre_range_timeout_micro_seconds);
+
+ sub_timeout = pre_range_timeout_micro_seconds +
+ pre_range_overhead_micro_seconds;
+
+ if (sub_timeout < final_range_timing_budget_micro_seconds) {
+ final_range_timing_budget_micro_seconds -= sub_timeout;
+ } else {
+ /* Requested timeout too big. */
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ }
+
+
+ if (status == VL53L0X_ERROR_NONE &&
+ scheduler_sequence_steps.FinalRangeOn) {
+
+ final_range_timing_budget_micro_seconds -=
+ final_range_overhead_micro_seconds;
+
+ /* Final Range Timeout
+ * Note that the final range timeout is determined by the timing
+ * budget and the sum of all other timeouts within the sequence.
+ * If there is no room for the final range timeout, then an error
+ * will be set. Otherwise the remaining time will be applied to
+ * the final range.
+ */
+ status = set_sequence_step_timeout(dev,
+ VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+ final_range_timing_budget_micro_seconds);
+
+ VL53L0X_SETPARAMETERFIELD(dev,
+ MeasurementTimingBudgetMicroSeconds,
+ measurement_timing_budget_micro_seconds);
+ }
+
+ LOG_FUNCTION_END(status);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t measurement_timing_budget_micro_seconds)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(dev,
+ measurement_timing_budget_micro_seconds);
+
+ LOG_FUNCTION_END(status);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_sequence_step_enable(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_step_enabled)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t sequence_config = 0;
+ uint8_t sequence_config_new = 0;
+ uint32_t measurement_timing_budget_micro_seconds;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_read_byte(dev, VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG,
+ &sequence_config);
+
+ sequence_config_new = sequence_config;
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (sequence_step_enabled == 1) {
+
+ /* Enable requested sequence step
+ */
+ switch (sequence_step_id) {
+ case VL53L0X_SEQUENCESTEP_TCC:
+ sequence_config_new |= 0x10;
+ break;
+ case VL53L0X_SEQUENCESTEP_DSS:
+ sequence_config_new |= 0x28;
+ break;
+ case VL53L0X_SEQUENCESTEP_MSRC:
+ sequence_config_new |= 0x04;
+ break;
+ case VL53L0X_SEQUENCESTEP_PRE_RANGE:
+ sequence_config_new |= 0x40;
+ break;
+ case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
+ sequence_config_new |= 0x80;
+ break;
+ default:
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ } else {
+ /* Disable requested sequence step
+ */
+ switch (sequence_step_id) {
+ case VL53L0X_SEQUENCESTEP_TCC:
+ sequence_config_new &= 0xef;
+ break;
+ case VL53L0X_SEQUENCESTEP_DSS:
+ sequence_config_new &= 0xd7;
+ break;
+ case VL53L0X_SEQUENCESTEP_MSRC:
+ sequence_config_new &= 0xfb;
+ break;
+ case VL53L0X_SEQUENCESTEP_PRE_RANGE:
+ sequence_config_new &= 0xbf;
+ break;
+ case VL53L0X_SEQUENCESTEP_FINAL_RANGE:
+ sequence_config_new &= 0x7f;
+ break;
+ default:
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ }
+ }
+
+ if (sequence_config_new != sequence_config) {
+ /* Apply New Setting */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev,
+ VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, sequence_config_new);
+ }
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, SequenceConfig, sequence_config_new);
+ }
+
+
+ /* Recalculate timing budget */
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_GETPARAMETERFIELD(dev,
+ MeasurementTimingBudgetMicroSeconds,
+ measurement_timing_budget_micro_seconds);
+
+ VL53L0X_set_measurement_timing_budget_micro_seconds(dev,
+ measurement_timing_budget_micro_seconds);
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_set_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
+ uint8_t limit_check_enable)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ FixPoint1616_t temp_fix1616 = 0;
+ uint8_t limit_check_enable_int = 0;
+ uint8_t limit_check_disable = 0;
+ uint8_t temp8;
+
+ LOG_FUNCTION_START("");
+
+ if (limit_check_id >= VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS) {
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ } else {
+ if (limit_check_enable == 0) {
+ temp_fix1616 = 0;
+ limit_check_enable_int = 0;
+ limit_check_disable = 1;
+
+ } else {
+ VL53L0X_GETARRAYPARAMETERFIELD(dev, LimitChecksValue,
+ limit_check_id, temp_fix1616);
+ limit_check_disable = 0;
+ /* this to be sure to have either 0 or 1 */
+ limit_check_enable_int = 1;
+ }
+
+ switch (limit_check_id) {
+
+ case VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE:
+ /* internal computation: */
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE,
+ limit_check_enable_int);
+
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE:
+
+ status = VL53L0X_write_word(dev,
+ VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT,
+ VL53L0X_FIXPOINT1616TOFIXPOINT97(temp_fix1616));
+
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP:
+
+ /* internal computation: */
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
+ VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP,
+ limit_check_enable_int);
+
+ break;
+
+ case VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD:
+
+ /* internal computation: */
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
+ VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD,
+ limit_check_enable_int);
+
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC:
+
+ temp8 = (uint8_t)(limit_check_disable << 1);
+ status = VL53L0X_update_byte(dev,
+ VL53L0X_REG_MSRC_CONFIG_CONTROL,
+ 0xFE, temp8);
+
+ break;
+
+ case VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE:
+
+ temp8 = (uint8_t)(limit_check_disable << 4);
+ status = VL53L0X_update_byte(dev,
+ VL53L0X_REG_MSRC_CONFIG_CONTROL,
+ 0xEF, temp8);
+
+ break;
+
+
+ default:
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+
+ }
+
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ if (limit_check_enable == 0) {
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
+ limit_check_id, 0);
+ } else {
+ VL53L0X_SETARRAYPARAMETERFIELD(dev, LimitChecksEnable,
+ limit_check_id, 1);
+ }
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_static_init(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ VL53L0X_DeviceParameters_t current_parameters = {0};
+ uint8_t *p_tuning_setting_buffer;
+ uint16_t tempword = 0;
+ uint8_t tempbyte = 0;
+ uint8_t use_internal_tuning_settings = 0;
+ uint32_t count = 0;
+ uint8_t is_aperture_spads = 0;
+ uint32_t ref_spad_count = 0;
+ uint8_t aperture_spads = 0;
+ uint8_t vcsel_pulse_period_pclk;
+ uint32_t seq_timeout_micro_secs;
+
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_get_info_from_device(dev, 1);
+
+ /* set the ref spad from NVM */
+ count = (uint32_t)VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadCount);
+ aperture_spads = VL53L0X_GETDEVICESPECIFICPARAMETER(dev,
+ ReferenceSpadType);
+
+ /* NVM value invalid */
+ if ((aperture_spads > 1) ||
+ ((aperture_spads == 1) && (count > 32)) ||
+ ((aperture_spads == 0) && (count > 12))) {
+ status = wrapped_VL53L0X_perform_ref_spad_management(dev, &ref_spad_count,
+ &is_aperture_spads);
+ } else {
+ status = VL53L0X_set_reference_spads(dev, count, aperture_spads);
+ }
+
+
+ /* Initialize tuning settings buffer to prevent compiler warning. */
+ p_tuning_setting_buffer = DefaultTuningSettings;
+
+ if (status == VL53L0X_ERROR_NONE) {
+ use_internal_tuning_settings = PALDevDataGet(dev,
+ UseInternalTuningSettings);
+
+ if (use_internal_tuning_settings == 0) {
+ p_tuning_setting_buffer = PALDevDataGet(dev,
+ pTuningSettingsPointer);
+ } else {
+ p_tuning_setting_buffer = DefaultTuningSettings;
+ }
+
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_load_tuning_settings(dev, p_tuning_setting_buffer);
+ }
+
+
+ /* Set interrupt config to new sample ready */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_set_gpio_config(dev, 0, 0,
+ VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
+ VL53L0X_INTERRUPTPOLARITY_LOW);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status |= VL53L0X_read_word(dev, 0x84, &tempword);
+ status |= VL53L0X_write_byte(dev, 0xFF, 0x00);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(dev, OscFrequencyMHz,
+ VL53L0X_FIXPOINT412TOFIXPOINT1616(tempword));
+ }
+
+ /* After static init, some device parameters may be changed,
+ * so update them */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_device_parameters(dev, ¤t_parameters);
+ }
+
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_fraction_enable(dev, &tempbyte);
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, RangeFractionalEnable, tempbyte);
+ }
+
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, CurrentParameters, current_parameters);
+ }
+
+
+ /* read the sequence config and save it */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_byte(dev,
+ VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG, &tempbyte);
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, SequenceConfig, tempbyte);
+ }
+ }
+
+ /* Disable MSRC and TCC by default */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_set_sequence_step_enable(dev,
+ VL53L0X_SEQUENCESTEP_TCC, 0);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_set_sequence_step_enable(dev,
+ VL53L0X_SEQUENCESTEP_MSRC, 0);
+ }
+
+ /* Set PAL State to standby */
+ if (status == VL53L0X_ERROR_NONE) {
+ PALDevDataSet(dev, PalState, VL53L0X_STATE_IDLE);
+ }
+
+ /* Store pre-range vcsel period */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_vcsel_pulse_period(
+ dev,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE,
+ &vcsel_pulse_period_pclk);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ PreRangeVcselPulsePeriod,
+ vcsel_pulse_period_pclk);
+ }
+
+ /* Store final-range vcsel period */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_get_vcsel_pulse_period(
+ dev,
+ VL53L0X_VCSEL_PERIOD_FINAL_RANGE,
+ &vcsel_pulse_period_pclk);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ FinalRangeVcselPulsePeriod,
+ vcsel_pulse_period_pclk);
+ }
+
+ /* Store pre-range timeout */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = get_sequence_step_timeout(
+ dev,
+ VL53L0X_SEQUENCESTEP_PRE_RANGE,
+ &seq_timeout_micro_secs);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ PreRangeTimeoutMicroSecs,
+ seq_timeout_micro_secs);
+ }
+
+ /* Store final-range timeout */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = get_sequence_step_timeout(
+ dev,
+ VL53L0X_SEQUENCESTEP_FINAL_RANGE,
+ &seq_timeout_micro_secs);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ VL53L0X_SETDEVICESPECIFICPARAMETER(
+ dev,
+ FinalRangeTimeoutMicroSecs,
+ seq_timeout_micro_secs);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+
+VL53L0X_Error VL53L0X::VL53L0X_stop_measurement(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_write_byte(dev, VL53L0X_REG_SYSRANGE_START,
+ VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT);
+
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status = VL53L0X_write_byte(dev, 0x00, 0x00);
+ status = VL53L0X_write_byte(dev, 0x91, 0x00);
+ status = VL53L0X_write_byte(dev, 0x00, 0x01);
+ status = VL53L0X_write_byte(dev, 0xFF, 0x00);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ /* Set PAL State to Idle */
+ PALDevDataSet(dev, PalState, VL53L0X_STATE_IDLE);
+ }
+
+ /* Check if need to apply interrupt settings */
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_check_and_load_interrupt_settings(dev, 0);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_get_stop_completed_status(VL53L0X_DEV dev,
+ uint32_t *p_stop_status)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t byte = 0;
+ LOG_FUNCTION_START("");
+
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_read_byte(dev, 0x04, &byte);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ status = VL53L0X_write_byte(dev, 0xFF, 0x0);
+ }
+
+ *p_stop_status = byte;
+
+ if (byte == 0) {
+ status = VL53L0X_write_byte(dev, 0x80, 0x01);
+ status = VL53L0X_write_byte(dev, 0xFF, 0x01);
+ status = VL53L0X_write_byte(dev, 0x00, 0x00);
+ status = VL53L0X_write_byte(dev, 0x91,
+ PALDevDataGet(dev, StopVariable));
+ status = VL53L0X_write_byte(dev, 0x00, 0x01);
+ status = VL53L0X_write_byte(dev, 0xFF, 0x00);
+ status = VL53L0X_write_byte(dev, 0x80, 0x00);
+ }
+
+ LOG_FUNCTION_END(status);
+ return status;
+}
+
+/****************** Write and read functions from I2C *************************/
+
+VL53L0X_Error VL53L0X::VL53L0X_write_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count)
+{
+ int status;
+
+ status = VL53L0X_i2c_write(dev->I2cDevAddr, index, p_data, (uint16_t)count);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_read_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count)
+{
+ int status;
+
+ if (count >= VL53L0X_MAX_I2C_XFER_SIZE) {
+ status = VL53L0X_ERROR_INVALID_PARAMS;
+ }
+
+ status = VL53L0X_i2c_read(dev->I2cDevAddr, index, p_data, (uint16_t)count);
+
+ return status;
+}
+
+
+VL53L0X_Error VL53L0X::VL53L0X_write_byte(VL53L0X_DEV Dev, uint8_t index, uint8_t data)
+{
+ int status;
+
+ status = VL53L0X_i2c_write(Dev->I2cDevAddr, index, &data, 1);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_write_word(VL53L0X_DEV dev, uint8_t index, uint16_t data)
+{
+ int status;
+ uint8_t buffer[2];
+
+ buffer[0] = data >> 8;
+ buffer[1] = data & 0x00FF;
+ status = VL53L0X_i2c_write(dev->I2cDevAddr, index, (uint8_t *)buffer, 2);
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_write_dword(VL53L0X_DEV Dev, uint8_t index, uint32_t data)
+{
+ int status;
+ uint8_t buffer[4];
+
+ buffer[0] = (data >> 24) & 0xFF;
+ buffer[1] = (data >> 16) & 0xFF;
+ buffer[2] = (data >> 8) & 0xFF;
+ buffer[3] = (data >> 0) & 0xFF;
+ status = VL53L0X_i2c_write(Dev->I2cDevAddr, index, (uint8_t *)buffer, 4);
+ return status;
+}
+
+
+VL53L0X_Error VL53L0X::VL53L0X_read_byte(VL53L0X_DEV Dev, uint8_t index, uint8_t *p_data)
+{
+ int status;
+
+ status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, p_data, 1);
+
+ if (status) {
+ return -1;
+ }
+
+ return 0;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_read_word(VL53L0X_DEV Dev, uint8_t index, uint16_t *p_data)
+{
+ int status;
+ uint8_t buffer[2] = {0, 0};
+
+ status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, buffer, 2);
+ if (!status) {
+ *p_data = (buffer[0] << 8) + buffer[1];
+ }
+ return status;
+
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_read_dword(VL53L0X_DEV Dev, uint8_t index, uint32_t *p_data)
+{
+ int status;
+ uint8_t buffer[4] = {0, 0, 0, 0};
+
+ status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, buffer, 4);
+ if (!status) {
+ *p_data = (buffer[0] << 24) + (buffer[1] << 16) + (buffer[2] << 8) + buffer[3];
+ }
+ return status;
+
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_update_byte(VL53L0X_DEV Dev, uint8_t index, uint8_t and_data, uint8_t or_data)
+{
+ int status;
+ uint8_t buffer = 0;
+
+ /* read data direct onto buffer */
+ status = VL53L0X_i2c_read(Dev->I2cDevAddr, index, &buffer, 1);
+ if (!status) {
+ buffer = (buffer & and_data) | or_data;
+ status = VL53L0X_i2c_write(Dev->I2cDevAddr, index, &buffer, (uint8_t)1);
+ }
+ return status;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_i2c_write(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t *p_data,
+ uint16_t NumByteToWrite)
+{
+ int ret;
+#if ORIGINAL
+ ret = _dev_i2c->i2c_write(p_data, DeviceAddr, RegisterAddr, NumByteToWrite);
+#else
+ ret = i2c_write(p_data, DeviceAddr, RegisterAddr, NumByteToWrite);
+#endif
+
+ if (ret) {
+ return -1;
+ }
+ return 0;
+}
+
+VL53L0X_Error VL53L0X::VL53L0X_i2c_read(uint8_t DeviceAddr, uint8_t RegisterAddr, uint8_t *p_data,
+ uint16_t NumByteToRead)
+{
+ int ret;
+
+#if ORIGINAL
+ ret = _dev_i2c->i2c_read(p_data, DeviceAddr, RegisterAddr, NumByteToRead);
+#else
+ ret = i2c_read(p_data, DeviceAddr, RegisterAddr, NumByteToRead);
+#endif
+
+ if (ret) {
+ return -1;
+ }
+ return 0;
+}
+
+int VL53L0X::read_id(uint8_t *id)
+{
+ int status = 0;
+ uint16_t rl_id = 0;
+
+ status = VL53L0X_read_word(_device, VL53L0X_REG_IDENTIFICATION_MODEL_ID, &rl_id);
+ if (rl_id == 0xEEAA) {
+ return status;
+ }
+
+ return -1;
+}
+
+
+VL53L0X_Error VL53L0X::wait_measurement_data_ready(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint8_t new_dat_ready = 0;
+ uint32_t loop_nb;
+
+ // Wait until it finished
+ // use timeout to avoid deadlock
+ if (status == VL53L0X_ERROR_NONE) {
+ loop_nb = 0;
+ do {
+ status = VL53L0X_get_measurement_data_ready(dev, &new_dat_ready);
+ if ((new_dat_ready == 0x01) || status != VL53L0X_ERROR_NONE) {
+ break;
+ }
+ loop_nb = loop_nb + 1;
+ VL53L0X_polling_delay(dev);
+ } while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
+
+ if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
+ status = VL53L0X_ERROR_TIME_OUT;
+ }
+ }
+
+ return status;
+}
+
+VL53L0X_Error VL53L0X::wait_stop_completed(VL53L0X_DEV dev)
+{
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint32_t stop_completed = 0;
+ uint32_t loop_nb;
+
+ // Wait until it finished
+ // use timeout to avoid deadlock
+ if (status == VL53L0X_ERROR_NONE) {
+ loop_nb = 0;
+ do {
+ status = VL53L0X_get_stop_completed_status(dev, &stop_completed);
+ if ((stop_completed == 0x00) || status != VL53L0X_ERROR_NONE) {
+ break;
+ }
+ loop_nb = loop_nb + 1;
+ VL53L0X_polling_delay(dev);
+ } while (loop_nb < VL53L0X_DEFAULT_MAX_LOOP);
+
+ if (loop_nb >= VL53L0X_DEFAULT_MAX_LOOP) {
+ status = VL53L0X_ERROR_TIME_OUT;
+ }
+
+ }
+
+ return status;
+}
+
+
+int VL53L0X::init_sensor(uint8_t new_addr)
+{
+ int status;
+
+ VL53L0X_off();
+ VL53L0X_on();
+
+// status=VL53L0X_WaitDeviceBooted(Device);
+// if(status)
+// printf("WaitDeviceBooted fail\n\r");
+ status = is_present();
+ if (!status) {
+ status = init(&_my_device);
+ if (status != VL53L0X_ERROR_NONE) {
+ printf("Failed to init VL53L0X sensor!\n\r");
+ return status;
+ }
+
+ // deduce silicon version
+ status = VL53L0X_get_device_info(&_my_device, &_device_info);
+
+ status = prepare();
+ if (status != VL53L0X_ERROR_NONE) {
+ printf("Failed to prepare VL53L0X!\n\r");
+ return status;
+ }
+
+ if (new_addr != VL53L0X_DEFAULT_ADDRESS) {
+ status = set_device_address(new_addr);
+ if (status) {
+ printf("Failed to change I2C address!\n\r");
+ return status;
+ }
+ } else {
+#if ORIGINAL
+ printf("Invalid new address!\n\r");
+#endif
+ return VL53L0X_ERROR_INVALID_PARAMS;
+ }
+ }
+ return status;
+}
+
+int VL53L0X::range_meas_int_continuous_mode(void (*fptr)(void))
+{
+ int status, clr_status;
+
+ status = VL53L0X_stop_measurement(_device); // it is safer to do this while sensor is stopped
+
+// status = VL53L0X_SetInterruptThresholds(Device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING, 0, 300);
+
+ status = VL53L0X_set_gpio_config(_device, 0, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
+ VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
+ VL53L0X_INTERRUPTPOLARITY_HIGH);
+
+ if (!status) {
+ attach_interrupt_measure_detection_irq(fptr);
+ enable_interrupt_measure_detection_irq();
+ }
+
+ clr_status = clear_interrupt(VL53L0X_REG_RESULT_INTERRUPT_STATUS | VL53L0X_REG_RESULT_RANGE_STATUS);
+ if (clr_status) {
+ VL53L0X_ErrLog("VL53L0X_ClearErrorInterrupt fail\r\n");
+ }
+
+ if (!status) {
+ status = range_start_continuous_mode();
+ }
+ return status;
+}
+
+
+int VL53L0X::start_measurement(OperatingMode operating_mode, void (*fptr)(void))
+{
+ int Status = VL53L0X_ERROR_NONE;
+ int ClrStatus;
+
+ uint8_t VhvSettings;
+ uint8_t PhaseCal;
+ // *** from mass market cube expansion v1.1, ranging with satellites.
+ // default settings, for normal range.
+ FixPoint1616_t signalLimit = (FixPoint1616_t)(0.25 * 65536);
+ FixPoint1616_t sigmaLimit = (FixPoint1616_t)(18 * 65536);
+ uint32_t timingBudget = 33000;
+ uint8_t preRangeVcselPeriod = 14;
+ uint8_t finalRangeVcselPeriod = 10;
+
+ if (operating_mode == range_continuous_interrupt) {
+ if (_gpio1Int == NULL) {
+ printf("GPIO1 Error\r\n");
+ return 1;
+ }
+
+ Status = VL53L0X_stop_measurement(_device); // it is safer to do this while sensor is stopped
+
+// Status = VL53L0X_SetInterruptThresholds(Device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING, 0, 300);
+
+ Status = VL53L0X_set_gpio_config(_device, 0, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
+ VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY,
+ VL53L0X_INTERRUPTPOLARITY_HIGH);
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ attach_interrupt_measure_detection_irq(fptr);
+ enable_interrupt_measure_detection_irq();
+ }
+
+ ClrStatus = clear_interrupt(VL53L0X_REG_RESULT_INTERRUPT_STATUS | VL53L0X_REG_RESULT_RANGE_STATUS);
+ if (ClrStatus) {
+ VL53L0X_ErrLog("VL53L0X_ClearErrorInterrupt fail\r\n");
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING); // Setup in continuous ranging mode
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_start_measurement(_device);
+ }
+ }
+
+ if (operating_mode == range_single_shot_polling) {
+ // singelshot, polled ranging
+ if (Status == VL53L0X_ERROR_NONE) {
+ // no need to do this when we use VL53L0X_PerformSingleRangingMeasurement
+ Status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_SINGLE_RANGING); // Setup in single ranging mode
+ }
+
+ // Enable/Disable Sigma and Signal check
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_limit_check_enable(_device,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, 1);
+ }
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_limit_check_enable(_device,
+ VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE, 1);
+ }
+
+// *** from mass market cube expansion v1.1, ranging with satellites.
+#if ORIGINAL
+ /* Ranging configuration */
+//*
+// switch(rangingConfig) {
+// case LONG_RANGE:
+ signalLimit = (FixPoint1616_t)(0.1 * 65536);
+ sigmaLimit = (FixPoint1616_t)(60 * 65536);
+ timingBudget = 33000;
+ preRangeVcselPeriod = 18;
+ finalRangeVcselPeriod = 14;
+ /* break;
+ case HIGH_ACCURACY:
+ signalLimit = (FixPoint1616_t)(0.25*65536);
+ sigmaLimit = (FixPoint1616_t)(18*65536);
+ timingBudget = 200000;
+ preRangeVcselPeriod = 14;
+ finalRangeVcselPeriod = 10;
+ break;
+ case HIGH_SPEED:
+ signalLimit = (FixPoint1616_t)(0.25*65536);
+ sigmaLimit = (FixPoint1616_t)(32*65536);
+ timingBudget = 20000;
+ preRangeVcselPeriod = 14;
+ finalRangeVcselPeriod = 10;
+ break;
+ default:
+ debug_printf("Not Supported");
+ }
+ */
+#else
+ /* Ranging configuration */
+ switch(_range_mode) {
+ case range_hi_accurate_200ms_120cm:
+ signalLimit = (FixPoint1616_t)(0.25*65536);
+ sigmaLimit = (FixPoint1616_t)(18*65536);
+ timingBudget = 200000;
+ preRangeVcselPeriod = 14;
+ finalRangeVcselPeriod = 10;
+ break;
+ case range_hi_speed_20ms_120cm:
+ signalLimit = (FixPoint1616_t)(0.25*65536);
+ sigmaLimit = (FixPoint1616_t)(32*65536);
+ timingBudget = 20000;
+ preRangeVcselPeriod = 14;
+ finalRangeVcselPeriod = 10;
+ break;
+ case range_long_distance_33ms_200cm:
+ default:
+ signalLimit = (FixPoint1616_t)(0.1 * 65536);
+ sigmaLimit = (FixPoint1616_t)(60 * 65536);
+ timingBudget = 33000;
+ preRangeVcselPeriod = 18;
+ finalRangeVcselPeriod = 14;
+ }
+#endif
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_limit_check_value(_device,
+ VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE, signalLimit);
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_limit_check_value(_device,
+ VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE, sigmaLimit);
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_measurement_timing_budget_micro_seconds(_device, timingBudget);
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_vcsel_pulse_period(_device,
+ VL53L0X_VCSEL_PERIOD_PRE_RANGE, preRangeVcselPeriod);
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_set_vcsel_pulse_period(_device,
+ VL53L0X_VCSEL_PERIOD_FINAL_RANGE, finalRangeVcselPeriod);
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_perform_ref_calibration(_device, &VhvSettings, &PhaseCal);
+ }
+
+ }
+
+ if (operating_mode == range_continuous_polling) {
+ if (Status == VL53L0X_ERROR_NONE) {
+ //printf("Call of VL53L0X_SetDeviceMode\n");
+ Status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING); // Setup in continuous ranging mode
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ //printf("Call of VL53L0X_StartMeasurement\n");
+ Status = VL53L0X_start_measurement(_device);
+ }
+ }
+
+ return Status;
+}
+
+
+int VL53L0X::get_measurement(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *p_data)
+{
+ int Status = VL53L0X_ERROR_NONE;
+
+ if (operating_mode == range_single_shot_polling) {
+ Status = VL53L0X_perform_single_ranging_measurement(_device, p_data);
+ }
+
+ if (operating_mode == range_continuous_polling) {
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_measurement_poll_for_completion(_device);
+ }
+
+ if (Status == VL53L0X_ERROR_NONE) {
+ Status = VL53L0X_get_ranging_measurement_data(_device, p_data);
+
+ // Clear the interrupt
+ VL53L0X_clear_interrupt_mask(_device, VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY);
+ VL53L0X_polling_delay(_device);
+ }
+ }
+
+ if (operating_mode == range_continuous_interrupt) {
+ Status = VL53L0X_get_ranging_measurement_data(_device, p_data);
+ VL53L0X_clear_interrupt_mask(_device, VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR | VL53L0X_REG_RESULT_INTERRUPT_STATUS);
+ }
+
+ return Status;
+}
+
+
+int VL53L0X::stop_measurement(OperatingMode operating_mode)
+{
+ int status = VL53L0X_ERROR_NONE;
+
+
+ // don't need to stop for a singleshot range!
+ if (operating_mode == range_single_shot_polling) {
+ }
+
+ if (operating_mode == range_continuous_interrupt || operating_mode == range_continuous_polling) {
+ // continuous mode
+ if (status == VL53L0X_ERROR_NONE) {
+ //printf("Call of VL53L0X_StopMeasurement\n");
+ status = VL53L0X_stop_measurement(_device);
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ //printf("Wait Stop to be competed\n");
+ status = wait_stop_completed(_device);
+ }
+
+ if (status == VL53L0X_ERROR_NONE)
+ status = VL53L0X_clear_interrupt_mask(_device,
+ VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY);
+ }
+
+ return status;
+}
+
+
+int VL53L0X::handle_irq(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *data)
+{
+ int status;
+ status = get_measurement(operating_mode, data);
+ enable_interrupt_measure_detection_irq();
+ return status;
+}
+
+
+/******************************************************************************/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,414 @@
+/*******************************************************************************
+ Copyright © 2016, STMicroelectronics International N.V.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+ IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+#ifndef __VL53L0X_CLASS_H
+#define __VL53L0X_CLASS_H
+
+//------- Feburary 6th, 2018 by JH1PJL / K.Arai --------------------------------
+//ORIGINAL=1 does NOT mean anything but just keep original source code as it is!
+//You can NOT compile with ORIGINAL=1 !!
+#define ORIGINAL 0 // Just keep = 0
+#define USE_I2C_2V8
+//------------------------------------------------------------------------------
+
+#if ORIGINAL
+#ifdef _MSC_VER
+# ifdef VL53L0X_API_EXPORTS
+# define VL53L0X_API __declspec(dllexport)
+# else
+# define VL53L0X_API
+# endif
+#else
+# define VL53L0X_API
+#endif
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "mbed.h"
+#if ORIGINAL
+#include "RangeSensor.h"
+#include "DevI2C.h"
+#include "PinNames.h"
+#endif
+#include "VL53L0X_def.h"
+#include "VL53L0X_platform.h"
+#if ORIGINAL
+#include "Stmpe1600.h"
+#endif
+
+#if !ORIGINAL
+//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
+// moved to following header file
+#include "VL53L0X_1st.h"
+//------------------------------------------------------------------------------
+#endif
+
+/* sensor operating modes */
+typedef enum {
+ range_single_shot_polling = 1,
+ range_continuous_polling,
+ range_continuous_interrupt,
+ range_continuous_polling_low_threshold,
+ range_continuous_polling_high_threshold,
+ range_continuous_polling_out_of_window,
+ range_continuous_interrupt_low_threshold,
+ range_continuous_interrupt_high_threshold,
+ range_continuous_interrupt_out_of_window,
+} OperatingMode;
+
+#if !ORIGINAL
+/* sensor range profiles */
+typedef enum {
+ range_long_distance_33ms_200cm = 1,
+ range_hi_accurate_200ms_120cm,
+ range_hi_speed_20ms_120cm,
+} RangeProfile;
+#endif
+
+/** default device address */
+#if ORIGINAL
+#define VL53L0X_DEFAULT_ADDRESS 0x52 /* (8-bit) */
+#else
+// No other choice
+#define VL53L0X_DEFAULT_ADDRESS 0x52 // 8-bit(0x53/Read & 0x52?Write) 0x29(7bit)
+#endif
+
+#if !ORIGINAL
+#if (MBED_MAJOR_VERSION == 2)
+#define WAIT_MS(x) wait_ms(x)
+#define VL53L0X_OsDelay(...) wait_ms(2)
+#elif (MBED_MAJOR_VERSION == 5)
+#define WAIT_MS(x) Thread::wait(x)
+#define VL53L0X_OsDelay(...) Thread::wait(2)
+#else
+#warning "I cannot control wait_ms()!!"
+#endif
+#endif // !ORIGINAL
+
+#if !ORIGINAL
+
+//--------------- Simple debug -------------------------------------------------
+//extern DigitalOut myled;
+//------------------------------------------------------------------------------
+
+/** Interface for STMicronics VL53L0X
+ * World smallest Time-of-Flight (ToF) ranging sensor
+ *
+ * @code
+ * #include "mbed.h"
+ *
+ * // I2C Communication
+ * VL53L0X sensor(I2C_SDA, I2C_SCL, D8); // SDA, SCL & XSHUT
+ * // If you connected I2C line not only this device but also other devices,
+ * // you need to declare following method.
+ * I2C i2c(I2C_SDA, I2C_SCL);
+ * VL53L0X sensor(i2c, D8); // I2C, XSHUT
+ *
+ * int main()
+ * {
+ * int status = VL53L0X_ERROR_NONE;
+ * uint32_t data;
+ *
+ * status = sensor.init_sensor(0x33<<1U); //new addres(not equal others)
+ * status = sensor.set_mode(range_long_distance_33ms_200cm);
+ * //status = sensor.set_mode(range_hi_accurate_200ms_120cm);
+ * //status = sensor.set_mode(range_hi_speed_20ms_120cm);
+ * while (true) {
+ * status = sensor.get_distance(&data);
+ * if (status == VL53L0X_ERROR_NONE) {
+ * printf("%5d\r\n", data);
+ * } else {
+ * printf("error\r\n");
+ * }
+ * }
+ * }
+ * @endcode
+ */
+
+
+/* Classes -------------------------------------------------------------------*/
+/** Class representing a VL53L0 sensor component
+ */
+class VL53L0X
+{
+public:
+ /** Constructor
+ * @param[in] &i2c device I2C to be used for communication
+ * @param[in] pin Mbed DigitalInOut PinName to be used for XSHUT
+ * @param[in] &pin_gpio1 pin Mbed InterruptIn PinName
+ * to be used as component GPIO_1 INT
+ */
+ VL53L0X(I2C& i2c, PinName xshut, PinName pin_gpio1) : _i2c(i2c),
+ _gpio0(xshut)
+ {
+ if (pin_gpio1 != NC) {
+ _gpio1Int = new InterruptIn(pin_gpio1);
+ } else {
+ _gpio1Int = NULL;
+ }
+ preparation();
+ }
+
+ /** Constructor 2 (another simple way)
+ * @param[in] Pin for I2C SDA & SDL
+ * @param[in] pin Mbed DigitalInOut PinName to be used for XSHUT
+ */
+ VL53L0X(PinName p_sda, PinName p_scl, PinName xshut)
+ : _i2c_p(new I2C(p_sda, p_scl)), _i2c(*_i2c_p), _gpio0(xshut) {
+ _gpio1Int = NULL;
+ preparation();
+ }
+
+ /** Constructor 3 (another simple way)
+ * @param[in] &i2c device I2C to be used for communication
+ * @param[in] pin Mbed DigitalInOut PinName to be used for XSHUT
+ */
+ VL53L0X(I2C& p_i2c, PinName xshut) : _i2c(p_i2c), _gpio0(xshut) {
+ _gpio1Int = NULL;
+ preparation();
+ }
+
+ /** Destructor
+ */
+ virtual ~VL53L0X()
+ {
+ if (_gpio1Int != NULL) {
+ delete _gpio1Int;
+ }
+ }
+#else
+#warning "please recover original constractor form VL53L0X_header_original.txt"
+#endif
+
+ /*** Interface Methods ***/
+ /*** High level API ***/
+#if !ORIGINAL
+ /**
+ * @brief initialize
+ * @return void
+ */
+ /* turns on the sensor */
+ void preparation(void)
+ {
+ _my_device.I2cDevAddr = VL53L0X_DEFAULT_ADDRESS;
+ _my_device.comms_type = 1; // VL53L0X_COMMS_I2C
+ _my_device.comms_speed_khz = 400;
+ _device = &_my_device;
+ _range_mode = range_long_distance_33ms_200cm;
+ VL53L0X_off();
+ }
+#endif
+
+ /**
+ * @brief PowerOn the sensor
+ * @return void
+ */
+ /* turns on the sensor */
+ void VL53L0X_on(void)
+ {
+#if ORIGINAL
+ if (_gpio0) {
+ *_gpio0 = 1;
+ } else {
+ if (_expgpio0) {
+ *_expgpio0 = 1;
+ }
+ }
+ wait_ms(10);
+#else
+ _gpio0.output();
+ _gpio0 = 1;
+ _gpio0.input();
+ WAIT_MS(1);
+#endif
+ }
+
+ /**
+ * @brief PowerOff the sensor
+ * @return void
+ */
+ /* turns off the sensor */
+ void VL53L0X_off(void)
+ {
+#if ORIGINAL
+ if (_gpio0) {
+ *_gpio0 = 0;
+ } else {
+ if (_expgpio0) {
+ *_expgpio0 = 0;
+ }
+ }
+ wait_ms(10);
+#else
+ _gpio0 = 0;
+ _gpio0.output();
+ WAIT_MS(10);
+#endif
+ }
+
+ /**
+ * @brief Initialize the sensor with default values
+ * @param[in] new I2C address
+ * @return "0" on success
+ */
+ int init_sensor(uint8_t new_addr);
+
+#if !ORIGINAL
+ /**
+ * @brief Start the measure by single shot operating mode
+ * @param[in] operating mode
+ * @return "0" on success
+ */
+ int set_mode(RangeProfile range_mode) {
+ _range_mode = range_mode;
+ return start_measurement(range_single_shot_polling, NULL);
+ }
+
+ /**
+ * @brief Get ranging result and only that
+ *
+ * @par Function Description
+ * Unlike @a VL53L0X_get_ranging_measurement_data()
+ * this function only retrieves the range in millimeter \n
+ * It does any required up-scale translation\n
+ * It can be called after success status polling or in interrupt mode \n
+ * @warning these function is not doing wrap around filtering \n
+ * This function doesn't perform any data ready check!
+ *
+ * @param p_data Pointer to range distance
+ * @return "0" on success
+ */
+ virtual int get_distance(uint32_t *p_data)
+ {
+ int status = 0;
+ VL53L0X_RangingMeasurementData_t p_ranging_measurement_data;
+
+#if ORIGINAL
+ status = start_measurement(range_single_shot_polling, NULL);
+#else
+ status = VL53L0X_start_measurement(_device);
+#endif
+ if (!status) {
+ status = get_measurement(range_single_shot_polling,
+ &p_ranging_measurement_data);
+ }
+ if (p_ranging_measurement_data.RangeStatus == 0) {
+ // we have a valid range.
+ *p_data = p_ranging_measurement_data.RangeMilliMeter;
+ } else {
+ *p_data = 0;
+ status = VL53L0X_ERROR_RANGE_ERROR;
+ }
+ stop_measurement(range_single_shot_polling);
+ return status;
+ }
+#endif
+
+#if !ORIGINAL
+//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
+// moved to following header file
+#include "VL53L0X_2nd.h"
+//------------------------------------------------------------------------------
+#else
+#warning "please recover original functions form VL53L0X_2nd.h"
+#endif
+
+private:
+
+#if !ORIGINAL
+//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
+// moved to following header file
+#include "VL53L0X_3rd.h"
+//------------------------------------------------------------------------------
+#else
+#warning "please recover original functions form VL53L0X_3rd.h"
+#endif
+#if !ORIGINAL
+ static const unsigned int TEMP_BUF_SIZE = 32;
+
+ int i2c_write(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr,
+ uint16_t NumByteToWrite) {
+ int ret;
+ uint8_t tmp[TEMP_BUF_SIZE];
+
+ if(NumByteToWrite >= TEMP_BUF_SIZE) return -2;
+ /* First, send device address. Then, send data and STOP condition */
+ tmp[0] = RegisterAddr;
+ memcpy(tmp+1, pBuffer, NumByteToWrite);
+ ret = _i2c.write(DeviceAddr, (const char*)tmp, NumByteToWrite+1, false);
+ if(ret) return -1;
+ return 0;
+ }
+
+ int i2c_read(uint8_t* pBuffer, uint8_t DeviceAddr, uint8_t RegisterAddr,
+ uint16_t NumByteToRead) {
+ int ret;
+
+ //--debug--
+ //myled = 1;
+ /* Send device address, with no STOP condition */
+ ret = _i2c.write(DeviceAddr, (const char*)&RegisterAddr, 1, true);
+ //--debug--
+ //myled = 0;
+ if(!ret) {
+ /* Read data, with STOP condition */
+ ret = _i2c.read(DeviceAddr, (char*)pBuffer, NumByteToRead, false);
+ }
+ if(ret) return -1;
+ return 0;
+ }
+#endif
+
+ VL53L0X_DeviceInfo_t _device_info;
+
+#if !ORIGINAL
+ RangeProfile _range_mode;
+#endif
+
+#if ORIGINAL
+ /* IO Device */
+ DevI2C *_dev_i2c;
+ /* Digital out pin */
+ DigitalOut *_gpio0;
+ /* GPIO expander */
+ Stmpe1600DigiOut *_expgpio0;
+#else
+ /* IO Device */
+ I2C *_i2c_p;
+ I2C &_i2c;
+ /* Digital in and out pin */
+ DigitalInOut _gpio0;
+#endif
+ /* Measure detection IRQ */
+ InterruptIn *_gpio1Int;
+ /* Device data */
+ VL53L0X_Dev_t _my_device;
+ VL53L0X_DEV _device;
+};
+
+#endif /* _VL53L0X_CLASS_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/VL53L0X_simple/VL53L0X_1st.h Mon Mar 18 22:45:39 2019 +0000 @@ -0,0 +1,221 @@ + +/** + * The device model ID + */ +#define IDENTIFICATION_MODEL_ID 0x000 + + +#define STATUS_OK 0x00 +#define STATUS_FAIL 0x01 + +#if ORIGINAL +#define VL53L0X_OsDelay(...) wait_ms(2) // 2 msec delay. can also use wait(float secs)/wait_us(int) +#endif + +#ifdef USE_EMPTY_STRING +#define VL53L0X_STRING_DEVICE_INFO_NAME "" +#define VL53L0X_STRING_DEVICE_INFO_NAME_TS0 "" +#define VL53L0X_STRING_DEVICE_INFO_NAME_TS1 "" +#define VL53L0X_STRING_DEVICE_INFO_NAME_TS2 "" +#define VL53L0X_STRING_DEVICE_INFO_NAME_ES1 "" +#define VL53L0X_STRING_DEVICE_INFO_TYPE "" + +/* PAL ERROR strings */ +#define VL53L0X_STRING_ERROR_NONE "" +#define VL53L0X_STRING_ERROR_CALIBRATION_WARNING "" +#define VL53L0X_STRING_ERROR_MIN_CLIPPED "" +#define VL53L0X_STRING_ERROR_UNDEFINED "" +#define VL53L0X_STRING_ERROR_INVALID_PARAMS "" +#define VL53L0X_STRING_ERROR_NOT_SUPPORTED "" +#define VL53L0X_STRING_ERROR_RANGE_ERROR "" +#define VL53L0X_STRING_ERROR_TIME_OUT "" +#define VL53L0X_STRING_ERROR_MODE_NOT_SUPPORTED "" +#define VL53L0X_STRING_ERROR_BUFFER_TOO_SMALL "" +#define VL53L0X_STRING_ERROR_GPIO_NOT_EXISTING "" +#define VL53L0X_STRING_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED "" +#define VL53L0X_STRING_ERROR_CONTROL_INTERFACE "" +#define VL53L0X_STRING_ERROR_INVALID_COMMAND "" +#define VL53L0X_STRING_ERROR_DIVISION_BY_ZERO "" +#define VL53L0X_STRING_ERROR_REF_SPAD_INIT "" +#define VL53L0X_STRING_ERROR_NOT_IMPLEMENTED "" + +#define VL53L0X_STRING_UNKNOW_ERROR_CODE "" + + + +/* Range Status */ +#define VL53L0X_STRING_RANGESTATUS_NONE "" +#define VL53L0X_STRING_RANGESTATUS_RANGEVALID "" +#define VL53L0X_STRING_RANGESTATUS_SIGMA "" +#define VL53L0X_STRING_RANGESTATUS_SIGNAL "" +#define VL53L0X_STRING_RANGESTATUS_MINRANGE "" +#define VL53L0X_STRING_RANGESTATUS_PHASE "" +#define VL53L0X_STRING_RANGESTATUS_HW "" + + +/* Range Status */ +#define VL53L0X_STRING_STATE_POWERDOWN "" +#define VL53L0X_STRING_STATE_WAIT_STATICINIT "" +#define VL53L0X_STRING_STATE_STANDBY "" +#define VL53L0X_STRING_STATE_IDLE "" +#define VL53L0X_STRING_STATE_RUNNING "" +#define VL53L0X_STRING_STATE_UNKNOWN "" +#define VL53L0X_STRING_STATE_ERROR "" + + +/* Device Specific */ +#define VL53L0X_STRING_DEVICEERROR_NONE "" +#define VL53L0X_STRING_DEVICEERROR_VCSELCONTINUITYTESTFAILURE "" +#define VL53L0X_STRING_DEVICEERROR_VCSELWATCHDOGTESTFAILURE "" +#define VL53L0X_STRING_DEVICEERROR_NOVHVVALUEFOUND "" +#define VL53L0X_STRING_DEVICEERROR_MSRCNOTARGET "" +#define VL53L0X_STRING_DEVICEERROR_SNRCHECK "" +#define VL53L0X_STRING_DEVICEERROR_RANGEPHASECHECK "" +#define VL53L0X_STRING_DEVICEERROR_SIGMATHRESHOLDCHECK "" +#define VL53L0X_STRING_DEVICEERROR_TCC "" +#define VL53L0X_STRING_DEVICEERROR_PHASECONSISTENCY "" +#define VL53L0X_STRING_DEVICEERROR_MINCLIP "" +#define VL53L0X_STRING_DEVICEERROR_RANGECOMPLETE "" +#define VL53L0X_STRING_DEVICEERROR_ALGOUNDERFLOW "" +#define VL53L0X_STRING_DEVICEERROR_ALGOOVERFLOW "" +#define VL53L0X_STRING_DEVICEERROR_RANGEIGNORETHRESHOLD "" +#define VL53L0X_STRING_DEVICEERROR_UNKNOWN "" + +/* Check Enable */ +#define VL53L0X_STRING_CHECKENABLE_SIGMA_FINAL_RANGE "" +#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE "" +#define VL53L0X_STRING_CHECKENABLE_SIGNAL_REF_CLIP "" +#define VL53L0X_STRING_CHECKENABLE_RANGE_IGNORE_THRESHOLD "" + +/* Sequence Step */ +#define VL53L0X_STRING_SEQUENCESTEP_TCC "" +#define VL53L0X_STRING_SEQUENCESTEP_DSS "" +#define VL53L0X_STRING_SEQUENCESTEP_MSRC "" +#define VL53L0X_STRING_SEQUENCESTEP_PRE_RANGE "" +#define VL53L0X_STRING_SEQUENCESTEP_FINAL_RANGE "" +#else +#define VL53L0X_STRING_DEVICE_INFO_NAME "VL53L0X cut1.0" +#define VL53L0X_STRING_DEVICE_INFO_NAME_TS0 "VL53L0X TS0" +#define VL53L0X_STRING_DEVICE_INFO_NAME_TS1 "VL53L0X TS1" +#define VL53L0X_STRING_DEVICE_INFO_NAME_TS2 "VL53L0X TS2" +#define VL53L0X_STRING_DEVICE_INFO_NAME_ES1 "VL53L0X ES1 or later" +#define VL53L0X_STRING_DEVICE_INFO_TYPE "VL53L0X" + +/* PAL ERROR strings */ +#define VL53L0X_STRING_ERROR_NONE \ + "No Error" +#define VL53L0X_STRING_ERROR_CALIBRATION_WARNING \ + "Calibration Warning Error" +#define VL53L0X_STRING_ERROR_MIN_CLIPPED \ + "Min clipped error" +#define VL53L0X_STRING_ERROR_UNDEFINED \ + "Undefined error" +#define VL53L0X_STRING_ERROR_INVALID_PARAMS \ + "Invalid parameters error" +#define VL53L0X_STRING_ERROR_NOT_SUPPORTED \ + "Not supported error" +#define VL53L0X_STRING_ERROR_RANGE_ERROR \ + "Range error" +#define VL53L0X_STRING_ERROR_TIME_OUT \ + "Time out error" +#define VL53L0X_STRING_ERROR_MODE_NOT_SUPPORTED \ + "Mode not supported error" +#define VL53L0X_STRING_ERROR_BUFFER_TOO_SMALL \ + "Buffer too small" +#define VL53L0X_STRING_ERROR_GPIO_NOT_EXISTING \ + "GPIO not existing" +#define VL53L0X_STRING_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED \ + "GPIO funct not supported" +#define VL53L0X_STRING_ERROR_INTERRUPT_NOT_CLEARED \ + "Interrupt not Cleared" +#define VL53L0X_STRING_ERROR_CONTROL_INTERFACE \ + "Control Interface Error" +#define VL53L0X_STRING_ERROR_INVALID_COMMAND \ + "Invalid Command Error" +#define VL53L0X_STRING_ERROR_DIVISION_BY_ZERO \ + "Division by zero Error" +#define VL53L0X_STRING_ERROR_REF_SPAD_INIT \ + "Reference Spad Init Error" +#define VL53L0X_STRING_ERROR_NOT_IMPLEMENTED \ + "Not implemented error" + +#define VL53L0X_STRING_UNKNOW_ERROR_CODE \ + "Unknown Error Code" + + + +/* Range Status */ +#define VL53L0X_STRING_RANGESTATUS_NONE "No Update" +#define VL53L0X_STRING_RANGESTATUS_RANGEVALID "Range Valid" +#define VL53L0X_STRING_RANGESTATUS_SIGMA "Sigma Fail" +#define VL53L0X_STRING_RANGESTATUS_SIGNAL "Signal Fail" +#define VL53L0X_STRING_RANGESTATUS_MINRANGE "Min Range Fail" +#define VL53L0X_STRING_RANGESTATUS_PHASE "Phase Fail" +#define VL53L0X_STRING_RANGESTATUS_HW "Hardware Fail" + + +/* Range Status */ +#define VL53L0X_STRING_STATE_POWERDOWN "POWERDOWN State" +#define VL53L0X_STRING_STATE_WAIT_STATICINIT \ + "Wait for staticinit State" +#define VL53L0X_STRING_STATE_STANDBY "STANDBY State" +#define VL53L0X_STRING_STATE_IDLE "IDLE State" +#define VL53L0X_STRING_STATE_RUNNING "RUNNING State" +#define VL53L0X_STRING_STATE_UNKNOWN "UNKNOWN State" +#define VL53L0X_STRING_STATE_ERROR "ERROR State" + + +/* Device Specific */ +#define VL53L0X_STRING_DEVICEERROR_NONE "No Update" +#define VL53L0X_STRING_DEVICEERROR_VCSELCONTINUITYTESTFAILURE \ + "VCSEL Continuity Test Failure" +#define VL53L0X_STRING_DEVICEERROR_VCSELWATCHDOGTESTFAILURE \ + "VCSEL Watchdog Test Failure" +#define VL53L0X_STRING_DEVICEERROR_NOVHVVALUEFOUND \ + "No VHV Value found" +#define VL53L0X_STRING_DEVICEERROR_MSRCNOTARGET \ + "MSRC No Target Error" +#define VL53L0X_STRING_DEVICEERROR_SNRCHECK \ + "SNR Check Exit" +#define VL53L0X_STRING_DEVICEERROR_RANGEPHASECHECK \ + "Range Phase Check Error" +#define VL53L0X_STRING_DEVICEERROR_SIGMATHRESHOLDCHECK \ + "Sigma Threshold Check Error" +#define VL53L0X_STRING_DEVICEERROR_TCC \ + "TCC Error" +#define VL53L0X_STRING_DEVICEERROR_PHASECONSISTENCY \ + "Phase Consistency Error" +#define VL53L0X_STRING_DEVICEERROR_MINCLIP \ + "Min Clip Error" +#define VL53L0X_STRING_DEVICEERROR_RANGECOMPLETE \ + "Range Complete" +#define VL53L0X_STRING_DEVICEERROR_ALGOUNDERFLOW \ + "Range Algo Underflow Error" +#define VL53L0X_STRING_DEVICEERROR_ALGOOVERFLOW \ + "Range Algo Overlow Error" +#define VL53L0X_STRING_DEVICEERROR_RANGEIGNORETHRESHOLD \ + "Range Ignore Threshold Error" +#define VL53L0X_STRING_DEVICEERROR_UNKNOWN \ + "Unknown error code" + +/* Check Enable */ +#define VL53L0X_STRING_CHECKENABLE_SIGMA_FINAL_RANGE \ + "SIGMA FINAL RANGE" +#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE \ + "SIGNAL RATE FINAL RANGE" +#define VL53L0X_STRING_CHECKENABLE_SIGNAL_REF_CLIP \ + "SIGNAL REF CLIP" +#define VL53L0X_STRING_CHECKENABLE_RANGE_IGNORE_THRESHOLD \ + "RANGE IGNORE THRESHOLD" +#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_MSRC \ + "SIGNAL RATE MSRC" +#define VL53L0X_STRING_CHECKENABLE_SIGNAL_RATE_PRE_RANGE \ + "SIGNAL RATE PRE RANGE" + +/* Sequence Step */ +#define VL53L0X_STRING_SEQUENCESTEP_TCC "TCC" +#define VL53L0X_STRING_SEQUENCESTEP_DSS "DSS" +#define VL53L0X_STRING_SEQUENCESTEP_MSRC "MSRC" +#define VL53L0X_STRING_SEQUENCESTEP_PRE_RANGE "PRE RANGE" +#define VL53L0X_STRING_SEQUENCESTEP_FINAL_RANGE "FINAL RANGE" +#endif /* USE_EMPTY_STRING */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_2nd.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,1446 @@
+
+ /**
+ * @brief Start the measure indicated by operating mode
+ * @param[in] operating_mode specifies requested measure
+ * @param[in] fptr specifies call back function must be !NULL in case of interrupt measure
+ * @return "0" on success
+ */
+ int start_measurement(OperatingMode operating_mode, void (*fptr)(void));
+
+ /**
+ * @brief Get results for the measure indicated by operating mode
+ * @param[in] operating_mode specifies requested measure results
+ * @param[out] p_data pointer to the MeasureData_t structure to read data in to
+ * @return "0" on success
+ */
+ int get_measurement(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *p_data);
+
+ /**
+ * @brief Stop the currently running measure indicate by operating_mode
+ * @param[in] operating_mode specifies requested measure to stop
+ * @return "0" on success
+ */
+ int stop_measurement(OperatingMode operating_mode);
+
+ /**
+ * @brief Interrupt handling func to be called by user after an INT is occourred
+ * @param[in] opeating_mode indicating the in progress measure
+ * @param[out] Data pointer to the MeasureData_t structure to read data in to
+ * @return "0" on success
+ */
+ int handle_irq(OperatingMode operating_mode, VL53L0X_RangingMeasurementData_t *data);
+
+ /**
+ * @brief Enable interrupt measure IRQ
+ * @return "0" on success
+ */
+ void enable_interrupt_measure_detection_irq(void)
+ {
+ if (_gpio1Int != NULL) {
+ _gpio1Int->enable_irq();
+ }
+ }
+
+ /**
+ * @brief Disable interrupt measure IRQ
+ * @return "0" on success
+ */
+ void disable_interrupt_measure_detection_irq(void)
+ {
+ if (_gpio1Int != NULL) {
+ _gpio1Int->disable_irq();
+ }
+ }
+
+ /**
+ * @brief Attach a function to call when an interrupt is detected, i.e. measurement is ready
+ * @param[in] fptr pointer to call back function to be called whenever an interrupt occours
+ * @return "0" on success
+ */
+ void attach_interrupt_measure_detection_irq(void (*fptr)(void))
+ {
+ if (_gpio1Int != NULL) {
+ _gpio1Int->rise(fptr);
+ }
+ }
+
+
+ /** Wrapper functions */
+ /** @defgroup api_init Init functions
+ * @brief API init functions
+ * @ingroup api_hl
+ * @{
+ */
+
+ /**
+ *
+ * @brief One time device initialization
+ *
+ * To be called once and only once after device is brought out of reset (Chip enable) and booted.
+ *
+ * @par Function Description
+ * When not used after a fresh device "power up" or reset, it may return @a #CALIBRATION_WARNING
+ * meaning wrong calibration data may have been fetched from device that can result in ranging offset error\n
+ * If application cannot execute device reset or need to run VL53L0X_data_init multiple time
+ * then it must ensure proper offset calibration saving and restore on its own
+ * by using @a VL53L0X_get_offset_calibration_data_micro_meter() on first power up and then @a VL53L0X_set_offset_calibration_data_micro_meter() all all subsequent init
+ *
+ * @param void
+ * @return "0" on success, @a #CALIBRATION_WARNING if failed
+ */
+ virtual int init(void *init)
+ {
+ return VL53L0X_data_init(_device);
+ }
+
+ /**
+ * @brief Prepare device for operation
+ * @par Function Description
+ * Does static initialization and reprogram common default settings \n
+ * Device is prepared for new measure, ready single shot ranging or ALS typical polling operation\n
+ * After prepare user can : \n
+ * @li Call other API function to set other settings\n
+ * @li Configure the interrupt pins, etc... \n
+ * @li Then start ranging or ALS operations in single shot or continuous mode
+ *
+ * @param void
+ * @return "0" on success
+ */
+ int prepare()
+ {
+ VL53L0X_Error status = VL53L0X_ERROR_NONE;
+ uint32_t ref_spad_count;
+ uint8_t is_aperture_spads;
+ uint8_t vhv_settings;
+ uint8_t phase_cal;
+
+ if (status == VL53L0X_ERROR_NONE) {
+ //printf("Call of VL53L0X_StaticInit\r\n");
+ status = VL53L0X_static_init(_device); // Device Initialization
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ //printf("Call of VL53L0X_PerformRefCalibration\r\n");
+ status = VL53L0X_perform_ref_calibration(_device,
+ &vhv_settings, &phase_cal); // Device Initialization
+ }
+
+ if (status == VL53L0X_ERROR_NONE) {
+ //printf("Call of VL53L0X_PerformRefSpadManagement\r\n");
+ status = VL53L0X_perform_ref_spad_management(_device,
+ &ref_spad_count, &is_aperture_spads); // Device Initialization
+// printf ("refSpadCount = %d, isApertureSpads = %d\r\n", refSpadCount, isApertureSpads);
+ }
+
+ return status;
+ }
+
+ /**
+ * @brief Start continuous ranging mode
+ *
+ * @details End user should ensure device is in idle state and not already running
+ * @return "0" on success
+ */
+ int range_start_continuous_mode()
+ {
+ int status;
+ status = VL53L0X_set_device_mode(_device, VL53L0X_DEVICEMODE_CONTINUOUS_RANGING);
+
+ if (status == VL53L0X_ERROR_NONE) {
+ //printf ("Call of VL53L0X_StartMeasurement\r\n");
+ status = VL53L0X_start_measurement(_device);
+ }
+
+ return status;
+ }
+
+//------- Feburary 4th, 2018 by JH1PJL / K.Arai --------------------------------
+#if ORIGINAL
+ /**
+ * @brief Get ranging result and only that
+ *
+ * @par Function Description
+ * Unlike @a VL53L0X_get_ranging_measurement_data() this function only retrieves the range in millimeter \n
+ * It does any required up-scale translation\n
+ * It can be called after success status polling or in interrupt mode \n
+ * @warning these function is not doing wrap around filtering \n
+ * This function doesn't perform any data ready check!
+ *
+ * @param p_data Pointer to range distance
+ * @return "0" on success
+ */
+ virtual int get_distance(uint32_t *p_data)
+ {
+ int status = 0;
+ VL53L0X_RangingMeasurementData_t p_ranging_measurement_data;
+
+ status = start_measurement(range_single_shot_polling, NULL);
+ if (!status) {
+ status = get_measurement(range_single_shot_polling, &p_ranging_measurement_data);
+ }
+ if (p_ranging_measurement_data.RangeStatus == 0) {
+ // we have a valid range.
+ *p_data = p_ranging_measurement_data.RangeMilliMeter;
+ } else {
+ *p_data = 0;
+ status = VL53L0X_ERROR_RANGE_ERROR;
+ }
+ stop_measurement(range_single_shot_polling);
+ return status;
+ }
+#endif
+
+ /** @} */
+
+ /**
+ * @brief Set new device i2c address
+ *
+ * After completion the device will answer to the new address programmed.
+ *
+ * @param new_addr The new i2c address (7bit)
+ * @return "0" on success
+ */
+ int set_device_address(int new_addr)
+ {
+ int status;
+
+ status = VL53L0X_set_device_address(_device, new_addr);
+ if (!status) {
+ _device->I2cDevAddr = new_addr;
+ }
+ return status;
+
+ }
+
+ /**
+ * @brief Clear given system interrupt condition
+ *
+ * @par Function Description
+ * Clear given interrupt cause by writing into register #SYSTEM_INTERRUPT_CLEAR register.
+ * @param dev The device
+ * @param int_clear Which interrupt source to clear. Use any combinations of #INTERRUPT_CLEAR_RANGING , #INTERRUPT_CLEAR_ALS , #INTERRUPT_CLEAR_ERROR.
+ * @return "0" on success
+ */
+ int clear_interrupt(uint8_t int_clear)
+ {
+ return VL53L0X_clear_interrupt_mask(_device, int_clear);
+ }
+
+ /**
+ *
+ * @brief Get the 53L0 device
+ *
+ * To be called to retrive the internal device descriptor to allow usage of
+ * low level API having device as parameter. To be called after set_device_address()
+ * (if any).
+ *
+ * @par Function Description
+ * To be called if low level API usage is needed as those functions requires
+ * device as a parameter.TICINIT.
+ *
+ * @note This function return a pointer to an object internal structure
+ *
+ * @param dev ptr to ptr to Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error vl53l0x_get_device(VL53L0X_DEV *dev)
+{
+ *dev = _device;
+ return VL53L0X_ERROR_NONE;
+}
+
+ /**
+ *
+ * @brief One time device initialization
+ *
+ * To be called once and only once after device is brought out of reset
+ * (Chip enable) and booted see @a VL53L0X_WaitDeviceBooted()
+ *
+ * @par Function Description
+ * When not used after a fresh device "power up" or reset, it may return
+ * @a #VL53L0X_ERROR_CALIBRATION_WARNING meaning wrong calibration data
+ * may have been fetched from device that can result in ranging offset error\n
+ * If application cannot execute device reset or need to run VL53L0X_DataInit
+ * multiple time then it must ensure proper offset calibration saving and
+ * restore on its own by using @a VL53L0X_GetOffsetCalibrationData() on first
+ * power up and then @a VL53L0X_SetOffsetCalibrationData() in all subsequent init
+ * This function will change the VL53L0X_State from VL53L0X_STATE_POWERDOWN to
+ * VL53L0X_STATE_WAIT_STATICINIT.
+ *
+ * @note This function accesses to the device
+ *
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_data_init(VL53L0X_DEV dev);
+
+ /**
+ * @brief Do basic device init (and eventually patch loading)
+ * This function will change the VL53L0X_State from
+ * VL53L0X_STATE_WAIT_STATICINIT to VL53L0X_STATE_IDLE.
+ * In this stage all default setting will be applied.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_static_init(VL53L0X_DEV dev);
+
+ /**
+ * @brief Perform Reference Calibration
+ *
+ * @details Perform a reference calibration of the Device.
+ * This function should be run from time to time before doing
+ * a ranging measurement.
+ * This function will launch a special ranging measurement, so
+ * if interrupt are enable an interrupt will be done.
+ * This function will clear the interrupt generated automatically.
+ *
+ * @warning This function is a blocking function
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_vhv_settings Pointer to vhv settings parameter.
+ * @param p_phase_cal Pointer to PhaseCal parameter.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_perform_ref_calibration(VL53L0X_DEV dev, uint8_t *p_vhv_settings,
+ uint8_t *p_phase_cal);
+
+ /**
+ * @brief Get Reference Calibration Parameters
+ *
+ * @par Function Description
+ * Get Reference Calibration Parameters.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_vhv_settings Pointer to VHV parameter
+ * @param p_phase_cal Pointer to PhaseCal Parameter
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_ref_calibration(VL53L0X_DEV dev,
+ uint8_t *p_vhv_settings, uint8_t *p_phase_cal);
+
+ VL53L0X_Error VL53L0X_set_ref_calibration(VL53L0X_DEV dev,
+ uint8_t vhv_settings, uint8_t phase_cal);
+
+ /**
+ * @brief Performs Reference Spad Management
+ *
+ * @par Function Description
+ * The reference SPAD initialization procedure determines the minimum amount
+ * of reference spads to be enables to achieve a target reference signal rate
+ * and should be performed once during initialization.
+ *
+ * @note This function Access to the device
+ *
+ * @note This function change the device mode to
+ * VL53L0X_DEVICEMODE_SINGLE_RANGING
+ *
+ * @param dev Device Handle
+ * @param ref_spad_count Reports ref Spad Count
+ * @param is_aperture_spads Reports if spads are of type
+ * aperture or non-aperture.
+ * 1:=aperture, 0:=Non-Aperture
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the Ref Spad procedure.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
+ uint32_t *ref_spad_count, uint8_t *is_aperture_spads);
+
+ /**
+ * @brief Applies Reference SPAD configuration
+ *
+ * @par Function Description
+ * This function applies a given number of reference spads, identified as
+ * either Aperture or Non-Aperture.
+ * The requested spad count and type are stored within the device specific
+ * parameters data for access by the host.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param refSpadCount Number of ref spads.
+ * @param is_aperture_spads Defines if spads are of type
+ * aperture or non-aperture.
+ * 1:=aperture, 0:=Non-Aperture
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the in the reference
+ * spad configuration.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_reference_spads(VL53L0X_DEV dev,
+ uint32_t refSpadCount, uint8_t is_aperture_spads);
+
+ /**
+ * @brief Retrieves SPAD configuration
+ *
+ * @par Function Description
+ * This function retrieves the current number of applied reference spads
+ * and also their type : Aperture or Non-Aperture.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_spad_count Number ref Spad Count
+ * @param p_is_aperture_spads Reports if spads are of type
+ * aperture or non-aperture.
+ * 1:=aperture, 0:=Non-Aperture
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the in the reference
+ * spad configuration.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_reference_spads(VL53L0X_DEV dev,
+ uint32_t *p_spad_count, uint8_t *p_is_aperture_spads);
+
+ /**
+ * @brief Get part to part calibration offset
+ *
+ * @par Function Description
+ * Should only be used after a successful call to @a VL53L0X_DataInit to backup
+ * device NVM value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_offset_calibration_data_micro_meter Return part to part
+ * calibration offset from device (microns)
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t *p_offset_calibration_data_micro_meter);
+ /**
+ * Set or over-hide part to part calibration offset
+ * \sa VL53L0X_DataInit() VL53L0X_GetOffsetCalibrationDataMicroMeter()
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_offset_calibration_data_micro_meter Offset (microns)
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t offset_calibration_data_micro_meter);
+
+ VL53L0X_Error VL53L0X_perform_offset_calibration(VL53L0X_DEV dev,
+ FixPoint1616_t cal_distance_milli_meter,
+ int32_t *p_offset_micro_meter);
+
+ VL53L0X_Error VL53L0X_perform_xtalk_calibration(VL53L0X_DEV dev,
+ FixPoint1616_t xtalk_cal_distance,
+ FixPoint1616_t *p_xtalk_compensation_rate_mega_cps);
+
+ /**
+ * @brief Perform XTalk Measurement
+ *
+ * @details Measures the current cross talk from glass in front
+ * of the sensor.
+ * This functions performs a histogram measurement and uses the results
+ * to measure the crosstalk. For the function to be successful, there
+ * must be no target in front of the sensor.
+ *
+ * @warning This function is a blocking function
+ *
+ * @warning This function is not supported when the final range
+ * vcsel clock period is set below 10 PCLKS.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param timeout_ms Histogram measurement duration.
+ * @param p_xtalk_per_spad Output parameter containing the crosstalk
+ * measurement result, in MCPS/Spad.
+ * Format fixpoint 16:16.
+ * @param p_ambient_too_high Output parameter which indicate that
+ * pXtalkPerSpad is not good if the Ambient
+ * is too high.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS vcsel clock period not supported
+ * for this operation.
+ * Must not be less than 10PCLKS.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_perform_xtalk_measurement(VL53L0X_DEV dev,
+ uint32_t timeout_ms, FixPoint1616_t *p_xtalk_per_spad,
+ uint8_t *p_ambient_too_high);
+
+ /**
+ * @brief Enable/Disable Cross talk compensation feature
+ *
+ * @note This function is not Implemented.
+ * Enable/Disable Cross Talk by set to zero the Cross Talk value
+ * by using @a VL53L0X_SetXTalkCompensationRateMegaCps().
+ *
+ * @param dev Device Handle
+ * @param x_talk_compensation_enable Cross talk compensation
+ * to be set 0=disabled else = enabled
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ */
+ VL53L0X_Error VL53L0X_set_x_talk_compensation_enable(VL53L0X_DEV dev,
+ uint8_t x_talk_compensation_enable);
+
+ /**
+ * @brief Get Cross talk compensation rate
+ *
+ * @note This function is not Implemented.
+ * Enable/Disable Cross Talk by set to zero the Cross Talk value by
+ * using @a VL53L0X_SetXTalkCompensationRateMegaCps().
+ *
+ * @param dev Device Handle
+ * @param p_x_talk_compensation_enable Pointer to the Cross talk compensation
+ * state 0=disabled or 1 = enabled
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ */
+ VL53L0X_Error VL53L0X_get_x_talk_compensation_enable(VL53L0X_DEV dev,
+ uint8_t *p_x_talk_compensation_enable);
+ /**
+ * @brief Set Cross talk compensation rate
+ *
+ * @par Function Description
+ * Set Cross talk compensation rate.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param x_talk_compensation_rate_mega_cps Compensation rate in
+ * Mega counts per second
+ * (16.16 fix point) see
+ * datasheet for details
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_x_talk_compensation_rate_mega_cps(VL53L0X_DEV dev,
+ FixPoint1616_t x_talk_compensation_rate_mega_cps);
+
+ /**
+ * @brief Get Cross talk compensation rate
+ *
+ * @par Function Description
+ * Get Cross talk compensation rate.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_xtalk_compensation_rate_mega_cps Pointer to Compensation rate
+ * in Mega counts per second
+ * (16.16 fix point) see
+ * datasheet for details
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_x_talk_compensation_rate_mega_cps(VL53L0X_DEV dev,
+ FixPoint1616_t *p_xtalk_compensation_rate_mega_cps);
+
+ /**
+ * @brief Set a new device mode
+ * @par Function Description
+ * Set device to a new mode (ranging, histogram ...)
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param device_mode New device mode to apply
+ * Valid values are:
+ * VL53L0X_DEVICEMODE_SINGLE_RANGING
+ * VL53L0X_DEVICEMODE_CONTINUOUS_RANGING
+ * VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING
+ * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
+ * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
+ * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
+ * VL53L0X_HISTOGRAMMODE_BOTH
+ *
+ *
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
+ * DeviceMode is not in the
+ * supported list
+ */
+ VL53L0X_Error VL53L0X_set_device_mode(VL53L0X_DEV dev, VL53L0X_DeviceModes device_mode);
+
+ /**
+ * @brief Get current new device mode
+ * @par Function Description
+ * Get actual mode of the device(ranging, histogram ...)
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_device_mode Pointer to current apply mode value
+ * Valid values are:
+ * VL53L0X_DEVICEMODE_SINGLE_RANGING
+ * VL53L0X_DEVICEMODE_CONTINUOUS_RANGING
+ * VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING
+ * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
+ * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
+ * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
+ * VL53L0X_HISTOGRAMMODE_BOTH
+ *
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
+ * DeviceMode is not in the
+ * supported list
+ */
+ VL53L0X_Error VL53L0X_get_device_mode(VL53L0X_DEV dev,
+ VL53L0X_DeviceModes *p_device_mode);
+
+ /**
+ * @brief Get current configuration for GPIO pin for a given device
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param pin ID of the GPIO Pin
+ * @param p_device_mode Pointer to Device Mode associated to the Gpio.
+ * @param p_functionality Pointer to Pin functionality.
+ * Refer to ::VL53L0X_GpioFunctionality
+ * @param p_polarity Pointer to interrupt polarity.
+ * Active high or active low see
+ * ::VL53L0X_InterruptPolarity
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_GPIO_NOT_EXISTING Only Pin=0 is accepted.
+ * @return VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED
+ * This error occurs
+ * when Funcionality programmed is not in the supported list:
+ * Supported value are:
+ * VL53L0X_GPIOFUNCTIONALITY_OFF,
+ * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW,
+ * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH,
+ * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT,
+ * VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_gpio_config(VL53L0X_DEV dev, uint8_t pin,
+ VL53L0X_DeviceModes *p_device_mode,
+ VL53L0X_GpioFunctionality *p_functionality,
+ VL53L0X_InterruptPolarity *p_polarity);
+
+ /**
+ * @brief Set the configuration of GPIO pin for a given device
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param pin ID of the GPIO Pin
+ * @param functionality Select Pin functionality.
+ * Refer to ::VL53L0X_GpioFunctionality
+ * @param device_mode Device Mode associated to the Gpio.
+ * @param polarity Set interrupt polarity. Active high
+ * or active low see ::VL53L0X_InterruptPolarity
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_GPIO_NOT_EXISTING Only Pin=0 is accepted.
+ * @return VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED This error occurs
+ * when Functionality programmed is not in the supported list:
+ * Supported value are:
+ * VL53L0X_GPIOFUNCTIONALITY_OFF,
+ * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW,
+ * VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH,
+ VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT,
+ * VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_gpio_config(VL53L0X_DEV dev, uint8_t pin,
+ VL53L0X_DeviceModes device_mode, VL53L0X_GpioFunctionality functionality,
+ VL53L0X_InterruptPolarity polarity);
+
+ /**
+ * @brief Start device measurement
+ *
+ * @details Started measurement will depend on device parameters set through
+ * @a VL53L0X_SetParameters()
+ * This is a non-blocking function.
+ * This function will change the VL53L0X_State from VL53L0X_STATE_IDLE to
+ * VL53L0X_STATE_RUNNING.
+ *
+ * @note This function Access to the device
+ *
+
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
+ * DeviceMode programmed with @a VL53L0X_SetDeviceMode is not in the supported
+ * list:
+ * Supported mode are:
+ * VL53L0X_DEVICEMODE_SINGLE_RANGING,
+ * VL53L0X_DEVICEMODE_CONTINUOUS_RANGING,
+ * VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING
+ * @return VL53L0X_ERROR_TIME_OUT Time out on start measurement
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_start_measurement(VL53L0X_DEV dev);
+
+ /**
+ * @brief Stop device measurement
+ *
+ * @details Will set the device in standby mode at end of current measurement\n
+ * Not necessary in single mode as device shall return automatically
+ * in standby mode at end of measurement.
+ * This function will change the VL53L0X_State from VL53L0X_STATE_RUNNING
+ * to VL53L0X_STATE_IDLE.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_stop_measurement(VL53L0X_DEV dev);
+
+ /**
+ * @brief Return device stop completion status
+ *
+ * @par Function Description
+ * Returns stop completiob status.
+ * User shall call this function after a stop command
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_stop_status Pointer to status variable to update
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_stop_completed_status(VL53L0X_DEV dev,
+ uint32_t *p_stop_status);
+
+ /**
+ * @brief Return Measurement Data Ready
+ *
+ * @par Function Description
+ * This function indicate that a measurement data is ready.
+ * This function check if interrupt mode is used then check is done accordingly.
+ * If perform function clear the interrupt, this function will not work,
+ * like in case of @a VL53L0X_PerformSingleRangingMeasurement().
+ * The previous function is blocking function, VL53L0X_GetMeasurementDataReady
+ * is used for non-blocking capture.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_measurement_data_ready Pointer to Measurement Data Ready.
+ * 0=data not ready, 1 = data ready
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_measurement_data_ready(VL53L0X_DEV dev,
+ uint8_t *p_measurement_data_ready);
+
+ /**
+ * @brief Retrieve the measurements from device for a given setup
+ *
+ * @par Function Description
+ * Get data from last successful Ranging measurement
+ * @warning USER should take care about @a VL53L0X_GetNumberOfROIZones()
+ * before get data.
+ * PAL will fill a NumberOfROIZones times the corresponding data
+ * structure used in the measurement function.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_ranging_measurement_data Pointer to the data structure to fill up.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_ranging_measurement_data(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data);
+
+ /**
+ * @brief Clear given system interrupt condition
+ *
+ * @par Function Description
+ * Clear given interrupt(s).
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param interrupt_mask Mask of interrupts to clear
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INTERRUPT_NOT_CLEARED Cannot clear interrupts
+ *
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_clear_interrupt_mask(VL53L0X_DEV dev, uint32_t interrupt_mask);
+
+ /**
+ * @brief Return device interrupt status
+ *
+ * @par Function Description
+ * Returns currently raised interrupts by the device.
+ * User shall be able to activate/deactivate interrupts through
+ * @a VL53L0X_SetGpioConfig()
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_interrupt_mask_status Pointer to status variable to update
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_interrupt_mask_status(VL53L0X_DEV dev,
+ uint32_t *p_interrupt_mask_status);
+
+ /**
+ * @brief Performs a single ranging measurement and retrieve the ranging
+ * measurement data
+ *
+ * @par Function Description
+ * This function will change the device mode to VL53L0X_DEVICEMODE_SINGLE_RANGING
+ * with @a VL53L0X_SetDeviceMode(),
+ * It performs measurement with @a VL53L0X_PerformSingleMeasurement()
+ * It get data from last successful Ranging measurement with
+ * @a VL53L0X_GetRangingMeasurementData.
+ * Finally it clear the interrupt with @a VL53L0X_ClearInterruptMask().
+ *
+ * @note This function Access to the device
+ *
+ * @note This function change the device mode to
+ * VL53L0X_DEVICEMODE_SINGLE_RANGING
+ *
+ * @param dev Device Handle
+ * @param p_ranging_measurement_data Pointer to the data structure to fill up.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_perform_single_ranging_measurement(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data);
+
+ /**
+ * @brief Single shot measurement.
+ *
+ * @par Function Description
+ * Perform simple measurement sequence (Start measure, Wait measure to end,
+ * and returns when measurement is done).
+ * Once function returns, user can get valid data by calling
+ * VL53L0X_GetRangingMeasurement or VL53L0X_GetHistogramMeasurement
+ * depending on defined measurement mode
+ * User should Clear the interrupt in case this are enabled by using the
+ * function VL53L0X_ClearInterruptMask().
+ *
+ * @warning This function is a blocking function
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_perform_single_measurement(VL53L0X_DEV dev);
+
+ /**
+ * @brief Read current status of the error register for the selected device
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_device_error_status Pointer to current error code of the device
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_device_error_status(VL53L0X_DEV dev,
+ VL53L0X_DeviceError *p_device_error_status);
+
+ /**
+ * @brief Human readable error string for a given Error Code
+ *
+ * @note This function doesn't access to the device
+ *
+ * @param error_code The error code as stored on ::VL53L0X_DeviceError
+ * @param p_device_error_string The error string corresponding to the ErrorCode
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_device_error_string(
+ VL53L0X_DeviceError error_code, char *p_device_error_string);
+
+ /**
+ * @brief Human readable Range Status string for a given RangeStatus
+ *
+ * @note This function doesn't access to the device
+ *
+ * @param range_status The RangeStatus code as stored on
+ * @a VL53L0X_RangingMeasurementData_t
+ * @param p_range_status_string The returned RangeStatus string.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_range_status_string(uint8_t range_status,
+ char *p_range_status_string);
+
+ VL53L0X_Error VL53L0X_get_total_signal_rate(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ FixPoint1616_t *p_total_signal_rate_mcps);
+
+ VL53L0X_Error VL53L0X_get_total_xtalk_rate(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ FixPoint1616_t *p_total_xtalk_rate_mcps);
+
+ /**
+ * @brief Get Ranging Timing Budget in microseconds
+ *
+ * @par Function Description
+ * Returns the programmed the maximum time allowed by the user to the
+ * device to run a full ranging sequence for the current mode
+ * (ranging, histogram, ASL ...)
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_measurement_timing_budget_micro_seconds Max measurement time in
+ * microseconds.
+ * Valid values are:
+ * >= 17000 microsecs when wraparound enabled
+ * >= 12000 microsecs when wraparound disabled
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t *p_measurement_timing_budget_micro_seconds);
+
+ /**
+ * @brief Set Ranging Timing Budget in microseconds
+ *
+ * @par Function Description
+ * Defines the maximum time allowed by the user to the device to run a
+ * full ranging sequence for the current mode (ranging, histogram, ASL ...)
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param measurement_timing_budget_micro_seconds Max measurement time in
+ * microseconds.
+ * Valid values are:
+ * >= 17000 microsecs when wraparound enabled
+ * >= 12000 microsecs when wraparound disabled
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned if
+ MeasurementTimingBudgetMicroSeconds out of range
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t measurement_timing_budget_micro_seconds);
+
+ /**
+ * @brief Get specific limit check enable state
+ *
+ * @par Function Description
+ * This function get the enable state of a specific limit check.
+ * The limit check is identified with the LimitCheckId.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param limit_check_id Limit Check ID
+ * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
+ * @param p_limit_check_enable Pointer to the check limit enable
+ * value.
+ * if 1 the check limit
+ * corresponding to LimitCheckId is Enabled
+ * if 0 the check limit
+ * corresponding to LimitCheckId is disabled
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned
+ * when LimitCheckId value is out of range.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
+ uint8_t *p_limit_check_enable);
+
+ /**
+ * @brief Enable/Disable a specific limit check
+ *
+ * @par Function Description
+ * This function Enable/Disable a specific limit check.
+ * The limit check is identified with the LimitCheckId.
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param limit_check_id Limit Check ID
+ * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
+ * @param limit_check_enable if 1 the check limit
+ * corresponding to LimitCheckId is Enabled
+ * if 0 the check limit
+ * corresponding to LimitCheckId is disabled
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned
+ * when LimitCheckId value is out of range.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_limit_check_enable(VL53L0X_DEV dev, uint16_t limit_check_id,
+ uint8_t limit_check_enable);
+
+ /**
+ * @brief Get a specific limit check value
+ *
+ * @par Function Description
+ * This function get a specific limit check value from device then it updates
+ * internal values and check enables.
+ * The limit check is identified with the LimitCheckId.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param limit_check_id Limit Check ID
+ * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
+ * @param p_limit_check_value Pointer to Limit
+ * check Value for a given LimitCheckId.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned
+ * when LimitCheckId value is out of range.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
+ FixPoint1616_t *p_limit_check_value);
+
+ /**
+ * @brief Set a specific limit check value
+ *
+ * @par Function Description
+ * This function set a specific limit check value.
+ * The limit check is identified with the LimitCheckId.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param limit_check_id Limit Check ID
+ * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
+ * @param limit_check_value Limit check Value for a given
+ * LimitCheckId
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned when either
+ * LimitCheckId or LimitCheckValue value is out of range.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_limit_check_value(VL53L0X_DEV dev, uint16_t limit_check_id,
+ FixPoint1616_t limit_check_value);
+
+ /**
+ * @brief Get the current value of the signal used for the limit check
+ *
+ * @par Function Description
+ * This function get a the current value of the signal used for the limit check.
+ * To obtain the latest value you should run a ranging before.
+ * The value reported is linked to the limit check identified with the
+ * LimitCheckId.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param limit_check_id Limit Check ID
+ * (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
+ * @param p_limit_check_current Pointer to current Value for a
+ * given LimitCheckId.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned when
+ * LimitCheckId value is out of range.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_limit_check_current(VL53L0X_DEV dev, uint16_t limit_check_id,
+ FixPoint1616_t *p_limit_check_current);
+
+ /**
+ * @brief Return a the Status of the specified check limit
+ *
+ * @par Function Description
+ * This function returns the Status of the specified check limit.
+ * The value indicate if the check is fail or not.
+ * The limit check is identified with the LimitCheckId.
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param limit_check_id Limit Check ID
+ (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
+ * @param p_limit_check_status Pointer to the
+ Limit Check Status of the given check limit.
+ * LimitCheckStatus :
+ * 0 the check is not fail
+ * 1 the check if fail or not enabled
+ *
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is
+ returned when LimitCheckId value is out of range.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_limit_check_status(VL53L0X_DEV dev,
+ uint16_t limit_check_id, uint8_t *p_limit_check_status);
+
+ /**
+ * Get continuous mode Inter-Measurement period in milliseconds
+ *
+ * @par Function Description
+ * When trying to set too short time return INVALID_PARAMS minimal value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_inter_measurement_period_milli_seconds Pointer to programmed
+ * Inter-Measurement Period in milliseconds.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_inter_measurement_period_milli_seconds(VL53L0X_DEV dev,
+ uint32_t *p_inter_measurement_period_milli_seconds);
+
+ /**
+ * Program continuous mode Inter-Measurement period in milliseconds
+ *
+ * @par Function Description
+ * When trying to set too short time return INVALID_PARAMS minimal value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param inter_measurement_period_milli_seconds Inter-Measurement Period in ms.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_inter_measurement_period_milli_seconds(
+ VL53L0X_DEV dev, uint32_t inter_measurement_period_milli_seconds);
+
+ /**
+ * @brief Set new device address
+ *
+ * After completion the device will answer to the new address programmed.
+ * This function should be called when several devices are used in parallel
+ * before start programming the sensor.
+ * When a single device us used, there is no need to call this function.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param device_address The new Device address
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_device_address(VL53L0X_DEV dev, uint8_t device_address);
+
+ /**
+ * @brief Do an hard reset or soft reset (depending on implementation) of the
+ * device \nAfter call of this function, device must be in same state as right
+ * after a power-up sequence.This function will change the VL53L0X_State to
+ * VL53L0X_STATE_POWERDOWN.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_reset_device(VL53L0X_DEV dev);
+
+ /**
+ * @brief Get setup of Wrap around Check
+ *
+ * @par Function Description
+ * This function get the wrapAround check enable parameters
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_wrap_around_check_enable Pointer to the Wrap around Check state
+ * 0=disabled or 1 = enabled
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_wrap_around_check_enable(VL53L0X_DEV dev,
+ uint8_t *p_wrap_around_check_enable);
+
+ /**
+ * @brief Enable (or disable) Wrap around Check
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param wrap_around_check_enable Wrap around Check to be set
+ * 0=disabled, other = enabled
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_wrap_around_check_enable(VL53L0X_DEV dev,
+ uint8_t wrap_around_check_enable);
+
+ /**
+ * @brief Gets the VCSEL pulse period.
+ *
+ * @par Function Description
+ * This function retrieves the VCSEL pulse period for the given period type.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param vcsel_period_type VCSEL period identifier (pre-range|final).
+ * @param p_vcsel_pulse_period_pclk Pointer to VCSEL period value.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS Error VcselPeriodType parameter not
+ * supported.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk);
+
+ /**
+ * @brief Sets the VCSEL pulse period.
+ *
+ * @par Function Description
+ * This function retrieves the VCSEL pulse period for the given period type.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param vcsel_period_type VCSEL period identifier (pre-range|final).
+ * @param vcsel_pulse_period VCSEL period value
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS Error VcselPeriodType parameter not
+ * supported.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period);
+
+ /**
+ * @brief Set low and high Interrupt thresholds for a given mode
+ * (ranging, ALS, ...) for a given device
+ *
+ * @par Function Description
+ * Set low and high Interrupt thresholds for a given mode (ranging, ALS, ...)
+ * for a given device
+ *
+ * @note This function Access to the device
+ *
+ * @note DeviceMode is ignored for the current device
+ *
+ * @param dev Device Handle
+ * @param device_mode Device Mode for which change thresholds
+ * @param threshold_low Low threshold (mm, lux ..., depending on the mode)
+ * @param threshold_high High threshold (mm, lux ..., depending on the mode)
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_interrupt_thresholds(VL53L0X_DEV dev,
+ VL53L0X_DeviceModes device_mode, FixPoint1616_t threshold_low,
+ FixPoint1616_t threshold_high);
+
+ /**
+ * @brief Get high and low Interrupt thresholds for a given mode
+ * (ranging, ALS, ...) for a given device
+ *
+ * @par Function Description
+ * Get high and low Interrupt thresholds for a given mode (ranging, ALS, ...)
+ * for a given device
+ *
+ * @note This function Access to the device
+ *
+ * @note DeviceMode is ignored for the current device
+ *
+ * @param dev Device Handle
+ * @param device_mode Device Mode from which read thresholds
+ * @param p_threshold_low Low threshold (mm, lux ..., depending on the mode)
+ * @param p_threshold_high High threshold (mm, lux ..., depending on the mode)
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_interrupt_thresholds(VL53L0X_DEV dev,
+ VL53L0X_DeviceModes device_mode, FixPoint1616_t *p_threshold_low,
+ FixPoint1616_t *p_threshold_high);
+
+ /**
+ * @brief Reads the Device information for given Device
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_VL53L0X_device_info Pointer to current device info for a given
+ * Device
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_device_info(VL53L0X_DEV dev,
+ VL53L0X_DeviceInfo_t *p_VL53L0X_device_info);
+
+ /**
+ * @brief Gets the (on/off) state of all sequence steps.
+ *
+ * @par Function Description
+ * This function retrieves the state of all sequence step in the scheduler.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param p_scheduler_sequence_steps Pointer to struct containing result.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_sequence_step_enables(VL53L0X_DEV dev,
+ VL53L0X_SchedulerSequenceSteps_t *p_scheduler_sequence_steps);
+
+ /**
+ * @brief Sets the (on/off) state of a requested sequence step.
+ *
+ * @par Function Description
+ * This function enables/disables a requested sequence step.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param sequence_step_id Sequence step identifier.
+ * @param sequence_step_enabled Demanded state {0=Off,1=On}
+ * is enabled.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
+ * supported.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_sequence_step_enable(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_step_enabled);
+
+ /**
+ * @brief Gets the fraction enable parameter indicating the resolution of
+ * range measurements.
+ *
+ * @par Function Description
+ * Gets the fraction enable state, which translates to the resolution of
+ * range measurements as follows :Enabled:=0.25mm resolution,
+ * Not Enabled:=1mm resolution.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param p_enabled Output Parameter reporting the fraction enable state.
+ *
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_fraction_enable(VL53L0X_DEV dev, uint8_t *p_enabled);
+
+ /**
+ * @brief Sets the resolution of range measurements.
+ * @par Function Description
+ * Set resolution of range measurements to either 0.25mm if
+ * fraction enabled or 1mm if not enabled.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param enable Enable high resolution
+ *
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_range_fraction_enable(VL53L0X_DEV dev,
+ uint8_t enable);
+
+ /**
+ * @brief Return the VL53L0X PAL Implementation Version
+ *
+ * @note This function doesn't access to the device
+ *
+ * @param p_version Pointer to current PAL Implementation Version
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_version(VL53L0X_Version_t *p_version);
+
+ /**
+ * @brief Reads the Product Revision for a for given Device
+ * This function can be used to distinguish cut1.0 from cut1.1.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_product_revision_major Pointer to Product Revision Major
+ * for a given Device
+ * @param p_product_revision_minor Pointer to Product Revision Minor
+ * for a given Device
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_product_revision(VL53L0X_DEV dev,
+ uint8_t *p_product_revision_major, uint8_t *p_product_revision_minor);
+
+ /**
+ * @brief Retrieve current device parameters
+ * @par Function Description
+ * Get actual parameters of the device
+ * @li Then start ranging operation.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_device_parameters Pointer to store current device parameters.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_device_parameters(VL53L0X_DEV dev,
+ VL53L0X_DeviceParameters_t *p_device_parameters);
+
+ /**
+ * @brief Human readable error string for current PAL error status
+ *
+ * @note This function doesn't access to the device
+ *
+ * @param pal_error_code The error code as stored on @a VL53L0X_Error
+ * @param p_pal_error_string The error string corresponding to the
+ * PalErrorCode
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_pal_error_string(VL53L0X_Error pal_error_code,
+ char *p_pal_error_string);
+
+ /**
+ * @brief Return the PAL Specification Version used for the current
+ * implementation.
+ *
+ * @note This function doesn't access to the device
+ *
+ * @param p_pal_spec_version Pointer to current PAL Specification Version
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_pal_spec_version(
+ VL53L0X_Version_t *p_pal_spec_version);
+
+ /**
+ * @brief Reads the internal state of the PAL for a given Device
+ *
+ * @note This function doesn't access to the device
+ *
+ * @param dev Device Handle
+ * @param p_pal_state Pointer to current state of the PAL for a
+ * given Device
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_pal_state(VL53L0X_DEV dev,
+ VL53L0X_State *p_pal_state);
+
+ /**
+ * @brief Human readable PAL State string
+ *
+ * @note This function doesn't access to the device
+ *
+ * @param pal_state_code The State code as stored on @a VL53L0X_State
+ * @param p_pal_state_string The State string corresponding to the
+ * PalStateCode
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_pal_state_string(VL53L0X_State pal_state_code,
+ char *p_pal_state_string);
+
+ /*** End High level API ***/
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_3rd.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,952 @@
+
+ /* api.h functions */
+
+ /**
+ * @brief Wait for device booted after chip enable (hardware standby)
+ * This function can be run only when VL53L0X_State is VL53L0X_STATE_POWERDOWN.
+ *
+ * @note This function is not Implemented
+ *
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ *
+ */
+ VL53L0X_Error VL53L0X_wait_device_booted(VL53L0X_DEV dev);
+
+
+ VL53L0X_Error sequence_step_enabled(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id, uint8_t sequence_config,
+ uint8_t *p_sequence_step_enabled);
+
+ VL53L0X_Error VL53L0X_check_and_load_interrupt_settings(VL53L0X_DEV dev,
+ uint8_t start_not_stopflag);
+
+
+ /* api_core.h functions */
+
+ VL53L0X_Error VL53L0X_get_info_from_device(VL53L0X_DEV dev, uint8_t option);
+
+ VL53L0X_Error VL53L0X_device_read_strobe(VL53L0X_DEV dev);
+
+ VL53L0X_Error wrapped_VL53L0X_get_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t *p_measurement_timing_budget_micro_seconds);
+
+ VL53L0X_Error wrapped_VL53L0X_get_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t *p_vcsel_pulse_period_pclk);
+
+ uint8_t VL53L0X_decode_vcsel_period(uint8_t vcsel_period_reg);
+
+ uint32_t VL53L0X_decode_timeout(uint16_t encoded_timeout);
+
+ uint32_t VL53L0X_calc_timeout_us(VL53L0X_DEV dev,
+ uint16_t timeout_period_mclks,
+ uint8_t vcsel_period_pclks);
+
+ uint32_t VL53L0X_calc_macro_period_ps(VL53L0X_DEV dev, uint8_t vcsel_period_pclks);
+
+ VL53L0X_Error VL53L0X_measurement_poll_for_completion(VL53L0X_DEV dev);
+
+ VL53L0X_Error VL53L0X_load_tuning_settings(VL53L0X_DEV dev,
+ uint8_t *p_tuning_setting_buffer);
+
+ VL53L0X_Error VL53L0X_get_pal_range_status(VL53L0X_DEV dev,
+ uint8_t device_range_status,
+ FixPoint1616_t signal_rate,
+ uint16_t effective_spad_rtn_count,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ uint8_t *p_pal_range_status);
+ VL53L0X_Error VL53L0X_calc_sigma_estimate(VL53L0X_DEV dev,
+ VL53L0X_RangingMeasurementData_t *p_ranging_measurement_data,
+ FixPoint1616_t *p_sigma_estimate,
+ uint32_t *p_dmax_mm);
+ uint32_t VL53L0X_calc_timeout_mclks(VL53L0X_DEV dev,
+ uint32_t timeout_period_us,
+ uint8_t vcsel_period_pclks);
+ uint32_t VL53L0X_isqrt(uint32_t num);
+
+ uint32_t VL53L0X_quadrature_sum(uint32_t a, uint32_t b);
+
+ VL53L0X_Error VL53L0X_calc_dmax(
+ VL53L0X_DEV dev,
+ FixPoint1616_t total_signal_rate_mcps,
+ FixPoint1616_t total_corr_signal_rate_mcps,
+ FixPoint1616_t pw_mult,
+ uint32_t sigma_estimate_p1,
+ FixPoint1616_t sigma_estimate_p2,
+ uint32_t peak_vcsel_duration_us,
+ uint32_t *pd_max_mm);
+ VL53L0X_Error wrapped_VL53L0X_set_measurement_timing_budget_micro_seconds(VL53L0X_DEV dev,
+ uint32_t measurement_timing_budget_micro_seconds);
+ VL53L0X_Error get_sequence_step_timeout(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id,
+ uint32_t *p_time_out_micro_secs);
+ VL53L0X_Error set_sequence_step_timeout(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id,
+ uint32_t timeout_micro_secs);
+ uint16_t VL53L0X_encode_timeout(uint32_t timeout_macro_clks);
+ VL53L0X_Error wrapped_VL53L0X_set_vcsel_pulse_period(VL53L0X_DEV dev,
+ VL53L0X_VcselPeriod vcsel_period_type, uint8_t vcsel_pulse_period_pclk);
+ uint8_t lv53l0x_encode_vcsel_period(uint8_t vcsel_period_pclks);
+
+ /* api_calibration.h functions */
+ VL53L0X_Error VL53L0X_apply_offset_adjustment(VL53L0X_DEV dev);
+ VL53L0X_Error wrapped_VL53L0X_get_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t *p_offset_calibration_data_micro_meter);
+ VL53L0X_Error wrapped_VL53L0X_set_offset_calibration_data_micro_meter(VL53L0X_DEV dev,
+ int32_t offset_calibration_data_micro_meter);
+ VL53L0X_Error wrapped_VL53L0X_perform_ref_spad_management(VL53L0X_DEV dev,
+ uint32_t *ref_spad_count,
+ uint8_t *is_aperture_spads);
+ VL53L0X_Error VL53L0X_perform_ref_calibration(VL53L0X_DEV dev,
+ uint8_t *p_vhv_settings, uint8_t *p_phase_cal, uint8_t get_data_enable);
+ VL53L0X_Error VL53L0X_perform_vhv_calibration(VL53L0X_DEV dev,
+ uint8_t *p_vhv_settings, const uint8_t get_data_enable,
+ const uint8_t restore_config);
+ VL53L0X_Error VL53L0X_perform_single_ref_calibration(VL53L0X_DEV dev,
+ uint8_t vhv_init_byte);
+ VL53L0X_Error VL53L0X_ref_calibration_io(VL53L0X_DEV dev, uint8_t read_not_write,
+ uint8_t vhv_settings, uint8_t phase_cal,
+ uint8_t *p_vhv_settings, uint8_t *p_phase_cal,
+ const uint8_t vhv_enable, const uint8_t phase_enable);
+ VL53L0X_Error VL53L0X_perform_phase_calibration(VL53L0X_DEV dev,
+ uint8_t *p_phase_cal, const uint8_t get_data_enable,
+ const uint8_t restore_config);
+ VL53L0X_Error enable_ref_spads(VL53L0X_DEV dev,
+ uint8_t aperture_spads,
+ uint8_t good_spad_array[],
+ uint8_t spad_array[],
+ uint32_t size,
+ uint32_t start,
+ uint32_t offset,
+ uint32_t spad_count,
+ uint32_t *p_last_spad);
+ void get_next_good_spad(uint8_t good_spad_array[], uint32_t size,
+ uint32_t curr, int32_t *p_next);
+ uint8_t is_aperture(uint32_t spad_index);
+ VL53L0X_Error enable_spad_bit(uint8_t spad_array[], uint32_t size,
+ uint32_t spad_index);
+ VL53L0X_Error set_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array);
+ VL53L0X_Error get_ref_spad_map(VL53L0X_DEV dev, uint8_t *p_ref_spad_array);
+ VL53L0X_Error perform_ref_signal_measurement(VL53L0X_DEV dev,
+ uint16_t *p_ref_signal_rate);
+ VL53L0X_Error wrapped_VL53L0X_set_reference_spads(VL53L0X_DEV dev,
+ uint32_t count, uint8_t is_aperture_spads);
+
+ /* api_strings.h functions */
+ VL53L0X_Error wrapped_VL53L0X_get_device_info(VL53L0X_DEV dev,
+ VL53L0X_DeviceInfo_t *p_VL53L0X_device_info);
+ VL53L0X_Error VL53L0X_check_part_used(VL53L0X_DEV dev,
+ uint8_t *revision,
+ VL53L0X_DeviceInfo_t *p_VL53L0X_device_info);
+
+ /* Read function of the ID device */
+ // virtual int read_id();
+ virtual int read_id(uint8_t *id);
+
+ VL53L0X_Error wait_measurement_data_ready(VL53L0X_DEV dev);
+
+ VL53L0X_Error wait_stop_completed(VL53L0X_DEV dev);
+
+ /* Write and read functions from I2C */
+ /**
+ * Write single byte register
+ * @param dev Device Handle
+ * @param index The register index
+ * @param data 8 bit register data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_write_byte(VL53L0X_DEV dev, uint8_t index, uint8_t data);
+ /**
+ * Write word register
+ * @param dev Device Handle
+ * @param index The register index
+ * @param data 16 bit register data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_write_word(VL53L0X_DEV dev, uint8_t index, uint16_t data);
+ /**
+ * Write double word (4 byte) register
+ * @param dev Device Handle
+ * @param index The register index
+ * @param data 32 bit register data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_write_dword(VL53L0X_DEV dev, uint8_t index, uint32_t data);
+ /**
+ * Read single byte register
+ * @param dev Device Handle
+ * @param index The register index
+ * @param data pointer to 8 bit data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_read_byte(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data);
+ /**
+ * Read word (2byte) register
+ * @param dev Device Handle
+ * @param index The register index
+ * @param data pointer to 16 bit data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_read_word(VL53L0X_DEV dev, uint8_t index, uint16_t *p_data);
+ /**
+ * Read dword (4byte) register
+ * @param dev Device Handle
+ * @param index The register index
+ * @param data pointer to 32 bit data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_read_dword(VL53L0X_DEV dev, uint8_t index, uint32_t *p_data);
+ /**
+ * Threat safe Update (read/modify/write) single byte register
+ *
+ * Final_reg = (Initial_reg & and_data) |or_data
+ *
+ * @param dev Device Handle
+ * @param index The register index
+ * @param and_data 8 bit and data
+ * @param or_data 8 bit or data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_update_byte(VL53L0X_DEV dev, uint8_t index, uint8_t and_data, uint8_t or_data);
+ /**
+ * Writes the supplied byte buffer to the device
+ * @param dev Device Handle
+ * @param index The register index
+ * @param p_data Pointer to uint8_t buffer containing the data to be written
+ * @param count Number of bytes in the supplied byte buffer
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_write_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count);
+ /**
+ * Reads the requested number of bytes from the device
+ * @param dev Device Handle
+ * @param index The register index
+ * @param p_data Pointer to the uint8_t buffer to store read data
+ * @param count Number of uint8_t's to read
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_read_multi(VL53L0X_DEV dev, uint8_t index, uint8_t *p_data, uint32_t count);
+
+ /**
+ * @brief Writes a buffer towards the I2C peripheral device.
+ * @param dev Device Handle
+ * @param p_data pointer to the byte-array data to send
+ * @param number_of_bytes number of bytes to be written.
+ * @retval 0 if ok,
+ * @retval -1 if an I2C error has occured
+ * @note On some devices if NumByteToWrite is greater
+ * than one, the RegisterAddr must be masked correctly!
+ */
+ VL53L0X_Error VL53L0X_i2c_write(uint8_t dev, uint8_t index, uint8_t *p_data, uint16_t number_of_bytes);
+
+ /**
+ * @brief Reads a buffer from the I2C peripheral device.
+ * @param dev Device Handle
+ * @param p_data pointer to the byte-array to read data in to
+ * @param number_of_bytes number of bytes to be read.
+ * @retval 0 if ok,
+ * @retval -1 if an I2C error has occured
+ * @note On some devices if NumByteToWrite is greater
+ * than one, the RegisterAddr must be masked correctly!
+ */
+ VL53L0X_Error VL53L0X_i2c_read(uint8_t dev, uint8_t index, uint8_t *p_data, uint16_t number_of_bytes);
+
+ /**
+ * @brief execute delay in all polling API call
+ *
+ * A typical multi-thread or RTOs implementation is to sleep the task for some 5ms (with 100Hz max rate faster polling is not needed)
+ * if nothing specific is need you can define it as an empty/void macro
+ * @code
+ * #define VL53L0X_PollingDelay(...) (void)0
+ * @endcode
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_polling_delay(VL53L0X_DEV dev); /* usually best implemented as a real function */
+
+ int is_present()
+ {
+ int status;
+ uint8_t id = 0;
+
+ status = read_id(&id);
+ if (status) {
+ VL53L0X_ErrLog("Failed to read ID device. Device not present!\n\r");
+ }
+ return status;
+ }
+
+ ///////////////////////////////////////////////////////////////////////////////////////////////////////
+ //Added functions //
+ ///////////////////////////////////////////////////////////////////////////////////////////////////////
+
+ /**
+ * @brief Cycle Power to Device
+ *
+ * @return status - status 0 = ok, 1 = error
+ *
+ */
+ int32_t VL53L0X_cycle_power(void);
+
+ uint8_t VL53L0X_encode_vcsel_period(uint8_t vcsel_period_pclks);
+
+ VL53L0X_Error wrapped_VL53L0X_get_device_error_string(VL53L0X_DeviceError error_code,
+ char *p_device_error_string);
+
+ VL53L0X_Error wrapped_VL53L0X_get_limit_check_info(VL53L0X_DEV dev, uint16_t limit_check_id,
+ char *p_limit_check_string);
+
+ VL53L0X_Error wrapped_VL53L0X_get_pal_error_string(VL53L0X_Error pal_error_code,
+ char *p_pal_error_string);
+
+ VL53L0X_Error wrapped_VL53L0X_get_pal_state_string(VL53L0X_State pal_state_code,
+ char *p_pal_state_string);
+
+ VL53L0X_Error wrapped_VL53L0X_get_range_status_string(uint8_t range_status,
+ char *p_range_status_string);
+
+ VL53L0X_Error wrapped_VL53L0X_get_ref_calibration(VL53L0X_DEV dev,
+ uint8_t *p_vhv_settings, uint8_t *p_phase_cal);
+
+
+ VL53L0X_Error count_enabled_spads(uint8_t spad_array[],
+ uint32_t byte_count, uint32_t max_spads,
+ uint32_t *p_total_spads_enabled, uint8_t *p_is_aperture);
+
+ VL53L0X_Error wrapped_VL53L0X_get_sequence_steps_info(VL53L0X_SequenceStepId sequence_step_id,
+ char *p_sequence_steps_string);
+
+
+ /**
+ * @brief Gets the name of a given sequence step.
+ *
+ * @par Function Description
+ * This function retrieves the name of sequence steps corresponding to
+ * SequenceStepId.
+ *
+ * @note This function doesn't Accesses the device
+ *
+ * @param sequence_step_id Sequence step identifier.
+ * @param p_sequence_steps_string Pointer to Info string
+ *
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_sequence_steps_info(VL53L0X_SequenceStepId sequence_step_id,
+ char *p_sequence_steps_string);
+
+ /**
+ * @brief Get the frequency of the timer used for ranging results time stamps
+ *
+ * @param[out] p_timer_freq_hz : pointer for timer frequency
+ *
+ * @return status : 0 = ok, 1 = error
+ *
+ */
+ int32_t VL53L0X_get_timer_frequency(int32_t *p_timer_freq_hz);
+
+ /**
+ * @brief Get the timer value in units of timer_freq_hz (see VL53L0X_get_timestamp_frequency())
+ *
+ * @param[out] p_timer_count : pointer for timer count value
+ *
+ * @return status : 0 = ok, 1 = error
+ *
+ */
+ int32_t VL53L0X_get_timer_value(int32_t *p_timer_count);
+
+ /**
+ * @brief Configure ranging interrupt reported to system
+ *
+ * @note This function is not Implemented
+ *
+ * @param dev Device Handle
+ * @param interrupt_mask Mask of interrupt to Enable/disable
+ * (0:interrupt disabled or 1: interrupt enabled)
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ */
+ VL53L0X_Error VL53L0X_enable_interrupt_mask(VL53L0X_DEV dev,
+ uint32_t interrupt_mask);
+
+ /**
+ * @brief Get Dmax Calibration Parameters for a given device
+ *
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_range_milli_meter Pointer to Calibration Distance
+ * @param p_signal_rate_rtn_mega_cps Pointer to Signal rate return
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_dmax_cal_parameters(VL53L0X_DEV dev,
+ uint16_t *p_range_milli_meter, FixPoint1616_t *p_signal_rate_rtn_mega_cps);
+
+ /**
+ * @brief Set Dmax Calibration Parameters for a given device
+ * When one of the parameter is zero, this function will get parameter
+ * from NVM.
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param range_milli_meter Calibration Distance
+ * @param signal_rate_rtn_mega_cps Signal rate return read at CalDistance
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_dmax_cal_parameters(VL53L0X_DEV dev,
+ uint16_t range_milli_meter, FixPoint1616_t signal_rate_rtn_mega_cps);
+
+ /**
+ * @brief Retrieve the measurements from device for a given setup
+ *
+ * @par Function Description
+ * Get data from last successful Histogram measurement
+ * @warning USER should take care about @a VL53L0X_GetNumberOfROIZones()
+ * before get data.
+ * PAL will fill a NumberOfROIZones times the corresponding data structure
+ * used in the measurement function.
+ *
+ * @note This function is not Implemented
+ *
+ * @param dev Device Handle
+ * @param p_histogram_measurement_data Pointer to the histogram data structure.
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ */
+ VL53L0X_Error VL53L0X_get_histogram_measurement_data(VL53L0X_DEV dev,
+ VL53L0X_HistogramMeasurementData_t *p_histogram_measurement_data);
+
+ /**
+ * @brief Get current new device mode
+ * @par Function Description
+ * Get current Histogram mode of a Device
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_histogram_mode Pointer to current Histogram Mode value
+ * Valid values are:
+ * VL53L0X_HISTOGRAMMODE_DISABLED
+ * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
+ * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
+ * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
+ * VL53L0X_HISTOGRAMMODE_BOTH
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_histogram_mode(VL53L0X_DEV dev,
+ VL53L0X_HistogramModes *p_histogram_mode);
+
+ /**
+ * @brief Set a new Histogram mode
+ * @par Function Description
+ * Set device to a new Histogram mode
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param histogram_mode New device mode to apply
+ * Valid values are:
+ * VL53L0X_HISTOGRAMMODE_DISABLED
+ * VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM
+ * VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY
+ * VL53L0X_HISTOGRAMMODE_RETURN_ONLY
+ * VL53L0X_HISTOGRAMMODE_BOTH
+ *
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when
+ * HistogramMode is not in the supported list
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_histogram_mode(VL53L0X_DEV dev,
+ VL53L0X_HistogramModes histogram_mode);
+
+ /**
+ * @brief Return a description string for a given limit check number
+ *
+ * @par Function Description
+ * This function returns a description string for a given limit check number.
+ * The limit check is identified with the LimitCheckId.
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param limit_check_id Limit Check ID
+ (0<= LimitCheckId < VL53L0X_GetNumberOfLimitCheck() ).
+ * @param p_limit_check_string Pointer to the
+ description string of the given check limit.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is
+ returned when LimitCheckId value is out of range.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_limit_check_info(VL53L0X_DEV dev,
+ uint16_t limit_check_id, char *p_limit_check_string);
+
+ /**
+ * @brief Get the linearity corrective gain
+ *
+ * @par Function Description
+ * Should only be used after a successful call to @a VL53L0X_DataInit to backup
+ * device NVM value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_linearity_corrective_gain Pointer to the linearity
+ * corrective gain in x1000
+ * if value is 1000 then no modification is applied.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_linearity_corrective_gain(VL53L0X_DEV dev,
+ uint16_t *p_linearity_corrective_gain);
+
+ /**
+ * Set the linearity corrective gain
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param linearity_corrective_gain Linearity corrective
+ * gain in x1000
+ * if value is 1000 then no modification is applied.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_linearity_corrective_gain(VL53L0X_DEV dev,
+ int16_t linearity_corrective_gain);
+
+ /**
+ * @brief Get the Maximum number of ROI Zones managed by the Device
+ *
+ * @par Function Description
+ * Get Maximum number of ROI Zones managed by the Device.
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_max_number_of_roi_zones Pointer to the Maximum Number
+ * of ROI Zones value.
+ * @return VL53L0X_ERROR_NONE Success
+ */
+ VL53L0X_Error VL53L0X_get_max_number_of_roi_zones(VL53L0X_DEV dev,
+ uint8_t *p_max_number_of_roi_zones);
+
+ /**
+ * @brief Retrieve the Reference Signal after a measurements
+ *
+ * @par Function Description
+ * Get Reference Signal from last successful Ranging measurement
+ * This function return a valid value after that you call the
+ * @a VL53L0X_GetRangingMeasurementData().
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_measurement_ref_signal Pointer to the Ref Signal to fill up.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_measurement_ref_signal(VL53L0X_DEV dev,
+ FixPoint1616_t *p_measurement_ref_signal);
+
+ /**
+ * @brief Get the number of the check limit managed by a given Device
+ *
+ * @par Function Description
+ * This function give the number of the check limit managed by the Device
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param p_number_of_limit_check Pointer to the number of check limit.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_number_of_limit_check(
+ uint16_t *p_number_of_limit_check);
+
+ /**
+ * @brief Get the number of ROI Zones managed by the Device
+ *
+ * @par Function Description
+ * Get number of ROI Zones managed by the Device
+ * USER should take care about @a VL53L0X_GetNumberOfROIZones()
+ * before get data after a perform measurement.
+ * PAL will fill a NumberOfROIZones times the corresponding data
+ * structure used in the measurement function.
+ *
+ * @note This function doesn't Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_number_of_roi_zones Pointer to the Number of ROI Zones value.
+ * @return VL53L0X_ERROR_NONE Success
+ */
+ VL53L0X_Error VL53L0X_get_number_of_roi_zones(VL53L0X_DEV dev,
+ uint8_t *p_number_of_roi_zones);
+
+ /**
+ * @brief Set the number of ROI Zones to be used for a specific Device
+ *
+ * @par Function Description
+ * Set the number of ROI Zones to be used for a specific Device.
+ * The programmed value should be less than the max number of ROI Zones given
+ * with @a VL53L0X_GetMaxNumberOfROIZones().
+ * This version of API manage only one zone.
+ *
+ * @param dev Device Handle
+ * @param number_of_roi_zones Number of ROI Zones to be used for a
+ * specific Device.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS This error is returned if
+ * NumberOfROIZones != 1
+ */
+ VL53L0X_Error VL53L0X_set_number_of_roi_zones(VL53L0X_DEV dev,
+ uint8_t number_of_roi_zones);
+
+ /**
+ * @brief Gets number of sequence steps managed by the API.
+ *
+ * @par Function Description
+ * This function retrieves the number of sequence steps currently managed
+ * by the API
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param p_number_of_sequence_steps Out parameter reporting the number of
+ * sequence steps.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_number_of_sequence_steps(VL53L0X_DEV dev,
+ uint8_t *p_number_of_sequence_steps);
+ /**
+ * @brief Get the power mode for a given Device
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_power_mode Pointer to the current value of the power
+ * mode. see ::VL53L0X_PowerModes
+ * Valid values are:
+ * VL53L0X_POWERMODE_STANDBY_LEVEL1,
+ * VL53L0X_POWERMODE_IDLE_LEVEL1
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_power_mode(VL53L0X_DEV dev,
+ VL53L0X_PowerModes *p_power_mode);
+
+ /**
+ * @brief Set the power mode for a given Device
+ * The power mode can be Standby or Idle. Different level of both Standby and
+ * Idle can exists.
+ * This function should not be used when device is in Ranging state.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param power_mode The value of the power mode to set.
+ * see ::VL53L0X_PowerModes
+ * Valid values are:
+ * VL53L0X_POWERMODE_STANDBY_LEVEL1,
+ * VL53L0X_POWERMODE_IDLE_LEVEL1
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_MODE_NOT_SUPPORTED This error occurs when PowerMode
+ * is not in the supported list
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_power_mode(VL53L0X_DEV dev,
+ VL53L0X_PowerModes power_mode);
+
+ /**
+ * @brief Retrieves SPAD configuration
+ *
+ * @par Function Description
+ * This function retrieves the current number of applied reference spads
+ * and also their type : Aperture or Non-Aperture.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_spad_count Number ref Spad Count
+ * @param p_is_aperture_spads Reports if spads are of type
+ * aperture or non-aperture.
+ * 1:=aperture, 0:=Non-Aperture
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_REF_SPAD_INIT Error in the in the reference
+ * spad configuration.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error wrapped_VL53L0X_get_reference_spads(VL53L0X_DEV dev,
+ uint32_t *p_spad_count, uint8_t *p_is_aperture_spads);
+
+ /**
+ * @brief Gets the (on/off) state of a requested sequence step.
+ *
+ * @par Function Description
+ * This function retrieves the state of a requested sequence step, i.e. on/off.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param sequence_step_id Sequence step identifier.
+ * @param p_sequence_step_enabled Out parameter reporting if the sequence step
+ * is enabled {0=Off,1=On}.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
+ * supported.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_sequence_step_enable(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id, uint8_t *p_sequence_step_enabled);
+
+
+ /**
+ * @brief Gets the timeout of a requested sequence step.
+ *
+ * @par Function Description
+ * This function retrieves the timeout of a requested sequence step.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param sequence_step_id Sequence step identifier.
+ * @param p_time_out_milli_secs Timeout value.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
+ * supported.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_sequence_step_timeout(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id,
+ FixPoint1616_t *p_time_out_milli_secs);
+
+ /**
+ * @brief Sets the timeout of a requested sequence step.
+ *
+ * @par Function Description
+ * This function sets the timeout of a requested sequence step.
+ *
+ * @note This function Accesses the device
+ *
+ * @param dev Device Handle
+ * @param sequence_step_id Sequence step identifier.
+ * @param time_out_milli_secs Demanded timeout
+ * @return VL53L0X_ERROR_NONE Success
+ * @return VL53L0X_ERROR_INVALID_PARAMS Error SequenceStepId parameter not
+ * supported.
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_sequence_step_timeout(VL53L0X_DEV dev,
+ VL53L0X_SequenceStepId sequence_step_id, FixPoint1616_t time_out_milli_secs);
+
+ /**
+ * @brief Get the current SPAD Ambient Damper Factor value
+ *
+ * @par Function Description
+ * This function get the SPAD Ambient Damper Factor value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_spad_ambient_damper_factor Pointer to programmed SPAD Ambient
+ * Damper Factor value
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_spad_ambient_damper_factor(VL53L0X_DEV dev,
+ uint16_t *p_spad_ambient_damper_factor);
+ /**
+ * @brief Set the SPAD Ambient Damper Factor value
+ *
+ * @par Function Description
+ * This function set the SPAD Ambient Damper Factor value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param spad_ambient_damper_factor SPAD Ambient Damper Factor value
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_spad_ambient_damper_factor(VL53L0X_DEV dev,
+ uint16_t spad_ambient_damper_factor);
+
+ /**
+ * @brief Get the current SPAD Ambient Damper Threshold value
+ *
+ * @par Function Description
+ * This function get the SPAD Ambient Damper Threshold value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_spad_ambient_damper_threshold Pointer to programmed
+ * SPAD Ambient Damper Threshold value
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_spad_ambient_damper_threshold(VL53L0X_DEV dev,
+ uint16_t *p_spad_ambient_damper_threshold);
+
+ /**
+ * @brief Set the SPAD Ambient Damper Threshold value
+ *
+ * @par Function Description
+ * This function set the SPAD Ambient Damper Threshold value
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param spad_ambient_damper_threshold SPAD Ambient Damper Threshold value
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_spad_ambient_damper_threshold(VL53L0X_DEV dev,
+ uint16_t spad_ambient_damper_threshold);
+
+ /**
+ * @brief Get the maximal distance for actual setup
+ * @par Function Description
+ * Device must be initialized through @a VL53L0X_SetParameters() prior calling
+ * this function.
+ *
+ * Any range value more than the value returned is to be considered as
+ * "no target detected" or
+ * "no target in detectable range"\n
+ * @warning The maximal distance depends on the setup
+ *
+ * @note This function is not Implemented
+ *
+ * @param dev Device Handle
+ * @param p_upper_limit_milli_meter The maximal range limit for actual setup
+ * (in millimeter)
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ */
+ VL53L0X_Error VL53L0X_get_upper_limit_milli_meter(VL53L0X_DEV dev,
+ uint16_t *p_upper_limit_milli_meter);
+
+ /**
+ * @brief Get the tuning settings pointer and the internal external switch
+ * value.
+ *
+ * This function is used to get the Tuning settings buffer pointer and the
+ * value.
+ * of the switch to select either external or internal tuning settings.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param pp_tuning_setting_buffer Pointer to tuning settings buffer.
+ * @param p_use_internal_tuning_settings Pointer to store Use internal tuning
+ * settings value.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_get_tuning_setting_buffer(VL53L0X_DEV dev,
+ uint8_t **pp_tuning_setting_buffer, uint8_t *p_use_internal_tuning_settings);
+
+ /**
+ * @brief Set the tuning settings pointer
+ *
+ * This function is used to specify the Tuning settings buffer to be used
+ * for a given device. The buffer contains all the necessary data to permit
+ * the API to write tuning settings.
+ * This function permit to force the usage of either external or internal
+ * tuning settings.
+ *
+ * @note This function Access to the device
+ *
+ * @param dev Device Handle
+ * @param p_tuning_setting_buffer Pointer to tuning settings buffer.
+ * @param use_internal_tuning_settings Use internal tuning settings value.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_set_tuning_setting_buffer(VL53L0X_DEV dev,
+ uint8_t *p_tuning_setting_buffer, uint8_t use_internal_tuning_settings);
+
+ /**
+ * @defgroup VL53L0X_registerAccess_group PAL Register Access Functions
+ * @brief PAL Register Access Functions
+ * @{
+ */
+
+ /**
+ * Lock comms interface to serialize all commands to a shared I2C interface for a specific device
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_lock_sequence_access(VL53L0X_DEV dev);
+
+ /**
+ * Unlock comms interface to serialize all commands to a shared I2C interface for a specific device
+ * @param dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error VL53L0X_unlock_sequence_access(VL53L0X_DEV dev);
+
+ /**
+ * @brief Prepare device for operation
+ * @par Function Description
+ * Update device with provided parameters
+ * @li Then start ranging operation.
+ *
+ * @note This function Access to the device
+ *
+ * @param Dev Device Handle
+ * @param pDeviceParameters Pointer to store current device parameters.
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+ VL53L0X_Error vl53L0x_set_device_parameters(VL53L0X_DEV Dev,
+ const VL53L0X_DeviceParameters_t *pDeviceParameters);
+
+ /**
+ * Set Group parameter Hold state
+ *
+ * @par Function Description
+ * Set or remove device internal group parameter hold
+ *
+ * @note This function is not Implemented
+ *
+ * @param dev Device Handle
+ * @param group_param_hold Group parameter Hold state to be set (on/off)
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ */
+ VL53L0X_Error VL53L0X_set_group_param_hold(VL53L0X_DEV dev,
+ uint8_t group_param_hold);
+
+
+ /**
+ * @brief Wait for device ready for a new measurement command.
+ * Blocking function.
+ *
+ * @note This function is not Implemented
+ *
+ * @param dev Device Handle
+ * @param max_loop Max Number of polling loop (timeout).
+ * @return VL53L0X_ERROR_NOT_IMPLEMENTED Not implemented
+ */
+ VL53L0X_Error VL53L0X_wait_device_ready_for_new_measurement(VL53L0X_DEV dev,
+ uint32_t max_loop);
+
+ VL53L0X_Error VL53L0X_reverse_bytes(uint8_t *data, uint32_t size);
+
+ int range_meas_int_continuous_mode(void (*fptr)(void));
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_def.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,640 @@
+/*******************************************************************************
+Copyright © 2016, STMicroelectronics International N.V.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/**
+ * @file VL53L0X_def.h
+ *
+ * @brief Type definitions for VL53L0X API.
+ *
+ */
+
+
+#ifndef _VL53L0X_DEF_H_
+#define _VL53L0X_DEF_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup VL53L0X_globaldefine_group VL53L0X Defines
+ * @brief VL53L0X Defines
+ * @{
+ */
+
+
+/** PAL SPECIFICATION major version */
+#define VL53L0X10_SPECIFICATION_VER_MAJOR 1
+/** PAL SPECIFICATION minor version */
+#define VL53L0X10_SPECIFICATION_VER_MINOR 2
+/** PAL SPECIFICATION sub version */
+#define VL53L0X10_SPECIFICATION_VER_SUB 7
+/** PAL SPECIFICATION sub version */
+#define VL53L0X10_SPECIFICATION_VER_REVISION 1440
+
+/** VL53L0X PAL IMPLEMENTATION major version */
+#define VL53L0X10_IMPLEMENTATION_VER_MAJOR 1
+/** VL53L0X PAL IMPLEMENTATION minor version */
+#define VL53L0X10_IMPLEMENTATION_VER_MINOR 0
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X10_IMPLEMENTATION_VER_SUB 9
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X10_IMPLEMENTATION_VER_REVISION 3673
+
+/** PAL SPECIFICATION major version */
+#define VL53L0X_SPECIFICATION_VER_MAJOR 1
+/** PAL SPECIFICATION minor version */
+#define VL53L0X_SPECIFICATION_VER_MINOR 2
+/** PAL SPECIFICATION sub version */
+#define VL53L0X_SPECIFICATION_VER_SUB 7
+/** PAL SPECIFICATION sub version */
+#define VL53L0X_SPECIFICATION_VER_REVISION 1440
+
+/** VL53L0X PAL IMPLEMENTATION major version */
+#define VL53L0X_IMPLEMENTATION_VER_MAJOR 1
+/** VL53L0X PAL IMPLEMENTATION minor version */
+#define VL53L0X_IMPLEMENTATION_VER_MINOR 1
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X_IMPLEMENTATION_VER_SUB 21
+/** VL53L0X PAL IMPLEMENTATION sub version */
+#define VL53L0X_IMPLEMENTATION_VER_REVISION 4823
+#define VL53L0X_DEFAULT_MAX_LOOP 2000
+#define VL53L0X_MAX_STRING_LENGTH 32
+
+
+#include "VL53L0X_device.h"
+#include "VL53L0X_types.h"
+
+
+/****************************************
+ * PRIVATE define do not edit
+ ****************************************/
+
+/** @brief Defines the parameters of the Get Version Functions
+ */
+typedef struct {
+ uint32_t revision; /*!< revision number */
+ uint8_t major; /*!< major number */
+ uint8_t minor; /*!< minor number */
+ uint8_t build; /*!< build number */
+} VL53L0X_Version_t;
+
+
+/** @brief Defines the parameters of the Get Device Info Functions
+ */
+typedef struct {
+ char Name[VL53L0X_MAX_STRING_LENGTH];
+ /*!< Name of the Device e.g. Left_Distance */
+ char Type[VL53L0X_MAX_STRING_LENGTH];
+ /*!< Type of the Device e.g VL53L0X */
+ char ProductId[VL53L0X_MAX_STRING_LENGTH];
+ /*!< Product Identifier String */
+ uint8_t ProductType;
+ /*!< Product Type, VL53L0X = 1, VL53L1 = 2 */
+ uint8_t ProductRevisionMajor;
+ /*!< Product revision major */
+ uint8_t ProductRevisionMinor;
+ /*!< Product revision minor */
+} VL53L0X_DeviceInfo_t;
+
+
+/** @defgroup VL53L0X_define_Error_group Error and Warning code returned by API
+ * The following DEFINE are used to identify the PAL ERROR
+ * @{
+ */
+
+typedef int8_t VL53L0X_Error;
+
+#define VL53L0X_ERROR_NONE ((VL53L0X_Error) 0)
+#define VL53L0X_ERROR_CALIBRATION_WARNING ((VL53L0X_Error) -1)
+/*!< Warning invalid calibration data may be in used
+ \a VL53L0X_InitData()
+ \a VL53L0X_GetOffsetCalibrationData
+ \a VL53L0X_SetOffsetCalibrationData */
+#define VL53L0X_ERROR_MIN_CLIPPED ((VL53L0X_Error) -2)
+/*!< Warning parameter passed was clipped to min before to be applied */
+
+#define VL53L0X_ERROR_UNDEFINED ((VL53L0X_Error) -3)
+/*!< Unqualified error */
+#define VL53L0X_ERROR_INVALID_PARAMS ((VL53L0X_Error) -4)
+/*!< Parameter passed is invalid or out of range */
+#define VL53L0X_ERROR_NOT_SUPPORTED ((VL53L0X_Error) -5)
+/*!< Function is not supported in current mode or configuration */
+#define VL53L0X_ERROR_RANGE_ERROR ((VL53L0X_Error) -6)
+/*!< Device report a ranging error interrupt status */
+#define VL53L0X_ERROR_TIME_OUT ((VL53L0X_Error) -7)
+/*!< Aborted due to time out */
+#define VL53L0X_ERROR_MODE_NOT_SUPPORTED ((VL53L0X_Error) -8)
+/*!< Asked mode is not supported by the device */
+#define VL53L0X_ERROR_BUFFER_TOO_SMALL ((VL53L0X_Error) -9)
+/*!< ... */
+#define VL53L0X_ERROR_GPIO_NOT_EXISTING ((VL53L0X_Error) -10)
+/*!< User tried to setup a non-existing GPIO pin */
+#define VL53L0X_ERROR_GPIO_FUNCTIONALITY_NOT_SUPPORTED ((VL53L0X_Error) -11)
+/*!< unsupported GPIO functionality */
+#define VL53L0X_ERROR_INTERRUPT_NOT_CLEARED ((VL53L0X_Error) -12)
+/*!< Error during interrupt clear */
+#define VL53L0X_ERROR_CONTROL_INTERFACE ((VL53L0X_Error) -20)
+/*!< error reported from IO functions */
+#define VL53L0X_ERROR_INVALID_COMMAND ((VL53L0X_Error) -30)
+/*!< The command is not allowed in the current device state
+ * (power down) */
+#define VL53L0X_ERROR_DIVISION_BY_ZERO ((VL53L0X_Error) -40)
+/*!< In the function a division by zero occurs */
+#define VL53L0X_ERROR_REF_SPAD_INIT ((VL53L0X_Error) -50)
+/*!< Error during reference SPAD initialization */
+#define VL53L0X_ERROR_NOT_IMPLEMENTED ((VL53L0X_Error) -99)
+/*!< Tells requested functionality has not been implemented yet or
+ * not compatible with the device */
+/** @} VL53L0X_define_Error_group */
+
+
+/** @defgroup VL53L0X_define_DeviceModes_group Defines Device modes
+ * Defines all possible modes for the device
+ * @{
+ */
+typedef uint8_t VL53L0X_DeviceModes;
+
+#define VL53L0X_DEVICEMODE_SINGLE_RANGING ((VL53L0X_DeviceModes) 0)
+#define VL53L0X_DEVICEMODE_CONTINUOUS_RANGING ((VL53L0X_DeviceModes) 1)
+#define VL53L0X_DEVICEMODE_SINGLE_HISTOGRAM ((VL53L0X_DeviceModes) 2)
+#define VL53L0X_DEVICEMODE_CONTINUOUS_TIMED_RANGING ((VL53L0X_DeviceModes) 3)
+#define VL53L0X_DEVICEMODE_SINGLE_ALS ((VL53L0X_DeviceModes) 10)
+#define VL53L0X_DEVICEMODE_GPIO_DRIVE ((VL53L0X_DeviceModes) 20)
+#define VL53L0X_DEVICEMODE_GPIO_OSC ((VL53L0X_DeviceModes) 21)
+/* ... Modes to be added depending on device */
+/** @} VL53L0X_define_DeviceModes_group */
+
+
+
+/** @defgroup VL53L0X_define_HistogramModes_group Defines Histogram modes
+ * Defines all possible Histogram modes for the device
+ * @{
+ */
+typedef uint8_t VL53L0X_HistogramModes;
+
+#define VL53L0X_HISTOGRAMMODE_DISABLED ((VL53L0X_HistogramModes) 0)
+/*!< Histogram Disabled */
+#define VL53L0X_HISTOGRAMMODE_REFERENCE_ONLY ((VL53L0X_HistogramModes) 1)
+/*!< Histogram Reference array only */
+#define VL53L0X_HISTOGRAMMODE_RETURN_ONLY ((VL53L0X_HistogramModes) 2)
+/*!< Histogram Return array only */
+#define VL53L0X_HISTOGRAMMODE_BOTH ((VL53L0X_HistogramModes) 3)
+/*!< Histogram both Reference and Return Arrays */
+/* ... Modes to be added depending on device */
+/** @} VL53L0X_define_HistogramModes_group */
+
+
+/** @defgroup VL53L0X_define_PowerModes_group List of available Power Modes
+ * List of available Power Modes
+ * @{
+ */
+
+typedef uint8_t VL53L0X_PowerModes;
+
+#define VL53L0X_POWERMODE_STANDBY_LEVEL1 ((VL53L0X_PowerModes) 0)
+/*!< Standby level 1 */
+#define VL53L0X_POWERMODE_STANDBY_LEVEL2 ((VL53L0X_PowerModes) 1)
+/*!< Standby level 2 */
+#define VL53L0X_POWERMODE_IDLE_LEVEL1 ((VL53L0X_PowerModes) 2)
+/*!< Idle level 1 */
+#define VL53L0X_POWERMODE_IDLE_LEVEL2 ((VL53L0X_PowerModes) 3)
+/*!< Idle level 2 */
+
+/** @} VL53L0X_define_PowerModes_group */
+
+
+/** @brief Defines all parameters for the device
+ */
+typedef struct {
+ VL53L0X_DeviceModes DeviceMode;
+ /*!< Defines type of measurement to be done for the next measure */
+ VL53L0X_HistogramModes HistogramMode;
+ /*!< Defines type of histogram measurement to be done for the next
+ * measure */
+ uint32_t MeasurementTimingBudgetMicroSeconds;
+ /*!< Defines the allowed total time for a single measurement */
+ uint32_t InterMeasurementPeriodMilliSeconds;
+ /*!< Defines time between two consecutive measurements (between two
+ * measurement starts). If set to 0 means back-to-back mode */
+ uint8_t XTalkCompensationEnable;
+ /*!< Tells if Crosstalk compensation shall be enable or not */
+ uint16_t XTalkCompensationRangeMilliMeter;
+ /*!< CrossTalk compensation range in millimeter */
+ FixPoint1616_t XTalkCompensationRateMegaCps;
+ /*!< CrossTalk compensation rate in Mega counts per seconds.
+ * Expressed in 16.16 fixed point format. */
+ int32_t RangeOffsetMicroMeters;
+ /*!< Range offset adjustment (mm). */
+
+ uint8_t LimitChecksEnable[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
+ /*!< This Array store all the Limit Check enable for this device. */
+ uint8_t LimitChecksStatus[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
+ /*!< This Array store all the Status of the check linked to last
+ * measurement. */
+ FixPoint1616_t LimitChecksValue[VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS];
+ /*!< This Array store all the Limit Check value for this device */
+
+ uint8_t WrapAroundCheckEnable;
+ /*!< Tells if Wrap Around Check shall be enable or not */
+} VL53L0X_DeviceParameters_t;
+
+
+/** @defgroup VL53L0X_define_State_group Defines the current status of the device
+ * Defines the current status of the device
+ * @{
+ */
+
+typedef uint8_t VL53L0X_State;
+
+#define VL53L0X_STATE_POWERDOWN ((VL53L0X_State) 0)
+/*!< Device is in HW reset */
+#define VL53L0X_STATE_WAIT_STATICINIT ((VL53L0X_State) 1)
+/*!< Device is initialized and wait for static initialization */
+#define VL53L0X_STATE_STANDBY ((VL53L0X_State) 2)
+/*!< Device is in Low power Standby mode */
+#define VL53L0X_STATE_IDLE ((VL53L0X_State) 3)
+/*!< Device has been initialized and ready to do measurements */
+#define VL53L0X_STATE_RUNNING ((VL53L0X_State) 4)
+/*!< Device is performing measurement */
+#define VL53L0X_STATE_UNKNOWN ((VL53L0X_State) 98)
+/*!< Device is in unknown state and need to be rebooted */
+#define VL53L0X_STATE_ERROR ((VL53L0X_State) 99)
+/*!< Device is in error state and need to be rebooted */
+
+/** @} VL53L0X_define_State_group */
+
+
+/** @brief Structure containing the Dmax computation parameters and data
+ */
+typedef struct {
+ int32_t AmbTuningWindowFactor_K;
+ /*!< internal algo tuning (*1000) */
+ int32_t RetSignalAt0mm;
+ /*!< intermediate dmax computation value caching */
+} VL53L0X_DMaxData_t;
+
+/**
+ * @struct VL53L0X_RangeData_t
+ * @brief Range measurement data.
+ */
+typedef struct {
+ uint32_t TimeStamp; /*!< 32-bit time stamp. */
+ uint32_t MeasurementTimeUsec;
+ /*!< Give the Measurement time needed by the device to do the
+ * measurement.*/
+
+
+ uint16_t RangeMilliMeter; /*!< range distance in millimeter. */
+
+ uint16_t RangeDMaxMilliMeter;
+ /*!< Tells what is the maximum detection distance of the device
+ * in current setup and environment conditions (Filled when
+ * applicable) */
+
+ FixPoint1616_t SignalRateRtnMegaCps;
+ /*!< Return signal rate (MCPS)\n these is a 16.16 fix point
+ * value, which is effectively a measure of target
+ * reflectance.*/
+ FixPoint1616_t AmbientRateRtnMegaCps;
+ /*!< Return ambient rate (MCPS)\n these is a 16.16 fix point
+ * value, which is effectively a measure of the ambien
+ * t light.*/
+
+ uint16_t EffectiveSpadRtnCount;
+ /*!< Return the effective SPAD count for the return signal.
+ * To obtain Real value it should be divided by 256 */
+
+ uint8_t ZoneId;
+ /*!< Denotes which zone and range scheduler stage the range
+ * data relates to. */
+ uint8_t RangeFractionalPart;
+ /*!< Fractional part of range distance. Final value is a
+ * FixPoint168 value. */
+ uint8_t RangeStatus;
+ /*!< Range Status for the current measurement. This is device
+ * dependent. Value = 0 means value is valid.
+ * See \ref RangeStatusPage */
+} VL53L0X_RangingMeasurementData_t;
+
+
+#define VL53L0X_HISTOGRAM_BUFFER_SIZE 24
+
+/**
+ * @struct VL53L0X_HistogramData_t
+ * @brief Histogram measurement data.
+ */
+typedef struct {
+ /* Histogram Measurement data */
+ uint32_t HistogramData[VL53L0X_HISTOGRAM_BUFFER_SIZE];
+ /*!< Histogram data */
+ uint8_t HistogramType; /*!< Indicate the types of histogram data :
+ Return only, Reference only, both Return and Reference */
+ uint8_t FirstBin; /*!< First Bin value */
+ uint8_t BufferSize; /*!< Buffer Size - Set by the user.*/
+ uint8_t NumberOfBins;
+ /*!< Number of bins filled by the histogram measurement */
+
+ VL53L0X_DeviceError ErrorStatus;
+ /*!< Error status of the current measurement. \n
+ see @a ::VL53L0X_DeviceError @a VL53L0X_GetStatusErrorString() */
+} VL53L0X_HistogramMeasurementData_t;
+
+#define VL53L0X_REF_SPAD_BUFFER_SIZE 6
+
+/**
+ * @struct VL53L0X_SpadData_t
+ * @brief Spad Configuration Data.
+ */
+typedef struct {
+ uint8_t RefSpadEnables[VL53L0X_REF_SPAD_BUFFER_SIZE];
+ /*!< Reference Spad Enables */
+ uint8_t RefGoodSpadMap[VL53L0X_REF_SPAD_BUFFER_SIZE];
+ /*!< Reference Spad Good Spad Map */
+} VL53L0X_SpadData_t;
+
+typedef struct {
+ FixPoint1616_t OscFrequencyMHz; /* Frequency used */
+
+ uint16_t LastEncodedTimeout;
+ /* last encoded Time out used for timing budget*/
+
+ VL53L0X_GpioFunctionality Pin0GpioFunctionality;
+ /* store the functionality of the GPIO: pin0 */
+
+ uint32_t FinalRangeTimeoutMicroSecs;
+ /*!< Execution time of the final range*/
+ uint8_t FinalRangeVcselPulsePeriod;
+ /*!< Vcsel pulse period (pll clocks) for the final range measurement*/
+ uint32_t PreRangeTimeoutMicroSecs;
+ /*!< Execution time of the final range*/
+ uint8_t PreRangeVcselPulsePeriod;
+ /*!< Vcsel pulse period (pll clocks) for the pre-range measurement*/
+
+ uint16_t SigmaEstRefArray;
+ /*!< Reference array sigma value in 1/100th of [mm] e.g. 100 = 1mm */
+ uint16_t SigmaEstEffPulseWidth;
+ /*!< Effective Pulse width for sigma estimate in 1/100th
+ * of ns e.g. 900 = 9.0ns */
+ uint16_t SigmaEstEffAmbWidth;
+ /*!< Effective Ambient width for sigma estimate in 1/100th of ns
+ * e.g. 500 = 5.0ns */
+
+
+ uint8_t ReadDataFromDeviceDone; /* Indicate if read from device has
+ been done (==1) or not (==0) */
+ uint8_t ModuleId; /* Module ID */
+ uint8_t Revision; /* test Revision */
+ char ProductId[VL53L0X_MAX_STRING_LENGTH];
+ /* Product Identifier String */
+ uint8_t ReferenceSpadCount; /* used for ref spad management */
+ uint8_t ReferenceSpadType; /* used for ref spad management */
+ uint8_t RefSpadsInitialised; /* reports if ref spads are initialised. */
+ uint32_t PartUIDUpper; /*!< Unique Part ID Upper */
+ uint32_t PartUIDLower; /*!< Unique Part ID Lower */
+ FixPoint1616_t SignalRateMeasFixed400mm; /*!< Peek Signal rate
+ at 400 mm*/
+
+} VL53L0X_DeviceSpecificParameters_t;
+
+/**
+ * @struct VL53L0X_DevData_t
+ *
+ * @brief VL53L0X PAL device ST private data structure \n
+ * End user should never access any of these field directly
+ *
+ * These must never access directly but only via macro
+ */
+typedef struct {
+ VL53L0X_DMaxData_t DMaxData;
+ /*!< Dmax Data */
+ int32_t Part2PartOffsetNVMMicroMeter;
+ /*!< backed up NVM value */
+ int32_t Part2PartOffsetAdjustmentNVMMicroMeter;
+ /*!< backed up NVM value representing additional offset adjustment */
+ VL53L0X_DeviceParameters_t CurrentParameters;
+ /*!< Current Device Parameter */
+ VL53L0X_RangingMeasurementData_t LastRangeMeasure;
+ /*!< Ranging Data */
+ VL53L0X_HistogramMeasurementData_t LastHistogramMeasure;
+ /*!< Histogram Data */
+ VL53L0X_DeviceSpecificParameters_t DeviceSpecificParameters;
+ /*!< Parameters specific to the device */
+ VL53L0X_SpadData_t SpadData;
+ /*!< Spad Data */
+ uint8_t SequenceConfig;
+ /*!< Internal value for the sequence config */
+ uint8_t RangeFractionalEnable;
+ /*!< Enable/Disable fractional part of ranging data */
+ VL53L0X_State PalState;
+ /*!< Current state of the PAL for this device */
+ VL53L0X_PowerModes PowerMode;
+ /*!< Current Power Mode */
+ uint16_t SigmaEstRefArray;
+ /*!< Reference array sigma value in 1/100th of [mm] e.g. 100 = 1mm */
+ uint16_t SigmaEstEffPulseWidth;
+ /*!< Effective Pulse width for sigma estimate in 1/100th
+ * of ns e.g. 900 = 9.0ns */
+ uint16_t SigmaEstEffAmbWidth;
+ /*!< Effective Ambient width for sigma estimate in 1/100th of ns
+ * e.g. 500 = 5.0ns */
+ uint8_t StopVariable;
+ /*!< StopVariable used during the stop sequence */
+ uint16_t targetRefRate;
+ /*!< Target Ambient Rate for Ref spad management */
+ FixPoint1616_t SigmaEstimate;
+ /*!< Sigma Estimate - based on ambient & VCSEL rates and
+ * signal_total_events */
+ FixPoint1616_t SignalEstimate;
+ /*!< Signal Estimate - based on ambient & VCSEL rates and cross talk */
+ FixPoint1616_t LastSignalRefMcps;
+ /*!< Latest Signal ref in Mcps */
+ uint8_t *pTuningSettingsPointer;
+ /*!< Pointer for Tuning Settings table */
+ uint8_t UseInternalTuningSettings;
+ /*!< Indicate if we use Tuning Settings table */
+ uint16_t LinearityCorrectiveGain;
+ /*!< Linearity Corrective Gain value in x1000 */
+ uint16_t DmaxCalRangeMilliMeter;
+ /*!< Dmax Calibration Range millimeter */
+ FixPoint1616_t DmaxCalSignalRateRtnMegaCps;
+ /*!< Dmax Calibration Signal Rate Return MegaCps */
+
+} VL53L0X_DevData_t;
+
+
+/** @defgroup VL53L0X_define_InterruptPolarity_group Defines the Polarity
+ * of the Interrupt
+ * Defines the Polarity of the Interrupt
+ * @{
+ */
+typedef uint8_t VL53L0X_InterruptPolarity;
+
+#define VL53L0X_INTERRUPTPOLARITY_LOW ((VL53L0X_InterruptPolarity) 0)
+/*!< Set active low polarity best setup for falling edge. */
+#define VL53L0X_INTERRUPTPOLARITY_HIGH ((VL53L0X_InterruptPolarity) 1)
+/*!< Set active high polarity best setup for rising edge. */
+
+/** @} VL53L0X_define_InterruptPolarity_group */
+
+
+/** @defgroup VL53L0X_define_VcselPeriod_group Vcsel Period Defines
+ * Defines the range measurement for which to access the vcsel period.
+ * @{
+ */
+typedef uint8_t VL53L0X_VcselPeriod;
+
+#define VL53L0X_VCSEL_PERIOD_PRE_RANGE ((VL53L0X_VcselPeriod) 0)
+/*!<Identifies the pre-range vcsel period. */
+#define VL53L0X_VCSEL_PERIOD_FINAL_RANGE ((VL53L0X_VcselPeriod) 1)
+/*!<Identifies the final range vcsel period. */
+
+/** @} VL53L0X_define_VcselPeriod_group */
+
+/** @defgroup VL53L0X_define_SchedulerSequence_group Defines the steps
+ * carried out by the scheduler during a range measurement.
+ * @{
+ * Defines the states of all the steps in the scheduler
+ * i.e. enabled/disabled.
+ */
+typedef struct {
+ uint8_t TccOn; /*!<Reports if Target Centre Check On */
+ uint8_t MsrcOn; /*!<Reports if MSRC On */
+ uint8_t DssOn; /*!<Reports if DSS On */
+ uint8_t PreRangeOn; /*!<Reports if Pre-Range On */
+ uint8_t FinalRangeOn; /*!<Reports if Final-Range On */
+} VL53L0X_SchedulerSequenceSteps_t;
+
+/** @} VL53L0X_define_SchedulerSequence_group */
+
+/** @defgroup VL53L0X_define_SequenceStepId_group Defines the Polarity
+ * of the Interrupt
+ * Defines the the sequence steps performed during ranging..
+ * @{
+ */
+typedef uint8_t VL53L0X_SequenceStepId;
+
+#define VL53L0X_SEQUENCESTEP_TCC ((VL53L0X_VcselPeriod) 0)
+/*!<Target CentreCheck identifier. */
+#define VL53L0X_SEQUENCESTEP_DSS ((VL53L0X_VcselPeriod) 1)
+/*!<Dynamic Spad Selection function Identifier. */
+#define VL53L0X_SEQUENCESTEP_MSRC ((VL53L0X_VcselPeriod) 2)
+/*!<Minimum Signal Rate Check function Identifier. */
+#define VL53L0X_SEQUENCESTEP_PRE_RANGE ((VL53L0X_VcselPeriod) 3)
+/*!<Pre-Range check Identifier. */
+#define VL53L0X_SEQUENCESTEP_FINAL_RANGE ((VL53L0X_VcselPeriod) 4)
+/*!<Final Range Check Identifier. */
+
+#define VL53L0X_SEQUENCESTEP_NUMBER_OF_CHECKS 5
+/*!<Number of Sequence Step Managed by the API. */
+
+/** @} VL53L0X_define_SequenceStepId_group */
+
+
+/* MACRO Definitions */
+/** @defgroup VL53L0X_define_GeneralMacro_group General Macro Defines
+ * General Macro Defines
+ * @{
+ */
+
+/* Defines */
+#define VL53L0X_SETPARAMETERFIELD(Dev, field, value) \
+ PALDevDataSet(Dev, CurrentParameters.field, value)
+
+#define VL53L0X_GETPARAMETERFIELD(Dev, field, variable) \
+ variable = PALDevDataGet(Dev, CurrentParameters).field
+
+
+#define VL53L0X_SETARRAYPARAMETERFIELD(Dev, field, index, value) \
+ PALDevDataSet(Dev, CurrentParameters.field[index], value)
+
+#define VL53L0X_GETARRAYPARAMETERFIELD(Dev, field, index, variable) \
+ variable = PALDevDataGet(Dev, CurrentParameters).field[index]
+
+
+#define VL53L0X_SETDEVICESPECIFICPARAMETER(Dev, field, value) \
+ PALDevDataSet(Dev, DeviceSpecificParameters.field, value)
+
+#define VL53L0X_GETDEVICESPECIFICPARAMETER(Dev, field) \
+ PALDevDataGet(Dev, DeviceSpecificParameters).field
+
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT97(Value) \
+ (uint16_t)((Value>>9)&0xFFFF)
+#define VL53L0X_FIXPOINT97TOFIXPOINT1616(Value) \
+ (FixPoint1616_t)(Value<<9)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT88(Value) \
+ (uint16_t)((Value>>8)&0xFFFF)
+#define VL53L0X_FIXPOINT88TOFIXPOINT1616(Value) \
+ (FixPoint1616_t)(Value<<8)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT412(Value) \
+ (uint16_t)((Value>>4)&0xFFFF)
+#define VL53L0X_FIXPOINT412TOFIXPOINT1616(Value) \
+ (FixPoint1616_t)(Value<<4)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT313(Value) \
+ (uint16_t)((Value>>3)&0xFFFF)
+#define VL53L0X_FIXPOINT313TOFIXPOINT1616(Value) \
+ (FixPoint1616_t)(Value<<3)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT08(Value) \
+ (uint8_t)((Value>>8)&0x00FF)
+#define VL53L0X_FIXPOINT08TOFIXPOINT1616(Value) \
+ (FixPoint1616_t)(Value<<8)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT53(Value) \
+ (uint8_t)((Value>>13)&0x00FF)
+#define VL53L0X_FIXPOINT53TOFIXPOINT1616(Value) \
+ (FixPoint1616_t)(Value<<13)
+
+#define VL53L0X_FIXPOINT1616TOFIXPOINT102(Value) \
+ (uint16_t)((Value>>14)&0x0FFF)
+#define VL53L0X_FIXPOINT102TOFIXPOINT1616(Value) \
+ (FixPoint1616_t)(Value<<12)
+
+#define VL53L0X_MAKEUINT16(lsb, msb) (uint16_t)((((uint16_t)msb)<<8) + \
+ (uint16_t)lsb)
+
+/** @} VL53L0X_define_GeneralMacro_group */
+
+/** @} VL53L0X_globaldefine_group */
+
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _VL53L0X_DEF_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_device.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,257 @@
+/*******************************************************************************
+Copyright © 2016, STMicroelectronics International N.V.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/**
+ * Device specific defines. To be adapted by implementer for the targeted
+ * device.
+ */
+
+#ifndef _VL53L0X_DEVICE_H_
+#define _VL53L0X_DEVICE_H_
+
+#include "VL53L0X_types.h"
+
+
+/** @defgroup VL53L0X_DevSpecDefines_group VL53L0X cut1.1 Device Specific Defines
+ * @brief VL53L0X cut1.1 Device Specific Defines
+ * @{
+ */
+
+
+/** @defgroup VL53L0X_DeviceError_group Device Error
+ * @brief Device Error code
+ *
+ * This enum is Device specific it should be updated in the implementation
+ * Use @a VL53L0X_GetStatusErrorString() to get the string.
+ * It is related to Status Register of the Device.
+ * @{
+ */
+typedef uint8_t VL53L0X_DeviceError;
+
+#define VL53L0X_DEVICEERROR_NONE ((VL53L0X_DeviceError) 0)
+/*!< 0 NoError */
+#define VL53L0X_DEVICEERROR_VCSELCONTINUITYTESTFAILURE ((VL53L0X_DeviceError) 1)
+#define VL53L0X_DEVICEERROR_VCSELWATCHDOGTESTFAILURE ((VL53L0X_DeviceError) 2)
+#define VL53L0X_DEVICEERROR_NOVHVVALUEFOUND ((VL53L0X_DeviceError) 3)
+#define VL53L0X_DEVICEERROR_MSRCNOTARGET ((VL53L0X_DeviceError) 4)
+#define VL53L0X_DEVICEERROR_SNRCHECK ((VL53L0X_DeviceError) 5)
+#define VL53L0X_DEVICEERROR_RANGEPHASECHECK ((VL53L0X_DeviceError) 6)
+#define VL53L0X_DEVICEERROR_SIGMATHRESHOLDCHECK ((VL53L0X_DeviceError) 7)
+#define VL53L0X_DEVICEERROR_TCC ((VL53L0X_DeviceError) 8)
+#define VL53L0X_DEVICEERROR_PHASECONSISTENCY ((VL53L0X_DeviceError) 9)
+#define VL53L0X_DEVICEERROR_MINCLIP ((VL53L0X_DeviceError) 10)
+#define VL53L0X_DEVICEERROR_RANGECOMPLETE ((VL53L0X_DeviceError) 11)
+#define VL53L0X_DEVICEERROR_ALGOUNDERFLOW ((VL53L0X_DeviceError) 12)
+#define VL53L0X_DEVICEERROR_ALGOOVERFLOW ((VL53L0X_DeviceError) 13)
+#define VL53L0X_DEVICEERROR_RANGEIGNORETHRESHOLD ((VL53L0X_DeviceError) 14)
+
+/** @} end of VL53L0X_DeviceError_group */
+
+
+/** @defgroup VL53L0X_CheckEnable_group Check Enable list
+ * @brief Check Enable code
+ *
+ * Define used to specify the LimitCheckId.
+ * Use @a VL53L0X_GetLimitCheckInfo() to get the string.
+ * @{
+ */
+
+#define VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE 0
+#define VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE 1
+#define VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP 2
+#define VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD 3
+#define VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC 4
+#define VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE 5
+
+#define VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS 6
+
+/** @} end of VL53L0X_CheckEnable_group */
+
+
+/** @defgroup VL53L0X_GpioFunctionality_group Gpio Functionality
+ * @brief Defines the different functionalities for the device GPIO(s)
+ * @{
+ */
+typedef uint8_t VL53L0X_GpioFunctionality;
+
+#define VL53L0X_GPIOFUNCTIONALITY_OFF \
+ ((VL53L0X_GpioFunctionality) 0) /*!< NO Interrupt */
+#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW \
+ ((VL53L0X_GpioFunctionality) 1) /*!< Level Low (value < thresh_low) */
+#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH \
+ ((VL53L0X_GpioFunctionality) 2) /*!< Level High (value > thresh_high) */
+#define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT \
+ ((VL53L0X_GpioFunctionality) 3)
+/*!< Out Of Window (value < thresh_low OR value > thresh_high) */
+#define VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY \
+ ((VL53L0X_GpioFunctionality) 4) /*!< New Sample Ready */
+
+/** @} end of VL53L0X_GpioFunctionality_group */
+
+
+/* Device register map */
+
+/** @defgroup VL53L0X_DefineRegisters_group Define Registers
+ * @brief List of all the defined registers
+ * @{
+ */
+#define VL53L0X_REG_SYSRANGE_START 0x000
+/** mask existing bit in #VL53L0X_REG_SYSRANGE_START*/
+#define VL53L0X_REG_SYSRANGE_MODE_MASK 0x0F
+/** bit 0 in #VL53L0X_REG_SYSRANGE_START write 1 toggle state in
+ * continuous mode and arm next shot in single shot mode */
+#define VL53L0X_REG_SYSRANGE_MODE_START_STOP 0x01
+/** bit 1 write 0 in #VL53L0X_REG_SYSRANGE_START set single shot mode */
+#define VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT 0x00
+/** bit 1 write 1 in #VL53L0X_REG_SYSRANGE_START set back-to-back
+ * operation mode */
+#define VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK 0x02
+/** bit 2 write 1 in #VL53L0X_REG_SYSRANGE_START set timed operation
+ * mode */
+#define VL53L0X_REG_SYSRANGE_MODE_TIMED 0x04
+/** bit 3 write 1 in #VL53L0X_REG_SYSRANGE_START set histogram operation
+ * mode */
+#define VL53L0X_REG_SYSRANGE_MODE_HISTOGRAM 0x08
+
+
+#define VL53L0X_REG_SYSTEM_THRESH_HIGH 0x000C
+#define VL53L0X_REG_SYSTEM_THRESH_LOW 0x000E
+
+
+#define VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG 0x0001
+#define VL53L0X_REG_SYSTEM_RANGE_CONFIG 0x0009
+#define VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD 0x0004
+
+
+#define VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO 0x000A
+#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_DISABLED 0x00
+#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_LOW 0x01
+#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_HIGH 0x02
+#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_OUT_OF_WINDOW 0x03
+#define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY 0x04
+
+#define VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH 0x0084
+
+
+#define VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR 0x000B
+
+/* Result registers */
+#define VL53L0X_REG_RESULT_INTERRUPT_STATUS 0x0013
+#define VL53L0X_REG_RESULT_RANGE_STATUS 0x0014
+
+#define VL53L0X_REG_RESULT_CORE_PAGE 1
+#define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN 0x00BC
+#define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN 0x00C0
+#define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF 0x00D0
+#define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_REF 0x00D4
+#define VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF 0x00B6
+
+/* Algo register */
+
+#define VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM 0x0028
+
+#define VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS 0x008a
+
+/* Check Limit registers */
+#define VL53L0X_REG_MSRC_CONFIG_CONTROL 0x0060
+
+#define VL53L0X_REG_PRE_RANGE_CONFIG_MIN_SNR 0X0027
+#define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW 0x0056
+#define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH 0x0057
+#define VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT 0x0064
+
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_SNR 0X0067
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW 0x0047
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH 0x0048
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT 0x0044
+
+
+#define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_HI 0X0061
+#define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_LO 0X0062
+
+/* PRE RANGE registers */
+#define VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD 0x0050
+#define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0051
+#define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0052
+
+#define VL53L0X_REG_SYSTEM_HISTOGRAM_BIN 0x0081
+#define VL53L0X_REG_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT 0x0033
+#define VL53L0X_REG_HISTOGRAM_CONFIG_READOUT_CTRL 0x0055
+
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD 0x0070
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0071
+#define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0072
+#define VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS 0x0020
+
+#define VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP 0x0046
+
+
+#define VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N 0x00bf
+#define VL53L0X_REG_IDENTIFICATION_MODEL_ID 0x00c0
+#define VL53L0X_REG_IDENTIFICATION_REVISION_ID 0x00c2
+
+#define VL53L0X_REG_OSC_CALIBRATE_VAL 0x00f8
+
+
+#define VL53L0X_SIGMA_ESTIMATE_MAX_VALUE 65535
+/* equivalent to a range sigma of 655.35mm */
+
+#define VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH 0x032
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 0x0B0
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_1 0x0B1
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_2 0x0B2
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_3 0x0B3
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_4 0x0B4
+#define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_5 0x0B5
+
+#define VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT 0xB6
+#define VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD 0x4E /* 0x14E */
+#define VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET 0x4F /* 0x14F */
+#define VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE 0x80
+
+/*
+ * Speed of light in um per 1E-10 Seconds
+ */
+
+#define VL53L0X_SPEED_OF_LIGHT_IN_AIR 2997
+
+#define VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV 0x0089
+
+#define VL53L0X_REG_ALGO_PHASECAL_LIM 0x0030 /* 0x130 */
+#define VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT 0x0030
+
+/** @} VL53L0X_DefineRegisters_group */
+
+/** @} VL53L0X_DevSpecDefines_group */
+
+
+#endif
+
+/* _VL53L0X_DEVICE_H_ */
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_interrupt_threshold_settings.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,195 @@
+/*******************************************************************************
+Copyright © 2016, STMicroelectronics International N.V.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+
+#ifndef _VL53L0X_INTERRUPT_THRESHOLD_SETTINGS_H_
+#define _VL53L0X_INTERRUPT_THRESHOLD_SETTINGS_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+uint8_t InterruptThresholdSettings[] = {
+
+ /* Start of Interrupt Threshold Settings */
+ 0x1, 0xff, 0x00,
+ 0x1, 0x80, 0x01,
+ 0x1, 0xff, 0x01,
+ 0x1, 0x00, 0x00,
+ 0x1, 0xff, 0x01,
+ 0x1, 0x4f, 0x02,
+ 0x1, 0xFF, 0x0E,
+ 0x1, 0x00, 0x03,
+ 0x1, 0x01, 0x84,
+ 0x1, 0x02, 0x0A,
+ 0x1, 0x03, 0x03,
+ 0x1, 0x04, 0x08,
+ 0x1, 0x05, 0xC8,
+ 0x1, 0x06, 0x03,
+ 0x1, 0x07, 0x8D,
+ 0x1, 0x08, 0x08,
+ 0x1, 0x09, 0xC6,
+ 0x1, 0x0A, 0x01,
+ 0x1, 0x0B, 0x02,
+ 0x1, 0x0C, 0x00,
+ 0x1, 0x0D, 0xD5,
+ 0x1, 0x0E, 0x18,
+ 0x1, 0x0F, 0x12,
+ 0x1, 0x10, 0x01,
+ 0x1, 0x11, 0x82,
+ 0x1, 0x12, 0x00,
+ 0x1, 0x13, 0xD5,
+ 0x1, 0x14, 0x18,
+ 0x1, 0x15, 0x13,
+ 0x1, 0x16, 0x03,
+ 0x1, 0x17, 0x86,
+ 0x1, 0x18, 0x0A,
+ 0x1, 0x19, 0x09,
+ 0x1, 0x1A, 0x08,
+ 0x1, 0x1B, 0xC2,
+ 0x1, 0x1C, 0x03,
+ 0x1, 0x1D, 0x8F,
+ 0x1, 0x1E, 0x0A,
+ 0x1, 0x1F, 0x06,
+ 0x1, 0x20, 0x01,
+ 0x1, 0x21, 0x02,
+ 0x1, 0x22, 0x00,
+ 0x1, 0x23, 0xD5,
+ 0x1, 0x24, 0x18,
+ 0x1, 0x25, 0x22,
+ 0x1, 0x26, 0x01,
+ 0x1, 0x27, 0x82,
+ 0x1, 0x28, 0x00,
+ 0x1, 0x29, 0xD5,
+ 0x1, 0x2A, 0x18,
+ 0x1, 0x2B, 0x0B,
+ 0x1, 0x2C, 0x28,
+ 0x1, 0x2D, 0x78,
+ 0x1, 0x2E, 0x28,
+ 0x1, 0x2F, 0x91,
+ 0x1, 0x30, 0x00,
+ 0x1, 0x31, 0x0B,
+ 0x1, 0x32, 0x00,
+ 0x1, 0x33, 0x0B,
+ 0x1, 0x34, 0x00,
+ 0x1, 0x35, 0xA1,
+ 0x1, 0x36, 0x00,
+ 0x1, 0x37, 0xA0,
+ 0x1, 0x38, 0x00,
+ 0x1, 0x39, 0x04,
+ 0x1, 0x3A, 0x28,
+ 0x1, 0x3B, 0x30,
+ 0x1, 0x3C, 0x0C,
+ 0x1, 0x3D, 0x04,
+ 0x1, 0x3E, 0x0F,
+ 0x1, 0x3F, 0x79,
+ 0x1, 0x40, 0x28,
+ 0x1, 0x41, 0x1E,
+ 0x1, 0x42, 0x2F,
+ 0x1, 0x43, 0x87,
+ 0x1, 0x44, 0x00,
+ 0x1, 0x45, 0x0B,
+ 0x1, 0x46, 0x00,
+ 0x1, 0x47, 0x0B,
+ 0x1, 0x48, 0x00,
+ 0x1, 0x49, 0xA7,
+ 0x1, 0x4A, 0x00,
+ 0x1, 0x4B, 0xA6,
+ 0x1, 0x4C, 0x00,
+ 0x1, 0x4D, 0x04,
+ 0x1, 0x4E, 0x01,
+ 0x1, 0x4F, 0x00,
+ 0x1, 0x50, 0x00,
+ 0x1, 0x51, 0x80,
+ 0x1, 0x52, 0x09,
+ 0x1, 0x53, 0x08,
+ 0x1, 0x54, 0x01,
+ 0x1, 0x55, 0x00,
+ 0x1, 0x56, 0x0F,
+ 0x1, 0x57, 0x79,
+ 0x1, 0x58, 0x09,
+ 0x1, 0x59, 0x05,
+ 0x1, 0x5A, 0x00,
+ 0x1, 0x5B, 0x60,
+ 0x1, 0x5C, 0x05,
+ 0x1, 0x5D, 0xD1,
+ 0x1, 0x5E, 0x0C,
+ 0x1, 0x5F, 0x3C,
+ 0x1, 0x60, 0x00,
+ 0x1, 0x61, 0xD0,
+ 0x1, 0x62, 0x0B,
+ 0x1, 0x63, 0x03,
+ 0x1, 0x64, 0x28,
+ 0x1, 0x65, 0x10,
+ 0x1, 0x66, 0x2A,
+ 0x1, 0x67, 0x39,
+ 0x1, 0x68, 0x0B,
+ 0x1, 0x69, 0x02,
+ 0x1, 0x6A, 0x28,
+ 0x1, 0x6B, 0x10,
+ 0x1, 0x6C, 0x2A,
+ 0x1, 0x6D, 0x61,
+ 0x1, 0x6E, 0x0C,
+ 0x1, 0x6F, 0x00,
+ 0x1, 0x70, 0x0F,
+ 0x1, 0x71, 0x79,
+ 0x1, 0x72, 0x00,
+ 0x1, 0x73, 0x0B,
+ 0x1, 0x74, 0x00,
+ 0x1, 0x75, 0x0B,
+ 0x1, 0x76, 0x00,
+ 0x1, 0x77, 0xA1,
+ 0x1, 0x78, 0x00,
+ 0x1, 0x79, 0xA0,
+ 0x1, 0x7A, 0x00,
+ 0x1, 0x7B, 0x04,
+ 0x1, 0xFF, 0x04,
+ 0x1, 0x79, 0x1D,
+ 0x1, 0x7B, 0x27,
+ 0x1, 0x96, 0x0E,
+ 0x1, 0x97, 0xFE,
+ 0x1, 0x98, 0x03,
+ 0x1, 0x99, 0xEF,
+ 0x1, 0x9A, 0x02,
+ 0x1, 0x9B, 0x44,
+ 0x1, 0x73, 0x07,
+ 0x1, 0x70, 0x01,
+ 0x1, 0xff, 0x01,
+ 0x1, 0x00, 0x01,
+ 0x1, 0xff, 0x00,
+ 0x00, 0x00, 0x00
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _VL53L0X_INTERRUPT_THRESHOLD_SETTINGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_platform.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,242 @@
+/*******************************************************************************
+Copyright © 2015, STMicroelectronics International N.V.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+********************************************************************************/
+
+
+#ifndef _VL53L0X_PLATFORM_H_
+#define _VL53L0X_PLATFORM_H_
+
+#include "VL53L0X_def.h"
+#include "VL53L0X_platform_log.h"
+//#include "VL53L0X_i2c_platform.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file vl53l0_platform.h
+ *
+ * @brief All end user OS/platform/application porting
+ */
+
+/**
+ * @defgroup VL53L0X_platform_group VL53L0 Platform Functions
+ * @brief VL53L0 Platform Functions
+ * @{
+ */
+
+/**
+ * @struct VL53L0X_Dev_t
+ * @brief Generic PAL device type that does link between API and platform abstraction layer
+ *
+ */
+typedef struct {
+ VL53L0X_DevData_t Data; /*!< embed ST Ewok Dev data as "Data"*/
+
+ /*!< user specific field */
+ uint8_t I2cDevAddr; /*!< i2c device address user specific field */
+ uint8_t comms_type; /*!< Type of comms : VL53L0X_COMMS_I2C or VL53L0X_COMMS_SPI */
+ uint16_t comms_speed_khz; /*!< Comms speed [kHz] : typically 400kHz for I2C */
+
+} VL53L0X_Dev_t;
+
+
+/**
+ * @brief Declare the device Handle as a pointer of the structure @a VL53L0X_Dev_t.
+ *
+ */
+typedef VL53L0X_Dev_t *VL53L0X_DEV;
+
+/**
+ * @def PALDevDataGet
+ * @brief Get ST private structure @a VL53L0X_DevData_t data access
+ *
+ * @param Dev Device Handle
+ * @param field ST structure field name
+ * It maybe used and as real data "ref" not just as "get" for sub-structure item
+ * like PALDevDataGet(FilterData.field)[i] or PALDevDataGet(FilterData.MeasurementIndex)++
+ */
+#define PALDevDataGet(Dev, field) (Dev->Data.field)
+
+/**
+ * @def PALDevDataSet(Dev, field, data)
+ * @brief Set ST private structure @a VL53L0X_DevData_t data field
+ * @param Dev Device Handle
+ * @param field ST structure field name
+ * @param data Data to be set
+ */
+#define PALDevDataSet(Dev, field, data) (Dev->Data.field)=(data)
+
+
+/**
+ * @defgroup VL53L0X_registerAccess_group PAL Register Access Functions
+ * @brief PAL Register Access Functions
+ * @{
+ */
+
+/**
+ * Lock comms interface to serialize all commands to a shared I2C interface for a specific device
+ * @param Dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_LockSequenceAccess(VL53L0X_DEV Dev);
+
+/**
+ * Unlock comms interface to serialize all commands to a shared I2C interface for a specific device
+ * @param Dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_UnlockSequenceAccess(VL53L0X_DEV Dev);
+
+
+/**
+ * Writes the supplied byte buffer to the device
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param pdata Pointer to uint8_t buffer containing the data to be written
+ * @param count Number of bytes in the supplied byte buffer
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_WriteMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count);
+
+/**
+ * Reads the requested number of bytes from the device
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param pdata Pointer to the uint8_t buffer to store read data
+ * @param count Number of uint8_t's to read
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_ReadMulti(VL53L0X_DEV Dev, uint8_t index, uint8_t *pdata, uint32_t count);
+
+/**
+ * Write single byte register
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param data 8 bit register data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_WrByte(VL53L0X_DEV Dev, uint8_t index, uint8_t data);
+
+/**
+ * Write word register
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param data 16 bit register data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_WrWord(VL53L0X_DEV Dev, uint8_t index, uint16_t data);
+
+/**
+ * Write double word (4 byte) register
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param data 32 bit register data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_WrDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t data);
+
+/**
+ * Read single byte register
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param data pointer to 8 bit data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_RdByte(VL53L0X_DEV Dev, uint8_t index, uint8_t *data);
+
+/**
+ * Read word (2byte) register
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param data pointer to 16 bit data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_RdWord(VL53L0X_DEV Dev, uint8_t index, uint16_t *data);
+
+/**
+ * Read dword (4byte) register
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param data pointer to 32 bit data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_RdDWord(VL53L0X_DEV Dev, uint8_t index, uint32_t *data);
+
+/**
+ * Threat safe Update (read/modify/write) single byte register
+ *
+ * Final_reg = (Initial_reg & and_data) |or_data
+ *
+ * @param Dev Device Handle
+ * @param index The register index
+ * @param AndData 8 bit and data
+ * @param OrData 8 bit or data
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_UpdateByte(VL53L0X_DEV Dev, uint8_t index, uint8_t AndData, uint8_t OrData);
+
+/** @} end of VL53L0X_registerAccess_group */
+
+
+/**
+ * @brief execute delay in all polling API call
+ *
+ * A typical multi-thread or RTOs implementation is to sleep the task for some 5ms (with 100Hz max rate faster polling is not needed)
+ * if nothing specific is need you can define it as an empty/void macro
+ * @code
+ * #define VL53L0X_PollingDelay(...) (void)0
+ * @endcode
+ * @param Dev Device Handle
+ * @return VL53L0X_ERROR_NONE Success
+ * @return "Other error code" See ::VL53L0X_Error
+ */
+VL53L0X_Error VL53L0X_PollingDelay(VL53L0X_DEV Dev); /* usually best implemented as a real function */
+
+/** @} end of VL53L0X_platform_group */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _VL53L0X_PLATFORM_H_ */
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_platform_log.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,119 @@
+/*******************************************************************************
+Copyright © 2015, STMicroelectronics International N.V.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+********************************************************************************/
+
+
+#ifndef _VL53L0X_PLATFORM_LOG_H_
+#define _VL53L0X_PLATFORM_LOG_H_
+
+#include <stdio.h>
+#include <string.h>
+/* LOG Functions */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file vl53l0_platform_log.h
+ *
+ * @brief platform log function definition
+ */
+
+//#define VL53L0X_LOG_ENABLE 0
+
+enum {
+ TRACE_LEVEL_NONE,
+ TRACE_LEVEL_ERRORS,
+ TRACE_LEVEL_WARNING,
+ TRACE_LEVEL_INFO,
+ TRACE_LEVEL_DEBUG,
+ TRACE_LEVEL_ALL,
+ TRACE_LEVEL_IGNORE
+};
+
+enum {
+ TRACE_FUNCTION_NONE = 0,
+ TRACE_FUNCTION_I2C = 1,
+ TRACE_FUNCTION_ALL = 0x7fffffff //all bits except sign
+};
+
+enum {
+ TRACE_MODULE_NONE = 0x0,
+ TRACE_MODULE_API = 0x1,
+ TRACE_MODULE_PLATFORM = 0x2,
+ TRACE_MODULE_ALL = 0x7fffffff //all bits except sign
+};
+
+
+#ifdef VL53L0X_LOG_ENABLE
+
+#include <sys/time.h>
+
+extern uint32_t _trace_level;
+
+
+
+int32_t VL53L0X_trace_config(char *filename, uint32_t modules, uint32_t level, uint32_t functions);
+
+void trace_print_module_function(uint32_t module, uint32_t level, uint32_t function, const char *format, ...);
+
+
+//extern FILE * log_file;
+
+#define LOG_GET_TIME() (int)clock()
+
+#define _LOG_FUNCTION_START(module, fmt, ... ) \
+ trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <START> %s "fmt"\n", LOG_GET_TIME(), __FUNCTION__, ##__VA_ARGS__);
+
+#define _LOG_FUNCTION_END(module, status, ... )\
+ trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <END> %s %d\n", LOG_GET_TIME(), __FUNCTION__, (int)status, ##__VA_ARGS__)
+
+#define _LOG_FUNCTION_END_FMT(module, status, fmt, ... )\
+ trace_print_module_function(module, _trace_level, TRACE_FUNCTION_ALL, "%ld <END> %s %d "fmt"\n", LOG_GET_TIME(), __FUNCTION__, (int)status,##__VA_ARGS__)
+
+// __func__ is gcc only
+#define VL53L0X_ErrLog( fmt, ...) fprintf(stderr, "VL53L0X_ErrLog %s" fmt "\n", __func__, ##__VA_ARGS__)
+
+#else /* VL53L0X_LOG_ENABLE no logging */
+#define VL53L0X_ErrLog(...) (void)0
+#define _LOG_FUNCTION_START(module, fmt, ... ) (void)0
+#define _LOG_FUNCTION_END(module, status, ... ) (void)0
+#define _LOG_FUNCTION_END_FMT(module, status, fmt, ... ) (void)0
+#endif /* else */
+
+#define VL53L0X_COPYSTRING(str, ...) strcpy(str, ##__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _VL53L0X_PLATFORM_LOG_H_ */
+
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_tuning.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,147 @@
+/*******************************************************************************
+Copyright © 2016, STMicroelectronics International N.V.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+
+#ifndef _VL53L0X_TUNING_H_
+#define _VL53L0X_TUNING_H_
+
+#include "VL53L0X_def.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+uint8_t DefaultTuningSettings[] = {
+
+ /* update 02/11/2015_v36 */
+ 0x01, 0xFF, 0x01,
+ 0x01, 0x00, 0x00,
+
+ 0x01, 0xFF, 0x00,
+ 0x01, 0x09, 0x00,
+ 0x01, 0x10, 0x00,
+ 0x01, 0x11, 0x00,
+
+ 0x01, 0x24, 0x01,
+ 0x01, 0x25, 0xff,
+ 0x01, 0x75, 0x00,
+
+ 0x01, 0xFF, 0x01,
+ 0x01, 0x4e, 0x2c,
+ 0x01, 0x48, 0x00,
+ 0x01, 0x30, 0x20,
+
+ 0x01, 0xFF, 0x00,
+ 0x01, 0x30, 0x09, /* mja changed from 0x64. */
+ 0x01, 0x54, 0x00,
+ 0x01, 0x31, 0x04,
+ 0x01, 0x32, 0x03,
+ 0x01, 0x40, 0x83,
+ 0x01, 0x46, 0x25,
+ 0x01, 0x60, 0x00,
+ 0x01, 0x27, 0x00,
+ 0x01, 0x50, 0x06,
+ 0x01, 0x51, 0x00,
+ 0x01, 0x52, 0x96,
+ 0x01, 0x56, 0x08,
+ 0x01, 0x57, 0x30,
+ 0x01, 0x61, 0x00,
+ 0x01, 0x62, 0x00,
+ 0x01, 0x64, 0x00,
+ 0x01, 0x65, 0x00,
+ 0x01, 0x66, 0xa0,
+
+ 0x01, 0xFF, 0x01,
+ 0x01, 0x22, 0x32,
+ 0x01, 0x47, 0x14,
+ 0x01, 0x49, 0xff,
+ 0x01, 0x4a, 0x00,
+
+ 0x01, 0xFF, 0x00,
+ 0x01, 0x7a, 0x0a,
+ 0x01, 0x7b, 0x00,
+ 0x01, 0x78, 0x21,
+
+ 0x01, 0xFF, 0x01,
+ 0x01, 0x23, 0x34,
+ 0x01, 0x42, 0x00,
+ 0x01, 0x44, 0xff,
+ 0x01, 0x45, 0x26,
+ 0x01, 0x46, 0x05,
+ 0x01, 0x40, 0x40,
+ 0x01, 0x0E, 0x06,
+ 0x01, 0x20, 0x1a,
+ 0x01, 0x43, 0x40,
+
+ 0x01, 0xFF, 0x00,
+ 0x01, 0x34, 0x03,
+ 0x01, 0x35, 0x44,
+
+ 0x01, 0xFF, 0x01,
+ 0x01, 0x31, 0x04,
+ 0x01, 0x4b, 0x09,
+ 0x01, 0x4c, 0x05,
+ 0x01, 0x4d, 0x04,
+
+
+ 0x01, 0xFF, 0x00,
+ 0x01, 0x44, 0x00,
+ 0x01, 0x45, 0x20,
+ 0x01, 0x47, 0x08,
+ 0x01, 0x48, 0x28,
+ 0x01, 0x67, 0x00,
+ 0x01, 0x70, 0x04,
+ 0x01, 0x71, 0x01,
+ 0x01, 0x72, 0xfe,
+ 0x01, 0x76, 0x00,
+ 0x01, 0x77, 0x00,
+
+ 0x01, 0xFF, 0x01,
+ 0x01, 0x0d, 0x01,
+
+ 0x01, 0xFF, 0x00,
+ 0x01, 0x80, 0x01,
+ 0x01, 0x01, 0xF8,
+
+ 0x01, 0xFF, 0x01,
+ 0x01, 0x8e, 0x01,
+ 0x01, 0x00, 0x01,
+ 0x01, 0xFF, 0x00,
+ 0x01, 0x80, 0x00,
+
+ 0x00, 0x00, 0x00
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _VL53L0X_TUNING_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/VL53L0X_simple/VL53L0X_types.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,112 @@
+/*******************************************************************************
+Copyright © 2015, STMicroelectronics International N.V.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of STMicroelectronics nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
+IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+********************************************************************************/
+/**
+ * @file vl53l0_types.h
+ * @brief VL53L0 types definition
+ */
+
+#ifndef VL53L0X_TYPES_H_
+#define VL53L0X_TYPES_H_
+
+/** @defgroup porting_type Basic type definition
+ * @ingroup VL53L0X_platform_group
+ *
+ * @brief file vl53l0_types.h files hold basic type definition that may requires porting
+ *
+ * contains type that must be defined for the platform\n
+ * when target platform and compiler provide stdint.h and stddef.h it is enough to include it.\n
+ * If stdint.h is not available review and adapt all signed and unsigned 8/16/32 bits basic types. \n
+ * If stddef.h is not available review and adapt NULL definition .
+ */
+#include <stdint.h>
+#include <stddef.h>
+
+#ifndef NULL
+#error "Error NULL definition should be done. Please add required include "
+#endif
+
+
+#if ! defined(STDINT_H) && !defined(_GCC_STDINT_H) &&!defined(__STDINT_DECLS) && !defined(_GCC_WRAP_STDINT_H)
+
+#pragma message("Please review type definition of STDINT define for your platform and add to list above ")
+
+/*
+ * target platform do not provide stdint or use a different #define than above
+ * to avoid seeing the message below addapt the #define list above or implement
+ * all type and delete these pragma
+ */
+
+/** \ingroup VL53L0X_portingType_group
+ * @{
+ */
+
+
+typedef unsigned long long uint64_t;
+
+
+/** @brief Typedef defining 32 bit unsigned int type.\n
+ * The developer should modify this to suit the platform being deployed.
+ */
+typedef unsigned int uint32_t;
+
+/** @brief Typedef defining 32 bit int type.\n
+ * The developer should modify this to suit the platform being deployed.
+ */
+typedef int int32_t;
+
+/** @brief Typedef defining 16 bit unsigned short type.\n
+ * The developer should modify this to suit the platform being deployed.
+ */
+typedef unsigned short uint16_t;
+
+/** @brief Typedef defining 16 bit short type.\n
+ * The developer should modify this to suit the platform being deployed.
+ */
+typedef short int16_t;
+
+/** @brief Typedef defining 8 bit unsigned char type.\n
+ * The developer should modify this to suit the platform being deployed.
+ */
+typedef unsigned char uint8_t;
+
+/** @brief Typedef defining 8 bit char type.\n
+ * The developer should modify this to suit the platform being deployed.
+ */
+typedef signed char int8_t;
+
+/** @} */
+#endif /* _STDINT_H */
+
+
+/** use where fractional values are expected
+ *
+ * Given a floating point value f it's .16 bit point is (int)(f*(1<<16))*/
+typedef uint32_t FixPoint1616_t;
+
+#endif /* VL53L0X_TYPES_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,130 @@
+#include "stm32f103c8t6.h"
+#include "mbed.h"
+/*
+ * Mbed Application program
+ * Time-of-Flight ranging and gesture detection sensor / STMicro VL53L0X
+ * http://www.st.com/ja/imaging-and-photonics-solutions/vl53l0x.html
+ *
+ * 1) AKIZUKI AE-VL53L0X
+ * http://akizukidenshi.com/catalog/g/gM-12590/
+ * 2) SWITCH SCIENCE Pololu VL53L0X (POLOLU-2490)
+ * https://www.switch-science.com/catalog/2869/
+ * 3) SWITCH SCIENCE VL53L0X (SSCI-028943)
+ * https://www.switch-science.com/catalog/2894/
+ * 4) Strawberry Linux
+ * https://strawberry-linux.com/catalog/items?code=15310
+ *
+ * ---- Tested AE-VL53L0X BOARD and handmade circuit ----
+ * Tested on below Mbed boards and works fine on mbed 2.0
+ * Nucleo-F303K8
+ * Nucleo-F334R8, -F401RE, -F411RE, -F446RE
+ * Nucleo-L053R8, -L073RZ, -L152RE, -L476RG
+ * FRDM-K64F
+ * TY51822r3
+ * Run also on mbed-os5 (Tested on Nucleo-F446RE)
+ *
+ * Copyright (c) 2018 Kenji Arai / JH1PJL
+ * http://www.page.sannet.ne.jp/kenjia/index.html
+ * http://mbed.org/users/kenjiArai/
+ * Created: January 21st, 2018
+ * Revised: Feburary 6th, 2018 (with updated VL53L0X_simple library)
+ */
+
+// Include --------------------------------------------------------------------
+#include "VL53L0X.h"
+
+// Definition -----------------------------------------------------------------
+#define USE_XSHUT 1
+
+// Constructor ----------------------------------------------------------------
+DigitalOut myled(PA_5);
+DigitalOut CAN_STB(PA_4);
+
+CAN can1(PA_11, PA_12);
+
+Serial pc(USBTX, USBRX, 9600);
+//I2C i2c(P0_30, P0_7); // only for TY51822r3
+I2C i2c(PB_9, PB_8); //placa hensys
+//I2C i2c(PB_11, PB_10); //bluepill
+
+#if USE_XSHUT
+VL53L0X sensor(i2c, PA_8); // XSHUT = D8
+#else
+VL53L0X sensor(i2c, NC); // XSHUT = NC
+#endif
+Timer t;
+
+// RAM ------------------------------------------------------------------------
+
+// ROM / Constant data --------------------------------------------------------
+char *const msg0 = "VL53L0X is running correctly!!\r\n";
+char *const msg1 = "VL53L0X -> something is wrong!!\r\n";
+char *const msg2 = "#,";
+char *const msg3 = "d[mm]=,";
+char *const msg4 = "d[mm]=,error,";
+char *const msg5 = "VL53[mS]=, ";
+char *const msg6 = "all[mS]=, ";
+
+// Function prototypes --------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Control Program
+//------------------------------------------------------------------------------
+int main()
+{
+ char bosta = 1;
+ can1.frequency(500000);
+ CAN_STB = 0;
+ int status = VL53L0X_ERROR_NONE;
+ uint32_t data;
+ uint32_t count = 0;
+ uint32_t tm_sensor;
+ uint32_t tm_all_work;
+
+#if USE_XSHUT
+ status = sensor.init_sensor(0x53); // set new I2C address
+#else
+ // no control XSHUT then set default address (no other way)
+ status = sensor.init_sensor(VL53L0X_DEFAULT_ADDRESS);
+#endif
+ if (status == VL53L0X_ERROR_NONE) {
+ pc.printf(msg0);
+ } else {
+ pc.printf(msg1);
+ }
+ //status = sensor.set_mode(range_long_distance_33ms_200cm);
+ //status = sensor.set_mode(range_hi_accurate_200ms_120cm);
+ status = sensor.set_mode(range_hi_speed_20ms_120cm);
+ if (status == VL53L0X_ERROR_NONE) {
+ pc.printf(msg0);
+ } else {
+ pc.printf(msg1);
+ }
+ while(true) {
+ //can1.write(CANMessage(1337,&bosta,1));
+ //wait(0.2);
+ t.reset();
+ t.start();
+ pc.printf("olar");
+ //myled = !myled;
+ status = sensor.get_distance(&data);
+ tm_sensor = t.read_ms();
+ if (status == VL53L0X_ERROR_NONE) {
+ pc.printf("%s%5d,%s%5d,", msg2, count++, msg3, data);
+ if(data >= 300){
+ myled = 1;
+ can1.write(CANMessage(1337,&bosta,1));
+ wait(0.2);
+ }
+ else {
+ myled = 0;}
+ } else {
+ pc.printf("%s%5d,%s", msg2, count++, msg4);
+ }
+ pc.printf("%s%d,%s%d\r\n", msg5, tm_sensor, msg6, tm_all_work);
+ tm_all_work = t.read_ms();
+ if (tm_all_work < 99){
+ wait_ms(100 - tm_all_work);
+ }
+ }
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-STM32F103C8T6/PinNames.h Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,152 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ *
+ * Modified by Zoltan Hudak 2017
+ *
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ // Ports
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_3 = 0x03,
+ PA_4 = 0x04,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = NC,
+ PA_14 = NC,
+ PA_15 = 0x0F,
+
+ PB_0 = 0x10,
+ PB_1 = 0x11,
+ PB_2 = NC,
+ PB_3 = 0x13,
+ PB_4 = 0x14,
+ PB_5 = 0x15,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_9 = 0x19,
+ PB_10 = 0x1A,
+ PB_11 = 0x1B,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = NC,
+ PC_1 = NC,
+ PC_2 = NC,
+ PC_3 = NC,
+ PC_4 = NC,
+ PC_5 = NC,
+ PC_6 = NC,
+ PC_7 = NC,
+ PC_8 = NC,
+ PC_9 = NC,
+ PC_10 = NC,
+ PC_11 = NC,
+ PC_12 = NC,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_2 = NC,
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+
+ // Arduino connector namings
+ A0 = PA_0,
+ A1 = PA_1,
+ A2 = PA_4,
+ A3 = PB_0,
+ A4 = NC,
+ A5 = NC,
+ D0 = PA_3,
+ D1 = PA_2,
+ D2 = PA_10,
+ D3 = PB_3,
+ D4 = PB_5,
+ D5 = PB_4,
+ D6 = PB_10,
+ D7 = PA_8,
+ D8 = PA_9,
+ D9 = NC,
+ D10 = PB_6,
+ D11 = PA_7,
+ D12 = PA_6,
+ D13 = PA_5,
+ D14 = PB_9,
+ D15 = PB_8,
+
+ // Generic signals namings
+ LED1 = PC_13,
+ LED2 = NC,
+ LED3 = NC,
+ LED4 = NC,
+ USER_BUTTON = NC,
+ SERIAL_TX = PA_2,
+ SERIAL_RX = PA_3,
+ USBTX = PA_2,
+ USBRX = PA_3,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed-STM32F103C8T6/SysClockConf.cpp Mon Mar 18 22:45:39 2019 +0000
@@ -0,0 +1,60 @@
+/*
+ ******************************************************************************
+ * @file SysClockConf.c
+ * @author Zoltan Hudak
+ * @version
+ * @date 05-July-2016
+ * @brief System Clock configuration for STM32F103C8T6
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 Zoltan Hudak <hudakz@outlook.com>
+ *
+ * All rights reserved.
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "SysClockConf.h"
+#include "mbed.h"
+
+void HSE_SystemClock_Config(void) {
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_PeriphCLKInitTypeDef PeriphClkInit;
+
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+ HAL_RCC_OscConfig(&RCC_OscInitStruct);
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2);
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB;
+ PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
+ PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+}
+
+void confSysClock(void) {
+ HAL_RCC_DeInit();
+ HSE_SystemClock_Config();
+ SystemCoreClockUpdate();
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-STM32F103C8T6/SysClockConf.h Mon Mar 18 22:45:39 2019 +0000 @@ -0,0 +1,2 @@ +#pragma once +void confSysClock(void); \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed-STM32F103C8T6/stm32f103c8t6.h Mon Mar 18 22:45:39 2019 +0000 @@ -0,0 +1,3 @@ +#pragma once +#include "PinNames.h" +#include "SysClockConf.h"
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Mon Mar 18 22:45:39 2019 +0000 @@ -0,0 +1,1 @@ +https://os.mbed.com/users/mbed_official/code/mbed/builds/65be27845400 \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed_config.h Mon Mar 18 22:45:39 2019 +0000 @@ -0,0 +1,54 @@ +/* + * mbed SDK + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +// Automatically generated configuration file. +// DO NOT EDIT, content will be overwritten. + +#ifndef __MBED_CONFIG_DATA__ +#define __MBED_CONFIG_DATA__ + +// Configuration parameters +#define CLOCK_SOURCE USE_PLL_HSE_EXTC|USE_PLL_HSI // set by target:NUCLEO_F103RB +#define CLOCK_SOURCE_USB 0 // set by target:NUCLEO_F103RB +#define LPTICKER_DELAY_TICKS 1 // set by target:FAMILY_STM32 +#define MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED 0 // set by library:platform +#define MBED_CONF_PLATFORM_CTHUNK_COUNT_MAX 8 // set by library:platform +#define MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE 9600 // set by library:platform +#define MBED_CONF_PLATFORM_ERROR_ALL_THREADS_INFO 0 // set by library:platform +#define MBED_CONF_PLATFORM_ERROR_DECODE_HTTP_URL_STR "\nFor more info, visit: https://armmbed.github.io/mbedos-error/?error=0x%08X" // set by library:platform +#define MBED_CONF_PLATFORM_ERROR_FILENAME_CAPTURE_ENABLED 0 // set by library:platform +#define MBED_CONF_PLATFORM_ERROR_HIST_ENABLED 0 // set by library:platform +#define MBED_CONF_PLATFORM_ERROR_HIST_SIZE 4 // set by library:platform +#define MBED_CONF_PLATFORM_ERROR_REBOOT_MAX 1 // set by library:platform +#define MBED_CONF_PLATFORM_FATAL_ERROR_AUTO_REBOOT_ENABLED 0 // set by library:platform +#define MBED_CONF_PLATFORM_FORCE_NON_COPYABLE_ERROR 0 // set by library:platform +#define MBED_CONF_PLATFORM_MAX_ERROR_FILENAME_LEN 16 // set by library:platform +#define MBED_CONF_PLATFORM_POLL_USE_LOWPOWER_TIMER 0 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_BAUD_RATE 9600 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_BUFFERED_SERIAL 0 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES 0 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_CONVERT_TTY_NEWLINES 0 // set by library:platform +#define MBED_CONF_PLATFORM_STDIO_FLUSH_AT_EXIT 1 // set by library:platform +#define MBED_CONF_PLATFORM_USE_MPU 1 // set by library:platform +#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x1000 // set by target:Target +#define MBED_CONF_TARGET_DEEP_SLEEP_LATENCY 3 // set by target:FAMILY_STM32 +#define MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK 1 // set by target:FAMILY_STM32 +#define MBED_CONF_TARGET_LPUART_CLOCK_SOURCE USE_LPUART_CLK_LSE|USE_LPUART_CLK_PCLK1 // set by target:FAMILY_STM32 +#define MBED_CONF_TARGET_LSE_AVAILABLE 1 // set by target:FAMILY_STM32 +#define MBED_CONF_TARGET_MPU_ROM_END 0x0fffffff // set by target:Target + +#endif