Pablo Henrique / Mbed 2 deprecated STM32F103C8T6_VL53l0x_CAN

code for read VL53l0x sensor with CAN

Dependencies:   mbed

VL53L0X_simple/VL53L0X_device.h@1:7bbfe329c62b, 2019-03-18 (annotated)

Committer:
pablo_bmxrp
Date:
Mon Mar 18 22:45:39 2019 +0000
Revision:
1:7bbfe329c62b
Parent:
STM32F103C8T6_MPA/VL53L0X_simple/VL53L0X_device.h@0:44429c0a71d4 
V1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
pablo_bmxrp 0:44429c0a71d4 1 /*******************************************************************************
pablo_bmxrp 0:44429c0a71d4 2 Copyright © 2016, STMicroelectronics International N.V.
pablo_bmxrp 0:44429c0a71d4 3 All rights reserved.
pablo_bmxrp 0:44429c0a71d4 4
pablo_bmxrp 0:44429c0a71d4 5 Redistribution and use in source and binary forms, with or without
pablo_bmxrp 0:44429c0a71d4 6 modification, are permitted provided that the following conditions are met:
pablo_bmxrp 0:44429c0a71d4 7 * Redistributions of source code must retain the above copyright
pablo_bmxrp 0:44429c0a71d4 8 notice, this list of conditions and the following disclaimer.
pablo_bmxrp 0:44429c0a71d4 9 * Redistributions in binary form must reproduce the above copyright
pablo_bmxrp 0:44429c0a71d4 10 notice, this list of conditions and the following disclaimer in the
pablo_bmxrp 0:44429c0a71d4 11 documentation and/or other materials provided with the distribution.
pablo_bmxrp 0:44429c0a71d4 12 * Neither the name of STMicroelectronics nor the
pablo_bmxrp 0:44429c0a71d4 13 names of its contributors may be used to endorse or promote products
pablo_bmxrp 0:44429c0a71d4 14 derived from this software without specific prior written permission.
pablo_bmxrp 0:44429c0a71d4 15
pablo_bmxrp 0:44429c0a71d4 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
pablo_bmxrp 0:44429c0a71d4 17 ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
pablo_bmxrp 0:44429c0a71d4 18 WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
pablo_bmxrp 0:44429c0a71d4 19 NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS ARE DISCLAIMED.
pablo_bmxrp 0:44429c0a71d4 20 IN NO EVENT SHALL STMICROELECTRONICS INTERNATIONAL N.V. BE LIABLE FOR ANY
pablo_bmxrp 0:44429c0a71d4 21 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
pablo_bmxrp 0:44429c0a71d4 22 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
pablo_bmxrp 0:44429c0a71d4 23 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
pablo_bmxrp 0:44429c0a71d4 24 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
pablo_bmxrp 0:44429c0a71d4 25 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
pablo_bmxrp 0:44429c0a71d4 26 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
pablo_bmxrp 0:44429c0a71d4 27 *******************************************************************************/
pablo_bmxrp 0:44429c0a71d4 28
pablo_bmxrp 0:44429c0a71d4 29 /**
pablo_bmxrp 0:44429c0a71d4 30 * Device specific defines. To be adapted by implementer for the targeted
pablo_bmxrp 0:44429c0a71d4 31 * device.
pablo_bmxrp 0:44429c0a71d4 32 */
pablo_bmxrp 0:44429c0a71d4 33
pablo_bmxrp 0:44429c0a71d4 34 #ifndef _VL53L0X_DEVICE_H_
pablo_bmxrp 0:44429c0a71d4 35 #define _VL53L0X_DEVICE_H_
pablo_bmxrp 0:44429c0a71d4 36
pablo_bmxrp 0:44429c0a71d4 37 #include "VL53L0X_types.h"
pablo_bmxrp 0:44429c0a71d4 38
pablo_bmxrp 0:44429c0a71d4 39
pablo_bmxrp 0:44429c0a71d4 40 /** @defgroup VL53L0X_DevSpecDefines_group VL53L0X cut1.1 Device Specific Defines
pablo_bmxrp 0:44429c0a71d4 41 * @brief VL53L0X cut1.1 Device Specific Defines
pablo_bmxrp 0:44429c0a71d4 42 * @{
pablo_bmxrp 0:44429c0a71d4 43 */
pablo_bmxrp 0:44429c0a71d4 44
pablo_bmxrp 0:44429c0a71d4 45
pablo_bmxrp 0:44429c0a71d4 46 /** @defgroup VL53L0X_DeviceError_group Device Error
pablo_bmxrp 0:44429c0a71d4 47 * @brief Device Error code
pablo_bmxrp 0:44429c0a71d4 48 *
pablo_bmxrp 0:44429c0a71d4 49 * This enum is Device specific it should be updated in the implementation
pablo_bmxrp 0:44429c0a71d4 50 * Use @a VL53L0X_GetStatusErrorString() to get the string.
pablo_bmxrp 0:44429c0a71d4 51 * It is related to Status Register of the Device.
pablo_bmxrp 0:44429c0a71d4 52 * @{
pablo_bmxrp 0:44429c0a71d4 53 */
pablo_bmxrp 0:44429c0a71d4 54 typedef uint8_t VL53L0X_DeviceError;
pablo_bmxrp 0:44429c0a71d4 55
pablo_bmxrp 0:44429c0a71d4 56 #define VL53L0X_DEVICEERROR_NONE ((VL53L0X_DeviceError) 0)
pablo_bmxrp 0:44429c0a71d4 57 /*!< 0 NoError */
pablo_bmxrp 0:44429c0a71d4 58 #define VL53L0X_DEVICEERROR_VCSELCONTINUITYTESTFAILURE ((VL53L0X_DeviceError) 1)
pablo_bmxrp 0:44429c0a71d4 59 #define VL53L0X_DEVICEERROR_VCSELWATCHDOGTESTFAILURE ((VL53L0X_DeviceError) 2)
pablo_bmxrp 0:44429c0a71d4 60 #define VL53L0X_DEVICEERROR_NOVHVVALUEFOUND ((VL53L0X_DeviceError) 3)
pablo_bmxrp 0:44429c0a71d4 61 #define VL53L0X_DEVICEERROR_MSRCNOTARGET ((VL53L0X_DeviceError) 4)
pablo_bmxrp 0:44429c0a71d4 62 #define VL53L0X_DEVICEERROR_SNRCHECK ((VL53L0X_DeviceError) 5)
pablo_bmxrp 0:44429c0a71d4 63 #define VL53L0X_DEVICEERROR_RANGEPHASECHECK ((VL53L0X_DeviceError) 6)
pablo_bmxrp 0:44429c0a71d4 64 #define VL53L0X_DEVICEERROR_SIGMATHRESHOLDCHECK ((VL53L0X_DeviceError) 7)
pablo_bmxrp 0:44429c0a71d4 65 #define VL53L0X_DEVICEERROR_TCC ((VL53L0X_DeviceError) 8)
pablo_bmxrp 0:44429c0a71d4 66 #define VL53L0X_DEVICEERROR_PHASECONSISTENCY ((VL53L0X_DeviceError) 9)
pablo_bmxrp 0:44429c0a71d4 67 #define VL53L0X_DEVICEERROR_MINCLIP ((VL53L0X_DeviceError) 10)
pablo_bmxrp 0:44429c0a71d4 68 #define VL53L0X_DEVICEERROR_RANGECOMPLETE ((VL53L0X_DeviceError) 11)
pablo_bmxrp 0:44429c0a71d4 69 #define VL53L0X_DEVICEERROR_ALGOUNDERFLOW ((VL53L0X_DeviceError) 12)
pablo_bmxrp 0:44429c0a71d4 70 #define VL53L0X_DEVICEERROR_ALGOOVERFLOW ((VL53L0X_DeviceError) 13)
pablo_bmxrp 0:44429c0a71d4 71 #define VL53L0X_DEVICEERROR_RANGEIGNORETHRESHOLD ((VL53L0X_DeviceError) 14)
pablo_bmxrp 0:44429c0a71d4 72
pablo_bmxrp 0:44429c0a71d4 73 /** @} end of VL53L0X_DeviceError_group */
pablo_bmxrp 0:44429c0a71d4 74
pablo_bmxrp 0:44429c0a71d4 75
pablo_bmxrp 0:44429c0a71d4 76 /** @defgroup VL53L0X_CheckEnable_group Check Enable list
pablo_bmxrp 0:44429c0a71d4 77 * @brief Check Enable code
pablo_bmxrp 0:44429c0a71d4 78 *
pablo_bmxrp 0:44429c0a71d4 79 * Define used to specify the LimitCheckId.
pablo_bmxrp 0:44429c0a71d4 80 * Use @a VL53L0X_GetLimitCheckInfo() to get the string.
pablo_bmxrp 0:44429c0a71d4 81 * @{
pablo_bmxrp 0:44429c0a71d4 82 */
pablo_bmxrp 0:44429c0a71d4 83
pablo_bmxrp 0:44429c0a71d4 84 #define VL53L0X_CHECKENABLE_SIGMA_FINAL_RANGE 0
pablo_bmxrp 0:44429c0a71d4 85 #define VL53L0X_CHECKENABLE_SIGNAL_RATE_FINAL_RANGE 1
pablo_bmxrp 0:44429c0a71d4 86 #define VL53L0X_CHECKENABLE_SIGNAL_REF_CLIP 2
pablo_bmxrp 0:44429c0a71d4 87 #define VL53L0X_CHECKENABLE_RANGE_IGNORE_THRESHOLD 3
pablo_bmxrp 0:44429c0a71d4 88 #define VL53L0X_CHECKENABLE_SIGNAL_RATE_MSRC 4
pablo_bmxrp 0:44429c0a71d4 89 #define VL53L0X_CHECKENABLE_SIGNAL_RATE_PRE_RANGE 5
pablo_bmxrp 0:44429c0a71d4 90
pablo_bmxrp 0:44429c0a71d4 91 #define VL53L0X_CHECKENABLE_NUMBER_OF_CHECKS 6
pablo_bmxrp 0:44429c0a71d4 92
pablo_bmxrp 0:44429c0a71d4 93 /** @} end of VL53L0X_CheckEnable_group */
pablo_bmxrp 0:44429c0a71d4 94
pablo_bmxrp 0:44429c0a71d4 95
pablo_bmxrp 0:44429c0a71d4 96 /** @defgroup VL53L0X_GpioFunctionality_group Gpio Functionality
pablo_bmxrp 0:44429c0a71d4 97 * @brief Defines the different functionalities for the device GPIO(s)
pablo_bmxrp 0:44429c0a71d4 98 * @{
pablo_bmxrp 0:44429c0a71d4 99 */
pablo_bmxrp 0:44429c0a71d4 100 typedef uint8_t VL53L0X_GpioFunctionality;
pablo_bmxrp 0:44429c0a71d4 101
pablo_bmxrp 0:44429c0a71d4 102 #define VL53L0X_GPIOFUNCTIONALITY_OFF \
pablo_bmxrp 0:44429c0a71d4 103 ((VL53L0X_GpioFunctionality) 0) /*!< NO Interrupt */
pablo_bmxrp 0:44429c0a71d4 104 #define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_LOW \
pablo_bmxrp 0:44429c0a71d4 105 ((VL53L0X_GpioFunctionality) 1) /*!< Level Low (value < thresh_low) */
pablo_bmxrp 0:44429c0a71d4 106 #define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_HIGH \
pablo_bmxrp 0:44429c0a71d4 107 ((VL53L0X_GpioFunctionality) 2) /*!< Level High (value > thresh_high) */
pablo_bmxrp 0:44429c0a71d4 108 #define VL53L0X_GPIOFUNCTIONALITY_THRESHOLD_CROSSED_OUT \
pablo_bmxrp 0:44429c0a71d4 109 ((VL53L0X_GpioFunctionality) 3)
pablo_bmxrp 0:44429c0a71d4 110 /*!< Out Of Window (value < thresh_low OR value > thresh_high) */
pablo_bmxrp 0:44429c0a71d4 111 #define VL53L0X_GPIOFUNCTIONALITY_NEW_MEASURE_READY \
pablo_bmxrp 0:44429c0a71d4 112 ((VL53L0X_GpioFunctionality) 4) /*!< New Sample Ready */
pablo_bmxrp 0:44429c0a71d4 113
pablo_bmxrp 0:44429c0a71d4 114 /** @} end of VL53L0X_GpioFunctionality_group */
pablo_bmxrp 0:44429c0a71d4 115
pablo_bmxrp 0:44429c0a71d4 116
pablo_bmxrp 0:44429c0a71d4 117 /* Device register map */
pablo_bmxrp 0:44429c0a71d4 118
pablo_bmxrp 0:44429c0a71d4 119 /** @defgroup VL53L0X_DefineRegisters_group Define Registers
pablo_bmxrp 0:44429c0a71d4 120 * @brief List of all the defined registers
pablo_bmxrp 0:44429c0a71d4 121 * @{
pablo_bmxrp 0:44429c0a71d4 122 */
pablo_bmxrp 0:44429c0a71d4 123 #define VL53L0X_REG_SYSRANGE_START 0x000
pablo_bmxrp 0:44429c0a71d4 124 /** mask existing bit in #VL53L0X_REG_SYSRANGE_START*/
pablo_bmxrp 0:44429c0a71d4 125 #define VL53L0X_REG_SYSRANGE_MODE_MASK 0x0F
pablo_bmxrp 0:44429c0a71d4 126 /** bit 0 in #VL53L0X_REG_SYSRANGE_START write 1 toggle state in
pablo_bmxrp 0:44429c0a71d4 127 * continuous mode and arm next shot in single shot mode */
pablo_bmxrp 0:44429c0a71d4 128 #define VL53L0X_REG_SYSRANGE_MODE_START_STOP 0x01
pablo_bmxrp 0:44429c0a71d4 129 /** bit 1 write 0 in #VL53L0X_REG_SYSRANGE_START set single shot mode */
pablo_bmxrp 0:44429c0a71d4 130 #define VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT 0x00
pablo_bmxrp 0:44429c0a71d4 131 /** bit 1 write 1 in #VL53L0X_REG_SYSRANGE_START set back-to-back
pablo_bmxrp 0:44429c0a71d4 132 * operation mode */
pablo_bmxrp 0:44429c0a71d4 133 #define VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK 0x02
pablo_bmxrp 0:44429c0a71d4 134 /** bit 2 write 1 in #VL53L0X_REG_SYSRANGE_START set timed operation
pablo_bmxrp 0:44429c0a71d4 135 * mode */
pablo_bmxrp 0:44429c0a71d4 136 #define VL53L0X_REG_SYSRANGE_MODE_TIMED 0x04
pablo_bmxrp 0:44429c0a71d4 137 /** bit 3 write 1 in #VL53L0X_REG_SYSRANGE_START set histogram operation
pablo_bmxrp 0:44429c0a71d4 138 * mode */
pablo_bmxrp 0:44429c0a71d4 139 #define VL53L0X_REG_SYSRANGE_MODE_HISTOGRAM 0x08
pablo_bmxrp 0:44429c0a71d4 140
pablo_bmxrp 0:44429c0a71d4 141
pablo_bmxrp 0:44429c0a71d4 142 #define VL53L0X_REG_SYSTEM_THRESH_HIGH 0x000C
pablo_bmxrp 0:44429c0a71d4 143 #define VL53L0X_REG_SYSTEM_THRESH_LOW 0x000E
pablo_bmxrp 0:44429c0a71d4 144
pablo_bmxrp 0:44429c0a71d4 145
pablo_bmxrp 0:44429c0a71d4 146 #define VL53L0X_REG_SYSTEM_SEQUENCE_CONFIG 0x0001
pablo_bmxrp 0:44429c0a71d4 147 #define VL53L0X_REG_SYSTEM_RANGE_CONFIG 0x0009
pablo_bmxrp 0:44429c0a71d4 148 #define VL53L0X_REG_SYSTEM_INTERMEASUREMENT_PERIOD 0x0004
pablo_bmxrp 0:44429c0a71d4 149
pablo_bmxrp 0:44429c0a71d4 150
pablo_bmxrp 0:44429c0a71d4 151 #define VL53L0X_REG_SYSTEM_INTERRUPT_CONFIG_GPIO 0x000A
pablo_bmxrp 0:44429c0a71d4 152 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_DISABLED 0x00
pablo_bmxrp 0:44429c0a71d4 153 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_LOW 0x01
pablo_bmxrp 0:44429c0a71d4 154 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_LEVEL_HIGH 0x02
pablo_bmxrp 0:44429c0a71d4 155 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_OUT_OF_WINDOW 0x03
pablo_bmxrp 0:44429c0a71d4 156 #define VL53L0X_REG_SYSTEM_INTERRUPT_GPIO_NEW_SAMPLE_READY 0x04
pablo_bmxrp 0:44429c0a71d4 157
pablo_bmxrp 0:44429c0a71d4 158 #define VL53L0X_REG_GPIO_HV_MUX_ACTIVE_HIGH 0x0084
pablo_bmxrp 0:44429c0a71d4 159
pablo_bmxrp 0:44429c0a71d4 160
pablo_bmxrp 0:44429c0a71d4 161 #define VL53L0X_REG_SYSTEM_INTERRUPT_CLEAR 0x000B
pablo_bmxrp 0:44429c0a71d4 162
pablo_bmxrp 0:44429c0a71d4 163 /* Result registers */
pablo_bmxrp 0:44429c0a71d4 164 #define VL53L0X_REG_RESULT_INTERRUPT_STATUS 0x0013
pablo_bmxrp 0:44429c0a71d4 165 #define VL53L0X_REG_RESULT_RANGE_STATUS 0x0014
pablo_bmxrp 0:44429c0a71d4 166
pablo_bmxrp 0:44429c0a71d4 167 #define VL53L0X_REG_RESULT_CORE_PAGE 1
pablo_bmxrp 0:44429c0a71d4 168 #define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN 0x00BC
pablo_bmxrp 0:44429c0a71d4 169 #define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_RTN 0x00C0
pablo_bmxrp 0:44429c0a71d4 170 #define VL53L0X_REG_RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF 0x00D0
pablo_bmxrp 0:44429c0a71d4 171 #define VL53L0X_REG_RESULT_CORE_RANGING_TOTAL_EVENTS_REF 0x00D4
pablo_bmxrp 0:44429c0a71d4 172 #define VL53L0X_REG_RESULT_PEAK_SIGNAL_RATE_REF 0x00B6
pablo_bmxrp 0:44429c0a71d4 173
pablo_bmxrp 0:44429c0a71d4 174 /* Algo register */
pablo_bmxrp 0:44429c0a71d4 175
pablo_bmxrp 0:44429c0a71d4 176 #define VL53L0X_REG_ALGO_PART_TO_PART_RANGE_OFFSET_MM 0x0028
pablo_bmxrp 0:44429c0a71d4 177
pablo_bmxrp 0:44429c0a71d4 178 #define VL53L0X_REG_I2C_SLAVE_DEVICE_ADDRESS 0x008a
pablo_bmxrp 0:44429c0a71d4 179
pablo_bmxrp 0:44429c0a71d4 180 /* Check Limit registers */
pablo_bmxrp 0:44429c0a71d4 181 #define VL53L0X_REG_MSRC_CONFIG_CONTROL 0x0060
pablo_bmxrp 0:44429c0a71d4 182
pablo_bmxrp 0:44429c0a71d4 183 #define VL53L0X_REG_PRE_RANGE_CONFIG_MIN_SNR 0X0027
pablo_bmxrp 0:44429c0a71d4 184 #define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_LOW 0x0056
pablo_bmxrp 0:44429c0a71d4 185 #define VL53L0X_REG_PRE_RANGE_CONFIG_VALID_PHASE_HIGH 0x0057
pablo_bmxrp 0:44429c0a71d4 186 #define VL53L0X_REG_PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT 0x0064
pablo_bmxrp 0:44429c0a71d4 187
pablo_bmxrp 0:44429c0a71d4 188 #define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_SNR 0X0067
pablo_bmxrp 0:44429c0a71d4 189 #define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_LOW 0x0047
pablo_bmxrp 0:44429c0a71d4 190 #define VL53L0X_REG_FINAL_RANGE_CONFIG_VALID_PHASE_HIGH 0x0048
pablo_bmxrp 0:44429c0a71d4 191 #define VL53L0X_REG_FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT 0x0044
pablo_bmxrp 0:44429c0a71d4 192
pablo_bmxrp 0:44429c0a71d4 193
pablo_bmxrp 0:44429c0a71d4 194 #define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_HI 0X0061
pablo_bmxrp 0:44429c0a71d4 195 #define VL53L0X_REG_PRE_RANGE_CONFIG_SIGMA_THRESH_LO 0X0062
pablo_bmxrp 0:44429c0a71d4 196
pablo_bmxrp 0:44429c0a71d4 197 /* PRE RANGE registers */
pablo_bmxrp 0:44429c0a71d4 198 #define VL53L0X_REG_PRE_RANGE_CONFIG_VCSEL_PERIOD 0x0050
pablo_bmxrp 0:44429c0a71d4 199 #define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0051
pablo_bmxrp 0:44429c0a71d4 200 #define VL53L0X_REG_PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0052
pablo_bmxrp 0:44429c0a71d4 201
pablo_bmxrp 0:44429c0a71d4 202 #define VL53L0X_REG_SYSTEM_HISTOGRAM_BIN 0x0081
pablo_bmxrp 0:44429c0a71d4 203 #define VL53L0X_REG_HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT 0x0033
pablo_bmxrp 0:44429c0a71d4 204 #define VL53L0X_REG_HISTOGRAM_CONFIG_READOUT_CTRL 0x0055
pablo_bmxrp 0:44429c0a71d4 205
pablo_bmxrp 0:44429c0a71d4 206 #define VL53L0X_REG_FINAL_RANGE_CONFIG_VCSEL_PERIOD 0x0070
pablo_bmxrp 0:44429c0a71d4 207 #define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI 0x0071
pablo_bmxrp 0:44429c0a71d4 208 #define VL53L0X_REG_FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO 0x0072
pablo_bmxrp 0:44429c0a71d4 209 #define VL53L0X_REG_CROSSTALK_COMPENSATION_PEAK_RATE_MCPS 0x0020
pablo_bmxrp 0:44429c0a71d4 210
pablo_bmxrp 0:44429c0a71d4 211 #define VL53L0X_REG_MSRC_CONFIG_TIMEOUT_MACROP 0x0046
pablo_bmxrp 0:44429c0a71d4 212
pablo_bmxrp 0:44429c0a71d4 213
pablo_bmxrp 0:44429c0a71d4 214 #define VL53L0X_REG_SOFT_RESET_GO2_SOFT_RESET_N 0x00bf
pablo_bmxrp 0:44429c0a71d4 215 #define VL53L0X_REG_IDENTIFICATION_MODEL_ID 0x00c0
pablo_bmxrp 0:44429c0a71d4 216 #define VL53L0X_REG_IDENTIFICATION_REVISION_ID 0x00c2
pablo_bmxrp 0:44429c0a71d4 217
pablo_bmxrp 0:44429c0a71d4 218 #define VL53L0X_REG_OSC_CALIBRATE_VAL 0x00f8
pablo_bmxrp 0:44429c0a71d4 219
pablo_bmxrp 0:44429c0a71d4 220
pablo_bmxrp 0:44429c0a71d4 221 #define VL53L0X_SIGMA_ESTIMATE_MAX_VALUE 65535
pablo_bmxrp 0:44429c0a71d4 222 /* equivalent to a range sigma of 655.35mm */
pablo_bmxrp 0:44429c0a71d4 223
pablo_bmxrp 0:44429c0a71d4 224 #define VL53L0X_REG_GLOBAL_CONFIG_VCSEL_WIDTH 0x032
pablo_bmxrp 0:44429c0a71d4 225 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_0 0x0B0
pablo_bmxrp 0:44429c0a71d4 226 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_1 0x0B1
pablo_bmxrp 0:44429c0a71d4 227 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_2 0x0B2
pablo_bmxrp 0:44429c0a71d4 228 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_3 0x0B3
pablo_bmxrp 0:44429c0a71d4 229 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_4 0x0B4
pablo_bmxrp 0:44429c0a71d4 230 #define VL53L0X_REG_GLOBAL_CONFIG_SPAD_ENABLES_REF_5 0x0B5
pablo_bmxrp 0:44429c0a71d4 231
pablo_bmxrp 0:44429c0a71d4 232 #define VL53L0X_REG_GLOBAL_CONFIG_REF_EN_START_SELECT 0xB6
pablo_bmxrp 0:44429c0a71d4 233 #define VL53L0X_REG_DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD 0x4E /* 0x14E */
pablo_bmxrp 0:44429c0a71d4 234 #define VL53L0X_REG_DYNAMIC_SPAD_REF_EN_START_OFFSET 0x4F /* 0x14F */
pablo_bmxrp 0:44429c0a71d4 235 #define VL53L0X_REG_POWER_MANAGEMENT_GO1_POWER_FORCE 0x80
pablo_bmxrp 0:44429c0a71d4 236
pablo_bmxrp 0:44429c0a71d4 237 /*
pablo_bmxrp 0:44429c0a71d4 238 * Speed of light in um per 1E-10 Seconds
pablo_bmxrp 0:44429c0a71d4 239 */
pablo_bmxrp 0:44429c0a71d4 240
pablo_bmxrp 0:44429c0a71d4 241 #define VL53L0X_SPEED_OF_LIGHT_IN_AIR 2997
pablo_bmxrp 0:44429c0a71d4 242
pablo_bmxrp 0:44429c0a71d4 243 #define VL53L0X_REG_VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV 0x0089
pablo_bmxrp 0:44429c0a71d4 244
pablo_bmxrp 0:44429c0a71d4 245 #define VL53L0X_REG_ALGO_PHASECAL_LIM 0x0030 /* 0x130 */
pablo_bmxrp 0:44429c0a71d4 246 #define VL53L0X_REG_ALGO_PHASECAL_CONFIG_TIMEOUT 0x0030
pablo_bmxrp 0:44429c0a71d4 247
pablo_bmxrp 0:44429c0a71d4 248 /** @} VL53L0X_DefineRegisters_group */
pablo_bmxrp 0:44429c0a71d4 249
pablo_bmxrp 0:44429c0a71d4 250 /** @} VL53L0X_DevSpecDefines_group */
pablo_bmxrp 0:44429c0a71d4 251
pablo_bmxrp 0:44429c0a71d4 252
pablo_bmxrp 0:44429c0a71d4 253 #endif
pablo_bmxrp 0:44429c0a71d4 254
pablo_bmxrp 0:44429c0a71d4 255 /* _VL53L0X_DEVICE_H_ */
pablo_bmxrp 0:44429c0a71d4 256
pablo_bmxrp 0:44429c0a71d4 257