Bayley Wang / Mbed 2 deprecated qonly_controller

derp

Dependencies:   FastPWM3 mbed

main.cpp@13:728ddd6939d3, 2016-04-18 (annotated)

Committer:
bwang
Date:
Mon Apr 18 21:53:15 2016 +0000
Revision:
13:728ddd6939d3
Parent:
12:0811d08424e1 
almost switch based

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bwang 0:bac9c3a3a6ca 1 #include "mbed.h"
bwang 0:bac9c3a3a6ca 2 #include "math.h"
bwang 0:bac9c3a3a6ca 3 #include "PositionSensor.h"
bwang 0:bac9c3a3a6ca 4 #include "FastPWM.h"
bwang 8:314074b56470 5
bwang 8:314074b56470 6 #define PWMA PA_8
bwang 8:314074b56470 7 #define PWMB PA_9
bwang 8:314074b56470 8 #define PWMC PA_10
bwang 8:314074b56470 9 #define EN PB_15
bwang 8:314074b56470 10
bwang 8:314074b56470 11 #define IA PA_4
bwang 8:314074b56470 12 #define IB PB_0
bwang 8:314074b56470 13
bwang 8:314074b56470 14 #define PI 3.141593f
bwang 8:314074b56470 15 #define CPR 4096
bwang 8:314074b56470 16 #define POS_OFFSET 4.5f
bwang 8:314074b56470 17
bwang 8:314074b56470 18 #define I_SCALE_RAW 25.0f //mv/A
bwang 8:314074b56470 19 #define R_UP 12000.0f //ohms
bwang 8:314074b56470 20 #define R_DOWN 3600.0f //ohms
bwang 8:314074b56470 21 #define R_BIAS 3600.0f //ohms
bwang 8:314074b56470 22 #define AVDD 3300.0f //mV
bwang 8:314074b56470 23
bwang 8:314074b56470 24 #define I_OFFSET (AVDD * R_DOWN * R_UP / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 25 #define I_SCALE (R_BIAS * R_DOWN * I_SCALE_RAW / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 26
bwang 8:314074b56470 27 #define K_LOOP 0.02
bwang 10:7624146c5945 28 #define KI_BASE 0.008
bwang 8:314074b56470 29 #define BUS_VOLTAGE 20.0
bwang 8:314074b56470 30
bwang 8:314074b56470 31 #define KP (K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 32 #define KI (KI_BASE * K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 33
bwang 8:314074b56470 34 #define INTEGRAL_MAX 1.0f
bwang 0:bac9c3a3a6ca 35
bwang 12:0811d08424e1 36 #define THROTTLE_MAX 1900.0f
bwang 12:0811d08424e1 37 #define THROTTLE_MIN 1600.0f
bwang 12:0811d08424e1 38
bwang 12:0811d08424e1 39 #define THROTTLE_HIGH 5000.0f
bwang 12:0811d08424e1 40 #define THROTTLE_LOW 1550.0f
bwang 10:7624146c5945 41
bwang 11:825203ff4371 42 #define Q_REF_MAX (-200.0)
bwang 10:7624146c5945 43
bwang 1:7b61790f6be9 44 FastPWM *a;
bwang 1:7b61790f6be9 45 FastPWM *b;
bwang 1:7b61790f6be9 46 FastPWM *c;
bwang 0:bac9c3a3a6ca 47 DigitalOut en(EN);
bwang 0:bac9c3a3a6ca 48
bwang 13:728ddd6939d3 49 DigitalIn throttle_in(PB_8);
bwang 0:bac9c3a3a6ca 50 PositionSensorEncoder pos(CPR, 0);
bwang 0:bac9c3a3a6ca 51
bwang 1:7b61790f6be9 52 int adval1, adval2;
bwang 8:314074b56470 53 float ia, ib, ic, alpha, beta, q;
bwang 10:7624146c5945 54 double vq = 0.0, q_integral = 0.0, last_q = 0.0;
bwang 8:314074b56470 55
bwang 1:7b61790f6be9 56 extern "C" void TIM1_UP_TIM10_IRQHandler(void) {
bwang 8:314074b56470 57 if (TIM1->SR & TIM_SR_UIF) {
bwang 8:314074b56470 58 float p = pos.GetElecPosition() - POS_OFFSET;
bwang 8:314074b56470 59 if (p < 0) p += 2 * PI;
bwang 8:314074b56470 60
bwang 8:314074b56470 61 //float pos_dac = 0.85f * p / (2 * PI) + 0.05f;
bwang 8:314074b56470 62 //DAC->DHR12R2 = (unsigned int) (pos_dac * 4096);
bwang 8:314074b56470 63
bwang 8:314074b56470 64 float sin_p = sinf(p);
bwang 8:314074b56470 65 float cos_p = cosf(p);
bwang 8:314074b56470 66
bwang 4:a6669248ce4d 67 ADC1->CR2 |= 0x40000000;
bwang 4:a6669248ce4d 68 volatile int delay;
bwang 4:a6669248ce4d 69 for (delay = 0; delay < 35; delay++);
bwang 1:7b61790f6be9 70 adval1 = ADC1->DR;
bwang 1:7b61790f6be9 71 adval2 = ADC2->DR;
bwang 8:314074b56470 72
bwang 8:314074b56470 73 ia = ((float) adval1 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 74 ib = ((float) adval2 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 75 ic = -ia - ib;
bwang 8:314074b56470 76
bwang 8:314074b56470 77 float u = ib;
bwang 8:314074b56470 78 float v = ic;
bwang 8:314074b56470 79
bwang 8:314074b56470 80 alpha = u;
bwang 8:314074b56470 81 beta = 1 / sqrtf(3.0f) * u + 2 / sqrtf(3.0f) * v;
bwang 8:314074b56470 82
bwang 8:314074b56470 83 q = -alpha * sin_p - beta * cos_p;
bwang 8:314074b56470 84
bwang 13:728ddd6939d3 85 float throttle_scaler = 1.0f;
bwang 8:314074b56470 86
bwang 10:7624146c5945 87 double q_err = Q_REF_MAX * (double) throttle_scaler - q;
bwang 11:825203ff4371 88
bwang 10:7624146c5945 89 //DAC->DHR12R2 = (unsigned int) (q_err * 20 + 2048);
bwang 8:314074b56470 90
bwang 8:314074b56470 91 q_integral += q_err * KI;
bwang 8:314074b56470 92 if (q_integral > INTEGRAL_MAX) q_integral = INTEGRAL_MAX;
bwang 8:314074b56470 93 if (q_integral < -INTEGRAL_MAX) q_integral = -INTEGRAL_MAX;
bwang 8:314074b56470 94
bwang 8:314074b56470 95 vq = KP * q_err + q_integral;
bwang 8:314074b56470 96 if (vq < -1.0f) vq = -1.0f;
bwang 8:314074b56470 97 if (vq > 1.0f) vq = 1.0f;
bwang 11:825203ff4371 98
bwang 9:4812c9e932ea 99 //DAC->DHR12R2 = (unsigned int) (vq * 2000 + 2048);
bwang 12:0811d08424e1 100 //DAC->DHR12R2 = (unsigned int) (err_throttle_too_low * 2000 + 2048);
bwang 13:728ddd6939d3 101
bwang 13:728ddd6939d3 102 vq = 1.0f;
bwang 11:825203ff4371 103
bwang 8:314074b56470 104 *a = 0.5f + 0.5f * vq * sinf(p);
bwang 8:314074b56470 105 *b = 0.5f + 0.5f * vq * sinf(p + 2 * PI / 3);
bwang 8:314074b56470 106 *c = 0.5f + 0.5f * vq * sinf(p - 2 * PI / 3);
bwang 1:7b61790f6be9 107 }
bwang 1:7b61790f6be9 108 TIM1->SR = 0x00;
bwang 1:7b61790f6be9 109 }
bwang 10:7624146c5945 110
bwang 8:314074b56470 111 int main() {
bwang 1:7b61790f6be9 112 //Enable clocks for GPIOs
bwang 1:7b61790f6be9 113 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
bwang 1:7b61790f6be9 114 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
bwang 1:7b61790f6be9 115 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
bwang 1:7b61790f6be9 116
bwang 1:7b61790f6be9 117 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable TIM1 clock
bwang 1:7b61790f6be9 118
bwang 1:7b61790f6be9 119 a = new FastPWM(PWMA);
bwang 1:7b61790f6be9 120 b = new FastPWM(PWMB);
bwang 1:7b61790f6be9 121 c = new FastPWM(PWMC);
bwang 1:7b61790f6be9 122
bwang 1:7b61790f6be9 123 NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ
bwang 1:7b61790f6be9 124
bwang 1:7b61790f6be9 125 TIM1->DIER |= TIM_DIER_UIE; //enable update interrupt
bwang 8:314074b56470 126 //TIM1->CR1 = 0x40; //CMS = 10, interrupt only when counting up
bwang 1:7b61790f6be9 127 TIM1->CR1 |= TIM_CR1_ARPE; //autoreload on,
bwang 1:7b61790f6be9 128 TIM1->RCR |= 0x01; //update event once per up/down count of tim1
bwang 1:7b61790f6be9 129 TIM1->EGR |= TIM_EGR_UG;
bwang 1:7b61790f6be9 130
bwang 1:7b61790f6be9 131 TIM1->PSC = 0x00; //no prescaler, timer counts up in sync with the peripheral clock
bwang 8:314074b56470 132 TIM1->ARR = 0x2EE0;
bwang 8:314074b56470 133 //TIM1->ARR = 0x1770; //15 Khz
bwang 1:7b61790f6be9 134 TIM1->CCER |= ~(TIM_CCER_CC1NP); //Interupt when low side is on.
bwang 1:7b61790f6be9 135 TIM1->CR1 |= TIM_CR1_CEN;
bwang 1:7b61790f6be9 136
bwang 1:7b61790f6be9 137 //ADC Setup
bwang 1:7b61790f6be9 138 RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1
bwang 1:7b61790f6be9 139 RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2
bwang 1:7b61790f6be9 140
bwang 1:7b61790f6be9 141 ADC->CCR = 0x00000006; //Regular simultaneous mode, 3 channels
bwang 1:7b61790f6be9 142
bwang 1:7b61790f6be9 143 ADC1->CR2 |= ADC_CR2_ADON; //ADC1 on
bwang 1:7b61790f6be9 144 ADC1->SQR3 = 0x0000004; //PA_4 as ADC1, sequence 0
bwang 0:bac9c3a3a6ca 145
bwang 1:7b61790f6be9 146 ADC2->CR2 |= ADC_CR2_ADON; //ADC2 ON
bwang 1:7b61790f6be9 147 ADC2->SQR3 = 0x00000008; //PB_0 as ADC2, sequence 1
bwang 1:7b61790f6be9 148
bwang 1:7b61790f6be9 149 GPIOA->MODER |= (1 << 8);
bwang 1:7b61790f6be9 150 GPIOA->MODER |= (1 << 9);
bwang 1:7b61790f6be9 151
bwang 1:7b61790f6be9 152 GPIOA->MODER |= (1 << 2);
bwang 1:7b61790f6be9 153 GPIOA->MODER |= (1 << 3);
bwang 1:7b61790f6be9 154
bwang 1:7b61790f6be9 155 GPIOA->MODER |= (1 << 0);
bwang 1:7b61790f6be9 156 GPIOA->MODER |= (1 << 1);
bwang 1:7b61790f6be9 157
bwang 1:7b61790f6be9 158 GPIOB->MODER |= (1 << 0);
bwang 1:7b61790f6be9 159 GPIOB->MODER |= (1 << 1);
bwang 1:7b61790f6be9 160
bwang 1:7b61790f6be9 161 GPIOC->MODER |= (1 << 2);
bwang 1:7b61790f6be9 162 GPIOC->MODER |= (1 << 3);
bwang 1:7b61790f6be9 163
bwang 1:7b61790f6be9 164 //DAC setup
bwang 1:7b61790f6be9 165 RCC->APB1ENR |= 0x20000000;
bwang 1:7b61790f6be9 166 DAC->CR |= DAC_CR_EN2;
bwang 1:7b61790f6be9 167
bwang 1:7b61790f6be9 168 GPIOA->MODER |= (1 << 10);
bwang 1:7b61790f6be9 169 GPIOA->MODER |= (1 << 11);
bwang 1:7b61790f6be9 170
bwang 8:314074b56470 171 *a = 0.0f;
bwang 8:314074b56470 172 *b = 0.0f;
bwang 8:314074b56470 173 *c = 0.0f;
bwang 2:eabe8feaaabb 174
bwang 13:728ddd6939d3 175 throttle_in.mode(PullUp);
bwang 0:bac9c3a3a6ca 176
bwang 13:728ddd6939d3 177 en = 1;
bwang 0:bac9c3a3a6ca 178 }