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derp
main.cpp@10:7624146c5945, 2016-04-12 (annotated)
- Committer:
- bwang
- Date:
- Tue Apr 12 13:09:36 2016 +0000
- Revision:
- 10:7624146c5945
- Parent:
- 9:4812c9e932ea
- Child:
- 11:825203ff4371
throttle + safety shutdown code works
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bwang | 0:bac9c3a3a6ca | 1 | #include "mbed.h" |
bwang | 0:bac9c3a3a6ca | 2 | #include "math.h" |
bwang | 0:bac9c3a3a6ca | 3 | #include "PositionSensor.h" |
bwang | 0:bac9c3a3a6ca | 4 | #include "FastPWM.h" |
bwang | 8:314074b56470 | 5 | |
bwang | 8:314074b56470 | 6 | #define PWMA PA_8 |
bwang | 8:314074b56470 | 7 | #define PWMB PA_9 |
bwang | 8:314074b56470 | 8 | #define PWMC PA_10 |
bwang | 8:314074b56470 | 9 | #define EN PB_15 |
bwang | 8:314074b56470 | 10 | |
bwang | 8:314074b56470 | 11 | #define IA PA_4 |
bwang | 8:314074b56470 | 12 | #define IB PB_0 |
bwang | 8:314074b56470 | 13 | |
bwang | 8:314074b56470 | 14 | #define PI 3.141593f |
bwang | 8:314074b56470 | 15 | #define CPR 4096 |
bwang | 8:314074b56470 | 16 | #define POS_OFFSET 4.5f |
bwang | 8:314074b56470 | 17 | |
bwang | 8:314074b56470 | 18 | #define I_SCALE_RAW 25.0f //mv/A |
bwang | 8:314074b56470 | 19 | #define R_UP 12000.0f //ohms |
bwang | 8:314074b56470 | 20 | #define R_DOWN 3600.0f //ohms |
bwang | 8:314074b56470 | 21 | #define R_BIAS 3600.0f //ohms |
bwang | 8:314074b56470 | 22 | #define AVDD 3300.0f //mV |
bwang | 8:314074b56470 | 23 | |
bwang | 8:314074b56470 | 24 | #define I_OFFSET (AVDD * R_DOWN * R_UP / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP))) |
bwang | 8:314074b56470 | 25 | #define I_SCALE (R_BIAS * R_DOWN * I_SCALE_RAW / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP))) |
bwang | 8:314074b56470 | 26 | |
bwang | 8:314074b56470 | 27 | #define K_LOOP 0.02 |
bwang | 10:7624146c5945 | 28 | #define KI_BASE 0.008 |
bwang | 8:314074b56470 | 29 | #define BUS_VOLTAGE 20.0 |
bwang | 8:314074b56470 | 30 | |
bwang | 8:314074b56470 | 31 | #define KP (K_LOOP / BUS_VOLTAGE) |
bwang | 8:314074b56470 | 32 | #define KI (KI_BASE * K_LOOP / BUS_VOLTAGE) |
bwang | 8:314074b56470 | 33 | |
bwang | 8:314074b56470 | 34 | #define INTEGRAL_MAX 1.0f |
bwang | 0:bac9c3a3a6ca | 35 | |
bwang | 10:7624146c5945 | 36 | #define THROTTLE_MAX 2400.0f |
bwang | 10:7624146c5945 | 37 | #define THROTTLE_ERROR 4800.0f |
bwang | 10:7624146c5945 | 38 | #define THROTTLE_MIN 500.0f |
bwang | 10:7624146c5945 | 39 | |
bwang | 10:7624146c5945 | 40 | #define Q_REF_MAX 20.0 |
bwang | 10:7624146c5945 | 41 | |
bwang | 1:7b61790f6be9 | 42 | FastPWM *a; |
bwang | 1:7b61790f6be9 | 43 | FastPWM *b; |
bwang | 1:7b61790f6be9 | 44 | FastPWM *c; |
bwang | 0:bac9c3a3a6ca | 45 | DigitalOut en(EN); |
bwang | 0:bac9c3a3a6ca | 46 | |
bwang | 10:7624146c5945 | 47 | InterruptIn throttle_interrupt(PC_10); |
bwang | 0:bac9c3a3a6ca | 48 | PositionSensorEncoder pos(CPR, 0); |
bwang | 0:bac9c3a3a6ca | 49 | |
bwang | 1:7b61790f6be9 | 50 | int adval1, adval2; |
bwang | 8:314074b56470 | 51 | float ia, ib, ic, alpha, beta, q; |
bwang | 10:7624146c5945 | 52 | double vq = 0.0, q_integral = 0.0, last_q = 0.0; |
bwang | 10:7624146c5945 | 53 | float throttle = 0.0f; |
bwang | 10:7624146c5945 | 54 | |
bwang | 10:7624146c5945 | 55 | int edge_seen = 0, watchdog_divider = 0; |
bwang | 8:314074b56470 | 56 | |
bwang | 1:7b61790f6be9 | 57 | extern "C" void TIM1_UP_TIM10_IRQHandler(void) { |
bwang | 8:314074b56470 | 58 | if (TIM1->SR & TIM_SR_UIF) { |
bwang | 8:314074b56470 | 59 | float p = pos.GetElecPosition() - POS_OFFSET; |
bwang | 8:314074b56470 | 60 | if (p < 0) p += 2 * PI; |
bwang | 8:314074b56470 | 61 | |
bwang | 8:314074b56470 | 62 | //float pos_dac = 0.85f * p / (2 * PI) + 0.05f; |
bwang | 8:314074b56470 | 63 | //DAC->DHR12R2 = (unsigned int) (pos_dac * 4096); |
bwang | 8:314074b56470 | 64 | |
bwang | 8:314074b56470 | 65 | float sin_p = sinf(p); |
bwang | 8:314074b56470 | 66 | float cos_p = cosf(p); |
bwang | 8:314074b56470 | 67 | |
bwang | 4:a6669248ce4d | 68 | ADC1->CR2 |= 0x40000000; |
bwang | 4:a6669248ce4d | 69 | volatile int delay; |
bwang | 4:a6669248ce4d | 70 | for (delay = 0; delay < 35; delay++); |
bwang | 1:7b61790f6be9 | 71 | adval1 = ADC1->DR; |
bwang | 1:7b61790f6be9 | 72 | adval2 = ADC2->DR; |
bwang | 8:314074b56470 | 73 | |
bwang | 8:314074b56470 | 74 | ia = ((float) adval1 / 4096.0f * AVDD - I_OFFSET) / I_SCALE; |
bwang | 8:314074b56470 | 75 | ib = ((float) adval2 / 4096.0f * AVDD - I_OFFSET) / I_SCALE; |
bwang | 8:314074b56470 | 76 | ic = -ia - ib; |
bwang | 8:314074b56470 | 77 | |
bwang | 8:314074b56470 | 78 | float u = ib; |
bwang | 8:314074b56470 | 79 | float v = ic; |
bwang | 8:314074b56470 | 80 | |
bwang | 8:314074b56470 | 81 | alpha = u; |
bwang | 8:314074b56470 | 82 | beta = 1 / sqrtf(3.0f) * u + 2 / sqrtf(3.0f) * v; |
bwang | 8:314074b56470 | 83 | |
bwang | 8:314074b56470 | 84 | q = -alpha * sin_p - beta * cos_p; |
bwang | 8:314074b56470 | 85 | |
bwang | 10:7624146c5945 | 86 | if(edge_seen == 0) throttle = THROTTLE_MIN; |
bwang | 10:7624146c5945 | 87 | if (throttle < THROTTLE_MIN || throttle > THROTTLE_ERROR) throttle = THROTTLE_MIN; |
bwang | 10:7624146c5945 | 88 | if (throttle > THROTTLE_MAX) throttle = THROTTLE_MAX; |
bwang | 10:7624146c5945 | 89 | float throttle_scaler = (throttle - THROTTLE_MIN) / (THROTTLE_MAX - THROTTLE_MIN); |
bwang | 8:314074b56470 | 90 | |
bwang | 10:7624146c5945 | 91 | double q_err = Q_REF_MAX * (double) throttle_scaler - q; |
bwang | 10:7624146c5945 | 92 | |
bwang | 10:7624146c5945 | 93 | //DAC->DHR12R2 = (unsigned int) (q_err * 20 + 2048); |
bwang | 8:314074b56470 | 94 | |
bwang | 8:314074b56470 | 95 | q_integral += q_err * KI; |
bwang | 8:314074b56470 | 96 | if (q_integral > INTEGRAL_MAX) q_integral = INTEGRAL_MAX; |
bwang | 8:314074b56470 | 97 | if (q_integral < -INTEGRAL_MAX) q_integral = -INTEGRAL_MAX; |
bwang | 8:314074b56470 | 98 | |
bwang | 8:314074b56470 | 99 | vq = KP * q_err + q_integral; |
bwang | 8:314074b56470 | 100 | if (vq < -1.0f) vq = -1.0f; |
bwang | 8:314074b56470 | 101 | if (vq > 1.0f) vq = 1.0f; |
bwang | 9:4812c9e932ea | 102 | |
bwang | 9:4812c9e932ea | 103 | //DAC->DHR12R2 = (unsigned int) (vq * 2000 + 2048); |
bwang | 9:4812c9e932ea | 104 | |
bwang | 8:314074b56470 | 105 | *a = 0.5f + 0.5f * vq * sinf(p); |
bwang | 8:314074b56470 | 106 | *b = 0.5f + 0.5f * vq * sinf(p + 2 * PI / 3); |
bwang | 8:314074b56470 | 107 | *c = 0.5f + 0.5f * vq * sinf(p - 2 * PI / 3); |
bwang | 10:7624146c5945 | 108 | |
bwang | 10:7624146c5945 | 109 | watchdog_divider++; |
bwang | 10:7624146c5945 | 110 | if (watchdog_divider == 15000) { |
bwang | 10:7624146c5945 | 111 | watchdog_divider = 0; |
bwang | 10:7624146c5945 | 112 | edge_seen = 0; |
bwang | 10:7624146c5945 | 113 | } |
bwang | 1:7b61790f6be9 | 114 | } |
bwang | 1:7b61790f6be9 | 115 | TIM1->SR = 0x00; |
bwang | 1:7b61790f6be9 | 116 | } |
bwang | 10:7624146c5945 | 117 | |
bwang | 10:7624146c5945 | 118 | void throttle_rise() { |
bwang | 10:7624146c5945 | 119 | TIM5->CNT = 0; |
bwang | 10:7624146c5945 | 120 | edge_seen = 1; |
bwang | 10:7624146c5945 | 121 | } |
bwang | 10:7624146c5945 | 122 | |
bwang | 10:7624146c5945 | 123 | void throttle_fall() { |
bwang | 10:7624146c5945 | 124 | throttle = TIM5->CNT; |
bwang | 10:7624146c5945 | 125 | edge_seen = 1; |
bwang | 10:7624146c5945 | 126 | } |
bwang | 10:7624146c5945 | 127 | |
bwang | 8:314074b56470 | 128 | int main() { |
bwang | 1:7b61790f6be9 | 129 | //Enable clocks for GPIOs |
bwang | 1:7b61790f6be9 | 130 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; |
bwang | 1:7b61790f6be9 | 131 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; |
bwang | 1:7b61790f6be9 | 132 | RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; |
bwang | 1:7b61790f6be9 | 133 | |
bwang | 1:7b61790f6be9 | 134 | RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable TIM1 clock |
bwang | 1:7b61790f6be9 | 135 | |
bwang | 1:7b61790f6be9 | 136 | a = new FastPWM(PWMA); |
bwang | 1:7b61790f6be9 | 137 | b = new FastPWM(PWMB); |
bwang | 1:7b61790f6be9 | 138 | c = new FastPWM(PWMC); |
bwang | 1:7b61790f6be9 | 139 | |
bwang | 1:7b61790f6be9 | 140 | NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ |
bwang | 1:7b61790f6be9 | 141 | |
bwang | 1:7b61790f6be9 | 142 | TIM1->DIER |= TIM_DIER_UIE; //enable update interrupt |
bwang | 8:314074b56470 | 143 | //TIM1->CR1 = 0x40; //CMS = 10, interrupt only when counting up |
bwang | 1:7b61790f6be9 | 144 | TIM1->CR1 |= TIM_CR1_ARPE; //autoreload on, |
bwang | 1:7b61790f6be9 | 145 | TIM1->RCR |= 0x01; //update event once per up/down count of tim1 |
bwang | 1:7b61790f6be9 | 146 | TIM1->EGR |= TIM_EGR_UG; |
bwang | 1:7b61790f6be9 | 147 | |
bwang | 1:7b61790f6be9 | 148 | TIM1->PSC = 0x00; //no prescaler, timer counts up in sync with the peripheral clock |
bwang | 8:314074b56470 | 149 | TIM1->ARR = 0x2EE0; |
bwang | 8:314074b56470 | 150 | //TIM1->ARR = 0x1770; //15 Khz |
bwang | 1:7b61790f6be9 | 151 | TIM1->CCER |= ~(TIM_CCER_CC1NP); //Interupt when low side is on. |
bwang | 1:7b61790f6be9 | 152 | TIM1->CR1 |= TIM_CR1_CEN; |
bwang | 1:7b61790f6be9 | 153 | |
bwang | 10:7624146c5945 | 154 | TIM5->CR1 |= TIM_CR1_ARPE; |
bwang | 10:7624146c5945 | 155 | TIM5->EGR |= TIM_EGR_UG; |
bwang | 10:7624146c5945 | 156 | TIM5->PSC = 0x00; |
bwang | 10:7624146c5945 | 157 | TIM5->ARR = 0xFFFFFFFF; |
bwang | 10:7624146c5945 | 158 | TIM5->CR1 |= TIM_CR1_CEN; |
bwang | 10:7624146c5945 | 159 | |
bwang | 1:7b61790f6be9 | 160 | //ADC Setup |
bwang | 1:7b61790f6be9 | 161 | RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1 |
bwang | 1:7b61790f6be9 | 162 | RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2 |
bwang | 1:7b61790f6be9 | 163 | |
bwang | 1:7b61790f6be9 | 164 | ADC->CCR = 0x00000006; //Regular simultaneous mode, 3 channels |
bwang | 1:7b61790f6be9 | 165 | |
bwang | 1:7b61790f6be9 | 166 | ADC1->CR2 |= ADC_CR2_ADON; //ADC1 on |
bwang | 1:7b61790f6be9 | 167 | ADC1->SQR3 = 0x0000004; //PA_4 as ADC1, sequence 0 |
bwang | 0:bac9c3a3a6ca | 168 | |
bwang | 1:7b61790f6be9 | 169 | ADC2->CR2 |= ADC_CR2_ADON; //ADC2 ON |
bwang | 1:7b61790f6be9 | 170 | ADC2->SQR3 = 0x00000008; //PB_0 as ADC2, sequence 1 |
bwang | 1:7b61790f6be9 | 171 | |
bwang | 1:7b61790f6be9 | 172 | GPIOA->MODER |= (1 << 8); |
bwang | 1:7b61790f6be9 | 173 | GPIOA->MODER |= (1 << 9); |
bwang | 1:7b61790f6be9 | 174 | |
bwang | 1:7b61790f6be9 | 175 | GPIOA->MODER |= (1 << 2); |
bwang | 1:7b61790f6be9 | 176 | GPIOA->MODER |= (1 << 3); |
bwang | 1:7b61790f6be9 | 177 | |
bwang | 1:7b61790f6be9 | 178 | GPIOA->MODER |= (1 << 0); |
bwang | 1:7b61790f6be9 | 179 | GPIOA->MODER |= (1 << 1); |
bwang | 1:7b61790f6be9 | 180 | |
bwang | 1:7b61790f6be9 | 181 | GPIOB->MODER |= (1 << 0); |
bwang | 1:7b61790f6be9 | 182 | GPIOB->MODER |= (1 << 1); |
bwang | 1:7b61790f6be9 | 183 | |
bwang | 1:7b61790f6be9 | 184 | GPIOC->MODER |= (1 << 2); |
bwang | 1:7b61790f6be9 | 185 | GPIOC->MODER |= (1 << 3); |
bwang | 1:7b61790f6be9 | 186 | |
bwang | 1:7b61790f6be9 | 187 | //DAC setup |
bwang | 1:7b61790f6be9 | 188 | RCC->APB1ENR |= 0x20000000; |
bwang | 1:7b61790f6be9 | 189 | DAC->CR |= DAC_CR_EN2; |
bwang | 1:7b61790f6be9 | 190 | |
bwang | 1:7b61790f6be9 | 191 | GPIOA->MODER |= (1 << 10); |
bwang | 1:7b61790f6be9 | 192 | GPIOA->MODER |= (1 << 11); |
bwang | 1:7b61790f6be9 | 193 | |
bwang | 8:314074b56470 | 194 | *a = 0.0f; |
bwang | 8:314074b56470 | 195 | *b = 0.0f; |
bwang | 8:314074b56470 | 196 | *c = 0.0f; |
bwang | 2:eabe8feaaabb | 197 | |
bwang | 8:314074b56470 | 198 | en = 1; |
bwang | 0:bac9c3a3a6ca | 199 | |
bwang | 10:7624146c5945 | 200 | throttle_interrupt.rise(throttle_rise); |
bwang | 10:7624146c5945 | 201 | throttle_interrupt.fall(throttle_fall); |
bwang | 10:7624146c5945 | 202 | |
bwang | 0:bac9c3a3a6ca | 203 | for (;;) { |
bwang | 0:bac9c3a3a6ca | 204 | } |
bwang | 0:bac9c3a3a6ca | 205 | } |