Bayley Wang / Mbed 2 deprecated qonly_controller

derp

Dependencies:   FastPWM3 mbed

main.cpp@8:314074b56470, 2016-04-04 (annotated)

Committer:
bwang
Date:
Mon Apr 04 09:02:59 2016 +0000
Revision:
8:314074b56470
Parent:
7:caebf421f288
Child:
9:4812c9e932ea
ship it

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bwang 0:bac9c3a3a6ca 1 #include "mbed.h"
bwang 0:bac9c3a3a6ca 2 #include "math.h"
bwang 0:bac9c3a3a6ca 3 #include "PositionSensor.h"
bwang 0:bac9c3a3a6ca 4 #include "FastPWM.h"
bwang 8:314074b56470 5
bwang 8:314074b56470 6 #define PWMA PA_8
bwang 8:314074b56470 7 #define PWMB PA_9
bwang 8:314074b56470 8 #define PWMC PA_10
bwang 8:314074b56470 9 #define EN PB_15
bwang 8:314074b56470 10
bwang 8:314074b56470 11 #define IA PA_4
bwang 8:314074b56470 12 #define IB PB_0
bwang 8:314074b56470 13
bwang 8:314074b56470 14 #define PI 3.141593f
bwang 8:314074b56470 15 #define CPR 4096
bwang 8:314074b56470 16 #define POS_OFFSET 4.5f
bwang 8:314074b56470 17
bwang 8:314074b56470 18 #define I_SCALE_RAW 25.0f //mv/A
bwang 8:314074b56470 19 #define R_UP 12000.0f //ohms
bwang 8:314074b56470 20 #define R_DOWN 3600.0f //ohms
bwang 8:314074b56470 21 #define R_BIAS 3600.0f //ohms
bwang 8:314074b56470 22 #define AVDD 3300.0f //mV
bwang 8:314074b56470 23
bwang 8:314074b56470 24 #define I_OFFSET (AVDD * R_DOWN * R_UP / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 25 #define I_SCALE (R_BIAS * R_DOWN * I_SCALE_RAW / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 26
bwang 8:314074b56470 27 #define K_LOOP 0.02
bwang 8:314074b56470 28 #define KI_BASE 0.008
bwang 8:314074b56470 29 #define BUS_VOLTAGE 20.0
bwang 8:314074b56470 30
bwang 8:314074b56470 31 #define KP (K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 32 #define KI (KI_BASE * K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 33
bwang 8:314074b56470 34 #define INTEGRAL_MAX 1.0f
bwang 0:bac9c3a3a6ca 35
bwang 1:7b61790f6be9 36 FastPWM *a;
bwang 1:7b61790f6be9 37 FastPWM *b;
bwang 1:7b61790f6be9 38 FastPWM *c;
bwang 0:bac9c3a3a6ca 39 DigitalOut en(EN);
bwang 8:314074b56470 40 DigitalOut toggle(PC_10);
bwang 0:bac9c3a3a6ca 41
bwang 0:bac9c3a3a6ca 42 PositionSensorEncoder pos(CPR, 0);
bwang 0:bac9c3a3a6ca 43
bwang 1:7b61790f6be9 44 int adval1, adval2;
bwang 8:314074b56470 45 float ia, ib, ic, alpha, beta, q;
bwang 8:314074b56470 46 double vq = 0.0, q_integral = 0.0, last_q = 0.0, q_ref = 250.0, q_filtered = 0.0;
bwang 8:314074b56470 47
bwang 1:7b61790f6be9 48 extern "C" void TIM1_UP_TIM10_IRQHandler(void) {
bwang 8:314074b56470 49 if (TIM1->SR & TIM_SR_UIF) {
bwang 8:314074b56470 50 float p = pos.GetElecPosition() - POS_OFFSET;
bwang 8:314074b56470 51 if (p < 0) p += 2 * PI;
bwang 8:314074b56470 52
bwang 8:314074b56470 53 //float pos_dac = 0.85f * p / (2 * PI) + 0.05f;
bwang 8:314074b56470 54 //DAC->DHR12R2 = (unsigned int) (pos_dac * 4096);
bwang 8:314074b56470 55
bwang 8:314074b56470 56 float sin_p = sinf(p);
bwang 8:314074b56470 57 float cos_p = cosf(p);
bwang 8:314074b56470 58
bwang 4:a6669248ce4d 59 ADC1->CR2 |= 0x40000000;
bwang 4:a6669248ce4d 60 volatile int delay;
bwang 4:a6669248ce4d 61 for (delay = 0; delay < 35; delay++);
bwang 1:7b61790f6be9 62 adval1 = ADC1->DR;
bwang 1:7b61790f6be9 63 adval2 = ADC2->DR;
bwang 8:314074b56470 64
bwang 8:314074b56470 65 ia = ((float) adval1 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 66 ib = ((float) adval2 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 67 ic = -ia - ib;
bwang 8:314074b56470 68
bwang 8:314074b56470 69 float u = ib;
bwang 8:314074b56470 70 float v = ic;
bwang 8:314074b56470 71
bwang 8:314074b56470 72 alpha = u;
bwang 8:314074b56470 73 beta = 1 / sqrtf(3.0f) * u + 2 / sqrtf(3.0f) * v;
bwang 8:314074b56470 74
bwang 8:314074b56470 75 q = -alpha * sin_p - beta * cos_p;
bwang 8:314074b56470 76 q_filtered = 0.1 * (double) q + 0.9 * q_filtered;
bwang 8:314074b56470 77
bwang 8:314074b56470 78 DAC->DHR12R2 = (unsigned int) (q_filtered * 20 + 2048);
bwang 8:314074b56470 79
bwang 8:314074b56470 80 double q_err = q_ref - q_filtered;
bwang 8:314074b56470 81
bwang 8:314074b56470 82 q_integral += q_err * KI;
bwang 8:314074b56470 83 if (q_integral > INTEGRAL_MAX) q_integral = INTEGRAL_MAX;
bwang 8:314074b56470 84 if (q_integral < -INTEGRAL_MAX) q_integral = -INTEGRAL_MAX;
bwang 8:314074b56470 85
bwang 8:314074b56470 86 vq = KP * q_err + q_integral;
bwang 8:314074b56470 87 if (vq < -1.0f) vq = -1.0f;
bwang 8:314074b56470 88 if (vq > 1.0f) vq = 1.0f;
bwang 8:314074b56470 89
bwang 8:314074b56470 90 *a = 0.5f + 0.5f * vq * sinf(p);
bwang 8:314074b56470 91 *b = 0.5f + 0.5f * vq * sinf(p + 2 * PI / 3);
bwang 8:314074b56470 92 *c = 0.5f + 0.5f * vq * sinf(p - 2 * PI / 3);
bwang 1:7b61790f6be9 93 }
bwang 1:7b61790f6be9 94 TIM1->SR = 0x00;
bwang 1:7b61790f6be9 95 }
bwang 8:314074b56470 96
bwang 8:314074b56470 97 int main() {
bwang 1:7b61790f6be9 98 //Enable clocks for GPIOs
bwang 1:7b61790f6be9 99 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
bwang 1:7b61790f6be9 100 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
bwang 1:7b61790f6be9 101 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
bwang 1:7b61790f6be9 102
bwang 1:7b61790f6be9 103 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable TIM1 clock
bwang 1:7b61790f6be9 104
bwang 1:7b61790f6be9 105 a = new FastPWM(PWMA);
bwang 1:7b61790f6be9 106 b = new FastPWM(PWMB);
bwang 1:7b61790f6be9 107 c = new FastPWM(PWMC);
bwang 1:7b61790f6be9 108
bwang 1:7b61790f6be9 109 NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ
bwang 1:7b61790f6be9 110
bwang 1:7b61790f6be9 111 TIM1->DIER |= TIM_DIER_UIE; //enable update interrupt
bwang 8:314074b56470 112 //TIM1->CR1 = 0x40; //CMS = 10, interrupt only when counting up
bwang 1:7b61790f6be9 113 TIM1->CR1 |= TIM_CR1_ARPE; //autoreload on,
bwang 1:7b61790f6be9 114 TIM1->RCR |= 0x01; //update event once per up/down count of tim1
bwang 1:7b61790f6be9 115 TIM1->EGR |= TIM_EGR_UG;
bwang 1:7b61790f6be9 116
bwang 1:7b61790f6be9 117 TIM1->PSC = 0x00; //no prescaler, timer counts up in sync with the peripheral clock
bwang 8:314074b56470 118 TIM1->ARR = 0x2EE0;
bwang 8:314074b56470 119 //TIM1->ARR = 0x1770; //15 Khz
bwang 1:7b61790f6be9 120 TIM1->CCER |= ~(TIM_CCER_CC1NP); //Interupt when low side is on.
bwang 1:7b61790f6be9 121 TIM1->CR1 |= TIM_CR1_CEN;
bwang 1:7b61790f6be9 122
bwang 1:7b61790f6be9 123 //ADC Setup
bwang 1:7b61790f6be9 124 RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1
bwang 1:7b61790f6be9 125 RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2
bwang 1:7b61790f6be9 126
bwang 1:7b61790f6be9 127 ADC->CCR = 0x00000006; //Regular simultaneous mode, 3 channels
bwang 1:7b61790f6be9 128
bwang 1:7b61790f6be9 129 ADC1->CR2 |= ADC_CR2_ADON; //ADC1 on
bwang 1:7b61790f6be9 130 ADC1->SQR3 = 0x0000004; //PA_4 as ADC1, sequence 0
bwang 0:bac9c3a3a6ca 131
bwang 1:7b61790f6be9 132 ADC2->CR2 |= ADC_CR2_ADON; //ADC2 ON
bwang 1:7b61790f6be9 133 ADC2->SQR3 = 0x00000008; //PB_0 as ADC2, sequence 1
bwang 1:7b61790f6be9 134
bwang 1:7b61790f6be9 135 GPIOA->MODER |= (1 << 8);
bwang 1:7b61790f6be9 136 GPIOA->MODER |= (1 << 9);
bwang 1:7b61790f6be9 137
bwang 1:7b61790f6be9 138 GPIOA->MODER |= (1 << 2);
bwang 1:7b61790f6be9 139 GPIOA->MODER |= (1 << 3);
bwang 1:7b61790f6be9 140
bwang 1:7b61790f6be9 141 GPIOA->MODER |= (1 << 0);
bwang 1:7b61790f6be9 142 GPIOA->MODER |= (1 << 1);
bwang 1:7b61790f6be9 143
bwang 1:7b61790f6be9 144 GPIOB->MODER |= (1 << 0);
bwang 1:7b61790f6be9 145 GPIOB->MODER |= (1 << 1);
bwang 1:7b61790f6be9 146
bwang 1:7b61790f6be9 147 GPIOC->MODER |= (1 << 2);
bwang 1:7b61790f6be9 148 GPIOC->MODER |= (1 << 3);
bwang 1:7b61790f6be9 149
bwang 1:7b61790f6be9 150 //DAC setup
bwang 1:7b61790f6be9 151 RCC->APB1ENR |= 0x20000000;
bwang 1:7b61790f6be9 152 DAC->CR |= DAC_CR_EN2;
bwang 1:7b61790f6be9 153
bwang 1:7b61790f6be9 154 GPIOA->MODER |= (1 << 10);
bwang 1:7b61790f6be9 155 GPIOA->MODER |= (1 << 11);
bwang 1:7b61790f6be9 156
bwang 8:314074b56470 157 *a = 0.0f;
bwang 8:314074b56470 158 *b = 0.0f;
bwang 8:314074b56470 159 *c = 0.0f;
bwang 2:eabe8feaaabb 160
bwang 8:314074b56470 161 en = 1;
bwang 0:bac9c3a3a6ca 162
bwang 0:bac9c3a3a6ca 163 for (;;) {
bwang 0:bac9c3a3a6ca 164 }
bwang 0:bac9c3a3a6ca 165 }