Bayley Wang / Mbed 2 deprecated qonly_controller

derp

Dependencies:   FastPWM3 mbed

main.cpp@12:0811d08424e1, 2016-04-18 (annotated)

Committer:
bwang
Date:
Mon Apr 18 21:06:26 2016 +0000
Revision:
12:0811d08424e1
Parent:
11:825203ff4371
Child:
13:728ddd6939d3
Child:
15:8eb1dfbf0d41
wut

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bwang 0:bac9c3a3a6ca 1 #include "mbed.h"
bwang 0:bac9c3a3a6ca 2 #include "math.h"
bwang 0:bac9c3a3a6ca 3 #include "PositionSensor.h"
bwang 0:bac9c3a3a6ca 4 #include "FastPWM.h"
bwang 8:314074b56470 5
bwang 8:314074b56470 6 #define PWMA PA_8
bwang 8:314074b56470 7 #define PWMB PA_9
bwang 8:314074b56470 8 #define PWMC PA_10
bwang 8:314074b56470 9 #define EN PB_15
bwang 8:314074b56470 10
bwang 8:314074b56470 11 #define IA PA_4
bwang 8:314074b56470 12 #define IB PB_0
bwang 8:314074b56470 13
bwang 8:314074b56470 14 #define PI 3.141593f
bwang 8:314074b56470 15 #define CPR 4096
bwang 8:314074b56470 16 #define POS_OFFSET 4.5f
bwang 8:314074b56470 17
bwang 8:314074b56470 18 #define I_SCALE_RAW 25.0f //mv/A
bwang 8:314074b56470 19 #define R_UP 12000.0f //ohms
bwang 8:314074b56470 20 #define R_DOWN 3600.0f //ohms
bwang 8:314074b56470 21 #define R_BIAS 3600.0f //ohms
bwang 8:314074b56470 22 #define AVDD 3300.0f //mV
bwang 8:314074b56470 23
bwang 8:314074b56470 24 #define I_OFFSET (AVDD * R_DOWN * R_UP / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 25 #define I_SCALE (R_BIAS * R_DOWN * I_SCALE_RAW / (R_DOWN * R_UP + R_BIAS * (R_DOWN + R_UP)))
bwang 8:314074b56470 26
bwang 8:314074b56470 27 #define K_LOOP 0.02
bwang 10:7624146c5945 28 #define KI_BASE 0.008
bwang 8:314074b56470 29 #define BUS_VOLTAGE 20.0
bwang 8:314074b56470 30
bwang 8:314074b56470 31 #define KP (K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 32 #define KI (KI_BASE * K_LOOP / BUS_VOLTAGE)
bwang 8:314074b56470 33
bwang 8:314074b56470 34 #define INTEGRAL_MAX 1.0f
bwang 0:bac9c3a3a6ca 35
bwang 12:0811d08424e1 36 #define THROTTLE_MAX 1900.0f
bwang 12:0811d08424e1 37 #define THROTTLE_MIN 1600.0f
bwang 12:0811d08424e1 38
bwang 12:0811d08424e1 39 #define THROTTLE_HIGH 5000.0f
bwang 12:0811d08424e1 40 #define THROTTLE_LOW 1550.0f
bwang 10:7624146c5945 41
bwang 11:825203ff4371 42 #define Q_REF_MAX (-200.0)
bwang 10:7624146c5945 43
bwang 1:7b61790f6be9 44 FastPWM *a;
bwang 1:7b61790f6be9 45 FastPWM *b;
bwang 1:7b61790f6be9 46 FastPWM *c;
bwang 0:bac9c3a3a6ca 47 DigitalOut en(EN);
bwang 0:bac9c3a3a6ca 48
bwang 11:825203ff4371 49 InterruptIn throttle_interrupt(PB_8);
bwang 0:bac9c3a3a6ca 50 PositionSensorEncoder pos(CPR, 0);
bwang 0:bac9c3a3a6ca 51
bwang 1:7b61790f6be9 52 int adval1, adval2;
bwang 8:314074b56470 53 float ia, ib, ic, alpha, beta, q;
bwang 10:7624146c5945 54 double vq = 0.0, q_integral = 0.0, last_q = 0.0;
bwang 12:0811d08424e1 55 volatile float throttle = 0.0f, throttle_scaler = 0.0f;
bwang 10:7624146c5945 56
bwang 12:0811d08424e1 57 volatile int edge_seen = 0, watchdog_divider = 0;
bwang 11:825203ff4371 58
bwang 12:0811d08424e1 59 volatile int err_throttle_too_low = 0, err_throttle_too_high = 0;
bwang 8:314074b56470 60
bwang 1:7b61790f6be9 61 extern "C" void TIM1_UP_TIM10_IRQHandler(void) {
bwang 8:314074b56470 62 if (TIM1->SR & TIM_SR_UIF) {
bwang 8:314074b56470 63 float p = pos.GetElecPosition() - POS_OFFSET;
bwang 8:314074b56470 64 if (p < 0) p += 2 * PI;
bwang 8:314074b56470 65
bwang 8:314074b56470 66 //float pos_dac = 0.85f * p / (2 * PI) + 0.05f;
bwang 8:314074b56470 67 //DAC->DHR12R2 = (unsigned int) (pos_dac * 4096);
bwang 8:314074b56470 68
bwang 8:314074b56470 69 float sin_p = sinf(p);
bwang 8:314074b56470 70 float cos_p = cosf(p);
bwang 8:314074b56470 71
bwang 4:a6669248ce4d 72 ADC1->CR2 |= 0x40000000;
bwang 4:a6669248ce4d 73 volatile int delay;
bwang 4:a6669248ce4d 74 for (delay = 0; delay < 35; delay++);
bwang 1:7b61790f6be9 75 adval1 = ADC1->DR;
bwang 1:7b61790f6be9 76 adval2 = ADC2->DR;
bwang 8:314074b56470 77
bwang 8:314074b56470 78 ia = ((float) adval1 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 79 ib = ((float) adval2 / 4096.0f * AVDD - I_OFFSET) / I_SCALE;
bwang 8:314074b56470 80 ic = -ia - ib;
bwang 8:314074b56470 81
bwang 8:314074b56470 82 float u = ib;
bwang 8:314074b56470 83 float v = ic;
bwang 8:314074b56470 84
bwang 8:314074b56470 85 alpha = u;
bwang 8:314074b56470 86 beta = 1 / sqrtf(3.0f) * u + 2 / sqrtf(3.0f) * v;
bwang 8:314074b56470 87
bwang 8:314074b56470 88 q = -alpha * sin_p - beta * cos_p;
bwang 8:314074b56470 89
bwang 12:0811d08424e1 90 DAC->DHR12R2 = throttle;
bwang 8:314074b56470 91
bwang 10:7624146c5945 92 double q_err = Q_REF_MAX * (double) throttle_scaler - q;
bwang 11:825203ff4371 93
bwang 10:7624146c5945 94 //DAC->DHR12R2 = (unsigned int) (q_err * 20 + 2048);
bwang 8:314074b56470 95
bwang 8:314074b56470 96 q_integral += q_err * KI;
bwang 8:314074b56470 97 if (q_integral > INTEGRAL_MAX) q_integral = INTEGRAL_MAX;
bwang 8:314074b56470 98 if (q_integral < -INTEGRAL_MAX) q_integral = -INTEGRAL_MAX;
bwang 8:314074b56470 99
bwang 8:314074b56470 100 vq = KP * q_err + q_integral;
bwang 8:314074b56470 101 if (vq < -1.0f) vq = -1.0f;
bwang 8:314074b56470 102 if (vq > 1.0f) vq = 1.0f;
bwang 11:825203ff4371 103
bwang 9:4812c9e932ea 104 //DAC->DHR12R2 = (unsigned int) (vq * 2000 + 2048);
bwang 12:0811d08424e1 105 //DAC->DHR12R2 = (unsigned int) (err_throttle_too_low * 2000 + 2048);
bwang 11:825203ff4371 106
bwang 8:314074b56470 107 *a = 0.5f + 0.5f * vq * sinf(p);
bwang 8:314074b56470 108 *b = 0.5f + 0.5f * vq * sinf(p + 2 * PI / 3);
bwang 8:314074b56470 109 *c = 0.5f + 0.5f * vq * sinf(p - 2 * PI / 3);
bwang 10:7624146c5945 110
bwang 10:7624146c5945 111 watchdog_divider++;
bwang 10:7624146c5945 112 if (watchdog_divider == 15000) {
bwang 10:7624146c5945 113 watchdog_divider = 0;
bwang 10:7624146c5945 114 edge_seen = 0;
bwang 10:7624146c5945 115 }
bwang 1:7b61790f6be9 116 }
bwang 1:7b61790f6be9 117 TIM1->SR = 0x00;
bwang 1:7b61790f6be9 118 }
bwang 10:7624146c5945 119
bwang 10:7624146c5945 120 void throttle_rise() {
bwang 10:7624146c5945 121 TIM5->CNT = 0;
bwang 10:7624146c5945 122 edge_seen = 1;
bwang 10:7624146c5945 123 }
bwang 10:7624146c5945 124
bwang 10:7624146c5945 125 void throttle_fall() {
bwang 10:7624146c5945 126 throttle = TIM5->CNT;
bwang 12:0811d08424e1 127
bwang 12:0811d08424e1 128 /*
bwang 12:0811d08424e1 129 if (throttle < THROTTLE_LOW) {
bwang 12:0811d08424e1 130 err_throttle_too_low = 1;
bwang 12:0811d08424e1 131 } else {
bwang 12:0811d08424e1 132 err_throttle_too_low = 0;
bwang 12:0811d08424e1 133 }
bwang 12:0811d08424e1 134
bwang 12:0811d08424e1 135 if (throttle > THROTTLE_HIGH) {
bwang 12:0811d08424e1 136 err_throttle_too_high = 1;
bwang 12:0811d08424e1 137 } else {
bwang 12:0811d08424e1 138 err_throttle_too_high = 0;
bwang 12:0811d08424e1 139 }
bwang 12:0811d08424e1 140 */
bwang 12:0811d08424e1 141
bwang 12:0811d08424e1 142 if (throttle < THROTTLE_MIN) throttle = THROTTLE_MIN;
bwang 12:0811d08424e1 143 if (throttle > THROTTLE_MAX) throttle = THROTTLE_MAX;
bwang 12:0811d08424e1 144 throttle_scaler = (throttle - THROTTLE_MIN) / (THROTTLE_MAX - THROTTLE_MIN);
bwang 12:0811d08424e1 145
bwang 12:0811d08424e1 146 /*
bwang 12:0811d08424e1 147 if (err_throttle_too_low || err_throttle_too_high || !edge_seen) {
bwang 12:0811d08424e1 148 en = 0;
bwang 12:0811d08424e1 149 } else {
bwang 12:0811d08424e1 150 en = 1;
bwang 12:0811d08424e1 151 }
bwang 12:0811d08424e1 152 */
bwang 12:0811d08424e1 153
bwang 10:7624146c5945 154 edge_seen = 1;
bwang 10:7624146c5945 155 }
bwang 10:7624146c5945 156
bwang 8:314074b56470 157 int main() {
bwang 1:7b61790f6be9 158 //Enable clocks for GPIOs
bwang 1:7b61790f6be9 159 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
bwang 1:7b61790f6be9 160 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;
bwang 1:7b61790f6be9 161 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
bwang 1:7b61790f6be9 162
bwang 1:7b61790f6be9 163 RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; //enable TIM1 clock
bwang 1:7b61790f6be9 164
bwang 1:7b61790f6be9 165 a = new FastPWM(PWMA);
bwang 1:7b61790f6be9 166 b = new FastPWM(PWMB);
bwang 1:7b61790f6be9 167 c = new FastPWM(PWMC);
bwang 1:7b61790f6be9 168
bwang 1:7b61790f6be9 169 NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); //Enable TIM1 IRQ
bwang 1:7b61790f6be9 170
bwang 1:7b61790f6be9 171 TIM1->DIER |= TIM_DIER_UIE; //enable update interrupt
bwang 8:314074b56470 172 //TIM1->CR1 = 0x40; //CMS = 10, interrupt only when counting up
bwang 1:7b61790f6be9 173 TIM1->CR1 |= TIM_CR1_ARPE; //autoreload on,
bwang 1:7b61790f6be9 174 TIM1->RCR |= 0x01; //update event once per up/down count of tim1
bwang 1:7b61790f6be9 175 TIM1->EGR |= TIM_EGR_UG;
bwang 1:7b61790f6be9 176
bwang 1:7b61790f6be9 177 TIM1->PSC = 0x00; //no prescaler, timer counts up in sync with the peripheral clock
bwang 8:314074b56470 178 TIM1->ARR = 0x2EE0;
bwang 8:314074b56470 179 //TIM1->ARR = 0x1770; //15 Khz
bwang 1:7b61790f6be9 180 TIM1->CCER |= ~(TIM_CCER_CC1NP); //Interupt when low side is on.
bwang 1:7b61790f6be9 181 TIM1->CR1 |= TIM_CR1_CEN;
bwang 1:7b61790f6be9 182
bwang 10:7624146c5945 183 TIM5->CR1 |= TIM_CR1_ARPE;
bwang 10:7624146c5945 184 TIM5->EGR |= TIM_EGR_UG;
bwang 10:7624146c5945 185 TIM5->PSC = 0x00;
bwang 10:7624146c5945 186 TIM5->ARR = 0xFFFFFFFF;
bwang 10:7624146c5945 187 TIM5->CR1 |= TIM_CR1_CEN;
bwang 10:7624146c5945 188
bwang 1:7b61790f6be9 189 //ADC Setup
bwang 1:7b61790f6be9 190 RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; // clock for ADC1
bwang 1:7b61790f6be9 191 RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; // clock for ADC2
bwang 1:7b61790f6be9 192
bwang 1:7b61790f6be9 193 ADC->CCR = 0x00000006; //Regular simultaneous mode, 3 channels
bwang 1:7b61790f6be9 194
bwang 1:7b61790f6be9 195 ADC1->CR2 |= ADC_CR2_ADON; //ADC1 on
bwang 1:7b61790f6be9 196 ADC1->SQR3 = 0x0000004; //PA_4 as ADC1, sequence 0
bwang 0:bac9c3a3a6ca 197
bwang 1:7b61790f6be9 198 ADC2->CR2 |= ADC_CR2_ADON; //ADC2 ON
bwang 1:7b61790f6be9 199 ADC2->SQR3 = 0x00000008; //PB_0 as ADC2, sequence 1
bwang 1:7b61790f6be9 200
bwang 1:7b61790f6be9 201 GPIOA->MODER |= (1 << 8);
bwang 1:7b61790f6be9 202 GPIOA->MODER |= (1 << 9);
bwang 1:7b61790f6be9 203
bwang 1:7b61790f6be9 204 GPIOA->MODER |= (1 << 2);
bwang 1:7b61790f6be9 205 GPIOA->MODER |= (1 << 3);
bwang 1:7b61790f6be9 206
bwang 1:7b61790f6be9 207 GPIOA->MODER |= (1 << 0);
bwang 1:7b61790f6be9 208 GPIOA->MODER |= (1 << 1);
bwang 1:7b61790f6be9 209
bwang 1:7b61790f6be9 210 GPIOB->MODER |= (1 << 0);
bwang 1:7b61790f6be9 211 GPIOB->MODER |= (1 << 1);
bwang 1:7b61790f6be9 212
bwang 1:7b61790f6be9 213 GPIOC->MODER |= (1 << 2);
bwang 1:7b61790f6be9 214 GPIOC->MODER |= (1 << 3);
bwang 1:7b61790f6be9 215
bwang 1:7b61790f6be9 216 //DAC setup
bwang 1:7b61790f6be9 217 RCC->APB1ENR |= 0x20000000;
bwang 1:7b61790f6be9 218 DAC->CR |= DAC_CR_EN2;
bwang 1:7b61790f6be9 219
bwang 1:7b61790f6be9 220 GPIOA->MODER |= (1 << 10);
bwang 1:7b61790f6be9 221 GPIOA->MODER |= (1 << 11);
bwang 1:7b61790f6be9 222
bwang 8:314074b56470 223 *a = 0.0f;
bwang 8:314074b56470 224 *b = 0.0f;
bwang 8:314074b56470 225 *c = 0.0f;
bwang 2:eabe8feaaabb 226
bwang 8:314074b56470 227 en = 1;
bwang 0:bac9c3a3a6ca 228
bwang 10:7624146c5945 229 throttle_interrupt.rise(throttle_rise);
bwang 10:7624146c5945 230 throttle_interrupt.fall(throttle_fall);
bwang 10:7624146c5945 231
bwang 0:bac9c3a3a6ca 232 for (;;) {
bwang 0:bac9c3a3a6ca 233 }
bwang 0:bac9c3a3a6ca 234 }