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_hw_enet Struct Reference

_hw_enet Struct Reference

All ENET module registers. More...

#include <MK64F12_enet.h>

Data Fields

__IO hw_enet_eir_t EIR
__IO hw_enet_eimr_t EIMR
__IO hw_enet_rdar_t RDAR
__IO hw_enet_tdar_t TDAR
__IO hw_enet_ecr_t ECR
__IO hw_enet_mmfr_t MMFR
__IO hw_enet_mscr_t MSCR
__IO hw_enet_mibc_t MIBC
__IO hw_enet_rcr_t RCR
__IO hw_enet_tcr_t TCR
__IO hw_enet_palr_t PALR
__IO hw_enet_paur_t PAUR
__IO hw_enet_opd_t OPD
__IO hw_enet_iaur_t IAUR
__IO hw_enet_ialr_t IALR
__IO hw_enet_gaur_t GAUR
__IO hw_enet_galr_t GALR
__IO hw_enet_tfwr_t TFWR
__IO hw_enet_rdsr_t RDSR
__IO hw_enet_tdsr_t TDSR
__IO hw_enet_mrbr_t MRBR
__IO hw_enet_rsfl_t RSFL
__IO hw_enet_rsem_t RSEM
__IO hw_enet_raem_t RAEM
__IO hw_enet_rafl_t RAFL
__IO hw_enet_tsem_t TSEM
__IO hw_enet_taem_t TAEM
__IO hw_enet_tafl_t TAFL
__IO hw_enet_tipg_t TIPG
__IO hw_enet_ftrl_t FTRL
__IO hw_enet_tacc_t TACC
__IO hw_enet_racc_t RACC
__I hw_enet_rmon_t_packets_t RMON_T_PACKETS
__I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT
__I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT
__I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN
__I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE
__I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE
__I hw_enet_rmon_t_frag_t RMON_T_FRAG
__I hw_enet_rmon_t_jab_t RMON_T_JAB
__I hw_enet_rmon_t_col_t RMON_T_COL
__I hw_enet_rmon_t_p64_t RMON_T_P64
__I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127
__I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255
__I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511
__I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023
__I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047
__I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048
__I hw_enet_rmon_t_octets_t RMON_T_OCTETS
__I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK
__I hw_enet_ieee_t_1col_t IEEE_T_1COL
__I hw_enet_ieee_t_mcol_t IEEE_T_MCOL
__I hw_enet_ieee_t_def_t IEEE_T_DEF
__I hw_enet_ieee_t_lcol_t IEEE_T_LCOL
__I hw_enet_ieee_t_excol_t IEEE_T_EXCOL
__I hw_enet_ieee_t_macerr_t IEEE_T_MACERR
__I hw_enet_ieee_t_cserr_t IEEE_T_CSERR
__I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC
__I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK
__I hw_enet_rmon_r_packets_t RMON_R_PACKETS
__I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT
__I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT
__I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN
__I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE
__I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE
__I hw_enet_rmon_r_frag_t RMON_R_FRAG
__I hw_enet_rmon_r_jab_t RMON_R_JAB
__I hw_enet_rmon_r_p64_t RMON_R_P64
__I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127
__I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255
__I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511
__I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023
__I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047
__I hw_enet_rmon_r_p_gte2048_t RMON_R_P_GTE2048
__I hw_enet_rmon_r_octets_t RMON_R_OCTETS
__I hw_enet_ieee_r_drop_t IEEE_R_DROP
__I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK
__I hw_enet_ieee_r_crc_t IEEE_R_CRC
__I hw_enet_ieee_r_align_t IEEE_R_ALIGN
__I hw_enet_ieee_r_macerr_t IEEE_R_MACERR
__I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC
__I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK
__IO hw_enet_atcr_t ATCR
__IO hw_enet_atvr_t ATVR
__IO hw_enet_atoff_t ATOFF
__IO hw_enet_atper_t ATPER
__IO hw_enet_atcor_t ATCOR
__IO hw_enet_atinc_t ATINC
__I hw_enet_atstmp_t ATSTMP
__IO hw_enet_tgsr_t TGSR
__IO hw_enet_tcsrn_t TCSRn
__IO hw_enet_tccrn_t TCCRn

Detailed Description

All ENET module registers.

Definition at line 7378 of file MK64F12_enet.h.


Field Documentation

[0x410] Timer Correction Register

Definition at line 7485 of file MK64F12_enet.h.

[0x400] Adjustable Timer Control Register

Definition at line 7481 of file MK64F12_enet.h.

[0x414] Time-Stamping Clock Period Register

Definition at line 7486 of file MK64F12_enet.h.

[0x408] Timer Offset Register

Definition at line 7483 of file MK64F12_enet.h.

[0x40C] Timer Period Register

Definition at line 7484 of file MK64F12_enet.h.

[0x418] Timestamp of Last Transmitted Frame

Definition at line 7487 of file MK64F12_enet.h.

[0x404] Timer Value Register

Definition at line 7482 of file MK64F12_enet.h.

[0x24] Ethernet Control Register

Definition at line 7387 of file MK64F12_enet.h.

[0x8] Interrupt Mask Register

Definition at line 7382 of file MK64F12_enet.h.

[0x4] Interrupt Event Register

Definition at line 7381 of file MK64F12_enet.h.

[0x1B0] Frame Truncation Length

Definition at line 7421 of file MK64F12_enet.h.

[0x124] Descriptor Group Lower Address Register

Definition at line 7405 of file MK64F12_enet.h.

[0x120] Descriptor Group Upper Address Register

Definition at line 7404 of file MK64F12_enet.h.

[0x11C] Descriptor Individual Lower Address Register

Definition at line 7403 of file MK64F12_enet.h.

[0x118] Descriptor Individual Upper Address Register

Definition at line 7402 of file MK64F12_enet.h.

[0x2D4] Frames Received with Alignment Error Statistic Register

Definition at line 7476 of file MK64F12_enet.h.

[0x2D0] Frames Received with CRC Error Statistic Register

Definition at line 7475 of file MK64F12_enet.h.

[0x2C8] Frames not Counted Correctly Statistic Register

Definition at line 7473 of file MK64F12_enet.h.

[0x2DC] Flow Control Pause Frames Received Statistic Register

Definition at line 7478 of file MK64F12_enet.h.

[0x2CC] Frames Received OK Statistic Register

Definition at line 7474 of file MK64F12_enet.h.

[0x2D8] Receive FIFO Overflow Count Statistic Register

Definition at line 7477 of file MK64F12_enet.h.

[0x2E0] Octet Count for Frames Received without Error Statistic Register

Definition at line 7479 of file MK64F12_enet.h.

[0x250] Frames Transmitted with Single Collision Statistic Register

Definition at line 7445 of file MK64F12_enet.h.

[0x268] Frames Transmitted with Carrier Sense Error Statistic Register

Definition at line 7451 of file MK64F12_enet.h.

[0x258] Frames Transmitted after Deferral Delay Statistic Register

Definition at line 7447 of file MK64F12_enet.h.

[0x260] Frames Transmitted with Excessive Collisions Statistic Register

Definition at line 7449 of file MK64F12_enet.h.

[0x270] Flow Control Pause Frames Transmitted Statistic Register

Definition at line 7453 of file MK64F12_enet.h.

[0x24C] Frames Transmitted OK Statistic Register

Definition at line 7444 of file MK64F12_enet.h.

[0x25C] Frames Transmitted with Late Collision Statistic Register

Definition at line 7448 of file MK64F12_enet.h.

[0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register

Definition at line 7450 of file MK64F12_enet.h.

[0x254] Frames Transmitted with Multiple Collisions Statistic Register

Definition at line 7446 of file MK64F12_enet.h.

[0x274] Octet Count for Frames Transmitted w/o Error Statistic Register

Definition at line 7454 of file MK64F12_enet.h.

[0x64] MIB Control Register

Definition at line 7392 of file MK64F12_enet.h.

[0x40] MII Management Frame Register

Definition at line 7389 of file MK64F12_enet.h.

[0x188] Maximum Receive Buffer Size Register

Definition at line 7411 of file MK64F12_enet.h.

[0x44] MII Speed Control Register

Definition at line 7390 of file MK64F12_enet.h.

[0xEC] Opcode/Pause Duration Register

Definition at line 7400 of file MK64F12_enet.h.

[0xE4] Physical Address Lower Register

Definition at line 7398 of file MK64F12_enet.h.

[0xE8] Physical Address Upper Register

Definition at line 7399 of file MK64F12_enet.h.

[0x1C4] Receive Accelerator Function Configuration

Definition at line 7424 of file MK64F12_enet.h.

[0x198] Receive FIFO Almost Empty Threshold

Definition at line 7415 of file MK64F12_enet.h.

[0x19C] Receive FIFO Almost Full Threshold

Definition at line 7416 of file MK64F12_enet.h.

[0x84] Receive Control Register

Definition at line 7394 of file MK64F12_enet.h.

[0x10] Receive Descriptor Active Register

Definition at line 7384 of file MK64F12_enet.h.

[0x180] Receive Descriptor Ring Start Register

Definition at line 7409 of file MK64F12_enet.h.

[0x288] Rx Broadcast Packets Statistic Register

Definition at line 7457 of file MK64F12_enet.h.

[0x290] Rx Packets with CRC/Align Error Statistic Register

Definition at line 7459 of file MK64F12_enet.h.

[0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register

Definition at line 7462 of file MK64F12_enet.h.

[0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register

Definition at line 7463 of file MK64F12_enet.h.

[0x28C] Rx Multicast Packets Statistic Register

Definition at line 7458 of file MK64F12_enet.h.

[0x2C4] Rx Octets Statistic Register

Definition at line 7472 of file MK64F12_enet.h.

[0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register

Definition at line 7461 of file MK64F12_enet.h.

[0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register

Definition at line 7470 of file MK64F12_enet.h.

[0x2B0] Rx 128- to 255-Byte Packets Statistic Register

Definition at line 7467 of file MK64F12_enet.h.

[0x2B4] Rx 256- to 511-Byte Packets Statistic Register

Definition at line 7468 of file MK64F12_enet.h.

[0x2B8] Rx 512- to 1023-Byte Packets Statistic Register

Definition at line 7469 of file MK64F12_enet.h.

[0x2A8] Rx 64-Byte Packets Statistic Register

Definition at line 7465 of file MK64F12_enet.h.

[0x2AC] Rx 65- to 127-Byte Packets Statistic Register

Definition at line 7466 of file MK64F12_enet.h.

[0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register

Definition at line 7471 of file MK64F12_enet.h.

[0x284] Rx Packet Count Statistic Register

Definition at line 7456 of file MK64F12_enet.h.

[0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register

Definition at line 7460 of file MK64F12_enet.h.

[0x208] Tx Broadcast Packets Statistic Register

Definition at line 7427 of file MK64F12_enet.h.

[0x224] Tx Collision Count Statistic Register

Definition at line 7434 of file MK64F12_enet.h.

[0x210] Tx Packets with CRC/Align Error Statistic Register

Definition at line 7429 of file MK64F12_enet.h.

[0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register

Definition at line 7432 of file MK64F12_enet.h.

[0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register

Definition at line 7433 of file MK64F12_enet.h.

[0x20C] Tx Multicast Packets Statistic Register

Definition at line 7428 of file MK64F12_enet.h.

[0x244] Tx Octets Statistic Register

Definition at line 7442 of file MK64F12_enet.h.

[0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register

Definition at line 7431 of file MK64F12_enet.h.

[0x23C] Tx 1024- to 2047-byte Packets Statistic Register

Definition at line 7440 of file MK64F12_enet.h.

[0x230] Tx 128- to 255-byte Packets Statistic Register

Definition at line 7437 of file MK64F12_enet.h.

[0x234] Tx 256- to 511-byte Packets Statistic Register

Definition at line 7438 of file MK64F12_enet.h.

[0x238] Tx 512- to 1023-byte Packets Statistic Register

Definition at line 7439 of file MK64F12_enet.h.

[0x228] Tx 64-Byte Packets Statistic Register

Definition at line 7435 of file MK64F12_enet.h.

[0x22C] Tx 65- to 127-byte Packets Statistic Register

Definition at line 7436 of file MK64F12_enet.h.

[0x240] Tx Packets Greater Than 2048 Bytes Statistic Register

Definition at line 7441 of file MK64F12_enet.h.

[0x204] Tx Packet Count Statistic Register

Definition at line 7426 of file MK64F12_enet.h.

[0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register

Definition at line 7430 of file MK64F12_enet.h.

[0x194] Receive FIFO Section Empty Threshold

Definition at line 7414 of file MK64F12_enet.h.

[0x190] Receive FIFO Section Full Threshold

Definition at line 7413 of file MK64F12_enet.h.

[0x1C0] Transmit Accelerator Function Configuration

Definition at line 7423 of file MK64F12_enet.h.

[0x1A4] Transmit FIFO Almost Empty Threshold

Definition at line 7418 of file MK64F12_enet.h.

[0x1A8] Transmit FIFO Almost Full Threshold

Definition at line 7419 of file MK64F12_enet.h.

[0x60C] Timer Compare Capture Register

Definition at line 7492 of file MK64F12_enet.h.

[0xC4] Transmit Control Register

Definition at line 7396 of file MK64F12_enet.h.

[0x608] Timer Control Status Register

Definition at line 7491 of file MK64F12_enet.h.

[0x14] Transmit Descriptor Active Register

Definition at line 7385 of file MK64F12_enet.h.

[0x184] Transmit Buffer Descriptor Ring Start Register

Definition at line 7410 of file MK64F12_enet.h.

[0x144] Transmit FIFO Watermark Register

Definition at line 7407 of file MK64F12_enet.h.

[0x604] Timer Global Status Register

Definition at line 7489 of file MK64F12_enet.h.

[0x1AC] Transmit Inter-Packet Gap

Definition at line 7420 of file MK64F12_enet.h.

[0x1A0] Transmit FIFO Section Empty Threshold

Definition at line 7417 of file MK64F12_enet.h.