MK64F12_enet.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_ENET_REGISTERS_H__
00088 #define __HW_ENET_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 ENET
00095  *
00096  * Ethernet MAC-NET Core
00097  *
00098  * Registers defined in this header file:
00099  * - HW_ENET_EIR - Interrupt Event Register
00100  * - HW_ENET_EIMR - Interrupt Mask Register
00101  * - HW_ENET_RDAR - Receive Descriptor Active Register
00102  * - HW_ENET_TDAR - Transmit Descriptor Active Register
00103  * - HW_ENET_ECR - Ethernet Control Register
00104  * - HW_ENET_MMFR - MII Management Frame Register
00105  * - HW_ENET_MSCR - MII Speed Control Register
00106  * - HW_ENET_MIBC - MIB Control Register
00107  * - HW_ENET_RCR - Receive Control Register
00108  * - HW_ENET_TCR - Transmit Control Register
00109  * - HW_ENET_PALR - Physical Address Lower Register
00110  * - HW_ENET_PAUR - Physical Address Upper Register
00111  * - HW_ENET_OPD - Opcode/Pause Duration Register
00112  * - HW_ENET_IAUR - Descriptor Individual Upper Address Register
00113  * - HW_ENET_IALR - Descriptor Individual Lower Address Register
00114  * - HW_ENET_GAUR - Descriptor Group Upper Address Register
00115  * - HW_ENET_GALR - Descriptor Group Lower Address Register
00116  * - HW_ENET_TFWR - Transmit FIFO Watermark Register
00117  * - HW_ENET_RDSR - Receive Descriptor Ring Start Register
00118  * - HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
00119  * - HW_ENET_MRBR - Maximum Receive Buffer Size Register
00120  * - HW_ENET_RSFL - Receive FIFO Section Full Threshold
00121  * - HW_ENET_RSEM - Receive FIFO Section Empty Threshold
00122  * - HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
00123  * - HW_ENET_RAFL - Receive FIFO Almost Full Threshold
00124  * - HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
00125  * - HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
00126  * - HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
00127  * - HW_ENET_TIPG - Transmit Inter-Packet Gap
00128  * - HW_ENET_FTRL - Frame Truncation Length
00129  * - HW_ENET_TACC - Transmit Accelerator Function Configuration
00130  * - HW_ENET_RACC - Receive Accelerator Function Configuration
00131  * - HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
00132  * - HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
00133  * - HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
00134  * - HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
00135  * - HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
00136  * - HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
00137  * - HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
00138  * - HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
00139  * - HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
00140  * - HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
00141  * - HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
00142  * - HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
00143  * - HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
00144  * - HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
00145  * - HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
00146  * - HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
00147  * - HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
00148  * - HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
00149  * - HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
00150  * - HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
00151  * - HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
00152  * - HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
00153  * - HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
00154  * - HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
00155  * - HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
00156  * - HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
00157  * - HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
00158  * - HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
00159  * - HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
00160  * - HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
00161  * - HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
00162  * - HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
00163  * - HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
00164  * - HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
00165  * - HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
00166  * - HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
00167  * - HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
00168  * - HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
00169  * - HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
00170  * - HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
00171  * - HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
00172  * - HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
00173  * - HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
00174  * - HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
00175  * - HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
00176  * - HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
00177  * - HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
00178  * - HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
00179  * - HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
00180  * - HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
00181  * - HW_ENET_ATCR - Adjustable Timer Control Register
00182  * - HW_ENET_ATVR - Timer Value Register
00183  * - HW_ENET_ATOFF - Timer Offset Register
00184  * - HW_ENET_ATPER - Timer Period Register
00185  * - HW_ENET_ATCOR - Timer Correction Register
00186  * - HW_ENET_ATINC - Time-Stamping Clock Period Register
00187  * - HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
00188  * - HW_ENET_TGSR - Timer Global Status Register
00189  * - HW_ENET_TCSRn - Timer Control Status Register
00190  * - HW_ENET_TCCRn - Timer Compare Capture Register
00191  *
00192  * - hw_enet_t - Struct containing all module registers.
00193  */
00194 
00195 #define HW_ENET_INSTANCE_COUNT (1U) /*!< Number of instances of the ENET module. */
00196 
00197 /*******************************************************************************
00198  * HW_ENET_EIR - Interrupt Event Register
00199  ******************************************************************************/
00200 
00201 /*!
00202  * @brief HW_ENET_EIR - Interrupt Event Register (RW)
00203  *
00204  * Reset value: 0x00000000U
00205  *
00206  * When an event occurs that sets a bit in EIR, an interrupt occurs if the
00207  * corresponding bit in the interrupt mask register (EIMR) is also set. Writing a 1 to
00208  * an EIR bit clears it; writing 0 has no effect. This register is cleared upon
00209  * hardware reset. TxBD[INT] and RxBD[INT] must be set to 1 to allow setting the
00210  * corresponding EIR register flags in enhanced mode, ENET_ECR[EN1588] = 1.
00211  * Legacy mode does not require these flags to be enabled.
00212  */
00213 typedef union _hw_enet_eir
00214 {
00215     uint32_t U;
00216     struct _hw_enet_eir_bitfields
00217     {
00218         uint32_t RESERVED0 : 15;       /*!< [14:0]  */
00219         uint32_t TS_TIMER : 1;         /*!< [15] Timestamp Timer */
00220         uint32_t TS_AVAIL : 1;         /*!< [16] Transmit Timestamp Available */
00221         uint32_t WAKEUP : 1;           /*!< [17] Node Wakeup Request Indication */
00222         uint32_t PLR : 1;              /*!< [18] Payload Receive Error */
00223         uint32_t UN : 1;               /*!< [19] Transmit FIFO Underrun */
00224         uint32_t RL : 1;               /*!< [20] Collision Retry Limit */
00225         uint32_t LC : 1;               /*!< [21] Late Collision */
00226         uint32_t EBERR : 1;            /*!< [22] Ethernet Bus Error */
00227         uint32_t MII : 1;              /*!< [23] MII Interrupt. */
00228         uint32_t RXB : 1;              /*!< [24] Receive Buffer Interrupt */
00229         uint32_t RXF : 1;              /*!< [25] Receive Frame Interrupt */
00230         uint32_t TXB : 1;              /*!< [26] Transmit Buffer Interrupt */
00231         uint32_t TXF : 1;              /*!< [27] Transmit Frame Interrupt */
00232         uint32_t GRA : 1;              /*!< [28] Graceful Stop Complete */
00233         uint32_t BABT : 1;             /*!< [29] Babbling Transmit Error */
00234         uint32_t BABR : 1;             /*!< [30] Babbling Receive Error */
00235         uint32_t RESERVED1 : 1;        /*!< [31]  */
00236     } B;
00237 } hw_enet_eir_t;
00238 
00239 /*!
00240  * @name Constants and macros for entire ENET_EIR register
00241  */
00242 /*@{*/
00243 #define HW_ENET_EIR_ADDR(x)      ((x) + 0x4U)
00244 
00245 #define HW_ENET_EIR(x)           (*(__IO hw_enet_eir_t *) HW_ENET_EIR_ADDR(x))
00246 #define HW_ENET_EIR_RD(x)        (ADDRESS_READ(hw_enet_eir_t, HW_ENET_EIR_ADDR(x)))
00247 #define HW_ENET_EIR_WR(x, v)     (ADDRESS_WRITE(hw_enet_eir_t, HW_ENET_EIR_ADDR(x), v))
00248 #define HW_ENET_EIR_SET(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) |  (v)))
00249 #define HW_ENET_EIR_CLR(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) & ~(v)))
00250 #define HW_ENET_EIR_TOG(x, v)    (HW_ENET_EIR_WR(x, HW_ENET_EIR_RD(x) ^  (v)))
00251 /*@}*/
00252 
00253 /*
00254  * Constants & macros for individual ENET_EIR bitfields
00255  */
00256 
00257 /*!
00258  * @name Register ENET_EIR, field TS_TIMER[15] (W1C)
00259  *
00260  * The adjustable timer reached the period event. A period event interrupt can
00261  * be generated if ATCR[PEREN] is set and the timer wraps according to the
00262  * periodic setting in the ATPER register. Set the timer period value before setting
00263  * ATCR[PEREN].
00264  */
00265 /*@{*/
00266 #define BP_ENET_EIR_TS_TIMER (15U)         /*!< Bit position for ENET_EIR_TS_TIMER. */
00267 #define BM_ENET_EIR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIR_TS_TIMER. */
00268 #define BS_ENET_EIR_TS_TIMER (1U)          /*!< Bit field size in bits for ENET_EIR_TS_TIMER. */
00269 
00270 /*! @brief Read current value of the ENET_EIR_TS_TIMER field. */
00271 #define BR_ENET_EIR_TS_TIMER(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER)))
00272 
00273 /*! @brief Format value for bitfield ENET_EIR_TS_TIMER. */
00274 #define BF_ENET_EIR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_TIMER) & BM_ENET_EIR_TS_TIMER)
00275 
00276 /*! @brief Set the TS_TIMER field to a new value. */
00277 #define BW_ENET_EIR_TS_TIMER(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_TIMER), v))
00278 /*@}*/
00279 
00280 /*!
00281  * @name Register ENET_EIR, field TS_AVAIL[16] (W1C)
00282  *
00283  * Indicates that the timestamp of the last transmitted timing frame is
00284  * available in the ATSTMP register.
00285  */
00286 /*@{*/
00287 #define BP_ENET_EIR_TS_AVAIL (16U)         /*!< Bit position for ENET_EIR_TS_AVAIL. */
00288 #define BM_ENET_EIR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIR_TS_AVAIL. */
00289 #define BS_ENET_EIR_TS_AVAIL (1U)          /*!< Bit field size in bits for ENET_EIR_TS_AVAIL. */
00290 
00291 /*! @brief Read current value of the ENET_EIR_TS_AVAIL field. */
00292 #define BR_ENET_EIR_TS_AVAIL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL)))
00293 
00294 /*! @brief Format value for bitfield ENET_EIR_TS_AVAIL. */
00295 #define BF_ENET_EIR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TS_AVAIL) & BM_ENET_EIR_TS_AVAIL)
00296 
00297 /*! @brief Set the TS_AVAIL field to a new value. */
00298 #define BW_ENET_EIR_TS_AVAIL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TS_AVAIL), v))
00299 /*@}*/
00300 
00301 /*!
00302  * @name Register ENET_EIR, field WAKEUP[17] (W1C)
00303  *
00304  * Read-only status bit to indicate that a magic packet has been detected. Will
00305  * act only if ECR[MAGICEN] is set.
00306  */
00307 /*@{*/
00308 #define BP_ENET_EIR_WAKEUP   (17U)         /*!< Bit position for ENET_EIR_WAKEUP. */
00309 #define BM_ENET_EIR_WAKEUP   (0x00020000U) /*!< Bit mask for ENET_EIR_WAKEUP. */
00310 #define BS_ENET_EIR_WAKEUP   (1U)          /*!< Bit field size in bits for ENET_EIR_WAKEUP. */
00311 
00312 /*! @brief Read current value of the ENET_EIR_WAKEUP field. */
00313 #define BR_ENET_EIR_WAKEUP(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP)))
00314 
00315 /*! @brief Format value for bitfield ENET_EIR_WAKEUP. */
00316 #define BF_ENET_EIR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_WAKEUP) & BM_ENET_EIR_WAKEUP)
00317 
00318 /*! @brief Set the WAKEUP field to a new value. */
00319 #define BW_ENET_EIR_WAKEUP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_WAKEUP), v))
00320 /*@}*/
00321 
00322 /*!
00323  * @name Register ENET_EIR, field PLR[18] (W1C)
00324  *
00325  * Indicates a frame was received with a payload length error. See Frame
00326  * Length/Type Verification: Payload Length Check for more information.
00327  */
00328 /*@{*/
00329 #define BP_ENET_EIR_PLR      (18U)         /*!< Bit position for ENET_EIR_PLR. */
00330 #define BM_ENET_EIR_PLR      (0x00040000U) /*!< Bit mask for ENET_EIR_PLR. */
00331 #define BS_ENET_EIR_PLR      (1U)          /*!< Bit field size in bits for ENET_EIR_PLR. */
00332 
00333 /*! @brief Read current value of the ENET_EIR_PLR field. */
00334 #define BR_ENET_EIR_PLR(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR)))
00335 
00336 /*! @brief Format value for bitfield ENET_EIR_PLR. */
00337 #define BF_ENET_EIR_PLR(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_PLR) & BM_ENET_EIR_PLR)
00338 
00339 /*! @brief Set the PLR field to a new value. */
00340 #define BW_ENET_EIR_PLR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_PLR), v))
00341 /*@}*/
00342 
00343 /*!
00344  * @name Register ENET_EIR, field UN[19] (W1C)
00345  *
00346  * Indicates the transmit FIFO became empty before the complete frame was
00347  * transmitted. A bad CRC is appended to the frame fragment and the remainder of the
00348  * frame is discarded.
00349  */
00350 /*@{*/
00351 #define BP_ENET_EIR_UN       (19U)         /*!< Bit position for ENET_EIR_UN. */
00352 #define BM_ENET_EIR_UN       (0x00080000U) /*!< Bit mask for ENET_EIR_UN. */
00353 #define BS_ENET_EIR_UN       (1U)          /*!< Bit field size in bits for ENET_EIR_UN. */
00354 
00355 /*! @brief Read current value of the ENET_EIR_UN field. */
00356 #define BR_ENET_EIR_UN(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN)))
00357 
00358 /*! @brief Format value for bitfield ENET_EIR_UN. */
00359 #define BF_ENET_EIR_UN(v)    ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_UN) & BM_ENET_EIR_UN)
00360 
00361 /*! @brief Set the UN field to a new value. */
00362 #define BW_ENET_EIR_UN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_UN), v))
00363 /*@}*/
00364 
00365 /*!
00366  * @name Register ENET_EIR, field RL[20] (W1C)
00367  *
00368  * Indicates a collision occurred on each of 16 successive attempts to transmit
00369  * the frame. The frame is discarded without being transmitted and transmission
00370  * of the next frame commences. This error can only occur in half-duplex mode.
00371  */
00372 /*@{*/
00373 #define BP_ENET_EIR_RL       (20U)         /*!< Bit position for ENET_EIR_RL. */
00374 #define BM_ENET_EIR_RL       (0x00100000U) /*!< Bit mask for ENET_EIR_RL. */
00375 #define BS_ENET_EIR_RL       (1U)          /*!< Bit field size in bits for ENET_EIR_RL. */
00376 
00377 /*! @brief Read current value of the ENET_EIR_RL field. */
00378 #define BR_ENET_EIR_RL(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL)))
00379 
00380 /*! @brief Format value for bitfield ENET_EIR_RL. */
00381 #define BF_ENET_EIR_RL(v)    ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RL) & BM_ENET_EIR_RL)
00382 
00383 /*! @brief Set the RL field to a new value. */
00384 #define BW_ENET_EIR_RL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RL), v))
00385 /*@}*/
00386 
00387 /*!
00388  * @name Register ENET_EIR, field LC[21] (W1C)
00389  *
00390  * Indicates a collision occurred beyond the collision window (slot time) in
00391  * half-duplex mode. The frame truncates with a bad CRC and the remainder of the
00392  * frame is discarded.
00393  */
00394 /*@{*/
00395 #define BP_ENET_EIR_LC       (21U)         /*!< Bit position for ENET_EIR_LC. */
00396 #define BM_ENET_EIR_LC       (0x00200000U) /*!< Bit mask for ENET_EIR_LC. */
00397 #define BS_ENET_EIR_LC       (1U)          /*!< Bit field size in bits for ENET_EIR_LC. */
00398 
00399 /*! @brief Read current value of the ENET_EIR_LC field. */
00400 #define BR_ENET_EIR_LC(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC)))
00401 
00402 /*! @brief Format value for bitfield ENET_EIR_LC. */
00403 #define BF_ENET_EIR_LC(v)    ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_LC) & BM_ENET_EIR_LC)
00404 
00405 /*! @brief Set the LC field to a new value. */
00406 #define BW_ENET_EIR_LC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_LC), v))
00407 /*@}*/
00408 
00409 /*!
00410  * @name Register ENET_EIR, field EBERR[22] (W1C)
00411  *
00412  * Indicates a system bus error occurred when a uDMA transaction is underway.
00413  * When this bit is set, ECR[ETHEREN] is cleared, halting frame processing by the
00414  * MAC. When this occurs, software must ensure proper actions, possibly resetting
00415  * the system, to resume normal operation.
00416  */
00417 /*@{*/
00418 #define BP_ENET_EIR_EBERR    (22U)         /*!< Bit position for ENET_EIR_EBERR. */
00419 #define BM_ENET_EIR_EBERR    (0x00400000U) /*!< Bit mask for ENET_EIR_EBERR. */
00420 #define BS_ENET_EIR_EBERR    (1U)          /*!< Bit field size in bits for ENET_EIR_EBERR. */
00421 
00422 /*! @brief Read current value of the ENET_EIR_EBERR field. */
00423 #define BR_ENET_EIR_EBERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR)))
00424 
00425 /*! @brief Format value for bitfield ENET_EIR_EBERR. */
00426 #define BF_ENET_EIR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_EBERR) & BM_ENET_EIR_EBERR)
00427 
00428 /*! @brief Set the EBERR field to a new value. */
00429 #define BW_ENET_EIR_EBERR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_EBERR), v))
00430 /*@}*/
00431 
00432 /*!
00433  * @name Register ENET_EIR, field MII[23] (W1C)
00434  *
00435  * Indicates that the MII has completed the data transfer requested.
00436  */
00437 /*@{*/
00438 #define BP_ENET_EIR_MII      (23U)         /*!< Bit position for ENET_EIR_MII. */
00439 #define BM_ENET_EIR_MII      (0x00800000U) /*!< Bit mask for ENET_EIR_MII. */
00440 #define BS_ENET_EIR_MII      (1U)          /*!< Bit field size in bits for ENET_EIR_MII. */
00441 
00442 /*! @brief Read current value of the ENET_EIR_MII field. */
00443 #define BR_ENET_EIR_MII(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII)))
00444 
00445 /*! @brief Format value for bitfield ENET_EIR_MII. */
00446 #define BF_ENET_EIR_MII(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_MII) & BM_ENET_EIR_MII)
00447 
00448 /*! @brief Set the MII field to a new value. */
00449 #define BW_ENET_EIR_MII(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_MII), v))
00450 /*@}*/
00451 
00452 /*!
00453  * @name Register ENET_EIR, field RXB[24] (W1C)
00454  *
00455  * Indicates a receive buffer descriptor is not the last in the frame has been
00456  * updated.
00457  */
00458 /*@{*/
00459 #define BP_ENET_EIR_RXB      (24U)         /*!< Bit position for ENET_EIR_RXB. */
00460 #define BM_ENET_EIR_RXB      (0x01000000U) /*!< Bit mask for ENET_EIR_RXB. */
00461 #define BS_ENET_EIR_RXB      (1U)          /*!< Bit field size in bits for ENET_EIR_RXB. */
00462 
00463 /*! @brief Read current value of the ENET_EIR_RXB field. */
00464 #define BR_ENET_EIR_RXB(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB)))
00465 
00466 /*! @brief Format value for bitfield ENET_EIR_RXB. */
00467 #define BF_ENET_EIR_RXB(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXB) & BM_ENET_EIR_RXB)
00468 
00469 /*! @brief Set the RXB field to a new value. */
00470 #define BW_ENET_EIR_RXB(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXB), v))
00471 /*@}*/
00472 
00473 /*!
00474  * @name Register ENET_EIR, field RXF[25] (W1C)
00475  *
00476  * Indicates a frame has been received and the last corresponding buffer
00477  * descriptor has been updated.
00478  */
00479 /*@{*/
00480 #define BP_ENET_EIR_RXF      (25U)         /*!< Bit position for ENET_EIR_RXF. */
00481 #define BM_ENET_EIR_RXF      (0x02000000U) /*!< Bit mask for ENET_EIR_RXF. */
00482 #define BS_ENET_EIR_RXF      (1U)          /*!< Bit field size in bits for ENET_EIR_RXF. */
00483 
00484 /*! @brief Read current value of the ENET_EIR_RXF field. */
00485 #define BR_ENET_EIR_RXF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF)))
00486 
00487 /*! @brief Format value for bitfield ENET_EIR_RXF. */
00488 #define BF_ENET_EIR_RXF(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_RXF) & BM_ENET_EIR_RXF)
00489 
00490 /*! @brief Set the RXF field to a new value. */
00491 #define BW_ENET_EIR_RXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_RXF), v))
00492 /*@}*/
00493 
00494 /*!
00495  * @name Register ENET_EIR, field TXB[26] (W1C)
00496  *
00497  * Indicates a transmit buffer descriptor has been updated.
00498  */
00499 /*@{*/
00500 #define BP_ENET_EIR_TXB      (26U)         /*!< Bit position for ENET_EIR_TXB. */
00501 #define BM_ENET_EIR_TXB      (0x04000000U) /*!< Bit mask for ENET_EIR_TXB. */
00502 #define BS_ENET_EIR_TXB      (1U)          /*!< Bit field size in bits for ENET_EIR_TXB. */
00503 
00504 /*! @brief Read current value of the ENET_EIR_TXB field. */
00505 #define BR_ENET_EIR_TXB(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB)))
00506 
00507 /*! @brief Format value for bitfield ENET_EIR_TXB. */
00508 #define BF_ENET_EIR_TXB(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXB) & BM_ENET_EIR_TXB)
00509 
00510 /*! @brief Set the TXB field to a new value. */
00511 #define BW_ENET_EIR_TXB(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXB), v))
00512 /*@}*/
00513 
00514 /*!
00515  * @name Register ENET_EIR, field TXF[27] (W1C)
00516  *
00517  * Indicates a frame has been transmitted and the last corresponding buffer
00518  * descriptor has been updated.
00519  */
00520 /*@{*/
00521 #define BP_ENET_EIR_TXF      (27U)         /*!< Bit position for ENET_EIR_TXF. */
00522 #define BM_ENET_EIR_TXF      (0x08000000U) /*!< Bit mask for ENET_EIR_TXF. */
00523 #define BS_ENET_EIR_TXF      (1U)          /*!< Bit field size in bits for ENET_EIR_TXF. */
00524 
00525 /*! @brief Read current value of the ENET_EIR_TXF field. */
00526 #define BR_ENET_EIR_TXF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF)))
00527 
00528 /*! @brief Format value for bitfield ENET_EIR_TXF. */
00529 #define BF_ENET_EIR_TXF(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_TXF) & BM_ENET_EIR_TXF)
00530 
00531 /*! @brief Set the TXF field to a new value. */
00532 #define BW_ENET_EIR_TXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_TXF), v))
00533 /*@}*/
00534 
00535 /*!
00536  * @name Register ENET_EIR, field GRA[28] (W1C)
00537  *
00538  * This interrupt is asserted after the transmitter is put into a pause state
00539  * after completion of the frame currently being transmitted. See Graceful Transmit
00540  * Stop (GTS) for conditions that lead to graceful stop. The GRA interrupt is
00541  * asserted only when the TX transitions into the stopped state. If this bit is
00542  * cleared by writing 1 and the TX is still stopped, the bit is not set again.
00543  */
00544 /*@{*/
00545 #define BP_ENET_EIR_GRA      (28U)         /*!< Bit position for ENET_EIR_GRA. */
00546 #define BM_ENET_EIR_GRA      (0x10000000U) /*!< Bit mask for ENET_EIR_GRA. */
00547 #define BS_ENET_EIR_GRA      (1U)          /*!< Bit field size in bits for ENET_EIR_GRA. */
00548 
00549 /*! @brief Read current value of the ENET_EIR_GRA field. */
00550 #define BR_ENET_EIR_GRA(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA)))
00551 
00552 /*! @brief Format value for bitfield ENET_EIR_GRA. */
00553 #define BF_ENET_EIR_GRA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_GRA) & BM_ENET_EIR_GRA)
00554 
00555 /*! @brief Set the GRA field to a new value. */
00556 #define BW_ENET_EIR_GRA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_GRA), v))
00557 /*@}*/
00558 
00559 /*!
00560  * @name Register ENET_EIR, field BABT[29] (W1C)
00561  *
00562  * Indicates the transmitted frame length exceeds RCR[MAX_FL] bytes. Usually
00563  * this condition is caused when a frame that is too long is placed into the
00564  * transmit data buffer(s). Truncation does not occur.
00565  */
00566 /*@{*/
00567 #define BP_ENET_EIR_BABT     (29U)         /*!< Bit position for ENET_EIR_BABT. */
00568 #define BM_ENET_EIR_BABT     (0x20000000U) /*!< Bit mask for ENET_EIR_BABT. */
00569 #define BS_ENET_EIR_BABT     (1U)          /*!< Bit field size in bits for ENET_EIR_BABT. */
00570 
00571 /*! @brief Read current value of the ENET_EIR_BABT field. */
00572 #define BR_ENET_EIR_BABT(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT)))
00573 
00574 /*! @brief Format value for bitfield ENET_EIR_BABT. */
00575 #define BF_ENET_EIR_BABT(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABT) & BM_ENET_EIR_BABT)
00576 
00577 /*! @brief Set the BABT field to a new value. */
00578 #define BW_ENET_EIR_BABT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABT), v))
00579 /*@}*/
00580 
00581 /*!
00582  * @name Register ENET_EIR, field BABR[30] (W1C)
00583  *
00584  * Indicates a frame was received with length in excess of RCR[MAX_FL] bytes.
00585  */
00586 /*@{*/
00587 #define BP_ENET_EIR_BABR     (30U)         /*!< Bit position for ENET_EIR_BABR. */
00588 #define BM_ENET_EIR_BABR     (0x40000000U) /*!< Bit mask for ENET_EIR_BABR. */
00589 #define BS_ENET_EIR_BABR     (1U)          /*!< Bit field size in bits for ENET_EIR_BABR. */
00590 
00591 /*! @brief Read current value of the ENET_EIR_BABR field. */
00592 #define BR_ENET_EIR_BABR(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR)))
00593 
00594 /*! @brief Format value for bitfield ENET_EIR_BABR. */
00595 #define BF_ENET_EIR_BABR(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIR_BABR) & BM_ENET_EIR_BABR)
00596 
00597 /*! @brief Set the BABR field to a new value. */
00598 #define BW_ENET_EIR_BABR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIR_ADDR(x), BP_ENET_EIR_BABR), v))
00599 /*@}*/
00600 
00601 /*******************************************************************************
00602  * HW_ENET_EIMR - Interrupt Mask Register
00603  ******************************************************************************/
00604 
00605 /*!
00606  * @brief HW_ENET_EIMR - Interrupt Mask Register (RW)
00607  *
00608  * Reset value: 0x00000000U
00609  *
00610  * EIMR controls which interrupt events are allowed to generate actual
00611  * interrupts. A hardware reset clears this register. If the corresponding bits in the EIR
00612  * and EIMR registers are set, an interrupt is generated. The interrupt signal
00613  * remains asserted until a 1 is written to the EIR field (write 1 to clear) or a
00614  * 0 is written to the EIMR field.
00615  */
00616 typedef union _hw_enet_eimr
00617 {
00618     uint32_t U;
00619     struct _hw_enet_eimr_bitfields
00620     {
00621         uint32_t RESERVED0 : 15;       /*!< [14:0]  */
00622         uint32_t TS_TIMER : 1;         /*!< [15] TS_TIMER Interrupt Mask */
00623         uint32_t TS_AVAIL : 1;         /*!< [16] TS_AVAIL Interrupt Mask */
00624         uint32_t WAKEUP : 1;           /*!< [17] WAKEUP Interrupt Mask */
00625         uint32_t PLR : 1;              /*!< [18] PLR Interrupt Mask */
00626         uint32_t UN : 1;               /*!< [19] UN Interrupt Mask */
00627         uint32_t RL : 1;               /*!< [20] RL Interrupt Mask */
00628         uint32_t LC : 1;               /*!< [21] LC Interrupt Mask */
00629         uint32_t EBERR : 1;            /*!< [22] EBERR Interrupt Mask */
00630         uint32_t MII : 1;              /*!< [23] MII Interrupt Mask */
00631         uint32_t RXB : 1;              /*!< [24] RXB Interrupt Mask */
00632         uint32_t RXF : 1;              /*!< [25] RXF Interrupt Mask */
00633         uint32_t TXB : 1;              /*!< [26] TXB Interrupt Mask */
00634         uint32_t TXF : 1;              /*!< [27] TXF Interrupt Mask */
00635         uint32_t GRA : 1;              /*!< [28] GRA Interrupt Mask */
00636         uint32_t BABT : 1;             /*!< [29] BABT Interrupt Mask */
00637         uint32_t BABR : 1;             /*!< [30] BABR Interrupt Mask */
00638         uint32_t RESERVED1 : 1;        /*!< [31]  */
00639     } B;
00640 } hw_enet_eimr_t;
00641 
00642 /*!
00643  * @name Constants and macros for entire ENET_EIMR register
00644  */
00645 /*@{*/
00646 #define HW_ENET_EIMR_ADDR(x)     ((x) + 0x8U)
00647 
00648 #define HW_ENET_EIMR(x)          (*(__IO hw_enet_eimr_t *) HW_ENET_EIMR_ADDR(x))
00649 #define HW_ENET_EIMR_RD(x)       (ADDRESS_READ(hw_enet_eimr_t, HW_ENET_EIMR_ADDR(x)))
00650 #define HW_ENET_EIMR_WR(x, v)    (ADDRESS_WRITE(hw_enet_eimr_t, HW_ENET_EIMR_ADDR(x), v))
00651 #define HW_ENET_EIMR_SET(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) |  (v)))
00652 #define HW_ENET_EIMR_CLR(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) & ~(v)))
00653 #define HW_ENET_EIMR_TOG(x, v)   (HW_ENET_EIMR_WR(x, HW_ENET_EIMR_RD(x) ^  (v)))
00654 /*@}*/
00655 
00656 /*
00657  * Constants & macros for individual ENET_EIMR bitfields
00658  */
00659 
00660 /*!
00661  * @name Register ENET_EIMR, field TS_TIMER[15] (RW)
00662  *
00663  * Corresponds to interrupt source EIR[TS_TIMER] register and determines whether
00664  * an interrupt condition can generate an interrupt. At every module clock, the
00665  * EIR samples the signal generated by the interrupting source. The corresponding
00666  * EIR TS_TIMER field reflects the state of the interrupt signal even if the
00667  * corresponding EIMR field is cleared.
00668  */
00669 /*@{*/
00670 #define BP_ENET_EIMR_TS_TIMER (15U)        /*!< Bit position for ENET_EIMR_TS_TIMER. */
00671 #define BM_ENET_EIMR_TS_TIMER (0x00008000U) /*!< Bit mask for ENET_EIMR_TS_TIMER. */
00672 #define BS_ENET_EIMR_TS_TIMER (1U)         /*!< Bit field size in bits for ENET_EIMR_TS_TIMER. */
00673 
00674 /*! @brief Read current value of the ENET_EIMR_TS_TIMER field. */
00675 #define BR_ENET_EIMR_TS_TIMER(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER)))
00676 
00677 /*! @brief Format value for bitfield ENET_EIMR_TS_TIMER. */
00678 #define BF_ENET_EIMR_TS_TIMER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_TIMER) & BM_ENET_EIMR_TS_TIMER)
00679 
00680 /*! @brief Set the TS_TIMER field to a new value. */
00681 #define BW_ENET_EIMR_TS_TIMER(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_TIMER), v))
00682 /*@}*/
00683 
00684 /*!
00685  * @name Register ENET_EIMR, field TS_AVAIL[16] (RW)
00686  *
00687  * Corresponds to interrupt source EIR[TS_AVAIL] register and determines whether
00688  * an interrupt condition can generate an interrupt. At every module clock, the
00689  * EIR samples the signal generated by the interrupting source. The corresponding
00690  * EIR TS_AVAIL field reflects the state of the interrupt signal even if the
00691  * corresponding EIMR field is cleared.
00692  */
00693 /*@{*/
00694 #define BP_ENET_EIMR_TS_AVAIL (16U)        /*!< Bit position for ENET_EIMR_TS_AVAIL. */
00695 #define BM_ENET_EIMR_TS_AVAIL (0x00010000U) /*!< Bit mask for ENET_EIMR_TS_AVAIL. */
00696 #define BS_ENET_EIMR_TS_AVAIL (1U)         /*!< Bit field size in bits for ENET_EIMR_TS_AVAIL. */
00697 
00698 /*! @brief Read current value of the ENET_EIMR_TS_AVAIL field. */
00699 #define BR_ENET_EIMR_TS_AVAIL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL)))
00700 
00701 /*! @brief Format value for bitfield ENET_EIMR_TS_AVAIL. */
00702 #define BF_ENET_EIMR_TS_AVAIL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TS_AVAIL) & BM_ENET_EIMR_TS_AVAIL)
00703 
00704 /*! @brief Set the TS_AVAIL field to a new value. */
00705 #define BW_ENET_EIMR_TS_AVAIL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TS_AVAIL), v))
00706 /*@}*/
00707 
00708 /*!
00709  * @name Register ENET_EIMR, field WAKEUP[17] (RW)
00710  *
00711  * Corresponds to interrupt source EIR[WAKEUP] register and determines whether
00712  * an interrupt condition can generate an interrupt. At every module clock, the
00713  * EIR samples the signal generated by the interrupting source. The corresponding
00714  * EIR WAKEUP field reflects the state of the interrupt signal even if the
00715  * corresponding EIMR field is cleared.
00716  */
00717 /*@{*/
00718 #define BP_ENET_EIMR_WAKEUP  (17U)         /*!< Bit position for ENET_EIMR_WAKEUP. */
00719 #define BM_ENET_EIMR_WAKEUP  (0x00020000U) /*!< Bit mask for ENET_EIMR_WAKEUP. */
00720 #define BS_ENET_EIMR_WAKEUP  (1U)          /*!< Bit field size in bits for ENET_EIMR_WAKEUP. */
00721 
00722 /*! @brief Read current value of the ENET_EIMR_WAKEUP field. */
00723 #define BR_ENET_EIMR_WAKEUP(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP)))
00724 
00725 /*! @brief Format value for bitfield ENET_EIMR_WAKEUP. */
00726 #define BF_ENET_EIMR_WAKEUP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_WAKEUP) & BM_ENET_EIMR_WAKEUP)
00727 
00728 /*! @brief Set the WAKEUP field to a new value. */
00729 #define BW_ENET_EIMR_WAKEUP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_WAKEUP), v))
00730 /*@}*/
00731 
00732 /*!
00733  * @name Register ENET_EIMR, field PLR[18] (RW)
00734  *
00735  * Corresponds to interrupt source EIR[PLR] and determines whether an interrupt
00736  * condition can generate an interrupt. At every module clock, the EIR samples
00737  * the signal generated by the interrupting source. The corresponding EIR PLR field
00738  * reflects the state of the interrupt signal even if the corresponding EIMR
00739  * field is cleared.
00740  */
00741 /*@{*/
00742 #define BP_ENET_EIMR_PLR     (18U)         /*!< Bit position for ENET_EIMR_PLR. */
00743 #define BM_ENET_EIMR_PLR     (0x00040000U) /*!< Bit mask for ENET_EIMR_PLR. */
00744 #define BS_ENET_EIMR_PLR     (1U)          /*!< Bit field size in bits for ENET_EIMR_PLR. */
00745 
00746 /*! @brief Read current value of the ENET_EIMR_PLR field. */
00747 #define BR_ENET_EIMR_PLR(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR)))
00748 
00749 /*! @brief Format value for bitfield ENET_EIMR_PLR. */
00750 #define BF_ENET_EIMR_PLR(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_PLR) & BM_ENET_EIMR_PLR)
00751 
00752 /*! @brief Set the PLR field to a new value. */
00753 #define BW_ENET_EIMR_PLR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_PLR), v))
00754 /*@}*/
00755 
00756 /*!
00757  * @name Register ENET_EIMR, field UN[19] (RW)
00758  *
00759  * Corresponds to interrupt source EIR[UN] and determines whether an interrupt
00760  * condition can generate an interrupt. At every module clock, the EIR samples the
00761  * signal generated by the interrupting source. The corresponding EIR UN field
00762  * reflects the state of the interrupt signal even if the corresponding EIMR field
00763  * is cleared.
00764  */
00765 /*@{*/
00766 #define BP_ENET_EIMR_UN      (19U)         /*!< Bit position for ENET_EIMR_UN. */
00767 #define BM_ENET_EIMR_UN      (0x00080000U) /*!< Bit mask for ENET_EIMR_UN. */
00768 #define BS_ENET_EIMR_UN      (1U)          /*!< Bit field size in bits for ENET_EIMR_UN. */
00769 
00770 /*! @brief Read current value of the ENET_EIMR_UN field. */
00771 #define BR_ENET_EIMR_UN(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN)))
00772 
00773 /*! @brief Format value for bitfield ENET_EIMR_UN. */
00774 #define BF_ENET_EIMR_UN(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_UN) & BM_ENET_EIMR_UN)
00775 
00776 /*! @brief Set the UN field to a new value. */
00777 #define BW_ENET_EIMR_UN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_UN), v))
00778 /*@}*/
00779 
00780 /*!
00781  * @name Register ENET_EIMR, field RL[20] (RW)
00782  *
00783  * Corresponds to interrupt source EIR[RL] and determines whether an interrupt
00784  * condition can generate an interrupt. At every module clock, the EIR samples the
00785  * signal generated by the interrupting source. The corresponding EIR RL field
00786  * reflects the state of the interrupt signal even if the corresponding EIMR field
00787  * is cleared.
00788  */
00789 /*@{*/
00790 #define BP_ENET_EIMR_RL      (20U)         /*!< Bit position for ENET_EIMR_RL. */
00791 #define BM_ENET_EIMR_RL      (0x00100000U) /*!< Bit mask for ENET_EIMR_RL. */
00792 #define BS_ENET_EIMR_RL      (1U)          /*!< Bit field size in bits for ENET_EIMR_RL. */
00793 
00794 /*! @brief Read current value of the ENET_EIMR_RL field. */
00795 #define BR_ENET_EIMR_RL(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL)))
00796 
00797 /*! @brief Format value for bitfield ENET_EIMR_RL. */
00798 #define BF_ENET_EIMR_RL(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RL) & BM_ENET_EIMR_RL)
00799 
00800 /*! @brief Set the RL field to a new value. */
00801 #define BW_ENET_EIMR_RL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RL), v))
00802 /*@}*/
00803 
00804 /*!
00805  * @name Register ENET_EIMR, field LC[21] (RW)
00806  *
00807  * Corresponds to interrupt source EIR[LC] and determines whether an interrupt
00808  * condition can generate an interrupt. At every module clock, the EIR samples the
00809  * signal generated by the interrupting source. The corresponding EIR LC field
00810  * reflects the state of the interrupt signal even if the corresponding EIMR field
00811  * is cleared.
00812  */
00813 /*@{*/
00814 #define BP_ENET_EIMR_LC      (21U)         /*!< Bit position for ENET_EIMR_LC. */
00815 #define BM_ENET_EIMR_LC      (0x00200000U) /*!< Bit mask for ENET_EIMR_LC. */
00816 #define BS_ENET_EIMR_LC      (1U)          /*!< Bit field size in bits for ENET_EIMR_LC. */
00817 
00818 /*! @brief Read current value of the ENET_EIMR_LC field. */
00819 #define BR_ENET_EIMR_LC(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC)))
00820 
00821 /*! @brief Format value for bitfield ENET_EIMR_LC. */
00822 #define BF_ENET_EIMR_LC(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_LC) & BM_ENET_EIMR_LC)
00823 
00824 /*! @brief Set the LC field to a new value. */
00825 #define BW_ENET_EIMR_LC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_LC), v))
00826 /*@}*/
00827 
00828 /*!
00829  * @name Register ENET_EIMR, field EBERR[22] (RW)
00830  *
00831  * Corresponds to interrupt source EIR[EBERR] and determines whether an
00832  * interrupt condition can generate an interrupt. At every module clock, the EIR samples
00833  * the signal generated by the interrupting source. The corresponding EIR EBERR
00834  * field reflects the state of the interrupt signal even if the corresponding EIMR
00835  * field is cleared.
00836  */
00837 /*@{*/
00838 #define BP_ENET_EIMR_EBERR   (22U)         /*!< Bit position for ENET_EIMR_EBERR. */
00839 #define BM_ENET_EIMR_EBERR   (0x00400000U) /*!< Bit mask for ENET_EIMR_EBERR. */
00840 #define BS_ENET_EIMR_EBERR   (1U)          /*!< Bit field size in bits for ENET_EIMR_EBERR. */
00841 
00842 /*! @brief Read current value of the ENET_EIMR_EBERR field. */
00843 #define BR_ENET_EIMR_EBERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR)))
00844 
00845 /*! @brief Format value for bitfield ENET_EIMR_EBERR. */
00846 #define BF_ENET_EIMR_EBERR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_EBERR) & BM_ENET_EIMR_EBERR)
00847 
00848 /*! @brief Set the EBERR field to a new value. */
00849 #define BW_ENET_EIMR_EBERR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_EBERR), v))
00850 /*@}*/
00851 
00852 /*!
00853  * @name Register ENET_EIMR, field MII[23] (RW)
00854  *
00855  * Corresponds to interrupt source EIR[MII] and determines whether an interrupt
00856  * condition can generate an interrupt. At every module clock, the EIR samples
00857  * the signal generated by the interrupting source. The corresponding EIR MII field
00858  * reflects the state of the interrupt signal even if the corresponding EIMR
00859  * field is cleared.
00860  */
00861 /*@{*/
00862 #define BP_ENET_EIMR_MII     (23U)         /*!< Bit position for ENET_EIMR_MII. */
00863 #define BM_ENET_EIMR_MII     (0x00800000U) /*!< Bit mask for ENET_EIMR_MII. */
00864 #define BS_ENET_EIMR_MII     (1U)          /*!< Bit field size in bits for ENET_EIMR_MII. */
00865 
00866 /*! @brief Read current value of the ENET_EIMR_MII field. */
00867 #define BR_ENET_EIMR_MII(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII)))
00868 
00869 /*! @brief Format value for bitfield ENET_EIMR_MII. */
00870 #define BF_ENET_EIMR_MII(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_MII) & BM_ENET_EIMR_MII)
00871 
00872 /*! @brief Set the MII field to a new value. */
00873 #define BW_ENET_EIMR_MII(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_MII), v))
00874 /*@}*/
00875 
00876 /*!
00877  * @name Register ENET_EIMR, field RXB[24] (RW)
00878  *
00879  * Corresponds to interrupt source EIR[RXB] and determines whether an interrupt
00880  * condition can generate an interrupt. At every module clock, the EIR samples
00881  * the signal generated by the interrupting source. The corresponding EIR RXB field
00882  * reflects the state of the interrupt signal even if the corresponding EIMR
00883  * field is cleared.
00884  */
00885 /*@{*/
00886 #define BP_ENET_EIMR_RXB     (24U)         /*!< Bit position for ENET_EIMR_RXB. */
00887 #define BM_ENET_EIMR_RXB     (0x01000000U) /*!< Bit mask for ENET_EIMR_RXB. */
00888 #define BS_ENET_EIMR_RXB     (1U)          /*!< Bit field size in bits for ENET_EIMR_RXB. */
00889 
00890 /*! @brief Read current value of the ENET_EIMR_RXB field. */
00891 #define BR_ENET_EIMR_RXB(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB)))
00892 
00893 /*! @brief Format value for bitfield ENET_EIMR_RXB. */
00894 #define BF_ENET_EIMR_RXB(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXB) & BM_ENET_EIMR_RXB)
00895 
00896 /*! @brief Set the RXB field to a new value. */
00897 #define BW_ENET_EIMR_RXB(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXB), v))
00898 /*@}*/
00899 
00900 /*!
00901  * @name Register ENET_EIMR, field RXF[25] (RW)
00902  *
00903  * Corresponds to interrupt source EIR[RXF] and determines whether an interrupt
00904  * condition can generate an interrupt. At every module clock, the EIR samples
00905  * the signal generated by the interrupting source. The corresponding EIR RXF field
00906  * reflects the state of the interrupt signal even if the corresponding EIMR
00907  * field is cleared.
00908  */
00909 /*@{*/
00910 #define BP_ENET_EIMR_RXF     (25U)         /*!< Bit position for ENET_EIMR_RXF. */
00911 #define BM_ENET_EIMR_RXF     (0x02000000U) /*!< Bit mask for ENET_EIMR_RXF. */
00912 #define BS_ENET_EIMR_RXF     (1U)          /*!< Bit field size in bits for ENET_EIMR_RXF. */
00913 
00914 /*! @brief Read current value of the ENET_EIMR_RXF field. */
00915 #define BR_ENET_EIMR_RXF(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF)))
00916 
00917 /*! @brief Format value for bitfield ENET_EIMR_RXF. */
00918 #define BF_ENET_EIMR_RXF(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_RXF) & BM_ENET_EIMR_RXF)
00919 
00920 /*! @brief Set the RXF field to a new value. */
00921 #define BW_ENET_EIMR_RXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_RXF), v))
00922 /*@}*/
00923 
00924 /*!
00925  * @name Register ENET_EIMR, field TXB[26] (RW)
00926  *
00927  * Corresponds to interrupt source EIR[TXB] and determines whether an interrupt
00928  * condition can generate an interrupt. At every module clock, the EIR samples
00929  * the signal generated by the interrupting source. The corresponding EIR TXF field
00930  * reflects the state of the interrupt signal even if the corresponding EIMR
00931  * field is cleared.
00932  *
00933  * Values:
00934  * - 0 - The corresponding interrupt source is masked.
00935  * - 1 - The corresponding interrupt source is not masked.
00936  */
00937 /*@{*/
00938 #define BP_ENET_EIMR_TXB     (26U)         /*!< Bit position for ENET_EIMR_TXB. */
00939 #define BM_ENET_EIMR_TXB     (0x04000000U) /*!< Bit mask for ENET_EIMR_TXB. */
00940 #define BS_ENET_EIMR_TXB     (1U)          /*!< Bit field size in bits for ENET_EIMR_TXB. */
00941 
00942 /*! @brief Read current value of the ENET_EIMR_TXB field. */
00943 #define BR_ENET_EIMR_TXB(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB)))
00944 
00945 /*! @brief Format value for bitfield ENET_EIMR_TXB. */
00946 #define BF_ENET_EIMR_TXB(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXB) & BM_ENET_EIMR_TXB)
00947 
00948 /*! @brief Set the TXB field to a new value. */
00949 #define BW_ENET_EIMR_TXB(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXB), v))
00950 /*@}*/
00951 
00952 /*!
00953  * @name Register ENET_EIMR, field TXF[27] (RW)
00954  *
00955  * Corresponds to interrupt source EIR[TXF] and determines whether an interrupt
00956  * condition can generate an interrupt. At every module clock, the EIR samples
00957  * the signal generated by the interrupting source. The corresponding EIR TXF field
00958  * reflects the state of the interrupt signal even if the corresponding EIMR
00959  * field is cleared.
00960  *
00961  * Values:
00962  * - 0 - The corresponding interrupt source is masked.
00963  * - 1 - The corresponding interrupt source is not masked.
00964  */
00965 /*@{*/
00966 #define BP_ENET_EIMR_TXF     (27U)         /*!< Bit position for ENET_EIMR_TXF. */
00967 #define BM_ENET_EIMR_TXF     (0x08000000U) /*!< Bit mask for ENET_EIMR_TXF. */
00968 #define BS_ENET_EIMR_TXF     (1U)          /*!< Bit field size in bits for ENET_EIMR_TXF. */
00969 
00970 /*! @brief Read current value of the ENET_EIMR_TXF field. */
00971 #define BR_ENET_EIMR_TXF(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF)))
00972 
00973 /*! @brief Format value for bitfield ENET_EIMR_TXF. */
00974 #define BF_ENET_EIMR_TXF(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_TXF) & BM_ENET_EIMR_TXF)
00975 
00976 /*! @brief Set the TXF field to a new value. */
00977 #define BW_ENET_EIMR_TXF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_TXF), v))
00978 /*@}*/
00979 
00980 /*!
00981  * @name Register ENET_EIMR, field GRA[28] (RW)
00982  *
00983  * Corresponds to interrupt source EIR[GRA] and determines whether an interrupt
00984  * condition can generate an interrupt. At every module clock, the EIR samples
00985  * the signal generated by the interrupting source. The corresponding EIR GRA field
00986  * reflects the state of the interrupt signal even if the corresponding EIMR
00987  * field is cleared.
00988  *
00989  * Values:
00990  * - 0 - The corresponding interrupt source is masked.
00991  * - 1 - The corresponding interrupt source is not masked.
00992  */
00993 /*@{*/
00994 #define BP_ENET_EIMR_GRA     (28U)         /*!< Bit position for ENET_EIMR_GRA. */
00995 #define BM_ENET_EIMR_GRA     (0x10000000U) /*!< Bit mask for ENET_EIMR_GRA. */
00996 #define BS_ENET_EIMR_GRA     (1U)          /*!< Bit field size in bits for ENET_EIMR_GRA. */
00997 
00998 /*! @brief Read current value of the ENET_EIMR_GRA field. */
00999 #define BR_ENET_EIMR_GRA(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA)))
01000 
01001 /*! @brief Format value for bitfield ENET_EIMR_GRA. */
01002 #define BF_ENET_EIMR_GRA(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_GRA) & BM_ENET_EIMR_GRA)
01003 
01004 /*! @brief Set the GRA field to a new value. */
01005 #define BW_ENET_EIMR_GRA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_GRA), v))
01006 /*@}*/
01007 
01008 /*!
01009  * @name Register ENET_EIMR, field BABT[29] (RW)
01010  *
01011  * Corresponds to interrupt source EIR[BABT] and determines whether an interrupt
01012  * condition can generate an interrupt. At every module clock, the EIR samples
01013  * the signal generated by the interrupting source. The corresponding EIR BABT
01014  * field reflects the state of the interrupt signal even if the corresponding EIMR
01015  * field is cleared.
01016  *
01017  * Values:
01018  * - 0 - The corresponding interrupt source is masked.
01019  * - 1 - The corresponding interrupt source is not masked.
01020  */
01021 /*@{*/
01022 #define BP_ENET_EIMR_BABT    (29U)         /*!< Bit position for ENET_EIMR_BABT. */
01023 #define BM_ENET_EIMR_BABT    (0x20000000U) /*!< Bit mask for ENET_EIMR_BABT. */
01024 #define BS_ENET_EIMR_BABT    (1U)          /*!< Bit field size in bits for ENET_EIMR_BABT. */
01025 
01026 /*! @brief Read current value of the ENET_EIMR_BABT field. */
01027 #define BR_ENET_EIMR_BABT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT)))
01028 
01029 /*! @brief Format value for bitfield ENET_EIMR_BABT. */
01030 #define BF_ENET_EIMR_BABT(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABT) & BM_ENET_EIMR_BABT)
01031 
01032 /*! @brief Set the BABT field to a new value. */
01033 #define BW_ENET_EIMR_BABT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABT), v))
01034 /*@}*/
01035 
01036 /*!
01037  * @name Register ENET_EIMR, field BABR[30] (RW)
01038  *
01039  * Corresponds to interrupt source EIR[BABR] and determines whether an interrupt
01040  * condition can generate an interrupt. At every module clock, the EIR samples
01041  * the signal generated by the interrupting source. The corresponding EIR BABR
01042  * field reflects the state of the interrupt signal even if the corresponding EIMR
01043  * field is cleared.
01044  *
01045  * Values:
01046  * - 0 - The corresponding interrupt source is masked.
01047  * - 1 - The corresponding interrupt source is not masked.
01048  */
01049 /*@{*/
01050 #define BP_ENET_EIMR_BABR    (30U)         /*!< Bit position for ENET_EIMR_BABR. */
01051 #define BM_ENET_EIMR_BABR    (0x40000000U) /*!< Bit mask for ENET_EIMR_BABR. */
01052 #define BS_ENET_EIMR_BABR    (1U)          /*!< Bit field size in bits for ENET_EIMR_BABR. */
01053 
01054 /*! @brief Read current value of the ENET_EIMR_BABR field. */
01055 #define BR_ENET_EIMR_BABR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR)))
01056 
01057 /*! @brief Format value for bitfield ENET_EIMR_BABR. */
01058 #define BF_ENET_EIMR_BABR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_EIMR_BABR) & BM_ENET_EIMR_BABR)
01059 
01060 /*! @brief Set the BABR field to a new value. */
01061 #define BW_ENET_EIMR_BABR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_EIMR_ADDR(x), BP_ENET_EIMR_BABR), v))
01062 /*@}*/
01063 
01064 /*******************************************************************************
01065  * HW_ENET_RDAR - Receive Descriptor Active Register
01066  ******************************************************************************/
01067 
01068 /*!
01069  * @brief HW_ENET_RDAR - Receive Descriptor Active Register (RW)
01070  *
01071  * Reset value: 0x00000000U
01072  *
01073  * RDAR is a command register, written by the user, to indicate that the receive
01074  * descriptor ring has been updated, that is, that the driver produced empty
01075  * receive buffers with the empty bit set.
01076  */
01077 typedef union _hw_enet_rdar
01078 {
01079     uint32_t U;
01080     struct _hw_enet_rdar_bitfields
01081     {
01082         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
01083         uint32_t RDAR : 1;             /*!< [24] Receive Descriptor Active */
01084         uint32_t RESERVED1 : 7;        /*!< [31:25]  */
01085     } B;
01086 } hw_enet_rdar_t;
01087 
01088 /*!
01089  * @name Constants and macros for entire ENET_RDAR register
01090  */
01091 /*@{*/
01092 #define HW_ENET_RDAR_ADDR(x)     ((x) + 0x10U)
01093 
01094 #define HW_ENET_RDAR(x)          (*(__IO hw_enet_rdar_t *) HW_ENET_RDAR_ADDR(x))
01095 #define HW_ENET_RDAR_RD(x)       (ADDRESS_READ(hw_enet_rdar_t, HW_ENET_RDAR_ADDR(x)))
01096 #define HW_ENET_RDAR_WR(x, v)    (ADDRESS_WRITE(hw_enet_rdar_t, HW_ENET_RDAR_ADDR(x), v))
01097 #define HW_ENET_RDAR_SET(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) |  (v)))
01098 #define HW_ENET_RDAR_CLR(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) & ~(v)))
01099 #define HW_ENET_RDAR_TOG(x, v)   (HW_ENET_RDAR_WR(x, HW_ENET_RDAR_RD(x) ^  (v)))
01100 /*@}*/
01101 
01102 /*
01103  * Constants & macros for individual ENET_RDAR bitfields
01104  */
01105 
01106 /*!
01107  * @name Register ENET_RDAR, field RDAR[24] (RW)
01108  *
01109  * Always set to 1 when this register is written, regardless of the value
01110  * written. This field is cleared by the MAC device when no additional empty
01111  * descriptors remain in the receive ring. It is also cleared when ECR[ETHEREN] transitions
01112  * from set to cleared or when ECR[RESET] is set.
01113  */
01114 /*@{*/
01115 #define BP_ENET_RDAR_RDAR    (24U)         /*!< Bit position for ENET_RDAR_RDAR. */
01116 #define BM_ENET_RDAR_RDAR    (0x01000000U) /*!< Bit mask for ENET_RDAR_RDAR. */
01117 #define BS_ENET_RDAR_RDAR    (1U)          /*!< Bit field size in bits for ENET_RDAR_RDAR. */
01118 
01119 /*! @brief Read current value of the ENET_RDAR_RDAR field. */
01120 #define BR_ENET_RDAR_RDAR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR)))
01121 
01122 /*! @brief Format value for bitfield ENET_RDAR_RDAR. */
01123 #define BF_ENET_RDAR_RDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDAR_RDAR) & BM_ENET_RDAR_RDAR)
01124 
01125 /*! @brief Set the RDAR field to a new value. */
01126 #define BW_ENET_RDAR_RDAR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RDAR_ADDR(x), BP_ENET_RDAR_RDAR), v))
01127 /*@}*/
01128 
01129 /*******************************************************************************
01130  * HW_ENET_TDAR - Transmit Descriptor Active Register
01131  ******************************************************************************/
01132 
01133 /*!
01134  * @brief HW_ENET_TDAR - Transmit Descriptor Active Register (RW)
01135  *
01136  * Reset value: 0x00000000U
01137  *
01138  * The TDAR is a command register that the user writes to indicate that the
01139  * transmit descriptor ring has been updated, that is, that transmit buffers have
01140  * been produced by the driver with the ready bit set in the buffer descriptor. The
01141  * TDAR register is cleared at reset, when ECR[ETHEREN] transitions from set to
01142  * cleared, or when ECR[RESET] is set.
01143  */
01144 typedef union _hw_enet_tdar
01145 {
01146     uint32_t U;
01147     struct _hw_enet_tdar_bitfields
01148     {
01149         uint32_t RESERVED0 : 24;       /*!< [23:0]  */
01150         uint32_t TDAR : 1;             /*!< [24] Transmit Descriptor Active */
01151         uint32_t RESERVED1 : 7;        /*!< [31:25]  */
01152     } B;
01153 } hw_enet_tdar_t;
01154 
01155 /*!
01156  * @name Constants and macros for entire ENET_TDAR register
01157  */
01158 /*@{*/
01159 #define HW_ENET_TDAR_ADDR(x)     ((x) + 0x14U)
01160 
01161 #define HW_ENET_TDAR(x)          (*(__IO hw_enet_tdar_t *) HW_ENET_TDAR_ADDR(x))
01162 #define HW_ENET_TDAR_RD(x)       (ADDRESS_READ(hw_enet_tdar_t, HW_ENET_TDAR_ADDR(x)))
01163 #define HW_ENET_TDAR_WR(x, v)    (ADDRESS_WRITE(hw_enet_tdar_t, HW_ENET_TDAR_ADDR(x), v))
01164 #define HW_ENET_TDAR_SET(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) |  (v)))
01165 #define HW_ENET_TDAR_CLR(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) & ~(v)))
01166 #define HW_ENET_TDAR_TOG(x, v)   (HW_ENET_TDAR_WR(x, HW_ENET_TDAR_RD(x) ^  (v)))
01167 /*@}*/
01168 
01169 /*
01170  * Constants & macros for individual ENET_TDAR bitfields
01171  */
01172 
01173 /*!
01174  * @name Register ENET_TDAR, field TDAR[24] (RW)
01175  *
01176  * Always set to 1 when this register is written, regardless of the value
01177  * written. This bit is cleared by the MAC device when no additional ready descriptors
01178  * remain in the transmit ring. Also cleared when ECR[ETHEREN] transitions from
01179  * set to cleared or when ECR[RESET] is set.
01180  */
01181 /*@{*/
01182 #define BP_ENET_TDAR_TDAR    (24U)         /*!< Bit position for ENET_TDAR_TDAR. */
01183 #define BM_ENET_TDAR_TDAR    (0x01000000U) /*!< Bit mask for ENET_TDAR_TDAR. */
01184 #define BS_ENET_TDAR_TDAR    (1U)          /*!< Bit field size in bits for ENET_TDAR_TDAR. */
01185 
01186 /*! @brief Read current value of the ENET_TDAR_TDAR field. */
01187 #define BR_ENET_TDAR_TDAR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR)))
01188 
01189 /*! @brief Format value for bitfield ENET_TDAR_TDAR. */
01190 #define BF_ENET_TDAR_TDAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDAR_TDAR) & BM_ENET_TDAR_TDAR)
01191 
01192 /*! @brief Set the TDAR field to a new value. */
01193 #define BW_ENET_TDAR_TDAR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TDAR_ADDR(x), BP_ENET_TDAR_TDAR), v))
01194 /*@}*/
01195 
01196 /*******************************************************************************
01197  * HW_ENET_ECR - Ethernet Control Register
01198  ******************************************************************************/
01199 
01200 /*!
01201  * @brief HW_ENET_ECR - Ethernet Control Register (RW)
01202  *
01203  * Reset value: 0xF0000000U
01204  *
01205  * ECR is a read/write user register, though hardware may also alter fields in
01206  * this register. It controls many of the high level features of the Ethernet MAC,
01207  * including legacy FEC support through the EN1588 field.
01208  */
01209 typedef union _hw_enet_ecr
01210 {
01211     uint32_t U;
01212     struct _hw_enet_ecr_bitfields
01213     {
01214         uint32_t RESET : 1;            /*!< [0] Ethernet MAC Reset */
01215         uint32_t ETHEREN : 1;          /*!< [1] Ethernet Enable */
01216         uint32_t MAGICEN : 1;          /*!< [2] Magic Packet Detection Enable */
01217         uint32_t SLEEP : 1;            /*!< [3] Sleep Mode Enable */
01218         uint32_t EN1588 : 1;           /*!< [4] EN1588 Enable */
01219         uint32_t RESERVED0 : 1;        /*!< [5]  */
01220         uint32_t DBGEN : 1;            /*!< [6] Debug Enable */
01221         uint32_t STOPEN : 1;           /*!< [7] STOPEN Signal Control */
01222         uint32_t DBSWP : 1;            /*!< [8] Descriptor Byte Swapping Enable */
01223         uint32_t RESERVED1 : 23;       /*!< [31:9]  */
01224     } B;
01225 } hw_enet_ecr_t;
01226 
01227 /*!
01228  * @name Constants and macros for entire ENET_ECR register
01229  */
01230 /*@{*/
01231 #define HW_ENET_ECR_ADDR(x)      ((x) + 0x24U)
01232 
01233 #define HW_ENET_ECR(x)           (*(__IO hw_enet_ecr_t *) HW_ENET_ECR_ADDR(x))
01234 #define HW_ENET_ECR_RD(x)        (ADDRESS_READ(hw_enet_ecr_t, HW_ENET_ECR_ADDR(x)))
01235 #define HW_ENET_ECR_WR(x, v)     (ADDRESS_WRITE(hw_enet_ecr_t, HW_ENET_ECR_ADDR(x), v))
01236 #define HW_ENET_ECR_SET(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) |  (v)))
01237 #define HW_ENET_ECR_CLR(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) & ~(v)))
01238 #define HW_ENET_ECR_TOG(x, v)    (HW_ENET_ECR_WR(x, HW_ENET_ECR_RD(x) ^  (v)))
01239 /*@}*/
01240 
01241 /*
01242  * Constants & macros for individual ENET_ECR bitfields
01243  */
01244 
01245 /*!
01246  * @name Register ENET_ECR, field RESET[0] (RW)
01247  *
01248  * When this field is set, it clears the ETHEREN field.
01249  */
01250 /*@{*/
01251 #define BP_ENET_ECR_RESET    (0U)          /*!< Bit position for ENET_ECR_RESET. */
01252 #define BM_ENET_ECR_RESET    (0x00000001U) /*!< Bit mask for ENET_ECR_RESET. */
01253 #define BS_ENET_ECR_RESET    (1U)          /*!< Bit field size in bits for ENET_ECR_RESET. */
01254 
01255 /*! @brief Read current value of the ENET_ECR_RESET field. */
01256 #define BR_ENET_ECR_RESET(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET)))
01257 
01258 /*! @brief Format value for bitfield ENET_ECR_RESET. */
01259 #define BF_ENET_ECR_RESET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_RESET) & BM_ENET_ECR_RESET)
01260 
01261 /*! @brief Set the RESET field to a new value. */
01262 #define BW_ENET_ECR_RESET(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_RESET), v))
01263 /*@}*/
01264 
01265 /*!
01266  * @name Register ENET_ECR, field ETHEREN[1] (RW)
01267  *
01268  * Enables/disables the Ethernet MAC. When the MAC is disabled, the buffer
01269  * descriptors for an aborted transmit frame are not updated. The uDMA, buffer
01270  * descriptor, and FIFO control logic are reset, including the buffer descriptor and
01271  * FIFO pointers. Hardware clears this field under the following conditions: RESET
01272  * is set by software An error condition causes the EBERR field to set. ETHEREN
01273  * must be set at the very last step during ENET
01274  * configuration/setup/initialization, only after all other ENET-related registers have been configured. If ETHEREN
01275  * is cleared to 0 by software then then next time ETHEREN is set, the EIR
01276  * interrupts must cleared to 0 due to previous pending interrupts.
01277  *
01278  * Values:
01279  * - 0 - Reception immediately stops and transmission stops after a bad CRC is
01280  *     appended to any currently transmitted frame.
01281  * - 1 - MAC is enabled, and reception and transmission are possible.
01282  */
01283 /*@{*/
01284 #define BP_ENET_ECR_ETHEREN  (1U)          /*!< Bit position for ENET_ECR_ETHEREN. */
01285 #define BM_ENET_ECR_ETHEREN  (0x00000002U) /*!< Bit mask for ENET_ECR_ETHEREN. */
01286 #define BS_ENET_ECR_ETHEREN  (1U)          /*!< Bit field size in bits for ENET_ECR_ETHEREN. */
01287 
01288 /*! @brief Read current value of the ENET_ECR_ETHEREN field. */
01289 #define BR_ENET_ECR_ETHEREN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN)))
01290 
01291 /*! @brief Format value for bitfield ENET_ECR_ETHEREN. */
01292 #define BF_ENET_ECR_ETHEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_ETHEREN) & BM_ENET_ECR_ETHEREN)
01293 
01294 /*! @brief Set the ETHEREN field to a new value. */
01295 #define BW_ENET_ECR_ETHEREN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_ETHEREN), v))
01296 /*@}*/
01297 
01298 /*!
01299  * @name Register ENET_ECR, field MAGICEN[2] (RW)
01300  *
01301  * Enables/disables magic packet detection. MAGICEN is relevant only if the
01302  * SLEEP field is set. If MAGICEN is set, changing the SLEEP field enables/disables
01303  * sleep mode and magic packet detection.
01304  *
01305  * Values:
01306  * - 0 - Magic detection logic disabled.
01307  * - 1 - The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame
01308  *     is detected.
01309  */
01310 /*@{*/
01311 #define BP_ENET_ECR_MAGICEN  (2U)          /*!< Bit position for ENET_ECR_MAGICEN. */
01312 #define BM_ENET_ECR_MAGICEN  (0x00000004U) /*!< Bit mask for ENET_ECR_MAGICEN. */
01313 #define BS_ENET_ECR_MAGICEN  (1U)          /*!< Bit field size in bits for ENET_ECR_MAGICEN. */
01314 
01315 /*! @brief Read current value of the ENET_ECR_MAGICEN field. */
01316 #define BR_ENET_ECR_MAGICEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN)))
01317 
01318 /*! @brief Format value for bitfield ENET_ECR_MAGICEN. */
01319 #define BF_ENET_ECR_MAGICEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_MAGICEN) & BM_ENET_ECR_MAGICEN)
01320 
01321 /*! @brief Set the MAGICEN field to a new value. */
01322 #define BW_ENET_ECR_MAGICEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_MAGICEN), v))
01323 /*@}*/
01324 
01325 /*!
01326  * @name Register ENET_ECR, field SLEEP[3] (RW)
01327  *
01328  * Values:
01329  * - 0 - Normal operating mode.
01330  * - 1 - Sleep mode.
01331  */
01332 /*@{*/
01333 #define BP_ENET_ECR_SLEEP    (3U)          /*!< Bit position for ENET_ECR_SLEEP. */
01334 #define BM_ENET_ECR_SLEEP    (0x00000008U) /*!< Bit mask for ENET_ECR_SLEEP. */
01335 #define BS_ENET_ECR_SLEEP    (1U)          /*!< Bit field size in bits for ENET_ECR_SLEEP. */
01336 
01337 /*! @brief Read current value of the ENET_ECR_SLEEP field. */
01338 #define BR_ENET_ECR_SLEEP(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP)))
01339 
01340 /*! @brief Format value for bitfield ENET_ECR_SLEEP. */
01341 #define BF_ENET_ECR_SLEEP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_SLEEP) & BM_ENET_ECR_SLEEP)
01342 
01343 /*! @brief Set the SLEEP field to a new value. */
01344 #define BW_ENET_ECR_SLEEP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_SLEEP), v))
01345 /*@}*/
01346 
01347 /*!
01348  * @name Register ENET_ECR, field EN1588[4] (RW)
01349  *
01350  * Enables enhanced functionality of the MAC.
01351  *
01352  * Values:
01353  * - 0 - Legacy FEC buffer descriptors and functions enabled.
01354  * - 1 - Enhanced frame time-stamping functions enabled.
01355  */
01356 /*@{*/
01357 #define BP_ENET_ECR_EN1588   (4U)          /*!< Bit position for ENET_ECR_EN1588. */
01358 #define BM_ENET_ECR_EN1588   (0x00000010U) /*!< Bit mask for ENET_ECR_EN1588. */
01359 #define BS_ENET_ECR_EN1588   (1U)          /*!< Bit field size in bits for ENET_ECR_EN1588. */
01360 
01361 /*! @brief Read current value of the ENET_ECR_EN1588 field. */
01362 #define BR_ENET_ECR_EN1588(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588)))
01363 
01364 /*! @brief Format value for bitfield ENET_ECR_EN1588. */
01365 #define BF_ENET_ECR_EN1588(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_EN1588) & BM_ENET_ECR_EN1588)
01366 
01367 /*! @brief Set the EN1588 field to a new value. */
01368 #define BW_ENET_ECR_EN1588(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_EN1588), v))
01369 /*@}*/
01370 
01371 /*!
01372  * @name Register ENET_ECR, field DBGEN[6] (RW)
01373  *
01374  * Enables the MAC to enter hardware freeze mode when the device enters debug
01375  * mode.
01376  *
01377  * Values:
01378  * - 0 - MAC continues operation in debug mode.
01379  * - 1 - MAC enters hardware freeze mode when the processor is in debug mode.
01380  */
01381 /*@{*/
01382 #define BP_ENET_ECR_DBGEN    (6U)          /*!< Bit position for ENET_ECR_DBGEN. */
01383 #define BM_ENET_ECR_DBGEN    (0x00000040U) /*!< Bit mask for ENET_ECR_DBGEN. */
01384 #define BS_ENET_ECR_DBGEN    (1U)          /*!< Bit field size in bits for ENET_ECR_DBGEN. */
01385 
01386 /*! @brief Read current value of the ENET_ECR_DBGEN field. */
01387 #define BR_ENET_ECR_DBGEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN)))
01388 
01389 /*! @brief Format value for bitfield ENET_ECR_DBGEN. */
01390 #define BF_ENET_ECR_DBGEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBGEN) & BM_ENET_ECR_DBGEN)
01391 
01392 /*! @brief Set the DBGEN field to a new value. */
01393 #define BW_ENET_ECR_DBGEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBGEN), v))
01394 /*@}*/
01395 
01396 /*!
01397  * @name Register ENET_ECR, field STOPEN[7] (RW)
01398  *
01399  * Controls device behavior in doze mode. In doze mode, if this field is set
01400  * then all the clocks of the ENET assembly are disabled, except the RMII /MII
01401  * clock. Doze mode is similar to a conditional stop mode entry for the ENET assembly
01402  * depending on ECR[STOPEN]. If module clocks are gated in this mode, the module
01403  * can still wake the system after receiving a magic packet in stop mode. MAGICEN
01404  * must be set prior to entering sleep/stop mode.
01405  */
01406 /*@{*/
01407 #define BP_ENET_ECR_STOPEN   (7U)          /*!< Bit position for ENET_ECR_STOPEN. */
01408 #define BM_ENET_ECR_STOPEN   (0x00000080U) /*!< Bit mask for ENET_ECR_STOPEN. */
01409 #define BS_ENET_ECR_STOPEN   (1U)          /*!< Bit field size in bits for ENET_ECR_STOPEN. */
01410 
01411 /*! @brief Read current value of the ENET_ECR_STOPEN field. */
01412 #define BR_ENET_ECR_STOPEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN)))
01413 
01414 /*! @brief Format value for bitfield ENET_ECR_STOPEN. */
01415 #define BF_ENET_ECR_STOPEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_STOPEN) & BM_ENET_ECR_STOPEN)
01416 
01417 /*! @brief Set the STOPEN field to a new value. */
01418 #define BW_ENET_ECR_STOPEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_STOPEN), v))
01419 /*@}*/
01420 
01421 /*!
01422  * @name Register ENET_ECR, field DBSWP[8] (RW)
01423  *
01424  * Swaps the byte locations of the buffer descriptors. This field must be
01425  * written to 1 after reset.
01426  *
01427  * Values:
01428  * - 0 - The buffer descriptor bytes are not swapped to support big-endian
01429  *     devices.
01430  * - 1 - The buffer descriptor bytes are swapped to support little-endian
01431  *     devices.
01432  */
01433 /*@{*/
01434 #define BP_ENET_ECR_DBSWP    (8U)          /*!< Bit position for ENET_ECR_DBSWP. */
01435 #define BM_ENET_ECR_DBSWP    (0x00000100U) /*!< Bit mask for ENET_ECR_DBSWP. */
01436 #define BS_ENET_ECR_DBSWP    (1U)          /*!< Bit field size in bits for ENET_ECR_DBSWP. */
01437 
01438 /*! @brief Read current value of the ENET_ECR_DBSWP field. */
01439 #define BR_ENET_ECR_DBSWP(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP)))
01440 
01441 /*! @brief Format value for bitfield ENET_ECR_DBSWP. */
01442 #define BF_ENET_ECR_DBSWP(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ECR_DBSWP) & BM_ENET_ECR_DBSWP)
01443 
01444 /*! @brief Set the DBSWP field to a new value. */
01445 #define BW_ENET_ECR_DBSWP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ECR_ADDR(x), BP_ENET_ECR_DBSWP), v))
01446 /*@}*/
01447 
01448 /*******************************************************************************
01449  * HW_ENET_MMFR - MII Management Frame Register
01450  ******************************************************************************/
01451 
01452 /*!
01453  * @brief HW_ENET_MMFR - MII Management Frame Register (RW)
01454  *
01455  * Reset value: 0x00000000U
01456  *
01457  * Writing to MMFR triggers a management frame transaction to the PHY device
01458  * unless MSCR is programmed to zero. If MSCR is changed from zero to non-zero
01459  * during a write to MMFR, an MII frame is generated with the data previously written
01460  * to the MMFR. This allows MMFR and MSCR to be programmed in either order if
01461  * MSCR is currently zero. If the MMFR register is written while frame generation is
01462  * in progress, the frame contents are altered. Software must use the EIR[MII]
01463  * interrupt indication to avoid writing to the MMFR register while frame
01464  * generation is in progress.
01465  */
01466 typedef union _hw_enet_mmfr
01467 {
01468     uint32_t U;
01469     struct _hw_enet_mmfr_bitfields
01470     {
01471         uint32_t DATA : 16;            /*!< [15:0] Management Frame Data */
01472         uint32_t TA : 2;               /*!< [17:16] Turn Around */
01473         uint32_t RA : 5;               /*!< [22:18] Register Address */
01474         uint32_t PA : 5;               /*!< [27:23] PHY Address */
01475         uint32_t OP : 2;               /*!< [29:28] Operation Code */
01476         uint32_t ST : 2;               /*!< [31:30] Start Of Frame Delimiter */
01477     } B;
01478 } hw_enet_mmfr_t;
01479 
01480 /*!
01481  * @name Constants and macros for entire ENET_MMFR register
01482  */
01483 /*@{*/
01484 #define HW_ENET_MMFR_ADDR(x)     ((x) + 0x40U)
01485 
01486 #define HW_ENET_MMFR(x)          (*(__IO hw_enet_mmfr_t *) HW_ENET_MMFR_ADDR(x))
01487 #define HW_ENET_MMFR_RD(x)       (ADDRESS_READ(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x)))
01488 #define HW_ENET_MMFR_WR(x, v)    (ADDRESS_WRITE(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x), v))
01489 #define HW_ENET_MMFR_SET(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) |  (v)))
01490 #define HW_ENET_MMFR_CLR(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) & ~(v)))
01491 #define HW_ENET_MMFR_TOG(x, v)   (HW_ENET_MMFR_WR(x, HW_ENET_MMFR_RD(x) ^  (v)))
01492 /*@}*/
01493 
01494 /*
01495  * Constants & macros for individual ENET_MMFR bitfields
01496  */
01497 
01498 /*!
01499  * @name Register ENET_MMFR, field DATA[15:0] (RW)
01500  *
01501  * This is the field for data to be written to or read from the PHY register.
01502  */
01503 /*@{*/
01504 #define BP_ENET_MMFR_DATA    (0U)          /*!< Bit position for ENET_MMFR_DATA. */
01505 #define BM_ENET_MMFR_DATA    (0x0000FFFFU) /*!< Bit mask for ENET_MMFR_DATA. */
01506 #define BS_ENET_MMFR_DATA    (16U)         /*!< Bit field size in bits for ENET_MMFR_DATA. */
01507 
01508 /*! @brief Read current value of the ENET_MMFR_DATA field. */
01509 #define BR_ENET_MMFR_DATA(x) (UNION_READ(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x), U, B.DATA))
01510 
01511 /*! @brief Format value for bitfield ENET_MMFR_DATA. */
01512 #define BF_ENET_MMFR_DATA(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_DATA) & BM_ENET_MMFR_DATA)
01513 
01514 /*! @brief Set the DATA field to a new value. */
01515 #define BW_ENET_MMFR_DATA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_DATA) | BF_ENET_MMFR_DATA(v)))
01516 /*@}*/
01517 
01518 /*!
01519  * @name Register ENET_MMFR, field TA[17:16] (RW)
01520  *
01521  * This field must be programmed to 10 to generate a valid MII management frame.
01522  */
01523 /*@{*/
01524 #define BP_ENET_MMFR_TA      (16U)         /*!< Bit position for ENET_MMFR_TA. */
01525 #define BM_ENET_MMFR_TA      (0x00030000U) /*!< Bit mask for ENET_MMFR_TA. */
01526 #define BS_ENET_MMFR_TA      (2U)          /*!< Bit field size in bits for ENET_MMFR_TA. */
01527 
01528 /*! @brief Read current value of the ENET_MMFR_TA field. */
01529 #define BR_ENET_MMFR_TA(x)   (UNION_READ(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x), U, B.TA))
01530 
01531 /*! @brief Format value for bitfield ENET_MMFR_TA. */
01532 #define BF_ENET_MMFR_TA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_TA) & BM_ENET_MMFR_TA)
01533 
01534 /*! @brief Set the TA field to a new value. */
01535 #define BW_ENET_MMFR_TA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_TA) | BF_ENET_MMFR_TA(v)))
01536 /*@}*/
01537 
01538 /*!
01539  * @name Register ENET_MMFR, field RA[22:18] (RW)
01540  *
01541  * Specifies one of up to 32 registers within the specified PHY device.
01542  */
01543 /*@{*/
01544 #define BP_ENET_MMFR_RA      (18U)         /*!< Bit position for ENET_MMFR_RA. */
01545 #define BM_ENET_MMFR_RA      (0x007C0000U) /*!< Bit mask for ENET_MMFR_RA. */
01546 #define BS_ENET_MMFR_RA      (5U)          /*!< Bit field size in bits for ENET_MMFR_RA. */
01547 
01548 /*! @brief Read current value of the ENET_MMFR_RA field. */
01549 #define BR_ENET_MMFR_RA(x)   (UNION_READ(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x), U, B.RA))
01550 
01551 /*! @brief Format value for bitfield ENET_MMFR_RA. */
01552 #define BF_ENET_MMFR_RA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_RA) & BM_ENET_MMFR_RA)
01553 
01554 /*! @brief Set the RA field to a new value. */
01555 #define BW_ENET_MMFR_RA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_RA) | BF_ENET_MMFR_RA(v)))
01556 /*@}*/
01557 
01558 /*!
01559  * @name Register ENET_MMFR, field PA[27:23] (RW)
01560  *
01561  * Specifies one of up to 32 attached PHY devices.
01562  */
01563 /*@{*/
01564 #define BP_ENET_MMFR_PA      (23U)         /*!< Bit position for ENET_MMFR_PA. */
01565 #define BM_ENET_MMFR_PA      (0x0F800000U) /*!< Bit mask for ENET_MMFR_PA. */
01566 #define BS_ENET_MMFR_PA      (5U)          /*!< Bit field size in bits for ENET_MMFR_PA. */
01567 
01568 /*! @brief Read current value of the ENET_MMFR_PA field. */
01569 #define BR_ENET_MMFR_PA(x)   (UNION_READ(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x), U, B.PA))
01570 
01571 /*! @brief Format value for bitfield ENET_MMFR_PA. */
01572 #define BF_ENET_MMFR_PA(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_PA) & BM_ENET_MMFR_PA)
01573 
01574 /*! @brief Set the PA field to a new value. */
01575 #define BW_ENET_MMFR_PA(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_PA) | BF_ENET_MMFR_PA(v)))
01576 /*@}*/
01577 
01578 /*!
01579  * @name Register ENET_MMFR, field OP[29:28] (RW)
01580  *
01581  * Determines the frame operation.
01582  *
01583  * Values:
01584  * - 00 - Write frame operation, but not MII compliant.
01585  * - 01 - Write frame operation for a valid MII management frame.
01586  * - 10 - Read frame operation for a valid MII management frame.
01587  * - 11 - Read frame operation, but not MII compliant.
01588  */
01589 /*@{*/
01590 #define BP_ENET_MMFR_OP      (28U)         /*!< Bit position for ENET_MMFR_OP. */
01591 #define BM_ENET_MMFR_OP      (0x30000000U) /*!< Bit mask for ENET_MMFR_OP. */
01592 #define BS_ENET_MMFR_OP      (2U)          /*!< Bit field size in bits for ENET_MMFR_OP. */
01593 
01594 /*! @brief Read current value of the ENET_MMFR_OP field. */
01595 #define BR_ENET_MMFR_OP(x)   (UNION_READ(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x), U, B.OP))
01596 
01597 /*! @brief Format value for bitfield ENET_MMFR_OP. */
01598 #define BF_ENET_MMFR_OP(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_OP) & BM_ENET_MMFR_OP)
01599 
01600 /*! @brief Set the OP field to a new value. */
01601 #define BW_ENET_MMFR_OP(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_OP) | BF_ENET_MMFR_OP(v)))
01602 /*@}*/
01603 
01604 /*!
01605  * @name Register ENET_MMFR, field ST[31:30] (RW)
01606  *
01607  * These fields must be programmed to 01 for a valid MII management frame.
01608  */
01609 /*@{*/
01610 #define BP_ENET_MMFR_ST      (30U)         /*!< Bit position for ENET_MMFR_ST. */
01611 #define BM_ENET_MMFR_ST      (0xC0000000U) /*!< Bit mask for ENET_MMFR_ST. */
01612 #define BS_ENET_MMFR_ST      (2U)          /*!< Bit field size in bits for ENET_MMFR_ST. */
01613 
01614 /*! @brief Read current value of the ENET_MMFR_ST field. */
01615 #define BR_ENET_MMFR_ST(x)   (UNION_READ(hw_enet_mmfr_t, HW_ENET_MMFR_ADDR(x), U, B.ST))
01616 
01617 /*! @brief Format value for bitfield ENET_MMFR_ST. */
01618 #define BF_ENET_MMFR_ST(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_MMFR_ST) & BM_ENET_MMFR_ST)
01619 
01620 /*! @brief Set the ST field to a new value. */
01621 #define BW_ENET_MMFR_ST(x, v) (HW_ENET_MMFR_WR(x, (HW_ENET_MMFR_RD(x) & ~BM_ENET_MMFR_ST) | BF_ENET_MMFR_ST(v)))
01622 /*@}*/
01623 
01624 /*******************************************************************************
01625  * HW_ENET_MSCR - MII Speed Control Register
01626  ******************************************************************************/
01627 
01628 /*!
01629  * @brief HW_ENET_MSCR - MII Speed Control Register (RW)
01630  *
01631  * Reset value: 0x00000000U
01632  *
01633  * MSCR provides control of the MII clock (MDC pin) frequency and allows a
01634  * preamble drop on the MII management frame. The MII_SPEED field must be programmed
01635  * with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be
01636  * compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
01637  * a non-zero value to source a read or write management frame. After the
01638  * management frame is complete, the MSCR register may optionally be cleared to turn
01639  * off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED
01640  * changes during operation. This change takes effect following a rising or falling
01641  * edge of MDC. If the internal module clock is 25 MHz, programming this register
01642  * to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz
01643  * / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for
01644  * MII_SPEED as a function of internal module clock frequency. Programming Examples
01645  * for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz
01646  * 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz
01647  * 0xD 2.36 MHz
01648  */
01649 typedef union _hw_enet_mscr
01650 {
01651     uint32_t U;
01652     struct _hw_enet_mscr_bitfields
01653     {
01654         uint32_t RESERVED0 : 1;        /*!< [0]  */
01655         uint32_t MII_SPEED : 6;        /*!< [6:1] MII Speed */
01656         uint32_t DIS_PRE : 1;          /*!< [7] Disable Preamble */
01657         uint32_t HOLDTIME : 3;         /*!< [10:8] Hold time On MDIO Output */
01658         uint32_t RESERVED1 : 21;       /*!< [31:11]  */
01659     } B;
01660 } hw_enet_mscr_t;
01661 
01662 /*!
01663  * @name Constants and macros for entire ENET_MSCR register
01664  */
01665 /*@{*/
01666 #define HW_ENET_MSCR_ADDR(x)     ((x) + 0x44U)
01667 
01668 #define HW_ENET_MSCR(x)          (*(__IO hw_enet_mscr_t *) HW_ENET_MSCR_ADDR(x))
01669 #define HW_ENET_MSCR_RD(x)       (ADDRESS_READ(hw_enet_mscr_t, HW_ENET_MSCR_ADDR(x)))
01670 #define HW_ENET_MSCR_WR(x, v)    (ADDRESS_WRITE(hw_enet_mscr_t, HW_ENET_MSCR_ADDR(x), v))
01671 #define HW_ENET_MSCR_SET(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) |  (v)))
01672 #define HW_ENET_MSCR_CLR(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) & ~(v)))
01673 #define HW_ENET_MSCR_TOG(x, v)   (HW_ENET_MSCR_WR(x, HW_ENET_MSCR_RD(x) ^  (v)))
01674 /*@}*/
01675 
01676 /*
01677  * Constants & macros for individual ENET_MSCR bitfields
01678  */
01679 
01680 /*!
01681  * @name Register ENET_MSCR, field MII_SPEED[6:1] (RW)
01682  *
01683  * Controls the frequency of the MII management interface clock (MDC) relative
01684  * to the internal module clock. A value of 0 in this field turns off MDC and
01685  * leaves it in low voltage state. Any non-zero value results in the MDC frequency
01686  * of: 1/((MII_SPEED + 1) x 2) of the internal module clock frequency
01687  */
01688 /*@{*/
01689 #define BP_ENET_MSCR_MII_SPEED (1U)        /*!< Bit position for ENET_MSCR_MII_SPEED. */
01690 #define BM_ENET_MSCR_MII_SPEED (0x0000007EU) /*!< Bit mask for ENET_MSCR_MII_SPEED. */
01691 #define BS_ENET_MSCR_MII_SPEED (6U)        /*!< Bit field size in bits for ENET_MSCR_MII_SPEED. */
01692 
01693 /*! @brief Read current value of the ENET_MSCR_MII_SPEED field. */
01694 #define BR_ENET_MSCR_MII_SPEED(x) (UNION_READ(hw_enet_mscr_t, HW_ENET_MSCR_ADDR(x), U, B.MII_SPEED))
01695 
01696 /*! @brief Format value for bitfield ENET_MSCR_MII_SPEED. */
01697 #define BF_ENET_MSCR_MII_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_MII_SPEED) & BM_ENET_MSCR_MII_SPEED)
01698 
01699 /*! @brief Set the MII_SPEED field to a new value. */
01700 #define BW_ENET_MSCR_MII_SPEED(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_MII_SPEED) | BF_ENET_MSCR_MII_SPEED(v)))
01701 /*@}*/
01702 
01703 /*!
01704  * @name Register ENET_MSCR, field DIS_PRE[7] (RW)
01705  *
01706  * Enables/disables prepending a preamble to the MII management frame. The MII
01707  * standard allows the preamble to be dropped if the attached PHY devices do not
01708  * require it.
01709  *
01710  * Values:
01711  * - 0 - Preamble enabled.
01712  * - 1 - Preamble (32 ones) is not prepended to the MII management frame.
01713  */
01714 /*@{*/
01715 #define BP_ENET_MSCR_DIS_PRE (7U)          /*!< Bit position for ENET_MSCR_DIS_PRE. */
01716 #define BM_ENET_MSCR_DIS_PRE (0x00000080U) /*!< Bit mask for ENET_MSCR_DIS_PRE. */
01717 #define BS_ENET_MSCR_DIS_PRE (1U)          /*!< Bit field size in bits for ENET_MSCR_DIS_PRE. */
01718 
01719 /*! @brief Read current value of the ENET_MSCR_DIS_PRE field. */
01720 #define BR_ENET_MSCR_DIS_PRE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE)))
01721 
01722 /*! @brief Format value for bitfield ENET_MSCR_DIS_PRE. */
01723 #define BF_ENET_MSCR_DIS_PRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_DIS_PRE) & BM_ENET_MSCR_DIS_PRE)
01724 
01725 /*! @brief Set the DIS_PRE field to a new value. */
01726 #define BW_ENET_MSCR_DIS_PRE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_MSCR_ADDR(x), BP_ENET_MSCR_DIS_PRE), v))
01727 /*@}*/
01728 
01729 /*!
01730  * @name Register ENET_MSCR, field HOLDTIME[10:8] (RW)
01731  *
01732  * IEEE802.3 clause 22 defines a minimum of 10 ns for the hold time on the MDIO
01733  * output. Depending on the host bus frequency, the setting may need to be
01734  * increased.
01735  *
01736  * Values:
01737  * - 000 - 1 internal module clock cycle
01738  * - 001 - 2 internal module clock cycles
01739  * - 010 - 3 internal module clock cycles
01740  * - 111 - 8 internal module clock cycles
01741  */
01742 /*@{*/
01743 #define BP_ENET_MSCR_HOLDTIME (8U)         /*!< Bit position for ENET_MSCR_HOLDTIME. */
01744 #define BM_ENET_MSCR_HOLDTIME (0x00000700U) /*!< Bit mask for ENET_MSCR_HOLDTIME. */
01745 #define BS_ENET_MSCR_HOLDTIME (3U)         /*!< Bit field size in bits for ENET_MSCR_HOLDTIME. */
01746 
01747 /*! @brief Read current value of the ENET_MSCR_HOLDTIME field. */
01748 #define BR_ENET_MSCR_HOLDTIME(x) (UNION_READ(hw_enet_mscr_t, HW_ENET_MSCR_ADDR(x), U, B.HOLDTIME))
01749 
01750 /*! @brief Format value for bitfield ENET_MSCR_HOLDTIME. */
01751 #define BF_ENET_MSCR_HOLDTIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MSCR_HOLDTIME) & BM_ENET_MSCR_HOLDTIME)
01752 
01753 /*! @brief Set the HOLDTIME field to a new value. */
01754 #define BW_ENET_MSCR_HOLDTIME(x, v) (HW_ENET_MSCR_WR(x, (HW_ENET_MSCR_RD(x) & ~BM_ENET_MSCR_HOLDTIME) | BF_ENET_MSCR_HOLDTIME(v)))
01755 /*@}*/
01756 
01757 /*******************************************************************************
01758  * HW_ENET_MIBC - MIB Control Register
01759  ******************************************************************************/
01760 
01761 /*!
01762  * @brief HW_ENET_MIBC - MIB Control Register (RW)
01763  *
01764  * Reset value: 0xC0000000U
01765  *
01766  * MIBC is a read/write register controlling and observing the state of the MIB
01767  * block. Access this register to disable the MIB block operation or clear the
01768  * MIB counters. The MIB_DIS field resets to 1.
01769  */
01770 typedef union _hw_enet_mibc
01771 {
01772     uint32_t U;
01773     struct _hw_enet_mibc_bitfields
01774     {
01775         uint32_t RESERVED0 : 29;       /*!< [28:0]  */
01776         uint32_t MIB_CLEAR : 1;        /*!< [29] MIB Clear */
01777         uint32_t MIB_IDLE : 1;         /*!< [30] MIB Idle */
01778         uint32_t MIB_DIS : 1;          /*!< [31] Disable MIB Logic */
01779     } B;
01780 } hw_enet_mibc_t;
01781 
01782 /*!
01783  * @name Constants and macros for entire ENET_MIBC register
01784  */
01785 /*@{*/
01786 #define HW_ENET_MIBC_ADDR(x)     ((x) + 0x64U)
01787 
01788 #define HW_ENET_MIBC(x)          (*(__IO hw_enet_mibc_t *) HW_ENET_MIBC_ADDR(x))
01789 #define HW_ENET_MIBC_RD(x)       (ADDRESS_READ(hw_enet_mibc_t, HW_ENET_MIBC_ADDR(x)))
01790 #define HW_ENET_MIBC_WR(x, v)    (ADDRESS_WRITE(hw_enet_mibc_t, HW_ENET_MIBC_ADDR(x), v))
01791 #define HW_ENET_MIBC_SET(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) |  (v)))
01792 #define HW_ENET_MIBC_CLR(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) & ~(v)))
01793 #define HW_ENET_MIBC_TOG(x, v)   (HW_ENET_MIBC_WR(x, HW_ENET_MIBC_RD(x) ^  (v)))
01794 /*@}*/
01795 
01796 /*
01797  * Constants & macros for individual ENET_MIBC bitfields
01798  */
01799 
01800 /*!
01801  * @name Register ENET_MIBC, field MIB_CLEAR[29] (RW)
01802  *
01803  * If set, all statistics counters are reset to 0. This field is not
01804  * self-clearing. To clear the MIB counters set and then clear the field.
01805  */
01806 /*@{*/
01807 #define BP_ENET_MIBC_MIB_CLEAR (29U)       /*!< Bit position for ENET_MIBC_MIB_CLEAR. */
01808 #define BM_ENET_MIBC_MIB_CLEAR (0x20000000U) /*!< Bit mask for ENET_MIBC_MIB_CLEAR. */
01809 #define BS_ENET_MIBC_MIB_CLEAR (1U)        /*!< Bit field size in bits for ENET_MIBC_MIB_CLEAR. */
01810 
01811 /*! @brief Read current value of the ENET_MIBC_MIB_CLEAR field. */
01812 #define BR_ENET_MIBC_MIB_CLEAR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR)))
01813 
01814 /*! @brief Format value for bitfield ENET_MIBC_MIB_CLEAR. */
01815 #define BF_ENET_MIBC_MIB_CLEAR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_CLEAR) & BM_ENET_MIBC_MIB_CLEAR)
01816 
01817 /*! @brief Set the MIB_CLEAR field to a new value. */
01818 #define BW_ENET_MIBC_MIB_CLEAR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_CLEAR), v))
01819 /*@}*/
01820 
01821 /*!
01822  * @name Register ENET_MIBC, field MIB_IDLE[30] (RO)
01823  *
01824  * If this status field is set, the MIB block is not currently updating any MIB
01825  * counters.
01826  */
01827 /*@{*/
01828 #define BP_ENET_MIBC_MIB_IDLE (30U)        /*!< Bit position for ENET_MIBC_MIB_IDLE. */
01829 #define BM_ENET_MIBC_MIB_IDLE (0x40000000U) /*!< Bit mask for ENET_MIBC_MIB_IDLE. */
01830 #define BS_ENET_MIBC_MIB_IDLE (1U)         /*!< Bit field size in bits for ENET_MIBC_MIB_IDLE. */
01831 
01832 /*! @brief Read current value of the ENET_MIBC_MIB_IDLE field. */
01833 #define BR_ENET_MIBC_MIB_IDLE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_IDLE)))
01834 /*@}*/
01835 
01836 /*!
01837  * @name Register ENET_MIBC, field MIB_DIS[31] (RW)
01838  *
01839  * If this control field is set, the MIB logic halts and does not update any MIB
01840  * counters.
01841  */
01842 /*@{*/
01843 #define BP_ENET_MIBC_MIB_DIS (31U)         /*!< Bit position for ENET_MIBC_MIB_DIS. */
01844 #define BM_ENET_MIBC_MIB_DIS (0x80000000U) /*!< Bit mask for ENET_MIBC_MIB_DIS. */
01845 #define BS_ENET_MIBC_MIB_DIS (1U)          /*!< Bit field size in bits for ENET_MIBC_MIB_DIS. */
01846 
01847 /*! @brief Read current value of the ENET_MIBC_MIB_DIS field. */
01848 #define BR_ENET_MIBC_MIB_DIS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS)))
01849 
01850 /*! @brief Format value for bitfield ENET_MIBC_MIB_DIS. */
01851 #define BF_ENET_MIBC_MIB_DIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MIBC_MIB_DIS) & BM_ENET_MIBC_MIB_DIS)
01852 
01853 /*! @brief Set the MIB_DIS field to a new value. */
01854 #define BW_ENET_MIBC_MIB_DIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_MIBC_ADDR(x), BP_ENET_MIBC_MIB_DIS), v))
01855 /*@}*/
01856 
01857 /*******************************************************************************
01858  * HW_ENET_RCR - Receive Control Register
01859  ******************************************************************************/
01860 
01861 /*!
01862  * @brief HW_ENET_RCR - Receive Control Register (RW)
01863  *
01864  * Reset value: 0x05EE0001U
01865  */
01866 typedef union _hw_enet_rcr
01867 {
01868     uint32_t U;
01869     struct _hw_enet_rcr_bitfields
01870     {
01871         uint32_t LOOP : 1;             /*!< [0] Internal Loopback */
01872         uint32_t DRT : 1;              /*!< [1] Disable Receive On Transmit */
01873         uint32_t MII_MODE : 1;         /*!< [2] Media Independent Interface Mode */
01874         uint32_t PROM : 1;             /*!< [3] Promiscuous Mode */
01875         uint32_t BC_REJ : 1;           /*!< [4] Broadcast Frame Reject */
01876         uint32_t FCE : 1;              /*!< [5] Flow Control Enable */
01877         uint32_t RESERVED0 : 2;        /*!< [7:6]  */
01878         uint32_t RMII_MODE : 1;        /*!< [8] RMII Mode Enable */
01879         uint32_t RMII_10T : 1;         /*!< [9]  */
01880         uint32_t RESERVED1 : 2;        /*!< [11:10]  */
01881         uint32_t PADEN : 1;            /*!< [12] Enable Frame Padding Remove On Receive
01882                                         * */
01883         uint32_t PAUFWD : 1;           /*!< [13] Terminate/Forward Pause Frames */
01884         uint32_t CRCFWD : 1;           /*!< [14] Terminate/Forward Received CRC */
01885         uint32_t CFEN : 1;             /*!< [15] MAC Control Frame Enable */
01886         uint32_t MAX_FL : 14;          /*!< [29:16] Maximum Frame Length */
01887         uint32_t NLC : 1;              /*!< [30] Payload Length Check Disable */
01888         uint32_t GRS : 1;              /*!< [31] Graceful Receive Stopped */
01889     } B;
01890 } hw_enet_rcr_t;
01891 
01892 /*!
01893  * @name Constants and macros for entire ENET_RCR register
01894  */
01895 /*@{*/
01896 #define HW_ENET_RCR_ADDR(x)      ((x) + 0x84U)
01897 
01898 #define HW_ENET_RCR(x)           (*(__IO hw_enet_rcr_t *) HW_ENET_RCR_ADDR(x))
01899 #define HW_ENET_RCR_RD(x)        (ADDRESS_READ(hw_enet_rcr_t, HW_ENET_RCR_ADDR(x)))
01900 #define HW_ENET_RCR_WR(x, v)     (ADDRESS_WRITE(hw_enet_rcr_t, HW_ENET_RCR_ADDR(x), v))
01901 #define HW_ENET_RCR_SET(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) |  (v)))
01902 #define HW_ENET_RCR_CLR(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) & ~(v)))
01903 #define HW_ENET_RCR_TOG(x, v)    (HW_ENET_RCR_WR(x, HW_ENET_RCR_RD(x) ^  (v)))
01904 /*@}*/
01905 
01906 /*
01907  * Constants & macros for individual ENET_RCR bitfields
01908  */
01909 
01910 /*!
01911  * @name Register ENET_RCR, field LOOP[0] (RW)
01912  *
01913  * This is an MII internal loopback, therefore MII_MODE must be written to 1 and
01914  * RMII_MODE must be written to 0.
01915  *
01916  * Values:
01917  * - 0 - Loopback disabled.
01918  * - 1 - Transmitted frames are looped back internal to the device and transmit
01919  *     MII output signals are not asserted. DRT must be cleared.
01920  */
01921 /*@{*/
01922 #define BP_ENET_RCR_LOOP     (0U)          /*!< Bit position for ENET_RCR_LOOP. */
01923 #define BM_ENET_RCR_LOOP     (0x00000001U) /*!< Bit mask for ENET_RCR_LOOP. */
01924 #define BS_ENET_RCR_LOOP     (1U)          /*!< Bit field size in bits for ENET_RCR_LOOP. */
01925 
01926 /*! @brief Read current value of the ENET_RCR_LOOP field. */
01927 #define BR_ENET_RCR_LOOP(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP)))
01928 
01929 /*! @brief Format value for bitfield ENET_RCR_LOOP. */
01930 #define BF_ENET_RCR_LOOP(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_LOOP) & BM_ENET_RCR_LOOP)
01931 
01932 /*! @brief Set the LOOP field to a new value. */
01933 #define BW_ENET_RCR_LOOP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_LOOP), v))
01934 /*@}*/
01935 
01936 /*!
01937  * @name Register ENET_RCR, field DRT[1] (RW)
01938  *
01939  * Values:
01940  * - 0 - Receive path operates independently of transmit. Used for full-duplex
01941  *     or to monitor transmit activity in half-duplex mode.
01942  * - 1 - Disable reception of frames while transmitting. Normally used for
01943  *     half-duplex mode.
01944  */
01945 /*@{*/
01946 #define BP_ENET_RCR_DRT      (1U)          /*!< Bit position for ENET_RCR_DRT. */
01947 #define BM_ENET_RCR_DRT      (0x00000002U) /*!< Bit mask for ENET_RCR_DRT. */
01948 #define BS_ENET_RCR_DRT      (1U)          /*!< Bit field size in bits for ENET_RCR_DRT. */
01949 
01950 /*! @brief Read current value of the ENET_RCR_DRT field. */
01951 #define BR_ENET_RCR_DRT(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT)))
01952 
01953 /*! @brief Format value for bitfield ENET_RCR_DRT. */
01954 #define BF_ENET_RCR_DRT(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_DRT) & BM_ENET_RCR_DRT)
01955 
01956 /*! @brief Set the DRT field to a new value. */
01957 #define BW_ENET_RCR_DRT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_DRT), v))
01958 /*@}*/
01959 
01960 /*!
01961  * @name Register ENET_RCR, field MII_MODE[2] (RW)
01962  *
01963  * This field must always be set.
01964  *
01965  * Values:
01966  * - 0 - Reserved.
01967  * - 1 - MII or RMII mode, as indicated by the RMII_MODE field.
01968  */
01969 /*@{*/
01970 #define BP_ENET_RCR_MII_MODE (2U)          /*!< Bit position for ENET_RCR_MII_MODE. */
01971 #define BM_ENET_RCR_MII_MODE (0x00000004U) /*!< Bit mask for ENET_RCR_MII_MODE. */
01972 #define BS_ENET_RCR_MII_MODE (1U)          /*!< Bit field size in bits for ENET_RCR_MII_MODE. */
01973 
01974 /*! @brief Read current value of the ENET_RCR_MII_MODE field. */
01975 #define BR_ENET_RCR_MII_MODE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE)))
01976 
01977 /*! @brief Format value for bitfield ENET_RCR_MII_MODE. */
01978 #define BF_ENET_RCR_MII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MII_MODE) & BM_ENET_RCR_MII_MODE)
01979 
01980 /*! @brief Set the MII_MODE field to a new value. */
01981 #define BW_ENET_RCR_MII_MODE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_MII_MODE), v))
01982 /*@}*/
01983 
01984 /*!
01985  * @name Register ENET_RCR, field PROM[3] (RW)
01986  *
01987  * All frames are accepted regardless of address matching.
01988  *
01989  * Values:
01990  * - 0 - Disabled.
01991  * - 1 - Enabled.
01992  */
01993 /*@{*/
01994 #define BP_ENET_RCR_PROM     (3U)          /*!< Bit position for ENET_RCR_PROM. */
01995 #define BM_ENET_RCR_PROM     (0x00000008U) /*!< Bit mask for ENET_RCR_PROM. */
01996 #define BS_ENET_RCR_PROM     (1U)          /*!< Bit field size in bits for ENET_RCR_PROM. */
01997 
01998 /*! @brief Read current value of the ENET_RCR_PROM field. */
01999 #define BR_ENET_RCR_PROM(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM)))
02000 
02001 /*! @brief Format value for bitfield ENET_RCR_PROM. */
02002 #define BF_ENET_RCR_PROM(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PROM) & BM_ENET_RCR_PROM)
02003 
02004 /*! @brief Set the PROM field to a new value. */
02005 #define BW_ENET_RCR_PROM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PROM), v))
02006 /*@}*/
02007 
02008 /*!
02009  * @name Register ENET_RCR, field BC_REJ[4] (RW)
02010  *
02011  * If set, frames with destination address (DA) equal to 0xFFFF_FFFF_FFFF are
02012  * rejected unless the PROM field is set. If BC_REJ and PROM are set, frames with
02013  * broadcast DA are accepted and the MISS (M) is set in the receive buffer
02014  * descriptor.
02015  */
02016 /*@{*/
02017 #define BP_ENET_RCR_BC_REJ   (4U)          /*!< Bit position for ENET_RCR_BC_REJ. */
02018 #define BM_ENET_RCR_BC_REJ   (0x00000010U) /*!< Bit mask for ENET_RCR_BC_REJ. */
02019 #define BS_ENET_RCR_BC_REJ   (1U)          /*!< Bit field size in bits for ENET_RCR_BC_REJ. */
02020 
02021 /*! @brief Read current value of the ENET_RCR_BC_REJ field. */
02022 #define BR_ENET_RCR_BC_REJ(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ)))
02023 
02024 /*! @brief Format value for bitfield ENET_RCR_BC_REJ. */
02025 #define BF_ENET_RCR_BC_REJ(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_BC_REJ) & BM_ENET_RCR_BC_REJ)
02026 
02027 /*! @brief Set the BC_REJ field to a new value. */
02028 #define BW_ENET_RCR_BC_REJ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_BC_REJ), v))
02029 /*@}*/
02030 
02031 /*!
02032  * @name Register ENET_RCR, field FCE[5] (RW)
02033  *
02034  * If set, the receiver detects PAUSE frames. Upon PAUSE frame detection, the
02035  * transmitter stops transmitting data frames for a given duration.
02036  */
02037 /*@{*/
02038 #define BP_ENET_RCR_FCE      (5U)          /*!< Bit position for ENET_RCR_FCE. */
02039 #define BM_ENET_RCR_FCE      (0x00000020U) /*!< Bit mask for ENET_RCR_FCE. */
02040 #define BS_ENET_RCR_FCE      (1U)          /*!< Bit field size in bits for ENET_RCR_FCE. */
02041 
02042 /*! @brief Read current value of the ENET_RCR_FCE field. */
02043 #define BR_ENET_RCR_FCE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE)))
02044 
02045 /*! @brief Format value for bitfield ENET_RCR_FCE. */
02046 #define BF_ENET_RCR_FCE(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_FCE) & BM_ENET_RCR_FCE)
02047 
02048 /*! @brief Set the FCE field to a new value. */
02049 #define BW_ENET_RCR_FCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_FCE), v))
02050 /*@}*/
02051 
02052 /*!
02053  * @name Register ENET_RCR, field RMII_MODE[8] (RW)
02054  *
02055  * Specifies whether the MAC is configured for MII mode or RMII operation .
02056  *
02057  * Values:
02058  * - 0 - MAC configured for MII mode.
02059  * - 1 - MAC configured for RMII operation.
02060  */
02061 /*@{*/
02062 #define BP_ENET_RCR_RMII_MODE (8U)         /*!< Bit position for ENET_RCR_RMII_MODE. */
02063 #define BM_ENET_RCR_RMII_MODE (0x00000100U) /*!< Bit mask for ENET_RCR_RMII_MODE. */
02064 #define BS_ENET_RCR_RMII_MODE (1U)         /*!< Bit field size in bits for ENET_RCR_RMII_MODE. */
02065 
02066 /*! @brief Read current value of the ENET_RCR_RMII_MODE field. */
02067 #define BR_ENET_RCR_RMII_MODE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE)))
02068 
02069 /*! @brief Format value for bitfield ENET_RCR_RMII_MODE. */
02070 #define BF_ENET_RCR_RMII_MODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_MODE) & BM_ENET_RCR_RMII_MODE)
02071 
02072 /*! @brief Set the RMII_MODE field to a new value. */
02073 #define BW_ENET_RCR_RMII_MODE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_MODE), v))
02074 /*@}*/
02075 
02076 /*!
02077  * @name Register ENET_RCR, field RMII_10T[9] (RW)
02078  *
02079  * Enables 10-Mbps mode of the RMII .
02080  *
02081  * Values:
02082  * - 0 - 100 Mbps operation.
02083  * - 1 - 10 Mbps operation.
02084  */
02085 /*@{*/
02086 #define BP_ENET_RCR_RMII_10T (9U)          /*!< Bit position for ENET_RCR_RMII_10T. */
02087 #define BM_ENET_RCR_RMII_10T (0x00000200U) /*!< Bit mask for ENET_RCR_RMII_10T. */
02088 #define BS_ENET_RCR_RMII_10T (1U)          /*!< Bit field size in bits for ENET_RCR_RMII_10T. */
02089 
02090 /*! @brief Read current value of the ENET_RCR_RMII_10T field. */
02091 #define BR_ENET_RCR_RMII_10T(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T)))
02092 
02093 /*! @brief Format value for bitfield ENET_RCR_RMII_10T. */
02094 #define BF_ENET_RCR_RMII_10T(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_RMII_10T) & BM_ENET_RCR_RMII_10T)
02095 
02096 /*! @brief Set the RMII_10T field to a new value. */
02097 #define BW_ENET_RCR_RMII_10T(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_RMII_10T), v))
02098 /*@}*/
02099 
02100 /*!
02101  * @name Register ENET_RCR, field PADEN[12] (RW)
02102  *
02103  * Specifies whether the MAC removes padding from received frames.
02104  *
02105  * Values:
02106  * - 0 - No padding is removed on receive by the MAC.
02107  * - 1 - Padding is removed from received frames.
02108  */
02109 /*@{*/
02110 #define BP_ENET_RCR_PADEN    (12U)         /*!< Bit position for ENET_RCR_PADEN. */
02111 #define BM_ENET_RCR_PADEN    (0x00001000U) /*!< Bit mask for ENET_RCR_PADEN. */
02112 #define BS_ENET_RCR_PADEN    (1U)          /*!< Bit field size in bits for ENET_RCR_PADEN. */
02113 
02114 /*! @brief Read current value of the ENET_RCR_PADEN field. */
02115 #define BR_ENET_RCR_PADEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN)))
02116 
02117 /*! @brief Format value for bitfield ENET_RCR_PADEN. */
02118 #define BF_ENET_RCR_PADEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PADEN) & BM_ENET_RCR_PADEN)
02119 
02120 /*! @brief Set the PADEN field to a new value. */
02121 #define BW_ENET_RCR_PADEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PADEN), v))
02122 /*@}*/
02123 
02124 /*!
02125  * @name Register ENET_RCR, field PAUFWD[13] (RW)
02126  *
02127  * Specifies whether pause frames are terminated or forwarded.
02128  *
02129  * Values:
02130  * - 0 - Pause frames are terminated and discarded in the MAC.
02131  * - 1 - Pause frames are forwarded to the user application.
02132  */
02133 /*@{*/
02134 #define BP_ENET_RCR_PAUFWD   (13U)         /*!< Bit position for ENET_RCR_PAUFWD. */
02135 #define BM_ENET_RCR_PAUFWD   (0x00002000U) /*!< Bit mask for ENET_RCR_PAUFWD. */
02136 #define BS_ENET_RCR_PAUFWD   (1U)          /*!< Bit field size in bits for ENET_RCR_PAUFWD. */
02137 
02138 /*! @brief Read current value of the ENET_RCR_PAUFWD field. */
02139 #define BR_ENET_RCR_PAUFWD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD)))
02140 
02141 /*! @brief Format value for bitfield ENET_RCR_PAUFWD. */
02142 #define BF_ENET_RCR_PAUFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_PAUFWD) & BM_ENET_RCR_PAUFWD)
02143 
02144 /*! @brief Set the PAUFWD field to a new value. */
02145 #define BW_ENET_RCR_PAUFWD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_PAUFWD), v))
02146 /*@}*/
02147 
02148 /*!
02149  * @name Register ENET_RCR, field CRCFWD[14] (RW)
02150  *
02151  * Specifies whether the CRC field of received frames is transmitted or
02152  * stripped. If padding function is enabled (PADEN = 1), CRCFWD is ignored and the CRC
02153  * field is checked and always terminated and removed.
02154  *
02155  * Values:
02156  * - 0 - The CRC field of received frames is transmitted to the user application.
02157  * - 1 - The CRC field is stripped from the frame.
02158  */
02159 /*@{*/
02160 #define BP_ENET_RCR_CRCFWD   (14U)         /*!< Bit position for ENET_RCR_CRCFWD. */
02161 #define BM_ENET_RCR_CRCFWD   (0x00004000U) /*!< Bit mask for ENET_RCR_CRCFWD. */
02162 #define BS_ENET_RCR_CRCFWD   (1U)          /*!< Bit field size in bits for ENET_RCR_CRCFWD. */
02163 
02164 /*! @brief Read current value of the ENET_RCR_CRCFWD field. */
02165 #define BR_ENET_RCR_CRCFWD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD)))
02166 
02167 /*! @brief Format value for bitfield ENET_RCR_CRCFWD. */
02168 #define BF_ENET_RCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CRCFWD) & BM_ENET_RCR_CRCFWD)
02169 
02170 /*! @brief Set the CRCFWD field to a new value. */
02171 #define BW_ENET_RCR_CRCFWD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CRCFWD), v))
02172 /*@}*/
02173 
02174 /*!
02175  * @name Register ENET_RCR, field CFEN[15] (RW)
02176  *
02177  * Enables/disables the MAC control frame.
02178  *
02179  * Values:
02180  * - 0 - MAC control frames with any opcode other than 0x0001 (pause frame) are
02181  *     accepted and forwarded to the client interface.
02182  * - 1 - MAC control frames with any opcode other than 0x0001 (pause frame) are
02183  *     silently discarded.
02184  */
02185 /*@{*/
02186 #define BP_ENET_RCR_CFEN     (15U)         /*!< Bit position for ENET_RCR_CFEN. */
02187 #define BM_ENET_RCR_CFEN     (0x00008000U) /*!< Bit mask for ENET_RCR_CFEN. */
02188 #define BS_ENET_RCR_CFEN     (1U)          /*!< Bit field size in bits for ENET_RCR_CFEN. */
02189 
02190 /*! @brief Read current value of the ENET_RCR_CFEN field. */
02191 #define BR_ENET_RCR_CFEN(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN)))
02192 
02193 /*! @brief Format value for bitfield ENET_RCR_CFEN. */
02194 #define BF_ENET_RCR_CFEN(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_CFEN) & BM_ENET_RCR_CFEN)
02195 
02196 /*! @brief Set the CFEN field to a new value. */
02197 #define BW_ENET_RCR_CFEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_CFEN), v))
02198 /*@}*/
02199 
02200 /*!
02201  * @name Register ENET_RCR, field MAX_FL[29:16] (RW)
02202  *
02203  * Resets to decimal 1518. Length is measured starting at DA and includes the
02204  * CRC at the end of the frame. Transmit frames longer than MAX_FL cause the BABT
02205  * interrupt to occur. Receive frames longer than MAX_FL cause the BABR interrupt
02206  * to occur and set the LG field in the end of frame receive buffer descriptor.
02207  * The recommended default value to be programmed is 1518 or 1522 if VLAN tags are
02208  * supported.
02209  */
02210 /*@{*/
02211 #define BP_ENET_RCR_MAX_FL   (16U)         /*!< Bit position for ENET_RCR_MAX_FL. */
02212 #define BM_ENET_RCR_MAX_FL   (0x3FFF0000U) /*!< Bit mask for ENET_RCR_MAX_FL. */
02213 #define BS_ENET_RCR_MAX_FL   (14U)         /*!< Bit field size in bits for ENET_RCR_MAX_FL. */
02214 
02215 /*! @brief Read current value of the ENET_RCR_MAX_FL field. */
02216 #define BR_ENET_RCR_MAX_FL(x) (UNION_READ(hw_enet_rcr_t, HW_ENET_RCR_ADDR(x), U, B.MAX_FL))
02217 
02218 /*! @brief Format value for bitfield ENET_RCR_MAX_FL. */
02219 #define BF_ENET_RCR_MAX_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_MAX_FL) & BM_ENET_RCR_MAX_FL)
02220 
02221 /*! @brief Set the MAX_FL field to a new value. */
02222 #define BW_ENET_RCR_MAX_FL(x, v) (HW_ENET_RCR_WR(x, (HW_ENET_RCR_RD(x) & ~BM_ENET_RCR_MAX_FL) | BF_ENET_RCR_MAX_FL(v)))
02223 /*@}*/
02224 
02225 /*!
02226  * @name Register ENET_RCR, field NLC[30] (RW)
02227  *
02228  * Enables/disables a payload length check.
02229  *
02230  * Values:
02231  * - 0 - The payload length check is disabled.
02232  * - 1 - The core checks the frame's payload length with the frame length/type
02233  *     field. Errors are indicated in the EIR[PLC] field.
02234  */
02235 /*@{*/
02236 #define BP_ENET_RCR_NLC      (30U)         /*!< Bit position for ENET_RCR_NLC. */
02237 #define BM_ENET_RCR_NLC      (0x40000000U) /*!< Bit mask for ENET_RCR_NLC. */
02238 #define BS_ENET_RCR_NLC      (1U)          /*!< Bit field size in bits for ENET_RCR_NLC. */
02239 
02240 /*! @brief Read current value of the ENET_RCR_NLC field. */
02241 #define BR_ENET_RCR_NLC(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC)))
02242 
02243 /*! @brief Format value for bitfield ENET_RCR_NLC. */
02244 #define BF_ENET_RCR_NLC(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_RCR_NLC) & BM_ENET_RCR_NLC)
02245 
02246 /*! @brief Set the NLC field to a new value. */
02247 #define BW_ENET_RCR_NLC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_NLC), v))
02248 /*@}*/
02249 
02250 /*!
02251  * @name Register ENET_RCR, field GRS[31] (RO)
02252  *
02253  * Read-only status indicating that the MAC receive datapath is stopped.
02254  */
02255 /*@{*/
02256 #define BP_ENET_RCR_GRS      (31U)         /*!< Bit position for ENET_RCR_GRS. */
02257 #define BM_ENET_RCR_GRS      (0x80000000U) /*!< Bit mask for ENET_RCR_GRS. */
02258 #define BS_ENET_RCR_GRS      (1U)          /*!< Bit field size in bits for ENET_RCR_GRS. */
02259 
02260 /*! @brief Read current value of the ENET_RCR_GRS field. */
02261 #define BR_ENET_RCR_GRS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RCR_ADDR(x), BP_ENET_RCR_GRS)))
02262 /*@}*/
02263 
02264 /*******************************************************************************
02265  * HW_ENET_TCR - Transmit Control Register
02266  ******************************************************************************/
02267 
02268 /*!
02269  * @brief HW_ENET_TCR - Transmit Control Register (RW)
02270  *
02271  * Reset value: 0x00000000U
02272  *
02273  * TCR is read/write and configures the transmit block. This register is cleared
02274  * at system reset. FDEN can only be modified when ECR[ETHEREN] is cleared.
02275  */
02276 typedef union _hw_enet_tcr
02277 {
02278     uint32_t U;
02279     struct _hw_enet_tcr_bitfields
02280     {
02281         uint32_t GTS : 1;              /*!< [0] Graceful Transmit Stop */
02282         uint32_t RESERVED0 : 1;        /*!< [1]  */
02283         uint32_t FDEN : 1;             /*!< [2] Full-Duplex Enable */
02284         uint32_t TFC_PAUSE : 1;        /*!< [3] Transmit Frame Control Pause */
02285         uint32_t RFC_PAUSE : 1;        /*!< [4] Receive Frame Control Pause */
02286         uint32_t ADDSEL : 3;           /*!< [7:5] Source MAC Address Select On Transmit
02287                                         * */
02288         uint32_t ADDINS : 1;           /*!< [8] Set MAC Address On Transmit */
02289         uint32_t CRCFWD : 1;           /*!< [9] Forward Frame From Application With CRC
02290                                         * */
02291         uint32_t RESERVED1 : 22;       /*!< [31:10]  */
02292     } B;
02293 } hw_enet_tcr_t;
02294 
02295 /*!
02296  * @name Constants and macros for entire ENET_TCR register
02297  */
02298 /*@{*/
02299 #define HW_ENET_TCR_ADDR(x)      ((x) + 0xC4U)
02300 
02301 #define HW_ENET_TCR(x)           (*(__IO hw_enet_tcr_t *) HW_ENET_TCR_ADDR(x))
02302 #define HW_ENET_TCR_RD(x)        (ADDRESS_READ(hw_enet_tcr_t, HW_ENET_TCR_ADDR(x)))
02303 #define HW_ENET_TCR_WR(x, v)     (ADDRESS_WRITE(hw_enet_tcr_t, HW_ENET_TCR_ADDR(x), v))
02304 #define HW_ENET_TCR_SET(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) |  (v)))
02305 #define HW_ENET_TCR_CLR(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) & ~(v)))
02306 #define HW_ENET_TCR_TOG(x, v)    (HW_ENET_TCR_WR(x, HW_ENET_TCR_RD(x) ^  (v)))
02307 /*@}*/
02308 
02309 /*
02310  * Constants & macros for individual ENET_TCR bitfields
02311  */
02312 
02313 /*!
02314  * @name Register ENET_TCR, field GTS[0] (RW)
02315  *
02316  * When this field is set, MAC stops transmission after any frame currently
02317  * transmitted is complete and EIR[GRA] is set. If frame transmission is not
02318  * currently underway, the GRA interrupt is asserted immediately. After transmission
02319  * finishes, clear GTS to restart. The next frame in the transmit FIFO is then
02320  * transmitted. If an early collision occurs during transmission when GTS is set,
02321  * transmission stops after the collision. The frame is transmitted again after GTS is
02322  * cleared. There may be old frames in the transmit FIFO that transmit when GTS
02323  * is reasserted. To avoid this, clear ECR[ETHEREN] following the GRA interrupt.
02324  */
02325 /*@{*/
02326 #define BP_ENET_TCR_GTS      (0U)          /*!< Bit position for ENET_TCR_GTS. */
02327 #define BM_ENET_TCR_GTS      (0x00000001U) /*!< Bit mask for ENET_TCR_GTS. */
02328 #define BS_ENET_TCR_GTS      (1U)          /*!< Bit field size in bits for ENET_TCR_GTS. */
02329 
02330 /*! @brief Read current value of the ENET_TCR_GTS field. */
02331 #define BR_ENET_TCR_GTS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS)))
02332 
02333 /*! @brief Format value for bitfield ENET_TCR_GTS. */
02334 #define BF_ENET_TCR_GTS(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_GTS) & BM_ENET_TCR_GTS)
02335 
02336 /*! @brief Set the GTS field to a new value. */
02337 #define BW_ENET_TCR_GTS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_GTS), v))
02338 /*@}*/
02339 
02340 /*!
02341  * @name Register ENET_TCR, field FDEN[2] (RW)
02342  *
02343  * If this field is set, frames transmit independent of carrier sense and
02344  * collision inputs. Only modify this bit when ECR[ETHEREN] is cleared.
02345  */
02346 /*@{*/
02347 #define BP_ENET_TCR_FDEN     (2U)          /*!< Bit position for ENET_TCR_FDEN. */
02348 #define BM_ENET_TCR_FDEN     (0x00000004U) /*!< Bit mask for ENET_TCR_FDEN. */
02349 #define BS_ENET_TCR_FDEN     (1U)          /*!< Bit field size in bits for ENET_TCR_FDEN. */
02350 
02351 /*! @brief Read current value of the ENET_TCR_FDEN field. */
02352 #define BR_ENET_TCR_FDEN(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN)))
02353 
02354 /*! @brief Format value for bitfield ENET_TCR_FDEN. */
02355 #define BF_ENET_TCR_FDEN(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_FDEN) & BM_ENET_TCR_FDEN)
02356 
02357 /*! @brief Set the FDEN field to a new value. */
02358 #define BW_ENET_TCR_FDEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_FDEN), v))
02359 /*@}*/
02360 
02361 /*!
02362  * @name Register ENET_TCR, field TFC_PAUSE[3] (RW)
02363  *
02364  * Pauses frame transmission. When this field is set, EIR[GRA] is set. With
02365  * transmission of data frames stopped, the MAC transmits a MAC control PAUSE frame.
02366  * Next, the MAC clears TFC_PAUSE and resumes transmitting data frames. If the
02367  * transmitter pauses due to user assertion of GTS or reception of a PAUSE frame,
02368  * the MAC may continue transmitting a MAC control PAUSE frame.
02369  *
02370  * Values:
02371  * - 0 - No PAUSE frame transmitted.
02372  * - 1 - The MAC stops transmission of data frames after the current
02373  *     transmission is complete.
02374  */
02375 /*@{*/
02376 #define BP_ENET_TCR_TFC_PAUSE (3U)         /*!< Bit position for ENET_TCR_TFC_PAUSE. */
02377 #define BM_ENET_TCR_TFC_PAUSE (0x00000008U) /*!< Bit mask for ENET_TCR_TFC_PAUSE. */
02378 #define BS_ENET_TCR_TFC_PAUSE (1U)         /*!< Bit field size in bits for ENET_TCR_TFC_PAUSE. */
02379 
02380 /*! @brief Read current value of the ENET_TCR_TFC_PAUSE field. */
02381 #define BR_ENET_TCR_TFC_PAUSE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE)))
02382 
02383 /*! @brief Format value for bitfield ENET_TCR_TFC_PAUSE. */
02384 #define BF_ENET_TCR_TFC_PAUSE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_TFC_PAUSE) & BM_ENET_TCR_TFC_PAUSE)
02385 
02386 /*! @brief Set the TFC_PAUSE field to a new value. */
02387 #define BW_ENET_TCR_TFC_PAUSE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_TFC_PAUSE), v))
02388 /*@}*/
02389 
02390 /*!
02391  * @name Register ENET_TCR, field RFC_PAUSE[4] (RO)
02392  *
02393  * This status field is set when a full-duplex flow control pause frame is
02394  * received and the transmitter pauses for the duration defined in this pause frame.
02395  * This field automatically clears when the pause duration is complete.
02396  */
02397 /*@{*/
02398 #define BP_ENET_TCR_RFC_PAUSE (4U)         /*!< Bit position for ENET_TCR_RFC_PAUSE. */
02399 #define BM_ENET_TCR_RFC_PAUSE (0x00000010U) /*!< Bit mask for ENET_TCR_RFC_PAUSE. */
02400 #define BS_ENET_TCR_RFC_PAUSE (1U)         /*!< Bit field size in bits for ENET_TCR_RFC_PAUSE. */
02401 
02402 /*! @brief Read current value of the ENET_TCR_RFC_PAUSE field. */
02403 #define BR_ENET_TCR_RFC_PAUSE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_RFC_PAUSE)))
02404 /*@}*/
02405 
02406 /*!
02407  * @name Register ENET_TCR, field ADDSEL[7:5] (RW)
02408  *
02409  * If ADDINS is set, indicates the MAC address that overwrites the source MAC
02410  * address.
02411  *
02412  * Values:
02413  * - 000 - Node MAC address programmed on PADDR1/2 registers.
02414  * - 100 - Reserved.
02415  * - 101 - Reserved.
02416  * - 110 - Reserved.
02417  */
02418 /*@{*/
02419 #define BP_ENET_TCR_ADDSEL   (5U)          /*!< Bit position for ENET_TCR_ADDSEL. */
02420 #define BM_ENET_TCR_ADDSEL   (0x000000E0U) /*!< Bit mask for ENET_TCR_ADDSEL. */
02421 #define BS_ENET_TCR_ADDSEL   (3U)          /*!< Bit field size in bits for ENET_TCR_ADDSEL. */
02422 
02423 /*! @brief Read current value of the ENET_TCR_ADDSEL field. */
02424 #define BR_ENET_TCR_ADDSEL(x) (UNION_READ(hw_enet_tcr_t, HW_ENET_TCR_ADDR(x), U, B.ADDSEL))
02425 
02426 /*! @brief Format value for bitfield ENET_TCR_ADDSEL. */
02427 #define BF_ENET_TCR_ADDSEL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDSEL) & BM_ENET_TCR_ADDSEL)
02428 
02429 /*! @brief Set the ADDSEL field to a new value. */
02430 #define BW_ENET_TCR_ADDSEL(x, v) (HW_ENET_TCR_WR(x, (HW_ENET_TCR_RD(x) & ~BM_ENET_TCR_ADDSEL) | BF_ENET_TCR_ADDSEL(v)))
02431 /*@}*/
02432 
02433 /*!
02434  * @name Register ENET_TCR, field ADDINS[8] (RW)
02435  *
02436  * Values:
02437  * - 0 - The source MAC address is not modified by the MAC.
02438  * - 1 - The MAC overwrites the source MAC address with the programmed MAC
02439  *     address according to ADDSEL.
02440  */
02441 /*@{*/
02442 #define BP_ENET_TCR_ADDINS   (8U)          /*!< Bit position for ENET_TCR_ADDINS. */
02443 #define BM_ENET_TCR_ADDINS   (0x00000100U) /*!< Bit mask for ENET_TCR_ADDINS. */
02444 #define BS_ENET_TCR_ADDINS   (1U)          /*!< Bit field size in bits for ENET_TCR_ADDINS. */
02445 
02446 /*! @brief Read current value of the ENET_TCR_ADDINS field. */
02447 #define BR_ENET_TCR_ADDINS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS)))
02448 
02449 /*! @brief Format value for bitfield ENET_TCR_ADDINS. */
02450 #define BF_ENET_TCR_ADDINS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_ADDINS) & BM_ENET_TCR_ADDINS)
02451 
02452 /*! @brief Set the ADDINS field to a new value. */
02453 #define BW_ENET_TCR_ADDINS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_ADDINS), v))
02454 /*@}*/
02455 
02456 /*!
02457  * @name Register ENET_TCR, field CRCFWD[9] (RW)
02458  *
02459  * Values:
02460  * - 0 - TxBD[TC] controls whether the frame has a CRC from the application.
02461  * - 1 - The transmitter does not append any CRC to transmitted frames, as it is
02462  *     expecting a frame with CRC from the application.
02463  */
02464 /*@{*/
02465 #define BP_ENET_TCR_CRCFWD   (9U)          /*!< Bit position for ENET_TCR_CRCFWD. */
02466 #define BM_ENET_TCR_CRCFWD   (0x00000200U) /*!< Bit mask for ENET_TCR_CRCFWD. */
02467 #define BS_ENET_TCR_CRCFWD   (1U)          /*!< Bit field size in bits for ENET_TCR_CRCFWD. */
02468 
02469 /*! @brief Read current value of the ENET_TCR_CRCFWD field. */
02470 #define BR_ENET_TCR_CRCFWD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD)))
02471 
02472 /*! @brief Format value for bitfield ENET_TCR_CRCFWD. */
02473 #define BF_ENET_TCR_CRCFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCR_CRCFWD) & BM_ENET_TCR_CRCFWD)
02474 
02475 /*! @brief Set the CRCFWD field to a new value. */
02476 #define BW_ENET_TCR_CRCFWD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCR_ADDR(x), BP_ENET_TCR_CRCFWD), v))
02477 /*@}*/
02478 
02479 /*******************************************************************************
02480  * HW_ENET_PALR - Physical Address Lower Register
02481  ******************************************************************************/
02482 
02483 /*!
02484  * @brief HW_ENET_PALR - Physical Address Lower Register (RW)
02485  *
02486  * Reset value: 0x00000000U
02487  *
02488  * PALR contains the lower 32 bits (bytes 0, 1, 2, 3) of the 48-bit address used
02489  * in the address recognition process to compare with the destination address
02490  * (DA) field of receive frames with an individual DA. In addition, this register
02491  * is used in bytes 0 through 3 of the six-byte source address field when
02492  * transmitting PAUSE frames. This register is not reset and you must initialize it.
02493  */
02494 typedef union _hw_enet_palr
02495 {
02496     uint32_t U;
02497     struct _hw_enet_palr_bitfields
02498     {
02499         uint32_t PADDR1 : 32;          /*!< [31:0] Pause Address */
02500     } B;
02501 } hw_enet_palr_t;
02502 
02503 /*!
02504  * @name Constants and macros for entire ENET_PALR register
02505  */
02506 /*@{*/
02507 #define HW_ENET_PALR_ADDR(x)     ((x) + 0xE4U)
02508 
02509 #define HW_ENET_PALR(x)          (*(__IO hw_enet_palr_t *) HW_ENET_PALR_ADDR(x))
02510 #define HW_ENET_PALR_RD(x)       (ADDRESS_READ(hw_enet_palr_t, HW_ENET_PALR_ADDR(x)))
02511 #define HW_ENET_PALR_WR(x, v)    (ADDRESS_WRITE(hw_enet_palr_t, HW_ENET_PALR_ADDR(x), v))
02512 #define HW_ENET_PALR_SET(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) |  (v)))
02513 #define HW_ENET_PALR_CLR(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) & ~(v)))
02514 #define HW_ENET_PALR_TOG(x, v)   (HW_ENET_PALR_WR(x, HW_ENET_PALR_RD(x) ^  (v)))
02515 /*@}*/
02516 
02517 /*
02518  * Constants & macros for individual ENET_PALR bitfields
02519  */
02520 
02521 /*!
02522  * @name Register ENET_PALR, field PADDR1[31:0] (RW)
02523  *
02524  * Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the
02525  * 6-byte individual address are used for exact match and the source address
02526  * field in PAUSE frames.
02527  */
02528 /*@{*/
02529 #define BP_ENET_PALR_PADDR1  (0U)          /*!< Bit position for ENET_PALR_PADDR1. */
02530 #define BM_ENET_PALR_PADDR1  (0xFFFFFFFFU) /*!< Bit mask for ENET_PALR_PADDR1. */
02531 #define BS_ENET_PALR_PADDR1  (32U)         /*!< Bit field size in bits for ENET_PALR_PADDR1. */
02532 
02533 /*! @brief Read current value of the ENET_PALR_PADDR1 field. */
02534 #define BR_ENET_PALR_PADDR1(x) (HW_ENET_PALR(x).U)
02535 
02536 /*! @brief Format value for bitfield ENET_PALR_PADDR1. */
02537 #define BF_ENET_PALR_PADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PALR_PADDR1) & BM_ENET_PALR_PADDR1)
02538 
02539 /*! @brief Set the PADDR1 field to a new value. */
02540 #define BW_ENET_PALR_PADDR1(x, v) (HW_ENET_PALR_WR(x, v))
02541 /*@}*/
02542 
02543 /*******************************************************************************
02544  * HW_ENET_PAUR - Physical Address Upper Register
02545  ******************************************************************************/
02546 
02547 /*!
02548  * @brief HW_ENET_PAUR - Physical Address Upper Register (RW)
02549  *
02550  * Reset value: 0x00008808U
02551  *
02552  * PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in
02553  * the address recognition process to compare with the destination address (DA)
02554  * field of receive frames with an individual DA. In addition, this register is
02555  * used in bytes 4 and 5 of the six-byte source address field when transmitting
02556  * PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for
02557  * transmission of PAUSE frames. The upper 16 bits of this register are not reset and
02558  * you must initialize it.
02559  */
02560 typedef union _hw_enet_paur
02561 {
02562     uint32_t U;
02563     struct _hw_enet_paur_bitfields
02564     {
02565         uint32_t TYPE : 16;            /*!< [15:0] Type Field In PAUSE Frames */
02566         uint32_t PADDR2 : 16;          /*!< [31:16]  */
02567     } B;
02568 } hw_enet_paur_t;
02569 
02570 /*!
02571  * @name Constants and macros for entire ENET_PAUR register
02572  */
02573 /*@{*/
02574 #define HW_ENET_PAUR_ADDR(x)     ((x) + 0xE8U)
02575 
02576 #define HW_ENET_PAUR(x)          (*(__IO hw_enet_paur_t *) HW_ENET_PAUR_ADDR(x))
02577 #define HW_ENET_PAUR_RD(x)       (ADDRESS_READ(hw_enet_paur_t, HW_ENET_PAUR_ADDR(x)))
02578 #define HW_ENET_PAUR_WR(x, v)    (ADDRESS_WRITE(hw_enet_paur_t, HW_ENET_PAUR_ADDR(x), v))
02579 #define HW_ENET_PAUR_SET(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) |  (v)))
02580 #define HW_ENET_PAUR_CLR(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) & ~(v)))
02581 #define HW_ENET_PAUR_TOG(x, v)   (HW_ENET_PAUR_WR(x, HW_ENET_PAUR_RD(x) ^  (v)))
02582 /*@}*/
02583 
02584 /*
02585  * Constants & macros for individual ENET_PAUR bitfields
02586  */
02587 
02588 /*!
02589  * @name Register ENET_PAUR, field TYPE[15:0] (RO)
02590  *
02591  * These fields have a constant value of 0x8808.
02592  */
02593 /*@{*/
02594 #define BP_ENET_PAUR_TYPE    (0U)          /*!< Bit position for ENET_PAUR_TYPE. */
02595 #define BM_ENET_PAUR_TYPE    (0x0000FFFFU) /*!< Bit mask for ENET_PAUR_TYPE. */
02596 #define BS_ENET_PAUR_TYPE    (16U)         /*!< Bit field size in bits for ENET_PAUR_TYPE. */
02597 
02598 /*! @brief Read current value of the ENET_PAUR_TYPE field. */
02599 #define BR_ENET_PAUR_TYPE(x) (UNION_READ(hw_enet_paur_t, HW_ENET_PAUR_ADDR(x), U, B.TYPE))
02600 /*@}*/
02601 
02602 /*!
02603  * @name Register ENET_PAUR, field PADDR2[31:16] (RW)
02604  *
02605  * Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used
02606  * for exact match, and the source address field in PAUSE frames.
02607  */
02608 /*@{*/
02609 #define BP_ENET_PAUR_PADDR2  (16U)         /*!< Bit position for ENET_PAUR_PADDR2. */
02610 #define BM_ENET_PAUR_PADDR2  (0xFFFF0000U) /*!< Bit mask for ENET_PAUR_PADDR2. */
02611 #define BS_ENET_PAUR_PADDR2  (16U)         /*!< Bit field size in bits for ENET_PAUR_PADDR2. */
02612 
02613 /*! @brief Read current value of the ENET_PAUR_PADDR2 field. */
02614 #define BR_ENET_PAUR_PADDR2(x) (UNION_READ(hw_enet_paur_t, HW_ENET_PAUR_ADDR(x), U, B.PADDR2))
02615 
02616 /*! @brief Format value for bitfield ENET_PAUR_PADDR2. */
02617 #define BF_ENET_PAUR_PADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_PAUR_PADDR2) & BM_ENET_PAUR_PADDR2)
02618 
02619 /*! @brief Set the PADDR2 field to a new value. */
02620 #define BW_ENET_PAUR_PADDR2(x, v) (HW_ENET_PAUR_WR(x, (HW_ENET_PAUR_RD(x) & ~BM_ENET_PAUR_PADDR2) | BF_ENET_PAUR_PADDR2(v)))
02621 /*@}*/
02622 
02623 /*******************************************************************************
02624  * HW_ENET_OPD - Opcode/Pause Duration Register
02625  ******************************************************************************/
02626 
02627 /*!
02628  * @brief HW_ENET_OPD - Opcode/Pause Duration Register (RW)
02629  *
02630  * Reset value: 0x00010000U
02631  *
02632  * OPD is read/write accessible. This register contains the 16-bit opcode and
02633  * 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode
02634  * field is a constant value, 0x0001. When another node detects a PAUSE frame,
02635  * that node pauses transmission for the duration specified in the pause duration
02636  * field. The lower 16 bits of this register are not reset and you must initialize
02637  * it.
02638  */
02639 typedef union _hw_enet_opd
02640 {
02641     uint32_t U;
02642     struct _hw_enet_opd_bitfields
02643     {
02644         uint32_t PAUSE_DUR : 16;       /*!< [15:0] Pause Duration */
02645         uint32_t OPCODE : 16;          /*!< [31:16] Opcode Field In PAUSE Frames */
02646     } B;
02647 } hw_enet_opd_t;
02648 
02649 /*!
02650  * @name Constants and macros for entire ENET_OPD register
02651  */
02652 /*@{*/
02653 #define HW_ENET_OPD_ADDR(x)      ((x) + 0xECU)
02654 
02655 #define HW_ENET_OPD(x)           (*(__IO hw_enet_opd_t *) HW_ENET_OPD_ADDR(x))
02656 #define HW_ENET_OPD_RD(x)        (ADDRESS_READ(hw_enet_opd_t, HW_ENET_OPD_ADDR(x)))
02657 #define HW_ENET_OPD_WR(x, v)     (ADDRESS_WRITE(hw_enet_opd_t, HW_ENET_OPD_ADDR(x), v))
02658 #define HW_ENET_OPD_SET(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) |  (v)))
02659 #define HW_ENET_OPD_CLR(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) & ~(v)))
02660 #define HW_ENET_OPD_TOG(x, v)    (HW_ENET_OPD_WR(x, HW_ENET_OPD_RD(x) ^  (v)))
02661 /*@}*/
02662 
02663 /*
02664  * Constants & macros for individual ENET_OPD bitfields
02665  */
02666 
02667 /*!
02668  * @name Register ENET_OPD, field PAUSE_DUR[15:0] (RW)
02669  *
02670  * Pause duration field used in PAUSE frames.
02671  */
02672 /*@{*/
02673 #define BP_ENET_OPD_PAUSE_DUR (0U)         /*!< Bit position for ENET_OPD_PAUSE_DUR. */
02674 #define BM_ENET_OPD_PAUSE_DUR (0x0000FFFFU) /*!< Bit mask for ENET_OPD_PAUSE_DUR. */
02675 #define BS_ENET_OPD_PAUSE_DUR (16U)        /*!< Bit field size in bits for ENET_OPD_PAUSE_DUR. */
02676 
02677 /*! @brief Read current value of the ENET_OPD_PAUSE_DUR field. */
02678 #define BR_ENET_OPD_PAUSE_DUR(x) (UNION_READ(hw_enet_opd_t, HW_ENET_OPD_ADDR(x), U, B.PAUSE_DUR))
02679 
02680 /*! @brief Format value for bitfield ENET_OPD_PAUSE_DUR. */
02681 #define BF_ENET_OPD_PAUSE_DUR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_OPD_PAUSE_DUR) & BM_ENET_OPD_PAUSE_DUR)
02682 
02683 /*! @brief Set the PAUSE_DUR field to a new value. */
02684 #define BW_ENET_OPD_PAUSE_DUR(x, v) (HW_ENET_OPD_WR(x, (HW_ENET_OPD_RD(x) & ~BM_ENET_OPD_PAUSE_DUR) | BF_ENET_OPD_PAUSE_DUR(v)))
02685 /*@}*/
02686 
02687 /*!
02688  * @name Register ENET_OPD, field OPCODE[31:16] (RO)
02689  *
02690  * These fields have a constant value of 0x0001.
02691  */
02692 /*@{*/
02693 #define BP_ENET_OPD_OPCODE   (16U)         /*!< Bit position for ENET_OPD_OPCODE. */
02694 #define BM_ENET_OPD_OPCODE   (0xFFFF0000U) /*!< Bit mask for ENET_OPD_OPCODE. */
02695 #define BS_ENET_OPD_OPCODE   (16U)         /*!< Bit field size in bits for ENET_OPD_OPCODE. */
02696 
02697 /*! @brief Read current value of the ENET_OPD_OPCODE field. */
02698 #define BR_ENET_OPD_OPCODE(x) (UNION_READ(hw_enet_opd_t, HW_ENET_OPD_ADDR(x), U, B.OPCODE))
02699 /*@}*/
02700 
02701 /*******************************************************************************
02702  * HW_ENET_IAUR - Descriptor Individual Upper Address Register
02703  ******************************************************************************/
02704 
02705 /*!
02706  * @brief HW_ENET_IAUR - Descriptor Individual Upper Address Register (RW)
02707  *
02708  * Reset value: 0x00000000U
02709  *
02710  * IAUR contains the upper 32 bits of the 64-bit individual address hash table.
02711  * The address recognition process uses this table to check for a possible match
02712  * with the destination address (DA) field of receive frames with an individual
02713  * DA. This register is not reset and you must initialize it.
02714  */
02715 typedef union _hw_enet_iaur
02716 {
02717     uint32_t U;
02718     struct _hw_enet_iaur_bitfields
02719     {
02720         uint32_t IADDR1 : 32;          /*!< [31:0]  */
02721     } B;
02722 } hw_enet_iaur_t;
02723 
02724 /*!
02725  * @name Constants and macros for entire ENET_IAUR register
02726  */
02727 /*@{*/
02728 #define HW_ENET_IAUR_ADDR(x)     ((x) + 0x118U)
02729 
02730 #define HW_ENET_IAUR(x)          (*(__IO hw_enet_iaur_t *) HW_ENET_IAUR_ADDR(x))
02731 #define HW_ENET_IAUR_RD(x)       (ADDRESS_READ(hw_enet_iaur_t, HW_ENET_IAUR_ADDR(x)))
02732 #define HW_ENET_IAUR_WR(x, v)    (ADDRESS_WRITE(hw_enet_iaur_t, HW_ENET_IAUR_ADDR(x), v))
02733 #define HW_ENET_IAUR_SET(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) |  (v)))
02734 #define HW_ENET_IAUR_CLR(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) & ~(v)))
02735 #define HW_ENET_IAUR_TOG(x, v)   (HW_ENET_IAUR_WR(x, HW_ENET_IAUR_RD(x) ^  (v)))
02736 /*@}*/
02737 
02738 /*
02739  * Constants & macros for individual ENET_IAUR bitfields
02740  */
02741 
02742 /*!
02743  * @name Register ENET_IAUR, field IADDR1[31:0] (RW)
02744  *
02745  * Contains the upper 32 bits of the 64-bit hash table used in the address
02746  * recognition process for receive frames with a unicast address. Bit 31 of IADDR1
02747  * contains hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
02748  */
02749 /*@{*/
02750 #define BP_ENET_IAUR_IADDR1  (0U)          /*!< Bit position for ENET_IAUR_IADDR1. */
02751 #define BM_ENET_IAUR_IADDR1  (0xFFFFFFFFU) /*!< Bit mask for ENET_IAUR_IADDR1. */
02752 #define BS_ENET_IAUR_IADDR1  (32U)         /*!< Bit field size in bits for ENET_IAUR_IADDR1. */
02753 
02754 /*! @brief Read current value of the ENET_IAUR_IADDR1 field. */
02755 #define BR_ENET_IAUR_IADDR1(x) (HW_ENET_IAUR(x).U)
02756 
02757 /*! @brief Format value for bitfield ENET_IAUR_IADDR1. */
02758 #define BF_ENET_IAUR_IADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IAUR_IADDR1) & BM_ENET_IAUR_IADDR1)
02759 
02760 /*! @brief Set the IADDR1 field to a new value. */
02761 #define BW_ENET_IAUR_IADDR1(x, v) (HW_ENET_IAUR_WR(x, v))
02762 /*@}*/
02763 
02764 /*******************************************************************************
02765  * HW_ENET_IALR - Descriptor Individual Lower Address Register
02766  ******************************************************************************/
02767 
02768 /*!
02769  * @brief HW_ENET_IALR - Descriptor Individual Lower Address Register (RW)
02770  *
02771  * Reset value: 0x00000000U
02772  *
02773  * IALR contains the lower 32 bits of the 64-bit individual address hash table.
02774  * The address recognition process uses this table to check for a possible match
02775  * with the DA field of receive frames with an individual DA. This register is
02776  * not reset and you must initialize it.
02777  */
02778 typedef union _hw_enet_ialr
02779 {
02780     uint32_t U;
02781     struct _hw_enet_ialr_bitfields
02782     {
02783         uint32_t IADDR2 : 32;          /*!< [31:0]  */
02784     } B;
02785 } hw_enet_ialr_t;
02786 
02787 /*!
02788  * @name Constants and macros for entire ENET_IALR register
02789  */
02790 /*@{*/
02791 #define HW_ENET_IALR_ADDR(x)     ((x) + 0x11CU)
02792 
02793 #define HW_ENET_IALR(x)          (*(__IO hw_enet_ialr_t *) HW_ENET_IALR_ADDR(x))
02794 #define HW_ENET_IALR_RD(x)       (ADDRESS_READ(hw_enet_ialr_t, HW_ENET_IALR_ADDR(x)))
02795 #define HW_ENET_IALR_WR(x, v)    (ADDRESS_WRITE(hw_enet_ialr_t, HW_ENET_IALR_ADDR(x), v))
02796 #define HW_ENET_IALR_SET(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) |  (v)))
02797 #define HW_ENET_IALR_CLR(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) & ~(v)))
02798 #define HW_ENET_IALR_TOG(x, v)   (HW_ENET_IALR_WR(x, HW_ENET_IALR_RD(x) ^  (v)))
02799 /*@}*/
02800 
02801 /*
02802  * Constants & macros for individual ENET_IALR bitfields
02803  */
02804 
02805 /*!
02806  * @name Register ENET_IALR, field IADDR2[31:0] (RW)
02807  *
02808  * Contains the lower 32 bits of the 64-bit hash table used in the address
02809  * recognition process for receive frames with a unicast address. Bit 31 of IADDR2
02810  * contains hash index bit 31. Bit 0 of IADDR2 contains hash index bit 0.
02811  */
02812 /*@{*/
02813 #define BP_ENET_IALR_IADDR2  (0U)          /*!< Bit position for ENET_IALR_IADDR2. */
02814 #define BM_ENET_IALR_IADDR2  (0xFFFFFFFFU) /*!< Bit mask for ENET_IALR_IADDR2. */
02815 #define BS_ENET_IALR_IADDR2  (32U)         /*!< Bit field size in bits for ENET_IALR_IADDR2. */
02816 
02817 /*! @brief Read current value of the ENET_IALR_IADDR2 field. */
02818 #define BR_ENET_IALR_IADDR2(x) (HW_ENET_IALR(x).U)
02819 
02820 /*! @brief Format value for bitfield ENET_IALR_IADDR2. */
02821 #define BF_ENET_IALR_IADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_IALR_IADDR2) & BM_ENET_IALR_IADDR2)
02822 
02823 /*! @brief Set the IADDR2 field to a new value. */
02824 #define BW_ENET_IALR_IADDR2(x, v) (HW_ENET_IALR_WR(x, v))
02825 /*@}*/
02826 
02827 /*******************************************************************************
02828  * HW_ENET_GAUR - Descriptor Group Upper Address Register
02829  ******************************************************************************/
02830 
02831 /*!
02832  * @brief HW_ENET_GAUR - Descriptor Group Upper Address Register (RW)
02833  *
02834  * Reset value: 0x00000000U
02835  *
02836  * GAUR contains the upper 32 bits of the 64-bit hash table used in the address
02837  * recognition process for receive frames with a multicast address. You must
02838  * initialize this register.
02839  */
02840 typedef union _hw_enet_gaur
02841 {
02842     uint32_t U;
02843     struct _hw_enet_gaur_bitfields
02844     {
02845         uint32_t GADDR1 : 32;          /*!< [31:0]  */
02846     } B;
02847 } hw_enet_gaur_t;
02848 
02849 /*!
02850  * @name Constants and macros for entire ENET_GAUR register
02851  */
02852 /*@{*/
02853 #define HW_ENET_GAUR_ADDR(x)     ((x) + 0x120U)
02854 
02855 #define HW_ENET_GAUR(x)          (*(__IO hw_enet_gaur_t *) HW_ENET_GAUR_ADDR(x))
02856 #define HW_ENET_GAUR_RD(x)       (ADDRESS_READ(hw_enet_gaur_t, HW_ENET_GAUR_ADDR(x)))
02857 #define HW_ENET_GAUR_WR(x, v)    (ADDRESS_WRITE(hw_enet_gaur_t, HW_ENET_GAUR_ADDR(x), v))
02858 #define HW_ENET_GAUR_SET(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) |  (v)))
02859 #define HW_ENET_GAUR_CLR(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) & ~(v)))
02860 #define HW_ENET_GAUR_TOG(x, v)   (HW_ENET_GAUR_WR(x, HW_ENET_GAUR_RD(x) ^  (v)))
02861 /*@}*/
02862 
02863 /*
02864  * Constants & macros for individual ENET_GAUR bitfields
02865  */
02866 
02867 /*!
02868  * @name Register ENET_GAUR, field GADDR1[31:0] (RW)
02869  *
02870  * Contains the upper 32 bits of the 64-bit hash table used in the address
02871  * recognition process for receive frames with a multicast address. Bit 31 of GADDR1
02872  * contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.
02873  */
02874 /*@{*/
02875 #define BP_ENET_GAUR_GADDR1  (0U)          /*!< Bit position for ENET_GAUR_GADDR1. */
02876 #define BM_ENET_GAUR_GADDR1  (0xFFFFFFFFU) /*!< Bit mask for ENET_GAUR_GADDR1. */
02877 #define BS_ENET_GAUR_GADDR1  (32U)         /*!< Bit field size in bits for ENET_GAUR_GADDR1. */
02878 
02879 /*! @brief Read current value of the ENET_GAUR_GADDR1 field. */
02880 #define BR_ENET_GAUR_GADDR1(x) (HW_ENET_GAUR(x).U)
02881 
02882 /*! @brief Format value for bitfield ENET_GAUR_GADDR1. */
02883 #define BF_ENET_GAUR_GADDR1(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GAUR_GADDR1) & BM_ENET_GAUR_GADDR1)
02884 
02885 /*! @brief Set the GADDR1 field to a new value. */
02886 #define BW_ENET_GAUR_GADDR1(x, v) (HW_ENET_GAUR_WR(x, v))
02887 /*@}*/
02888 
02889 /*******************************************************************************
02890  * HW_ENET_GALR - Descriptor Group Lower Address Register
02891  ******************************************************************************/
02892 
02893 /*!
02894  * @brief HW_ENET_GALR - Descriptor Group Lower Address Register (RW)
02895  *
02896  * Reset value: 0x00000000U
02897  *
02898  * GALR contains the lower 32 bits of the 64-bit hash table used in the address
02899  * recognition process for receive frames with a multicast address. You must
02900  * initialize this register.
02901  */
02902 typedef union _hw_enet_galr
02903 {
02904     uint32_t U;
02905     struct _hw_enet_galr_bitfields
02906     {
02907         uint32_t GADDR2 : 32;          /*!< [31:0]  */
02908     } B;
02909 } hw_enet_galr_t;
02910 
02911 /*!
02912  * @name Constants and macros for entire ENET_GALR register
02913  */
02914 /*@{*/
02915 #define HW_ENET_GALR_ADDR(x)     ((x) + 0x124U)
02916 
02917 #define HW_ENET_GALR(x)          (*(__IO hw_enet_galr_t *) HW_ENET_GALR_ADDR(x))
02918 #define HW_ENET_GALR_RD(x)       (ADDRESS_READ(hw_enet_galr_t, HW_ENET_GALR_ADDR(x)))
02919 #define HW_ENET_GALR_WR(x, v)    (ADDRESS_WRITE(hw_enet_galr_t, HW_ENET_GALR_ADDR(x), v))
02920 #define HW_ENET_GALR_SET(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) |  (v)))
02921 #define HW_ENET_GALR_CLR(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) & ~(v)))
02922 #define HW_ENET_GALR_TOG(x, v)   (HW_ENET_GALR_WR(x, HW_ENET_GALR_RD(x) ^  (v)))
02923 /*@}*/
02924 
02925 /*
02926  * Constants & macros for individual ENET_GALR bitfields
02927  */
02928 
02929 /*!
02930  * @name Register ENET_GALR, field GADDR2[31:0] (RW)
02931  *
02932  * Contains the lower 32 bits of the 64-bit hash table used in the address
02933  * recognition process for receive frames with a multicast address. Bit 31 of GADDR2
02934  * contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.
02935  */
02936 /*@{*/
02937 #define BP_ENET_GALR_GADDR2  (0U)          /*!< Bit position for ENET_GALR_GADDR2. */
02938 #define BM_ENET_GALR_GADDR2  (0xFFFFFFFFU) /*!< Bit mask for ENET_GALR_GADDR2. */
02939 #define BS_ENET_GALR_GADDR2  (32U)         /*!< Bit field size in bits for ENET_GALR_GADDR2. */
02940 
02941 /*! @brief Read current value of the ENET_GALR_GADDR2 field. */
02942 #define BR_ENET_GALR_GADDR2(x) (HW_ENET_GALR(x).U)
02943 
02944 /*! @brief Format value for bitfield ENET_GALR_GADDR2. */
02945 #define BF_ENET_GALR_GADDR2(v) ((uint32_t)((uint32_t)(v) << BP_ENET_GALR_GADDR2) & BM_ENET_GALR_GADDR2)
02946 
02947 /*! @brief Set the GADDR2 field to a new value. */
02948 #define BW_ENET_GALR_GADDR2(x, v) (HW_ENET_GALR_WR(x, v))
02949 /*@}*/
02950 
02951 /*******************************************************************************
02952  * HW_ENET_TFWR - Transmit FIFO Watermark Register
02953  ******************************************************************************/
02954 
02955 /*!
02956  * @brief HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)
02957  *
02958  * Reset value: 0x00000000U
02959  *
02960  * If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required
02961  * in the transmit FIFO before transmission of a frame can begin. This allows you
02962  * to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access
02963  * latency (TFWR = 11) due to contention for the system bus. Setting the
02964  * watermark to a high value minimizes the risk of transmit FIFO underrun due to
02965  * contention for the system bus. The byte counts associated with the TFWR field may need
02966  * to be modified to match a given system requirement. For example, worst case
02967  * bus access latency by the transmit data DMA channel. When the FIFO level
02968  * reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC
02969  * transmit control logic starts frame transmission even before the end-of-frame is
02970  * available in the FIFO (cut-through operation). If a complete frame has a size
02971  * smaller than the threshold programmed with TFWR, the MAC also transmits the Frame
02972  * to the line. To enable store and forward on the Transmit path, set STR_FWD to
02973  * '1'. In this case, the MAC starts to transmit data only when a complete frame
02974  * is stored in the Transmit FIFO.
02975  */
02976 typedef union _hw_enet_tfwr
02977 {
02978     uint32_t U;
02979     struct _hw_enet_tfwr_bitfields
02980     {
02981         uint32_t TFWR : 6;             /*!< [5:0] Transmit FIFO Write */
02982         uint32_t RESERVED0 : 2;        /*!< [7:6]  */
02983         uint32_t STRFWD : 1;           /*!< [8] Store And Forward Enable */
02984         uint32_t RESERVED1 : 23;       /*!< [31:9]  */
02985     } B;
02986 } hw_enet_tfwr_t;
02987 
02988 /*!
02989  * @name Constants and macros for entire ENET_TFWR register
02990  */
02991 /*@{*/
02992 #define HW_ENET_TFWR_ADDR(x)     ((x) + 0x144U)
02993 
02994 #define HW_ENET_TFWR(x)          (*(__IO hw_enet_tfwr_t *) HW_ENET_TFWR_ADDR(x))
02995 #define HW_ENET_TFWR_RD(x)       (ADDRESS_READ(hw_enet_tfwr_t, HW_ENET_TFWR_ADDR(x)))
02996 #define HW_ENET_TFWR_WR(x, v)    (ADDRESS_WRITE(hw_enet_tfwr_t, HW_ENET_TFWR_ADDR(x), v))
02997 #define HW_ENET_TFWR_SET(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) |  (v)))
02998 #define HW_ENET_TFWR_CLR(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) & ~(v)))
02999 #define HW_ENET_TFWR_TOG(x, v)   (HW_ENET_TFWR_WR(x, HW_ENET_TFWR_RD(x) ^  (v)))
03000 /*@}*/
03001 
03002 /*
03003  * Constants & macros for individual ENET_TFWR bitfields
03004  */
03005 
03006 /*!
03007  * @name Register ENET_TFWR, field TFWR[5:0] (RW)
03008  *
03009  * If TFWR[STRFWD] is cleared, this field indicates the number of bytes, in
03010  * steps of 64 bytes, written to the transmit FIFO before transmission of a frame
03011  * begins. If a frame with less than the threshold is written, it is still sent
03012  * independently of this threshold setting. The threshold is relevant only if the
03013  * frame is larger than the threshold given. This chip may not support the maximum
03014  * number of bytes written shown below. See the chip-specific information for the
03015  * ENET module for this value.
03016  *
03017  * Values:
03018  * - 000000 - 64 bytes written.
03019  * - 000001 - 64 bytes written.
03020  * - 000010 - 128 bytes written.
03021  * - 000011 - 192 bytes written.
03022  * - 111110 - 3968 bytes written.
03023  * - 111111 - 4032 bytes written.
03024  */
03025 /*@{*/
03026 #define BP_ENET_TFWR_TFWR    (0U)          /*!< Bit position for ENET_TFWR_TFWR. */
03027 #define BM_ENET_TFWR_TFWR    (0x0000003FU) /*!< Bit mask for ENET_TFWR_TFWR. */
03028 #define BS_ENET_TFWR_TFWR    (6U)          /*!< Bit field size in bits for ENET_TFWR_TFWR. */
03029 
03030 /*! @brief Read current value of the ENET_TFWR_TFWR field. */
03031 #define BR_ENET_TFWR_TFWR(x) (UNION_READ(hw_enet_tfwr_t, HW_ENET_TFWR_ADDR(x), U, B.TFWR))
03032 
03033 /*! @brief Format value for bitfield ENET_TFWR_TFWR. */
03034 #define BF_ENET_TFWR_TFWR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_TFWR) & BM_ENET_TFWR_TFWR)
03035 
03036 /*! @brief Set the TFWR field to a new value. */
03037 #define BW_ENET_TFWR_TFWR(x, v) (HW_ENET_TFWR_WR(x, (HW_ENET_TFWR_RD(x) & ~BM_ENET_TFWR_TFWR) | BF_ENET_TFWR_TFWR(v)))
03038 /*@}*/
03039 
03040 /*!
03041  * @name Register ENET_TFWR, field STRFWD[8] (RW)
03042  *
03043  * Values:
03044  * - 0 - Reset. The transmission start threshold is programmed in TFWR[TFWR].
03045  * - 1 - Enabled.
03046  */
03047 /*@{*/
03048 #define BP_ENET_TFWR_STRFWD  (8U)          /*!< Bit position for ENET_TFWR_STRFWD. */
03049 #define BM_ENET_TFWR_STRFWD  (0x00000100U) /*!< Bit mask for ENET_TFWR_STRFWD. */
03050 #define BS_ENET_TFWR_STRFWD  (1U)          /*!< Bit field size in bits for ENET_TFWR_STRFWD. */
03051 
03052 /*! @brief Read current value of the ENET_TFWR_STRFWD field. */
03053 #define BR_ENET_TFWR_STRFWD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD)))
03054 
03055 /*! @brief Format value for bitfield ENET_TFWR_STRFWD. */
03056 #define BF_ENET_TFWR_STRFWD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TFWR_STRFWD) & BM_ENET_TFWR_STRFWD)
03057 
03058 /*! @brief Set the STRFWD field to a new value. */
03059 #define BW_ENET_TFWR_STRFWD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TFWR_ADDR(x), BP_ENET_TFWR_STRFWD), v))
03060 /*@}*/
03061 
03062 /*******************************************************************************
03063  * HW_ENET_RDSR - Receive Descriptor Ring Start Register
03064  ******************************************************************************/
03065 
03066 /*!
03067  * @brief HW_ENET_RDSR - Receive Descriptor Ring Start Register (RW)
03068  *
03069  * Reset value: 0x00000000U
03070  *
03071  * RDSR points to the beginning of the circular receive buffer descriptor queue
03072  * in external memory. This pointer must be 64-bit aligned (bits 2-0 must be
03073  * zero); however, it is recommended to be 128-bit aligned, that is, evenly divisible
03074  * by 16. This register must be initialized prior to operation
03075  */
03076 typedef union _hw_enet_rdsr
03077 {
03078     uint32_t U;
03079     struct _hw_enet_rdsr_bitfields
03080     {
03081         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
03082         uint32_t R_DES_START : 29;     /*!< [31:3]  */
03083     } B;
03084 } hw_enet_rdsr_t;
03085 
03086 /*!
03087  * @name Constants and macros for entire ENET_RDSR register
03088  */
03089 /*@{*/
03090 #define HW_ENET_RDSR_ADDR(x)     ((x) + 0x180U)
03091 
03092 #define HW_ENET_RDSR(x)          (*(__IO hw_enet_rdsr_t *) HW_ENET_RDSR_ADDR(x))
03093 #define HW_ENET_RDSR_RD(x)       (ADDRESS_READ(hw_enet_rdsr_t, HW_ENET_RDSR_ADDR(x)))
03094 #define HW_ENET_RDSR_WR(x, v)    (ADDRESS_WRITE(hw_enet_rdsr_t, HW_ENET_RDSR_ADDR(x), v))
03095 #define HW_ENET_RDSR_SET(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) |  (v)))
03096 #define HW_ENET_RDSR_CLR(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) & ~(v)))
03097 #define HW_ENET_RDSR_TOG(x, v)   (HW_ENET_RDSR_WR(x, HW_ENET_RDSR_RD(x) ^  (v)))
03098 /*@}*/
03099 
03100 /*
03101  * Constants & macros for individual ENET_RDSR bitfields
03102  */
03103 
03104 /*!
03105  * @name Register ENET_RDSR, field R_DES_START[31:3] (RW)
03106  *
03107  * Pointer to the beginning of the receive buffer descriptor queue.
03108  */
03109 /*@{*/
03110 #define BP_ENET_RDSR_R_DES_START (3U)      /*!< Bit position for ENET_RDSR_R_DES_START. */
03111 #define BM_ENET_RDSR_R_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_RDSR_R_DES_START. */
03112 #define BS_ENET_RDSR_R_DES_START (29U)     /*!< Bit field size in bits for ENET_RDSR_R_DES_START. */
03113 
03114 /*! @brief Read current value of the ENET_RDSR_R_DES_START field. */
03115 #define BR_ENET_RDSR_R_DES_START(x) (UNION_READ(hw_enet_rdsr_t, HW_ENET_RDSR_ADDR(x), U, B.R_DES_START))
03116 
03117 /*! @brief Format value for bitfield ENET_RDSR_R_DES_START. */
03118 #define BF_ENET_RDSR_R_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RDSR_R_DES_START) & BM_ENET_RDSR_R_DES_START)
03119 
03120 /*! @brief Set the R_DES_START field to a new value. */
03121 #define BW_ENET_RDSR_R_DES_START(x, v) (HW_ENET_RDSR_WR(x, (HW_ENET_RDSR_RD(x) & ~BM_ENET_RDSR_R_DES_START) | BF_ENET_RDSR_R_DES_START(v)))
03122 /*@}*/
03123 
03124 /*******************************************************************************
03125  * HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register
03126  ******************************************************************************/
03127 
03128 /*!
03129  * @brief HW_ENET_TDSR - Transmit Buffer Descriptor Ring Start Register (RW)
03130  *
03131  * Reset value: 0x00000000U
03132  *
03133  * TDSR provides a pointer to the beginning of the circular transmit buffer
03134  * descriptor queue in external memory. This pointer must be 64-bit aligned (bits 2-0
03135  * must be zero); however, it is recommended to be 128-bit aligned, that is,
03136  * evenly divisible by 16. This register must be initialized prior to operation.
03137  */
03138 typedef union _hw_enet_tdsr
03139 {
03140     uint32_t U;
03141     struct _hw_enet_tdsr_bitfields
03142     {
03143         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
03144         uint32_t X_DES_START : 29;     /*!< [31:3]  */
03145     } B;
03146 } hw_enet_tdsr_t;
03147 
03148 /*!
03149  * @name Constants and macros for entire ENET_TDSR register
03150  */
03151 /*@{*/
03152 #define HW_ENET_TDSR_ADDR(x)     ((x) + 0x184U)
03153 
03154 #define HW_ENET_TDSR(x)          (*(__IO hw_enet_tdsr_t *) HW_ENET_TDSR_ADDR(x))
03155 #define HW_ENET_TDSR_RD(x)       (ADDRESS_READ(hw_enet_tdsr_t, HW_ENET_TDSR_ADDR(x)))
03156 #define HW_ENET_TDSR_WR(x, v)    (ADDRESS_WRITE(hw_enet_tdsr_t, HW_ENET_TDSR_ADDR(x), v))
03157 #define HW_ENET_TDSR_SET(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) |  (v)))
03158 #define HW_ENET_TDSR_CLR(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) & ~(v)))
03159 #define HW_ENET_TDSR_TOG(x, v)   (HW_ENET_TDSR_WR(x, HW_ENET_TDSR_RD(x) ^  (v)))
03160 /*@}*/
03161 
03162 /*
03163  * Constants & macros for individual ENET_TDSR bitfields
03164  */
03165 
03166 /*!
03167  * @name Register ENET_TDSR, field X_DES_START[31:3] (RW)
03168  *
03169  * Pointer to the beginning of the transmit buffer descriptor queue.
03170  */
03171 /*@{*/
03172 #define BP_ENET_TDSR_X_DES_START (3U)      /*!< Bit position for ENET_TDSR_X_DES_START. */
03173 #define BM_ENET_TDSR_X_DES_START (0xFFFFFFF8U) /*!< Bit mask for ENET_TDSR_X_DES_START. */
03174 #define BS_ENET_TDSR_X_DES_START (29U)     /*!< Bit field size in bits for ENET_TDSR_X_DES_START. */
03175 
03176 /*! @brief Read current value of the ENET_TDSR_X_DES_START field. */
03177 #define BR_ENET_TDSR_X_DES_START(x) (UNION_READ(hw_enet_tdsr_t, HW_ENET_TDSR_ADDR(x), U, B.X_DES_START))
03178 
03179 /*! @brief Format value for bitfield ENET_TDSR_X_DES_START. */
03180 #define BF_ENET_TDSR_X_DES_START(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TDSR_X_DES_START) & BM_ENET_TDSR_X_DES_START)
03181 
03182 /*! @brief Set the X_DES_START field to a new value. */
03183 #define BW_ENET_TDSR_X_DES_START(x, v) (HW_ENET_TDSR_WR(x, (HW_ENET_TDSR_RD(x) & ~BM_ENET_TDSR_X_DES_START) | BF_ENET_TDSR_X_DES_START(v)))
03184 /*@}*/
03185 
03186 /*******************************************************************************
03187  * HW_ENET_MRBR - Maximum Receive Buffer Size Register
03188  ******************************************************************************/
03189 
03190 /*!
03191  * @brief HW_ENET_MRBR - Maximum Receive Buffer Size Register (RW)
03192  *
03193  * Reset value: 0x00000000U
03194  *
03195  * The MRBR is a user-programmable register that dictates the maximum size of
03196  * all receive buffers. This value should take into consideration that the receive
03197  * CRC is always written into the last receive buffer. To allow one maximum size
03198  * frame per buffer, MRBR must be set to RCR[MAX_FL] or larger. To properly align
03199  * the buffer, MRBR must be evenly divisible by 16. To ensure this, bits 3-0 are
03200  * set to zero by the device. To minimize bus usage (descriptor fetches), set
03201  * MRBR greater than or equal to 256 bytes. This register must be initialized
03202  * before operation.
03203  */
03204 typedef union _hw_enet_mrbr
03205 {
03206     uint32_t U;
03207     struct _hw_enet_mrbr_bitfields
03208     {
03209         uint32_t RESERVED0 : 4;        /*!< [3:0]  */
03210         uint32_t R_BUF_SIZE : 10;      /*!< [13:4]  */
03211         uint32_t RESERVED1 : 18;       /*!< [31:14]  */
03212     } B;
03213 } hw_enet_mrbr_t;
03214 
03215 /*!
03216  * @name Constants and macros for entire ENET_MRBR register
03217  */
03218 /*@{*/
03219 #define HW_ENET_MRBR_ADDR(x)     ((x) + 0x188U)
03220 
03221 #define HW_ENET_MRBR(x)          (*(__IO hw_enet_mrbr_t *) HW_ENET_MRBR_ADDR(x))
03222 #define HW_ENET_MRBR_RD(x)       (ADDRESS_READ(hw_enet_mrbr_t, HW_ENET_MRBR_ADDR(x)))
03223 #define HW_ENET_MRBR_WR(x, v)    (ADDRESS_WRITE(hw_enet_mrbr_t, HW_ENET_MRBR_ADDR(x), v))
03224 #define HW_ENET_MRBR_SET(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) |  (v)))
03225 #define HW_ENET_MRBR_CLR(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) & ~(v)))
03226 #define HW_ENET_MRBR_TOG(x, v)   (HW_ENET_MRBR_WR(x, HW_ENET_MRBR_RD(x) ^  (v)))
03227 /*@}*/
03228 
03229 /*
03230  * Constants & macros for individual ENET_MRBR bitfields
03231  */
03232 
03233 /*!
03234  * @name Register ENET_MRBR, field R_BUF_SIZE[13:4] (RW)
03235  *
03236  * Receive buffer size in bytes.
03237  */
03238 /*@{*/
03239 #define BP_ENET_MRBR_R_BUF_SIZE (4U)       /*!< Bit position for ENET_MRBR_R_BUF_SIZE. */
03240 #define BM_ENET_MRBR_R_BUF_SIZE (0x00003FF0U) /*!< Bit mask for ENET_MRBR_R_BUF_SIZE. */
03241 #define BS_ENET_MRBR_R_BUF_SIZE (10U)      /*!< Bit field size in bits for ENET_MRBR_R_BUF_SIZE. */
03242 
03243 /*! @brief Read current value of the ENET_MRBR_R_BUF_SIZE field. */
03244 #define BR_ENET_MRBR_R_BUF_SIZE(x) (UNION_READ(hw_enet_mrbr_t, HW_ENET_MRBR_ADDR(x), U, B.R_BUF_SIZE))
03245 
03246 /*! @brief Format value for bitfield ENET_MRBR_R_BUF_SIZE. */
03247 #define BF_ENET_MRBR_R_BUF_SIZE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_MRBR_R_BUF_SIZE) & BM_ENET_MRBR_R_BUF_SIZE)
03248 
03249 /*! @brief Set the R_BUF_SIZE field to a new value. */
03250 #define BW_ENET_MRBR_R_BUF_SIZE(x, v) (HW_ENET_MRBR_WR(x, (HW_ENET_MRBR_RD(x) & ~BM_ENET_MRBR_R_BUF_SIZE) | BF_ENET_MRBR_R_BUF_SIZE(v)))
03251 /*@}*/
03252 
03253 /*******************************************************************************
03254  * HW_ENET_RSFL - Receive FIFO Section Full Threshold
03255  ******************************************************************************/
03256 
03257 /*!
03258  * @brief HW_ENET_RSFL - Receive FIFO Section Full Threshold (RW)
03259  *
03260  * Reset value: 0x00000000U
03261  */
03262 typedef union _hw_enet_rsfl
03263 {
03264     uint32_t U;
03265     struct _hw_enet_rsfl_bitfields
03266     {
03267         uint32_t RX_SECTION_FULL : 8;  /*!< [7:0] Value Of Receive FIFO
03268                                         * Section Full Threshold */
03269         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03270     } B;
03271 } hw_enet_rsfl_t;
03272 
03273 /*!
03274  * @name Constants and macros for entire ENET_RSFL register
03275  */
03276 /*@{*/
03277 #define HW_ENET_RSFL_ADDR(x)     ((x) + 0x190U)
03278 
03279 #define HW_ENET_RSFL(x)          (*(__IO hw_enet_rsfl_t *) HW_ENET_RSFL_ADDR(x))
03280 #define HW_ENET_RSFL_RD(x)       (ADDRESS_READ(hw_enet_rsfl_t, HW_ENET_RSFL_ADDR(x)))
03281 #define HW_ENET_RSFL_WR(x, v)    (ADDRESS_WRITE(hw_enet_rsfl_t, HW_ENET_RSFL_ADDR(x), v))
03282 #define HW_ENET_RSFL_SET(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) |  (v)))
03283 #define HW_ENET_RSFL_CLR(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) & ~(v)))
03284 #define HW_ENET_RSFL_TOG(x, v)   (HW_ENET_RSFL_WR(x, HW_ENET_RSFL_RD(x) ^  (v)))
03285 /*@}*/
03286 
03287 /*
03288  * Constants & macros for individual ENET_RSFL bitfields
03289  */
03290 
03291 /*!
03292  * @name Register ENET_RSFL, field RX_SECTION_FULL[7:0] (RW)
03293  *
03294  * Value, in 64-bit words, of the receive FIFO section full threshold. Clear
03295  * this field to enable store and forward on the RX FIFO. When programming a value
03296  * greater than 0 (cut-through operation), it must be greater than
03297  * RAEM[RX_ALMOST_EMPTY]. When the FIFO level reaches the value in this field, data is available
03298  * in the Receive FIFO (cut-through operation).
03299  */
03300 /*@{*/
03301 #define BP_ENET_RSFL_RX_SECTION_FULL (0U)  /*!< Bit position for ENET_RSFL_RX_SECTION_FULL. */
03302 #define BM_ENET_RSFL_RX_SECTION_FULL (0x000000FFU) /*!< Bit mask for ENET_RSFL_RX_SECTION_FULL. */
03303 #define BS_ENET_RSFL_RX_SECTION_FULL (8U)  /*!< Bit field size in bits for ENET_RSFL_RX_SECTION_FULL. */
03304 
03305 /*! @brief Read current value of the ENET_RSFL_RX_SECTION_FULL field. */
03306 #define BR_ENET_RSFL_RX_SECTION_FULL(x) (UNION_READ(hw_enet_rsfl_t, HW_ENET_RSFL_ADDR(x), U, B.RX_SECTION_FULL))
03307 
03308 /*! @brief Format value for bitfield ENET_RSFL_RX_SECTION_FULL. */
03309 #define BF_ENET_RSFL_RX_SECTION_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSFL_RX_SECTION_FULL) & BM_ENET_RSFL_RX_SECTION_FULL)
03310 
03311 /*! @brief Set the RX_SECTION_FULL field to a new value. */
03312 #define BW_ENET_RSFL_RX_SECTION_FULL(x, v) (HW_ENET_RSFL_WR(x, (HW_ENET_RSFL_RD(x) & ~BM_ENET_RSFL_RX_SECTION_FULL) | BF_ENET_RSFL_RX_SECTION_FULL(v)))
03313 /*@}*/
03314 
03315 /*******************************************************************************
03316  * HW_ENET_RSEM - Receive FIFO Section Empty Threshold
03317  ******************************************************************************/
03318 
03319 /*!
03320  * @brief HW_ENET_RSEM - Receive FIFO Section Empty Threshold (RW)
03321  *
03322  * Reset value: 0x00000000U
03323  */
03324 typedef union _hw_enet_rsem
03325 {
03326     uint32_t U;
03327     struct _hw_enet_rsem_bitfields
03328     {
03329         uint32_t RX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Receive FIFO
03330                                         * Section Empty Threshold */
03331         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
03332         uint32_t STAT_SECTION_EMPTY : 5; /*!< [20:16] RX Status FIFO Section
03333                                         * Empty Threshold */
03334         uint32_t RESERVED1 : 11;       /*!< [31:21]  */
03335     } B;
03336 } hw_enet_rsem_t;
03337 
03338 /*!
03339  * @name Constants and macros for entire ENET_RSEM register
03340  */
03341 /*@{*/
03342 #define HW_ENET_RSEM_ADDR(x)     ((x) + 0x194U)
03343 
03344 #define HW_ENET_RSEM(x)          (*(__IO hw_enet_rsem_t *) HW_ENET_RSEM_ADDR(x))
03345 #define HW_ENET_RSEM_RD(x)       (ADDRESS_READ(hw_enet_rsem_t, HW_ENET_RSEM_ADDR(x)))
03346 #define HW_ENET_RSEM_WR(x, v)    (ADDRESS_WRITE(hw_enet_rsem_t, HW_ENET_RSEM_ADDR(x), v))
03347 #define HW_ENET_RSEM_SET(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) |  (v)))
03348 #define HW_ENET_RSEM_CLR(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) & ~(v)))
03349 #define HW_ENET_RSEM_TOG(x, v)   (HW_ENET_RSEM_WR(x, HW_ENET_RSEM_RD(x) ^  (v)))
03350 /*@}*/
03351 
03352 /*
03353  * Constants & macros for individual ENET_RSEM bitfields
03354  */
03355 
03356 /*!
03357  * @name Register ENET_RSEM, field RX_SECTION_EMPTY[7:0] (RW)
03358  *
03359  * Value, in 64-bit words, of the receive FIFO section empty threshold. When the
03360  * FIFO has reached this level, a pause frame will be issued. A value of 0
03361  * disables automatic pause frame generation. When the FIFO level goes below the value
03362  * programmed in this field, an XON pause frame is issued to indicate the FIFO
03363  * congestion is cleared to the remote Ethernet client. The section-empty
03364  * threshold indications from both FIFOs are OR'ed to cause XOFF pause frame generation.
03365  */
03366 /*@{*/
03367 #define BP_ENET_RSEM_RX_SECTION_EMPTY (0U) /*!< Bit position for ENET_RSEM_RX_SECTION_EMPTY. */
03368 #define BM_ENET_RSEM_RX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RSEM_RX_SECTION_EMPTY. */
03369 #define BS_ENET_RSEM_RX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_RSEM_RX_SECTION_EMPTY. */
03370 
03371 /*! @brief Read current value of the ENET_RSEM_RX_SECTION_EMPTY field. */
03372 #define BR_ENET_RSEM_RX_SECTION_EMPTY(x) (UNION_READ(hw_enet_rsem_t, HW_ENET_RSEM_ADDR(x), U, B.RX_SECTION_EMPTY))
03373 
03374 /*! @brief Format value for bitfield ENET_RSEM_RX_SECTION_EMPTY. */
03375 #define BF_ENET_RSEM_RX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_RX_SECTION_EMPTY) & BM_ENET_RSEM_RX_SECTION_EMPTY)
03376 
03377 /*! @brief Set the RX_SECTION_EMPTY field to a new value. */
03378 #define BW_ENET_RSEM_RX_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_RX_SECTION_EMPTY) | BF_ENET_RSEM_RX_SECTION_EMPTY(v)))
03379 /*@}*/
03380 
03381 /*!
03382  * @name Register ENET_RSEM, field STAT_SECTION_EMPTY[20:16] (RW)
03383  *
03384  * Defines number of frames in the receive FIFO, independent of its size, that
03385  * can be accepted. If the limit is reached, reception will continue normally,
03386  * however a pause frame will be triggered to indicate a possible congestion to the
03387  * remote device to avoid FIFO overflow. A value of 0 disables automatic pause
03388  * frame generation
03389  */
03390 /*@{*/
03391 #define BP_ENET_RSEM_STAT_SECTION_EMPTY (16U) /*!< Bit position for ENET_RSEM_STAT_SECTION_EMPTY. */
03392 #define BM_ENET_RSEM_STAT_SECTION_EMPTY (0x001F0000U) /*!< Bit mask for ENET_RSEM_STAT_SECTION_EMPTY. */
03393 #define BS_ENET_RSEM_STAT_SECTION_EMPTY (5U) /*!< Bit field size in bits for ENET_RSEM_STAT_SECTION_EMPTY. */
03394 
03395 /*! @brief Read current value of the ENET_RSEM_STAT_SECTION_EMPTY field. */
03396 #define BR_ENET_RSEM_STAT_SECTION_EMPTY(x) (UNION_READ(hw_enet_rsem_t, HW_ENET_RSEM_ADDR(x), U, B.STAT_SECTION_EMPTY))
03397 
03398 /*! @brief Format value for bitfield ENET_RSEM_STAT_SECTION_EMPTY. */
03399 #define BF_ENET_RSEM_STAT_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RSEM_STAT_SECTION_EMPTY) & BM_ENET_RSEM_STAT_SECTION_EMPTY)
03400 
03401 /*! @brief Set the STAT_SECTION_EMPTY field to a new value. */
03402 #define BW_ENET_RSEM_STAT_SECTION_EMPTY(x, v) (HW_ENET_RSEM_WR(x, (HW_ENET_RSEM_RD(x) & ~BM_ENET_RSEM_STAT_SECTION_EMPTY) | BF_ENET_RSEM_STAT_SECTION_EMPTY(v)))
03403 /*@}*/
03404 
03405 /*******************************************************************************
03406  * HW_ENET_RAEM - Receive FIFO Almost Empty Threshold
03407  ******************************************************************************/
03408 
03409 /*!
03410  * @brief HW_ENET_RAEM - Receive FIFO Almost Empty Threshold (RW)
03411  *
03412  * Reset value: 0x00000004U
03413  */
03414 typedef union _hw_enet_raem
03415 {
03416     uint32_t U;
03417     struct _hw_enet_raem_bitfields
03418     {
03419         uint32_t RX_ALMOST_EMPTY : 8;  /*!< [7:0] Value Of The Receive FIFO
03420                                         * Almost Empty Threshold */
03421         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03422     } B;
03423 } hw_enet_raem_t;
03424 
03425 /*!
03426  * @name Constants and macros for entire ENET_RAEM register
03427  */
03428 /*@{*/
03429 #define HW_ENET_RAEM_ADDR(x)     ((x) + 0x198U)
03430 
03431 #define HW_ENET_RAEM(x)          (*(__IO hw_enet_raem_t *) HW_ENET_RAEM_ADDR(x))
03432 #define HW_ENET_RAEM_RD(x)       (ADDRESS_READ(hw_enet_raem_t, HW_ENET_RAEM_ADDR(x)))
03433 #define HW_ENET_RAEM_WR(x, v)    (ADDRESS_WRITE(hw_enet_raem_t, HW_ENET_RAEM_ADDR(x), v))
03434 #define HW_ENET_RAEM_SET(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) |  (v)))
03435 #define HW_ENET_RAEM_CLR(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) & ~(v)))
03436 #define HW_ENET_RAEM_TOG(x, v)   (HW_ENET_RAEM_WR(x, HW_ENET_RAEM_RD(x) ^  (v)))
03437 /*@}*/
03438 
03439 /*
03440  * Constants & macros for individual ENET_RAEM bitfields
03441  */
03442 
03443 /*!
03444  * @name Register ENET_RAEM, field RX_ALMOST_EMPTY[7:0] (RW)
03445  *
03446  * Value, in 64-bit words, of the receive FIFO almost empty threshold. When the
03447  * FIFO level reaches the value programmed in this field and the end-of-frame has
03448  * not been received for the frame yet, the core receive read control stops FIFO
03449  * read (and subsequently stops transferring data to the MAC client
03450  * application). It continues to deliver the frame, if again more data than the threshold or
03451  * the end-of-frame is available in the FIFO. A minimum value of 4 should be set.
03452  */
03453 /*@{*/
03454 #define BP_ENET_RAEM_RX_ALMOST_EMPTY (0U)  /*!< Bit position for ENET_RAEM_RX_ALMOST_EMPTY. */
03455 #define BM_ENET_RAEM_RX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_RAEM_RX_ALMOST_EMPTY. */
03456 #define BS_ENET_RAEM_RX_ALMOST_EMPTY (8U)  /*!< Bit field size in bits for ENET_RAEM_RX_ALMOST_EMPTY. */
03457 
03458 /*! @brief Read current value of the ENET_RAEM_RX_ALMOST_EMPTY field. */
03459 #define BR_ENET_RAEM_RX_ALMOST_EMPTY(x) (UNION_READ(hw_enet_raem_t, HW_ENET_RAEM_ADDR(x), U, B.RX_ALMOST_EMPTY))
03460 
03461 /*! @brief Format value for bitfield ENET_RAEM_RX_ALMOST_EMPTY. */
03462 #define BF_ENET_RAEM_RX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAEM_RX_ALMOST_EMPTY) & BM_ENET_RAEM_RX_ALMOST_EMPTY)
03463 
03464 /*! @brief Set the RX_ALMOST_EMPTY field to a new value. */
03465 #define BW_ENET_RAEM_RX_ALMOST_EMPTY(x, v) (HW_ENET_RAEM_WR(x, (HW_ENET_RAEM_RD(x) & ~BM_ENET_RAEM_RX_ALMOST_EMPTY) | BF_ENET_RAEM_RX_ALMOST_EMPTY(v)))
03466 /*@}*/
03467 
03468 /*******************************************************************************
03469  * HW_ENET_RAFL - Receive FIFO Almost Full Threshold
03470  ******************************************************************************/
03471 
03472 /*!
03473  * @brief HW_ENET_RAFL - Receive FIFO Almost Full Threshold (RW)
03474  *
03475  * Reset value: 0x00000004U
03476  */
03477 typedef union _hw_enet_rafl
03478 {
03479     uint32_t U;
03480     struct _hw_enet_rafl_bitfields
03481     {
03482         uint32_t RX_ALMOST_FULL : 8;   /*!< [7:0] Value Of The Receive FIFO
03483                                         * Almost Full Threshold */
03484         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03485     } B;
03486 } hw_enet_rafl_t;
03487 
03488 /*!
03489  * @name Constants and macros for entire ENET_RAFL register
03490  */
03491 /*@{*/
03492 #define HW_ENET_RAFL_ADDR(x)     ((x) + 0x19CU)
03493 
03494 #define HW_ENET_RAFL(x)          (*(__IO hw_enet_rafl_t *) HW_ENET_RAFL_ADDR(x))
03495 #define HW_ENET_RAFL_RD(x)       (ADDRESS_READ(hw_enet_rafl_t, HW_ENET_RAFL_ADDR(x)))
03496 #define HW_ENET_RAFL_WR(x, v)    (ADDRESS_WRITE(hw_enet_rafl_t, HW_ENET_RAFL_ADDR(x), v))
03497 #define HW_ENET_RAFL_SET(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) |  (v)))
03498 #define HW_ENET_RAFL_CLR(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) & ~(v)))
03499 #define HW_ENET_RAFL_TOG(x, v)   (HW_ENET_RAFL_WR(x, HW_ENET_RAFL_RD(x) ^  (v)))
03500 /*@}*/
03501 
03502 /*
03503  * Constants & macros for individual ENET_RAFL bitfields
03504  */
03505 
03506 /*!
03507  * @name Register ENET_RAFL, field RX_ALMOST_FULL[7:0] (RW)
03508  *
03509  * Value, in 64-bit words, of the receive FIFO almost full threshold. When the
03510  * FIFO level comes close to the maximum, so that there is no more space for at
03511  * least RX_ALMOST_FULL number of words, the MAC stops writing data in the FIFO and
03512  * truncates the received frame to avoid FIFO overflow. The corresponding error
03513  * status will be set when the frame is delivered to the application. A minimum
03514  * value of 4 should be set.
03515  */
03516 /*@{*/
03517 #define BP_ENET_RAFL_RX_ALMOST_FULL (0U)   /*!< Bit position for ENET_RAFL_RX_ALMOST_FULL. */
03518 #define BM_ENET_RAFL_RX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_RAFL_RX_ALMOST_FULL. */
03519 #define BS_ENET_RAFL_RX_ALMOST_FULL (8U)   /*!< Bit field size in bits for ENET_RAFL_RX_ALMOST_FULL. */
03520 
03521 /*! @brief Read current value of the ENET_RAFL_RX_ALMOST_FULL field. */
03522 #define BR_ENET_RAFL_RX_ALMOST_FULL(x) (UNION_READ(hw_enet_rafl_t, HW_ENET_RAFL_ADDR(x), U, B.RX_ALMOST_FULL))
03523 
03524 /*! @brief Format value for bitfield ENET_RAFL_RX_ALMOST_FULL. */
03525 #define BF_ENET_RAFL_RX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RAFL_RX_ALMOST_FULL) & BM_ENET_RAFL_RX_ALMOST_FULL)
03526 
03527 /*! @brief Set the RX_ALMOST_FULL field to a new value. */
03528 #define BW_ENET_RAFL_RX_ALMOST_FULL(x, v) (HW_ENET_RAFL_WR(x, (HW_ENET_RAFL_RD(x) & ~BM_ENET_RAFL_RX_ALMOST_FULL) | BF_ENET_RAFL_RX_ALMOST_FULL(v)))
03529 /*@}*/
03530 
03531 /*******************************************************************************
03532  * HW_ENET_TSEM - Transmit FIFO Section Empty Threshold
03533  ******************************************************************************/
03534 
03535 /*!
03536  * @brief HW_ENET_TSEM - Transmit FIFO Section Empty Threshold (RW)
03537  *
03538  * Reset value: 0x00000000U
03539  */
03540 typedef union _hw_enet_tsem
03541 {
03542     uint32_t U;
03543     struct _hw_enet_tsem_bitfields
03544     {
03545         uint32_t TX_SECTION_EMPTY : 8; /*!< [7:0] Value Of The Transmit FIFO
03546                                         * Section Empty Threshold */
03547         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03548     } B;
03549 } hw_enet_tsem_t;
03550 
03551 /*!
03552  * @name Constants and macros for entire ENET_TSEM register
03553  */
03554 /*@{*/
03555 #define HW_ENET_TSEM_ADDR(x)     ((x) + 0x1A0U)
03556 
03557 #define HW_ENET_TSEM(x)          (*(__IO hw_enet_tsem_t *) HW_ENET_TSEM_ADDR(x))
03558 #define HW_ENET_TSEM_RD(x)       (ADDRESS_READ(hw_enet_tsem_t, HW_ENET_TSEM_ADDR(x)))
03559 #define HW_ENET_TSEM_WR(x, v)    (ADDRESS_WRITE(hw_enet_tsem_t, HW_ENET_TSEM_ADDR(x), v))
03560 #define HW_ENET_TSEM_SET(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) |  (v)))
03561 #define HW_ENET_TSEM_CLR(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) & ~(v)))
03562 #define HW_ENET_TSEM_TOG(x, v)   (HW_ENET_TSEM_WR(x, HW_ENET_TSEM_RD(x) ^  (v)))
03563 /*@}*/
03564 
03565 /*
03566  * Constants & macros for individual ENET_TSEM bitfields
03567  */
03568 
03569 /*!
03570  * @name Register ENET_TSEM, field TX_SECTION_EMPTY[7:0] (RW)
03571  *
03572  * Value, in 64-bit words, of the transmit FIFO section empty threshold. See
03573  * Transmit FIFOFour programmable thresholds are available which control the core
03574  * operation. for more information.
03575  */
03576 /*@{*/
03577 #define BP_ENET_TSEM_TX_SECTION_EMPTY (0U) /*!< Bit position for ENET_TSEM_TX_SECTION_EMPTY. */
03578 #define BM_ENET_TSEM_TX_SECTION_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TSEM_TX_SECTION_EMPTY. */
03579 #define BS_ENET_TSEM_TX_SECTION_EMPTY (8U) /*!< Bit field size in bits for ENET_TSEM_TX_SECTION_EMPTY. */
03580 
03581 /*! @brief Read current value of the ENET_TSEM_TX_SECTION_EMPTY field. */
03582 #define BR_ENET_TSEM_TX_SECTION_EMPTY(x) (UNION_READ(hw_enet_tsem_t, HW_ENET_TSEM_ADDR(x), U, B.TX_SECTION_EMPTY))
03583 
03584 /*! @brief Format value for bitfield ENET_TSEM_TX_SECTION_EMPTY. */
03585 #define BF_ENET_TSEM_TX_SECTION_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TSEM_TX_SECTION_EMPTY) & BM_ENET_TSEM_TX_SECTION_EMPTY)
03586 
03587 /*! @brief Set the TX_SECTION_EMPTY field to a new value. */
03588 #define BW_ENET_TSEM_TX_SECTION_EMPTY(x, v) (HW_ENET_TSEM_WR(x, (HW_ENET_TSEM_RD(x) & ~BM_ENET_TSEM_TX_SECTION_EMPTY) | BF_ENET_TSEM_TX_SECTION_EMPTY(v)))
03589 /*@}*/
03590 
03591 /*******************************************************************************
03592  * HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold
03593  ******************************************************************************/
03594 
03595 /*!
03596  * @brief HW_ENET_TAEM - Transmit FIFO Almost Empty Threshold (RW)
03597  *
03598  * Reset value: 0x00000004U
03599  */
03600 typedef union _hw_enet_taem
03601 {
03602     uint32_t U;
03603     struct _hw_enet_taem_bitfields
03604     {
03605         uint32_t TX_ALMOST_EMPTY : 8;  /*!< [7:0] Value of Transmit FIFO
03606                                         * Almost Empty Threshold */
03607         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03608     } B;
03609 } hw_enet_taem_t;
03610 
03611 /*!
03612  * @name Constants and macros for entire ENET_TAEM register
03613  */
03614 /*@{*/
03615 #define HW_ENET_TAEM_ADDR(x)     ((x) + 0x1A4U)
03616 
03617 #define HW_ENET_TAEM(x)          (*(__IO hw_enet_taem_t *) HW_ENET_TAEM_ADDR(x))
03618 #define HW_ENET_TAEM_RD(x)       (ADDRESS_READ(hw_enet_taem_t, HW_ENET_TAEM_ADDR(x)))
03619 #define HW_ENET_TAEM_WR(x, v)    (ADDRESS_WRITE(hw_enet_taem_t, HW_ENET_TAEM_ADDR(x), v))
03620 #define HW_ENET_TAEM_SET(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) |  (v)))
03621 #define HW_ENET_TAEM_CLR(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) & ~(v)))
03622 #define HW_ENET_TAEM_TOG(x, v)   (HW_ENET_TAEM_WR(x, HW_ENET_TAEM_RD(x) ^  (v)))
03623 /*@}*/
03624 
03625 /*
03626  * Constants & macros for individual ENET_TAEM bitfields
03627  */
03628 
03629 /*!
03630  * @name Register ENET_TAEM, field TX_ALMOST_EMPTY[7:0] (RW)
03631  *
03632  * Value, in 64-bit words, of the transmit FIFO almost empty threshold. When the
03633  * FIFO level reaches the value programmed in this field, and no end-of-frame is
03634  * available for the frame, the MAC transmit logic, to avoid FIFO underflow,
03635  * stops reading the FIFO and transmits a frame with an MII error indication. See
03636  * Transmit FIFOFour programmable thresholds are available which control the core
03637  * operation. for more information. A minimum value of 4 should be set.
03638  */
03639 /*@{*/
03640 #define BP_ENET_TAEM_TX_ALMOST_EMPTY (0U)  /*!< Bit position for ENET_TAEM_TX_ALMOST_EMPTY. */
03641 #define BM_ENET_TAEM_TX_ALMOST_EMPTY (0x000000FFU) /*!< Bit mask for ENET_TAEM_TX_ALMOST_EMPTY. */
03642 #define BS_ENET_TAEM_TX_ALMOST_EMPTY (8U)  /*!< Bit field size in bits for ENET_TAEM_TX_ALMOST_EMPTY. */
03643 
03644 /*! @brief Read current value of the ENET_TAEM_TX_ALMOST_EMPTY field. */
03645 #define BR_ENET_TAEM_TX_ALMOST_EMPTY(x) (UNION_READ(hw_enet_taem_t, HW_ENET_TAEM_ADDR(x), U, B.TX_ALMOST_EMPTY))
03646 
03647 /*! @brief Format value for bitfield ENET_TAEM_TX_ALMOST_EMPTY. */
03648 #define BF_ENET_TAEM_TX_ALMOST_EMPTY(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAEM_TX_ALMOST_EMPTY) & BM_ENET_TAEM_TX_ALMOST_EMPTY)
03649 
03650 /*! @brief Set the TX_ALMOST_EMPTY field to a new value. */
03651 #define BW_ENET_TAEM_TX_ALMOST_EMPTY(x, v) (HW_ENET_TAEM_WR(x, (HW_ENET_TAEM_RD(x) & ~BM_ENET_TAEM_TX_ALMOST_EMPTY) | BF_ENET_TAEM_TX_ALMOST_EMPTY(v)))
03652 /*@}*/
03653 
03654 /*******************************************************************************
03655  * HW_ENET_TAFL - Transmit FIFO Almost Full Threshold
03656  ******************************************************************************/
03657 
03658 /*!
03659  * @brief HW_ENET_TAFL - Transmit FIFO Almost Full Threshold (RW)
03660  *
03661  * Reset value: 0x00000008U
03662  */
03663 typedef union _hw_enet_tafl
03664 {
03665     uint32_t U;
03666     struct _hw_enet_tafl_bitfields
03667     {
03668         uint32_t TX_ALMOST_FULL : 8;   /*!< [7:0] Value Of The Transmit FIFO
03669                                         * Almost Full Threshold */
03670         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
03671     } B;
03672 } hw_enet_tafl_t;
03673 
03674 /*!
03675  * @name Constants and macros for entire ENET_TAFL register
03676  */
03677 /*@{*/
03678 #define HW_ENET_TAFL_ADDR(x)     ((x) + 0x1A8U)
03679 
03680 #define HW_ENET_TAFL(x)          (*(__IO hw_enet_tafl_t *) HW_ENET_TAFL_ADDR(x))
03681 #define HW_ENET_TAFL_RD(x)       (ADDRESS_READ(hw_enet_tafl_t, HW_ENET_TAFL_ADDR(x)))
03682 #define HW_ENET_TAFL_WR(x, v)    (ADDRESS_WRITE(hw_enet_tafl_t, HW_ENET_TAFL_ADDR(x), v))
03683 #define HW_ENET_TAFL_SET(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) |  (v)))
03684 #define HW_ENET_TAFL_CLR(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) & ~(v)))
03685 #define HW_ENET_TAFL_TOG(x, v)   (HW_ENET_TAFL_WR(x, HW_ENET_TAFL_RD(x) ^  (v)))
03686 /*@}*/
03687 
03688 /*
03689  * Constants & macros for individual ENET_TAFL bitfields
03690  */
03691 
03692 /*!
03693  * @name Register ENET_TAFL, field TX_ALMOST_FULL[7:0] (RW)
03694  *
03695  * Value, in 64-bit words, of the transmit FIFO almost full threshold. A minimum
03696  * value of six is required . A recommended value of at least 8 should be set
03697  * allowing a latency of two clock cycles to the application. If more latency is
03698  * required the value can be increased as necessary (latency = TAFL - 5). When the
03699  * FIFO level comes close to the maximum, so that there is no more space for at
03700  * least TX_ALMOST_FULL number of words, the pin ff_tx_rdy is deasserted. If the
03701  * application does not react on this signal, the FIFO write control logic, to
03702  * avoid FIFO overflow, truncates the current frame and sets the error status. As a
03703  * result, the frame will be transmitted with an GMII/MII error indication. See
03704  * Transmit FIFOFour programmable thresholds are available which control the core
03705  * operation. for more information. A FIFO overflow is a fatal error and requires
03706  * a global reset on the transmit datapath or at least deassertion of ETHEREN.
03707  */
03708 /*@{*/
03709 #define BP_ENET_TAFL_TX_ALMOST_FULL (0U)   /*!< Bit position for ENET_TAFL_TX_ALMOST_FULL. */
03710 #define BM_ENET_TAFL_TX_ALMOST_FULL (0x000000FFU) /*!< Bit mask for ENET_TAFL_TX_ALMOST_FULL. */
03711 #define BS_ENET_TAFL_TX_ALMOST_FULL (8U)   /*!< Bit field size in bits for ENET_TAFL_TX_ALMOST_FULL. */
03712 
03713 /*! @brief Read current value of the ENET_TAFL_TX_ALMOST_FULL field. */
03714 #define BR_ENET_TAFL_TX_ALMOST_FULL(x) (UNION_READ(hw_enet_tafl_t, HW_ENET_TAFL_ADDR(x), U, B.TX_ALMOST_FULL))
03715 
03716 /*! @brief Format value for bitfield ENET_TAFL_TX_ALMOST_FULL. */
03717 #define BF_ENET_TAFL_TX_ALMOST_FULL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TAFL_TX_ALMOST_FULL) & BM_ENET_TAFL_TX_ALMOST_FULL)
03718 
03719 /*! @brief Set the TX_ALMOST_FULL field to a new value. */
03720 #define BW_ENET_TAFL_TX_ALMOST_FULL(x, v) (HW_ENET_TAFL_WR(x, (HW_ENET_TAFL_RD(x) & ~BM_ENET_TAFL_TX_ALMOST_FULL) | BF_ENET_TAFL_TX_ALMOST_FULL(v)))
03721 /*@}*/
03722 
03723 /*******************************************************************************
03724  * HW_ENET_TIPG - Transmit Inter-Packet Gap
03725  ******************************************************************************/
03726 
03727 /*!
03728  * @brief HW_ENET_TIPG - Transmit Inter-Packet Gap (RW)
03729  *
03730  * Reset value: 0x0000000CU
03731  */
03732 typedef union _hw_enet_tipg
03733 {
03734     uint32_t U;
03735     struct _hw_enet_tipg_bitfields
03736     {
03737         uint32_t IPG : 5;              /*!< [4:0] Transmit Inter-Packet Gap */
03738         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
03739     } B;
03740 } hw_enet_tipg_t;
03741 
03742 /*!
03743  * @name Constants and macros for entire ENET_TIPG register
03744  */
03745 /*@{*/
03746 #define HW_ENET_TIPG_ADDR(x)     ((x) + 0x1ACU)
03747 
03748 #define HW_ENET_TIPG(x)          (*(__IO hw_enet_tipg_t *) HW_ENET_TIPG_ADDR(x))
03749 #define HW_ENET_TIPG_RD(x)       (ADDRESS_READ(hw_enet_tipg_t, HW_ENET_TIPG_ADDR(x)))
03750 #define HW_ENET_TIPG_WR(x, v)    (ADDRESS_WRITE(hw_enet_tipg_t, HW_ENET_TIPG_ADDR(x), v))
03751 #define HW_ENET_TIPG_SET(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) |  (v)))
03752 #define HW_ENET_TIPG_CLR(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) & ~(v)))
03753 #define HW_ENET_TIPG_TOG(x, v)   (HW_ENET_TIPG_WR(x, HW_ENET_TIPG_RD(x) ^  (v)))
03754 /*@}*/
03755 
03756 /*
03757  * Constants & macros for individual ENET_TIPG bitfields
03758  */
03759 
03760 /*!
03761  * @name Register ENET_TIPG, field IPG[4:0] (RW)
03762  *
03763  * Indicates the IPG, in bytes, between transmitted frames. Valid values range
03764  * from 8 to 27. If value is less than 8, the IPG is 8. If value is greater than
03765  * 27, the IPG is 27.
03766  */
03767 /*@{*/
03768 #define BP_ENET_TIPG_IPG     (0U)          /*!< Bit position for ENET_TIPG_IPG. */
03769 #define BM_ENET_TIPG_IPG     (0x0000001FU) /*!< Bit mask for ENET_TIPG_IPG. */
03770 #define BS_ENET_TIPG_IPG     (5U)          /*!< Bit field size in bits for ENET_TIPG_IPG. */
03771 
03772 /*! @brief Read current value of the ENET_TIPG_IPG field. */
03773 #define BR_ENET_TIPG_IPG(x)  (UNION_READ(hw_enet_tipg_t, HW_ENET_TIPG_ADDR(x), U, B.IPG))
03774 
03775 /*! @brief Format value for bitfield ENET_TIPG_IPG. */
03776 #define BF_ENET_TIPG_IPG(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TIPG_IPG) & BM_ENET_TIPG_IPG)
03777 
03778 /*! @brief Set the IPG field to a new value. */
03779 #define BW_ENET_TIPG_IPG(x, v) (HW_ENET_TIPG_WR(x, (HW_ENET_TIPG_RD(x) & ~BM_ENET_TIPG_IPG) | BF_ENET_TIPG_IPG(v)))
03780 /*@}*/
03781 
03782 /*******************************************************************************
03783  * HW_ENET_FTRL - Frame Truncation Length
03784  ******************************************************************************/
03785 
03786 /*!
03787  * @brief HW_ENET_FTRL - Frame Truncation Length (RW)
03788  *
03789  * Reset value: 0x000007FFU
03790  */
03791 typedef union _hw_enet_ftrl
03792 {
03793     uint32_t U;
03794     struct _hw_enet_ftrl_bitfields
03795     {
03796         uint32_t TRUNC_FL : 14;        /*!< [13:0] Frame Truncation Length */
03797         uint32_t RESERVED0 : 18;       /*!< [31:14]  */
03798     } B;
03799 } hw_enet_ftrl_t;
03800 
03801 /*!
03802  * @name Constants and macros for entire ENET_FTRL register
03803  */
03804 /*@{*/
03805 #define HW_ENET_FTRL_ADDR(x)     ((x) + 0x1B0U)
03806 
03807 #define HW_ENET_FTRL(x)          (*(__IO hw_enet_ftrl_t *) HW_ENET_FTRL_ADDR(x))
03808 #define HW_ENET_FTRL_RD(x)       (ADDRESS_READ(hw_enet_ftrl_t, HW_ENET_FTRL_ADDR(x)))
03809 #define HW_ENET_FTRL_WR(x, v)    (ADDRESS_WRITE(hw_enet_ftrl_t, HW_ENET_FTRL_ADDR(x), v))
03810 #define HW_ENET_FTRL_SET(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) |  (v)))
03811 #define HW_ENET_FTRL_CLR(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) & ~(v)))
03812 #define HW_ENET_FTRL_TOG(x, v)   (HW_ENET_FTRL_WR(x, HW_ENET_FTRL_RD(x) ^  (v)))
03813 /*@}*/
03814 
03815 /*
03816  * Constants & macros for individual ENET_FTRL bitfields
03817  */
03818 
03819 /*!
03820  * @name Register ENET_FTRL, field TRUNC_FL[13:0] (RW)
03821  *
03822  * Indicates the value a receive frame is truncated, if it is greater than this
03823  * value. Must be greater than or equal to RCR[MAX_FL]. Truncation happens at
03824  * TRUNC_FL. However, when truncation occurs, the application (FIFO) may receive
03825  * less data, guaranteeing that it never receives more than the set limit.
03826  */
03827 /*@{*/
03828 #define BP_ENET_FTRL_TRUNC_FL (0U)         /*!< Bit position for ENET_FTRL_TRUNC_FL. */
03829 #define BM_ENET_FTRL_TRUNC_FL (0x00003FFFU) /*!< Bit mask for ENET_FTRL_TRUNC_FL. */
03830 #define BS_ENET_FTRL_TRUNC_FL (14U)        /*!< Bit field size in bits for ENET_FTRL_TRUNC_FL. */
03831 
03832 /*! @brief Read current value of the ENET_FTRL_TRUNC_FL field. */
03833 #define BR_ENET_FTRL_TRUNC_FL(x) (UNION_READ(hw_enet_ftrl_t, HW_ENET_FTRL_ADDR(x), U, B.TRUNC_FL))
03834 
03835 /*! @brief Format value for bitfield ENET_FTRL_TRUNC_FL. */
03836 #define BF_ENET_FTRL_TRUNC_FL(v) ((uint32_t)((uint32_t)(v) << BP_ENET_FTRL_TRUNC_FL) & BM_ENET_FTRL_TRUNC_FL)
03837 
03838 /*! @brief Set the TRUNC_FL field to a new value. */
03839 #define BW_ENET_FTRL_TRUNC_FL(x, v) (HW_ENET_FTRL_WR(x, (HW_ENET_FTRL_RD(x) & ~BM_ENET_FTRL_TRUNC_FL) | BF_ENET_FTRL_TRUNC_FL(v)))
03840 /*@}*/
03841 
03842 /*******************************************************************************
03843  * HW_ENET_TACC - Transmit Accelerator Function Configuration
03844  ******************************************************************************/
03845 
03846 /*!
03847  * @brief HW_ENET_TACC - Transmit Accelerator Function Configuration (RW)
03848  *
03849  * Reset value: 0x00000000U
03850  *
03851  * TACC controls accelerator actions when sending frames. The register can be
03852  * changed before or after each frame, but it must remain unmodified during frame
03853  * writes into the transmit FIFO. The TFWR[STRFWD] field must be set to use the
03854  * checksum feature.
03855  */
03856 typedef union _hw_enet_tacc
03857 {
03858     uint32_t U;
03859     struct _hw_enet_tacc_bitfields
03860     {
03861         uint32_t SHIFT16 : 1;          /*!< [0] TX FIFO Shift-16 */
03862         uint32_t RESERVED0 : 2;        /*!< [2:1]  */
03863         uint32_t IPCHK : 1;            /*!< [3]  */
03864         uint32_t PROCHK : 1;           /*!< [4]  */
03865         uint32_t RESERVED1 : 27;       /*!< [31:5]  */
03866     } B;
03867 } hw_enet_tacc_t;
03868 
03869 /*!
03870  * @name Constants and macros for entire ENET_TACC register
03871  */
03872 /*@{*/
03873 #define HW_ENET_TACC_ADDR(x)     ((x) + 0x1C0U)
03874 
03875 #define HW_ENET_TACC(x)          (*(__IO hw_enet_tacc_t *) HW_ENET_TACC_ADDR(x))
03876 #define HW_ENET_TACC_RD(x)       (ADDRESS_READ(hw_enet_tacc_t, HW_ENET_TACC_ADDR(x)))
03877 #define HW_ENET_TACC_WR(x, v)    (ADDRESS_WRITE(hw_enet_tacc_t, HW_ENET_TACC_ADDR(x), v))
03878 #define HW_ENET_TACC_SET(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) |  (v)))
03879 #define HW_ENET_TACC_CLR(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) & ~(v)))
03880 #define HW_ENET_TACC_TOG(x, v)   (HW_ENET_TACC_WR(x, HW_ENET_TACC_RD(x) ^  (v)))
03881 /*@}*/
03882 
03883 /*
03884  * Constants & macros for individual ENET_TACC bitfields
03885  */
03886 
03887 /*!
03888  * @name Register ENET_TACC, field SHIFT16[0] (RW)
03889  *
03890  * Values:
03891  * - 0 - Disabled.
03892  * - 1 - Indicates to the transmit data FIFO that the written frames contain two
03893  *     additional octets before the frame data. This means the actual frame
03894  *     begins at bit 16 of the first word written into the FIFO. This function allows
03895  *     putting the frame payload on a 32-bit boundary in memory, as the 14-byte
03896  *     Ethernet header is extended to a 16-byte header.
03897  */
03898 /*@{*/
03899 #define BP_ENET_TACC_SHIFT16 (0U)          /*!< Bit position for ENET_TACC_SHIFT16. */
03900 #define BM_ENET_TACC_SHIFT16 (0x00000001U) /*!< Bit mask for ENET_TACC_SHIFT16. */
03901 #define BS_ENET_TACC_SHIFT16 (1U)          /*!< Bit field size in bits for ENET_TACC_SHIFT16. */
03902 
03903 /*! @brief Read current value of the ENET_TACC_SHIFT16 field. */
03904 #define BR_ENET_TACC_SHIFT16(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16)))
03905 
03906 /*! @brief Format value for bitfield ENET_TACC_SHIFT16. */
03907 #define BF_ENET_TACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_SHIFT16) & BM_ENET_TACC_SHIFT16)
03908 
03909 /*! @brief Set the SHIFT16 field to a new value. */
03910 #define BW_ENET_TACC_SHIFT16(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_SHIFT16), v))
03911 /*@}*/
03912 
03913 /*!
03914  * @name Register ENET_TACC, field IPCHK[3] (RW)
03915  *
03916  * Enables insertion of IP header checksum.
03917  *
03918  * Values:
03919  * - 0 - Checksum is not inserted.
03920  * - 1 - If an IP frame is transmitted, the checksum is inserted automatically.
03921  *     The IP header checksum field must be cleared. If a non-IP frame is
03922  *     transmitted the frame is not modified.
03923  */
03924 /*@{*/
03925 #define BP_ENET_TACC_IPCHK   (3U)          /*!< Bit position for ENET_TACC_IPCHK. */
03926 #define BM_ENET_TACC_IPCHK   (0x00000008U) /*!< Bit mask for ENET_TACC_IPCHK. */
03927 #define BS_ENET_TACC_IPCHK   (1U)          /*!< Bit field size in bits for ENET_TACC_IPCHK. */
03928 
03929 /*! @brief Read current value of the ENET_TACC_IPCHK field. */
03930 #define BR_ENET_TACC_IPCHK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK)))
03931 
03932 /*! @brief Format value for bitfield ENET_TACC_IPCHK. */
03933 #define BF_ENET_TACC_IPCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_IPCHK) & BM_ENET_TACC_IPCHK)
03934 
03935 /*! @brief Set the IPCHK field to a new value. */
03936 #define BW_ENET_TACC_IPCHK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_IPCHK), v))
03937 /*@}*/
03938 
03939 /*!
03940  * @name Register ENET_TACC, field PROCHK[4] (RW)
03941  *
03942  * Enables insertion of protocol checksum.
03943  *
03944  * Values:
03945  * - 0 - Checksum not inserted.
03946  * - 1 - If an IP frame with a known protocol is transmitted, the checksum is
03947  *     inserted automatically into the frame. The checksum field must be cleared.
03948  *     The other frames are not modified.
03949  */
03950 /*@{*/
03951 #define BP_ENET_TACC_PROCHK  (4U)          /*!< Bit position for ENET_TACC_PROCHK. */
03952 #define BM_ENET_TACC_PROCHK  (0x00000010U) /*!< Bit mask for ENET_TACC_PROCHK. */
03953 #define BS_ENET_TACC_PROCHK  (1U)          /*!< Bit field size in bits for ENET_TACC_PROCHK. */
03954 
03955 /*! @brief Read current value of the ENET_TACC_PROCHK field. */
03956 #define BR_ENET_TACC_PROCHK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK)))
03957 
03958 /*! @brief Format value for bitfield ENET_TACC_PROCHK. */
03959 #define BF_ENET_TACC_PROCHK(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TACC_PROCHK) & BM_ENET_TACC_PROCHK)
03960 
03961 /*! @brief Set the PROCHK field to a new value. */
03962 #define BW_ENET_TACC_PROCHK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TACC_ADDR(x), BP_ENET_TACC_PROCHK), v))
03963 /*@}*/
03964 
03965 /*******************************************************************************
03966  * HW_ENET_RACC - Receive Accelerator Function Configuration
03967  ******************************************************************************/
03968 
03969 /*!
03970  * @brief HW_ENET_RACC - Receive Accelerator Function Configuration (RW)
03971  *
03972  * Reset value: 0x00000000U
03973  */
03974 typedef union _hw_enet_racc
03975 {
03976     uint32_t U;
03977     struct _hw_enet_racc_bitfields
03978     {
03979         uint32_t PADREM : 1;           /*!< [0] Enable Padding Removal For Short IP
03980                                         * Frames */
03981         uint32_t IPDIS : 1;            /*!< [1] Enable Discard Of Frames With Wrong IPv4
03982                                         * Header Checksum */
03983         uint32_t PRODIS : 1;           /*!< [2] Enable Discard Of Frames With Wrong
03984                                         * Protocol Checksum */
03985         uint32_t RESERVED0 : 3;        /*!< [5:3]  */
03986         uint32_t LINEDIS : 1;          /*!< [6] Enable Discard Of Frames With MAC
03987                                         * Layer Errors */
03988         uint32_t SHIFT16 : 1;          /*!< [7] RX FIFO Shift-16 */
03989         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
03990     } B;
03991 } hw_enet_racc_t;
03992 
03993 /*!
03994  * @name Constants and macros for entire ENET_RACC register
03995  */
03996 /*@{*/
03997 #define HW_ENET_RACC_ADDR(x)     ((x) + 0x1C4U)
03998 
03999 #define HW_ENET_RACC(x)          (*(__IO hw_enet_racc_t *) HW_ENET_RACC_ADDR(x))
04000 #define HW_ENET_RACC_RD(x)       (ADDRESS_READ(hw_enet_racc_t, HW_ENET_RACC_ADDR(x)))
04001 #define HW_ENET_RACC_WR(x, v)    (ADDRESS_WRITE(hw_enet_racc_t, HW_ENET_RACC_ADDR(x), v))
04002 #define HW_ENET_RACC_SET(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) |  (v)))
04003 #define HW_ENET_RACC_CLR(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) & ~(v)))
04004 #define HW_ENET_RACC_TOG(x, v)   (HW_ENET_RACC_WR(x, HW_ENET_RACC_RD(x) ^  (v)))
04005 /*@}*/
04006 
04007 /*
04008  * Constants & macros for individual ENET_RACC bitfields
04009  */
04010 
04011 /*!
04012  * @name Register ENET_RACC, field PADREM[0] (RW)
04013  *
04014  * Values:
04015  * - 0 - Padding not removed.
04016  * - 1 - Any bytes following the IP payload section of the frame are removed
04017  *     from the frame.
04018  */
04019 /*@{*/
04020 #define BP_ENET_RACC_PADREM  (0U)          /*!< Bit position for ENET_RACC_PADREM. */
04021 #define BM_ENET_RACC_PADREM  (0x00000001U) /*!< Bit mask for ENET_RACC_PADREM. */
04022 #define BS_ENET_RACC_PADREM  (1U)          /*!< Bit field size in bits for ENET_RACC_PADREM. */
04023 
04024 /*! @brief Read current value of the ENET_RACC_PADREM field. */
04025 #define BR_ENET_RACC_PADREM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM)))
04026 
04027 /*! @brief Format value for bitfield ENET_RACC_PADREM. */
04028 #define BF_ENET_RACC_PADREM(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PADREM) & BM_ENET_RACC_PADREM)
04029 
04030 /*! @brief Set the PADREM field to a new value. */
04031 #define BW_ENET_RACC_PADREM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PADREM), v))
04032 /*@}*/
04033 
04034 /*!
04035  * @name Register ENET_RACC, field IPDIS[1] (RW)
04036  *
04037  * Values:
04038  * - 0 - Frames with wrong IPv4 header checksum are not discarded.
04039  * - 1 - If an IPv4 frame is received with a mismatching header checksum, the
04040  *     frame is discarded. IPv6 has no header checksum and is not affected by this
04041  *     setting. Discarding is only available when the RX FIFO operates in store
04042  *     and forward mode (RSFL cleared).
04043  */
04044 /*@{*/
04045 #define BP_ENET_RACC_IPDIS   (1U)          /*!< Bit position for ENET_RACC_IPDIS. */
04046 #define BM_ENET_RACC_IPDIS   (0x00000002U) /*!< Bit mask for ENET_RACC_IPDIS. */
04047 #define BS_ENET_RACC_IPDIS   (1U)          /*!< Bit field size in bits for ENET_RACC_IPDIS. */
04048 
04049 /*! @brief Read current value of the ENET_RACC_IPDIS field. */
04050 #define BR_ENET_RACC_IPDIS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS)))
04051 
04052 /*! @brief Format value for bitfield ENET_RACC_IPDIS. */
04053 #define BF_ENET_RACC_IPDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_IPDIS) & BM_ENET_RACC_IPDIS)
04054 
04055 /*! @brief Set the IPDIS field to a new value. */
04056 #define BW_ENET_RACC_IPDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_IPDIS), v))
04057 /*@}*/
04058 
04059 /*!
04060  * @name Register ENET_RACC, field PRODIS[2] (RW)
04061  *
04062  * Values:
04063  * - 0 - Frames with wrong checksum are not discarded.
04064  * - 1 - If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP,
04065  *     UDP, or ICMP checksum, the frame is discarded. Discarding is only
04066  *     available when the RX FIFO operates in store and forward mode (RSFL cleared).
04067  */
04068 /*@{*/
04069 #define BP_ENET_RACC_PRODIS  (2U)          /*!< Bit position for ENET_RACC_PRODIS. */
04070 #define BM_ENET_RACC_PRODIS  (0x00000004U) /*!< Bit mask for ENET_RACC_PRODIS. */
04071 #define BS_ENET_RACC_PRODIS  (1U)          /*!< Bit field size in bits for ENET_RACC_PRODIS. */
04072 
04073 /*! @brief Read current value of the ENET_RACC_PRODIS field. */
04074 #define BR_ENET_RACC_PRODIS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS)))
04075 
04076 /*! @brief Format value for bitfield ENET_RACC_PRODIS. */
04077 #define BF_ENET_RACC_PRODIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_PRODIS) & BM_ENET_RACC_PRODIS)
04078 
04079 /*! @brief Set the PRODIS field to a new value. */
04080 #define BW_ENET_RACC_PRODIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_PRODIS), v))
04081 /*@}*/
04082 
04083 /*!
04084  * @name Register ENET_RACC, field LINEDIS[6] (RW)
04085  *
04086  * Values:
04087  * - 0 - Frames with errors are not discarded.
04088  * - 1 - Any frame received with a CRC, length, or PHY error is automatically
04089  *     discarded and not forwarded to the user application interface.
04090  */
04091 /*@{*/
04092 #define BP_ENET_RACC_LINEDIS (6U)          /*!< Bit position for ENET_RACC_LINEDIS. */
04093 #define BM_ENET_RACC_LINEDIS (0x00000040U) /*!< Bit mask for ENET_RACC_LINEDIS. */
04094 #define BS_ENET_RACC_LINEDIS (1U)          /*!< Bit field size in bits for ENET_RACC_LINEDIS. */
04095 
04096 /*! @brief Read current value of the ENET_RACC_LINEDIS field. */
04097 #define BR_ENET_RACC_LINEDIS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS)))
04098 
04099 /*! @brief Format value for bitfield ENET_RACC_LINEDIS. */
04100 #define BF_ENET_RACC_LINEDIS(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_LINEDIS) & BM_ENET_RACC_LINEDIS)
04101 
04102 /*! @brief Set the LINEDIS field to a new value. */
04103 #define BW_ENET_RACC_LINEDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_LINEDIS), v))
04104 /*@}*/
04105 
04106 /*!
04107  * @name Register ENET_RACC, field SHIFT16[7] (RW)
04108  *
04109  * When this field is set, the actual frame data starts at bit 16 of the first
04110  * word read from the RX FIFO aligning the Ethernet payload on a 32-bit boundary.
04111  * This function only affects the FIFO storage and has no influence on the
04112  * statistics, which use the actual length of the frame received.
04113  *
04114  * Values:
04115  * - 0 - Disabled.
04116  * - 1 - Instructs the MAC to write two additional bytes in front of each frame
04117  *     received into the RX FIFO.
04118  */
04119 /*@{*/
04120 #define BP_ENET_RACC_SHIFT16 (7U)          /*!< Bit position for ENET_RACC_SHIFT16. */
04121 #define BM_ENET_RACC_SHIFT16 (0x00000080U) /*!< Bit mask for ENET_RACC_SHIFT16. */
04122 #define BS_ENET_RACC_SHIFT16 (1U)          /*!< Bit field size in bits for ENET_RACC_SHIFT16. */
04123 
04124 /*! @brief Read current value of the ENET_RACC_SHIFT16 field. */
04125 #define BR_ENET_RACC_SHIFT16(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16)))
04126 
04127 /*! @brief Format value for bitfield ENET_RACC_SHIFT16. */
04128 #define BF_ENET_RACC_SHIFT16(v) ((uint32_t)((uint32_t)(v) << BP_ENET_RACC_SHIFT16) & BM_ENET_RACC_SHIFT16)
04129 
04130 /*! @brief Set the SHIFT16 field to a new value. */
04131 #define BW_ENET_RACC_SHIFT16(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_RACC_ADDR(x), BP_ENET_RACC_SHIFT16), v))
04132 /*@}*/
04133 
04134 /*******************************************************************************
04135  * HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register
04136  ******************************************************************************/
04137 
04138 /*!
04139  * @brief HW_ENET_RMON_T_PACKETS - Tx Packet Count Statistic Register (RO)
04140  *
04141  * Reset value: 0x00000000U
04142  */
04143 typedef union _hw_enet_rmon_t_packets
04144 {
04145     uint32_t U;
04146     struct _hw_enet_rmon_t_packets_bitfields
04147     {
04148         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04149         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04150     } B;
04151 } hw_enet_rmon_t_packets_t;
04152 
04153 /*!
04154  * @name Constants and macros for entire ENET_RMON_T_PACKETS register
04155  */
04156 /*@{*/
04157 #define HW_ENET_RMON_T_PACKETS_ADDR(x) ((x) + 0x204U)
04158 
04159 #define HW_ENET_RMON_T_PACKETS(x) (*(__I hw_enet_rmon_t_packets_t *) HW_ENET_RMON_T_PACKETS_ADDR(x))
04160 #define HW_ENET_RMON_T_PACKETS_RD(x) (ADDRESS_READ(hw_enet_rmon_t_packets_t, HW_ENET_RMON_T_PACKETS_ADDR(x)))
04161 /*@}*/
04162 
04163 /*
04164  * Constants & macros for individual ENET_RMON_T_PACKETS bitfields
04165  */
04166 
04167 /*!
04168  * @name Register ENET_RMON_T_PACKETS, field TXPKTS[15:0] (RO)
04169  */
04170 /*@{*/
04171 #define BP_ENET_RMON_T_PACKETS_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_PACKETS_TXPKTS. */
04172 #define BM_ENET_RMON_T_PACKETS_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_PACKETS_TXPKTS. */
04173 #define BS_ENET_RMON_T_PACKETS_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_PACKETS_TXPKTS. */
04174 
04175 /*! @brief Read current value of the ENET_RMON_T_PACKETS_TXPKTS field. */
04176 #define BR_ENET_RMON_T_PACKETS_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_packets_t, HW_ENET_RMON_T_PACKETS_ADDR(x), U, B.TXPKTS))
04177 /*@}*/
04178 
04179 /*******************************************************************************
04180  * HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register
04181  ******************************************************************************/
04182 
04183 /*!
04184  * @brief HW_ENET_RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register (RO)
04185  *
04186  * Reset value: 0x00000000U
04187  *
04188  * RMON Tx Broadcast Packets
04189  */
04190 typedef union _hw_enet_rmon_t_bc_pkt
04191 {
04192     uint32_t U;
04193     struct _hw_enet_rmon_t_bc_pkt_bitfields
04194     {
04195         uint32_t TXPKTS : 16;          /*!< [15:0] Broadcast packets */
04196         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04197     } B;
04198 } hw_enet_rmon_t_bc_pkt_t;
04199 
04200 /*!
04201  * @name Constants and macros for entire ENET_RMON_T_BC_PKT register
04202  */
04203 /*@{*/
04204 #define HW_ENET_RMON_T_BC_PKT_ADDR(x) ((x) + 0x208U)
04205 
04206 #define HW_ENET_RMON_T_BC_PKT(x) (*(__I hw_enet_rmon_t_bc_pkt_t *) HW_ENET_RMON_T_BC_PKT_ADDR(x))
04207 #define HW_ENET_RMON_T_BC_PKT_RD(x) (ADDRESS_READ(hw_enet_rmon_t_bc_pkt_t, HW_ENET_RMON_T_BC_PKT_ADDR(x)))
04208 /*@}*/
04209 
04210 /*
04211  * Constants & macros for individual ENET_RMON_T_BC_PKT bitfields
04212  */
04213 
04214 /*!
04215  * @name Register ENET_RMON_T_BC_PKT, field TXPKTS[15:0] (RO)
04216  */
04217 /*@{*/
04218 #define BP_ENET_RMON_T_BC_PKT_TXPKTS (0U)  /*!< Bit position for ENET_RMON_T_BC_PKT_TXPKTS. */
04219 #define BM_ENET_RMON_T_BC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_BC_PKT_TXPKTS. */
04220 #define BS_ENET_RMON_T_BC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_BC_PKT_TXPKTS. */
04221 
04222 /*! @brief Read current value of the ENET_RMON_T_BC_PKT_TXPKTS field. */
04223 #define BR_ENET_RMON_T_BC_PKT_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_bc_pkt_t, HW_ENET_RMON_T_BC_PKT_ADDR(x), U, B.TXPKTS))
04224 /*@}*/
04225 
04226 /*******************************************************************************
04227  * HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register
04228  ******************************************************************************/
04229 
04230 /*!
04231  * @brief HW_ENET_RMON_T_MC_PKT - Tx Multicast Packets Statistic Register (RO)
04232  *
04233  * Reset value: 0x00000000U
04234  */
04235 typedef union _hw_enet_rmon_t_mc_pkt
04236 {
04237     uint32_t U;
04238     struct _hw_enet_rmon_t_mc_pkt_bitfields
04239     {
04240         uint32_t TXPKTS : 16;          /*!< [15:0] Multicast packets */
04241         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04242     } B;
04243 } hw_enet_rmon_t_mc_pkt_t;
04244 
04245 /*!
04246  * @name Constants and macros for entire ENET_RMON_T_MC_PKT register
04247  */
04248 /*@{*/
04249 #define HW_ENET_RMON_T_MC_PKT_ADDR(x) ((x) + 0x20CU)
04250 
04251 #define HW_ENET_RMON_T_MC_PKT(x) (*(__I hw_enet_rmon_t_mc_pkt_t *) HW_ENET_RMON_T_MC_PKT_ADDR(x))
04252 #define HW_ENET_RMON_T_MC_PKT_RD(x) (ADDRESS_READ(hw_enet_rmon_t_mc_pkt_t, HW_ENET_RMON_T_MC_PKT_ADDR(x)))
04253 /*@}*/
04254 
04255 /*
04256  * Constants & macros for individual ENET_RMON_T_MC_PKT bitfields
04257  */
04258 
04259 /*!
04260  * @name Register ENET_RMON_T_MC_PKT, field TXPKTS[15:0] (RO)
04261  */
04262 /*@{*/
04263 #define BP_ENET_RMON_T_MC_PKT_TXPKTS (0U)  /*!< Bit position for ENET_RMON_T_MC_PKT_TXPKTS. */
04264 #define BM_ENET_RMON_T_MC_PKT_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_MC_PKT_TXPKTS. */
04265 #define BS_ENET_RMON_T_MC_PKT_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_MC_PKT_TXPKTS. */
04266 
04267 /*! @brief Read current value of the ENET_RMON_T_MC_PKT_TXPKTS field. */
04268 #define BR_ENET_RMON_T_MC_PKT_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_mc_pkt_t, HW_ENET_RMON_T_MC_PKT_ADDR(x), U, B.TXPKTS))
04269 /*@}*/
04270 
04271 /*******************************************************************************
04272  * HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register
04273  ******************************************************************************/
04274 
04275 /*!
04276  * @brief HW_ENET_RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register (RO)
04277  *
04278  * Reset value: 0x00000000U
04279  */
04280 typedef union _hw_enet_rmon_t_crc_align
04281 {
04282     uint32_t U;
04283     struct _hw_enet_rmon_t_crc_align_bitfields
04284     {
04285         uint32_t TXPKTS : 16;          /*!< [15:0] Packets with CRC/align error */
04286         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04287     } B;
04288 } hw_enet_rmon_t_crc_align_t;
04289 
04290 /*!
04291  * @name Constants and macros for entire ENET_RMON_T_CRC_ALIGN register
04292  */
04293 /*@{*/
04294 #define HW_ENET_RMON_T_CRC_ALIGN_ADDR(x) ((x) + 0x210U)
04295 
04296 #define HW_ENET_RMON_T_CRC_ALIGN(x) (*(__I hw_enet_rmon_t_crc_align_t *) HW_ENET_RMON_T_CRC_ALIGN_ADDR(x))
04297 #define HW_ENET_RMON_T_CRC_ALIGN_RD(x) (ADDRESS_READ(hw_enet_rmon_t_crc_align_t, HW_ENET_RMON_T_CRC_ALIGN_ADDR(x)))
04298 /*@}*/
04299 
04300 /*
04301  * Constants & macros for individual ENET_RMON_T_CRC_ALIGN bitfields
04302  */
04303 
04304 /*!
04305  * @name Register ENET_RMON_T_CRC_ALIGN, field TXPKTS[15:0] (RO)
04306  */
04307 /*@{*/
04308 #define BP_ENET_RMON_T_CRC_ALIGN_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
04309 #define BM_ENET_RMON_T_CRC_ALIGN_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
04310 #define BS_ENET_RMON_T_CRC_ALIGN_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_CRC_ALIGN_TXPKTS. */
04311 
04312 /*! @brief Read current value of the ENET_RMON_T_CRC_ALIGN_TXPKTS field. */
04313 #define BR_ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_crc_align_t, HW_ENET_RMON_T_CRC_ALIGN_ADDR(x), U, B.TXPKTS))
04314 /*@}*/
04315 
04316 /*******************************************************************************
04317  * HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register
04318  ******************************************************************************/
04319 
04320 /*!
04321  * @brief HW_ENET_RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register (RO)
04322  *
04323  * Reset value: 0x00000000U
04324  */
04325 typedef union _hw_enet_rmon_t_undersize
04326 {
04327     uint32_t U;
04328     struct _hw_enet_rmon_t_undersize_bitfields
04329     {
04330         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04331         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04332     } B;
04333 } hw_enet_rmon_t_undersize_t;
04334 
04335 /*!
04336  * @name Constants and macros for entire ENET_RMON_T_UNDERSIZE register
04337  */
04338 /*@{*/
04339 #define HW_ENET_RMON_T_UNDERSIZE_ADDR(x) ((x) + 0x214U)
04340 
04341 #define HW_ENET_RMON_T_UNDERSIZE(x) (*(__I hw_enet_rmon_t_undersize_t *) HW_ENET_RMON_T_UNDERSIZE_ADDR(x))
04342 #define HW_ENET_RMON_T_UNDERSIZE_RD(x) (ADDRESS_READ(hw_enet_rmon_t_undersize_t, HW_ENET_RMON_T_UNDERSIZE_ADDR(x)))
04343 /*@}*/
04344 
04345 /*
04346  * Constants & macros for individual ENET_RMON_T_UNDERSIZE bitfields
04347  */
04348 
04349 /*!
04350  * @name Register ENET_RMON_T_UNDERSIZE, field TXPKTS[15:0] (RO)
04351  */
04352 /*@{*/
04353 #define BP_ENET_RMON_T_UNDERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_UNDERSIZE_TXPKTS. */
04354 #define BM_ENET_RMON_T_UNDERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_UNDERSIZE_TXPKTS. */
04355 #define BS_ENET_RMON_T_UNDERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_UNDERSIZE_TXPKTS. */
04356 
04357 /*! @brief Read current value of the ENET_RMON_T_UNDERSIZE_TXPKTS field. */
04358 #define BR_ENET_RMON_T_UNDERSIZE_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_undersize_t, HW_ENET_RMON_T_UNDERSIZE_ADDR(x), U, B.TXPKTS))
04359 /*@}*/
04360 
04361 /*******************************************************************************
04362  * HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register
04363  ******************************************************************************/
04364 
04365 /*!
04366  * @brief HW_ENET_RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (RO)
04367  *
04368  * Reset value: 0x00000000U
04369  */
04370 typedef union _hw_enet_rmon_t_oversize
04371 {
04372     uint32_t U;
04373     struct _hw_enet_rmon_t_oversize_bitfields
04374     {
04375         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04376         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04377     } B;
04378 } hw_enet_rmon_t_oversize_t;
04379 
04380 /*!
04381  * @name Constants and macros for entire ENET_RMON_T_OVERSIZE register
04382  */
04383 /*@{*/
04384 #define HW_ENET_RMON_T_OVERSIZE_ADDR(x) ((x) + 0x218U)
04385 
04386 #define HW_ENET_RMON_T_OVERSIZE(x) (*(__I hw_enet_rmon_t_oversize_t *) HW_ENET_RMON_T_OVERSIZE_ADDR(x))
04387 #define HW_ENET_RMON_T_OVERSIZE_RD(x) (ADDRESS_READ(hw_enet_rmon_t_oversize_t, HW_ENET_RMON_T_OVERSIZE_ADDR(x)))
04388 /*@}*/
04389 
04390 /*
04391  * Constants & macros for individual ENET_RMON_T_OVERSIZE bitfields
04392  */
04393 
04394 /*!
04395  * @name Register ENET_RMON_T_OVERSIZE, field TXPKTS[15:0] (RO)
04396  */
04397 /*@{*/
04398 #define BP_ENET_RMON_T_OVERSIZE_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_OVERSIZE_TXPKTS. */
04399 #define BM_ENET_RMON_T_OVERSIZE_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_OVERSIZE_TXPKTS. */
04400 #define BS_ENET_RMON_T_OVERSIZE_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_OVERSIZE_TXPKTS. */
04401 
04402 /*! @brief Read current value of the ENET_RMON_T_OVERSIZE_TXPKTS field. */
04403 #define BR_ENET_RMON_T_OVERSIZE_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_oversize_t, HW_ENET_RMON_T_OVERSIZE_ADDR(x), U, B.TXPKTS))
04404 /*@}*/
04405 
04406 /*******************************************************************************
04407  * HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register
04408  ******************************************************************************/
04409 
04410 /*!
04411  * @brief HW_ENET_RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
04412  *
04413  * Reset value: 0x00000000U
04414  *
04415  * .
04416  */
04417 typedef union _hw_enet_rmon_t_frag
04418 {
04419     uint32_t U;
04420     struct _hw_enet_rmon_t_frag_bitfields
04421     {
04422         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04423         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04424     } B;
04425 } hw_enet_rmon_t_frag_t;
04426 
04427 /*!
04428  * @name Constants and macros for entire ENET_RMON_T_FRAG register
04429  */
04430 /*@{*/
04431 #define HW_ENET_RMON_T_FRAG_ADDR(x) ((x) + 0x21CU)
04432 
04433 #define HW_ENET_RMON_T_FRAG(x)   (*(__I hw_enet_rmon_t_frag_t *) HW_ENET_RMON_T_FRAG_ADDR(x))
04434 #define HW_ENET_RMON_T_FRAG_RD(x) (ADDRESS_READ(hw_enet_rmon_t_frag_t, HW_ENET_RMON_T_FRAG_ADDR(x)))
04435 /*@}*/
04436 
04437 /*
04438  * Constants & macros for individual ENET_RMON_T_FRAG bitfields
04439  */
04440 
04441 /*!
04442  * @name Register ENET_RMON_T_FRAG, field TXPKTS[15:0] (RO)
04443  */
04444 /*@{*/
04445 #define BP_ENET_RMON_T_FRAG_TXPKTS (0U)    /*!< Bit position for ENET_RMON_T_FRAG_TXPKTS. */
04446 #define BM_ENET_RMON_T_FRAG_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_FRAG_TXPKTS. */
04447 #define BS_ENET_RMON_T_FRAG_TXPKTS (16U)   /*!< Bit field size in bits for ENET_RMON_T_FRAG_TXPKTS. */
04448 
04449 /*! @brief Read current value of the ENET_RMON_T_FRAG_TXPKTS field. */
04450 #define BR_ENET_RMON_T_FRAG_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_frag_t, HW_ENET_RMON_T_FRAG_ADDR(x), U, B.TXPKTS))
04451 /*@}*/
04452 
04453 /*******************************************************************************
04454  * HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register
04455  ******************************************************************************/
04456 
04457 /*!
04458  * @brief HW_ENET_RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (RO)
04459  *
04460  * Reset value: 0x00000000U
04461  */
04462 typedef union _hw_enet_rmon_t_jab
04463 {
04464     uint32_t U;
04465     struct _hw_enet_rmon_t_jab_bitfields
04466     {
04467         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04468         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04469     } B;
04470 } hw_enet_rmon_t_jab_t;
04471 
04472 /*!
04473  * @name Constants and macros for entire ENET_RMON_T_JAB register
04474  */
04475 /*@{*/
04476 #define HW_ENET_RMON_T_JAB_ADDR(x) ((x) + 0x220U)
04477 
04478 #define HW_ENET_RMON_T_JAB(x)    (*(__I hw_enet_rmon_t_jab_t *) HW_ENET_RMON_T_JAB_ADDR(x))
04479 #define HW_ENET_RMON_T_JAB_RD(x) (ADDRESS_READ(hw_enet_rmon_t_jab_t, HW_ENET_RMON_T_JAB_ADDR(x)))
04480 /*@}*/
04481 
04482 /*
04483  * Constants & macros for individual ENET_RMON_T_JAB bitfields
04484  */
04485 
04486 /*!
04487  * @name Register ENET_RMON_T_JAB, field TXPKTS[15:0] (RO)
04488  */
04489 /*@{*/
04490 #define BP_ENET_RMON_T_JAB_TXPKTS (0U)     /*!< Bit position for ENET_RMON_T_JAB_TXPKTS. */
04491 #define BM_ENET_RMON_T_JAB_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_JAB_TXPKTS. */
04492 #define BS_ENET_RMON_T_JAB_TXPKTS (16U)    /*!< Bit field size in bits for ENET_RMON_T_JAB_TXPKTS. */
04493 
04494 /*! @brief Read current value of the ENET_RMON_T_JAB_TXPKTS field. */
04495 #define BR_ENET_RMON_T_JAB_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_jab_t, HW_ENET_RMON_T_JAB_ADDR(x), U, B.TXPKTS))
04496 /*@}*/
04497 
04498 /*******************************************************************************
04499  * HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register
04500  ******************************************************************************/
04501 
04502 /*!
04503  * @brief HW_ENET_RMON_T_COL - Tx Collision Count Statistic Register (RO)
04504  *
04505  * Reset value: 0x00000000U
04506  */
04507 typedef union _hw_enet_rmon_t_col
04508 {
04509     uint32_t U;
04510     struct _hw_enet_rmon_t_col_bitfields
04511     {
04512         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04513         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04514     } B;
04515 } hw_enet_rmon_t_col_t;
04516 
04517 /*!
04518  * @name Constants and macros for entire ENET_RMON_T_COL register
04519  */
04520 /*@{*/
04521 #define HW_ENET_RMON_T_COL_ADDR(x) ((x) + 0x224U)
04522 
04523 #define HW_ENET_RMON_T_COL(x)    (*(__I hw_enet_rmon_t_col_t *) HW_ENET_RMON_T_COL_ADDR(x))
04524 #define HW_ENET_RMON_T_COL_RD(x) (ADDRESS_READ(hw_enet_rmon_t_col_t, HW_ENET_RMON_T_COL_ADDR(x)))
04525 /*@}*/
04526 
04527 /*
04528  * Constants & macros for individual ENET_RMON_T_COL bitfields
04529  */
04530 
04531 /*!
04532  * @name Register ENET_RMON_T_COL, field TXPKTS[15:0] (RO)
04533  */
04534 /*@{*/
04535 #define BP_ENET_RMON_T_COL_TXPKTS (0U)     /*!< Bit position for ENET_RMON_T_COL_TXPKTS. */
04536 #define BM_ENET_RMON_T_COL_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_COL_TXPKTS. */
04537 #define BS_ENET_RMON_T_COL_TXPKTS (16U)    /*!< Bit field size in bits for ENET_RMON_T_COL_TXPKTS. */
04538 
04539 /*! @brief Read current value of the ENET_RMON_T_COL_TXPKTS field. */
04540 #define BR_ENET_RMON_T_COL_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_col_t, HW_ENET_RMON_T_COL_ADDR(x), U, B.TXPKTS))
04541 /*@}*/
04542 
04543 /*******************************************************************************
04544  * HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register
04545  ******************************************************************************/
04546 
04547 /*!
04548  * @brief HW_ENET_RMON_T_P64 - Tx 64-Byte Packets Statistic Register (RO)
04549  *
04550  * Reset value: 0x00000000U
04551  *
04552  * .
04553  */
04554 typedef union _hw_enet_rmon_t_p64
04555 {
04556     uint32_t U;
04557     struct _hw_enet_rmon_t_p64_bitfields
04558     {
04559         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04560         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04561     } B;
04562 } hw_enet_rmon_t_p64_t;
04563 
04564 /*!
04565  * @name Constants and macros for entire ENET_RMON_T_P64 register
04566  */
04567 /*@{*/
04568 #define HW_ENET_RMON_T_P64_ADDR(x) ((x) + 0x228U)
04569 
04570 #define HW_ENET_RMON_T_P64(x)    (*(__I hw_enet_rmon_t_p64_t *) HW_ENET_RMON_T_P64_ADDR(x))
04571 #define HW_ENET_RMON_T_P64_RD(x) (ADDRESS_READ(hw_enet_rmon_t_p64_t, HW_ENET_RMON_T_P64_ADDR(x)))
04572 /*@}*/
04573 
04574 /*
04575  * Constants & macros for individual ENET_RMON_T_P64 bitfields
04576  */
04577 
04578 /*!
04579  * @name Register ENET_RMON_T_P64, field TXPKTS[15:0] (RO)
04580  */
04581 /*@{*/
04582 #define BP_ENET_RMON_T_P64_TXPKTS (0U)     /*!< Bit position for ENET_RMON_T_P64_TXPKTS. */
04583 #define BM_ENET_RMON_T_P64_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P64_TXPKTS. */
04584 #define BS_ENET_RMON_T_P64_TXPKTS (16U)    /*!< Bit field size in bits for ENET_RMON_T_P64_TXPKTS. */
04585 
04586 /*! @brief Read current value of the ENET_RMON_T_P64_TXPKTS field. */
04587 #define BR_ENET_RMON_T_P64_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_p64_t, HW_ENET_RMON_T_P64_ADDR(x), U, B.TXPKTS))
04588 /*@}*/
04589 
04590 /*******************************************************************************
04591  * HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register
04592  ******************************************************************************/
04593 
04594 /*!
04595  * @brief HW_ENET_RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register (RO)
04596  *
04597  * Reset value: 0x00000000U
04598  */
04599 typedef union _hw_enet_rmon_t_p65to127
04600 {
04601     uint32_t U;
04602     struct _hw_enet_rmon_t_p65to127_bitfields
04603     {
04604         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04605         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04606     } B;
04607 } hw_enet_rmon_t_p65to127_t;
04608 
04609 /*!
04610  * @name Constants and macros for entire ENET_RMON_T_P65TO127 register
04611  */
04612 /*@{*/
04613 #define HW_ENET_RMON_T_P65TO127_ADDR(x) ((x) + 0x22CU)
04614 
04615 #define HW_ENET_RMON_T_P65TO127(x) (*(__I hw_enet_rmon_t_p65to127_t *) HW_ENET_RMON_T_P65TO127_ADDR(x))
04616 #define HW_ENET_RMON_T_P65TO127_RD(x) (ADDRESS_READ(hw_enet_rmon_t_p65to127_t, HW_ENET_RMON_T_P65TO127_ADDR(x)))
04617 /*@}*/
04618 
04619 /*
04620  * Constants & macros for individual ENET_RMON_T_P65TO127 bitfields
04621  */
04622 
04623 /*!
04624  * @name Register ENET_RMON_T_P65TO127, field TXPKTS[15:0] (RO)
04625  */
04626 /*@{*/
04627 #define BP_ENET_RMON_T_P65TO127_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P65TO127_TXPKTS. */
04628 #define BM_ENET_RMON_T_P65TO127_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P65TO127_TXPKTS. */
04629 #define BS_ENET_RMON_T_P65TO127_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P65TO127_TXPKTS. */
04630 
04631 /*! @brief Read current value of the ENET_RMON_T_P65TO127_TXPKTS field. */
04632 #define BR_ENET_RMON_T_P65TO127_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_p65to127_t, HW_ENET_RMON_T_P65TO127_ADDR(x), U, B.TXPKTS))
04633 /*@}*/
04634 
04635 /*******************************************************************************
04636  * HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register
04637  ******************************************************************************/
04638 
04639 /*!
04640  * @brief HW_ENET_RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register (RO)
04641  *
04642  * Reset value: 0x00000000U
04643  */
04644 typedef union _hw_enet_rmon_t_p128to255
04645 {
04646     uint32_t U;
04647     struct _hw_enet_rmon_t_p128to255_bitfields
04648     {
04649         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04650         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04651     } B;
04652 } hw_enet_rmon_t_p128to255_t;
04653 
04654 /*!
04655  * @name Constants and macros for entire ENET_RMON_T_P128TO255 register
04656  */
04657 /*@{*/
04658 #define HW_ENET_RMON_T_P128TO255_ADDR(x) ((x) + 0x230U)
04659 
04660 #define HW_ENET_RMON_T_P128TO255(x) (*(__I hw_enet_rmon_t_p128to255_t *) HW_ENET_RMON_T_P128TO255_ADDR(x))
04661 #define HW_ENET_RMON_T_P128TO255_RD(x) (ADDRESS_READ(hw_enet_rmon_t_p128to255_t, HW_ENET_RMON_T_P128TO255_ADDR(x)))
04662 /*@}*/
04663 
04664 /*
04665  * Constants & macros for individual ENET_RMON_T_P128TO255 bitfields
04666  */
04667 
04668 /*!
04669  * @name Register ENET_RMON_T_P128TO255, field TXPKTS[15:0] (RO)
04670  */
04671 /*@{*/
04672 #define BP_ENET_RMON_T_P128TO255_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P128TO255_TXPKTS. */
04673 #define BM_ENET_RMON_T_P128TO255_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P128TO255_TXPKTS. */
04674 #define BS_ENET_RMON_T_P128TO255_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P128TO255_TXPKTS. */
04675 
04676 /*! @brief Read current value of the ENET_RMON_T_P128TO255_TXPKTS field. */
04677 #define BR_ENET_RMON_T_P128TO255_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_p128to255_t, HW_ENET_RMON_T_P128TO255_ADDR(x), U, B.TXPKTS))
04678 /*@}*/
04679 
04680 /*******************************************************************************
04681  * HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register
04682  ******************************************************************************/
04683 
04684 /*!
04685  * @brief HW_ENET_RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register (RO)
04686  *
04687  * Reset value: 0x00000000U
04688  */
04689 typedef union _hw_enet_rmon_t_p256to511
04690 {
04691     uint32_t U;
04692     struct _hw_enet_rmon_t_p256to511_bitfields
04693     {
04694         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04695         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04696     } B;
04697 } hw_enet_rmon_t_p256to511_t;
04698 
04699 /*!
04700  * @name Constants and macros for entire ENET_RMON_T_P256TO511 register
04701  */
04702 /*@{*/
04703 #define HW_ENET_RMON_T_P256TO511_ADDR(x) ((x) + 0x234U)
04704 
04705 #define HW_ENET_RMON_T_P256TO511(x) (*(__I hw_enet_rmon_t_p256to511_t *) HW_ENET_RMON_T_P256TO511_ADDR(x))
04706 #define HW_ENET_RMON_T_P256TO511_RD(x) (ADDRESS_READ(hw_enet_rmon_t_p256to511_t, HW_ENET_RMON_T_P256TO511_ADDR(x)))
04707 /*@}*/
04708 
04709 /*
04710  * Constants & macros for individual ENET_RMON_T_P256TO511 bitfields
04711  */
04712 
04713 /*!
04714  * @name Register ENET_RMON_T_P256TO511, field TXPKTS[15:0] (RO)
04715  */
04716 /*@{*/
04717 #define BP_ENET_RMON_T_P256TO511_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P256TO511_TXPKTS. */
04718 #define BM_ENET_RMON_T_P256TO511_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P256TO511_TXPKTS. */
04719 #define BS_ENET_RMON_T_P256TO511_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P256TO511_TXPKTS. */
04720 
04721 /*! @brief Read current value of the ENET_RMON_T_P256TO511_TXPKTS field. */
04722 #define BR_ENET_RMON_T_P256TO511_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_p256to511_t, HW_ENET_RMON_T_P256TO511_ADDR(x), U, B.TXPKTS))
04723 /*@}*/
04724 
04725 /*******************************************************************************
04726  * HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register
04727  ******************************************************************************/
04728 
04729 /*!
04730  * @brief HW_ENET_RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register (RO)
04731  *
04732  * Reset value: 0x00000000U
04733  *
04734  * .
04735  */
04736 typedef union _hw_enet_rmon_t_p512to1023
04737 {
04738     uint32_t U;
04739     struct _hw_enet_rmon_t_p512to1023_bitfields
04740     {
04741         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04742         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04743     } B;
04744 } hw_enet_rmon_t_p512to1023_t;
04745 
04746 /*!
04747  * @name Constants and macros for entire ENET_RMON_T_P512TO1023 register
04748  */
04749 /*@{*/
04750 #define HW_ENET_RMON_T_P512TO1023_ADDR(x) ((x) + 0x238U)
04751 
04752 #define HW_ENET_RMON_T_P512TO1023(x) (*(__I hw_enet_rmon_t_p512to1023_t *) HW_ENET_RMON_T_P512TO1023_ADDR(x))
04753 #define HW_ENET_RMON_T_P512TO1023_RD(x) (ADDRESS_READ(hw_enet_rmon_t_p512to1023_t, HW_ENET_RMON_T_P512TO1023_ADDR(x)))
04754 /*@}*/
04755 
04756 /*
04757  * Constants & macros for individual ENET_RMON_T_P512TO1023 bitfields
04758  */
04759 
04760 /*!
04761  * @name Register ENET_RMON_T_P512TO1023, field TXPKTS[15:0] (RO)
04762  */
04763 /*@{*/
04764 #define BP_ENET_RMON_T_P512TO1023_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P512TO1023_TXPKTS. */
04765 #define BM_ENET_RMON_T_P512TO1023_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P512TO1023_TXPKTS. */
04766 #define BS_ENET_RMON_T_P512TO1023_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P512TO1023_TXPKTS. */
04767 
04768 /*! @brief Read current value of the ENET_RMON_T_P512TO1023_TXPKTS field. */
04769 #define BR_ENET_RMON_T_P512TO1023_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_p512to1023_t, HW_ENET_RMON_T_P512TO1023_ADDR(x), U, B.TXPKTS))
04770 /*@}*/
04771 
04772 /*******************************************************************************
04773  * HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register
04774  ******************************************************************************/
04775 
04776 /*!
04777  * @brief HW_ENET_RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register (RO)
04778  *
04779  * Reset value: 0x00000000U
04780  */
04781 typedef union _hw_enet_rmon_t_p1024to2047
04782 {
04783     uint32_t U;
04784     struct _hw_enet_rmon_t_p1024to2047_bitfields
04785     {
04786         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04787         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04788     } B;
04789 } hw_enet_rmon_t_p1024to2047_t;
04790 
04791 /*!
04792  * @name Constants and macros for entire ENET_RMON_T_P1024TO2047 register
04793  */
04794 /*@{*/
04795 #define HW_ENET_RMON_T_P1024TO2047_ADDR(x) ((x) + 0x23CU)
04796 
04797 #define HW_ENET_RMON_T_P1024TO2047(x) (*(__I hw_enet_rmon_t_p1024to2047_t *) HW_ENET_RMON_T_P1024TO2047_ADDR(x))
04798 #define HW_ENET_RMON_T_P1024TO2047_RD(x) (ADDRESS_READ(hw_enet_rmon_t_p1024to2047_t, HW_ENET_RMON_T_P1024TO2047_ADDR(x)))
04799 /*@}*/
04800 
04801 /*
04802  * Constants & macros for individual ENET_RMON_T_P1024TO2047 bitfields
04803  */
04804 
04805 /*!
04806  * @name Register ENET_RMON_T_P1024TO2047, field TXPKTS[15:0] (RO)
04807  */
04808 /*@{*/
04809 #define BP_ENET_RMON_T_P1024TO2047_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P1024TO2047_TXPKTS. */
04810 #define BM_ENET_RMON_T_P1024TO2047_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P1024TO2047_TXPKTS. */
04811 #define BS_ENET_RMON_T_P1024TO2047_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P1024TO2047_TXPKTS. */
04812 
04813 /*! @brief Read current value of the ENET_RMON_T_P1024TO2047_TXPKTS field. */
04814 #define BR_ENET_RMON_T_P1024TO2047_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_p1024to2047_t, HW_ENET_RMON_T_P1024TO2047_ADDR(x), U, B.TXPKTS))
04815 /*@}*/
04816 
04817 /*******************************************************************************
04818  * HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register
04819  ******************************************************************************/
04820 
04821 /*!
04822  * @brief HW_ENET_RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register (RO)
04823  *
04824  * Reset value: 0x00000000U
04825  */
04826 typedef union _hw_enet_rmon_t_p_gte2048
04827 {
04828     uint32_t U;
04829     struct _hw_enet_rmon_t_p_gte2048_bitfields
04830     {
04831         uint32_t TXPKTS : 16;          /*!< [15:0] Packet count */
04832         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04833     } B;
04834 } hw_enet_rmon_t_p_gte2048_t;
04835 
04836 /*!
04837  * @name Constants and macros for entire ENET_RMON_T_P_GTE2048 register
04838  */
04839 /*@{*/
04840 #define HW_ENET_RMON_T_P_GTE2048_ADDR(x) ((x) + 0x240U)
04841 
04842 #define HW_ENET_RMON_T_P_GTE2048(x) (*(__I hw_enet_rmon_t_p_gte2048_t *) HW_ENET_RMON_T_P_GTE2048_ADDR(x))
04843 #define HW_ENET_RMON_T_P_GTE2048_RD(x) (ADDRESS_READ(hw_enet_rmon_t_p_gte2048_t, HW_ENET_RMON_T_P_GTE2048_ADDR(x)))
04844 /*@}*/
04845 
04846 /*
04847  * Constants & macros for individual ENET_RMON_T_P_GTE2048 bitfields
04848  */
04849 
04850 /*!
04851  * @name Register ENET_RMON_T_P_GTE2048, field TXPKTS[15:0] (RO)
04852  */
04853 /*@{*/
04854 #define BP_ENET_RMON_T_P_GTE2048_TXPKTS (0U) /*!< Bit position for ENET_RMON_T_P_GTE2048_TXPKTS. */
04855 #define BM_ENET_RMON_T_P_GTE2048_TXPKTS (0x0000FFFFU) /*!< Bit mask for ENET_RMON_T_P_GTE2048_TXPKTS. */
04856 #define BS_ENET_RMON_T_P_GTE2048_TXPKTS (16U) /*!< Bit field size in bits for ENET_RMON_T_P_GTE2048_TXPKTS. */
04857 
04858 /*! @brief Read current value of the ENET_RMON_T_P_GTE2048_TXPKTS field. */
04859 #define BR_ENET_RMON_T_P_GTE2048_TXPKTS(x) (UNION_READ(hw_enet_rmon_t_p_gte2048_t, HW_ENET_RMON_T_P_GTE2048_ADDR(x), U, B.TXPKTS))
04860 /*@}*/
04861 
04862 /*******************************************************************************
04863  * HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register
04864  ******************************************************************************/
04865 
04866 /*!
04867  * @brief HW_ENET_RMON_T_OCTETS - Tx Octets Statistic Register (RO)
04868  *
04869  * Reset value: 0x00000000U
04870  */
04871 typedef union _hw_enet_rmon_t_octets
04872 {
04873     uint32_t U;
04874     struct _hw_enet_rmon_t_octets_bitfields
04875     {
04876         uint32_t TXOCTS : 32;          /*!< [31:0] Octet count */
04877     } B;
04878 } hw_enet_rmon_t_octets_t;
04879 
04880 /*!
04881  * @name Constants and macros for entire ENET_RMON_T_OCTETS register
04882  */
04883 /*@{*/
04884 #define HW_ENET_RMON_T_OCTETS_ADDR(x) ((x) + 0x244U)
04885 
04886 #define HW_ENET_RMON_T_OCTETS(x) (*(__I hw_enet_rmon_t_octets_t *) HW_ENET_RMON_T_OCTETS_ADDR(x))
04887 #define HW_ENET_RMON_T_OCTETS_RD(x) (ADDRESS_READ(hw_enet_rmon_t_octets_t, HW_ENET_RMON_T_OCTETS_ADDR(x)))
04888 /*@}*/
04889 
04890 /*
04891  * Constants & macros for individual ENET_RMON_T_OCTETS bitfields
04892  */
04893 
04894 /*!
04895  * @name Register ENET_RMON_T_OCTETS, field TXOCTS[31:0] (RO)
04896  */
04897 /*@{*/
04898 #define BP_ENET_RMON_T_OCTETS_TXOCTS (0U)  /*!< Bit position for ENET_RMON_T_OCTETS_TXOCTS. */
04899 #define BM_ENET_RMON_T_OCTETS_TXOCTS (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_T_OCTETS_TXOCTS. */
04900 #define BS_ENET_RMON_T_OCTETS_TXOCTS (32U) /*!< Bit field size in bits for ENET_RMON_T_OCTETS_TXOCTS. */
04901 
04902 /*! @brief Read current value of the ENET_RMON_T_OCTETS_TXOCTS field. */
04903 #define BR_ENET_RMON_T_OCTETS_TXOCTS(x) (HW_ENET_RMON_T_OCTETS(x).U)
04904 /*@}*/
04905 
04906 /*******************************************************************************
04907  * HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register
04908  ******************************************************************************/
04909 
04910 /*!
04911  * @brief HW_ENET_IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register (RO)
04912  *
04913  * Reset value: 0x00000000U
04914  */
04915 typedef union _hw_enet_ieee_t_frame_ok
04916 {
04917     uint32_t U;
04918     struct _hw_enet_ieee_t_frame_ok_bitfields
04919     {
04920         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
04921         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04922     } B;
04923 } hw_enet_ieee_t_frame_ok_t;
04924 
04925 /*!
04926  * @name Constants and macros for entire ENET_IEEE_T_FRAME_OK register
04927  */
04928 /*@{*/
04929 #define HW_ENET_IEEE_T_FRAME_OK_ADDR(x) ((x) + 0x24CU)
04930 
04931 #define HW_ENET_IEEE_T_FRAME_OK(x) (*(__I hw_enet_ieee_t_frame_ok_t *) HW_ENET_IEEE_T_FRAME_OK_ADDR(x))
04932 #define HW_ENET_IEEE_T_FRAME_OK_RD(x) (ADDRESS_READ(hw_enet_ieee_t_frame_ok_t, HW_ENET_IEEE_T_FRAME_OK_ADDR(x)))
04933 /*@}*/
04934 
04935 /*
04936  * Constants & macros for individual ENET_IEEE_T_FRAME_OK bitfields
04937  */
04938 
04939 /*!
04940  * @name Register ENET_IEEE_T_FRAME_OK, field COUNT[15:0] (RO)
04941  */
04942 /*@{*/
04943 #define BP_ENET_IEEE_T_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_FRAME_OK_COUNT. */
04944 #define BM_ENET_IEEE_T_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FRAME_OK_COUNT. */
04945 #define BS_ENET_IEEE_T_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_T_FRAME_OK_COUNT. */
04946 
04947 /*! @brief Read current value of the ENET_IEEE_T_FRAME_OK_COUNT field. */
04948 #define BR_ENET_IEEE_T_FRAME_OK_COUNT(x) (UNION_READ(hw_enet_ieee_t_frame_ok_t, HW_ENET_IEEE_T_FRAME_OK_ADDR(x), U, B.COUNT))
04949 /*@}*/
04950 
04951 /*******************************************************************************
04952  * HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register
04953  ******************************************************************************/
04954 
04955 /*!
04956  * @brief HW_ENET_IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register (RO)
04957  *
04958  * Reset value: 0x00000000U
04959  */
04960 typedef union _hw_enet_ieee_t_1col
04961 {
04962     uint32_t U;
04963     struct _hw_enet_ieee_t_1col_bitfields
04964     {
04965         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
04966         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
04967     } B;
04968 } hw_enet_ieee_t_1col_t;
04969 
04970 /*!
04971  * @name Constants and macros for entire ENET_IEEE_T_1COL register
04972  */
04973 /*@{*/
04974 #define HW_ENET_IEEE_T_1COL_ADDR(x) ((x) + 0x250U)
04975 
04976 #define HW_ENET_IEEE_T_1COL(x)   (*(__I hw_enet_ieee_t_1col_t *) HW_ENET_IEEE_T_1COL_ADDR(x))
04977 #define HW_ENET_IEEE_T_1COL_RD(x) (ADDRESS_READ(hw_enet_ieee_t_1col_t, HW_ENET_IEEE_T_1COL_ADDR(x)))
04978 /*@}*/
04979 
04980 /*
04981  * Constants & macros for individual ENET_IEEE_T_1COL bitfields
04982  */
04983 
04984 /*!
04985  * @name Register ENET_IEEE_T_1COL, field COUNT[15:0] (RO)
04986  */
04987 /*@{*/
04988 #define BP_ENET_IEEE_T_1COL_COUNT (0U)     /*!< Bit position for ENET_IEEE_T_1COL_COUNT. */
04989 #define BM_ENET_IEEE_T_1COL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_1COL_COUNT. */
04990 #define BS_ENET_IEEE_T_1COL_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_T_1COL_COUNT. */
04991 
04992 /*! @brief Read current value of the ENET_IEEE_T_1COL_COUNT field. */
04993 #define BR_ENET_IEEE_T_1COL_COUNT(x) (UNION_READ(hw_enet_ieee_t_1col_t, HW_ENET_IEEE_T_1COL_ADDR(x), U, B.COUNT))
04994 /*@}*/
04995 
04996 /*******************************************************************************
04997  * HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register
04998  ******************************************************************************/
04999 
05000 /*!
05001  * @brief HW_ENET_IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register (RO)
05002  *
05003  * Reset value: 0x00000000U
05004  */
05005 typedef union _hw_enet_ieee_t_mcol
05006 {
05007     uint32_t U;
05008     struct _hw_enet_ieee_t_mcol_bitfields
05009     {
05010         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05011         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05012     } B;
05013 } hw_enet_ieee_t_mcol_t;
05014 
05015 /*!
05016  * @name Constants and macros for entire ENET_IEEE_T_MCOL register
05017  */
05018 /*@{*/
05019 #define HW_ENET_IEEE_T_MCOL_ADDR(x) ((x) + 0x254U)
05020 
05021 #define HW_ENET_IEEE_T_MCOL(x)   (*(__I hw_enet_ieee_t_mcol_t *) HW_ENET_IEEE_T_MCOL_ADDR(x))
05022 #define HW_ENET_IEEE_T_MCOL_RD(x) (ADDRESS_READ(hw_enet_ieee_t_mcol_t, HW_ENET_IEEE_T_MCOL_ADDR(x)))
05023 /*@}*/
05024 
05025 /*
05026  * Constants & macros for individual ENET_IEEE_T_MCOL bitfields
05027  */
05028 
05029 /*!
05030  * @name Register ENET_IEEE_T_MCOL, field COUNT[15:0] (RO)
05031  */
05032 /*@{*/
05033 #define BP_ENET_IEEE_T_MCOL_COUNT (0U)     /*!< Bit position for ENET_IEEE_T_MCOL_COUNT. */
05034 #define BM_ENET_IEEE_T_MCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MCOL_COUNT. */
05035 #define BS_ENET_IEEE_T_MCOL_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_T_MCOL_COUNT. */
05036 
05037 /*! @brief Read current value of the ENET_IEEE_T_MCOL_COUNT field. */
05038 #define BR_ENET_IEEE_T_MCOL_COUNT(x) (UNION_READ(hw_enet_ieee_t_mcol_t, HW_ENET_IEEE_T_MCOL_ADDR(x), U, B.COUNT))
05039 /*@}*/
05040 
05041 /*******************************************************************************
05042  * HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register
05043  ******************************************************************************/
05044 
05045 /*!
05046  * @brief HW_ENET_IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register (RO)
05047  *
05048  * Reset value: 0x00000000U
05049  */
05050 typedef union _hw_enet_ieee_t_def
05051 {
05052     uint32_t U;
05053     struct _hw_enet_ieee_t_def_bitfields
05054     {
05055         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05056         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05057     } B;
05058 } hw_enet_ieee_t_def_t;
05059 
05060 /*!
05061  * @name Constants and macros for entire ENET_IEEE_T_DEF register
05062  */
05063 /*@{*/
05064 #define HW_ENET_IEEE_T_DEF_ADDR(x) ((x) + 0x258U)
05065 
05066 #define HW_ENET_IEEE_T_DEF(x)    (*(__I hw_enet_ieee_t_def_t *) HW_ENET_IEEE_T_DEF_ADDR(x))
05067 #define HW_ENET_IEEE_T_DEF_RD(x) (ADDRESS_READ(hw_enet_ieee_t_def_t, HW_ENET_IEEE_T_DEF_ADDR(x)))
05068 /*@}*/
05069 
05070 /*
05071  * Constants & macros for individual ENET_IEEE_T_DEF bitfields
05072  */
05073 
05074 /*!
05075  * @name Register ENET_IEEE_T_DEF, field COUNT[15:0] (RO)
05076  */
05077 /*@{*/
05078 #define BP_ENET_IEEE_T_DEF_COUNT (0U)      /*!< Bit position for ENET_IEEE_T_DEF_COUNT. */
05079 #define BM_ENET_IEEE_T_DEF_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_DEF_COUNT. */
05080 #define BS_ENET_IEEE_T_DEF_COUNT (16U)     /*!< Bit field size in bits for ENET_IEEE_T_DEF_COUNT. */
05081 
05082 /*! @brief Read current value of the ENET_IEEE_T_DEF_COUNT field. */
05083 #define BR_ENET_IEEE_T_DEF_COUNT(x) (UNION_READ(hw_enet_ieee_t_def_t, HW_ENET_IEEE_T_DEF_ADDR(x), U, B.COUNT))
05084 /*@}*/
05085 
05086 /*******************************************************************************
05087  * HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register
05088  ******************************************************************************/
05089 
05090 /*!
05091  * @brief HW_ENET_IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register (RO)
05092  *
05093  * Reset value: 0x00000000U
05094  */
05095 typedef union _hw_enet_ieee_t_lcol
05096 {
05097     uint32_t U;
05098     struct _hw_enet_ieee_t_lcol_bitfields
05099     {
05100         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05101         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05102     } B;
05103 } hw_enet_ieee_t_lcol_t;
05104 
05105 /*!
05106  * @name Constants and macros for entire ENET_IEEE_T_LCOL register
05107  */
05108 /*@{*/
05109 #define HW_ENET_IEEE_T_LCOL_ADDR(x) ((x) + 0x25CU)
05110 
05111 #define HW_ENET_IEEE_T_LCOL(x)   (*(__I hw_enet_ieee_t_lcol_t *) HW_ENET_IEEE_T_LCOL_ADDR(x))
05112 #define HW_ENET_IEEE_T_LCOL_RD(x) (ADDRESS_READ(hw_enet_ieee_t_lcol_t, HW_ENET_IEEE_T_LCOL_ADDR(x)))
05113 /*@}*/
05114 
05115 /*
05116  * Constants & macros for individual ENET_IEEE_T_LCOL bitfields
05117  */
05118 
05119 /*!
05120  * @name Register ENET_IEEE_T_LCOL, field COUNT[15:0] (RO)
05121  */
05122 /*@{*/
05123 #define BP_ENET_IEEE_T_LCOL_COUNT (0U)     /*!< Bit position for ENET_IEEE_T_LCOL_COUNT. */
05124 #define BM_ENET_IEEE_T_LCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_LCOL_COUNT. */
05125 #define BS_ENET_IEEE_T_LCOL_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_T_LCOL_COUNT. */
05126 
05127 /*! @brief Read current value of the ENET_IEEE_T_LCOL_COUNT field. */
05128 #define BR_ENET_IEEE_T_LCOL_COUNT(x) (UNION_READ(hw_enet_ieee_t_lcol_t, HW_ENET_IEEE_T_LCOL_ADDR(x), U, B.COUNT))
05129 /*@}*/
05130 
05131 /*******************************************************************************
05132  * HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register
05133  ******************************************************************************/
05134 
05135 /*!
05136  * @brief HW_ENET_IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register (RO)
05137  *
05138  * Reset value: 0x00000000U
05139  */
05140 typedef union _hw_enet_ieee_t_excol
05141 {
05142     uint32_t U;
05143     struct _hw_enet_ieee_t_excol_bitfields
05144     {
05145         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05146         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05147     } B;
05148 } hw_enet_ieee_t_excol_t;
05149 
05150 /*!
05151  * @name Constants and macros for entire ENET_IEEE_T_EXCOL register
05152  */
05153 /*@{*/
05154 #define HW_ENET_IEEE_T_EXCOL_ADDR(x) ((x) + 0x260U)
05155 
05156 #define HW_ENET_IEEE_T_EXCOL(x)  (*(__I hw_enet_ieee_t_excol_t *) HW_ENET_IEEE_T_EXCOL_ADDR(x))
05157 #define HW_ENET_IEEE_T_EXCOL_RD(x) (ADDRESS_READ(hw_enet_ieee_t_excol_t, HW_ENET_IEEE_T_EXCOL_ADDR(x)))
05158 /*@}*/
05159 
05160 /*
05161  * Constants & macros for individual ENET_IEEE_T_EXCOL bitfields
05162  */
05163 
05164 /*!
05165  * @name Register ENET_IEEE_T_EXCOL, field COUNT[15:0] (RO)
05166  */
05167 /*@{*/
05168 #define BP_ENET_IEEE_T_EXCOL_COUNT (0U)    /*!< Bit position for ENET_IEEE_T_EXCOL_COUNT. */
05169 #define BM_ENET_IEEE_T_EXCOL_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_EXCOL_COUNT. */
05170 #define BS_ENET_IEEE_T_EXCOL_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_T_EXCOL_COUNT. */
05171 
05172 /*! @brief Read current value of the ENET_IEEE_T_EXCOL_COUNT field. */
05173 #define BR_ENET_IEEE_T_EXCOL_COUNT(x) (UNION_READ(hw_enet_ieee_t_excol_t, HW_ENET_IEEE_T_EXCOL_ADDR(x), U, B.COUNT))
05174 /*@}*/
05175 
05176 /*******************************************************************************
05177  * HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register
05178  ******************************************************************************/
05179 
05180 /*!
05181  * @brief HW_ENET_IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register (RO)
05182  *
05183  * Reset value: 0x00000000U
05184  */
05185 typedef union _hw_enet_ieee_t_macerr
05186 {
05187     uint32_t U;
05188     struct _hw_enet_ieee_t_macerr_bitfields
05189     {
05190         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05191         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05192     } B;
05193 } hw_enet_ieee_t_macerr_t;
05194 
05195 /*!
05196  * @name Constants and macros for entire ENET_IEEE_T_MACERR register
05197  */
05198 /*@{*/
05199 #define HW_ENET_IEEE_T_MACERR_ADDR(x) ((x) + 0x264U)
05200 
05201 #define HW_ENET_IEEE_T_MACERR(x) (*(__I hw_enet_ieee_t_macerr_t *) HW_ENET_IEEE_T_MACERR_ADDR(x))
05202 #define HW_ENET_IEEE_T_MACERR_RD(x) (ADDRESS_READ(hw_enet_ieee_t_macerr_t, HW_ENET_IEEE_T_MACERR_ADDR(x)))
05203 /*@}*/
05204 
05205 /*
05206  * Constants & macros for individual ENET_IEEE_T_MACERR bitfields
05207  */
05208 
05209 /*!
05210  * @name Register ENET_IEEE_T_MACERR, field COUNT[15:0] (RO)
05211  */
05212 /*@{*/
05213 #define BP_ENET_IEEE_T_MACERR_COUNT (0U)   /*!< Bit position for ENET_IEEE_T_MACERR_COUNT. */
05214 #define BM_ENET_IEEE_T_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_MACERR_COUNT. */
05215 #define BS_ENET_IEEE_T_MACERR_COUNT (16U)  /*!< Bit field size in bits for ENET_IEEE_T_MACERR_COUNT. */
05216 
05217 /*! @brief Read current value of the ENET_IEEE_T_MACERR_COUNT field. */
05218 #define BR_ENET_IEEE_T_MACERR_COUNT(x) (UNION_READ(hw_enet_ieee_t_macerr_t, HW_ENET_IEEE_T_MACERR_ADDR(x), U, B.COUNT))
05219 /*@}*/
05220 
05221 /*******************************************************************************
05222  * HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register
05223  ******************************************************************************/
05224 
05225 /*!
05226  * @brief HW_ENET_IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register (RO)
05227  *
05228  * Reset value: 0x00000000U
05229  */
05230 typedef union _hw_enet_ieee_t_cserr
05231 {
05232     uint32_t U;
05233     struct _hw_enet_ieee_t_cserr_bitfields
05234     {
05235         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05236         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05237     } B;
05238 } hw_enet_ieee_t_cserr_t;
05239 
05240 /*!
05241  * @name Constants and macros for entire ENET_IEEE_T_CSERR register
05242  */
05243 /*@{*/
05244 #define HW_ENET_IEEE_T_CSERR_ADDR(x) ((x) + 0x268U)
05245 
05246 #define HW_ENET_IEEE_T_CSERR(x)  (*(__I hw_enet_ieee_t_cserr_t *) HW_ENET_IEEE_T_CSERR_ADDR(x))
05247 #define HW_ENET_IEEE_T_CSERR_RD(x) (ADDRESS_READ(hw_enet_ieee_t_cserr_t, HW_ENET_IEEE_T_CSERR_ADDR(x)))
05248 /*@}*/
05249 
05250 /*
05251  * Constants & macros for individual ENET_IEEE_T_CSERR bitfields
05252  */
05253 
05254 /*!
05255  * @name Register ENET_IEEE_T_CSERR, field COUNT[15:0] (RO)
05256  */
05257 /*@{*/
05258 #define BP_ENET_IEEE_T_CSERR_COUNT (0U)    /*!< Bit position for ENET_IEEE_T_CSERR_COUNT. */
05259 #define BM_ENET_IEEE_T_CSERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_CSERR_COUNT. */
05260 #define BS_ENET_IEEE_T_CSERR_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_T_CSERR_COUNT. */
05261 
05262 /*! @brief Read current value of the ENET_IEEE_T_CSERR_COUNT field. */
05263 #define BR_ENET_IEEE_T_CSERR_COUNT(x) (UNION_READ(hw_enet_ieee_t_cserr_t, HW_ENET_IEEE_T_CSERR_ADDR(x), U, B.COUNT))
05264 /*@}*/
05265 
05266 /*******************************************************************************
05267  * HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register
05268  ******************************************************************************/
05269 
05270 /*!
05271  * @brief HW_ENET_IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register (RO)
05272  *
05273  * Reset value: 0x00000000U
05274  */
05275 typedef union _hw_enet_ieee_t_fdxfc
05276 {
05277     uint32_t U;
05278     struct _hw_enet_ieee_t_fdxfc_bitfields
05279     {
05280         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
05281         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05282     } B;
05283 } hw_enet_ieee_t_fdxfc_t;
05284 
05285 /*!
05286  * @name Constants and macros for entire ENET_IEEE_T_FDXFC register
05287  */
05288 /*@{*/
05289 #define HW_ENET_IEEE_T_FDXFC_ADDR(x) ((x) + 0x270U)
05290 
05291 #define HW_ENET_IEEE_T_FDXFC(x)  (*(__I hw_enet_ieee_t_fdxfc_t *) HW_ENET_IEEE_T_FDXFC_ADDR(x))
05292 #define HW_ENET_IEEE_T_FDXFC_RD(x) (ADDRESS_READ(hw_enet_ieee_t_fdxfc_t, HW_ENET_IEEE_T_FDXFC_ADDR(x)))
05293 /*@}*/
05294 
05295 /*
05296  * Constants & macros for individual ENET_IEEE_T_FDXFC bitfields
05297  */
05298 
05299 /*!
05300  * @name Register ENET_IEEE_T_FDXFC, field COUNT[15:0] (RO)
05301  */
05302 /*@{*/
05303 #define BP_ENET_IEEE_T_FDXFC_COUNT (0U)    /*!< Bit position for ENET_IEEE_T_FDXFC_COUNT. */
05304 #define BM_ENET_IEEE_T_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_T_FDXFC_COUNT. */
05305 #define BS_ENET_IEEE_T_FDXFC_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_T_FDXFC_COUNT. */
05306 
05307 /*! @brief Read current value of the ENET_IEEE_T_FDXFC_COUNT field. */
05308 #define BR_ENET_IEEE_T_FDXFC_COUNT(x) (UNION_READ(hw_enet_ieee_t_fdxfc_t, HW_ENET_IEEE_T_FDXFC_ADDR(x), U, B.COUNT))
05309 /*@}*/
05310 
05311 /*******************************************************************************
05312  * HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register
05313  ******************************************************************************/
05314 
05315 /*!
05316  * @brief HW_ENET_IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register (RO)
05317  *
05318  * Reset value: 0x00000000U
05319  *
05320  * Counts total octets (includes header and FCS fields).
05321  */
05322 typedef union _hw_enet_ieee_t_octets_ok
05323 {
05324     uint32_t U;
05325     struct _hw_enet_ieee_t_octets_ok_bitfields
05326     {
05327         uint32_t COUNT : 32;           /*!< [31:0] Octet count */
05328     } B;
05329 } hw_enet_ieee_t_octets_ok_t;
05330 
05331 /*!
05332  * @name Constants and macros for entire ENET_IEEE_T_OCTETS_OK register
05333  */
05334 /*@{*/
05335 #define HW_ENET_IEEE_T_OCTETS_OK_ADDR(x) ((x) + 0x274U)
05336 
05337 #define HW_ENET_IEEE_T_OCTETS_OK(x) (*(__I hw_enet_ieee_t_octets_ok_t *) HW_ENET_IEEE_T_OCTETS_OK_ADDR(x))
05338 #define HW_ENET_IEEE_T_OCTETS_OK_RD(x) (ADDRESS_READ(hw_enet_ieee_t_octets_ok_t, HW_ENET_IEEE_T_OCTETS_OK_ADDR(x)))
05339 /*@}*/
05340 
05341 /*
05342  * Constants & macros for individual ENET_IEEE_T_OCTETS_OK bitfields
05343  */
05344 
05345 /*!
05346  * @name Register ENET_IEEE_T_OCTETS_OK, field COUNT[31:0] (RO)
05347  */
05348 /*@{*/
05349 #define BP_ENET_IEEE_T_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_T_OCTETS_OK_COUNT. */
05350 #define BM_ENET_IEEE_T_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_T_OCTETS_OK_COUNT. */
05351 #define BS_ENET_IEEE_T_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_T_OCTETS_OK_COUNT. */
05352 
05353 /*! @brief Read current value of the ENET_IEEE_T_OCTETS_OK_COUNT field. */
05354 #define BR_ENET_IEEE_T_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_T_OCTETS_OK(x).U)
05355 /*@}*/
05356 
05357 /*******************************************************************************
05358  * HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register
05359  ******************************************************************************/
05360 
05361 /*!
05362  * @brief HW_ENET_RMON_R_PACKETS - Rx Packet Count Statistic Register (RO)
05363  *
05364  * Reset value: 0x00000000U
05365  */
05366 typedef union _hw_enet_rmon_r_packets
05367 {
05368     uint32_t U;
05369     struct _hw_enet_rmon_r_packets_bitfields
05370     {
05371         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05372         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05373     } B;
05374 } hw_enet_rmon_r_packets_t;
05375 
05376 /*!
05377  * @name Constants and macros for entire ENET_RMON_R_PACKETS register
05378  */
05379 /*@{*/
05380 #define HW_ENET_RMON_R_PACKETS_ADDR(x) ((x) + 0x284U)
05381 
05382 #define HW_ENET_RMON_R_PACKETS(x) (*(__I hw_enet_rmon_r_packets_t *) HW_ENET_RMON_R_PACKETS_ADDR(x))
05383 #define HW_ENET_RMON_R_PACKETS_RD(x) (ADDRESS_READ(hw_enet_rmon_r_packets_t, HW_ENET_RMON_R_PACKETS_ADDR(x)))
05384 /*@}*/
05385 
05386 /*
05387  * Constants & macros for individual ENET_RMON_R_PACKETS bitfields
05388  */
05389 
05390 /*!
05391  * @name Register ENET_RMON_R_PACKETS, field COUNT[15:0] (RO)
05392  */
05393 /*@{*/
05394 #define BP_ENET_RMON_R_PACKETS_COUNT (0U)  /*!< Bit position for ENET_RMON_R_PACKETS_COUNT. */
05395 #define BM_ENET_RMON_R_PACKETS_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_PACKETS_COUNT. */
05396 #define BS_ENET_RMON_R_PACKETS_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_PACKETS_COUNT. */
05397 
05398 /*! @brief Read current value of the ENET_RMON_R_PACKETS_COUNT field. */
05399 #define BR_ENET_RMON_R_PACKETS_COUNT(x) (UNION_READ(hw_enet_rmon_r_packets_t, HW_ENET_RMON_R_PACKETS_ADDR(x), U, B.COUNT))
05400 /*@}*/
05401 
05402 /*******************************************************************************
05403  * HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register
05404  ******************************************************************************/
05405 
05406 /*!
05407  * @brief HW_ENET_RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register (RO)
05408  *
05409  * Reset value: 0x00000000U
05410  */
05411 typedef union _hw_enet_rmon_r_bc_pkt
05412 {
05413     uint32_t U;
05414     struct _hw_enet_rmon_r_bc_pkt_bitfields
05415     {
05416         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05417         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05418     } B;
05419 } hw_enet_rmon_r_bc_pkt_t;
05420 
05421 /*!
05422  * @name Constants and macros for entire ENET_RMON_R_BC_PKT register
05423  */
05424 /*@{*/
05425 #define HW_ENET_RMON_R_BC_PKT_ADDR(x) ((x) + 0x288U)
05426 
05427 #define HW_ENET_RMON_R_BC_PKT(x) (*(__I hw_enet_rmon_r_bc_pkt_t *) HW_ENET_RMON_R_BC_PKT_ADDR(x))
05428 #define HW_ENET_RMON_R_BC_PKT_RD(x) (ADDRESS_READ(hw_enet_rmon_r_bc_pkt_t, HW_ENET_RMON_R_BC_PKT_ADDR(x)))
05429 /*@}*/
05430 
05431 /*
05432  * Constants & macros for individual ENET_RMON_R_BC_PKT bitfields
05433  */
05434 
05435 /*!
05436  * @name Register ENET_RMON_R_BC_PKT, field COUNT[15:0] (RO)
05437  */
05438 /*@{*/
05439 #define BP_ENET_RMON_R_BC_PKT_COUNT (0U)   /*!< Bit position for ENET_RMON_R_BC_PKT_COUNT. */
05440 #define BM_ENET_RMON_R_BC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_BC_PKT_COUNT. */
05441 #define BS_ENET_RMON_R_BC_PKT_COUNT (16U)  /*!< Bit field size in bits for ENET_RMON_R_BC_PKT_COUNT. */
05442 
05443 /*! @brief Read current value of the ENET_RMON_R_BC_PKT_COUNT field. */
05444 #define BR_ENET_RMON_R_BC_PKT_COUNT(x) (UNION_READ(hw_enet_rmon_r_bc_pkt_t, HW_ENET_RMON_R_BC_PKT_ADDR(x), U, B.COUNT))
05445 /*@}*/
05446 
05447 /*******************************************************************************
05448  * HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register
05449  ******************************************************************************/
05450 
05451 /*!
05452  * @brief HW_ENET_RMON_R_MC_PKT - Rx Multicast Packets Statistic Register (RO)
05453  *
05454  * Reset value: 0x00000000U
05455  */
05456 typedef union _hw_enet_rmon_r_mc_pkt
05457 {
05458     uint32_t U;
05459     struct _hw_enet_rmon_r_mc_pkt_bitfields
05460     {
05461         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05462         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05463     } B;
05464 } hw_enet_rmon_r_mc_pkt_t;
05465 
05466 /*!
05467  * @name Constants and macros for entire ENET_RMON_R_MC_PKT register
05468  */
05469 /*@{*/
05470 #define HW_ENET_RMON_R_MC_PKT_ADDR(x) ((x) + 0x28CU)
05471 
05472 #define HW_ENET_RMON_R_MC_PKT(x) (*(__I hw_enet_rmon_r_mc_pkt_t *) HW_ENET_RMON_R_MC_PKT_ADDR(x))
05473 #define HW_ENET_RMON_R_MC_PKT_RD(x) (ADDRESS_READ(hw_enet_rmon_r_mc_pkt_t, HW_ENET_RMON_R_MC_PKT_ADDR(x)))
05474 /*@}*/
05475 
05476 /*
05477  * Constants & macros for individual ENET_RMON_R_MC_PKT bitfields
05478  */
05479 
05480 /*!
05481  * @name Register ENET_RMON_R_MC_PKT, field COUNT[15:0] (RO)
05482  */
05483 /*@{*/
05484 #define BP_ENET_RMON_R_MC_PKT_COUNT (0U)   /*!< Bit position for ENET_RMON_R_MC_PKT_COUNT. */
05485 #define BM_ENET_RMON_R_MC_PKT_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_MC_PKT_COUNT. */
05486 #define BS_ENET_RMON_R_MC_PKT_COUNT (16U)  /*!< Bit field size in bits for ENET_RMON_R_MC_PKT_COUNT. */
05487 
05488 /*! @brief Read current value of the ENET_RMON_R_MC_PKT_COUNT field. */
05489 #define BR_ENET_RMON_R_MC_PKT_COUNT(x) (UNION_READ(hw_enet_rmon_r_mc_pkt_t, HW_ENET_RMON_R_MC_PKT_ADDR(x), U, B.COUNT))
05490 /*@}*/
05491 
05492 /*******************************************************************************
05493  * HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register
05494  ******************************************************************************/
05495 
05496 /*!
05497  * @brief HW_ENET_RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register (RO)
05498  *
05499  * Reset value: 0x00000000U
05500  */
05501 typedef union _hw_enet_rmon_r_crc_align
05502 {
05503     uint32_t U;
05504     struct _hw_enet_rmon_r_crc_align_bitfields
05505     {
05506         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05507         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05508     } B;
05509 } hw_enet_rmon_r_crc_align_t;
05510 
05511 /*!
05512  * @name Constants and macros for entire ENET_RMON_R_CRC_ALIGN register
05513  */
05514 /*@{*/
05515 #define HW_ENET_RMON_R_CRC_ALIGN_ADDR(x) ((x) + 0x290U)
05516 
05517 #define HW_ENET_RMON_R_CRC_ALIGN(x) (*(__I hw_enet_rmon_r_crc_align_t *) HW_ENET_RMON_R_CRC_ALIGN_ADDR(x))
05518 #define HW_ENET_RMON_R_CRC_ALIGN_RD(x) (ADDRESS_READ(hw_enet_rmon_r_crc_align_t, HW_ENET_RMON_R_CRC_ALIGN_ADDR(x)))
05519 /*@}*/
05520 
05521 /*
05522  * Constants & macros for individual ENET_RMON_R_CRC_ALIGN bitfields
05523  */
05524 
05525 /*!
05526  * @name Register ENET_RMON_R_CRC_ALIGN, field COUNT[15:0] (RO)
05527  */
05528 /*@{*/
05529 #define BP_ENET_RMON_R_CRC_ALIGN_COUNT (0U) /*!< Bit position for ENET_RMON_R_CRC_ALIGN_COUNT. */
05530 #define BM_ENET_RMON_R_CRC_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_CRC_ALIGN_COUNT. */
05531 #define BS_ENET_RMON_R_CRC_ALIGN_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_CRC_ALIGN_COUNT. */
05532 
05533 /*! @brief Read current value of the ENET_RMON_R_CRC_ALIGN_COUNT field. */
05534 #define BR_ENET_RMON_R_CRC_ALIGN_COUNT(x) (UNION_READ(hw_enet_rmon_r_crc_align_t, HW_ENET_RMON_R_CRC_ALIGN_ADDR(x), U, B.COUNT))
05535 /*@}*/
05536 
05537 /*******************************************************************************
05538  * HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
05539  ******************************************************************************/
05540 
05541 /*!
05542  * @brief HW_ENET_RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register (RO)
05543  *
05544  * Reset value: 0x00000000U
05545  */
05546 typedef union _hw_enet_rmon_r_undersize
05547 {
05548     uint32_t U;
05549     struct _hw_enet_rmon_r_undersize_bitfields
05550     {
05551         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05552         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05553     } B;
05554 } hw_enet_rmon_r_undersize_t;
05555 
05556 /*!
05557  * @name Constants and macros for entire ENET_RMON_R_UNDERSIZE register
05558  */
05559 /*@{*/
05560 #define HW_ENET_RMON_R_UNDERSIZE_ADDR(x) ((x) + 0x294U)
05561 
05562 #define HW_ENET_RMON_R_UNDERSIZE(x) (*(__I hw_enet_rmon_r_undersize_t *) HW_ENET_RMON_R_UNDERSIZE_ADDR(x))
05563 #define HW_ENET_RMON_R_UNDERSIZE_RD(x) (ADDRESS_READ(hw_enet_rmon_r_undersize_t, HW_ENET_RMON_R_UNDERSIZE_ADDR(x)))
05564 /*@}*/
05565 
05566 /*
05567  * Constants & macros for individual ENET_RMON_R_UNDERSIZE bitfields
05568  */
05569 
05570 /*!
05571  * @name Register ENET_RMON_R_UNDERSIZE, field COUNT[15:0] (RO)
05572  */
05573 /*@{*/
05574 #define BP_ENET_RMON_R_UNDERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_UNDERSIZE_COUNT. */
05575 #define BM_ENET_RMON_R_UNDERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_UNDERSIZE_COUNT. */
05576 #define BS_ENET_RMON_R_UNDERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_UNDERSIZE_COUNT. */
05577 
05578 /*! @brief Read current value of the ENET_RMON_R_UNDERSIZE_COUNT field. */
05579 #define BR_ENET_RMON_R_UNDERSIZE_COUNT(x) (UNION_READ(hw_enet_rmon_r_undersize_t, HW_ENET_RMON_R_UNDERSIZE_ADDR(x), U, B.COUNT))
05580 /*@}*/
05581 
05582 /*******************************************************************************
05583  * HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register
05584  ******************************************************************************/
05585 
05586 /*!
05587  * @brief HW_ENET_RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (RO)
05588  *
05589  * Reset value: 0x00000000U
05590  */
05591 typedef union _hw_enet_rmon_r_oversize
05592 {
05593     uint32_t U;
05594     struct _hw_enet_rmon_r_oversize_bitfields
05595     {
05596         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05597         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05598     } B;
05599 } hw_enet_rmon_r_oversize_t;
05600 
05601 /*!
05602  * @name Constants and macros for entire ENET_RMON_R_OVERSIZE register
05603  */
05604 /*@{*/
05605 #define HW_ENET_RMON_R_OVERSIZE_ADDR(x) ((x) + 0x298U)
05606 
05607 #define HW_ENET_RMON_R_OVERSIZE(x) (*(__I hw_enet_rmon_r_oversize_t *) HW_ENET_RMON_R_OVERSIZE_ADDR(x))
05608 #define HW_ENET_RMON_R_OVERSIZE_RD(x) (ADDRESS_READ(hw_enet_rmon_r_oversize_t, HW_ENET_RMON_R_OVERSIZE_ADDR(x)))
05609 /*@}*/
05610 
05611 /*
05612  * Constants & macros for individual ENET_RMON_R_OVERSIZE bitfields
05613  */
05614 
05615 /*!
05616  * @name Register ENET_RMON_R_OVERSIZE, field COUNT[15:0] (RO)
05617  */
05618 /*@{*/
05619 #define BP_ENET_RMON_R_OVERSIZE_COUNT (0U) /*!< Bit position for ENET_RMON_R_OVERSIZE_COUNT. */
05620 #define BM_ENET_RMON_R_OVERSIZE_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_OVERSIZE_COUNT. */
05621 #define BS_ENET_RMON_R_OVERSIZE_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_OVERSIZE_COUNT. */
05622 
05623 /*! @brief Read current value of the ENET_RMON_R_OVERSIZE_COUNT field. */
05624 #define BR_ENET_RMON_R_OVERSIZE_COUNT(x) (UNION_READ(hw_enet_rmon_r_oversize_t, HW_ENET_RMON_R_OVERSIZE_ADDR(x), U, B.COUNT))
05625 /*@}*/
05626 
05627 /*******************************************************************************
05628  * HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register
05629  ******************************************************************************/
05630 
05631 /*!
05632  * @brief HW_ENET_RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (RO)
05633  *
05634  * Reset value: 0x00000000U
05635  */
05636 typedef union _hw_enet_rmon_r_frag
05637 {
05638     uint32_t U;
05639     struct _hw_enet_rmon_r_frag_bitfields
05640     {
05641         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05642         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05643     } B;
05644 } hw_enet_rmon_r_frag_t;
05645 
05646 /*!
05647  * @name Constants and macros for entire ENET_RMON_R_FRAG register
05648  */
05649 /*@{*/
05650 #define HW_ENET_RMON_R_FRAG_ADDR(x) ((x) + 0x29CU)
05651 
05652 #define HW_ENET_RMON_R_FRAG(x)   (*(__I hw_enet_rmon_r_frag_t *) HW_ENET_RMON_R_FRAG_ADDR(x))
05653 #define HW_ENET_RMON_R_FRAG_RD(x) (ADDRESS_READ(hw_enet_rmon_r_frag_t, HW_ENET_RMON_R_FRAG_ADDR(x)))
05654 /*@}*/
05655 
05656 /*
05657  * Constants & macros for individual ENET_RMON_R_FRAG bitfields
05658  */
05659 
05660 /*!
05661  * @name Register ENET_RMON_R_FRAG, field COUNT[15:0] (RO)
05662  */
05663 /*@{*/
05664 #define BP_ENET_RMON_R_FRAG_COUNT (0U)     /*!< Bit position for ENET_RMON_R_FRAG_COUNT. */
05665 #define BM_ENET_RMON_R_FRAG_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_FRAG_COUNT. */
05666 #define BS_ENET_RMON_R_FRAG_COUNT (16U)    /*!< Bit field size in bits for ENET_RMON_R_FRAG_COUNT. */
05667 
05668 /*! @brief Read current value of the ENET_RMON_R_FRAG_COUNT field. */
05669 #define BR_ENET_RMON_R_FRAG_COUNT(x) (UNION_READ(hw_enet_rmon_r_frag_t, HW_ENET_RMON_R_FRAG_ADDR(x), U, B.COUNT))
05670 /*@}*/
05671 
05672 /*******************************************************************************
05673  * HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register
05674  ******************************************************************************/
05675 
05676 /*!
05677  * @brief HW_ENET_RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (RO)
05678  *
05679  * Reset value: 0x00000000U
05680  */
05681 typedef union _hw_enet_rmon_r_jab
05682 {
05683     uint32_t U;
05684     struct _hw_enet_rmon_r_jab_bitfields
05685     {
05686         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05687         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05688     } B;
05689 } hw_enet_rmon_r_jab_t;
05690 
05691 /*!
05692  * @name Constants and macros for entire ENET_RMON_R_JAB register
05693  */
05694 /*@{*/
05695 #define HW_ENET_RMON_R_JAB_ADDR(x) ((x) + 0x2A0U)
05696 
05697 #define HW_ENET_RMON_R_JAB(x)    (*(__I hw_enet_rmon_r_jab_t *) HW_ENET_RMON_R_JAB_ADDR(x))
05698 #define HW_ENET_RMON_R_JAB_RD(x) (ADDRESS_READ(hw_enet_rmon_r_jab_t, HW_ENET_RMON_R_JAB_ADDR(x)))
05699 /*@}*/
05700 
05701 /*
05702  * Constants & macros for individual ENET_RMON_R_JAB bitfields
05703  */
05704 
05705 /*!
05706  * @name Register ENET_RMON_R_JAB, field COUNT[15:0] (RO)
05707  */
05708 /*@{*/
05709 #define BP_ENET_RMON_R_JAB_COUNT (0U)      /*!< Bit position for ENET_RMON_R_JAB_COUNT. */
05710 #define BM_ENET_RMON_R_JAB_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_JAB_COUNT. */
05711 #define BS_ENET_RMON_R_JAB_COUNT (16U)     /*!< Bit field size in bits for ENET_RMON_R_JAB_COUNT. */
05712 
05713 /*! @brief Read current value of the ENET_RMON_R_JAB_COUNT field. */
05714 #define BR_ENET_RMON_R_JAB_COUNT(x) (UNION_READ(hw_enet_rmon_r_jab_t, HW_ENET_RMON_R_JAB_ADDR(x), U, B.COUNT))
05715 /*@}*/
05716 
05717 /*******************************************************************************
05718  * HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register
05719  ******************************************************************************/
05720 
05721 /*!
05722  * @brief HW_ENET_RMON_R_P64 - Rx 64-Byte Packets Statistic Register (RO)
05723  *
05724  * Reset value: 0x00000000U
05725  */
05726 typedef union _hw_enet_rmon_r_p64
05727 {
05728     uint32_t U;
05729     struct _hw_enet_rmon_r_p64_bitfields
05730     {
05731         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05732         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05733     } B;
05734 } hw_enet_rmon_r_p64_t;
05735 
05736 /*!
05737  * @name Constants and macros for entire ENET_RMON_R_P64 register
05738  */
05739 /*@{*/
05740 #define HW_ENET_RMON_R_P64_ADDR(x) ((x) + 0x2A8U)
05741 
05742 #define HW_ENET_RMON_R_P64(x)    (*(__I hw_enet_rmon_r_p64_t *) HW_ENET_RMON_R_P64_ADDR(x))
05743 #define HW_ENET_RMON_R_P64_RD(x) (ADDRESS_READ(hw_enet_rmon_r_p64_t, HW_ENET_RMON_R_P64_ADDR(x)))
05744 /*@}*/
05745 
05746 /*
05747  * Constants & macros for individual ENET_RMON_R_P64 bitfields
05748  */
05749 
05750 /*!
05751  * @name Register ENET_RMON_R_P64, field COUNT[15:0] (RO)
05752  */
05753 /*@{*/
05754 #define BP_ENET_RMON_R_P64_COUNT (0U)      /*!< Bit position for ENET_RMON_R_P64_COUNT. */
05755 #define BM_ENET_RMON_R_P64_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P64_COUNT. */
05756 #define BS_ENET_RMON_R_P64_COUNT (16U)     /*!< Bit field size in bits for ENET_RMON_R_P64_COUNT. */
05757 
05758 /*! @brief Read current value of the ENET_RMON_R_P64_COUNT field. */
05759 #define BR_ENET_RMON_R_P64_COUNT(x) (UNION_READ(hw_enet_rmon_r_p64_t, HW_ENET_RMON_R_P64_ADDR(x), U, B.COUNT))
05760 /*@}*/
05761 
05762 /*******************************************************************************
05763  * HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register
05764  ******************************************************************************/
05765 
05766 /*!
05767  * @brief HW_ENET_RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register (RO)
05768  *
05769  * Reset value: 0x00000000U
05770  */
05771 typedef union _hw_enet_rmon_r_p65to127
05772 {
05773     uint32_t U;
05774     struct _hw_enet_rmon_r_p65to127_bitfields
05775     {
05776         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05777         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05778     } B;
05779 } hw_enet_rmon_r_p65to127_t;
05780 
05781 /*!
05782  * @name Constants and macros for entire ENET_RMON_R_P65TO127 register
05783  */
05784 /*@{*/
05785 #define HW_ENET_RMON_R_P65TO127_ADDR(x) ((x) + 0x2ACU)
05786 
05787 #define HW_ENET_RMON_R_P65TO127(x) (*(__I hw_enet_rmon_r_p65to127_t *) HW_ENET_RMON_R_P65TO127_ADDR(x))
05788 #define HW_ENET_RMON_R_P65TO127_RD(x) (ADDRESS_READ(hw_enet_rmon_r_p65to127_t, HW_ENET_RMON_R_P65TO127_ADDR(x)))
05789 /*@}*/
05790 
05791 /*
05792  * Constants & macros for individual ENET_RMON_R_P65TO127 bitfields
05793  */
05794 
05795 /*!
05796  * @name Register ENET_RMON_R_P65TO127, field COUNT[15:0] (RO)
05797  */
05798 /*@{*/
05799 #define BP_ENET_RMON_R_P65TO127_COUNT (0U) /*!< Bit position for ENET_RMON_R_P65TO127_COUNT. */
05800 #define BM_ENET_RMON_R_P65TO127_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P65TO127_COUNT. */
05801 #define BS_ENET_RMON_R_P65TO127_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P65TO127_COUNT. */
05802 
05803 /*! @brief Read current value of the ENET_RMON_R_P65TO127_COUNT field. */
05804 #define BR_ENET_RMON_R_P65TO127_COUNT(x) (UNION_READ(hw_enet_rmon_r_p65to127_t, HW_ENET_RMON_R_P65TO127_ADDR(x), U, B.COUNT))
05805 /*@}*/
05806 
05807 /*******************************************************************************
05808  * HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register
05809  ******************************************************************************/
05810 
05811 /*!
05812  * @brief HW_ENET_RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register (RO)
05813  *
05814  * Reset value: 0x00000000U
05815  */
05816 typedef union _hw_enet_rmon_r_p128to255
05817 {
05818     uint32_t U;
05819     struct _hw_enet_rmon_r_p128to255_bitfields
05820     {
05821         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05822         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05823     } B;
05824 } hw_enet_rmon_r_p128to255_t;
05825 
05826 /*!
05827  * @name Constants and macros for entire ENET_RMON_R_P128TO255 register
05828  */
05829 /*@{*/
05830 #define HW_ENET_RMON_R_P128TO255_ADDR(x) ((x) + 0x2B0U)
05831 
05832 #define HW_ENET_RMON_R_P128TO255(x) (*(__I hw_enet_rmon_r_p128to255_t *) HW_ENET_RMON_R_P128TO255_ADDR(x))
05833 #define HW_ENET_RMON_R_P128TO255_RD(x) (ADDRESS_READ(hw_enet_rmon_r_p128to255_t, HW_ENET_RMON_R_P128TO255_ADDR(x)))
05834 /*@}*/
05835 
05836 /*
05837  * Constants & macros for individual ENET_RMON_R_P128TO255 bitfields
05838  */
05839 
05840 /*!
05841  * @name Register ENET_RMON_R_P128TO255, field COUNT[15:0] (RO)
05842  */
05843 /*@{*/
05844 #define BP_ENET_RMON_R_P128TO255_COUNT (0U) /*!< Bit position for ENET_RMON_R_P128TO255_COUNT. */
05845 #define BM_ENET_RMON_R_P128TO255_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P128TO255_COUNT. */
05846 #define BS_ENET_RMON_R_P128TO255_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P128TO255_COUNT. */
05847 
05848 /*! @brief Read current value of the ENET_RMON_R_P128TO255_COUNT field. */
05849 #define BR_ENET_RMON_R_P128TO255_COUNT(x) (UNION_READ(hw_enet_rmon_r_p128to255_t, HW_ENET_RMON_R_P128TO255_ADDR(x), U, B.COUNT))
05850 /*@}*/
05851 
05852 /*******************************************************************************
05853  * HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register
05854  ******************************************************************************/
05855 
05856 /*!
05857  * @brief HW_ENET_RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register (RO)
05858  *
05859  * Reset value: 0x00000000U
05860  */
05861 typedef union _hw_enet_rmon_r_p256to511
05862 {
05863     uint32_t U;
05864     struct _hw_enet_rmon_r_p256to511_bitfields
05865     {
05866         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05867         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05868     } B;
05869 } hw_enet_rmon_r_p256to511_t;
05870 
05871 /*!
05872  * @name Constants and macros for entire ENET_RMON_R_P256TO511 register
05873  */
05874 /*@{*/
05875 #define HW_ENET_RMON_R_P256TO511_ADDR(x) ((x) + 0x2B4U)
05876 
05877 #define HW_ENET_RMON_R_P256TO511(x) (*(__I hw_enet_rmon_r_p256to511_t *) HW_ENET_RMON_R_P256TO511_ADDR(x))
05878 #define HW_ENET_RMON_R_P256TO511_RD(x) (ADDRESS_READ(hw_enet_rmon_r_p256to511_t, HW_ENET_RMON_R_P256TO511_ADDR(x)))
05879 /*@}*/
05880 
05881 /*
05882  * Constants & macros for individual ENET_RMON_R_P256TO511 bitfields
05883  */
05884 
05885 /*!
05886  * @name Register ENET_RMON_R_P256TO511, field COUNT[15:0] (RO)
05887  */
05888 /*@{*/
05889 #define BP_ENET_RMON_R_P256TO511_COUNT (0U) /*!< Bit position for ENET_RMON_R_P256TO511_COUNT. */
05890 #define BM_ENET_RMON_R_P256TO511_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P256TO511_COUNT. */
05891 #define BS_ENET_RMON_R_P256TO511_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P256TO511_COUNT. */
05892 
05893 /*! @brief Read current value of the ENET_RMON_R_P256TO511_COUNT field. */
05894 #define BR_ENET_RMON_R_P256TO511_COUNT(x) (UNION_READ(hw_enet_rmon_r_p256to511_t, HW_ENET_RMON_R_P256TO511_ADDR(x), U, B.COUNT))
05895 /*@}*/
05896 
05897 /*******************************************************************************
05898  * HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register
05899  ******************************************************************************/
05900 
05901 /*!
05902  * @brief HW_ENET_RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register (RO)
05903  *
05904  * Reset value: 0x00000000U
05905  */
05906 typedef union _hw_enet_rmon_r_p512to1023
05907 {
05908     uint32_t U;
05909     struct _hw_enet_rmon_r_p512to1023_bitfields
05910     {
05911         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05912         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05913     } B;
05914 } hw_enet_rmon_r_p512to1023_t;
05915 
05916 /*!
05917  * @name Constants and macros for entire ENET_RMON_R_P512TO1023 register
05918  */
05919 /*@{*/
05920 #define HW_ENET_RMON_R_P512TO1023_ADDR(x) ((x) + 0x2B8U)
05921 
05922 #define HW_ENET_RMON_R_P512TO1023(x) (*(__I hw_enet_rmon_r_p512to1023_t *) HW_ENET_RMON_R_P512TO1023_ADDR(x))
05923 #define HW_ENET_RMON_R_P512TO1023_RD(x) (ADDRESS_READ(hw_enet_rmon_r_p512to1023_t, HW_ENET_RMON_R_P512TO1023_ADDR(x)))
05924 /*@}*/
05925 
05926 /*
05927  * Constants & macros for individual ENET_RMON_R_P512TO1023 bitfields
05928  */
05929 
05930 /*!
05931  * @name Register ENET_RMON_R_P512TO1023, field COUNT[15:0] (RO)
05932  */
05933 /*@{*/
05934 #define BP_ENET_RMON_R_P512TO1023_COUNT (0U) /*!< Bit position for ENET_RMON_R_P512TO1023_COUNT. */
05935 #define BM_ENET_RMON_R_P512TO1023_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P512TO1023_COUNT. */
05936 #define BS_ENET_RMON_R_P512TO1023_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P512TO1023_COUNT. */
05937 
05938 /*! @brief Read current value of the ENET_RMON_R_P512TO1023_COUNT field. */
05939 #define BR_ENET_RMON_R_P512TO1023_COUNT(x) (UNION_READ(hw_enet_rmon_r_p512to1023_t, HW_ENET_RMON_R_P512TO1023_ADDR(x), U, B.COUNT))
05940 /*@}*/
05941 
05942 /*******************************************************************************
05943  * HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register
05944  ******************************************************************************/
05945 
05946 /*!
05947  * @brief HW_ENET_RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register (RO)
05948  *
05949  * Reset value: 0x00000000U
05950  */
05951 typedef union _hw_enet_rmon_r_p1024to2047
05952 {
05953     uint32_t U;
05954     struct _hw_enet_rmon_r_p1024to2047_bitfields
05955     {
05956         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
05957         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05958     } B;
05959 } hw_enet_rmon_r_p1024to2047_t;
05960 
05961 /*!
05962  * @name Constants and macros for entire ENET_RMON_R_P1024TO2047 register
05963  */
05964 /*@{*/
05965 #define HW_ENET_RMON_R_P1024TO2047_ADDR(x) ((x) + 0x2BCU)
05966 
05967 #define HW_ENET_RMON_R_P1024TO2047(x) (*(__I hw_enet_rmon_r_p1024to2047_t *) HW_ENET_RMON_R_P1024TO2047_ADDR(x))
05968 #define HW_ENET_RMON_R_P1024TO2047_RD(x) (ADDRESS_READ(hw_enet_rmon_r_p1024to2047_t, HW_ENET_RMON_R_P1024TO2047_ADDR(x)))
05969 /*@}*/
05970 
05971 /*
05972  * Constants & macros for individual ENET_RMON_R_P1024TO2047 bitfields
05973  */
05974 
05975 /*!
05976  * @name Register ENET_RMON_R_P1024TO2047, field COUNT[15:0] (RO)
05977  */
05978 /*@{*/
05979 #define BP_ENET_RMON_R_P1024TO2047_COUNT (0U) /*!< Bit position for ENET_RMON_R_P1024TO2047_COUNT. */
05980 #define BM_ENET_RMON_R_P1024TO2047_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P1024TO2047_COUNT. */
05981 #define BS_ENET_RMON_R_P1024TO2047_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P1024TO2047_COUNT. */
05982 
05983 /*! @brief Read current value of the ENET_RMON_R_P1024TO2047_COUNT field. */
05984 #define BR_ENET_RMON_R_P1024TO2047_COUNT(x) (UNION_READ(hw_enet_rmon_r_p1024to2047_t, HW_ENET_RMON_R_P1024TO2047_ADDR(x), U, B.COUNT))
05985 /*@}*/
05986 
05987 /*******************************************************************************
05988  * HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register
05989  ******************************************************************************/
05990 
05991 /*!
05992  * @brief HW_ENET_RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register (RO)
05993  *
05994  * Reset value: 0x00000000U
05995  */
05996 typedef union _hw_enet_rmon_r_p_gte2048
05997 {
05998     uint32_t U;
05999     struct _hw_enet_rmon_r_p_gte2048_bitfields
06000     {
06001         uint32_t COUNT : 16;           /*!< [15:0] Packet count */
06002         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06003     } B;
06004 } hw_enet_rmon_r_p_gte2048_t;
06005 
06006 /*!
06007  * @name Constants and macros for entire ENET_RMON_R_P_GTE2048 register
06008  */
06009 /*@{*/
06010 #define HW_ENET_RMON_R_P_GTE2048_ADDR(x) ((x) + 0x2C0U)
06011 
06012 #define HW_ENET_RMON_R_P_GTE2048(x) (*(__I hw_enet_rmon_r_p_gte2048_t *) HW_ENET_RMON_R_P_GTE2048_ADDR(x))
06013 #define HW_ENET_RMON_R_P_GTE2048_RD(x) (ADDRESS_READ(hw_enet_rmon_r_p_gte2048_t, HW_ENET_RMON_R_P_GTE2048_ADDR(x)))
06014 /*@}*/
06015 
06016 /*
06017  * Constants & macros for individual ENET_RMON_R_P_GTE2048 bitfields
06018  */
06019 
06020 /*!
06021  * @name Register ENET_RMON_R_P_GTE2048, field COUNT[15:0] (RO)
06022  */
06023 /*@{*/
06024 #define BP_ENET_RMON_R_P_GTE2048_COUNT (0U) /*!< Bit position for ENET_RMON_R_P_GTE2048_COUNT. */
06025 #define BM_ENET_RMON_R_P_GTE2048_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_RMON_R_P_GTE2048_COUNT. */
06026 #define BS_ENET_RMON_R_P_GTE2048_COUNT (16U) /*!< Bit field size in bits for ENET_RMON_R_P_GTE2048_COUNT. */
06027 
06028 /*! @brief Read current value of the ENET_RMON_R_P_GTE2048_COUNT field. */
06029 #define BR_ENET_RMON_R_P_GTE2048_COUNT(x) (UNION_READ(hw_enet_rmon_r_p_gte2048_t, HW_ENET_RMON_R_P_GTE2048_ADDR(x), U, B.COUNT))
06030 /*@}*/
06031 
06032 /*******************************************************************************
06033  * HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register
06034  ******************************************************************************/
06035 
06036 /*!
06037  * @brief HW_ENET_RMON_R_OCTETS - Rx Octets Statistic Register (RO)
06038  *
06039  * Reset value: 0x00000000U
06040  */
06041 typedef union _hw_enet_rmon_r_octets
06042 {
06043     uint32_t U;
06044     struct _hw_enet_rmon_r_octets_bitfields
06045     {
06046         uint32_t COUNT : 32;           /*!< [31:0] Octet count */
06047     } B;
06048 } hw_enet_rmon_r_octets_t;
06049 
06050 /*!
06051  * @name Constants and macros for entire ENET_RMON_R_OCTETS register
06052  */
06053 /*@{*/
06054 #define HW_ENET_RMON_R_OCTETS_ADDR(x) ((x) + 0x2C4U)
06055 
06056 #define HW_ENET_RMON_R_OCTETS(x) (*(__I hw_enet_rmon_r_octets_t *) HW_ENET_RMON_R_OCTETS_ADDR(x))
06057 #define HW_ENET_RMON_R_OCTETS_RD(x) (ADDRESS_READ(hw_enet_rmon_r_octets_t, HW_ENET_RMON_R_OCTETS_ADDR(x)))
06058 /*@}*/
06059 
06060 /*
06061  * Constants & macros for individual ENET_RMON_R_OCTETS bitfields
06062  */
06063 
06064 /*!
06065  * @name Register ENET_RMON_R_OCTETS, field COUNT[31:0] (RO)
06066  */
06067 /*@{*/
06068 #define BP_ENET_RMON_R_OCTETS_COUNT (0U)   /*!< Bit position for ENET_RMON_R_OCTETS_COUNT. */
06069 #define BM_ENET_RMON_R_OCTETS_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_RMON_R_OCTETS_COUNT. */
06070 #define BS_ENET_RMON_R_OCTETS_COUNT (32U)  /*!< Bit field size in bits for ENET_RMON_R_OCTETS_COUNT. */
06071 
06072 /*! @brief Read current value of the ENET_RMON_R_OCTETS_COUNT field. */
06073 #define BR_ENET_RMON_R_OCTETS_COUNT(x) (HW_ENET_RMON_R_OCTETS(x).U)
06074 /*@}*/
06075 
06076 /*******************************************************************************
06077  * HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register
06078  ******************************************************************************/
06079 
06080 /*!
06081  * @brief HW_ENET_IEEE_R_DROP - Frames not Counted Correctly Statistic Register (RO)
06082  *
06083  * Reset value: 0x00000000U
06084  *
06085  * Counter increments if a frame with invalid or missing SFD character is
06086  * detected and has been dropped. None of the other counters increments if this counter
06087  * increments.
06088  */
06089 typedef union _hw_enet_ieee_r_drop
06090 {
06091     uint32_t U;
06092     struct _hw_enet_ieee_r_drop_bitfields
06093     {
06094         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06095         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06096     } B;
06097 } hw_enet_ieee_r_drop_t;
06098 
06099 /*!
06100  * @name Constants and macros for entire ENET_IEEE_R_DROP register
06101  */
06102 /*@{*/
06103 #define HW_ENET_IEEE_R_DROP_ADDR(x) ((x) + 0x2C8U)
06104 
06105 #define HW_ENET_IEEE_R_DROP(x)   (*(__I hw_enet_ieee_r_drop_t *) HW_ENET_IEEE_R_DROP_ADDR(x))
06106 #define HW_ENET_IEEE_R_DROP_RD(x) (ADDRESS_READ(hw_enet_ieee_r_drop_t, HW_ENET_IEEE_R_DROP_ADDR(x)))
06107 /*@}*/
06108 
06109 /*
06110  * Constants & macros for individual ENET_IEEE_R_DROP bitfields
06111  */
06112 
06113 /*!
06114  * @name Register ENET_IEEE_R_DROP, field COUNT[15:0] (RO)
06115  */
06116 /*@{*/
06117 #define BP_ENET_IEEE_R_DROP_COUNT (0U)     /*!< Bit position for ENET_IEEE_R_DROP_COUNT. */
06118 #define BM_ENET_IEEE_R_DROP_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_DROP_COUNT. */
06119 #define BS_ENET_IEEE_R_DROP_COUNT (16U)    /*!< Bit field size in bits for ENET_IEEE_R_DROP_COUNT. */
06120 
06121 /*! @brief Read current value of the ENET_IEEE_R_DROP_COUNT field. */
06122 #define BR_ENET_IEEE_R_DROP_COUNT(x) (UNION_READ(hw_enet_ieee_r_drop_t, HW_ENET_IEEE_R_DROP_ADDR(x), U, B.COUNT))
06123 /*@}*/
06124 
06125 /*******************************************************************************
06126  * HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register
06127  ******************************************************************************/
06128 
06129 /*!
06130  * @brief HW_ENET_IEEE_R_FRAME_OK - Frames Received OK Statistic Register (RO)
06131  *
06132  * Reset value: 0x00000000U
06133  */
06134 typedef union _hw_enet_ieee_r_frame_ok
06135 {
06136     uint32_t U;
06137     struct _hw_enet_ieee_r_frame_ok_bitfields
06138     {
06139         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06140         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06141     } B;
06142 } hw_enet_ieee_r_frame_ok_t;
06143 
06144 /*!
06145  * @name Constants and macros for entire ENET_IEEE_R_FRAME_OK register
06146  */
06147 /*@{*/
06148 #define HW_ENET_IEEE_R_FRAME_OK_ADDR(x) ((x) + 0x2CCU)
06149 
06150 #define HW_ENET_IEEE_R_FRAME_OK(x) (*(__I hw_enet_ieee_r_frame_ok_t *) HW_ENET_IEEE_R_FRAME_OK_ADDR(x))
06151 #define HW_ENET_IEEE_R_FRAME_OK_RD(x) (ADDRESS_READ(hw_enet_ieee_r_frame_ok_t, HW_ENET_IEEE_R_FRAME_OK_ADDR(x)))
06152 /*@}*/
06153 
06154 /*
06155  * Constants & macros for individual ENET_IEEE_R_FRAME_OK bitfields
06156  */
06157 
06158 /*!
06159  * @name Register ENET_IEEE_R_FRAME_OK, field COUNT[15:0] (RO)
06160  */
06161 /*@{*/
06162 #define BP_ENET_IEEE_R_FRAME_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_FRAME_OK_COUNT. */
06163 #define BM_ENET_IEEE_R_FRAME_OK_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FRAME_OK_COUNT. */
06164 #define BS_ENET_IEEE_R_FRAME_OK_COUNT (16U) /*!< Bit field size in bits for ENET_IEEE_R_FRAME_OK_COUNT. */
06165 
06166 /*! @brief Read current value of the ENET_IEEE_R_FRAME_OK_COUNT field. */
06167 #define BR_ENET_IEEE_R_FRAME_OK_COUNT(x) (UNION_READ(hw_enet_ieee_r_frame_ok_t, HW_ENET_IEEE_R_FRAME_OK_ADDR(x), U, B.COUNT))
06168 /*@}*/
06169 
06170 /*******************************************************************************
06171  * HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register
06172  ******************************************************************************/
06173 
06174 /*!
06175  * @brief HW_ENET_IEEE_R_CRC - Frames Received with CRC Error Statistic Register (RO)
06176  *
06177  * Reset value: 0x00000000U
06178  */
06179 typedef union _hw_enet_ieee_r_crc
06180 {
06181     uint32_t U;
06182     struct _hw_enet_ieee_r_crc_bitfields
06183     {
06184         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06185         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06186     } B;
06187 } hw_enet_ieee_r_crc_t;
06188 
06189 /*!
06190  * @name Constants and macros for entire ENET_IEEE_R_CRC register
06191  */
06192 /*@{*/
06193 #define HW_ENET_IEEE_R_CRC_ADDR(x) ((x) + 0x2D0U)
06194 
06195 #define HW_ENET_IEEE_R_CRC(x)    (*(__I hw_enet_ieee_r_crc_t *) HW_ENET_IEEE_R_CRC_ADDR(x))
06196 #define HW_ENET_IEEE_R_CRC_RD(x) (ADDRESS_READ(hw_enet_ieee_r_crc_t, HW_ENET_IEEE_R_CRC_ADDR(x)))
06197 /*@}*/
06198 
06199 /*
06200  * Constants & macros for individual ENET_IEEE_R_CRC bitfields
06201  */
06202 
06203 /*!
06204  * @name Register ENET_IEEE_R_CRC, field COUNT[15:0] (RO)
06205  */
06206 /*@{*/
06207 #define BP_ENET_IEEE_R_CRC_COUNT (0U)      /*!< Bit position for ENET_IEEE_R_CRC_COUNT. */
06208 #define BM_ENET_IEEE_R_CRC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_CRC_COUNT. */
06209 #define BS_ENET_IEEE_R_CRC_COUNT (16U)     /*!< Bit field size in bits for ENET_IEEE_R_CRC_COUNT. */
06210 
06211 /*! @brief Read current value of the ENET_IEEE_R_CRC_COUNT field. */
06212 #define BR_ENET_IEEE_R_CRC_COUNT(x) (UNION_READ(hw_enet_ieee_r_crc_t, HW_ENET_IEEE_R_CRC_ADDR(x), U, B.COUNT))
06213 /*@}*/
06214 
06215 /*******************************************************************************
06216  * HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register
06217  ******************************************************************************/
06218 
06219 /*!
06220  * @brief HW_ENET_IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register (RO)
06221  *
06222  * Reset value: 0x00000000U
06223  */
06224 typedef union _hw_enet_ieee_r_align
06225 {
06226     uint32_t U;
06227     struct _hw_enet_ieee_r_align_bitfields
06228     {
06229         uint32_t COUNT : 16;           /*!< [15:0] Frame count */
06230         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06231     } B;
06232 } hw_enet_ieee_r_align_t;
06233 
06234 /*!
06235  * @name Constants and macros for entire ENET_IEEE_R_ALIGN register
06236  */
06237 /*@{*/
06238 #define HW_ENET_IEEE_R_ALIGN_ADDR(x) ((x) + 0x2D4U)
06239 
06240 #define HW_ENET_IEEE_R_ALIGN(x)  (*(__I hw_enet_ieee_r_align_t *) HW_ENET_IEEE_R_ALIGN_ADDR(x))
06241 #define HW_ENET_IEEE_R_ALIGN_RD(x) (ADDRESS_READ(hw_enet_ieee_r_align_t, HW_ENET_IEEE_R_ALIGN_ADDR(x)))
06242 /*@}*/
06243 
06244 /*
06245  * Constants & macros for individual ENET_IEEE_R_ALIGN bitfields
06246  */
06247 
06248 /*!
06249  * @name Register ENET_IEEE_R_ALIGN, field COUNT[15:0] (RO)
06250  */
06251 /*@{*/
06252 #define BP_ENET_IEEE_R_ALIGN_COUNT (0U)    /*!< Bit position for ENET_IEEE_R_ALIGN_COUNT. */
06253 #define BM_ENET_IEEE_R_ALIGN_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_ALIGN_COUNT. */
06254 #define BS_ENET_IEEE_R_ALIGN_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_R_ALIGN_COUNT. */
06255 
06256 /*! @brief Read current value of the ENET_IEEE_R_ALIGN_COUNT field. */
06257 #define BR_ENET_IEEE_R_ALIGN_COUNT(x) (UNION_READ(hw_enet_ieee_r_align_t, HW_ENET_IEEE_R_ALIGN_ADDR(x), U, B.COUNT))
06258 /*@}*/
06259 
06260 /*******************************************************************************
06261  * HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register
06262  ******************************************************************************/
06263 
06264 /*!
06265  * @brief HW_ENET_IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register (RO)
06266  *
06267  * Reset value: 0x00000000U
06268  */
06269 typedef union _hw_enet_ieee_r_macerr
06270 {
06271     uint32_t U;
06272     struct _hw_enet_ieee_r_macerr_bitfields
06273     {
06274         uint32_t COUNT : 16;           /*!< [15:0] Count */
06275         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06276     } B;
06277 } hw_enet_ieee_r_macerr_t;
06278 
06279 /*!
06280  * @name Constants and macros for entire ENET_IEEE_R_MACERR register
06281  */
06282 /*@{*/
06283 #define HW_ENET_IEEE_R_MACERR_ADDR(x) ((x) + 0x2D8U)
06284 
06285 #define HW_ENET_IEEE_R_MACERR(x) (*(__I hw_enet_ieee_r_macerr_t *) HW_ENET_IEEE_R_MACERR_ADDR(x))
06286 #define HW_ENET_IEEE_R_MACERR_RD(x) (ADDRESS_READ(hw_enet_ieee_r_macerr_t, HW_ENET_IEEE_R_MACERR_ADDR(x)))
06287 /*@}*/
06288 
06289 /*
06290  * Constants & macros for individual ENET_IEEE_R_MACERR bitfields
06291  */
06292 
06293 /*!
06294  * @name Register ENET_IEEE_R_MACERR, field COUNT[15:0] (RO)
06295  */
06296 /*@{*/
06297 #define BP_ENET_IEEE_R_MACERR_COUNT (0U)   /*!< Bit position for ENET_IEEE_R_MACERR_COUNT. */
06298 #define BM_ENET_IEEE_R_MACERR_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_MACERR_COUNT. */
06299 #define BS_ENET_IEEE_R_MACERR_COUNT (16U)  /*!< Bit field size in bits for ENET_IEEE_R_MACERR_COUNT. */
06300 
06301 /*! @brief Read current value of the ENET_IEEE_R_MACERR_COUNT field. */
06302 #define BR_ENET_IEEE_R_MACERR_COUNT(x) (UNION_READ(hw_enet_ieee_r_macerr_t, HW_ENET_IEEE_R_MACERR_ADDR(x), U, B.COUNT))
06303 /*@}*/
06304 
06305 /*******************************************************************************
06306  * HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register
06307  ******************************************************************************/
06308 
06309 /*!
06310  * @brief HW_ENET_IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register (RO)
06311  *
06312  * Reset value: 0x00000000U
06313  */
06314 typedef union _hw_enet_ieee_r_fdxfc
06315 {
06316     uint32_t U;
06317     struct _hw_enet_ieee_r_fdxfc_bitfields
06318     {
06319         uint32_t COUNT : 16;           /*!< [15:0] Pause frame count */
06320         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
06321     } B;
06322 } hw_enet_ieee_r_fdxfc_t;
06323 
06324 /*!
06325  * @name Constants and macros for entire ENET_IEEE_R_FDXFC register
06326  */
06327 /*@{*/
06328 #define HW_ENET_IEEE_R_FDXFC_ADDR(x) ((x) + 0x2DCU)
06329 
06330 #define HW_ENET_IEEE_R_FDXFC(x)  (*(__I hw_enet_ieee_r_fdxfc_t *) HW_ENET_IEEE_R_FDXFC_ADDR(x))
06331 #define HW_ENET_IEEE_R_FDXFC_RD(x) (ADDRESS_READ(hw_enet_ieee_r_fdxfc_t, HW_ENET_IEEE_R_FDXFC_ADDR(x)))
06332 /*@}*/
06333 
06334 /*
06335  * Constants & macros for individual ENET_IEEE_R_FDXFC bitfields
06336  */
06337 
06338 /*!
06339  * @name Register ENET_IEEE_R_FDXFC, field COUNT[15:0] (RO)
06340  */
06341 /*@{*/
06342 #define BP_ENET_IEEE_R_FDXFC_COUNT (0U)    /*!< Bit position for ENET_IEEE_R_FDXFC_COUNT. */
06343 #define BM_ENET_IEEE_R_FDXFC_COUNT (0x0000FFFFU) /*!< Bit mask for ENET_IEEE_R_FDXFC_COUNT. */
06344 #define BS_ENET_IEEE_R_FDXFC_COUNT (16U)   /*!< Bit field size in bits for ENET_IEEE_R_FDXFC_COUNT. */
06345 
06346 /*! @brief Read current value of the ENET_IEEE_R_FDXFC_COUNT field. */
06347 #define BR_ENET_IEEE_R_FDXFC_COUNT(x) (UNION_READ(hw_enet_ieee_r_fdxfc_t, HW_ENET_IEEE_R_FDXFC_ADDR(x), U, B.COUNT))
06348 /*@}*/
06349 
06350 /*******************************************************************************
06351  * HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register
06352  ******************************************************************************/
06353 
06354 /*!
06355  * @brief HW_ENET_IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register (RO)
06356  *
06357  * Reset value: 0x00000000U
06358  */
06359 typedef union _hw_enet_ieee_r_octets_ok
06360 {
06361     uint32_t U;
06362     struct _hw_enet_ieee_r_octets_ok_bitfields
06363     {
06364         uint32_t COUNT : 32;           /*!< [31:0] Octet count */
06365     } B;
06366 } hw_enet_ieee_r_octets_ok_t;
06367 
06368 /*!
06369  * @name Constants and macros for entire ENET_IEEE_R_OCTETS_OK register
06370  */
06371 /*@{*/
06372 #define HW_ENET_IEEE_R_OCTETS_OK_ADDR(x) ((x) + 0x2E0U)
06373 
06374 #define HW_ENET_IEEE_R_OCTETS_OK(x) (*(__I hw_enet_ieee_r_octets_ok_t *) HW_ENET_IEEE_R_OCTETS_OK_ADDR(x))
06375 #define HW_ENET_IEEE_R_OCTETS_OK_RD(x) (ADDRESS_READ(hw_enet_ieee_r_octets_ok_t, HW_ENET_IEEE_R_OCTETS_OK_ADDR(x)))
06376 /*@}*/
06377 
06378 /*
06379  * Constants & macros for individual ENET_IEEE_R_OCTETS_OK bitfields
06380  */
06381 
06382 /*!
06383  * @name Register ENET_IEEE_R_OCTETS_OK, field COUNT[31:0] (RO)
06384  */
06385 /*@{*/
06386 #define BP_ENET_IEEE_R_OCTETS_OK_COUNT (0U) /*!< Bit position for ENET_IEEE_R_OCTETS_OK_COUNT. */
06387 #define BM_ENET_IEEE_R_OCTETS_OK_COUNT (0xFFFFFFFFU) /*!< Bit mask for ENET_IEEE_R_OCTETS_OK_COUNT. */
06388 #define BS_ENET_IEEE_R_OCTETS_OK_COUNT (32U) /*!< Bit field size in bits for ENET_IEEE_R_OCTETS_OK_COUNT. */
06389 
06390 /*! @brief Read current value of the ENET_IEEE_R_OCTETS_OK_COUNT field. */
06391 #define BR_ENET_IEEE_R_OCTETS_OK_COUNT(x) (HW_ENET_IEEE_R_OCTETS_OK(x).U)
06392 /*@}*/
06393 
06394 /*******************************************************************************
06395  * HW_ENET_ATCR - Adjustable Timer Control Register
06396  ******************************************************************************/
06397 
06398 /*!
06399  * @brief HW_ENET_ATCR - Adjustable Timer Control Register (RW)
06400  *
06401  * Reset value: 0x00000000U
06402  *
06403  * ATCR command fields can trigger the corresponding events directly. It is not
06404  * necessary to preserve any of the configuration fields when a command field is
06405  * set in the register, that is, no read-modify-write is required. The fields are
06406  * automatically cleared after the command completes.
06407  */
06408 typedef union _hw_enet_atcr
06409 {
06410     uint32_t U;
06411     struct _hw_enet_atcr_bitfields
06412     {
06413         uint32_t EN : 1;               /*!< [0] Enable Timer */
06414         uint32_t RESERVED0 : 1;        /*!< [1]  */
06415         uint32_t OFFEN : 1;            /*!< [2] Enable One-Shot Offset Event */
06416         uint32_t OFFRST : 1;           /*!< [3] Reset Timer On Offset Event */
06417         uint32_t PEREN : 1;            /*!< [4] Enable Periodical Event */
06418         uint32_t RESERVED1 : 2;        /*!< [6:5]  */
06419         uint32_t PINPER : 1;           /*!< [7]  */
06420         uint32_t RESERVED2 : 1;        /*!< [8]  */
06421         uint32_t RESTART : 1;          /*!< [9] Reset Timer */
06422         uint32_t RESERVED3 : 1;        /*!< [10]  */
06423         uint32_t CAPTURE : 1;          /*!< [11] Capture Timer Value */
06424         uint32_t RESERVED4 : 1;        /*!< [12]  */
06425         uint32_t SLAVE : 1;            /*!< [13] Enable Timer Slave Mode */
06426         uint32_t RESERVED5 : 18;       /*!< [31:14]  */
06427     } B;
06428 } hw_enet_atcr_t;
06429 
06430 /*!
06431  * @name Constants and macros for entire ENET_ATCR register
06432  */
06433 /*@{*/
06434 #define HW_ENET_ATCR_ADDR(x)     ((x) + 0x400U)
06435 
06436 #define HW_ENET_ATCR(x)          (*(__IO hw_enet_atcr_t *) HW_ENET_ATCR_ADDR(x))
06437 #define HW_ENET_ATCR_RD(x)       (ADDRESS_READ(hw_enet_atcr_t, HW_ENET_ATCR_ADDR(x)))
06438 #define HW_ENET_ATCR_WR(x, v)    (ADDRESS_WRITE(hw_enet_atcr_t, HW_ENET_ATCR_ADDR(x), v))
06439 #define HW_ENET_ATCR_SET(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) |  (v)))
06440 #define HW_ENET_ATCR_CLR(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) & ~(v)))
06441 #define HW_ENET_ATCR_TOG(x, v)   (HW_ENET_ATCR_WR(x, HW_ENET_ATCR_RD(x) ^  (v)))
06442 /*@}*/
06443 
06444 /*
06445  * Constants & macros for individual ENET_ATCR bitfields
06446  */
06447 
06448 /*!
06449  * @name Register ENET_ATCR, field EN[0] (RW)
06450  *
06451  * Values:
06452  * - 0 - The timer stops at the current value.
06453  * - 1 - The timer starts incrementing.
06454  */
06455 /*@{*/
06456 #define BP_ENET_ATCR_EN      (0U)          /*!< Bit position for ENET_ATCR_EN. */
06457 #define BM_ENET_ATCR_EN      (0x00000001U) /*!< Bit mask for ENET_ATCR_EN. */
06458 #define BS_ENET_ATCR_EN      (1U)          /*!< Bit field size in bits for ENET_ATCR_EN. */
06459 
06460 /*! @brief Read current value of the ENET_ATCR_EN field. */
06461 #define BR_ENET_ATCR_EN(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN)))
06462 
06463 /*! @brief Format value for bitfield ENET_ATCR_EN. */
06464 #define BF_ENET_ATCR_EN(v)   ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_EN) & BM_ENET_ATCR_EN)
06465 
06466 /*! @brief Set the EN field to a new value. */
06467 #define BW_ENET_ATCR_EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_EN), v))
06468 /*@}*/
06469 
06470 /*!
06471  * @name Register ENET_ATCR, field OFFEN[2] (RW)
06472  *
06473  * Values:
06474  * - 0 - Disable.
06475  * - 1 - The timer can be reset to zero when the given offset time is reached
06476  *     (offset event). The field is cleared when the offset event is reached, so no
06477  *     further event occurs until the field is set again. The timer offset value
06478  *     must be set before setting this field.
06479  */
06480 /*@{*/
06481 #define BP_ENET_ATCR_OFFEN   (2U)          /*!< Bit position for ENET_ATCR_OFFEN. */
06482 #define BM_ENET_ATCR_OFFEN   (0x00000004U) /*!< Bit mask for ENET_ATCR_OFFEN. */
06483 #define BS_ENET_ATCR_OFFEN   (1U)          /*!< Bit field size in bits for ENET_ATCR_OFFEN. */
06484 
06485 /*! @brief Read current value of the ENET_ATCR_OFFEN field. */
06486 #define BR_ENET_ATCR_OFFEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN)))
06487 
06488 /*! @brief Format value for bitfield ENET_ATCR_OFFEN. */
06489 #define BF_ENET_ATCR_OFFEN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFEN) & BM_ENET_ATCR_OFFEN)
06490 
06491 /*! @brief Set the OFFEN field to a new value. */
06492 #define BW_ENET_ATCR_OFFEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFEN), v))
06493 /*@}*/
06494 
06495 /*!
06496  * @name Register ENET_ATCR, field OFFRST[3] (RW)
06497  *
06498  * Values:
06499  * - 0 - The timer is not affected and no action occurs, besides clearing OFFEN,
06500  *     when the offset is reached.
06501  * - 1 - If OFFEN is set, the timer resets to zero when the offset setting is
06502  *     reached. The offset event does not cause a timer interrupt.
06503  */
06504 /*@{*/
06505 #define BP_ENET_ATCR_OFFRST  (3U)          /*!< Bit position for ENET_ATCR_OFFRST. */
06506 #define BM_ENET_ATCR_OFFRST  (0x00000008U) /*!< Bit mask for ENET_ATCR_OFFRST. */
06507 #define BS_ENET_ATCR_OFFRST  (1U)          /*!< Bit field size in bits for ENET_ATCR_OFFRST. */
06508 
06509 /*! @brief Read current value of the ENET_ATCR_OFFRST field. */
06510 #define BR_ENET_ATCR_OFFRST(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST)))
06511 
06512 /*! @brief Format value for bitfield ENET_ATCR_OFFRST. */
06513 #define BF_ENET_ATCR_OFFRST(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_OFFRST) & BM_ENET_ATCR_OFFRST)
06514 
06515 /*! @brief Set the OFFRST field to a new value. */
06516 #define BW_ENET_ATCR_OFFRST(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_OFFRST), v))
06517 /*@}*/
06518 
06519 /*!
06520  * @name Register ENET_ATCR, field PEREN[4] (RW)
06521  *
06522  * Values:
06523  * - 0 - Disable.
06524  * - 1 - A period event interrupt can be generated (EIR[TS_TIMER]) and the event
06525  *     signal output is asserted when the timer wraps around according to the
06526  *     periodic setting ATPER. The timer period value must be set before setting
06527  *     this bit. Not all devices contain the event signal output. See the chip
06528  *     configuration details.
06529  */
06530 /*@{*/
06531 #define BP_ENET_ATCR_PEREN   (4U)          /*!< Bit position for ENET_ATCR_PEREN. */
06532 #define BM_ENET_ATCR_PEREN   (0x00000010U) /*!< Bit mask for ENET_ATCR_PEREN. */
06533 #define BS_ENET_ATCR_PEREN   (1U)          /*!< Bit field size in bits for ENET_ATCR_PEREN. */
06534 
06535 /*! @brief Read current value of the ENET_ATCR_PEREN field. */
06536 #define BR_ENET_ATCR_PEREN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN)))
06537 
06538 /*! @brief Format value for bitfield ENET_ATCR_PEREN. */
06539 #define BF_ENET_ATCR_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PEREN) & BM_ENET_ATCR_PEREN)
06540 
06541 /*! @brief Set the PEREN field to a new value. */
06542 #define BW_ENET_ATCR_PEREN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PEREN), v))
06543 /*@}*/
06544 
06545 /*!
06546  * @name Register ENET_ATCR, field PINPER[7] (RW)
06547  *
06548  * Enables event signal output assertion on period event. Not all devices
06549  * contain the event signal output. See the chip configuration details.
06550  *
06551  * Values:
06552  * - 0 - Disable.
06553  * - 1 - Enable.
06554  */
06555 /*@{*/
06556 #define BP_ENET_ATCR_PINPER  (7U)          /*!< Bit position for ENET_ATCR_PINPER. */
06557 #define BM_ENET_ATCR_PINPER  (0x00000080U) /*!< Bit mask for ENET_ATCR_PINPER. */
06558 #define BS_ENET_ATCR_PINPER  (1U)          /*!< Bit field size in bits for ENET_ATCR_PINPER. */
06559 
06560 /*! @brief Read current value of the ENET_ATCR_PINPER field. */
06561 #define BR_ENET_ATCR_PINPER(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER)))
06562 
06563 /*! @brief Format value for bitfield ENET_ATCR_PINPER. */
06564 #define BF_ENET_ATCR_PINPER(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_PINPER) & BM_ENET_ATCR_PINPER)
06565 
06566 /*! @brief Set the PINPER field to a new value. */
06567 #define BW_ENET_ATCR_PINPER(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_PINPER), v))
06568 /*@}*/
06569 
06570 /*!
06571  * @name Register ENET_ATCR, field RESTART[9] (RW)
06572  *
06573  * Resets the timer to zero. This has no effect on the counter enable. If the
06574  * counter is enabled when this field is set, the timer is reset to zero and starts
06575  * counting from there. When set, all other fields are ignored during a write.
06576  */
06577 /*@{*/
06578 #define BP_ENET_ATCR_RESTART (9U)          /*!< Bit position for ENET_ATCR_RESTART. */
06579 #define BM_ENET_ATCR_RESTART (0x00000200U) /*!< Bit mask for ENET_ATCR_RESTART. */
06580 #define BS_ENET_ATCR_RESTART (1U)          /*!< Bit field size in bits for ENET_ATCR_RESTART. */
06581 
06582 /*! @brief Read current value of the ENET_ATCR_RESTART field. */
06583 #define BR_ENET_ATCR_RESTART(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART)))
06584 
06585 /*! @brief Format value for bitfield ENET_ATCR_RESTART. */
06586 #define BF_ENET_ATCR_RESTART(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_RESTART) & BM_ENET_ATCR_RESTART)
06587 
06588 /*! @brief Set the RESTART field to a new value. */
06589 #define BW_ENET_ATCR_RESTART(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_RESTART), v))
06590 /*@}*/
06591 
06592 /*!
06593  * @name Register ENET_ATCR, field CAPTURE[11] (RW)
06594  *
06595  * Values:
06596  * - 0 - No effect.
06597  * - 1 - The current time is captured and can be read from the ATVR register.
06598  */
06599 /*@{*/
06600 #define BP_ENET_ATCR_CAPTURE (11U)         /*!< Bit position for ENET_ATCR_CAPTURE. */
06601 #define BM_ENET_ATCR_CAPTURE (0x00000800U) /*!< Bit mask for ENET_ATCR_CAPTURE. */
06602 #define BS_ENET_ATCR_CAPTURE (1U)          /*!< Bit field size in bits for ENET_ATCR_CAPTURE. */
06603 
06604 /*! @brief Read current value of the ENET_ATCR_CAPTURE field. */
06605 #define BR_ENET_ATCR_CAPTURE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE)))
06606 
06607 /*! @brief Format value for bitfield ENET_ATCR_CAPTURE. */
06608 #define BF_ENET_ATCR_CAPTURE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_CAPTURE) & BM_ENET_ATCR_CAPTURE)
06609 
06610 /*! @brief Set the CAPTURE field to a new value. */
06611 #define BW_ENET_ATCR_CAPTURE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_CAPTURE), v))
06612 /*@}*/
06613 
06614 /*!
06615  * @name Register ENET_ATCR, field SLAVE[13] (RW)
06616  *
06617  * Values:
06618  * - 0 - The timer is active and all configuration fields in this register are
06619  *     relevant.
06620  * - 1 - The internal timer is disabled and the externally provided timer value
06621  *     is used. All other fields, except CAPTURE, in this register have no
06622  *     effect. CAPTURE can still be used to capture the current timer value.
06623  */
06624 /*@{*/
06625 #define BP_ENET_ATCR_SLAVE   (13U)         /*!< Bit position for ENET_ATCR_SLAVE. */
06626 #define BM_ENET_ATCR_SLAVE   (0x00002000U) /*!< Bit mask for ENET_ATCR_SLAVE. */
06627 #define BS_ENET_ATCR_SLAVE   (1U)          /*!< Bit field size in bits for ENET_ATCR_SLAVE. */
06628 
06629 /*! @brief Read current value of the ENET_ATCR_SLAVE field. */
06630 #define BR_ENET_ATCR_SLAVE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE)))
06631 
06632 /*! @brief Format value for bitfield ENET_ATCR_SLAVE. */
06633 #define BF_ENET_ATCR_SLAVE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCR_SLAVE) & BM_ENET_ATCR_SLAVE)
06634 
06635 /*! @brief Set the SLAVE field to a new value. */
06636 #define BW_ENET_ATCR_SLAVE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_ATCR_ADDR(x), BP_ENET_ATCR_SLAVE), v))
06637 /*@}*/
06638 
06639 /*******************************************************************************
06640  * HW_ENET_ATVR - Timer Value Register
06641  ******************************************************************************/
06642 
06643 /*!
06644  * @brief HW_ENET_ATVR - Timer Value Register (RW)
06645  *
06646  * Reset value: 0x00000000U
06647  */
06648 typedef union _hw_enet_atvr
06649 {
06650     uint32_t U;
06651     struct _hw_enet_atvr_bitfields
06652     {
06653         uint32_t ATIME : 32;           /*!< [31:0]  */
06654     } B;
06655 } hw_enet_atvr_t;
06656 
06657 /*!
06658  * @name Constants and macros for entire ENET_ATVR register
06659  */
06660 /*@{*/
06661 #define HW_ENET_ATVR_ADDR(x)     ((x) + 0x404U)
06662 
06663 #define HW_ENET_ATVR(x)          (*(__IO hw_enet_atvr_t *) HW_ENET_ATVR_ADDR(x))
06664 #define HW_ENET_ATVR_RD(x)       (ADDRESS_READ(hw_enet_atvr_t, HW_ENET_ATVR_ADDR(x)))
06665 #define HW_ENET_ATVR_WR(x, v)    (ADDRESS_WRITE(hw_enet_atvr_t, HW_ENET_ATVR_ADDR(x), v))
06666 #define HW_ENET_ATVR_SET(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) |  (v)))
06667 #define HW_ENET_ATVR_CLR(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) & ~(v)))
06668 #define HW_ENET_ATVR_TOG(x, v)   (HW_ENET_ATVR_WR(x, HW_ENET_ATVR_RD(x) ^  (v)))
06669 /*@}*/
06670 
06671 /*
06672  * Constants & macros for individual ENET_ATVR bitfields
06673  */
06674 
06675 /*!
06676  * @name Register ENET_ATVR, field ATIME[31:0] (RW)
06677  *
06678  * A write sets the timer. A read returns the last captured value. To read the
06679  * current value, issue a capture command (set ATCR[CAPTURE]) prior to reading
06680  * this register.
06681  */
06682 /*@{*/
06683 #define BP_ENET_ATVR_ATIME   (0U)          /*!< Bit position for ENET_ATVR_ATIME. */
06684 #define BM_ENET_ATVR_ATIME   (0xFFFFFFFFU) /*!< Bit mask for ENET_ATVR_ATIME. */
06685 #define BS_ENET_ATVR_ATIME   (32U)         /*!< Bit field size in bits for ENET_ATVR_ATIME. */
06686 
06687 /*! @brief Read current value of the ENET_ATVR_ATIME field. */
06688 #define BR_ENET_ATVR_ATIME(x) (HW_ENET_ATVR(x).U)
06689 
06690 /*! @brief Format value for bitfield ENET_ATVR_ATIME. */
06691 #define BF_ENET_ATVR_ATIME(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATVR_ATIME) & BM_ENET_ATVR_ATIME)
06692 
06693 /*! @brief Set the ATIME field to a new value. */
06694 #define BW_ENET_ATVR_ATIME(x, v) (HW_ENET_ATVR_WR(x, v))
06695 /*@}*/
06696 
06697 /*******************************************************************************
06698  * HW_ENET_ATOFF - Timer Offset Register
06699  ******************************************************************************/
06700 
06701 /*!
06702  * @brief HW_ENET_ATOFF - Timer Offset Register (RW)
06703  *
06704  * Reset value: 0x00000000U
06705  */
06706 typedef union _hw_enet_atoff
06707 {
06708     uint32_t U;
06709     struct _hw_enet_atoff_bitfields
06710     {
06711         uint32_t OFFSET : 32;          /*!< [31:0]  */
06712     } B;
06713 } hw_enet_atoff_t;
06714 
06715 /*!
06716  * @name Constants and macros for entire ENET_ATOFF register
06717  */
06718 /*@{*/
06719 #define HW_ENET_ATOFF_ADDR(x)    ((x) + 0x408U)
06720 
06721 #define HW_ENET_ATOFF(x)         (*(__IO hw_enet_atoff_t *) HW_ENET_ATOFF_ADDR(x))
06722 #define HW_ENET_ATOFF_RD(x)      (ADDRESS_READ(hw_enet_atoff_t, HW_ENET_ATOFF_ADDR(x)))
06723 #define HW_ENET_ATOFF_WR(x, v)   (ADDRESS_WRITE(hw_enet_atoff_t, HW_ENET_ATOFF_ADDR(x), v))
06724 #define HW_ENET_ATOFF_SET(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) |  (v)))
06725 #define HW_ENET_ATOFF_CLR(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) & ~(v)))
06726 #define HW_ENET_ATOFF_TOG(x, v)  (HW_ENET_ATOFF_WR(x, HW_ENET_ATOFF_RD(x) ^  (v)))
06727 /*@}*/
06728 
06729 /*
06730  * Constants & macros for individual ENET_ATOFF bitfields
06731  */
06732 
06733 /*!
06734  * @name Register ENET_ATOFF, field OFFSET[31:0] (RW)
06735  *
06736  * Offset value for one-shot event generation. When the timer reaches the value,
06737  * an event can be generated to reset the counter. If the increment value in
06738  * ATINC is given in true nanoseconds, this value is also given in true nanoseconds.
06739  */
06740 /*@{*/
06741 #define BP_ENET_ATOFF_OFFSET (0U)          /*!< Bit position for ENET_ATOFF_OFFSET. */
06742 #define BM_ENET_ATOFF_OFFSET (0xFFFFFFFFU) /*!< Bit mask for ENET_ATOFF_OFFSET. */
06743 #define BS_ENET_ATOFF_OFFSET (32U)         /*!< Bit field size in bits for ENET_ATOFF_OFFSET. */
06744 
06745 /*! @brief Read current value of the ENET_ATOFF_OFFSET field. */
06746 #define BR_ENET_ATOFF_OFFSET(x) (HW_ENET_ATOFF(x).U)
06747 
06748 /*! @brief Format value for bitfield ENET_ATOFF_OFFSET. */
06749 #define BF_ENET_ATOFF_OFFSET(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATOFF_OFFSET) & BM_ENET_ATOFF_OFFSET)
06750 
06751 /*! @brief Set the OFFSET field to a new value. */
06752 #define BW_ENET_ATOFF_OFFSET(x, v) (HW_ENET_ATOFF_WR(x, v))
06753 /*@}*/
06754 
06755 /*******************************************************************************
06756  * HW_ENET_ATPER - Timer Period Register
06757  ******************************************************************************/
06758 
06759 /*!
06760  * @brief HW_ENET_ATPER - Timer Period Register (RW)
06761  *
06762  * Reset value: 0x3B9ACA00U
06763  */
06764 typedef union _hw_enet_atper
06765 {
06766     uint32_t U;
06767     struct _hw_enet_atper_bitfields
06768     {
06769         uint32_t PERIOD : 32;          /*!< [31:0]  */
06770     } B;
06771 } hw_enet_atper_t;
06772 
06773 /*!
06774  * @name Constants and macros for entire ENET_ATPER register
06775  */
06776 /*@{*/
06777 #define HW_ENET_ATPER_ADDR(x)    ((x) + 0x40CU)
06778 
06779 #define HW_ENET_ATPER(x)         (*(__IO hw_enet_atper_t *) HW_ENET_ATPER_ADDR(x))
06780 #define HW_ENET_ATPER_RD(x)      (ADDRESS_READ(hw_enet_atper_t, HW_ENET_ATPER_ADDR(x)))
06781 #define HW_ENET_ATPER_WR(x, v)   (ADDRESS_WRITE(hw_enet_atper_t, HW_ENET_ATPER_ADDR(x), v))
06782 #define HW_ENET_ATPER_SET(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) |  (v)))
06783 #define HW_ENET_ATPER_CLR(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) & ~(v)))
06784 #define HW_ENET_ATPER_TOG(x, v)  (HW_ENET_ATPER_WR(x, HW_ENET_ATPER_RD(x) ^  (v)))
06785 /*@}*/
06786 
06787 /*
06788  * Constants & macros for individual ENET_ATPER bitfields
06789  */
06790 
06791 /*!
06792  * @name Register ENET_ATPER, field PERIOD[31:0] (RW)
06793  *
06794  * Value for generating periodic events. Each instance the timer reaches this
06795  * value, the period event occurs and the timer restarts. If the increment value in
06796  * ATINC is given in true nanoseconds, this value is also given in true
06797  * nanoseconds. The value should be initialized to 1,000,000,000 (1 x 10 9 ) to represent
06798  * a timer wrap around of one second. The increment value set in ATINC should be
06799  * set to the true nanoseconds of the period of clock ts_clk, hence implementing
06800  * a true 1 second counter.
06801  */
06802 /*@{*/
06803 #define BP_ENET_ATPER_PERIOD (0U)          /*!< Bit position for ENET_ATPER_PERIOD. */
06804 #define BM_ENET_ATPER_PERIOD (0xFFFFFFFFU) /*!< Bit mask for ENET_ATPER_PERIOD. */
06805 #define BS_ENET_ATPER_PERIOD (32U)         /*!< Bit field size in bits for ENET_ATPER_PERIOD. */
06806 
06807 /*! @brief Read current value of the ENET_ATPER_PERIOD field. */
06808 #define BR_ENET_ATPER_PERIOD(x) (HW_ENET_ATPER(x).U)
06809 
06810 /*! @brief Format value for bitfield ENET_ATPER_PERIOD. */
06811 #define BF_ENET_ATPER_PERIOD(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATPER_PERIOD) & BM_ENET_ATPER_PERIOD)
06812 
06813 /*! @brief Set the PERIOD field to a new value. */
06814 #define BW_ENET_ATPER_PERIOD(x, v) (HW_ENET_ATPER_WR(x, v))
06815 /*@}*/
06816 
06817 /*******************************************************************************
06818  * HW_ENET_ATCOR - Timer Correction Register
06819  ******************************************************************************/
06820 
06821 /*!
06822  * @brief HW_ENET_ATCOR - Timer Correction Register (RW)
06823  *
06824  * Reset value: 0x00000000U
06825  */
06826 typedef union _hw_enet_atcor
06827 {
06828     uint32_t U;
06829     struct _hw_enet_atcor_bitfields
06830     {
06831         uint32_t COR : 31;             /*!< [30:0] Correction Counter Wrap-Around Value */
06832         uint32_t RESERVED0 : 1;        /*!< [31]  */
06833     } B;
06834 } hw_enet_atcor_t;
06835 
06836 /*!
06837  * @name Constants and macros for entire ENET_ATCOR register
06838  */
06839 /*@{*/
06840 #define HW_ENET_ATCOR_ADDR(x)    ((x) + 0x410U)
06841 
06842 #define HW_ENET_ATCOR(x)         (*(__IO hw_enet_atcor_t *) HW_ENET_ATCOR_ADDR(x))
06843 #define HW_ENET_ATCOR_RD(x)      (ADDRESS_READ(hw_enet_atcor_t, HW_ENET_ATCOR_ADDR(x)))
06844 #define HW_ENET_ATCOR_WR(x, v)   (ADDRESS_WRITE(hw_enet_atcor_t, HW_ENET_ATCOR_ADDR(x), v))
06845 #define HW_ENET_ATCOR_SET(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) |  (v)))
06846 #define HW_ENET_ATCOR_CLR(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) & ~(v)))
06847 #define HW_ENET_ATCOR_TOG(x, v)  (HW_ENET_ATCOR_WR(x, HW_ENET_ATCOR_RD(x) ^  (v)))
06848 /*@}*/
06849 
06850 /*
06851  * Constants & macros for individual ENET_ATCOR bitfields
06852  */
06853 
06854 /*!
06855  * @name Register ENET_ATCOR, field COR[30:0] (RW)
06856  *
06857  * Defines after how many timer clock cycles (ts_clk) the correction counter
06858  * should be reset and trigger a correction increment on the timer. The amount of
06859  * correction is defined in ATINC[INC_CORR]. A value of 0 disables the correction
06860  * counter and no corrections occur. This value is given in clock cycles, not in
06861  * nanoseconds as all other values.
06862  */
06863 /*@{*/
06864 #define BP_ENET_ATCOR_COR    (0U)          /*!< Bit position for ENET_ATCOR_COR. */
06865 #define BM_ENET_ATCOR_COR    (0x7FFFFFFFU) /*!< Bit mask for ENET_ATCOR_COR. */
06866 #define BS_ENET_ATCOR_COR    (31U)         /*!< Bit field size in bits for ENET_ATCOR_COR. */
06867 
06868 /*! @brief Read current value of the ENET_ATCOR_COR field. */
06869 #define BR_ENET_ATCOR_COR(x) (UNION_READ(hw_enet_atcor_t, HW_ENET_ATCOR_ADDR(x), U, B.COR))
06870 
06871 /*! @brief Format value for bitfield ENET_ATCOR_COR. */
06872 #define BF_ENET_ATCOR_COR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATCOR_COR) & BM_ENET_ATCOR_COR)
06873 
06874 /*! @brief Set the COR field to a new value. */
06875 #define BW_ENET_ATCOR_COR(x, v) (HW_ENET_ATCOR_WR(x, (HW_ENET_ATCOR_RD(x) & ~BM_ENET_ATCOR_COR) | BF_ENET_ATCOR_COR(v)))
06876 /*@}*/
06877 
06878 /*******************************************************************************
06879  * HW_ENET_ATINC - Time-Stamping Clock Period Register
06880  ******************************************************************************/
06881 
06882 /*!
06883  * @brief HW_ENET_ATINC - Time-Stamping Clock Period Register (RW)
06884  *
06885  * Reset value: 0x00000000U
06886  */
06887 typedef union _hw_enet_atinc
06888 {
06889     uint32_t U;
06890     struct _hw_enet_atinc_bitfields
06891     {
06892         uint32_t INC : 7;              /*!< [6:0] Clock Period Of The Timestamping Clock
06893                                         * (ts_clk) In Nanoseconds */
06894         uint32_t RESERVED0 : 1;        /*!< [7]  */
06895         uint32_t INC_CORR : 7;         /*!< [14:8] Correction Increment Value */
06896         uint32_t RESERVED1 : 17;       /*!< [31:15]  */
06897     } B;
06898 } hw_enet_atinc_t;
06899 
06900 /*!
06901  * @name Constants and macros for entire ENET_ATINC register
06902  */
06903 /*@{*/
06904 #define HW_ENET_ATINC_ADDR(x)    ((x) + 0x414U)
06905 
06906 #define HW_ENET_ATINC(x)         (*(__IO hw_enet_atinc_t *) HW_ENET_ATINC_ADDR(x))
06907 #define HW_ENET_ATINC_RD(x)      (ADDRESS_READ(hw_enet_atinc_t, HW_ENET_ATINC_ADDR(x)))
06908 #define HW_ENET_ATINC_WR(x, v)   (ADDRESS_WRITE(hw_enet_atinc_t, HW_ENET_ATINC_ADDR(x), v))
06909 #define HW_ENET_ATINC_SET(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) |  (v)))
06910 #define HW_ENET_ATINC_CLR(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) & ~(v)))
06911 #define HW_ENET_ATINC_TOG(x, v)  (HW_ENET_ATINC_WR(x, HW_ENET_ATINC_RD(x) ^  (v)))
06912 /*@}*/
06913 
06914 /*
06915  * Constants & macros for individual ENET_ATINC bitfields
06916  */
06917 
06918 /*!
06919  * @name Register ENET_ATINC, field INC[6:0] (RW)
06920  *
06921  * The timer increments by this amount each clock cycle. For example, set to 10
06922  * for 100 MHz, 8 for 125 MHz, 5 for 200 MHz. For highest precision, use a value
06923  * that is an integer fraction of the period set in ATPER.
06924  */
06925 /*@{*/
06926 #define BP_ENET_ATINC_INC    (0U)          /*!< Bit position for ENET_ATINC_INC. */
06927 #define BM_ENET_ATINC_INC    (0x0000007FU) /*!< Bit mask for ENET_ATINC_INC. */
06928 #define BS_ENET_ATINC_INC    (7U)          /*!< Bit field size in bits for ENET_ATINC_INC. */
06929 
06930 /*! @brief Read current value of the ENET_ATINC_INC field. */
06931 #define BR_ENET_ATINC_INC(x) (UNION_READ(hw_enet_atinc_t, HW_ENET_ATINC_ADDR(x), U, B.INC))
06932 
06933 /*! @brief Format value for bitfield ENET_ATINC_INC. */
06934 #define BF_ENET_ATINC_INC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC) & BM_ENET_ATINC_INC)
06935 
06936 /*! @brief Set the INC field to a new value. */
06937 #define BW_ENET_ATINC_INC(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC) | BF_ENET_ATINC_INC(v)))
06938 /*@}*/
06939 
06940 /*!
06941  * @name Register ENET_ATINC, field INC_CORR[14:8] (RW)
06942  *
06943  * This value is added every time the correction timer expires (every clock
06944  * cycle given in ATCOR). A value less than INC slows down the timer. A value greater
06945  * than INC speeds up the timer.
06946  */
06947 /*@{*/
06948 #define BP_ENET_ATINC_INC_CORR (8U)        /*!< Bit position for ENET_ATINC_INC_CORR. */
06949 #define BM_ENET_ATINC_INC_CORR (0x00007F00U) /*!< Bit mask for ENET_ATINC_INC_CORR. */
06950 #define BS_ENET_ATINC_INC_CORR (7U)        /*!< Bit field size in bits for ENET_ATINC_INC_CORR. */
06951 
06952 /*! @brief Read current value of the ENET_ATINC_INC_CORR field. */
06953 #define BR_ENET_ATINC_INC_CORR(x) (UNION_READ(hw_enet_atinc_t, HW_ENET_ATINC_ADDR(x), U, B.INC_CORR))
06954 
06955 /*! @brief Format value for bitfield ENET_ATINC_INC_CORR. */
06956 #define BF_ENET_ATINC_INC_CORR(v) ((uint32_t)((uint32_t)(v) << BP_ENET_ATINC_INC_CORR) & BM_ENET_ATINC_INC_CORR)
06957 
06958 /*! @brief Set the INC_CORR field to a new value. */
06959 #define BW_ENET_ATINC_INC_CORR(x, v) (HW_ENET_ATINC_WR(x, (HW_ENET_ATINC_RD(x) & ~BM_ENET_ATINC_INC_CORR) | BF_ENET_ATINC_INC_CORR(v)))
06960 /*@}*/
06961 
06962 /*******************************************************************************
06963  * HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame
06964  ******************************************************************************/
06965 
06966 /*!
06967  * @brief HW_ENET_ATSTMP - Timestamp of Last Transmitted Frame (RO)
06968  *
06969  * Reset value: 0x00000000U
06970  */
06971 typedef union _hw_enet_atstmp
06972 {
06973     uint32_t U;
06974     struct _hw_enet_atstmp_bitfields
06975     {
06976         uint32_t TIMESTAMP : 32;       /*!< [31:0]  */
06977     } B;
06978 } hw_enet_atstmp_t;
06979 
06980 /*!
06981  * @name Constants and macros for entire ENET_ATSTMP register
06982  */
06983 /*@{*/
06984 #define HW_ENET_ATSTMP_ADDR(x)   ((x) + 0x418U)
06985 
06986 #define HW_ENET_ATSTMP(x)        (*(__I hw_enet_atstmp_t *) HW_ENET_ATSTMP_ADDR(x))
06987 #define HW_ENET_ATSTMP_RD(x)     (ADDRESS_READ(hw_enet_atstmp_t, HW_ENET_ATSTMP_ADDR(x)))
06988 /*@}*/
06989 
06990 /*
06991  * Constants & macros for individual ENET_ATSTMP bitfields
06992  */
06993 
06994 /*!
06995  * @name Register ENET_ATSTMP, field TIMESTAMP[31:0] (RO)
06996  *
06997  * Timestamp of the last frame transmitted by the core that had TxBD[TS] set .
06998  * This register is only valid when EIR[TS_AVAIL] is set.
06999  */
07000 /*@{*/
07001 #define BP_ENET_ATSTMP_TIMESTAMP (0U)      /*!< Bit position for ENET_ATSTMP_TIMESTAMP. */
07002 #define BM_ENET_ATSTMP_TIMESTAMP (0xFFFFFFFFU) /*!< Bit mask for ENET_ATSTMP_TIMESTAMP. */
07003 #define BS_ENET_ATSTMP_TIMESTAMP (32U)     /*!< Bit field size in bits for ENET_ATSTMP_TIMESTAMP. */
07004 
07005 /*! @brief Read current value of the ENET_ATSTMP_TIMESTAMP field. */
07006 #define BR_ENET_ATSTMP_TIMESTAMP(x) (HW_ENET_ATSTMP(x).U)
07007 /*@}*/
07008 
07009 /*******************************************************************************
07010  * HW_ENET_TGSR - Timer Global Status Register
07011  ******************************************************************************/
07012 
07013 /*!
07014  * @brief HW_ENET_TGSR - Timer Global Status Register (RW)
07015  *
07016  * Reset value: 0x00000000U
07017  */
07018 typedef union _hw_enet_tgsr
07019 {
07020     uint32_t U;
07021     struct _hw_enet_tgsr_bitfields
07022     {
07023         uint32_t TF0 : 1;              /*!< [0] Copy Of Timer Flag For Channel 0 */
07024         uint32_t TF1 : 1;              /*!< [1] Copy Of Timer Flag For Channel 1 */
07025         uint32_t TF2 : 1;              /*!< [2] Copy Of Timer Flag For Channel 2 */
07026         uint32_t TF3 : 1;              /*!< [3] Copy Of Timer Flag For Channel 3 */
07027         uint32_t RESERVED0 : 28;       /*!< [31:4]  */
07028     } B;
07029 } hw_enet_tgsr_t;
07030 
07031 /*!
07032  * @name Constants and macros for entire ENET_TGSR register
07033  */
07034 /*@{*/
07035 #define HW_ENET_TGSR_ADDR(x)     ((x) + 0x604U)
07036 
07037 #define HW_ENET_TGSR(x)          (*(__IO hw_enet_tgsr_t *) HW_ENET_TGSR_ADDR(x))
07038 #define HW_ENET_TGSR_RD(x)       (ADDRESS_READ(hw_enet_tgsr_t, HW_ENET_TGSR_ADDR(x)))
07039 #define HW_ENET_TGSR_WR(x, v)    (ADDRESS_WRITE(hw_enet_tgsr_t, HW_ENET_TGSR_ADDR(x), v))
07040 #define HW_ENET_TGSR_SET(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) |  (v)))
07041 #define HW_ENET_TGSR_CLR(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) & ~(v)))
07042 #define HW_ENET_TGSR_TOG(x, v)   (HW_ENET_TGSR_WR(x, HW_ENET_TGSR_RD(x) ^  (v)))
07043 /*@}*/
07044 
07045 /*
07046  * Constants & macros for individual ENET_TGSR bitfields
07047  */
07048 
07049 /*!
07050  * @name Register ENET_TGSR, field TF0[0] (W1C)
07051  *
07052  * Values:
07053  * - 0 - Timer Flag for Channel 0 is clear
07054  * - 1 - Timer Flag for Channel 0 is set
07055  */
07056 /*@{*/
07057 #define BP_ENET_TGSR_TF0     (0U)          /*!< Bit position for ENET_TGSR_TF0. */
07058 #define BM_ENET_TGSR_TF0     (0x00000001U) /*!< Bit mask for ENET_TGSR_TF0. */
07059 #define BS_ENET_TGSR_TF0     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF0. */
07060 
07061 /*! @brief Read current value of the ENET_TGSR_TF0 field. */
07062 #define BR_ENET_TGSR_TF0(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0)))
07063 
07064 /*! @brief Format value for bitfield ENET_TGSR_TF0. */
07065 #define BF_ENET_TGSR_TF0(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF0) & BM_ENET_TGSR_TF0)
07066 
07067 /*! @brief Set the TF0 field to a new value. */
07068 #define BW_ENET_TGSR_TF0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF0), v))
07069 /*@}*/
07070 
07071 /*!
07072  * @name Register ENET_TGSR, field TF1[1] (W1C)
07073  *
07074  * Values:
07075  * - 0 - Timer Flag for Channel 1 is clear
07076  * - 1 - Timer Flag for Channel 1 is set
07077  */
07078 /*@{*/
07079 #define BP_ENET_TGSR_TF1     (1U)          /*!< Bit position for ENET_TGSR_TF1. */
07080 #define BM_ENET_TGSR_TF1     (0x00000002U) /*!< Bit mask for ENET_TGSR_TF1. */
07081 #define BS_ENET_TGSR_TF1     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF1. */
07082 
07083 /*! @brief Read current value of the ENET_TGSR_TF1 field. */
07084 #define BR_ENET_TGSR_TF1(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1)))
07085 
07086 /*! @brief Format value for bitfield ENET_TGSR_TF1. */
07087 #define BF_ENET_TGSR_TF1(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF1) & BM_ENET_TGSR_TF1)
07088 
07089 /*! @brief Set the TF1 field to a new value. */
07090 #define BW_ENET_TGSR_TF1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF1), v))
07091 /*@}*/
07092 
07093 /*!
07094  * @name Register ENET_TGSR, field TF2[2] (W1C)
07095  *
07096  * Values:
07097  * - 0 - Timer Flag for Channel 2 is clear
07098  * - 1 - Timer Flag for Channel 2 is set
07099  */
07100 /*@{*/
07101 #define BP_ENET_TGSR_TF2     (2U)          /*!< Bit position for ENET_TGSR_TF2. */
07102 #define BM_ENET_TGSR_TF2     (0x00000004U) /*!< Bit mask for ENET_TGSR_TF2. */
07103 #define BS_ENET_TGSR_TF2     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF2. */
07104 
07105 /*! @brief Read current value of the ENET_TGSR_TF2 field. */
07106 #define BR_ENET_TGSR_TF2(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2)))
07107 
07108 /*! @brief Format value for bitfield ENET_TGSR_TF2. */
07109 #define BF_ENET_TGSR_TF2(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF2) & BM_ENET_TGSR_TF2)
07110 
07111 /*! @brief Set the TF2 field to a new value. */
07112 #define BW_ENET_TGSR_TF2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF2), v))
07113 /*@}*/
07114 
07115 /*!
07116  * @name Register ENET_TGSR, field TF3[3] (W1C)
07117  *
07118  * Values:
07119  * - 0 - Timer Flag for Channel 3 is clear
07120  * - 1 - Timer Flag for Channel 3 is set
07121  */
07122 /*@{*/
07123 #define BP_ENET_TGSR_TF3     (3U)          /*!< Bit position for ENET_TGSR_TF3. */
07124 #define BM_ENET_TGSR_TF3     (0x00000008U) /*!< Bit mask for ENET_TGSR_TF3. */
07125 #define BS_ENET_TGSR_TF3     (1U)          /*!< Bit field size in bits for ENET_TGSR_TF3. */
07126 
07127 /*! @brief Read current value of the ENET_TGSR_TF3 field. */
07128 #define BR_ENET_TGSR_TF3(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3)))
07129 
07130 /*! @brief Format value for bitfield ENET_TGSR_TF3. */
07131 #define BF_ENET_TGSR_TF3(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TGSR_TF3) & BM_ENET_TGSR_TF3)
07132 
07133 /*! @brief Set the TF3 field to a new value. */
07134 #define BW_ENET_TGSR_TF3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TGSR_ADDR(x), BP_ENET_TGSR_TF3), v))
07135 /*@}*/
07136 
07137 /*******************************************************************************
07138  * HW_ENET_TCSRn - Timer Control Status Register
07139  ******************************************************************************/
07140 
07141 /*!
07142  * @brief HW_ENET_TCSRn - Timer Control Status Register (RW)
07143  *
07144  * Reset value: 0x00000000U
07145  */
07146 typedef union _hw_enet_tcsrn
07147 {
07148     uint32_t U;
07149     struct _hw_enet_tcsrn_bitfields
07150     {
07151         uint32_t TDRE : 1;             /*!< [0] Timer DMA Request Enable */
07152         uint32_t RESERVED0 : 1;        /*!< [1]  */
07153         uint32_t TMODE : 4;            /*!< [5:2] Timer Mode */
07154         uint32_t TIE : 1;              /*!< [6] Timer Interrupt Enable */
07155         uint32_t TF : 1;               /*!< [7] Timer Flag */
07156         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
07157     } B;
07158 } hw_enet_tcsrn_t;
07159 
07160 /*!
07161  * @name Constants and macros for entire ENET_TCSRn register
07162  */
07163 /*@{*/
07164 #define HW_ENET_TCSRn_COUNT (4U)
07165 
07166 #define HW_ENET_TCSRn_ADDR(x, n) ((x) + 0x608U + (0x8U * (n)))
07167 
07168 #define HW_ENET_TCSRn(x, n)      (*(__IO hw_enet_tcsrn_t *) HW_ENET_TCSRn_ADDR(x, n))
07169 #define HW_ENET_TCSRn_RD(x, n)   (ADDRESS_READ(hw_enet_tcsrn_t, HW_ENET_TCSRn_ADDR(x, n)))
07170 #define HW_ENET_TCSRn_WR(x, n, v) (ADDRESS_WRITE(hw_enet_tcsrn_t, HW_ENET_TCSRn_ADDR(x, n), v))
07171 #define HW_ENET_TCSRn_SET(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) |  (v)))
07172 #define HW_ENET_TCSRn_CLR(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) & ~(v)))
07173 #define HW_ENET_TCSRn_TOG(x, n, v) (HW_ENET_TCSRn_WR(x, n, HW_ENET_TCSRn_RD(x, n) ^  (v)))
07174 /*@}*/
07175 
07176 /*
07177  * Constants & macros for individual ENET_TCSRn bitfields
07178  */
07179 
07180 /*!
07181  * @name Register ENET_TCSRn, field TDRE[0] (RW)
07182  *
07183  * Values:
07184  * - 0 - DMA request is disabled
07185  * - 1 - DMA request is enabled
07186  */
07187 /*@{*/
07188 #define BP_ENET_TCSRn_TDRE   (0U)          /*!< Bit position for ENET_TCSRn_TDRE. */
07189 #define BM_ENET_TCSRn_TDRE   (0x00000001U) /*!< Bit mask for ENET_TCSRn_TDRE. */
07190 #define BS_ENET_TCSRn_TDRE   (1U)          /*!< Bit field size in bits for ENET_TCSRn_TDRE. */
07191 
07192 /*! @brief Read current value of the ENET_TCSRn_TDRE field. */
07193 #define BR_ENET_TCSRn_TDRE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE)))
07194 
07195 /*! @brief Format value for bitfield ENET_TCSRn_TDRE. */
07196 #define BF_ENET_TCSRn_TDRE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TDRE) & BM_ENET_TCSRn_TDRE)
07197 
07198 /*! @brief Set the TDRE field to a new value. */
07199 #define BW_ENET_TCSRn_TDRE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TDRE), v))
07200 /*@}*/
07201 
07202 /*!
07203  * @name Register ENET_TCSRn, field TMODE[5:2] (RW)
07204  *
07205  * Updating the Timer Mode field takes a few cycles to register because it is
07206  * synchronized to the 1588 clock. The version of Timer Mode returned on a read is
07207  * from the 1588 clock domain. When changing Timer Mode, always disable the
07208  * channel and read this register to verify the channel is disabled first.
07209  *
07210  * Values:
07211  * - 0000 - Timer Channel is disabled.
07212  * - 0001 - Timer Channel is configured for Input Capture on rising edge
07213  * - 0010 - Timer Channel is configured for Input Capture on falling edge
07214  * - 0011 - Timer Channel is configured for Input Capture on both edges
07215  * - 0100 - Timer Channel is configured for Output Compare - software only
07216  * - 0101 - Timer Channel is configured for Output Compare - toggle output on
07217  *     compare
07218  * - 0110 - Timer Channel is configured for Output Compare - clear output on
07219  *     compare
07220  * - 0111 - Timer Channel is configured for Output Compare - set output on
07221  *     compare
07222  * - 1000 - Reserved
07223  * - 1010 - Timer Channel is configured for Output Compare - clear output on
07224  *     compare, set output on overflow
07225  * - 10x1 - Timer Channel is configured for Output Compare - set output on
07226  *     compare, clear output on overflow
07227  * - 1100 - Reserved
07228  * - 1110 - Timer Channel is configured for Output Compare - pulse output low on
07229  *     compare for one 1588 clock cycle
07230  * - 1111 - Timer Channel is configured for Output Compare - pulse output high
07231  *     on compare for one 1588 clock cycle
07232  */
07233 /*@{*/
07234 #define BP_ENET_TCSRn_TMODE  (2U)          /*!< Bit position for ENET_TCSRn_TMODE. */
07235 #define BM_ENET_TCSRn_TMODE  (0x0000003CU) /*!< Bit mask for ENET_TCSRn_TMODE. */
07236 #define BS_ENET_TCSRn_TMODE  (4U)          /*!< Bit field size in bits for ENET_TCSRn_TMODE. */
07237 
07238 /*! @brief Read current value of the ENET_TCSRn_TMODE field. */
07239 #define BR_ENET_TCSRn_TMODE(x, n) (UNION_READ(hw_enet_tcsrn_t, HW_ENET_TCSRn_ADDR(x, n), U, B.TMODE))
07240 
07241 /*! @brief Format value for bitfield ENET_TCSRn_TMODE. */
07242 #define BF_ENET_TCSRn_TMODE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TMODE) & BM_ENET_TCSRn_TMODE)
07243 
07244 /*! @brief Set the TMODE field to a new value. */
07245 #define BW_ENET_TCSRn_TMODE(x, n, v) (HW_ENET_TCSRn_WR(x, n, (HW_ENET_TCSRn_RD(x, n) & ~BM_ENET_TCSRn_TMODE) | BF_ENET_TCSRn_TMODE(v)))
07246 /*@}*/
07247 
07248 /*!
07249  * @name Register ENET_TCSRn, field TIE[6] (RW)
07250  *
07251  * Values:
07252  * - 0 - Interrupt is disabled
07253  * - 1 - Interrupt is enabled
07254  */
07255 /*@{*/
07256 #define BP_ENET_TCSRn_TIE    (6U)          /*!< Bit position for ENET_TCSRn_TIE. */
07257 #define BM_ENET_TCSRn_TIE    (0x00000040U) /*!< Bit mask for ENET_TCSRn_TIE. */
07258 #define BS_ENET_TCSRn_TIE    (1U)          /*!< Bit field size in bits for ENET_TCSRn_TIE. */
07259 
07260 /*! @brief Read current value of the ENET_TCSRn_TIE field. */
07261 #define BR_ENET_TCSRn_TIE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE)))
07262 
07263 /*! @brief Format value for bitfield ENET_TCSRn_TIE. */
07264 #define BF_ENET_TCSRn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TIE) & BM_ENET_TCSRn_TIE)
07265 
07266 /*! @brief Set the TIE field to a new value. */
07267 #define BW_ENET_TCSRn_TIE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TIE), v))
07268 /*@}*/
07269 
07270 /*!
07271  * @name Register ENET_TCSRn, field TF[7] (W1C)
07272  *
07273  * Sets when input capture or output compare occurs. This flag is double
07274  * buffered between the module clock and 1588 clock domains. When this field is 1, it
07275  * can be cleared to 0 by writing 1 to it.
07276  *
07277  * Values:
07278  * - 0 - Input Capture or Output Compare has not occurred
07279  * - 1 - Input Capture or Output Compare has occurred
07280  */
07281 /*@{*/
07282 #define BP_ENET_TCSRn_TF     (7U)          /*!< Bit position for ENET_TCSRn_TF. */
07283 #define BM_ENET_TCSRn_TF     (0x00000080U) /*!< Bit mask for ENET_TCSRn_TF. */
07284 #define BS_ENET_TCSRn_TF     (1U)          /*!< Bit field size in bits for ENET_TCSRn_TF. */
07285 
07286 /*! @brief Read current value of the ENET_TCSRn_TF field. */
07287 #define BR_ENET_TCSRn_TF(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF)))
07288 
07289 /*! @brief Format value for bitfield ENET_TCSRn_TF. */
07290 #define BF_ENET_TCSRn_TF(v)  ((uint32_t)((uint32_t)(v) << BP_ENET_TCSRn_TF) & BM_ENET_TCSRn_TF)
07291 
07292 /*! @brief Set the TF field to a new value. */
07293 #define BW_ENET_TCSRn_TF(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_ENET_TCSRn_ADDR(x, n), BP_ENET_TCSRn_TF), v))
07294 /*@}*/
07295 /*******************************************************************************
07296  * HW_ENET_TCCRn - Timer Compare Capture Register
07297  ******************************************************************************/
07298 
07299 /*!
07300  * @brief HW_ENET_TCCRn - Timer Compare Capture Register (RW)
07301  *
07302  * Reset value: 0x00000000U
07303  */
07304 typedef union _hw_enet_tccrn
07305 {
07306     uint32_t U;
07307     struct _hw_enet_tccrn_bitfields
07308     {
07309         uint32_t TCC : 32;             /*!< [31:0] Timer Capture Compare */
07310     } B;
07311 } hw_enet_tccrn_t;
07312 
07313 /*!
07314  * @name Constants and macros for entire ENET_TCCRn register
07315  */
07316 /*@{*/
07317 #define HW_ENET_TCCRn_COUNT (4U)
07318 
07319 #define HW_ENET_TCCRn_ADDR(x, n) ((x) + 0x60CU + (0x8U * (n)))
07320 
07321 #define HW_ENET_TCCRn(x, n)      (*(__IO hw_enet_tccrn_t *) HW_ENET_TCCRn_ADDR(x, n))
07322 #define HW_ENET_TCCRn_RD(x, n)   (ADDRESS_READ(hw_enet_tccrn_t, HW_ENET_TCCRn_ADDR(x, n)))
07323 #define HW_ENET_TCCRn_WR(x, n, v) (ADDRESS_WRITE(hw_enet_tccrn_t, HW_ENET_TCCRn_ADDR(x, n), v))
07324 #define HW_ENET_TCCRn_SET(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) |  (v)))
07325 #define HW_ENET_TCCRn_CLR(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) & ~(v)))
07326 #define HW_ENET_TCCRn_TOG(x, n, v) (HW_ENET_TCCRn_WR(x, n, HW_ENET_TCCRn_RD(x, n) ^  (v)))
07327 /*@}*/
07328 
07329 /*
07330  * Constants & macros for individual ENET_TCCRn bitfields
07331  */
07332 
07333 /*!
07334  * @name Register ENET_TCCRn, field TCC[31:0] (RW)
07335  *
07336  * This register is double buffered between the module clock and 1588 clock
07337  * domains. When configured for compare, the 1588 clock domain updates with the value
07338  * in the module clock domain whenever the Timer Channel is first enabled and on
07339  * each subsequent compare. Write to this register with the first compare value
07340  * before enabling the Timer Channel. When the Timer Channel is enabled, write
07341  * the second compare value either immediately, or at least before the first
07342  * compare occurs. After each compare, write the next compare value before the previous
07343  * compare occurs and before clearing the Timer Flag. The compare occurs one
07344  * 1588 clock cycle after the IEEE 1588 Counter increments past the compare value in
07345  * the 1588 clock domain. If the compare value is less than the value of the
07346  * 1588 Counter when the Timer Channel is first enabled, then the compare does not
07347  * occur until following the next overflow of the 1588 Counter. If the compare
07348  * value is greater than the IEEE 1588 Counter when the 1588 Counter overflows, or
07349  * the compare value is less than the value of the IEEE 1588 Counter after the
07350  * overflow, then the compare occurs one 1588 clock cycle following the overflow.
07351  * When configured for Capture, the value of the IEEE 1588 Counter is captured into
07352  * the 1588 clock domain and then updated into the module clock domain, provided
07353  * the Timer Flag is clear. Always read the capture value before clearing the
07354  * Timer Flag.
07355  */
07356 /*@{*/
07357 #define BP_ENET_TCCRn_TCC    (0U)          /*!< Bit position for ENET_TCCRn_TCC. */
07358 #define BM_ENET_TCCRn_TCC    (0xFFFFFFFFU) /*!< Bit mask for ENET_TCCRn_TCC. */
07359 #define BS_ENET_TCCRn_TCC    (32U)         /*!< Bit field size in bits for ENET_TCCRn_TCC. */
07360 
07361 /*! @brief Read current value of the ENET_TCCRn_TCC field. */
07362 #define BR_ENET_TCCRn_TCC(x, n) (HW_ENET_TCCRn(x, n).U)
07363 
07364 /*! @brief Format value for bitfield ENET_TCCRn_TCC. */
07365 #define BF_ENET_TCCRn_TCC(v) ((uint32_t)((uint32_t)(v) << BP_ENET_TCCRn_TCC) & BM_ENET_TCCRn_TCC)
07366 
07367 /*! @brief Set the TCC field to a new value. */
07368 #define BW_ENET_TCCRn_TCC(x, n, v) (HW_ENET_TCCRn_WR(x, n, v))
07369 /*@}*/
07370 
07371 /*******************************************************************************
07372  * hw_enet_t - module struct
07373  ******************************************************************************/
07374 /*!
07375  * @brief All ENET module registers.
07376  */
07377 #pragma pack(1)
07378 typedef struct _hw_enet
07379 {
07380     uint8_t _reserved0[4];
07381     __IO hw_enet_eir_t EIR ;                /*!< [0x4] Interrupt Event Register */
07382     __IO hw_enet_eimr_t EIMR ;              /*!< [0x8] Interrupt Mask Register */
07383     uint8_t _reserved1[4];
07384     __IO hw_enet_rdar_t RDAR ;              /*!< [0x10] Receive Descriptor Active Register */
07385     __IO hw_enet_tdar_t TDAR ;              /*!< [0x14] Transmit Descriptor Active Register */
07386     uint8_t _reserved2[12];
07387     __IO hw_enet_ecr_t ECR ;                /*!< [0x24] Ethernet Control Register */
07388     uint8_t _reserved3[24];
07389     __IO hw_enet_mmfr_t MMFR ;              /*!< [0x40] MII Management Frame Register */
07390     __IO hw_enet_mscr_t MSCR ;              /*!< [0x44] MII Speed Control Register */
07391     uint8_t _reserved4[28];
07392     __IO hw_enet_mibc_t MIBC ;              /*!< [0x64] MIB Control Register */
07393     uint8_t _reserved5[28];
07394     __IO hw_enet_rcr_t RCR ;                /*!< [0x84] Receive Control Register */
07395     uint8_t _reserved6[60];
07396     __IO hw_enet_tcr_t TCR ;                /*!< [0xC4] Transmit Control Register */
07397     uint8_t _reserved7[28];
07398     __IO hw_enet_palr_t PALR ;              /*!< [0xE4] Physical Address Lower Register */
07399     __IO hw_enet_paur_t PAUR ;              /*!< [0xE8] Physical Address Upper Register */
07400     __IO hw_enet_opd_t OPD ;                /*!< [0xEC] Opcode/Pause Duration Register */
07401     uint8_t _reserved8[40];
07402     __IO hw_enet_iaur_t IAUR ;              /*!< [0x118] Descriptor Individual Upper Address Register */
07403     __IO hw_enet_ialr_t IALR ;              /*!< [0x11C] Descriptor Individual Lower Address Register */
07404     __IO hw_enet_gaur_t GAUR ;              /*!< [0x120] Descriptor Group Upper Address Register */
07405     __IO hw_enet_galr_t GALR ;              /*!< [0x124] Descriptor Group Lower Address Register */
07406     uint8_t _reserved9[28];
07407     __IO hw_enet_tfwr_t TFWR ;              /*!< [0x144] Transmit FIFO Watermark Register */
07408     uint8_t _reserved10[56];
07409     __IO hw_enet_rdsr_t RDSR ;              /*!< [0x180] Receive Descriptor Ring Start Register */
07410     __IO hw_enet_tdsr_t TDSR ;              /*!< [0x184] Transmit Buffer Descriptor Ring Start Register */
07411     __IO hw_enet_mrbr_t MRBR ;              /*!< [0x188] Maximum Receive Buffer Size Register */
07412     uint8_t _reserved11[4];
07413     __IO hw_enet_rsfl_t RSFL ;              /*!< [0x190] Receive FIFO Section Full Threshold */
07414     __IO hw_enet_rsem_t RSEM ;              /*!< [0x194] Receive FIFO Section Empty Threshold */
07415     __IO hw_enet_raem_t RAEM ;              /*!< [0x198] Receive FIFO Almost Empty Threshold */
07416     __IO hw_enet_rafl_t RAFL ;              /*!< [0x19C] Receive FIFO Almost Full Threshold */
07417     __IO hw_enet_tsem_t TSEM ;              /*!< [0x1A0] Transmit FIFO Section Empty Threshold */
07418     __IO hw_enet_taem_t TAEM ;              /*!< [0x1A4] Transmit FIFO Almost Empty Threshold */
07419     __IO hw_enet_tafl_t TAFL ;              /*!< [0x1A8] Transmit FIFO Almost Full Threshold */
07420     __IO hw_enet_tipg_t TIPG ;              /*!< [0x1AC] Transmit Inter-Packet Gap */
07421     __IO hw_enet_ftrl_t FTRL ;              /*!< [0x1B0] Frame Truncation Length */
07422     uint8_t _reserved12[12];
07423     __IO hw_enet_tacc_t TACC ;              /*!< [0x1C0] Transmit Accelerator Function Configuration */
07424     __IO hw_enet_racc_t RACC ;              /*!< [0x1C4] Receive Accelerator Function Configuration */
07425     uint8_t _reserved13[60];
07426     __I hw_enet_rmon_t_packets_t RMON_T_PACKETS ; /*!< [0x204] Tx Packet Count Statistic Register */
07427     __I hw_enet_rmon_t_bc_pkt_t RMON_T_BC_PKT ; /*!< [0x208] Tx Broadcast Packets Statistic Register */
07428     __I hw_enet_rmon_t_mc_pkt_t RMON_T_MC_PKT ; /*!< [0x20C] Tx Multicast Packets Statistic Register */
07429     __I hw_enet_rmon_t_crc_align_t RMON_T_CRC_ALIGN ; /*!< [0x210] Tx Packets with CRC/Align Error Statistic Register */
07430     __I hw_enet_rmon_t_undersize_t RMON_T_UNDERSIZE ; /*!< [0x214] Tx Packets Less Than Bytes and Good CRC Statistic Register */
07431     __I hw_enet_rmon_t_oversize_t RMON_T_OVERSIZE ; /*!< [0x218] Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
07432     __I hw_enet_rmon_t_frag_t RMON_T_FRAG ; /*!< [0x21C] Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
07433     __I hw_enet_rmon_t_jab_t RMON_T_JAB ;   /*!< [0x220] Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
07434     __I hw_enet_rmon_t_col_t RMON_T_COL ;   /*!< [0x224] Tx Collision Count Statistic Register */
07435     __I hw_enet_rmon_t_p64_t RMON_T_P64 ;   /*!< [0x228] Tx 64-Byte Packets Statistic Register */
07436     __I hw_enet_rmon_t_p65to127_t RMON_T_P65TO127 ; /*!< [0x22C] Tx 65- to 127-byte Packets Statistic Register */
07437     __I hw_enet_rmon_t_p128to255_t RMON_T_P128TO255 ; /*!< [0x230] Tx 128- to 255-byte Packets Statistic Register */
07438     __I hw_enet_rmon_t_p256to511_t RMON_T_P256TO511 ; /*!< [0x234] Tx 256- to 511-byte Packets Statistic Register */
07439     __I hw_enet_rmon_t_p512to1023_t RMON_T_P512TO1023 ; /*!< [0x238] Tx 512- to 1023-byte Packets Statistic Register */
07440     __I hw_enet_rmon_t_p1024to2047_t RMON_T_P1024TO2047 ; /*!< [0x23C] Tx 1024- to 2047-byte Packets Statistic Register */
07441     __I hw_enet_rmon_t_p_gte2048_t RMON_T_P_GTE2048 ; /*!< [0x240] Tx Packets Greater Than 2048 Bytes Statistic Register */
07442     __I hw_enet_rmon_t_octets_t RMON_T_OCTETS ; /*!< [0x244] Tx Octets Statistic Register */
07443     uint8_t _reserved14[4];
07444     __I hw_enet_ieee_t_frame_ok_t IEEE_T_FRAME_OK ; /*!< [0x24C] Frames Transmitted OK Statistic Register */
07445     __I hw_enet_ieee_t_1col_t IEEE_T_1COL ; /*!< [0x250] Frames Transmitted with Single Collision Statistic Register */
07446     __I hw_enet_ieee_t_mcol_t IEEE_T_MCOL ; /*!< [0x254] Frames Transmitted with Multiple Collisions Statistic Register */
07447     __I hw_enet_ieee_t_def_t IEEE_T_DEF ;   /*!< [0x258] Frames Transmitted after Deferral Delay Statistic Register */
07448     __I hw_enet_ieee_t_lcol_t IEEE_T_LCOL ; /*!< [0x25C] Frames Transmitted with Late Collision Statistic Register */
07449     __I hw_enet_ieee_t_excol_t IEEE_T_EXCOL ; /*!< [0x260] Frames Transmitted with Excessive Collisions Statistic Register */
07450     __I hw_enet_ieee_t_macerr_t IEEE_T_MACERR ; /*!< [0x264] Frames Transmitted with Tx FIFO Underrun Statistic Register */
07451     __I hw_enet_ieee_t_cserr_t IEEE_T_CSERR ; /*!< [0x268] Frames Transmitted with Carrier Sense Error Statistic Register */
07452     uint8_t _reserved15[4];
07453     __I hw_enet_ieee_t_fdxfc_t IEEE_T_FDXFC ; /*!< [0x270] Flow Control Pause Frames Transmitted Statistic Register */
07454     __I hw_enet_ieee_t_octets_ok_t IEEE_T_OCTETS_OK ; /*!< [0x274] Octet Count for Frames Transmitted w/o Error Statistic Register */
07455     uint8_t _reserved16[12];
07456     __I hw_enet_rmon_r_packets_t RMON_R_PACKETS ; /*!< [0x284] Rx Packet Count Statistic Register */
07457     __I hw_enet_rmon_r_bc_pkt_t RMON_R_BC_PKT ; /*!< [0x288] Rx Broadcast Packets Statistic Register */
07458     __I hw_enet_rmon_r_mc_pkt_t RMON_R_MC_PKT ; /*!< [0x28C] Rx Multicast Packets Statistic Register */
07459     __I hw_enet_rmon_r_crc_align_t RMON_R_CRC_ALIGN ; /*!< [0x290] Rx Packets with CRC/Align Error Statistic Register */
07460     __I hw_enet_rmon_r_undersize_t RMON_R_UNDERSIZE ; /*!< [0x294] Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
07461     __I hw_enet_rmon_r_oversize_t RMON_R_OVERSIZE ; /*!< [0x298] Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
07462     __I hw_enet_rmon_r_frag_t RMON_R_FRAG ; /*!< [0x29C] Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
07463     __I hw_enet_rmon_r_jab_t RMON_R_JAB ;   /*!< [0x2A0] Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
07464     uint8_t _reserved17[4];
07465     __I hw_enet_rmon_r_p64_t RMON_R_P64 ;   /*!< [0x2A8] Rx 64-Byte Packets Statistic Register */
07466     __I hw_enet_rmon_r_p65to127_t RMON_R_P65TO127 ; /*!< [0x2AC] Rx 65- to 127-Byte Packets Statistic Register */
07467     __I hw_enet_rmon_r_p128to255_t RMON_R_P128TO255 ; /*!< [0x2B0] Rx 128- to 255-Byte Packets Statistic Register */
07468     __I hw_enet_rmon_r_p256to511_t RMON_R_P256TO511 ; /*!< [0x2B4] Rx 256- to 511-Byte Packets Statistic Register */
07469     __I hw_enet_rmon_r_p512to1023_t RMON_R_P512TO1023 ; /*!< [0x2B8] Rx 512- to 1023-Byte Packets Statistic Register */
07470     __I hw_enet_rmon_r_p1024to2047_t RMON_R_P1024TO2047 ; /*!< [0x2BC] Rx 1024- to 2047-Byte Packets Statistic Register */
07471     __I hw_enet_rmon_r_p_gte2048_t RMON_R_P_GTE2048 ; /*!< [0x2C0] Rx Packets Greater than 2048 Bytes Statistic Register */
07472     __I hw_enet_rmon_r_octets_t RMON_R_OCTETS ; /*!< [0x2C4] Rx Octets Statistic Register */
07473     __I hw_enet_ieee_r_drop_t IEEE_R_DROP ; /*!< [0x2C8] Frames not Counted Correctly Statistic Register */
07474     __I hw_enet_ieee_r_frame_ok_t IEEE_R_FRAME_OK ; /*!< [0x2CC] Frames Received OK Statistic Register */
07475     __I hw_enet_ieee_r_crc_t IEEE_R_CRC ;   /*!< [0x2D0] Frames Received with CRC Error Statistic Register */
07476     __I hw_enet_ieee_r_align_t IEEE_R_ALIGN ; /*!< [0x2D4] Frames Received with Alignment Error Statistic Register */
07477     __I hw_enet_ieee_r_macerr_t IEEE_R_MACERR ; /*!< [0x2D8] Receive FIFO Overflow Count Statistic Register */
07478     __I hw_enet_ieee_r_fdxfc_t IEEE_R_FDXFC ; /*!< [0x2DC] Flow Control Pause Frames Received Statistic Register */
07479     __I hw_enet_ieee_r_octets_ok_t IEEE_R_OCTETS_OK ; /*!< [0x2E0] Octet Count for Frames Received without Error Statistic Register */
07480     uint8_t _reserved18[284];
07481     __IO hw_enet_atcr_t ATCR ;              /*!< [0x400] Adjustable Timer Control Register */
07482     __IO hw_enet_atvr_t ATVR ;              /*!< [0x404] Timer Value Register */
07483     __IO hw_enet_atoff_t ATOFF ;            /*!< [0x408] Timer Offset Register */
07484     __IO hw_enet_atper_t ATPER ;            /*!< [0x40C] Timer Period Register */
07485     __IO hw_enet_atcor_t ATCOR ;            /*!< [0x410] Timer Correction Register */
07486     __IO hw_enet_atinc_t ATINC ;            /*!< [0x414] Time-Stamping Clock Period Register */
07487     __I hw_enet_atstmp_t ATSTMP ;           /*!< [0x418] Timestamp of Last Transmitted Frame */
07488     uint8_t _reserved19[488];
07489     __IO hw_enet_tgsr_t TGSR ;              /*!< [0x604] Timer Global Status Register */
07490     struct {
07491         __IO hw_enet_tcsrn_t TCSRn ;        /*!< [0x608] Timer Control Status Register */
07492         __IO hw_enet_tccrn_t TCCRn ;        /*!< [0x60C] Timer Compare Capture Register */
07493     } CHANNEL[4];
07494 } hw_enet_t;
07495 #pragma pack()
07496 
07497 /*! @brief Macro to access all ENET registers. */
07498 /*! @param x ENET module instance base address. */
07499 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
07500  *     use the '&' operator, like <code>&HW_ENET(ENET_BASE)</code>. */
07501 #define HW_ENET(x)     (*(hw_enet_t *)(x))
07502 
07503 #endif /* __HW_ENET_REGISTERS_H__ */
07504 /* EOF */