_hw_enet_tfwr Union Reference

HW_ENET_TFWR - Transmit FIFO Watermark Register (RW) More...

#include <MK64F12_enet.h>

Detailed Description

HW_ENET_TFWR - Transmit FIFO Watermark Register (RW)

Reset value: 0x00000000U

If TFWR[STRFWD] is cleared, TFWR[TFWR] controls the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows you to minimize transmit latency (TFWR = 00 or 01) or allow for larger bus access latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value minimizes the risk of transmit FIFO underrun due to contention for the system bus. The byte counts associated with the TFWR field may need to be modified to match a given system requirement. For example, worst case bus access latency by the transmit data DMA channel. When the FIFO level reaches the value the TFWR field and when the STR_FWD is set to '0', the MAC transmit control logic starts frame transmission even before the end-of-frame is available in the FIFO (cut-through operation). If a complete frame has a size smaller than the threshold programmed with TFWR, the MAC also transmits the Frame to the line. To enable store and forward on the Transmit path, set STR_FWD to '1'. In this case, the MAC starts to transmit data only when a complete frame is stored in the Transmit FIFO.

Definition at line 2976 of file MK64F12_enet.h.