_hw_enet_mscr Union Reference

HW_ENET_MSCR - MII Speed Control Register (RW) More...

#include <MK64F12_enet.h>

Detailed Description

HW_ENET_MSCR - MII Speed Control Register (RW)

Reset value: 0x00000000U

MSCR provides control of the MII clock (MDC pin) frequency and allows a preamble drop on the MII management frame. The MII_SPEED field must be programmed with a value to provide an MDC frequency of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to a non-zero value to source a read or write management frame. After the management frame is complete, the MSCR register may optionally be cleared to turn off MDC. The MDC signal generated has a 50% duty cycle except when MII_SPEED changes during operation. This change takes effect following a rising or falling edge of MDC. If the internal module clock is 25 MHz, programming this register to 0x0000_0004 results in an MDC as stated in the following equation: 25 MHz / ((4 + 1) x 2) = 2.5 MHz The following table shows the optimum values for MII_SPEED as a function of internal module clock frequency. Programming Examples for MSCR Internal MAC clock frequency MSCR [MII_SPEED] MDC frequency 25 MHz 0x4 2.50 MHz 33 MHz 0x6 2.36 MHz 40 MHz 0x7 2.50 MHz 50 MHz 0x9 2.50 MHz 66 MHz 0xD 2.36 MHz

Definition at line 1649 of file MK64F12_enet.h.