MK64F12_dma.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_DMA_REGISTERS_H__
00088 #define __HW_DMA_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 DMA
00095  *
00096  * Enhanced direct memory access controller
00097  *
00098  * Registers defined in this header file:
00099  * - HW_DMA_CR - Control Register
00100  * - HW_DMA_ES - Error Status Register
00101  * - HW_DMA_ERQ - Enable Request Register
00102  * - HW_DMA_EEI - Enable Error Interrupt Register
00103  * - HW_DMA_CEEI - Clear Enable Error Interrupt Register
00104  * - HW_DMA_SEEI - Set Enable Error Interrupt Register
00105  * - HW_DMA_CERQ - Clear Enable Request Register
00106  * - HW_DMA_SERQ - Set Enable Request Register
00107  * - HW_DMA_CDNE - Clear DONE Status Bit Register
00108  * - HW_DMA_SSRT - Set START Bit Register
00109  * - HW_DMA_CERR - Clear Error Register
00110  * - HW_DMA_CINT - Clear Interrupt Request Register
00111  * - HW_DMA_INT - Interrupt Request Register
00112  * - HW_DMA_ERR - Error Register
00113  * - HW_DMA_HRS - Hardware Request Status Register
00114  * - HW_DMA_DCHPRIn - Channel n Priority Register
00115  * - HW_DMA_TCDn_SADDR - TCD Source Address
00116  * - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
00117  * - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
00118  * - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
00119  * - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
00120  * - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
00121  * - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
00122  * - HW_DMA_TCDn_DADDR - TCD Destination Address
00123  * - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
00124  * - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
00125  * - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
00126  * - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
00127  * - HW_DMA_TCDn_CSR - TCD Control and Status
00128  * - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
00129  * - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
00130  *
00131  * - hw_dma_t - Struct containing all module registers.
00132  */
00133 
00134 #define HW_DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
00135 
00136 /*******************************************************************************
00137  * HW_DMA_CR - Control Register
00138  ******************************************************************************/
00139 
00140 /*!
00141  * @brief HW_DMA_CR - Control Register (RW)
00142  *
00143  * Reset value: 0x00000000U
00144  *
00145  * The CR defines the basic operating configuration of the DMA. Arbitration can
00146  * be configured to use either a fixed-priority or a round-robin scheme. For
00147  * fixed-priority arbitration, the highest priority channel requesting service is
00148  * selected to execute. The channel priority registers assign the priorities; see
00149  * the DCHPRIn registers. For round-robin arbitration, the channel priorities are
00150  * ignored and channels are cycled through (from high to low channel number)
00151  * without regard to priority. For correct operation, writes to the CR register must
00152  * be performed only when the DMA channels are inactive; that is, when
00153  * TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
00154  * the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
00155  * minor loop completion. When minor loop offsets are enabled, the minor loop
00156  * offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
00157  * destination address (TCDn_DADDR), or to both prior to the addresses being
00158  * written back into the TCD. If the major loop is complete, the minor loop offset is
00159  * ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
00160  * used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
00161  * mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
00162  * is used to specify multiple fields: a source enable bit (SMLOE) to specify
00163  * the minor loop offset should be applied to the source address (TCDn_SADDR) upon
00164  * minor loop completion, a destination enable bit (DMLOE) to specify the minor
00165  * loop offset should be applied to the destination address (TCDn_DADDR) upon
00166  * minor loop completion, and the sign extended minor loop offset value (MLOFF). The
00167  * same offset value (MLOFF) is used for both source and destination minor loop
00168  * offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
00169  * NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
00170  * (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
00171  * minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
00172  * assigned to the NBYTES field.
00173  */
00174 typedef union _hw_dma_cr
00175 {
00176     uint32_t U;
00177     struct _hw_dma_cr_bitfields
00178     {
00179         uint32_t RESERVED0 : 1;        /*!< [0] Reserved. */
00180         uint32_t EDBG : 1;             /*!< [1] Enable Debug */
00181         uint32_t ERCA : 1;             /*!< [2] Enable Round Robin Channel Arbitration */
00182         uint32_t RESERVED1 : 1;        /*!< [3] Reserved. */
00183         uint32_t HOE : 1;              /*!< [4] Halt On Error */
00184         uint32_t HALT : 1;             /*!< [5] Halt DMA Operations */
00185         uint32_t CLM : 1;              /*!< [6] Continuous Link Mode */
00186         uint32_t EMLM : 1;             /*!< [7] Enable Minor Loop Mapping */
00187         uint32_t RESERVED2 : 8;        /*!< [15:8]  */
00188         uint32_t ECX : 1;              /*!< [16] Error Cancel Transfer */
00189         uint32_t CX : 1;               /*!< [17] Cancel Transfer */
00190         uint32_t RESERVED3 : 14;       /*!< [31:18]  */
00191     } B;
00192 } hw_dma_cr_t;
00193 
00194 /*!
00195  * @name Constants and macros for entire DMA_CR register
00196  */
00197 /*@{*/
00198 #define HW_DMA_CR_ADDR(x)        ((x) + 0x0U)
00199 
00200 #define HW_DMA_CR(x)             (*(__IO hw_dma_cr_t *) HW_DMA_CR_ADDR(x))
00201 #define HW_DMA_CR_RD(x)          (ADDRESS_READ(hw_dma_cr_t, HW_DMA_CR_ADDR(x)))
00202 #define HW_DMA_CR_WR(x, v)       (ADDRESS_WRITE(hw_dma_cr_t, HW_DMA_CR_ADDR(x), v))
00203 #define HW_DMA_CR_SET(x, v)      (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) |  (v)))
00204 #define HW_DMA_CR_CLR(x, v)      (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
00205 #define HW_DMA_CR_TOG(x, v)      (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^  (v)))
00206 /*@}*/
00207 
00208 /*
00209  * Constants & macros for individual DMA_CR bitfields
00210  */
00211 
00212 /*!
00213  * @name Register DMA_CR, field EDBG[1] (RW)
00214  *
00215  * Values:
00216  * - 0 - When in debug mode, the DMA continues to operate.
00217  * - 1 - When in debug mode, the DMA stalls the start of a new channel.
00218  *     Executing channels are allowed to complete. Channel execution resumes when the
00219  *     system exits debug mode or the EDBG bit is cleared.
00220  */
00221 /*@{*/
00222 #define BP_DMA_CR_EDBG       (1U)          /*!< Bit position for DMA_CR_EDBG. */
00223 #define BM_DMA_CR_EDBG       (0x00000002U) /*!< Bit mask for DMA_CR_EDBG. */
00224 #define BS_DMA_CR_EDBG       (1U)          /*!< Bit field size in bits for DMA_CR_EDBG. */
00225 
00226 /*! @brief Read current value of the DMA_CR_EDBG field. */
00227 #define BR_DMA_CR_EDBG(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG)))
00228 
00229 /*! @brief Format value for bitfield DMA_CR_EDBG. */
00230 #define BF_DMA_CR_EDBG(v)    ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EDBG) & BM_DMA_CR_EDBG)
00231 
00232 /*! @brief Set the EDBG field to a new value. */
00233 #define BW_DMA_CR_EDBG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG), v))
00234 /*@}*/
00235 
00236 /*!
00237  * @name Register DMA_CR, field ERCA[2] (RW)
00238  *
00239  * Values:
00240  * - 0 - Fixed priority arbitration is used for channel selection .
00241  * - 1 - Round robin arbitration is used for channel selection .
00242  */
00243 /*@{*/
00244 #define BP_DMA_CR_ERCA       (2U)          /*!< Bit position for DMA_CR_ERCA. */
00245 #define BM_DMA_CR_ERCA       (0x00000004U) /*!< Bit mask for DMA_CR_ERCA. */
00246 #define BS_DMA_CR_ERCA       (1U)          /*!< Bit field size in bits for DMA_CR_ERCA. */
00247 
00248 /*! @brief Read current value of the DMA_CR_ERCA field. */
00249 #define BR_DMA_CR_ERCA(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA)))
00250 
00251 /*! @brief Format value for bitfield DMA_CR_ERCA. */
00252 #define BF_DMA_CR_ERCA(v)    ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ERCA) & BM_DMA_CR_ERCA)
00253 
00254 /*! @brief Set the ERCA field to a new value. */
00255 #define BW_DMA_CR_ERCA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA), v))
00256 /*@}*/
00257 
00258 /*!
00259  * @name Register DMA_CR, field HOE[4] (RW)
00260  *
00261  * Values:
00262  * - 0 - Normal operation
00263  * - 1 - Any error causes the HALT bit to set. Subsequently, all service
00264  *     requests are ignored until the HALT bit is cleared.
00265  */
00266 /*@{*/
00267 #define BP_DMA_CR_HOE        (4U)          /*!< Bit position for DMA_CR_HOE. */
00268 #define BM_DMA_CR_HOE        (0x00000010U) /*!< Bit mask for DMA_CR_HOE. */
00269 #define BS_DMA_CR_HOE        (1U)          /*!< Bit field size in bits for DMA_CR_HOE. */
00270 
00271 /*! @brief Read current value of the DMA_CR_HOE field. */
00272 #define BR_DMA_CR_HOE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE)))
00273 
00274 /*! @brief Format value for bitfield DMA_CR_HOE. */
00275 #define BF_DMA_CR_HOE(v)     ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HOE) & BM_DMA_CR_HOE)
00276 
00277 /*! @brief Set the HOE field to a new value. */
00278 #define BW_DMA_CR_HOE(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE), v))
00279 /*@}*/
00280 
00281 /*!
00282  * @name Register DMA_CR, field HALT[5] (RW)
00283  *
00284  * Values:
00285  * - 0 - Normal operation
00286  * - 1 - Stall the start of any new channels. Executing channels are allowed to
00287  *     complete. Channel execution resumes when this bit is cleared.
00288  */
00289 /*@{*/
00290 #define BP_DMA_CR_HALT       (5U)          /*!< Bit position for DMA_CR_HALT. */
00291 #define BM_DMA_CR_HALT       (0x00000020U) /*!< Bit mask for DMA_CR_HALT. */
00292 #define BS_DMA_CR_HALT       (1U)          /*!< Bit field size in bits for DMA_CR_HALT. */
00293 
00294 /*! @brief Read current value of the DMA_CR_HALT field. */
00295 #define BR_DMA_CR_HALT(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT)))
00296 
00297 /*! @brief Format value for bitfield DMA_CR_HALT. */
00298 #define BF_DMA_CR_HALT(v)    ((uint32_t)((uint32_t)(v) << BP_DMA_CR_HALT) & BM_DMA_CR_HALT)
00299 
00300 /*! @brief Set the HALT field to a new value. */
00301 #define BW_DMA_CR_HALT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT), v))
00302 /*@}*/
00303 
00304 /*!
00305  * @name Register DMA_CR, field CLM[6] (RW)
00306  *
00307  * Values:
00308  * - 0 - A minor loop channel link made to itself goes through channel
00309  *     arbitration before being activated again.
00310  * - 1 - A minor loop channel link made to itself does not go through channel
00311  *     arbitration before being activated again. Upon minor loop completion, the
00312  *     channel activates again if that channel has a minor loop channel link
00313  *     enabled and the link channel is itself. This effectively applies the minor loop
00314  *     offsets and restarts the next minor loop.
00315  */
00316 /*@{*/
00317 #define BP_DMA_CR_CLM        (6U)          /*!< Bit position for DMA_CR_CLM. */
00318 #define BM_DMA_CR_CLM        (0x00000040U) /*!< Bit mask for DMA_CR_CLM. */
00319 #define BS_DMA_CR_CLM        (1U)          /*!< Bit field size in bits for DMA_CR_CLM. */
00320 
00321 /*! @brief Read current value of the DMA_CR_CLM field. */
00322 #define BR_DMA_CR_CLM(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM)))
00323 
00324 /*! @brief Format value for bitfield DMA_CR_CLM. */
00325 #define BF_DMA_CR_CLM(v)     ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CLM) & BM_DMA_CR_CLM)
00326 
00327 /*! @brief Set the CLM field to a new value. */
00328 #define BW_DMA_CR_CLM(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM), v))
00329 /*@}*/
00330 
00331 /*!
00332  * @name Register DMA_CR, field EMLM[7] (RW)
00333  *
00334  * Values:
00335  * - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
00336  * - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
00337  *     an offset field, and the NBYTES field. The individual enable fields allow
00338  *     the minor loop offset to be applied to the source address, the destination
00339  *     address, or both. The NBYTES field is reduced when either offset is
00340  *     enabled.
00341  */
00342 /*@{*/
00343 #define BP_DMA_CR_EMLM       (7U)          /*!< Bit position for DMA_CR_EMLM. */
00344 #define BM_DMA_CR_EMLM       (0x00000080U) /*!< Bit mask for DMA_CR_EMLM. */
00345 #define BS_DMA_CR_EMLM       (1U)          /*!< Bit field size in bits for DMA_CR_EMLM. */
00346 
00347 /*! @brief Read current value of the DMA_CR_EMLM field. */
00348 #define BR_DMA_CR_EMLM(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM)))
00349 
00350 /*! @brief Format value for bitfield DMA_CR_EMLM. */
00351 #define BF_DMA_CR_EMLM(v)    ((uint32_t)((uint32_t)(v) << BP_DMA_CR_EMLM) & BM_DMA_CR_EMLM)
00352 
00353 /*! @brief Set the EMLM field to a new value. */
00354 #define BW_DMA_CR_EMLM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM), v))
00355 /*@}*/
00356 
00357 /*!
00358  * @name Register DMA_CR, field ECX[16] (RW)
00359  *
00360  * Values:
00361  * - 0 - Normal operation
00362  * - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
00363  *     Stop the executing channel and force the minor loop to finish. The cancel
00364  *     takes effect after the last write of the current read/write sequence. The
00365  *     ECX bit clears itself after the cancel is honored. In addition to
00366  *     cancelling the transfer, ECX treats the cancel as an error condition, thus updating
00367  *     the Error Status register (DMAx_ES) and generating an optional error
00368  *     interrupt.
00369  */
00370 /*@{*/
00371 #define BP_DMA_CR_ECX        (16U)         /*!< Bit position for DMA_CR_ECX. */
00372 #define BM_DMA_CR_ECX        (0x00010000U) /*!< Bit mask for DMA_CR_ECX. */
00373 #define BS_DMA_CR_ECX        (1U)          /*!< Bit field size in bits for DMA_CR_ECX. */
00374 
00375 /*! @brief Read current value of the DMA_CR_ECX field. */
00376 #define BR_DMA_CR_ECX(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX)))
00377 
00378 /*! @brief Format value for bitfield DMA_CR_ECX. */
00379 #define BF_DMA_CR_ECX(v)     ((uint32_t)((uint32_t)(v) << BP_DMA_CR_ECX) & BM_DMA_CR_ECX)
00380 
00381 /*! @brief Set the ECX field to a new value. */
00382 #define BW_DMA_CR_ECX(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX), v))
00383 /*@}*/
00384 
00385 /*!
00386  * @name Register DMA_CR, field CX[17] (RW)
00387  *
00388  * Values:
00389  * - 0 - Normal operation
00390  * - 1 - Cancel the remaining data transfer. Stop the executing channel and
00391  *     force the minor loop to finish. The cancel takes effect after the last write
00392  *     of the current read/write sequence. The CX bit clears itself after the
00393  *     cancel has been honored. This cancel retires the channel normally as if the
00394  *     minor loop was completed.
00395  */
00396 /*@{*/
00397 #define BP_DMA_CR_CX         (17U)         /*!< Bit position for DMA_CR_CX. */
00398 #define BM_DMA_CR_CX         (0x00020000U) /*!< Bit mask for DMA_CR_CX. */
00399 #define BS_DMA_CR_CX         (1U)          /*!< Bit field size in bits for DMA_CR_CX. */
00400 
00401 /*! @brief Read current value of the DMA_CR_CX field. */
00402 #define BR_DMA_CR_CX(x)      (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX)))
00403 
00404 /*! @brief Format value for bitfield DMA_CR_CX. */
00405 #define BF_DMA_CR_CX(v)      ((uint32_t)((uint32_t)(v) << BP_DMA_CR_CX) & BM_DMA_CR_CX)
00406 
00407 /*! @brief Set the CX field to a new value. */
00408 #define BW_DMA_CR_CX(x, v)   (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX), v))
00409 /*@}*/
00410 
00411 /*******************************************************************************
00412  * HW_DMA_ES - Error Status Register
00413  ******************************************************************************/
00414 
00415 /*!
00416  * @brief HW_DMA_ES - Error Status Register (RO)
00417  *
00418  * Reset value: 0x00000000U
00419  *
00420  * The ES provides information concerning the last recorded channel error.
00421  * Channel errors can be caused by: A configuration error, that is: An illegal setting
00422  * in the transfer-control descriptor, or An illegal priority register setting
00423  * in fixed-arbitration An error termination to a bus master read or write cycle
00424  * See the Error Reporting and Handling section for more details.
00425  */
00426 typedef union _hw_dma_es
00427 {
00428     uint32_t U;
00429     struct _hw_dma_es_bitfields
00430     {
00431         uint32_t DBE : 1;              /*!< [0] Destination Bus Error */
00432         uint32_t SBE : 1;              /*!< [1] Source Bus Error */
00433         uint32_t SGE : 1;              /*!< [2] Scatter/Gather Configuration Error */
00434         uint32_t NCE : 1;              /*!< [3] NBYTES/CITER Configuration Error */
00435         uint32_t DOE : 1;              /*!< [4] Destination Offset Error */
00436         uint32_t DAE : 1;              /*!< [5] Destination Address Error */
00437         uint32_t SOE : 1;              /*!< [6] Source Offset Error */
00438         uint32_t SAE : 1;              /*!< [7] Source Address Error */
00439         uint32_t ERRCHN : 4;           /*!< [11:8] Error Channel Number or Canceled
00440                                         * Channel Number */
00441         uint32_t RESERVED0 : 2;        /*!< [13:12]  */
00442         uint32_t CPE : 1;              /*!< [14] Channel Priority Error */
00443         uint32_t RESERVED1 : 1;        /*!< [15]  */
00444         uint32_t ECX : 1;              /*!< [16] Transfer Canceled */
00445         uint32_t RESERVED2 : 14;       /*!< [30:17]  */
00446         uint32_t VLD : 1;              /*!< [31]  */
00447     } B;
00448 } hw_dma_es_t;
00449 
00450 /*!
00451  * @name Constants and macros for entire DMA_ES register
00452  */
00453 /*@{*/
00454 #define HW_DMA_ES_ADDR(x)        ((x) + 0x4U)
00455 
00456 #define HW_DMA_ES(x)             (*(__I hw_dma_es_t *) HW_DMA_ES_ADDR(x))
00457 #define HW_DMA_ES_RD(x)          (ADDRESS_READ(hw_dma_es_t, HW_DMA_ES_ADDR(x)))
00458 /*@}*/
00459 
00460 /*
00461  * Constants & macros for individual DMA_ES bitfields
00462  */
00463 
00464 /*!
00465  * @name Register DMA_ES, field DBE[0] (RO)
00466  *
00467  * Values:
00468  * - 0 - No destination bus error
00469  * - 1 - The last recorded error was a bus error on a destination write
00470  */
00471 /*@{*/
00472 #define BP_DMA_ES_DBE        (0U)          /*!< Bit position for DMA_ES_DBE. */
00473 #define BM_DMA_ES_DBE        (0x00000001U) /*!< Bit mask for DMA_ES_DBE. */
00474 #define BS_DMA_ES_DBE        (1U)          /*!< Bit field size in bits for DMA_ES_DBE. */
00475 
00476 /*! @brief Read current value of the DMA_ES_DBE field. */
00477 #define BR_DMA_ES_DBE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE)))
00478 /*@}*/
00479 
00480 /*!
00481  * @name Register DMA_ES, field SBE[1] (RO)
00482  *
00483  * Values:
00484  * - 0 - No source bus error
00485  * - 1 - The last recorded error was a bus error on a source read
00486  */
00487 /*@{*/
00488 #define BP_DMA_ES_SBE        (1U)          /*!< Bit position for DMA_ES_SBE. */
00489 #define BM_DMA_ES_SBE        (0x00000002U) /*!< Bit mask for DMA_ES_SBE. */
00490 #define BS_DMA_ES_SBE        (1U)          /*!< Bit field size in bits for DMA_ES_SBE. */
00491 
00492 /*! @brief Read current value of the DMA_ES_SBE field. */
00493 #define BR_DMA_ES_SBE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE)))
00494 /*@}*/
00495 
00496 /*!
00497  * @name Register DMA_ES, field SGE[2] (RO)
00498  *
00499  * Values:
00500  * - 0 - No scatter/gather configuration error
00501  * - 1 - The last recorded error was a configuration error detected in the
00502  *     TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
00503  *     operation after major loop completion if TCDn_CSR[ESG] is enabled.
00504  *     TCDn_DLASTSGA is not on a 32 byte boundary.
00505  */
00506 /*@{*/
00507 #define BP_DMA_ES_SGE        (2U)          /*!< Bit position for DMA_ES_SGE. */
00508 #define BM_DMA_ES_SGE        (0x00000004U) /*!< Bit mask for DMA_ES_SGE. */
00509 #define BS_DMA_ES_SGE        (1U)          /*!< Bit field size in bits for DMA_ES_SGE. */
00510 
00511 /*! @brief Read current value of the DMA_ES_SGE field. */
00512 #define BR_DMA_ES_SGE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE)))
00513 /*@}*/
00514 
00515 /*!
00516  * @name Register DMA_ES, field NCE[3] (RO)
00517  *
00518  * Values:
00519  * - 0 - No NBYTES/CITER configuration error
00520  * - 1 - The last recorded error was a configuration error detected in the
00521  *     TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
00522  *     TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
00523  *     TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
00524  */
00525 /*@{*/
00526 #define BP_DMA_ES_NCE        (3U)          /*!< Bit position for DMA_ES_NCE. */
00527 #define BM_DMA_ES_NCE        (0x00000008U) /*!< Bit mask for DMA_ES_NCE. */
00528 #define BS_DMA_ES_NCE        (1U)          /*!< Bit field size in bits for DMA_ES_NCE. */
00529 
00530 /*! @brief Read current value of the DMA_ES_NCE field. */
00531 #define BR_DMA_ES_NCE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE)))
00532 /*@}*/
00533 
00534 /*!
00535  * @name Register DMA_ES, field DOE[4] (RO)
00536  *
00537  * Values:
00538  * - 0 - No destination offset configuration error
00539  * - 1 - The last recorded error was a configuration error detected in the
00540  *     TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
00541  */
00542 /*@{*/
00543 #define BP_DMA_ES_DOE        (4U)          /*!< Bit position for DMA_ES_DOE. */
00544 #define BM_DMA_ES_DOE        (0x00000010U) /*!< Bit mask for DMA_ES_DOE. */
00545 #define BS_DMA_ES_DOE        (1U)          /*!< Bit field size in bits for DMA_ES_DOE. */
00546 
00547 /*! @brief Read current value of the DMA_ES_DOE field. */
00548 #define BR_DMA_ES_DOE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE)))
00549 /*@}*/
00550 
00551 /*!
00552  * @name Register DMA_ES, field DAE[5] (RO)
00553  *
00554  * Values:
00555  * - 0 - No destination address configuration error
00556  * - 1 - The last recorded error was a configuration error detected in the
00557  *     TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
00558  */
00559 /*@{*/
00560 #define BP_DMA_ES_DAE        (5U)          /*!< Bit position for DMA_ES_DAE. */
00561 #define BM_DMA_ES_DAE        (0x00000020U) /*!< Bit mask for DMA_ES_DAE. */
00562 #define BS_DMA_ES_DAE        (1U)          /*!< Bit field size in bits for DMA_ES_DAE. */
00563 
00564 /*! @brief Read current value of the DMA_ES_DAE field. */
00565 #define BR_DMA_ES_DAE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE)))
00566 /*@}*/
00567 
00568 /*!
00569  * @name Register DMA_ES, field SOE[6] (RO)
00570  *
00571  * Values:
00572  * - 0 - No source offset configuration error
00573  * - 1 - The last recorded error was a configuration error detected in the
00574  *     TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
00575  */
00576 /*@{*/
00577 #define BP_DMA_ES_SOE        (6U)          /*!< Bit position for DMA_ES_SOE. */
00578 #define BM_DMA_ES_SOE        (0x00000040U) /*!< Bit mask for DMA_ES_SOE. */
00579 #define BS_DMA_ES_SOE        (1U)          /*!< Bit field size in bits for DMA_ES_SOE. */
00580 
00581 /*! @brief Read current value of the DMA_ES_SOE field. */
00582 #define BR_DMA_ES_SOE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE)))
00583 /*@}*/
00584 
00585 /*!
00586  * @name Register DMA_ES, field SAE[7] (RO)
00587  *
00588  * Values:
00589  * - 0 - No source address configuration error.
00590  * - 1 - The last recorded error was a configuration error detected in the
00591  *     TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
00592  */
00593 /*@{*/
00594 #define BP_DMA_ES_SAE        (7U)          /*!< Bit position for DMA_ES_SAE. */
00595 #define BM_DMA_ES_SAE        (0x00000080U) /*!< Bit mask for DMA_ES_SAE. */
00596 #define BS_DMA_ES_SAE        (1U)          /*!< Bit field size in bits for DMA_ES_SAE. */
00597 
00598 /*! @brief Read current value of the DMA_ES_SAE field. */
00599 #define BR_DMA_ES_SAE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE)))
00600 /*@}*/
00601 
00602 /*!
00603  * @name Register DMA_ES, field ERRCHN[11:8] (RO)
00604  *
00605  * The channel number of the last recorded error (excluding CPE errors) or last
00606  * recorded error canceled transfer.
00607  */
00608 /*@{*/
00609 #define BP_DMA_ES_ERRCHN     (8U)          /*!< Bit position for DMA_ES_ERRCHN. */
00610 #define BM_DMA_ES_ERRCHN     (0x00000F00U) /*!< Bit mask for DMA_ES_ERRCHN. */
00611 #define BS_DMA_ES_ERRCHN     (4U)          /*!< Bit field size in bits for DMA_ES_ERRCHN. */
00612 
00613 /*! @brief Read current value of the DMA_ES_ERRCHN field. */
00614 #define BR_DMA_ES_ERRCHN(x)  (UNION_READ(hw_dma_es_t, HW_DMA_ES_ADDR(x), U, B.ERRCHN))
00615 /*@}*/
00616 
00617 /*!
00618  * @name Register DMA_ES, field CPE[14] (RO)
00619  *
00620  * Values:
00621  * - 0 - No channel priority error
00622  * - 1 - The last recorded error was a configuration error in the channel
00623  *     priorities . Channel priorities are not unique.
00624  */
00625 /*@{*/
00626 #define BP_DMA_ES_CPE        (14U)         /*!< Bit position for DMA_ES_CPE. */
00627 #define BM_DMA_ES_CPE        (0x00004000U) /*!< Bit mask for DMA_ES_CPE. */
00628 #define BS_DMA_ES_CPE        (1U)          /*!< Bit field size in bits for DMA_ES_CPE. */
00629 
00630 /*! @brief Read current value of the DMA_ES_CPE field. */
00631 #define BR_DMA_ES_CPE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE)))
00632 /*@}*/
00633 
00634 /*!
00635  * @name Register DMA_ES, field ECX[16] (RO)
00636  *
00637  * Values:
00638  * - 0 - No canceled transfers
00639  * - 1 - The last recorded entry was a canceled transfer by the error cancel
00640  *     transfer input
00641  */
00642 /*@{*/
00643 #define BP_DMA_ES_ECX        (16U)         /*!< Bit position for DMA_ES_ECX. */
00644 #define BM_DMA_ES_ECX        (0x00010000U) /*!< Bit mask for DMA_ES_ECX. */
00645 #define BS_DMA_ES_ECX        (1U)          /*!< Bit field size in bits for DMA_ES_ECX. */
00646 
00647 /*! @brief Read current value of the DMA_ES_ECX field. */
00648 #define BR_DMA_ES_ECX(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX)))
00649 /*@}*/
00650 
00651 /*!
00652  * @name Register DMA_ES, field VLD[31] (RO)
00653  *
00654  * Logical OR of all ERR status bits
00655  *
00656  * Values:
00657  * - 0 - No ERR bits are set
00658  * - 1 - At least one ERR bit is set indicating a valid error exists that has
00659  *     not been cleared
00660  */
00661 /*@{*/
00662 #define BP_DMA_ES_VLD        (31U)         /*!< Bit position for DMA_ES_VLD. */
00663 #define BM_DMA_ES_VLD        (0x80000000U) /*!< Bit mask for DMA_ES_VLD. */
00664 #define BS_DMA_ES_VLD        (1U)          /*!< Bit field size in bits for DMA_ES_VLD. */
00665 
00666 /*! @brief Read current value of the DMA_ES_VLD field. */
00667 #define BR_DMA_ES_VLD(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD)))
00668 /*@}*/
00669 
00670 /*******************************************************************************
00671  * HW_DMA_ERQ - Enable Request Register
00672  ******************************************************************************/
00673 
00674 /*!
00675  * @brief HW_DMA_ERQ - Enable Request Register (RW)
00676  *
00677  * Reset value: 0x00000000U
00678  *
00679  * The ERQ register provides a bit map for the 16 implemented channels to enable
00680  * the request signal for each channel. The state of any given channel enable is
00681  * directly affected by writes to this register; it is also affected by writes
00682  * to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
00683  * for a single channel can easily be modified without needing to perform a
00684  * read-modify-write sequence to the ERQ. DMA request input signals and this enable
00685  * request flag must be asserted before a channel's hardware service request is
00686  * accepted. The state of the DMA enable request flag does not affect a channel
00687  * service request made explicitly through software or a linked channel request.
00688  */
00689 typedef union _hw_dma_erq
00690 {
00691     uint32_t U;
00692     struct _hw_dma_erq_bitfields
00693     {
00694         uint32_t ERQ0 : 1;             /*!< [0] Enable DMA Request 0 */
00695         uint32_t ERQ1 : 1;             /*!< [1] Enable DMA Request 1 */
00696         uint32_t ERQ2 : 1;             /*!< [2] Enable DMA Request 2 */
00697         uint32_t ERQ3 : 1;             /*!< [3] Enable DMA Request 3 */
00698         uint32_t ERQ4 : 1;             /*!< [4] Enable DMA Request 4 */
00699         uint32_t ERQ5 : 1;             /*!< [5] Enable DMA Request 5 */
00700         uint32_t ERQ6 : 1;             /*!< [6] Enable DMA Request 6 */
00701         uint32_t ERQ7 : 1;             /*!< [7] Enable DMA Request 7 */
00702         uint32_t ERQ8 : 1;             /*!< [8] Enable DMA Request 8 */
00703         uint32_t ERQ9 : 1;             /*!< [9] Enable DMA Request 9 */
00704         uint32_t ERQ10 : 1;            /*!< [10] Enable DMA Request 10 */
00705         uint32_t ERQ11 : 1;            /*!< [11] Enable DMA Request 11 */
00706         uint32_t ERQ12 : 1;            /*!< [12] Enable DMA Request 12 */
00707         uint32_t ERQ13 : 1;            /*!< [13] Enable DMA Request 13 */
00708         uint32_t ERQ14 : 1;            /*!< [14] Enable DMA Request 14 */
00709         uint32_t ERQ15 : 1;            /*!< [15] Enable DMA Request 15 */
00710         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00711     } B;
00712 } hw_dma_erq_t;
00713 
00714 /*!
00715  * @name Constants and macros for entire DMA_ERQ register
00716  */
00717 /*@{*/
00718 #define HW_DMA_ERQ_ADDR(x)       ((x) + 0xCU)
00719 
00720 #define HW_DMA_ERQ(x)            (*(__IO hw_dma_erq_t *) HW_DMA_ERQ_ADDR(x))
00721 #define HW_DMA_ERQ_RD(x)         (ADDRESS_READ(hw_dma_erq_t, HW_DMA_ERQ_ADDR(x)))
00722 #define HW_DMA_ERQ_WR(x, v)      (ADDRESS_WRITE(hw_dma_erq_t, HW_DMA_ERQ_ADDR(x), v))
00723 #define HW_DMA_ERQ_SET(x, v)     (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) |  (v)))
00724 #define HW_DMA_ERQ_CLR(x, v)     (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
00725 #define HW_DMA_ERQ_TOG(x, v)     (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^  (v)))
00726 /*@}*/
00727 
00728 /*
00729  * Constants & macros for individual DMA_ERQ bitfields
00730  */
00731 
00732 /*!
00733  * @name Register DMA_ERQ, field ERQ0[0] (RW)
00734  *
00735  * Values:
00736  * - 0 - The DMA request signal for the corresponding channel is disabled
00737  * - 1 - The DMA request signal for the corresponding channel is enabled
00738  */
00739 /*@{*/
00740 #define BP_DMA_ERQ_ERQ0      (0U)          /*!< Bit position for DMA_ERQ_ERQ0. */
00741 #define BM_DMA_ERQ_ERQ0      (0x00000001U) /*!< Bit mask for DMA_ERQ_ERQ0. */
00742 #define BS_DMA_ERQ_ERQ0      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ0. */
00743 
00744 /*! @brief Read current value of the DMA_ERQ_ERQ0 field. */
00745 #define BR_DMA_ERQ_ERQ0(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0)))
00746 
00747 /*! @brief Format value for bitfield DMA_ERQ_ERQ0. */
00748 #define BF_DMA_ERQ_ERQ0(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ0) & BM_DMA_ERQ_ERQ0)
00749 
00750 /*! @brief Set the ERQ0 field to a new value. */
00751 #define BW_DMA_ERQ_ERQ0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0), v))
00752 /*@}*/
00753 
00754 /*!
00755  * @name Register DMA_ERQ, field ERQ1[1] (RW)
00756  *
00757  * Values:
00758  * - 0 - The DMA request signal for the corresponding channel is disabled
00759  * - 1 - The DMA request signal for the corresponding channel is enabled
00760  */
00761 /*@{*/
00762 #define BP_DMA_ERQ_ERQ1      (1U)          /*!< Bit position for DMA_ERQ_ERQ1. */
00763 #define BM_DMA_ERQ_ERQ1      (0x00000002U) /*!< Bit mask for DMA_ERQ_ERQ1. */
00764 #define BS_DMA_ERQ_ERQ1      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ1. */
00765 
00766 /*! @brief Read current value of the DMA_ERQ_ERQ1 field. */
00767 #define BR_DMA_ERQ_ERQ1(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1)))
00768 
00769 /*! @brief Format value for bitfield DMA_ERQ_ERQ1. */
00770 #define BF_DMA_ERQ_ERQ1(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ1) & BM_DMA_ERQ_ERQ1)
00771 
00772 /*! @brief Set the ERQ1 field to a new value. */
00773 #define BW_DMA_ERQ_ERQ1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1), v))
00774 /*@}*/
00775 
00776 /*!
00777  * @name Register DMA_ERQ, field ERQ2[2] (RW)
00778  *
00779  * Values:
00780  * - 0 - The DMA request signal for the corresponding channel is disabled
00781  * - 1 - The DMA request signal for the corresponding channel is enabled
00782  */
00783 /*@{*/
00784 #define BP_DMA_ERQ_ERQ2      (2U)          /*!< Bit position for DMA_ERQ_ERQ2. */
00785 #define BM_DMA_ERQ_ERQ2      (0x00000004U) /*!< Bit mask for DMA_ERQ_ERQ2. */
00786 #define BS_DMA_ERQ_ERQ2      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ2. */
00787 
00788 /*! @brief Read current value of the DMA_ERQ_ERQ2 field. */
00789 #define BR_DMA_ERQ_ERQ2(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2)))
00790 
00791 /*! @brief Format value for bitfield DMA_ERQ_ERQ2. */
00792 #define BF_DMA_ERQ_ERQ2(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ2) & BM_DMA_ERQ_ERQ2)
00793 
00794 /*! @brief Set the ERQ2 field to a new value. */
00795 #define BW_DMA_ERQ_ERQ2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2), v))
00796 /*@}*/
00797 
00798 /*!
00799  * @name Register DMA_ERQ, field ERQ3[3] (RW)
00800  *
00801  * Values:
00802  * - 0 - The DMA request signal for the corresponding channel is disabled
00803  * - 1 - The DMA request signal for the corresponding channel is enabled
00804  */
00805 /*@{*/
00806 #define BP_DMA_ERQ_ERQ3      (3U)          /*!< Bit position for DMA_ERQ_ERQ3. */
00807 #define BM_DMA_ERQ_ERQ3      (0x00000008U) /*!< Bit mask for DMA_ERQ_ERQ3. */
00808 #define BS_DMA_ERQ_ERQ3      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ3. */
00809 
00810 /*! @brief Read current value of the DMA_ERQ_ERQ3 field. */
00811 #define BR_DMA_ERQ_ERQ3(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3)))
00812 
00813 /*! @brief Format value for bitfield DMA_ERQ_ERQ3. */
00814 #define BF_DMA_ERQ_ERQ3(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ3) & BM_DMA_ERQ_ERQ3)
00815 
00816 /*! @brief Set the ERQ3 field to a new value. */
00817 #define BW_DMA_ERQ_ERQ3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3), v))
00818 /*@}*/
00819 
00820 /*!
00821  * @name Register DMA_ERQ, field ERQ4[4] (RW)
00822  *
00823  * Values:
00824  * - 0 - The DMA request signal for the corresponding channel is disabled
00825  * - 1 - The DMA request signal for the corresponding channel is enabled
00826  */
00827 /*@{*/
00828 #define BP_DMA_ERQ_ERQ4      (4U)          /*!< Bit position for DMA_ERQ_ERQ4. */
00829 #define BM_DMA_ERQ_ERQ4      (0x00000010U) /*!< Bit mask for DMA_ERQ_ERQ4. */
00830 #define BS_DMA_ERQ_ERQ4      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ4. */
00831 
00832 /*! @brief Read current value of the DMA_ERQ_ERQ4 field. */
00833 #define BR_DMA_ERQ_ERQ4(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4)))
00834 
00835 /*! @brief Format value for bitfield DMA_ERQ_ERQ4. */
00836 #define BF_DMA_ERQ_ERQ4(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ4) & BM_DMA_ERQ_ERQ4)
00837 
00838 /*! @brief Set the ERQ4 field to a new value. */
00839 #define BW_DMA_ERQ_ERQ4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4), v))
00840 /*@}*/
00841 
00842 /*!
00843  * @name Register DMA_ERQ, field ERQ5[5] (RW)
00844  *
00845  * Values:
00846  * - 0 - The DMA request signal for the corresponding channel is disabled
00847  * - 1 - The DMA request signal for the corresponding channel is enabled
00848  */
00849 /*@{*/
00850 #define BP_DMA_ERQ_ERQ5      (5U)          /*!< Bit position for DMA_ERQ_ERQ5. */
00851 #define BM_DMA_ERQ_ERQ5      (0x00000020U) /*!< Bit mask for DMA_ERQ_ERQ5. */
00852 #define BS_DMA_ERQ_ERQ5      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ5. */
00853 
00854 /*! @brief Read current value of the DMA_ERQ_ERQ5 field. */
00855 #define BR_DMA_ERQ_ERQ5(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5)))
00856 
00857 /*! @brief Format value for bitfield DMA_ERQ_ERQ5. */
00858 #define BF_DMA_ERQ_ERQ5(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ5) & BM_DMA_ERQ_ERQ5)
00859 
00860 /*! @brief Set the ERQ5 field to a new value. */
00861 #define BW_DMA_ERQ_ERQ5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5), v))
00862 /*@}*/
00863 
00864 /*!
00865  * @name Register DMA_ERQ, field ERQ6[6] (RW)
00866  *
00867  * Values:
00868  * - 0 - The DMA request signal for the corresponding channel is disabled
00869  * - 1 - The DMA request signal for the corresponding channel is enabled
00870  */
00871 /*@{*/
00872 #define BP_DMA_ERQ_ERQ6      (6U)          /*!< Bit position for DMA_ERQ_ERQ6. */
00873 #define BM_DMA_ERQ_ERQ6      (0x00000040U) /*!< Bit mask for DMA_ERQ_ERQ6. */
00874 #define BS_DMA_ERQ_ERQ6      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ6. */
00875 
00876 /*! @brief Read current value of the DMA_ERQ_ERQ6 field. */
00877 #define BR_DMA_ERQ_ERQ6(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6)))
00878 
00879 /*! @brief Format value for bitfield DMA_ERQ_ERQ6. */
00880 #define BF_DMA_ERQ_ERQ6(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ6) & BM_DMA_ERQ_ERQ6)
00881 
00882 /*! @brief Set the ERQ6 field to a new value. */
00883 #define BW_DMA_ERQ_ERQ6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6), v))
00884 /*@}*/
00885 
00886 /*!
00887  * @name Register DMA_ERQ, field ERQ7[7] (RW)
00888  *
00889  * Values:
00890  * - 0 - The DMA request signal for the corresponding channel is disabled
00891  * - 1 - The DMA request signal for the corresponding channel is enabled
00892  */
00893 /*@{*/
00894 #define BP_DMA_ERQ_ERQ7      (7U)          /*!< Bit position for DMA_ERQ_ERQ7. */
00895 #define BM_DMA_ERQ_ERQ7      (0x00000080U) /*!< Bit mask for DMA_ERQ_ERQ7. */
00896 #define BS_DMA_ERQ_ERQ7      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ7. */
00897 
00898 /*! @brief Read current value of the DMA_ERQ_ERQ7 field. */
00899 #define BR_DMA_ERQ_ERQ7(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7)))
00900 
00901 /*! @brief Format value for bitfield DMA_ERQ_ERQ7. */
00902 #define BF_DMA_ERQ_ERQ7(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ7) & BM_DMA_ERQ_ERQ7)
00903 
00904 /*! @brief Set the ERQ7 field to a new value. */
00905 #define BW_DMA_ERQ_ERQ7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7), v))
00906 /*@}*/
00907 
00908 /*!
00909  * @name Register DMA_ERQ, field ERQ8[8] (RW)
00910  *
00911  * Values:
00912  * - 0 - The DMA request signal for the corresponding channel is disabled
00913  * - 1 - The DMA request signal for the corresponding channel is enabled
00914  */
00915 /*@{*/
00916 #define BP_DMA_ERQ_ERQ8      (8U)          /*!< Bit position for DMA_ERQ_ERQ8. */
00917 #define BM_DMA_ERQ_ERQ8      (0x00000100U) /*!< Bit mask for DMA_ERQ_ERQ8. */
00918 #define BS_DMA_ERQ_ERQ8      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ8. */
00919 
00920 /*! @brief Read current value of the DMA_ERQ_ERQ8 field. */
00921 #define BR_DMA_ERQ_ERQ8(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8)))
00922 
00923 /*! @brief Format value for bitfield DMA_ERQ_ERQ8. */
00924 #define BF_DMA_ERQ_ERQ8(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ8) & BM_DMA_ERQ_ERQ8)
00925 
00926 /*! @brief Set the ERQ8 field to a new value. */
00927 #define BW_DMA_ERQ_ERQ8(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8), v))
00928 /*@}*/
00929 
00930 /*!
00931  * @name Register DMA_ERQ, field ERQ9[9] (RW)
00932  *
00933  * Values:
00934  * - 0 - The DMA request signal for the corresponding channel is disabled
00935  * - 1 - The DMA request signal for the corresponding channel is enabled
00936  */
00937 /*@{*/
00938 #define BP_DMA_ERQ_ERQ9      (9U)          /*!< Bit position for DMA_ERQ_ERQ9. */
00939 #define BM_DMA_ERQ_ERQ9      (0x00000200U) /*!< Bit mask for DMA_ERQ_ERQ9. */
00940 #define BS_DMA_ERQ_ERQ9      (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ9. */
00941 
00942 /*! @brief Read current value of the DMA_ERQ_ERQ9 field. */
00943 #define BR_DMA_ERQ_ERQ9(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9)))
00944 
00945 /*! @brief Format value for bitfield DMA_ERQ_ERQ9. */
00946 #define BF_DMA_ERQ_ERQ9(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ9) & BM_DMA_ERQ_ERQ9)
00947 
00948 /*! @brief Set the ERQ9 field to a new value. */
00949 #define BW_DMA_ERQ_ERQ9(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9), v))
00950 /*@}*/
00951 
00952 /*!
00953  * @name Register DMA_ERQ, field ERQ10[10] (RW)
00954  *
00955  * Values:
00956  * - 0 - The DMA request signal for the corresponding channel is disabled
00957  * - 1 - The DMA request signal for the corresponding channel is enabled
00958  */
00959 /*@{*/
00960 #define BP_DMA_ERQ_ERQ10     (10U)         /*!< Bit position for DMA_ERQ_ERQ10. */
00961 #define BM_DMA_ERQ_ERQ10     (0x00000400U) /*!< Bit mask for DMA_ERQ_ERQ10. */
00962 #define BS_DMA_ERQ_ERQ10     (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ10. */
00963 
00964 /*! @brief Read current value of the DMA_ERQ_ERQ10 field. */
00965 #define BR_DMA_ERQ_ERQ10(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10)))
00966 
00967 /*! @brief Format value for bitfield DMA_ERQ_ERQ10. */
00968 #define BF_DMA_ERQ_ERQ10(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ10) & BM_DMA_ERQ_ERQ10)
00969 
00970 /*! @brief Set the ERQ10 field to a new value. */
00971 #define BW_DMA_ERQ_ERQ10(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10), v))
00972 /*@}*/
00973 
00974 /*!
00975  * @name Register DMA_ERQ, field ERQ11[11] (RW)
00976  *
00977  * Values:
00978  * - 0 - The DMA request signal for the corresponding channel is disabled
00979  * - 1 - The DMA request signal for the corresponding channel is enabled
00980  */
00981 /*@{*/
00982 #define BP_DMA_ERQ_ERQ11     (11U)         /*!< Bit position for DMA_ERQ_ERQ11. */
00983 #define BM_DMA_ERQ_ERQ11     (0x00000800U) /*!< Bit mask for DMA_ERQ_ERQ11. */
00984 #define BS_DMA_ERQ_ERQ11     (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ11. */
00985 
00986 /*! @brief Read current value of the DMA_ERQ_ERQ11 field. */
00987 #define BR_DMA_ERQ_ERQ11(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11)))
00988 
00989 /*! @brief Format value for bitfield DMA_ERQ_ERQ11. */
00990 #define BF_DMA_ERQ_ERQ11(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ11) & BM_DMA_ERQ_ERQ11)
00991 
00992 /*! @brief Set the ERQ11 field to a new value. */
00993 #define BW_DMA_ERQ_ERQ11(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11), v))
00994 /*@}*/
00995 
00996 /*!
00997  * @name Register DMA_ERQ, field ERQ12[12] (RW)
00998  *
00999  * Values:
01000  * - 0 - The DMA request signal for the corresponding channel is disabled
01001  * - 1 - The DMA request signal for the corresponding channel is enabled
01002  */
01003 /*@{*/
01004 #define BP_DMA_ERQ_ERQ12     (12U)         /*!< Bit position for DMA_ERQ_ERQ12. */
01005 #define BM_DMA_ERQ_ERQ12     (0x00001000U) /*!< Bit mask for DMA_ERQ_ERQ12. */
01006 #define BS_DMA_ERQ_ERQ12     (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ12. */
01007 
01008 /*! @brief Read current value of the DMA_ERQ_ERQ12 field. */
01009 #define BR_DMA_ERQ_ERQ12(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12)))
01010 
01011 /*! @brief Format value for bitfield DMA_ERQ_ERQ12. */
01012 #define BF_DMA_ERQ_ERQ12(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ12) & BM_DMA_ERQ_ERQ12)
01013 
01014 /*! @brief Set the ERQ12 field to a new value. */
01015 #define BW_DMA_ERQ_ERQ12(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12), v))
01016 /*@}*/
01017 
01018 /*!
01019  * @name Register DMA_ERQ, field ERQ13[13] (RW)
01020  *
01021  * Values:
01022  * - 0 - The DMA request signal for the corresponding channel is disabled
01023  * - 1 - The DMA request signal for the corresponding channel is enabled
01024  */
01025 /*@{*/
01026 #define BP_DMA_ERQ_ERQ13     (13U)         /*!< Bit position for DMA_ERQ_ERQ13. */
01027 #define BM_DMA_ERQ_ERQ13     (0x00002000U) /*!< Bit mask for DMA_ERQ_ERQ13. */
01028 #define BS_DMA_ERQ_ERQ13     (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ13. */
01029 
01030 /*! @brief Read current value of the DMA_ERQ_ERQ13 field. */
01031 #define BR_DMA_ERQ_ERQ13(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13)))
01032 
01033 /*! @brief Format value for bitfield DMA_ERQ_ERQ13. */
01034 #define BF_DMA_ERQ_ERQ13(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ13) & BM_DMA_ERQ_ERQ13)
01035 
01036 /*! @brief Set the ERQ13 field to a new value. */
01037 #define BW_DMA_ERQ_ERQ13(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13), v))
01038 /*@}*/
01039 
01040 /*!
01041  * @name Register DMA_ERQ, field ERQ14[14] (RW)
01042  *
01043  * Values:
01044  * - 0 - The DMA request signal for the corresponding channel is disabled
01045  * - 1 - The DMA request signal for the corresponding channel is enabled
01046  */
01047 /*@{*/
01048 #define BP_DMA_ERQ_ERQ14     (14U)         /*!< Bit position for DMA_ERQ_ERQ14. */
01049 #define BM_DMA_ERQ_ERQ14     (0x00004000U) /*!< Bit mask for DMA_ERQ_ERQ14. */
01050 #define BS_DMA_ERQ_ERQ14     (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ14. */
01051 
01052 /*! @brief Read current value of the DMA_ERQ_ERQ14 field. */
01053 #define BR_DMA_ERQ_ERQ14(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14)))
01054 
01055 /*! @brief Format value for bitfield DMA_ERQ_ERQ14. */
01056 #define BF_DMA_ERQ_ERQ14(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ14) & BM_DMA_ERQ_ERQ14)
01057 
01058 /*! @brief Set the ERQ14 field to a new value. */
01059 #define BW_DMA_ERQ_ERQ14(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14), v))
01060 /*@}*/
01061 
01062 /*!
01063  * @name Register DMA_ERQ, field ERQ15[15] (RW)
01064  *
01065  * Values:
01066  * - 0 - The DMA request signal for the corresponding channel is disabled
01067  * - 1 - The DMA request signal for the corresponding channel is enabled
01068  */
01069 /*@{*/
01070 #define BP_DMA_ERQ_ERQ15     (15U)         /*!< Bit position for DMA_ERQ_ERQ15. */
01071 #define BM_DMA_ERQ_ERQ15     (0x00008000U) /*!< Bit mask for DMA_ERQ_ERQ15. */
01072 #define BS_DMA_ERQ_ERQ15     (1U)          /*!< Bit field size in bits for DMA_ERQ_ERQ15. */
01073 
01074 /*! @brief Read current value of the DMA_ERQ_ERQ15 field. */
01075 #define BR_DMA_ERQ_ERQ15(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15)))
01076 
01077 /*! @brief Format value for bitfield DMA_ERQ_ERQ15. */
01078 #define BF_DMA_ERQ_ERQ15(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERQ_ERQ15) & BM_DMA_ERQ_ERQ15)
01079 
01080 /*! @brief Set the ERQ15 field to a new value. */
01081 #define BW_DMA_ERQ_ERQ15(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15), v))
01082 /*@}*/
01083 
01084 /*******************************************************************************
01085  * HW_DMA_EEI - Enable Error Interrupt Register
01086  ******************************************************************************/
01087 
01088 /*!
01089  * @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
01090  *
01091  * Reset value: 0x00000000U
01092  *
01093  * The EEI register provides a bit map for the 16 channels to enable the error
01094  * interrupt signal for each channel. The state of any given channel's error
01095  * interrupt enable is directly affected by writes to this register; it is also
01096  * affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
01097  * interrupt enable for a single channel can easily be modified without the need to
01098  * perform a read-modify-write sequence to the EEI register. The DMA error
01099  * indicator and the error interrupt enable flag must be asserted before an error
01100  * interrupt request for a given channel is asserted to the interrupt controller.
01101  */
01102 typedef union _hw_dma_eei
01103 {
01104     uint32_t U;
01105     struct _hw_dma_eei_bitfields
01106     {
01107         uint32_t EEI0 : 1;             /*!< [0] Enable Error Interrupt 0 */
01108         uint32_t EEI1 : 1;             /*!< [1] Enable Error Interrupt 1 */
01109         uint32_t EEI2 : 1;             /*!< [2] Enable Error Interrupt 2 */
01110         uint32_t EEI3 : 1;             /*!< [3] Enable Error Interrupt 3 */
01111         uint32_t EEI4 : 1;             /*!< [4] Enable Error Interrupt 4 */
01112         uint32_t EEI5 : 1;             /*!< [5] Enable Error Interrupt 5 */
01113         uint32_t EEI6 : 1;             /*!< [6] Enable Error Interrupt 6 */
01114         uint32_t EEI7 : 1;             /*!< [7] Enable Error Interrupt 7 */
01115         uint32_t EEI8 : 1;             /*!< [8] Enable Error Interrupt 8 */
01116         uint32_t EEI9 : 1;             /*!< [9] Enable Error Interrupt 9 */
01117         uint32_t EEI10 : 1;            /*!< [10] Enable Error Interrupt 10 */
01118         uint32_t EEI11 : 1;            /*!< [11] Enable Error Interrupt 11 */
01119         uint32_t EEI12 : 1;            /*!< [12] Enable Error Interrupt 12 */
01120         uint32_t EEI13 : 1;            /*!< [13] Enable Error Interrupt 13 */
01121         uint32_t EEI14 : 1;            /*!< [14] Enable Error Interrupt 14 */
01122         uint32_t EEI15 : 1;            /*!< [15] Enable Error Interrupt 15 */
01123         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01124     } B;
01125 } hw_dma_eei_t;
01126 
01127 /*!
01128  * @name Constants and macros for entire DMA_EEI register
01129  */
01130 /*@{*/
01131 #define HW_DMA_EEI_ADDR(x)       ((x) + 0x14U)
01132 
01133 #define HW_DMA_EEI(x)            (*(__IO hw_dma_eei_t *) HW_DMA_EEI_ADDR(x))
01134 #define HW_DMA_EEI_RD(x)         (ADDRESS_READ(hw_dma_eei_t, HW_DMA_EEI_ADDR(x)))
01135 #define HW_DMA_EEI_WR(x, v)      (ADDRESS_WRITE(hw_dma_eei_t, HW_DMA_EEI_ADDR(x), v))
01136 #define HW_DMA_EEI_SET(x, v)     (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) |  (v)))
01137 #define HW_DMA_EEI_CLR(x, v)     (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
01138 #define HW_DMA_EEI_TOG(x, v)     (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^  (v)))
01139 /*@}*/
01140 
01141 /*
01142  * Constants & macros for individual DMA_EEI bitfields
01143  */
01144 
01145 /*!
01146  * @name Register DMA_EEI, field EEI0[0] (RW)
01147  *
01148  * Values:
01149  * - 0 - The error signal for corresponding channel does not generate an error
01150  *     interrupt
01151  * - 1 - The assertion of the error signal for corresponding channel generates
01152  *     an error interrupt request
01153  */
01154 /*@{*/
01155 #define BP_DMA_EEI_EEI0      (0U)          /*!< Bit position for DMA_EEI_EEI0. */
01156 #define BM_DMA_EEI_EEI0      (0x00000001U) /*!< Bit mask for DMA_EEI_EEI0. */
01157 #define BS_DMA_EEI_EEI0      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI0. */
01158 
01159 /*! @brief Read current value of the DMA_EEI_EEI0 field. */
01160 #define BR_DMA_EEI_EEI0(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0)))
01161 
01162 /*! @brief Format value for bitfield DMA_EEI_EEI0. */
01163 #define BF_DMA_EEI_EEI0(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI0) & BM_DMA_EEI_EEI0)
01164 
01165 /*! @brief Set the EEI0 field to a new value. */
01166 #define BW_DMA_EEI_EEI0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0), v))
01167 /*@}*/
01168 
01169 /*!
01170  * @name Register DMA_EEI, field EEI1[1] (RW)
01171  *
01172  * Values:
01173  * - 0 - The error signal for corresponding channel does not generate an error
01174  *     interrupt
01175  * - 1 - The assertion of the error signal for corresponding channel generates
01176  *     an error interrupt request
01177  */
01178 /*@{*/
01179 #define BP_DMA_EEI_EEI1      (1U)          /*!< Bit position for DMA_EEI_EEI1. */
01180 #define BM_DMA_EEI_EEI1      (0x00000002U) /*!< Bit mask for DMA_EEI_EEI1. */
01181 #define BS_DMA_EEI_EEI1      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI1. */
01182 
01183 /*! @brief Read current value of the DMA_EEI_EEI1 field. */
01184 #define BR_DMA_EEI_EEI1(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1)))
01185 
01186 /*! @brief Format value for bitfield DMA_EEI_EEI1. */
01187 #define BF_DMA_EEI_EEI1(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI1) & BM_DMA_EEI_EEI1)
01188 
01189 /*! @brief Set the EEI1 field to a new value. */
01190 #define BW_DMA_EEI_EEI1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1), v))
01191 /*@}*/
01192 
01193 /*!
01194  * @name Register DMA_EEI, field EEI2[2] (RW)
01195  *
01196  * Values:
01197  * - 0 - The error signal for corresponding channel does not generate an error
01198  *     interrupt
01199  * - 1 - The assertion of the error signal for corresponding channel generates
01200  *     an error interrupt request
01201  */
01202 /*@{*/
01203 #define BP_DMA_EEI_EEI2      (2U)          /*!< Bit position for DMA_EEI_EEI2. */
01204 #define BM_DMA_EEI_EEI2      (0x00000004U) /*!< Bit mask for DMA_EEI_EEI2. */
01205 #define BS_DMA_EEI_EEI2      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI2. */
01206 
01207 /*! @brief Read current value of the DMA_EEI_EEI2 field. */
01208 #define BR_DMA_EEI_EEI2(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2)))
01209 
01210 /*! @brief Format value for bitfield DMA_EEI_EEI2. */
01211 #define BF_DMA_EEI_EEI2(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI2) & BM_DMA_EEI_EEI2)
01212 
01213 /*! @brief Set the EEI2 field to a new value. */
01214 #define BW_DMA_EEI_EEI2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2), v))
01215 /*@}*/
01216 
01217 /*!
01218  * @name Register DMA_EEI, field EEI3[3] (RW)
01219  *
01220  * Values:
01221  * - 0 - The error signal for corresponding channel does not generate an error
01222  *     interrupt
01223  * - 1 - The assertion of the error signal for corresponding channel generates
01224  *     an error interrupt request
01225  */
01226 /*@{*/
01227 #define BP_DMA_EEI_EEI3      (3U)          /*!< Bit position for DMA_EEI_EEI3. */
01228 #define BM_DMA_EEI_EEI3      (0x00000008U) /*!< Bit mask for DMA_EEI_EEI3. */
01229 #define BS_DMA_EEI_EEI3      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI3. */
01230 
01231 /*! @brief Read current value of the DMA_EEI_EEI3 field. */
01232 #define BR_DMA_EEI_EEI3(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3)))
01233 
01234 /*! @brief Format value for bitfield DMA_EEI_EEI3. */
01235 #define BF_DMA_EEI_EEI3(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI3) & BM_DMA_EEI_EEI3)
01236 
01237 /*! @brief Set the EEI3 field to a new value. */
01238 #define BW_DMA_EEI_EEI3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3), v))
01239 /*@}*/
01240 
01241 /*!
01242  * @name Register DMA_EEI, field EEI4[4] (RW)
01243  *
01244  * Values:
01245  * - 0 - The error signal for corresponding channel does not generate an error
01246  *     interrupt
01247  * - 1 - The assertion of the error signal for corresponding channel generates
01248  *     an error interrupt request
01249  */
01250 /*@{*/
01251 #define BP_DMA_EEI_EEI4      (4U)          /*!< Bit position for DMA_EEI_EEI4. */
01252 #define BM_DMA_EEI_EEI4      (0x00000010U) /*!< Bit mask for DMA_EEI_EEI4. */
01253 #define BS_DMA_EEI_EEI4      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI4. */
01254 
01255 /*! @brief Read current value of the DMA_EEI_EEI4 field. */
01256 #define BR_DMA_EEI_EEI4(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4)))
01257 
01258 /*! @brief Format value for bitfield DMA_EEI_EEI4. */
01259 #define BF_DMA_EEI_EEI4(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI4) & BM_DMA_EEI_EEI4)
01260 
01261 /*! @brief Set the EEI4 field to a new value. */
01262 #define BW_DMA_EEI_EEI4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4), v))
01263 /*@}*/
01264 
01265 /*!
01266  * @name Register DMA_EEI, field EEI5[5] (RW)
01267  *
01268  * Values:
01269  * - 0 - The error signal for corresponding channel does not generate an error
01270  *     interrupt
01271  * - 1 - The assertion of the error signal for corresponding channel generates
01272  *     an error interrupt request
01273  */
01274 /*@{*/
01275 #define BP_DMA_EEI_EEI5      (5U)          /*!< Bit position for DMA_EEI_EEI5. */
01276 #define BM_DMA_EEI_EEI5      (0x00000020U) /*!< Bit mask for DMA_EEI_EEI5. */
01277 #define BS_DMA_EEI_EEI5      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI5. */
01278 
01279 /*! @brief Read current value of the DMA_EEI_EEI5 field. */
01280 #define BR_DMA_EEI_EEI5(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5)))
01281 
01282 /*! @brief Format value for bitfield DMA_EEI_EEI5. */
01283 #define BF_DMA_EEI_EEI5(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI5) & BM_DMA_EEI_EEI5)
01284 
01285 /*! @brief Set the EEI5 field to a new value. */
01286 #define BW_DMA_EEI_EEI5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5), v))
01287 /*@}*/
01288 
01289 /*!
01290  * @name Register DMA_EEI, field EEI6[6] (RW)
01291  *
01292  * Values:
01293  * - 0 - The error signal for corresponding channel does not generate an error
01294  *     interrupt
01295  * - 1 - The assertion of the error signal for corresponding channel generates
01296  *     an error interrupt request
01297  */
01298 /*@{*/
01299 #define BP_DMA_EEI_EEI6      (6U)          /*!< Bit position for DMA_EEI_EEI6. */
01300 #define BM_DMA_EEI_EEI6      (0x00000040U) /*!< Bit mask for DMA_EEI_EEI6. */
01301 #define BS_DMA_EEI_EEI6      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI6. */
01302 
01303 /*! @brief Read current value of the DMA_EEI_EEI6 field. */
01304 #define BR_DMA_EEI_EEI6(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6)))
01305 
01306 /*! @brief Format value for bitfield DMA_EEI_EEI6. */
01307 #define BF_DMA_EEI_EEI6(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI6) & BM_DMA_EEI_EEI6)
01308 
01309 /*! @brief Set the EEI6 field to a new value. */
01310 #define BW_DMA_EEI_EEI6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6), v))
01311 /*@}*/
01312 
01313 /*!
01314  * @name Register DMA_EEI, field EEI7[7] (RW)
01315  *
01316  * Values:
01317  * - 0 - The error signal for corresponding channel does not generate an error
01318  *     interrupt
01319  * - 1 - The assertion of the error signal for corresponding channel generates
01320  *     an error interrupt request
01321  */
01322 /*@{*/
01323 #define BP_DMA_EEI_EEI7      (7U)          /*!< Bit position for DMA_EEI_EEI7. */
01324 #define BM_DMA_EEI_EEI7      (0x00000080U) /*!< Bit mask for DMA_EEI_EEI7. */
01325 #define BS_DMA_EEI_EEI7      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI7. */
01326 
01327 /*! @brief Read current value of the DMA_EEI_EEI7 field. */
01328 #define BR_DMA_EEI_EEI7(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7)))
01329 
01330 /*! @brief Format value for bitfield DMA_EEI_EEI7. */
01331 #define BF_DMA_EEI_EEI7(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI7) & BM_DMA_EEI_EEI7)
01332 
01333 /*! @brief Set the EEI7 field to a new value. */
01334 #define BW_DMA_EEI_EEI7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7), v))
01335 /*@}*/
01336 
01337 /*!
01338  * @name Register DMA_EEI, field EEI8[8] (RW)
01339  *
01340  * Values:
01341  * - 0 - The error signal for corresponding channel does not generate an error
01342  *     interrupt
01343  * - 1 - The assertion of the error signal for corresponding channel generates
01344  *     an error interrupt request
01345  */
01346 /*@{*/
01347 #define BP_DMA_EEI_EEI8      (8U)          /*!< Bit position for DMA_EEI_EEI8. */
01348 #define BM_DMA_EEI_EEI8      (0x00000100U) /*!< Bit mask for DMA_EEI_EEI8. */
01349 #define BS_DMA_EEI_EEI8      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI8. */
01350 
01351 /*! @brief Read current value of the DMA_EEI_EEI8 field. */
01352 #define BR_DMA_EEI_EEI8(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8)))
01353 
01354 /*! @brief Format value for bitfield DMA_EEI_EEI8. */
01355 #define BF_DMA_EEI_EEI8(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI8) & BM_DMA_EEI_EEI8)
01356 
01357 /*! @brief Set the EEI8 field to a new value. */
01358 #define BW_DMA_EEI_EEI8(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8), v))
01359 /*@}*/
01360 
01361 /*!
01362  * @name Register DMA_EEI, field EEI9[9] (RW)
01363  *
01364  * Values:
01365  * - 0 - The error signal for corresponding channel does not generate an error
01366  *     interrupt
01367  * - 1 - The assertion of the error signal for corresponding channel generates
01368  *     an error interrupt request
01369  */
01370 /*@{*/
01371 #define BP_DMA_EEI_EEI9      (9U)          /*!< Bit position for DMA_EEI_EEI9. */
01372 #define BM_DMA_EEI_EEI9      (0x00000200U) /*!< Bit mask for DMA_EEI_EEI9. */
01373 #define BS_DMA_EEI_EEI9      (1U)          /*!< Bit field size in bits for DMA_EEI_EEI9. */
01374 
01375 /*! @brief Read current value of the DMA_EEI_EEI9 field. */
01376 #define BR_DMA_EEI_EEI9(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9)))
01377 
01378 /*! @brief Format value for bitfield DMA_EEI_EEI9. */
01379 #define BF_DMA_EEI_EEI9(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI9) & BM_DMA_EEI_EEI9)
01380 
01381 /*! @brief Set the EEI9 field to a new value. */
01382 #define BW_DMA_EEI_EEI9(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9), v))
01383 /*@}*/
01384 
01385 /*!
01386  * @name Register DMA_EEI, field EEI10[10] (RW)
01387  *
01388  * Values:
01389  * - 0 - The error signal for corresponding channel does not generate an error
01390  *     interrupt
01391  * - 1 - The assertion of the error signal for corresponding channel generates
01392  *     an error interrupt request
01393  */
01394 /*@{*/
01395 #define BP_DMA_EEI_EEI10     (10U)         /*!< Bit position for DMA_EEI_EEI10. */
01396 #define BM_DMA_EEI_EEI10     (0x00000400U) /*!< Bit mask for DMA_EEI_EEI10. */
01397 #define BS_DMA_EEI_EEI10     (1U)          /*!< Bit field size in bits for DMA_EEI_EEI10. */
01398 
01399 /*! @brief Read current value of the DMA_EEI_EEI10 field. */
01400 #define BR_DMA_EEI_EEI10(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10)))
01401 
01402 /*! @brief Format value for bitfield DMA_EEI_EEI10. */
01403 #define BF_DMA_EEI_EEI10(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI10) & BM_DMA_EEI_EEI10)
01404 
01405 /*! @brief Set the EEI10 field to a new value. */
01406 #define BW_DMA_EEI_EEI10(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10), v))
01407 /*@}*/
01408 
01409 /*!
01410  * @name Register DMA_EEI, field EEI11[11] (RW)
01411  *
01412  * Values:
01413  * - 0 - The error signal for corresponding channel does not generate an error
01414  *     interrupt
01415  * - 1 - The assertion of the error signal for corresponding channel generates
01416  *     an error interrupt request
01417  */
01418 /*@{*/
01419 #define BP_DMA_EEI_EEI11     (11U)         /*!< Bit position for DMA_EEI_EEI11. */
01420 #define BM_DMA_EEI_EEI11     (0x00000800U) /*!< Bit mask for DMA_EEI_EEI11. */
01421 #define BS_DMA_EEI_EEI11     (1U)          /*!< Bit field size in bits for DMA_EEI_EEI11. */
01422 
01423 /*! @brief Read current value of the DMA_EEI_EEI11 field. */
01424 #define BR_DMA_EEI_EEI11(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11)))
01425 
01426 /*! @brief Format value for bitfield DMA_EEI_EEI11. */
01427 #define BF_DMA_EEI_EEI11(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI11) & BM_DMA_EEI_EEI11)
01428 
01429 /*! @brief Set the EEI11 field to a new value. */
01430 #define BW_DMA_EEI_EEI11(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11), v))
01431 /*@}*/
01432 
01433 /*!
01434  * @name Register DMA_EEI, field EEI12[12] (RW)
01435  *
01436  * Values:
01437  * - 0 - The error signal for corresponding channel does not generate an error
01438  *     interrupt
01439  * - 1 - The assertion of the error signal for corresponding channel generates
01440  *     an error interrupt request
01441  */
01442 /*@{*/
01443 #define BP_DMA_EEI_EEI12     (12U)         /*!< Bit position for DMA_EEI_EEI12. */
01444 #define BM_DMA_EEI_EEI12     (0x00001000U) /*!< Bit mask for DMA_EEI_EEI12. */
01445 #define BS_DMA_EEI_EEI12     (1U)          /*!< Bit field size in bits for DMA_EEI_EEI12. */
01446 
01447 /*! @brief Read current value of the DMA_EEI_EEI12 field. */
01448 #define BR_DMA_EEI_EEI12(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12)))
01449 
01450 /*! @brief Format value for bitfield DMA_EEI_EEI12. */
01451 #define BF_DMA_EEI_EEI12(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI12) & BM_DMA_EEI_EEI12)
01452 
01453 /*! @brief Set the EEI12 field to a new value. */
01454 #define BW_DMA_EEI_EEI12(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12), v))
01455 /*@}*/
01456 
01457 /*!
01458  * @name Register DMA_EEI, field EEI13[13] (RW)
01459  *
01460  * Values:
01461  * - 0 - The error signal for corresponding channel does not generate an error
01462  *     interrupt
01463  * - 1 - The assertion of the error signal for corresponding channel generates
01464  *     an error interrupt request
01465  */
01466 /*@{*/
01467 #define BP_DMA_EEI_EEI13     (13U)         /*!< Bit position for DMA_EEI_EEI13. */
01468 #define BM_DMA_EEI_EEI13     (0x00002000U) /*!< Bit mask for DMA_EEI_EEI13. */
01469 #define BS_DMA_EEI_EEI13     (1U)          /*!< Bit field size in bits for DMA_EEI_EEI13. */
01470 
01471 /*! @brief Read current value of the DMA_EEI_EEI13 field. */
01472 #define BR_DMA_EEI_EEI13(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13)))
01473 
01474 /*! @brief Format value for bitfield DMA_EEI_EEI13. */
01475 #define BF_DMA_EEI_EEI13(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI13) & BM_DMA_EEI_EEI13)
01476 
01477 /*! @brief Set the EEI13 field to a new value. */
01478 #define BW_DMA_EEI_EEI13(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13), v))
01479 /*@}*/
01480 
01481 /*!
01482  * @name Register DMA_EEI, field EEI14[14] (RW)
01483  *
01484  * Values:
01485  * - 0 - The error signal for corresponding channel does not generate an error
01486  *     interrupt
01487  * - 1 - The assertion of the error signal for corresponding channel generates
01488  *     an error interrupt request
01489  */
01490 /*@{*/
01491 #define BP_DMA_EEI_EEI14     (14U)         /*!< Bit position for DMA_EEI_EEI14. */
01492 #define BM_DMA_EEI_EEI14     (0x00004000U) /*!< Bit mask for DMA_EEI_EEI14. */
01493 #define BS_DMA_EEI_EEI14     (1U)          /*!< Bit field size in bits for DMA_EEI_EEI14. */
01494 
01495 /*! @brief Read current value of the DMA_EEI_EEI14 field. */
01496 #define BR_DMA_EEI_EEI14(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14)))
01497 
01498 /*! @brief Format value for bitfield DMA_EEI_EEI14. */
01499 #define BF_DMA_EEI_EEI14(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI14) & BM_DMA_EEI_EEI14)
01500 
01501 /*! @brief Set the EEI14 field to a new value. */
01502 #define BW_DMA_EEI_EEI14(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14), v))
01503 /*@}*/
01504 
01505 /*!
01506  * @name Register DMA_EEI, field EEI15[15] (RW)
01507  *
01508  * Values:
01509  * - 0 - The error signal for corresponding channel does not generate an error
01510  *     interrupt
01511  * - 1 - The assertion of the error signal for corresponding channel generates
01512  *     an error interrupt request
01513  */
01514 /*@{*/
01515 #define BP_DMA_EEI_EEI15     (15U)         /*!< Bit position for DMA_EEI_EEI15. */
01516 #define BM_DMA_EEI_EEI15     (0x00008000U) /*!< Bit mask for DMA_EEI_EEI15. */
01517 #define BS_DMA_EEI_EEI15     (1U)          /*!< Bit field size in bits for DMA_EEI_EEI15. */
01518 
01519 /*! @brief Read current value of the DMA_EEI_EEI15 field. */
01520 #define BR_DMA_EEI_EEI15(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15)))
01521 
01522 /*! @brief Format value for bitfield DMA_EEI_EEI15. */
01523 #define BF_DMA_EEI_EEI15(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_EEI_EEI15) & BM_DMA_EEI_EEI15)
01524 
01525 /*! @brief Set the EEI15 field to a new value. */
01526 #define BW_DMA_EEI_EEI15(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15), v))
01527 /*@}*/
01528 
01529 /*******************************************************************************
01530  * HW_DMA_CEEI - Clear Enable Error Interrupt Register
01531  ******************************************************************************/
01532 
01533 /*!
01534  * @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
01535  *
01536  * Reset value: 0x00U
01537  *
01538  * The CEEI provides a simple memory-mapped mechanism to clear a given bit in
01539  * the EEI to disable the error interrupt for a given channel. The data value on a
01540  * register write causes the corresponding bit in the EEI to be cleared. Setting
01541  * the CAEE bit provides a global clear function, forcing the EEI contents to be
01542  * cleared, disabling all DMA request inputs. If the NOP bit is set, the command
01543  * is ignored. This allows you to write multiple-byte registers as a 32-bit word.
01544  * Reads of this register return all zeroes.
01545  */
01546 typedef union _hw_dma_ceei
01547 {
01548     uint8_t U;
01549     struct _hw_dma_ceei_bitfields
01550     {
01551         uint8_t CEEI : 4;              /*!< [3:0] Clear Enable Error Interrupt */
01552         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
01553         uint8_t CAEE : 1;              /*!< [6] Clear All Enable Error Interrupts */
01554         uint8_t NOP : 1;               /*!< [7] No Op enable */
01555     } B;
01556 } hw_dma_ceei_t;
01557 
01558 /*!
01559  * @name Constants and macros for entire DMA_CEEI register
01560  */
01561 /*@{*/
01562 #define HW_DMA_CEEI_ADDR(x)      ((x) + 0x18U)
01563 
01564 #define HW_DMA_CEEI(x)           (*(__O hw_dma_ceei_t *) HW_DMA_CEEI_ADDR(x))
01565 #define HW_DMA_CEEI_RD(x)        (ADDRESS_READ(hw_dma_ceei_t, HW_DMA_CEEI_ADDR(x)))
01566 #define HW_DMA_CEEI_WR(x, v)     (ADDRESS_WRITE(hw_dma_ceei_t, HW_DMA_CEEI_ADDR(x), v))
01567 /*@}*/
01568 
01569 /*
01570  * Constants & macros for individual DMA_CEEI bitfields
01571  */
01572 
01573 /*!
01574  * @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
01575  *
01576  * Clears the corresponding bit in EEI
01577  */
01578 /*@{*/
01579 #define BP_DMA_CEEI_CEEI     (0U)          /*!< Bit position for DMA_CEEI_CEEI. */
01580 #define BM_DMA_CEEI_CEEI     (0x0FU)       /*!< Bit mask for DMA_CEEI_CEEI. */
01581 #define BS_DMA_CEEI_CEEI     (4U)          /*!< Bit field size in bits for DMA_CEEI_CEEI. */
01582 
01583 /*! @brief Format value for bitfield DMA_CEEI_CEEI. */
01584 #define BF_DMA_CEEI_CEEI(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CEEI) & BM_DMA_CEEI_CEEI)
01585 
01586 /*! @brief Set the CEEI field to a new value. */
01587 #define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) | BF_DMA_CEEI_CEEI(v)))
01588 /*@}*/
01589 
01590 /*!
01591  * @name Register DMA_CEEI, field CAEE[6] (WORZ)
01592  *
01593  * Values:
01594  * - 0 - Clear only the EEI bit specified in the CEEI field
01595  * - 1 - Clear all bits in EEI
01596  */
01597 /*@{*/
01598 #define BP_DMA_CEEI_CAEE     (6U)          /*!< Bit position for DMA_CEEI_CAEE. */
01599 #define BM_DMA_CEEI_CAEE     (0x40U)       /*!< Bit mask for DMA_CEEI_CAEE. */
01600 #define BS_DMA_CEEI_CAEE     (1U)          /*!< Bit field size in bits for DMA_CEEI_CAEE. */
01601 
01602 /*! @brief Format value for bitfield DMA_CEEI_CAEE. */
01603 #define BF_DMA_CEEI_CAEE(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_CAEE) & BM_DMA_CEEI_CAEE)
01604 
01605 /*! @brief Set the CAEE field to a new value. */
01606 #define BW_DMA_CEEI_CAEE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE), v))
01607 /*@}*/
01608 
01609 /*!
01610  * @name Register DMA_CEEI, field NOP[7] (WORZ)
01611  *
01612  * Values:
01613  * - 0 - Normal operation
01614  * - 1 - No operation, ignore the other bits in this register
01615  */
01616 /*@{*/
01617 #define BP_DMA_CEEI_NOP      (7U)          /*!< Bit position for DMA_CEEI_NOP. */
01618 #define BM_DMA_CEEI_NOP      (0x80U)       /*!< Bit mask for DMA_CEEI_NOP. */
01619 #define BS_DMA_CEEI_NOP      (1U)          /*!< Bit field size in bits for DMA_CEEI_NOP. */
01620 
01621 /*! @brief Format value for bitfield DMA_CEEI_NOP. */
01622 #define BF_DMA_CEEI_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_CEEI_NOP) & BM_DMA_CEEI_NOP)
01623 
01624 /*! @brief Set the NOP field to a new value. */
01625 #define BW_DMA_CEEI_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP), v))
01626 /*@}*/
01627 
01628 /*******************************************************************************
01629  * HW_DMA_SEEI - Set Enable Error Interrupt Register
01630  ******************************************************************************/
01631 
01632 /*!
01633  * @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
01634  *
01635  * Reset value: 0x00U
01636  *
01637  * The SEEI provides a simple memory-mapped mechanism to set a given bit in the
01638  * EEI to enable the error interrupt for a given channel. The data value on a
01639  * register write causes the corresponding bit in the EEI to be set. Setting the
01640  * SAEE bit provides a global set function, forcing the entire EEI contents to be
01641  * set. If the NOP bit is set, the command is ignored. This allows you to write
01642  * multiple-byte registers as a 32-bit word. Reads of this register return all
01643  * zeroes.
01644  */
01645 typedef union _hw_dma_seei
01646 {
01647     uint8_t U;
01648     struct _hw_dma_seei_bitfields
01649     {
01650         uint8_t SEEI : 4;              /*!< [3:0] Set Enable Error Interrupt */
01651         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
01652         uint8_t SAEE : 1;              /*!< [6] Sets All Enable Error Interrupts */
01653         uint8_t NOP : 1;               /*!< [7] No Op enable */
01654     } B;
01655 } hw_dma_seei_t;
01656 
01657 /*!
01658  * @name Constants and macros for entire DMA_SEEI register
01659  */
01660 /*@{*/
01661 #define HW_DMA_SEEI_ADDR(x)      ((x) + 0x19U)
01662 
01663 #define HW_DMA_SEEI(x)           (*(__O hw_dma_seei_t *) HW_DMA_SEEI_ADDR(x))
01664 #define HW_DMA_SEEI_RD(x)        (ADDRESS_READ(hw_dma_seei_t, HW_DMA_SEEI_ADDR(x)))
01665 #define HW_DMA_SEEI_WR(x, v)     (ADDRESS_WRITE(hw_dma_seei_t, HW_DMA_SEEI_ADDR(x), v))
01666 /*@}*/
01667 
01668 /*
01669  * Constants & macros for individual DMA_SEEI bitfields
01670  */
01671 
01672 /*!
01673  * @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
01674  *
01675  * Sets the corresponding bit in EEI
01676  */
01677 /*@{*/
01678 #define BP_DMA_SEEI_SEEI     (0U)          /*!< Bit position for DMA_SEEI_SEEI. */
01679 #define BM_DMA_SEEI_SEEI     (0x0FU)       /*!< Bit mask for DMA_SEEI_SEEI. */
01680 #define BS_DMA_SEEI_SEEI     (4U)          /*!< Bit field size in bits for DMA_SEEI_SEEI. */
01681 
01682 /*! @brief Format value for bitfield DMA_SEEI_SEEI. */
01683 #define BF_DMA_SEEI_SEEI(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SEEI) & BM_DMA_SEEI_SEEI)
01684 
01685 /*! @brief Set the SEEI field to a new value. */
01686 #define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) | BF_DMA_SEEI_SEEI(v)))
01687 /*@}*/
01688 
01689 /*!
01690  * @name Register DMA_SEEI, field SAEE[6] (WORZ)
01691  *
01692  * Values:
01693  * - 0 - Set only the EEI bit specified in the SEEI field.
01694  * - 1 - Sets all bits in EEI
01695  */
01696 /*@{*/
01697 #define BP_DMA_SEEI_SAEE     (6U)          /*!< Bit position for DMA_SEEI_SAEE. */
01698 #define BM_DMA_SEEI_SAEE     (0x40U)       /*!< Bit mask for DMA_SEEI_SAEE. */
01699 #define BS_DMA_SEEI_SAEE     (1U)          /*!< Bit field size in bits for DMA_SEEI_SAEE. */
01700 
01701 /*! @brief Format value for bitfield DMA_SEEI_SAEE. */
01702 #define BF_DMA_SEEI_SAEE(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_SAEE) & BM_DMA_SEEI_SAEE)
01703 
01704 /*! @brief Set the SAEE field to a new value. */
01705 #define BW_DMA_SEEI_SAEE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE), v))
01706 /*@}*/
01707 
01708 /*!
01709  * @name Register DMA_SEEI, field NOP[7] (WORZ)
01710  *
01711  * Values:
01712  * - 0 - Normal operation
01713  * - 1 - No operation, ignore the other bits in this register
01714  */
01715 /*@{*/
01716 #define BP_DMA_SEEI_NOP      (7U)          /*!< Bit position for DMA_SEEI_NOP. */
01717 #define BM_DMA_SEEI_NOP      (0x80U)       /*!< Bit mask for DMA_SEEI_NOP. */
01718 #define BS_DMA_SEEI_NOP      (1U)          /*!< Bit field size in bits for DMA_SEEI_NOP. */
01719 
01720 /*! @brief Format value for bitfield DMA_SEEI_NOP. */
01721 #define BF_DMA_SEEI_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_SEEI_NOP) & BM_DMA_SEEI_NOP)
01722 
01723 /*! @brief Set the NOP field to a new value. */
01724 #define BW_DMA_SEEI_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP), v))
01725 /*@}*/
01726 
01727 /*******************************************************************************
01728  * HW_DMA_CERQ - Clear Enable Request Register
01729  ******************************************************************************/
01730 
01731 /*!
01732  * @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
01733  *
01734  * Reset value: 0x00U
01735  *
01736  * The CERQ provides a simple memory-mapped mechanism to clear a given bit in
01737  * the ERQ to disable the DMA request for a given channel. The data value on a
01738  * register write causes the corresponding bit in the ERQ to be cleared. Setting the
01739  * CAER bit provides a global clear function, forcing the entire contents of the
01740  * ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
01741  * command is ignored. This allows you to write multiple-byte registers as a 32-bit
01742  * word. Reads of this register return all zeroes.
01743  */
01744 typedef union _hw_dma_cerq
01745 {
01746     uint8_t U;
01747     struct _hw_dma_cerq_bitfields
01748     {
01749         uint8_t CERQ : 4;              /*!< [3:0] Clear Enable Request */
01750         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
01751         uint8_t CAER : 1;              /*!< [6] Clear All Enable Requests */
01752         uint8_t NOP : 1;               /*!< [7] No Op enable */
01753     } B;
01754 } hw_dma_cerq_t;
01755 
01756 /*!
01757  * @name Constants and macros for entire DMA_CERQ register
01758  */
01759 /*@{*/
01760 #define HW_DMA_CERQ_ADDR(x)      ((x) + 0x1AU)
01761 
01762 #define HW_DMA_CERQ(x)           (*(__O hw_dma_cerq_t *) HW_DMA_CERQ_ADDR(x))
01763 #define HW_DMA_CERQ_RD(x)        (ADDRESS_READ(hw_dma_cerq_t, HW_DMA_CERQ_ADDR(x)))
01764 #define HW_DMA_CERQ_WR(x, v)     (ADDRESS_WRITE(hw_dma_cerq_t, HW_DMA_CERQ_ADDR(x), v))
01765 /*@}*/
01766 
01767 /*
01768  * Constants & macros for individual DMA_CERQ bitfields
01769  */
01770 
01771 /*!
01772  * @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
01773  *
01774  * Clears the corresponding bit in ERQ
01775  */
01776 /*@{*/
01777 #define BP_DMA_CERQ_CERQ     (0U)          /*!< Bit position for DMA_CERQ_CERQ. */
01778 #define BM_DMA_CERQ_CERQ     (0x0FU)       /*!< Bit mask for DMA_CERQ_CERQ. */
01779 #define BS_DMA_CERQ_CERQ     (4U)          /*!< Bit field size in bits for DMA_CERQ_CERQ. */
01780 
01781 /*! @brief Format value for bitfield DMA_CERQ_CERQ. */
01782 #define BF_DMA_CERQ_CERQ(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CERQ) & BM_DMA_CERQ_CERQ)
01783 
01784 /*! @brief Set the CERQ field to a new value. */
01785 #define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) | BF_DMA_CERQ_CERQ(v)))
01786 /*@}*/
01787 
01788 /*!
01789  * @name Register DMA_CERQ, field CAER[6] (WORZ)
01790  *
01791  * Values:
01792  * - 0 - Clear only the ERQ bit specified in the CERQ field
01793  * - 1 - Clear all bits in ERQ
01794  */
01795 /*@{*/
01796 #define BP_DMA_CERQ_CAER     (6U)          /*!< Bit position for DMA_CERQ_CAER. */
01797 #define BM_DMA_CERQ_CAER     (0x40U)       /*!< Bit mask for DMA_CERQ_CAER. */
01798 #define BS_DMA_CERQ_CAER     (1U)          /*!< Bit field size in bits for DMA_CERQ_CAER. */
01799 
01800 /*! @brief Format value for bitfield DMA_CERQ_CAER. */
01801 #define BF_DMA_CERQ_CAER(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_CAER) & BM_DMA_CERQ_CAER)
01802 
01803 /*! @brief Set the CAER field to a new value. */
01804 #define BW_DMA_CERQ_CAER(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER), v))
01805 /*@}*/
01806 
01807 /*!
01808  * @name Register DMA_CERQ, field NOP[7] (WORZ)
01809  *
01810  * Values:
01811  * - 0 - Normal operation
01812  * - 1 - No operation, ignore the other bits in this register
01813  */
01814 /*@{*/
01815 #define BP_DMA_CERQ_NOP      (7U)          /*!< Bit position for DMA_CERQ_NOP. */
01816 #define BM_DMA_CERQ_NOP      (0x80U)       /*!< Bit mask for DMA_CERQ_NOP. */
01817 #define BS_DMA_CERQ_NOP      (1U)          /*!< Bit field size in bits for DMA_CERQ_NOP. */
01818 
01819 /*! @brief Format value for bitfield DMA_CERQ_NOP. */
01820 #define BF_DMA_CERQ_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_CERQ_NOP) & BM_DMA_CERQ_NOP)
01821 
01822 /*! @brief Set the NOP field to a new value. */
01823 #define BW_DMA_CERQ_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP), v))
01824 /*@}*/
01825 
01826 /*******************************************************************************
01827  * HW_DMA_SERQ - Set Enable Request Register
01828  ******************************************************************************/
01829 
01830 /*!
01831  * @brief HW_DMA_SERQ - Set Enable Request Register (WO)
01832  *
01833  * Reset value: 0x00U
01834  *
01835  * The SERQ provides a simple memory-mapped mechanism to set a given bit in the
01836  * ERQ to enable the DMA request for a given channel. The data value on a
01837  * register write causes the corresponding bit in the ERQ to be set. Setting the SAER
01838  * bit provides a global set function, forcing the entire contents of ERQ to be
01839  * set. If the NOP bit is set, the command is ignored. This allows you to write
01840  * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
01841  */
01842 typedef union _hw_dma_serq
01843 {
01844     uint8_t U;
01845     struct _hw_dma_serq_bitfields
01846     {
01847         uint8_t SERQ : 4;              /*!< [3:0] Set enable request */
01848         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
01849         uint8_t SAER : 1;              /*!< [6] Set All Enable Requests */
01850         uint8_t NOP : 1;               /*!< [7] No Op enable */
01851     } B;
01852 } hw_dma_serq_t;
01853 
01854 /*!
01855  * @name Constants and macros for entire DMA_SERQ register
01856  */
01857 /*@{*/
01858 #define HW_DMA_SERQ_ADDR(x)      ((x) + 0x1BU)
01859 
01860 #define HW_DMA_SERQ(x)           (*(__O hw_dma_serq_t *) HW_DMA_SERQ_ADDR(x))
01861 #define HW_DMA_SERQ_RD(x)        (ADDRESS_READ(hw_dma_serq_t, HW_DMA_SERQ_ADDR(x)))
01862 #define HW_DMA_SERQ_WR(x, v)     (ADDRESS_WRITE(hw_dma_serq_t, HW_DMA_SERQ_ADDR(x), v))
01863 /*@}*/
01864 
01865 /*
01866  * Constants & macros for individual DMA_SERQ bitfields
01867  */
01868 
01869 /*!
01870  * @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
01871  *
01872  * Sets the corresponding bit in ERQ
01873  */
01874 /*@{*/
01875 #define BP_DMA_SERQ_SERQ     (0U)          /*!< Bit position for DMA_SERQ_SERQ. */
01876 #define BM_DMA_SERQ_SERQ     (0x0FU)       /*!< Bit mask for DMA_SERQ_SERQ. */
01877 #define BS_DMA_SERQ_SERQ     (4U)          /*!< Bit field size in bits for DMA_SERQ_SERQ. */
01878 
01879 /*! @brief Format value for bitfield DMA_SERQ_SERQ. */
01880 #define BF_DMA_SERQ_SERQ(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SERQ) & BM_DMA_SERQ_SERQ)
01881 
01882 /*! @brief Set the SERQ field to a new value. */
01883 #define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) | BF_DMA_SERQ_SERQ(v)))
01884 /*@}*/
01885 
01886 /*!
01887  * @name Register DMA_SERQ, field SAER[6] (WORZ)
01888  *
01889  * Values:
01890  * - 0 - Set only the ERQ bit specified in the SERQ field
01891  * - 1 - Set all bits in ERQ
01892  */
01893 /*@{*/
01894 #define BP_DMA_SERQ_SAER     (6U)          /*!< Bit position for DMA_SERQ_SAER. */
01895 #define BM_DMA_SERQ_SAER     (0x40U)       /*!< Bit mask for DMA_SERQ_SAER. */
01896 #define BS_DMA_SERQ_SAER     (1U)          /*!< Bit field size in bits for DMA_SERQ_SAER. */
01897 
01898 /*! @brief Format value for bitfield DMA_SERQ_SAER. */
01899 #define BF_DMA_SERQ_SAER(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_SAER) & BM_DMA_SERQ_SAER)
01900 
01901 /*! @brief Set the SAER field to a new value. */
01902 #define BW_DMA_SERQ_SAER(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER), v))
01903 /*@}*/
01904 
01905 /*!
01906  * @name Register DMA_SERQ, field NOP[7] (WORZ)
01907  *
01908  * Values:
01909  * - 0 - Normal operation
01910  * - 1 - No operation, ignore the other bits in this register
01911  */
01912 /*@{*/
01913 #define BP_DMA_SERQ_NOP      (7U)          /*!< Bit position for DMA_SERQ_NOP. */
01914 #define BM_DMA_SERQ_NOP      (0x80U)       /*!< Bit mask for DMA_SERQ_NOP. */
01915 #define BS_DMA_SERQ_NOP      (1U)          /*!< Bit field size in bits for DMA_SERQ_NOP. */
01916 
01917 /*! @brief Format value for bitfield DMA_SERQ_NOP. */
01918 #define BF_DMA_SERQ_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_SERQ_NOP) & BM_DMA_SERQ_NOP)
01919 
01920 /*! @brief Set the NOP field to a new value. */
01921 #define BW_DMA_SERQ_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP), v))
01922 /*@}*/
01923 
01924 /*******************************************************************************
01925  * HW_DMA_CDNE - Clear DONE Status Bit Register
01926  ******************************************************************************/
01927 
01928 /*!
01929  * @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
01930  *
01931  * Reset value: 0x00U
01932  *
01933  * The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
01934  * the TCD of the given channel. The data value on a register write causes the
01935  * DONE bit in the corresponding transfer control descriptor to be cleared. Setting
01936  * the CADN bit provides a global clear function, forcing all DONE bits to be
01937  * cleared. If the NOP bit is set, the command is ignored. This allows you to write
01938  * multiple-byte registers as a 32-bit word. Reads of this register return all
01939  * zeroes.
01940  */
01941 typedef union _hw_dma_cdne
01942 {
01943     uint8_t U;
01944     struct _hw_dma_cdne_bitfields
01945     {
01946         uint8_t CDNE : 4;              /*!< [3:0] Clear DONE Bit */
01947         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
01948         uint8_t CADN : 1;              /*!< [6] Clears All DONE Bits */
01949         uint8_t NOP : 1;               /*!< [7] No Op enable */
01950     } B;
01951 } hw_dma_cdne_t;
01952 
01953 /*!
01954  * @name Constants and macros for entire DMA_CDNE register
01955  */
01956 /*@{*/
01957 #define HW_DMA_CDNE_ADDR(x)      ((x) + 0x1CU)
01958 
01959 #define HW_DMA_CDNE(x)           (*(__O hw_dma_cdne_t *) HW_DMA_CDNE_ADDR(x))
01960 #define HW_DMA_CDNE_RD(x)        (ADDRESS_READ(hw_dma_cdne_t, HW_DMA_CDNE_ADDR(x)))
01961 #define HW_DMA_CDNE_WR(x, v)     (ADDRESS_WRITE(hw_dma_cdne_t, HW_DMA_CDNE_ADDR(x), v))
01962 /*@}*/
01963 
01964 /*
01965  * Constants & macros for individual DMA_CDNE bitfields
01966  */
01967 
01968 /*!
01969  * @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
01970  *
01971  * Clears the corresponding bit in TCDn_CSR[DONE]
01972  */
01973 /*@{*/
01974 #define BP_DMA_CDNE_CDNE     (0U)          /*!< Bit position for DMA_CDNE_CDNE. */
01975 #define BM_DMA_CDNE_CDNE     (0x0FU)       /*!< Bit mask for DMA_CDNE_CDNE. */
01976 #define BS_DMA_CDNE_CDNE     (4U)          /*!< Bit field size in bits for DMA_CDNE_CDNE. */
01977 
01978 /*! @brief Format value for bitfield DMA_CDNE_CDNE. */
01979 #define BF_DMA_CDNE_CDNE(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CDNE) & BM_DMA_CDNE_CDNE)
01980 
01981 /*! @brief Set the CDNE field to a new value. */
01982 #define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) | BF_DMA_CDNE_CDNE(v)))
01983 /*@}*/
01984 
01985 /*!
01986  * @name Register DMA_CDNE, field CADN[6] (WORZ)
01987  *
01988  * Values:
01989  * - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
01990  * - 1 - Clears all bits in TCDn_CSR[DONE]
01991  */
01992 /*@{*/
01993 #define BP_DMA_CDNE_CADN     (6U)          /*!< Bit position for DMA_CDNE_CADN. */
01994 #define BM_DMA_CDNE_CADN     (0x40U)       /*!< Bit mask for DMA_CDNE_CADN. */
01995 #define BS_DMA_CDNE_CADN     (1U)          /*!< Bit field size in bits for DMA_CDNE_CADN. */
01996 
01997 /*! @brief Format value for bitfield DMA_CDNE_CADN. */
01998 #define BF_DMA_CDNE_CADN(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_CADN) & BM_DMA_CDNE_CADN)
01999 
02000 /*! @brief Set the CADN field to a new value. */
02001 #define BW_DMA_CDNE_CADN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN), v))
02002 /*@}*/
02003 
02004 /*!
02005  * @name Register DMA_CDNE, field NOP[7] (WORZ)
02006  *
02007  * Values:
02008  * - 0 - Normal operation
02009  * - 1 - No operation, ignore the other bits in this register
02010  */
02011 /*@{*/
02012 #define BP_DMA_CDNE_NOP      (7U)          /*!< Bit position for DMA_CDNE_NOP. */
02013 #define BM_DMA_CDNE_NOP      (0x80U)       /*!< Bit mask for DMA_CDNE_NOP. */
02014 #define BS_DMA_CDNE_NOP      (1U)          /*!< Bit field size in bits for DMA_CDNE_NOP. */
02015 
02016 /*! @brief Format value for bitfield DMA_CDNE_NOP. */
02017 #define BF_DMA_CDNE_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_CDNE_NOP) & BM_DMA_CDNE_NOP)
02018 
02019 /*! @brief Set the NOP field to a new value. */
02020 #define BW_DMA_CDNE_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP), v))
02021 /*@}*/
02022 
02023 /*******************************************************************************
02024  * HW_DMA_SSRT - Set START Bit Register
02025  ******************************************************************************/
02026 
02027 /*!
02028  * @brief HW_DMA_SSRT - Set START Bit Register (WO)
02029  *
02030  * Reset value: 0x00U
02031  *
02032  * The SSRT provides a simple memory-mapped mechanism to set the START bit in
02033  * the TCD of the given channel. The data value on a register write causes the
02034  * START bit in the corresponding transfer control descriptor to be set. Setting the
02035  * SAST bit provides a global set function, forcing all START bits to be set. If
02036  * the NOP bit is set, the command is ignored. This allows you to write
02037  * multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
02038  */
02039 typedef union _hw_dma_ssrt
02040 {
02041     uint8_t U;
02042     struct _hw_dma_ssrt_bitfields
02043     {
02044         uint8_t SSRT : 4;              /*!< [3:0] Set START Bit */
02045         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
02046         uint8_t SAST : 1;              /*!< [6] Set All START Bits (activates all
02047                                         * channels) */
02048         uint8_t NOP : 1;               /*!< [7] No Op enable */
02049     } B;
02050 } hw_dma_ssrt_t;
02051 
02052 /*!
02053  * @name Constants and macros for entire DMA_SSRT register
02054  */
02055 /*@{*/
02056 #define HW_DMA_SSRT_ADDR(x)      ((x) + 0x1DU)
02057 
02058 #define HW_DMA_SSRT(x)           (*(__O hw_dma_ssrt_t *) HW_DMA_SSRT_ADDR(x))
02059 #define HW_DMA_SSRT_RD(x)        (ADDRESS_READ(hw_dma_ssrt_t, HW_DMA_SSRT_ADDR(x)))
02060 #define HW_DMA_SSRT_WR(x, v)     (ADDRESS_WRITE(hw_dma_ssrt_t, HW_DMA_SSRT_ADDR(x), v))
02061 /*@}*/
02062 
02063 /*
02064  * Constants & macros for individual DMA_SSRT bitfields
02065  */
02066 
02067 /*!
02068  * @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
02069  *
02070  * Sets the corresponding bit in TCDn_CSR[START]
02071  */
02072 /*@{*/
02073 #define BP_DMA_SSRT_SSRT     (0U)          /*!< Bit position for DMA_SSRT_SSRT. */
02074 #define BM_DMA_SSRT_SSRT     (0x0FU)       /*!< Bit mask for DMA_SSRT_SSRT. */
02075 #define BS_DMA_SSRT_SSRT     (4U)          /*!< Bit field size in bits for DMA_SSRT_SSRT. */
02076 
02077 /*! @brief Format value for bitfield DMA_SSRT_SSRT. */
02078 #define BF_DMA_SSRT_SSRT(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SSRT) & BM_DMA_SSRT_SSRT)
02079 
02080 /*! @brief Set the SSRT field to a new value. */
02081 #define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) | BF_DMA_SSRT_SSRT(v)))
02082 /*@}*/
02083 
02084 /*!
02085  * @name Register DMA_SSRT, field SAST[6] (WORZ)
02086  *
02087  * Values:
02088  * - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
02089  * - 1 - Set all bits in TCDn_CSR[START]
02090  */
02091 /*@{*/
02092 #define BP_DMA_SSRT_SAST     (6U)          /*!< Bit position for DMA_SSRT_SAST. */
02093 #define BM_DMA_SSRT_SAST     (0x40U)       /*!< Bit mask for DMA_SSRT_SAST. */
02094 #define BS_DMA_SSRT_SAST     (1U)          /*!< Bit field size in bits for DMA_SSRT_SAST. */
02095 
02096 /*! @brief Format value for bitfield DMA_SSRT_SAST. */
02097 #define BF_DMA_SSRT_SAST(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_SAST) & BM_DMA_SSRT_SAST)
02098 
02099 /*! @brief Set the SAST field to a new value. */
02100 #define BW_DMA_SSRT_SAST(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST), v))
02101 /*@}*/
02102 
02103 /*!
02104  * @name Register DMA_SSRT, field NOP[7] (WORZ)
02105  *
02106  * Values:
02107  * - 0 - Normal operation
02108  * - 1 - No operation, ignore the other bits in this register
02109  */
02110 /*@{*/
02111 #define BP_DMA_SSRT_NOP      (7U)          /*!< Bit position for DMA_SSRT_NOP. */
02112 #define BM_DMA_SSRT_NOP      (0x80U)       /*!< Bit mask for DMA_SSRT_NOP. */
02113 #define BS_DMA_SSRT_NOP      (1U)          /*!< Bit field size in bits for DMA_SSRT_NOP. */
02114 
02115 /*! @brief Format value for bitfield DMA_SSRT_NOP. */
02116 #define BF_DMA_SSRT_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_SSRT_NOP) & BM_DMA_SSRT_NOP)
02117 
02118 /*! @brief Set the NOP field to a new value. */
02119 #define BW_DMA_SSRT_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP), v))
02120 /*@}*/
02121 
02122 /*******************************************************************************
02123  * HW_DMA_CERR - Clear Error Register
02124  ******************************************************************************/
02125 
02126 /*!
02127  * @brief HW_DMA_CERR - Clear Error Register (WO)
02128  *
02129  * Reset value: 0x00U
02130  *
02131  * The CERR provides a simple memory-mapped mechanism to clear a given bit in
02132  * the ERR to disable the error condition flag for a given channel. The given value
02133  * on a register write causes the corresponding bit in the ERR to be cleared.
02134  * Setting the CAEI bit provides a global clear function, forcing the ERR contents
02135  * to be cleared, clearing all channel error indicators. If the NOP bit is set,
02136  * the command is ignored. This allows you to write multiple-byte registers as a
02137  * 32-bit word. Reads of this register return all zeroes.
02138  */
02139 typedef union _hw_dma_cerr
02140 {
02141     uint8_t U;
02142     struct _hw_dma_cerr_bitfields
02143     {
02144         uint8_t CERR : 4;              /*!< [3:0] Clear Error Indicator */
02145         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
02146         uint8_t CAEI : 1;              /*!< [6] Clear All Error Indicators */
02147         uint8_t NOP : 1;               /*!< [7] No Op enable */
02148     } B;
02149 } hw_dma_cerr_t;
02150 
02151 /*!
02152  * @name Constants and macros for entire DMA_CERR register
02153  */
02154 /*@{*/
02155 #define HW_DMA_CERR_ADDR(x)      ((x) + 0x1EU)
02156 
02157 #define HW_DMA_CERR(x)           (*(__O hw_dma_cerr_t *) HW_DMA_CERR_ADDR(x))
02158 #define HW_DMA_CERR_RD(x)        (ADDRESS_READ(hw_dma_cerr_t, HW_DMA_CERR_ADDR(x)))
02159 #define HW_DMA_CERR_WR(x, v)     (ADDRESS_WRITE(hw_dma_cerr_t, HW_DMA_CERR_ADDR(x), v))
02160 /*@}*/
02161 
02162 /*
02163  * Constants & macros for individual DMA_CERR bitfields
02164  */
02165 
02166 /*!
02167  * @name Register DMA_CERR, field CERR[3:0] (WORZ)
02168  *
02169  * Clears the corresponding bit in ERR
02170  */
02171 /*@{*/
02172 #define BP_DMA_CERR_CERR     (0U)          /*!< Bit position for DMA_CERR_CERR. */
02173 #define BM_DMA_CERR_CERR     (0x0FU)       /*!< Bit mask for DMA_CERR_CERR. */
02174 #define BS_DMA_CERR_CERR     (4U)          /*!< Bit field size in bits for DMA_CERR_CERR. */
02175 
02176 /*! @brief Format value for bitfield DMA_CERR_CERR. */
02177 #define BF_DMA_CERR_CERR(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CERR) & BM_DMA_CERR_CERR)
02178 
02179 /*! @brief Set the CERR field to a new value. */
02180 #define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) | BF_DMA_CERR_CERR(v)))
02181 /*@}*/
02182 
02183 /*!
02184  * @name Register DMA_CERR, field CAEI[6] (WORZ)
02185  *
02186  * Values:
02187  * - 0 - Clear only the ERR bit specified in the CERR field
02188  * - 1 - Clear all bits in ERR
02189  */
02190 /*@{*/
02191 #define BP_DMA_CERR_CAEI     (6U)          /*!< Bit position for DMA_CERR_CAEI. */
02192 #define BM_DMA_CERR_CAEI     (0x40U)       /*!< Bit mask for DMA_CERR_CAEI. */
02193 #define BS_DMA_CERR_CAEI     (1U)          /*!< Bit field size in bits for DMA_CERR_CAEI. */
02194 
02195 /*! @brief Format value for bitfield DMA_CERR_CAEI. */
02196 #define BF_DMA_CERR_CAEI(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_CAEI) & BM_DMA_CERR_CAEI)
02197 
02198 /*! @brief Set the CAEI field to a new value. */
02199 #define BW_DMA_CERR_CAEI(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI), v))
02200 /*@}*/
02201 
02202 /*!
02203  * @name Register DMA_CERR, field NOP[7] (WORZ)
02204  *
02205  * Values:
02206  * - 0 - Normal operation
02207  * - 1 - No operation, ignore the other bits in this register
02208  */
02209 /*@{*/
02210 #define BP_DMA_CERR_NOP      (7U)          /*!< Bit position for DMA_CERR_NOP. */
02211 #define BM_DMA_CERR_NOP      (0x80U)       /*!< Bit mask for DMA_CERR_NOP. */
02212 #define BS_DMA_CERR_NOP      (1U)          /*!< Bit field size in bits for DMA_CERR_NOP. */
02213 
02214 /*! @brief Format value for bitfield DMA_CERR_NOP. */
02215 #define BF_DMA_CERR_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_CERR_NOP) & BM_DMA_CERR_NOP)
02216 
02217 /*! @brief Set the NOP field to a new value. */
02218 #define BW_DMA_CERR_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP), v))
02219 /*@}*/
02220 
02221 /*******************************************************************************
02222  * HW_DMA_CINT - Clear Interrupt Request Register
02223  ******************************************************************************/
02224 
02225 /*!
02226  * @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
02227  *
02228  * Reset value: 0x00U
02229  *
02230  * The CINT provides a simple, memory-mapped mechanism to clear a given bit in
02231  * the INT to disable the interrupt request for a given channel. The given value
02232  * on a register write causes the corresponding bit in the INT to be cleared.
02233  * Setting the CAIR bit provides a global clear function, forcing the entire contents
02234  * of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
02235  * bit is set, the command is ignored. This allows you to write multiple-byte
02236  * registers as a 32-bit word. Reads of this register return all zeroes.
02237  */
02238 typedef union _hw_dma_cint
02239 {
02240     uint8_t U;
02241     struct _hw_dma_cint_bitfields
02242     {
02243         uint8_t CINT : 4;              /*!< [3:0] Clear Interrupt Request */
02244         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
02245         uint8_t CAIR : 1;              /*!< [6] Clear All Interrupt Requests */
02246         uint8_t NOP : 1;               /*!< [7] No Op enable */
02247     } B;
02248 } hw_dma_cint_t;
02249 
02250 /*!
02251  * @name Constants and macros for entire DMA_CINT register
02252  */
02253 /*@{*/
02254 #define HW_DMA_CINT_ADDR(x)      ((x) + 0x1FU)
02255 
02256 #define HW_DMA_CINT(x)           (*(__O hw_dma_cint_t *) HW_DMA_CINT_ADDR(x))
02257 #define HW_DMA_CINT_RD(x)        (ADDRESS_READ(hw_dma_cint_t, HW_DMA_CINT_ADDR(x)))
02258 #define HW_DMA_CINT_WR(x, v)     (ADDRESS_WRITE(hw_dma_cint_t, HW_DMA_CINT_ADDR(x), v))
02259 /*@}*/
02260 
02261 /*
02262  * Constants & macros for individual DMA_CINT bitfields
02263  */
02264 
02265 /*!
02266  * @name Register DMA_CINT, field CINT[3:0] (WORZ)
02267  *
02268  * Clears the corresponding bit in INT
02269  */
02270 /*@{*/
02271 #define BP_DMA_CINT_CINT     (0U)          /*!< Bit position for DMA_CINT_CINT. */
02272 #define BM_DMA_CINT_CINT     (0x0FU)       /*!< Bit mask for DMA_CINT_CINT. */
02273 #define BS_DMA_CINT_CINT     (4U)          /*!< Bit field size in bits for DMA_CINT_CINT. */
02274 
02275 /*! @brief Format value for bitfield DMA_CINT_CINT. */
02276 #define BF_DMA_CINT_CINT(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CINT) & BM_DMA_CINT_CINT)
02277 
02278 /*! @brief Set the CINT field to a new value. */
02279 #define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) | BF_DMA_CINT_CINT(v)))
02280 /*@}*/
02281 
02282 /*!
02283  * @name Register DMA_CINT, field CAIR[6] (WORZ)
02284  *
02285  * Values:
02286  * - 0 - Clear only the INT bit specified in the CINT field
02287  * - 1 - Clear all bits in INT
02288  */
02289 /*@{*/
02290 #define BP_DMA_CINT_CAIR     (6U)          /*!< Bit position for DMA_CINT_CAIR. */
02291 #define BM_DMA_CINT_CAIR     (0x40U)       /*!< Bit mask for DMA_CINT_CAIR. */
02292 #define BS_DMA_CINT_CAIR     (1U)          /*!< Bit field size in bits for DMA_CINT_CAIR. */
02293 
02294 /*! @brief Format value for bitfield DMA_CINT_CAIR. */
02295 #define BF_DMA_CINT_CAIR(v)  ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_CAIR) & BM_DMA_CINT_CAIR)
02296 
02297 /*! @brief Set the CAIR field to a new value. */
02298 #define BW_DMA_CINT_CAIR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR), v))
02299 /*@}*/
02300 
02301 /*!
02302  * @name Register DMA_CINT, field NOP[7] (WORZ)
02303  *
02304  * Values:
02305  * - 0 - Normal operation
02306  * - 1 - No operation, ignore the other bits in this register
02307  */
02308 /*@{*/
02309 #define BP_DMA_CINT_NOP      (7U)          /*!< Bit position for DMA_CINT_NOP. */
02310 #define BM_DMA_CINT_NOP      (0x80U)       /*!< Bit mask for DMA_CINT_NOP. */
02311 #define BS_DMA_CINT_NOP      (1U)          /*!< Bit field size in bits for DMA_CINT_NOP. */
02312 
02313 /*! @brief Format value for bitfield DMA_CINT_NOP. */
02314 #define BF_DMA_CINT_NOP(v)   ((uint8_t)((uint8_t)(v) << BP_DMA_CINT_NOP) & BM_DMA_CINT_NOP)
02315 
02316 /*! @brief Set the NOP field to a new value. */
02317 #define BW_DMA_CINT_NOP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP), v))
02318 /*@}*/
02319 
02320 /*******************************************************************************
02321  * HW_DMA_INT - Interrupt Request Register
02322  ******************************************************************************/
02323 
02324 /*!
02325  * @brief HW_DMA_INT - Interrupt Request Register (RW)
02326  *
02327  * Reset value: 0x00000000U
02328  *
02329  * The INT register provides a bit map for the 16 channels signaling the
02330  * presence of an interrupt request for each channel. Depending on the appropriate bit
02331  * setting in the transfer-control descriptors, the eDMA engine generates an
02332  * interrupt on data transfer completion. The outputs of this register are directly
02333  * routed to the interrupt controller (INTC). During the interrupt-service routine
02334  * associated with any given channel, it is the software's responsibility to
02335  * clear the appropriate bit, negating the interrupt request. Typically, a write to
02336  * the CINT register in the interrupt service routine is used for this purpose.
02337  * The state of any given channel's interrupt request is directly affected by
02338  * writes to this register; it is also affected by writes to the CINT register. On
02339  * writes to INT, a 1 in any bit position clears the corresponding channel's
02340  * interrupt request. A zero in any bit position has no affect on the corresponding
02341  * channel's current interrupt status. The CINT register is provided so the interrupt
02342  * request for a single channel can easily be cleared without the need to
02343  * perform a read-modify-write sequence to the INT register.
02344  */
02345 typedef union _hw_dma_int
02346 {
02347     uint32_t U;
02348     struct _hw_dma_int_bitfields
02349     {
02350         uint32_t INT0 : 1;             /*!< [0] Interrupt Request 0 */
02351         uint32_t INT1 : 1;             /*!< [1] Interrupt Request 1 */
02352         uint32_t INT2 : 1;             /*!< [2] Interrupt Request 2 */
02353         uint32_t INT3 : 1;             /*!< [3] Interrupt Request 3 */
02354         uint32_t INT4 : 1;             /*!< [4] Interrupt Request 4 */
02355         uint32_t INT5 : 1;             /*!< [5] Interrupt Request 5 */
02356         uint32_t INT6 : 1;             /*!< [6] Interrupt Request 6 */
02357         uint32_t INT7 : 1;             /*!< [7] Interrupt Request 7 */
02358         uint32_t INT8 : 1;             /*!< [8] Interrupt Request 8 */
02359         uint32_t INT9 : 1;             /*!< [9] Interrupt Request 9 */
02360         uint32_t INT10 : 1;            /*!< [10] Interrupt Request 10 */
02361         uint32_t INT11 : 1;            /*!< [11] Interrupt Request 11 */
02362         uint32_t INT12 : 1;            /*!< [12] Interrupt Request 12 */
02363         uint32_t INT13 : 1;            /*!< [13] Interrupt Request 13 */
02364         uint32_t INT14 : 1;            /*!< [14] Interrupt Request 14 */
02365         uint32_t INT15 : 1;            /*!< [15] Interrupt Request 15 */
02366         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
02367     } B;
02368 } hw_dma_int_t;
02369 
02370 /*!
02371  * @name Constants and macros for entire DMA_INT register
02372  */
02373 /*@{*/
02374 #define HW_DMA_INT_ADDR(x)       ((x) + 0x24U)
02375 
02376 #define HW_DMA_INT(x)            (*(__IO hw_dma_int_t *) HW_DMA_INT_ADDR(x))
02377 #define HW_DMA_INT_RD(x)         (ADDRESS_READ(hw_dma_int_t, HW_DMA_INT_ADDR(x)))
02378 #define HW_DMA_INT_WR(x, v)      (ADDRESS_WRITE(hw_dma_int_t, HW_DMA_INT_ADDR(x), v))
02379 #define HW_DMA_INT_SET(x, v)     (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) |  (v)))
02380 #define HW_DMA_INT_CLR(x, v)     (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
02381 #define HW_DMA_INT_TOG(x, v)     (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^  (v)))
02382 /*@}*/
02383 
02384 /*
02385  * Constants & macros for individual DMA_INT bitfields
02386  */
02387 
02388 /*!
02389  * @name Register DMA_INT, field INT0[0] (W1C)
02390  *
02391  * Values:
02392  * - 0 - The interrupt request for corresponding channel is cleared
02393  * - 1 - The interrupt request for corresponding channel is active
02394  */
02395 /*@{*/
02396 #define BP_DMA_INT_INT0      (0U)          /*!< Bit position for DMA_INT_INT0. */
02397 #define BM_DMA_INT_INT0      (0x00000001U) /*!< Bit mask for DMA_INT_INT0. */
02398 #define BS_DMA_INT_INT0      (1U)          /*!< Bit field size in bits for DMA_INT_INT0. */
02399 
02400 /*! @brief Read current value of the DMA_INT_INT0 field. */
02401 #define BR_DMA_INT_INT0(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0)))
02402 
02403 /*! @brief Format value for bitfield DMA_INT_INT0. */
02404 #define BF_DMA_INT_INT0(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT0) & BM_DMA_INT_INT0)
02405 
02406 /*! @brief Set the INT0 field to a new value. */
02407 #define BW_DMA_INT_INT0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0), v))
02408 /*@}*/
02409 
02410 /*!
02411  * @name Register DMA_INT, field INT1[1] (W1C)
02412  *
02413  * Values:
02414  * - 0 - The interrupt request for corresponding channel is cleared
02415  * - 1 - The interrupt request for corresponding channel is active
02416  */
02417 /*@{*/
02418 #define BP_DMA_INT_INT1      (1U)          /*!< Bit position for DMA_INT_INT1. */
02419 #define BM_DMA_INT_INT1      (0x00000002U) /*!< Bit mask for DMA_INT_INT1. */
02420 #define BS_DMA_INT_INT1      (1U)          /*!< Bit field size in bits for DMA_INT_INT1. */
02421 
02422 /*! @brief Read current value of the DMA_INT_INT1 field. */
02423 #define BR_DMA_INT_INT1(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1)))
02424 
02425 /*! @brief Format value for bitfield DMA_INT_INT1. */
02426 #define BF_DMA_INT_INT1(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT1) & BM_DMA_INT_INT1)
02427 
02428 /*! @brief Set the INT1 field to a new value. */
02429 #define BW_DMA_INT_INT1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1), v))
02430 /*@}*/
02431 
02432 /*!
02433  * @name Register DMA_INT, field INT2[2] (W1C)
02434  *
02435  * Values:
02436  * - 0 - The interrupt request for corresponding channel is cleared
02437  * - 1 - The interrupt request for corresponding channel is active
02438  */
02439 /*@{*/
02440 #define BP_DMA_INT_INT2      (2U)          /*!< Bit position for DMA_INT_INT2. */
02441 #define BM_DMA_INT_INT2      (0x00000004U) /*!< Bit mask for DMA_INT_INT2. */
02442 #define BS_DMA_INT_INT2      (1U)          /*!< Bit field size in bits for DMA_INT_INT2. */
02443 
02444 /*! @brief Read current value of the DMA_INT_INT2 field. */
02445 #define BR_DMA_INT_INT2(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2)))
02446 
02447 /*! @brief Format value for bitfield DMA_INT_INT2. */
02448 #define BF_DMA_INT_INT2(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT2) & BM_DMA_INT_INT2)
02449 
02450 /*! @brief Set the INT2 field to a new value. */
02451 #define BW_DMA_INT_INT2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2), v))
02452 /*@}*/
02453 
02454 /*!
02455  * @name Register DMA_INT, field INT3[3] (W1C)
02456  *
02457  * Values:
02458  * - 0 - The interrupt request for corresponding channel is cleared
02459  * - 1 - The interrupt request for corresponding channel is active
02460  */
02461 /*@{*/
02462 #define BP_DMA_INT_INT3      (3U)          /*!< Bit position for DMA_INT_INT3. */
02463 #define BM_DMA_INT_INT3      (0x00000008U) /*!< Bit mask for DMA_INT_INT3. */
02464 #define BS_DMA_INT_INT3      (1U)          /*!< Bit field size in bits for DMA_INT_INT3. */
02465 
02466 /*! @brief Read current value of the DMA_INT_INT3 field. */
02467 #define BR_DMA_INT_INT3(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3)))
02468 
02469 /*! @brief Format value for bitfield DMA_INT_INT3. */
02470 #define BF_DMA_INT_INT3(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT3) & BM_DMA_INT_INT3)
02471 
02472 /*! @brief Set the INT3 field to a new value. */
02473 #define BW_DMA_INT_INT3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3), v))
02474 /*@}*/
02475 
02476 /*!
02477  * @name Register DMA_INT, field INT4[4] (W1C)
02478  *
02479  * Values:
02480  * - 0 - The interrupt request for corresponding channel is cleared
02481  * - 1 - The interrupt request for corresponding channel is active
02482  */
02483 /*@{*/
02484 #define BP_DMA_INT_INT4      (4U)          /*!< Bit position for DMA_INT_INT4. */
02485 #define BM_DMA_INT_INT4      (0x00000010U) /*!< Bit mask for DMA_INT_INT4. */
02486 #define BS_DMA_INT_INT4      (1U)          /*!< Bit field size in bits for DMA_INT_INT4. */
02487 
02488 /*! @brief Read current value of the DMA_INT_INT4 field. */
02489 #define BR_DMA_INT_INT4(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4)))
02490 
02491 /*! @brief Format value for bitfield DMA_INT_INT4. */
02492 #define BF_DMA_INT_INT4(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT4) & BM_DMA_INT_INT4)
02493 
02494 /*! @brief Set the INT4 field to a new value. */
02495 #define BW_DMA_INT_INT4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4), v))
02496 /*@}*/
02497 
02498 /*!
02499  * @name Register DMA_INT, field INT5[5] (W1C)
02500  *
02501  * Values:
02502  * - 0 - The interrupt request for corresponding channel is cleared
02503  * - 1 - The interrupt request for corresponding channel is active
02504  */
02505 /*@{*/
02506 #define BP_DMA_INT_INT5      (5U)          /*!< Bit position for DMA_INT_INT5. */
02507 #define BM_DMA_INT_INT5      (0x00000020U) /*!< Bit mask for DMA_INT_INT5. */
02508 #define BS_DMA_INT_INT5      (1U)          /*!< Bit field size in bits for DMA_INT_INT5. */
02509 
02510 /*! @brief Read current value of the DMA_INT_INT5 field. */
02511 #define BR_DMA_INT_INT5(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5)))
02512 
02513 /*! @brief Format value for bitfield DMA_INT_INT5. */
02514 #define BF_DMA_INT_INT5(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT5) & BM_DMA_INT_INT5)
02515 
02516 /*! @brief Set the INT5 field to a new value. */
02517 #define BW_DMA_INT_INT5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5), v))
02518 /*@}*/
02519 
02520 /*!
02521  * @name Register DMA_INT, field INT6[6] (W1C)
02522  *
02523  * Values:
02524  * - 0 - The interrupt request for corresponding channel is cleared
02525  * - 1 - The interrupt request for corresponding channel is active
02526  */
02527 /*@{*/
02528 #define BP_DMA_INT_INT6      (6U)          /*!< Bit position for DMA_INT_INT6. */
02529 #define BM_DMA_INT_INT6      (0x00000040U) /*!< Bit mask for DMA_INT_INT6. */
02530 #define BS_DMA_INT_INT6      (1U)          /*!< Bit field size in bits for DMA_INT_INT6. */
02531 
02532 /*! @brief Read current value of the DMA_INT_INT6 field. */
02533 #define BR_DMA_INT_INT6(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6)))
02534 
02535 /*! @brief Format value for bitfield DMA_INT_INT6. */
02536 #define BF_DMA_INT_INT6(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT6) & BM_DMA_INT_INT6)
02537 
02538 /*! @brief Set the INT6 field to a new value. */
02539 #define BW_DMA_INT_INT6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6), v))
02540 /*@}*/
02541 
02542 /*!
02543  * @name Register DMA_INT, field INT7[7] (W1C)
02544  *
02545  * Values:
02546  * - 0 - The interrupt request for corresponding channel is cleared
02547  * - 1 - The interrupt request for corresponding channel is active
02548  */
02549 /*@{*/
02550 #define BP_DMA_INT_INT7      (7U)          /*!< Bit position for DMA_INT_INT7. */
02551 #define BM_DMA_INT_INT7      (0x00000080U) /*!< Bit mask for DMA_INT_INT7. */
02552 #define BS_DMA_INT_INT7      (1U)          /*!< Bit field size in bits for DMA_INT_INT7. */
02553 
02554 /*! @brief Read current value of the DMA_INT_INT7 field. */
02555 #define BR_DMA_INT_INT7(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7)))
02556 
02557 /*! @brief Format value for bitfield DMA_INT_INT7. */
02558 #define BF_DMA_INT_INT7(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT7) & BM_DMA_INT_INT7)
02559 
02560 /*! @brief Set the INT7 field to a new value. */
02561 #define BW_DMA_INT_INT7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7), v))
02562 /*@}*/
02563 
02564 /*!
02565  * @name Register DMA_INT, field INT8[8] (W1C)
02566  *
02567  * Values:
02568  * - 0 - The interrupt request for corresponding channel is cleared
02569  * - 1 - The interrupt request for corresponding channel is active
02570  */
02571 /*@{*/
02572 #define BP_DMA_INT_INT8      (8U)          /*!< Bit position for DMA_INT_INT8. */
02573 #define BM_DMA_INT_INT8      (0x00000100U) /*!< Bit mask for DMA_INT_INT8. */
02574 #define BS_DMA_INT_INT8      (1U)          /*!< Bit field size in bits for DMA_INT_INT8. */
02575 
02576 /*! @brief Read current value of the DMA_INT_INT8 field. */
02577 #define BR_DMA_INT_INT8(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8)))
02578 
02579 /*! @brief Format value for bitfield DMA_INT_INT8. */
02580 #define BF_DMA_INT_INT8(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT8) & BM_DMA_INT_INT8)
02581 
02582 /*! @brief Set the INT8 field to a new value. */
02583 #define BW_DMA_INT_INT8(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8), v))
02584 /*@}*/
02585 
02586 /*!
02587  * @name Register DMA_INT, field INT9[9] (W1C)
02588  *
02589  * Values:
02590  * - 0 - The interrupt request for corresponding channel is cleared
02591  * - 1 - The interrupt request for corresponding channel is active
02592  */
02593 /*@{*/
02594 #define BP_DMA_INT_INT9      (9U)          /*!< Bit position for DMA_INT_INT9. */
02595 #define BM_DMA_INT_INT9      (0x00000200U) /*!< Bit mask for DMA_INT_INT9. */
02596 #define BS_DMA_INT_INT9      (1U)          /*!< Bit field size in bits for DMA_INT_INT9. */
02597 
02598 /*! @brief Read current value of the DMA_INT_INT9 field. */
02599 #define BR_DMA_INT_INT9(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9)))
02600 
02601 /*! @brief Format value for bitfield DMA_INT_INT9. */
02602 #define BF_DMA_INT_INT9(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT9) & BM_DMA_INT_INT9)
02603 
02604 /*! @brief Set the INT9 field to a new value. */
02605 #define BW_DMA_INT_INT9(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9), v))
02606 /*@}*/
02607 
02608 /*!
02609  * @name Register DMA_INT, field INT10[10] (W1C)
02610  *
02611  * Values:
02612  * - 0 - The interrupt request for corresponding channel is cleared
02613  * - 1 - The interrupt request for corresponding channel is active
02614  */
02615 /*@{*/
02616 #define BP_DMA_INT_INT10     (10U)         /*!< Bit position for DMA_INT_INT10. */
02617 #define BM_DMA_INT_INT10     (0x00000400U) /*!< Bit mask for DMA_INT_INT10. */
02618 #define BS_DMA_INT_INT10     (1U)          /*!< Bit field size in bits for DMA_INT_INT10. */
02619 
02620 /*! @brief Read current value of the DMA_INT_INT10 field. */
02621 #define BR_DMA_INT_INT10(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10)))
02622 
02623 /*! @brief Format value for bitfield DMA_INT_INT10. */
02624 #define BF_DMA_INT_INT10(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT10) & BM_DMA_INT_INT10)
02625 
02626 /*! @brief Set the INT10 field to a new value. */
02627 #define BW_DMA_INT_INT10(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10), v))
02628 /*@}*/
02629 
02630 /*!
02631  * @name Register DMA_INT, field INT11[11] (W1C)
02632  *
02633  * Values:
02634  * - 0 - The interrupt request for corresponding channel is cleared
02635  * - 1 - The interrupt request for corresponding channel is active
02636  */
02637 /*@{*/
02638 #define BP_DMA_INT_INT11     (11U)         /*!< Bit position for DMA_INT_INT11. */
02639 #define BM_DMA_INT_INT11     (0x00000800U) /*!< Bit mask for DMA_INT_INT11. */
02640 #define BS_DMA_INT_INT11     (1U)          /*!< Bit field size in bits for DMA_INT_INT11. */
02641 
02642 /*! @brief Read current value of the DMA_INT_INT11 field. */
02643 #define BR_DMA_INT_INT11(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11)))
02644 
02645 /*! @brief Format value for bitfield DMA_INT_INT11. */
02646 #define BF_DMA_INT_INT11(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT11) & BM_DMA_INT_INT11)
02647 
02648 /*! @brief Set the INT11 field to a new value. */
02649 #define BW_DMA_INT_INT11(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11), v))
02650 /*@}*/
02651 
02652 /*!
02653  * @name Register DMA_INT, field INT12[12] (W1C)
02654  *
02655  * Values:
02656  * - 0 - The interrupt request for corresponding channel is cleared
02657  * - 1 - The interrupt request for corresponding channel is active
02658  */
02659 /*@{*/
02660 #define BP_DMA_INT_INT12     (12U)         /*!< Bit position for DMA_INT_INT12. */
02661 #define BM_DMA_INT_INT12     (0x00001000U) /*!< Bit mask for DMA_INT_INT12. */
02662 #define BS_DMA_INT_INT12     (1U)          /*!< Bit field size in bits for DMA_INT_INT12. */
02663 
02664 /*! @brief Read current value of the DMA_INT_INT12 field. */
02665 #define BR_DMA_INT_INT12(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12)))
02666 
02667 /*! @brief Format value for bitfield DMA_INT_INT12. */
02668 #define BF_DMA_INT_INT12(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT12) & BM_DMA_INT_INT12)
02669 
02670 /*! @brief Set the INT12 field to a new value. */
02671 #define BW_DMA_INT_INT12(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12), v))
02672 /*@}*/
02673 
02674 /*!
02675  * @name Register DMA_INT, field INT13[13] (W1C)
02676  *
02677  * Values:
02678  * - 0 - The interrupt request for corresponding channel is cleared
02679  * - 1 - The interrupt request for corresponding channel is active
02680  */
02681 /*@{*/
02682 #define BP_DMA_INT_INT13     (13U)         /*!< Bit position for DMA_INT_INT13. */
02683 #define BM_DMA_INT_INT13     (0x00002000U) /*!< Bit mask for DMA_INT_INT13. */
02684 #define BS_DMA_INT_INT13     (1U)          /*!< Bit field size in bits for DMA_INT_INT13. */
02685 
02686 /*! @brief Read current value of the DMA_INT_INT13 field. */
02687 #define BR_DMA_INT_INT13(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13)))
02688 
02689 /*! @brief Format value for bitfield DMA_INT_INT13. */
02690 #define BF_DMA_INT_INT13(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT13) & BM_DMA_INT_INT13)
02691 
02692 /*! @brief Set the INT13 field to a new value. */
02693 #define BW_DMA_INT_INT13(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13), v))
02694 /*@}*/
02695 
02696 /*!
02697  * @name Register DMA_INT, field INT14[14] (W1C)
02698  *
02699  * Values:
02700  * - 0 - The interrupt request for corresponding channel is cleared
02701  * - 1 - The interrupt request for corresponding channel is active
02702  */
02703 /*@{*/
02704 #define BP_DMA_INT_INT14     (14U)         /*!< Bit position for DMA_INT_INT14. */
02705 #define BM_DMA_INT_INT14     (0x00004000U) /*!< Bit mask for DMA_INT_INT14. */
02706 #define BS_DMA_INT_INT14     (1U)          /*!< Bit field size in bits for DMA_INT_INT14. */
02707 
02708 /*! @brief Read current value of the DMA_INT_INT14 field. */
02709 #define BR_DMA_INT_INT14(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14)))
02710 
02711 /*! @brief Format value for bitfield DMA_INT_INT14. */
02712 #define BF_DMA_INT_INT14(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT14) & BM_DMA_INT_INT14)
02713 
02714 /*! @brief Set the INT14 field to a new value. */
02715 #define BW_DMA_INT_INT14(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14), v))
02716 /*@}*/
02717 
02718 /*!
02719  * @name Register DMA_INT, field INT15[15] (W1C)
02720  *
02721  * Values:
02722  * - 0 - The interrupt request for corresponding channel is cleared
02723  * - 1 - The interrupt request for corresponding channel is active
02724  */
02725 /*@{*/
02726 #define BP_DMA_INT_INT15     (15U)         /*!< Bit position for DMA_INT_INT15. */
02727 #define BM_DMA_INT_INT15     (0x00008000U) /*!< Bit mask for DMA_INT_INT15. */
02728 #define BS_DMA_INT_INT15     (1U)          /*!< Bit field size in bits for DMA_INT_INT15. */
02729 
02730 /*! @brief Read current value of the DMA_INT_INT15 field. */
02731 #define BR_DMA_INT_INT15(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15)))
02732 
02733 /*! @brief Format value for bitfield DMA_INT_INT15. */
02734 #define BF_DMA_INT_INT15(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_INT_INT15) & BM_DMA_INT_INT15)
02735 
02736 /*! @brief Set the INT15 field to a new value. */
02737 #define BW_DMA_INT_INT15(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15), v))
02738 /*@}*/
02739 
02740 /*******************************************************************************
02741  * HW_DMA_ERR - Error Register
02742  ******************************************************************************/
02743 
02744 /*!
02745  * @brief HW_DMA_ERR - Error Register (RW)
02746  *
02747  * Reset value: 0x00000000U
02748  *
02749  * The ERR provides a bit map for the 16 channels, signaling the presence of an
02750  * error for each channel. The eDMA engine signals the occurrence of an error
02751  * condition by setting the appropriate bit in this register. The outputs of this
02752  * register are enabled by the contents of the EEI, and then routed to the
02753  * interrupt controller. During the execution of the interrupt-service routine associated
02754  * with any DMA errors, it is software's responsibility to clear the appropriate
02755  * bit, negating the error-interrupt request. Typically, a write to the CERR in
02756  * the interrupt-service routine is used for this purpose. The normal DMA channel
02757  * completion indicators (setting the transfer control descriptor DONE flag and
02758  * the possible assertion of an interrupt request) are not affected when an error
02759  * is detected. The contents of this register can also be polled because a
02760  * non-zero value indicates the presence of a channel error regardless of the state of
02761  * the EEI. The state of any given channel's error indicators is affected by
02762  * writes to this register; it is also affected by writes to the CERR. On writes to
02763  * the ERR, a one in any bit position clears the corresponding channel's error
02764  * status. A zero in any bit position has no affect on the corresponding channel's
02765  * current error status. The CERR is provided so the error indicator for a single
02766  * channel can easily be cleared.
02767  */
02768 typedef union _hw_dma_err
02769 {
02770     uint32_t U;
02771     struct _hw_dma_err_bitfields
02772     {
02773         uint32_t ERR0 : 1;             /*!< [0] Error In Channel 0 */
02774         uint32_t ERR1 : 1;             /*!< [1] Error In Channel 1 */
02775         uint32_t ERR2 : 1;             /*!< [2] Error In Channel 2 */
02776         uint32_t ERR3 : 1;             /*!< [3] Error In Channel 3 */
02777         uint32_t ERR4 : 1;             /*!< [4] Error In Channel 4 */
02778         uint32_t ERR5 : 1;             /*!< [5] Error In Channel 5 */
02779         uint32_t ERR6 : 1;             /*!< [6] Error In Channel 6 */
02780         uint32_t ERR7 : 1;             /*!< [7] Error In Channel 7 */
02781         uint32_t ERR8 : 1;             /*!< [8] Error In Channel 8 */
02782         uint32_t ERR9 : 1;             /*!< [9] Error In Channel 9 */
02783         uint32_t ERR10 : 1;            /*!< [10] Error In Channel 10 */
02784         uint32_t ERR11 : 1;            /*!< [11] Error In Channel 11 */
02785         uint32_t ERR12 : 1;            /*!< [12] Error In Channel 12 */
02786         uint32_t ERR13 : 1;            /*!< [13] Error In Channel 13 */
02787         uint32_t ERR14 : 1;            /*!< [14] Error In Channel 14 */
02788         uint32_t ERR15 : 1;            /*!< [15] Error In Channel 15 */
02789         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
02790     } B;
02791 } hw_dma_err_t;
02792 
02793 /*!
02794  * @name Constants and macros for entire DMA_ERR register
02795  */
02796 /*@{*/
02797 #define HW_DMA_ERR_ADDR(x)       ((x) + 0x2CU)
02798 
02799 #define HW_DMA_ERR(x)            (*(__IO hw_dma_err_t *) HW_DMA_ERR_ADDR(x))
02800 #define HW_DMA_ERR_RD(x)         (ADDRESS_READ(hw_dma_err_t, HW_DMA_ERR_ADDR(x)))
02801 #define HW_DMA_ERR_WR(x, v)      (ADDRESS_WRITE(hw_dma_err_t, HW_DMA_ERR_ADDR(x), v))
02802 #define HW_DMA_ERR_SET(x, v)     (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) |  (v)))
02803 #define HW_DMA_ERR_CLR(x, v)     (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
02804 #define HW_DMA_ERR_TOG(x, v)     (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^  (v)))
02805 /*@}*/
02806 
02807 /*
02808  * Constants & macros for individual DMA_ERR bitfields
02809  */
02810 
02811 /*!
02812  * @name Register DMA_ERR, field ERR0[0] (W1C)
02813  *
02814  * Values:
02815  * - 0 - An error in the corresponding channel has not occurred
02816  * - 1 - An error in the corresponding channel has occurred
02817  */
02818 /*@{*/
02819 #define BP_DMA_ERR_ERR0      (0U)          /*!< Bit position for DMA_ERR_ERR0. */
02820 #define BM_DMA_ERR_ERR0      (0x00000001U) /*!< Bit mask for DMA_ERR_ERR0. */
02821 #define BS_DMA_ERR_ERR0      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR0. */
02822 
02823 /*! @brief Read current value of the DMA_ERR_ERR0 field. */
02824 #define BR_DMA_ERR_ERR0(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0)))
02825 
02826 /*! @brief Format value for bitfield DMA_ERR_ERR0. */
02827 #define BF_DMA_ERR_ERR0(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR0) & BM_DMA_ERR_ERR0)
02828 
02829 /*! @brief Set the ERR0 field to a new value. */
02830 #define BW_DMA_ERR_ERR0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0), v))
02831 /*@}*/
02832 
02833 /*!
02834  * @name Register DMA_ERR, field ERR1[1] (W1C)
02835  *
02836  * Values:
02837  * - 0 - An error in the corresponding channel has not occurred
02838  * - 1 - An error in the corresponding channel has occurred
02839  */
02840 /*@{*/
02841 #define BP_DMA_ERR_ERR1      (1U)          /*!< Bit position for DMA_ERR_ERR1. */
02842 #define BM_DMA_ERR_ERR1      (0x00000002U) /*!< Bit mask for DMA_ERR_ERR1. */
02843 #define BS_DMA_ERR_ERR1      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR1. */
02844 
02845 /*! @brief Read current value of the DMA_ERR_ERR1 field. */
02846 #define BR_DMA_ERR_ERR1(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1)))
02847 
02848 /*! @brief Format value for bitfield DMA_ERR_ERR1. */
02849 #define BF_DMA_ERR_ERR1(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR1) & BM_DMA_ERR_ERR1)
02850 
02851 /*! @brief Set the ERR1 field to a new value. */
02852 #define BW_DMA_ERR_ERR1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1), v))
02853 /*@}*/
02854 
02855 /*!
02856  * @name Register DMA_ERR, field ERR2[2] (W1C)
02857  *
02858  * Values:
02859  * - 0 - An error in the corresponding channel has not occurred
02860  * - 1 - An error in the corresponding channel has occurred
02861  */
02862 /*@{*/
02863 #define BP_DMA_ERR_ERR2      (2U)          /*!< Bit position for DMA_ERR_ERR2. */
02864 #define BM_DMA_ERR_ERR2      (0x00000004U) /*!< Bit mask for DMA_ERR_ERR2. */
02865 #define BS_DMA_ERR_ERR2      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR2. */
02866 
02867 /*! @brief Read current value of the DMA_ERR_ERR2 field. */
02868 #define BR_DMA_ERR_ERR2(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2)))
02869 
02870 /*! @brief Format value for bitfield DMA_ERR_ERR2. */
02871 #define BF_DMA_ERR_ERR2(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR2) & BM_DMA_ERR_ERR2)
02872 
02873 /*! @brief Set the ERR2 field to a new value. */
02874 #define BW_DMA_ERR_ERR2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2), v))
02875 /*@}*/
02876 
02877 /*!
02878  * @name Register DMA_ERR, field ERR3[3] (W1C)
02879  *
02880  * Values:
02881  * - 0 - An error in the corresponding channel has not occurred
02882  * - 1 - An error in the corresponding channel has occurred
02883  */
02884 /*@{*/
02885 #define BP_DMA_ERR_ERR3      (3U)          /*!< Bit position for DMA_ERR_ERR3. */
02886 #define BM_DMA_ERR_ERR3      (0x00000008U) /*!< Bit mask for DMA_ERR_ERR3. */
02887 #define BS_DMA_ERR_ERR3      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR3. */
02888 
02889 /*! @brief Read current value of the DMA_ERR_ERR3 field. */
02890 #define BR_DMA_ERR_ERR3(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3)))
02891 
02892 /*! @brief Format value for bitfield DMA_ERR_ERR3. */
02893 #define BF_DMA_ERR_ERR3(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR3) & BM_DMA_ERR_ERR3)
02894 
02895 /*! @brief Set the ERR3 field to a new value. */
02896 #define BW_DMA_ERR_ERR3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3), v))
02897 /*@}*/
02898 
02899 /*!
02900  * @name Register DMA_ERR, field ERR4[4] (W1C)
02901  *
02902  * Values:
02903  * - 0 - An error in the corresponding channel has not occurred
02904  * - 1 - An error in the corresponding channel has occurred
02905  */
02906 /*@{*/
02907 #define BP_DMA_ERR_ERR4      (4U)          /*!< Bit position for DMA_ERR_ERR4. */
02908 #define BM_DMA_ERR_ERR4      (0x00000010U) /*!< Bit mask for DMA_ERR_ERR4. */
02909 #define BS_DMA_ERR_ERR4      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR4. */
02910 
02911 /*! @brief Read current value of the DMA_ERR_ERR4 field. */
02912 #define BR_DMA_ERR_ERR4(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4)))
02913 
02914 /*! @brief Format value for bitfield DMA_ERR_ERR4. */
02915 #define BF_DMA_ERR_ERR4(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR4) & BM_DMA_ERR_ERR4)
02916 
02917 /*! @brief Set the ERR4 field to a new value. */
02918 #define BW_DMA_ERR_ERR4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4), v))
02919 /*@}*/
02920 
02921 /*!
02922  * @name Register DMA_ERR, field ERR5[5] (W1C)
02923  *
02924  * Values:
02925  * - 0 - An error in the corresponding channel has not occurred
02926  * - 1 - An error in the corresponding channel has occurred
02927  */
02928 /*@{*/
02929 #define BP_DMA_ERR_ERR5      (5U)          /*!< Bit position for DMA_ERR_ERR5. */
02930 #define BM_DMA_ERR_ERR5      (0x00000020U) /*!< Bit mask for DMA_ERR_ERR5. */
02931 #define BS_DMA_ERR_ERR5      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR5. */
02932 
02933 /*! @brief Read current value of the DMA_ERR_ERR5 field. */
02934 #define BR_DMA_ERR_ERR5(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5)))
02935 
02936 /*! @brief Format value for bitfield DMA_ERR_ERR5. */
02937 #define BF_DMA_ERR_ERR5(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR5) & BM_DMA_ERR_ERR5)
02938 
02939 /*! @brief Set the ERR5 field to a new value. */
02940 #define BW_DMA_ERR_ERR5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5), v))
02941 /*@}*/
02942 
02943 /*!
02944  * @name Register DMA_ERR, field ERR6[6] (W1C)
02945  *
02946  * Values:
02947  * - 0 - An error in the corresponding channel has not occurred
02948  * - 1 - An error in the corresponding channel has occurred
02949  */
02950 /*@{*/
02951 #define BP_DMA_ERR_ERR6      (6U)          /*!< Bit position for DMA_ERR_ERR6. */
02952 #define BM_DMA_ERR_ERR6      (0x00000040U) /*!< Bit mask for DMA_ERR_ERR6. */
02953 #define BS_DMA_ERR_ERR6      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR6. */
02954 
02955 /*! @brief Read current value of the DMA_ERR_ERR6 field. */
02956 #define BR_DMA_ERR_ERR6(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6)))
02957 
02958 /*! @brief Format value for bitfield DMA_ERR_ERR6. */
02959 #define BF_DMA_ERR_ERR6(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR6) & BM_DMA_ERR_ERR6)
02960 
02961 /*! @brief Set the ERR6 field to a new value. */
02962 #define BW_DMA_ERR_ERR6(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6), v))
02963 /*@}*/
02964 
02965 /*!
02966  * @name Register DMA_ERR, field ERR7[7] (W1C)
02967  *
02968  * Values:
02969  * - 0 - An error in the corresponding channel has not occurred
02970  * - 1 - An error in the corresponding channel has occurred
02971  */
02972 /*@{*/
02973 #define BP_DMA_ERR_ERR7      (7U)          /*!< Bit position for DMA_ERR_ERR7. */
02974 #define BM_DMA_ERR_ERR7      (0x00000080U) /*!< Bit mask for DMA_ERR_ERR7. */
02975 #define BS_DMA_ERR_ERR7      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR7. */
02976 
02977 /*! @brief Read current value of the DMA_ERR_ERR7 field. */
02978 #define BR_DMA_ERR_ERR7(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7)))
02979 
02980 /*! @brief Format value for bitfield DMA_ERR_ERR7. */
02981 #define BF_DMA_ERR_ERR7(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR7) & BM_DMA_ERR_ERR7)
02982 
02983 /*! @brief Set the ERR7 field to a new value. */
02984 #define BW_DMA_ERR_ERR7(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7), v))
02985 /*@}*/
02986 
02987 /*!
02988  * @name Register DMA_ERR, field ERR8[8] (W1C)
02989  *
02990  * Values:
02991  * - 0 - An error in the corresponding channel has not occurred
02992  * - 1 - An error in the corresponding channel has occurred
02993  */
02994 /*@{*/
02995 #define BP_DMA_ERR_ERR8      (8U)          /*!< Bit position for DMA_ERR_ERR8. */
02996 #define BM_DMA_ERR_ERR8      (0x00000100U) /*!< Bit mask for DMA_ERR_ERR8. */
02997 #define BS_DMA_ERR_ERR8      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR8. */
02998 
02999 /*! @brief Read current value of the DMA_ERR_ERR8 field. */
03000 #define BR_DMA_ERR_ERR8(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8)))
03001 
03002 /*! @brief Format value for bitfield DMA_ERR_ERR8. */
03003 #define BF_DMA_ERR_ERR8(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR8) & BM_DMA_ERR_ERR8)
03004 
03005 /*! @brief Set the ERR8 field to a new value. */
03006 #define BW_DMA_ERR_ERR8(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8), v))
03007 /*@}*/
03008 
03009 /*!
03010  * @name Register DMA_ERR, field ERR9[9] (W1C)
03011  *
03012  * Values:
03013  * - 0 - An error in the corresponding channel has not occurred
03014  * - 1 - An error in the corresponding channel has occurred
03015  */
03016 /*@{*/
03017 #define BP_DMA_ERR_ERR9      (9U)          /*!< Bit position for DMA_ERR_ERR9. */
03018 #define BM_DMA_ERR_ERR9      (0x00000200U) /*!< Bit mask for DMA_ERR_ERR9. */
03019 #define BS_DMA_ERR_ERR9      (1U)          /*!< Bit field size in bits for DMA_ERR_ERR9. */
03020 
03021 /*! @brief Read current value of the DMA_ERR_ERR9 field. */
03022 #define BR_DMA_ERR_ERR9(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9)))
03023 
03024 /*! @brief Format value for bitfield DMA_ERR_ERR9. */
03025 #define BF_DMA_ERR_ERR9(v)   ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR9) & BM_DMA_ERR_ERR9)
03026 
03027 /*! @brief Set the ERR9 field to a new value. */
03028 #define BW_DMA_ERR_ERR9(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9), v))
03029 /*@}*/
03030 
03031 /*!
03032  * @name Register DMA_ERR, field ERR10[10] (W1C)
03033  *
03034  * Values:
03035  * - 0 - An error in the corresponding channel has not occurred
03036  * - 1 - An error in the corresponding channel has occurred
03037  */
03038 /*@{*/
03039 #define BP_DMA_ERR_ERR10     (10U)         /*!< Bit position for DMA_ERR_ERR10. */
03040 #define BM_DMA_ERR_ERR10     (0x00000400U) /*!< Bit mask for DMA_ERR_ERR10. */
03041 #define BS_DMA_ERR_ERR10     (1U)          /*!< Bit field size in bits for DMA_ERR_ERR10. */
03042 
03043 /*! @brief Read current value of the DMA_ERR_ERR10 field. */
03044 #define BR_DMA_ERR_ERR10(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10)))
03045 
03046 /*! @brief Format value for bitfield DMA_ERR_ERR10. */
03047 #define BF_DMA_ERR_ERR10(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR10) & BM_DMA_ERR_ERR10)
03048 
03049 /*! @brief Set the ERR10 field to a new value. */
03050 #define BW_DMA_ERR_ERR10(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10), v))
03051 /*@}*/
03052 
03053 /*!
03054  * @name Register DMA_ERR, field ERR11[11] (W1C)
03055  *
03056  * Values:
03057  * - 0 - An error in the corresponding channel has not occurred
03058  * - 1 - An error in the corresponding channel has occurred
03059  */
03060 /*@{*/
03061 #define BP_DMA_ERR_ERR11     (11U)         /*!< Bit position for DMA_ERR_ERR11. */
03062 #define BM_DMA_ERR_ERR11     (0x00000800U) /*!< Bit mask for DMA_ERR_ERR11. */
03063 #define BS_DMA_ERR_ERR11     (1U)          /*!< Bit field size in bits for DMA_ERR_ERR11. */
03064 
03065 /*! @brief Read current value of the DMA_ERR_ERR11 field. */
03066 #define BR_DMA_ERR_ERR11(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11)))
03067 
03068 /*! @brief Format value for bitfield DMA_ERR_ERR11. */
03069 #define BF_DMA_ERR_ERR11(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR11) & BM_DMA_ERR_ERR11)
03070 
03071 /*! @brief Set the ERR11 field to a new value. */
03072 #define BW_DMA_ERR_ERR11(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11), v))
03073 /*@}*/
03074 
03075 /*!
03076  * @name Register DMA_ERR, field ERR12[12] (W1C)
03077  *
03078  * Values:
03079  * - 0 - An error in the corresponding channel has not occurred
03080  * - 1 - An error in the corresponding channel has occurred
03081  */
03082 /*@{*/
03083 #define BP_DMA_ERR_ERR12     (12U)         /*!< Bit position for DMA_ERR_ERR12. */
03084 #define BM_DMA_ERR_ERR12     (0x00001000U) /*!< Bit mask for DMA_ERR_ERR12. */
03085 #define BS_DMA_ERR_ERR12     (1U)          /*!< Bit field size in bits for DMA_ERR_ERR12. */
03086 
03087 /*! @brief Read current value of the DMA_ERR_ERR12 field. */
03088 #define BR_DMA_ERR_ERR12(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12)))
03089 
03090 /*! @brief Format value for bitfield DMA_ERR_ERR12. */
03091 #define BF_DMA_ERR_ERR12(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR12) & BM_DMA_ERR_ERR12)
03092 
03093 /*! @brief Set the ERR12 field to a new value. */
03094 #define BW_DMA_ERR_ERR12(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12), v))
03095 /*@}*/
03096 
03097 /*!
03098  * @name Register DMA_ERR, field ERR13[13] (W1C)
03099  *
03100  * Values:
03101  * - 0 - An error in the corresponding channel has not occurred
03102  * - 1 - An error in the corresponding channel has occurred
03103  */
03104 /*@{*/
03105 #define BP_DMA_ERR_ERR13     (13U)         /*!< Bit position for DMA_ERR_ERR13. */
03106 #define BM_DMA_ERR_ERR13     (0x00002000U) /*!< Bit mask for DMA_ERR_ERR13. */
03107 #define BS_DMA_ERR_ERR13     (1U)          /*!< Bit field size in bits for DMA_ERR_ERR13. */
03108 
03109 /*! @brief Read current value of the DMA_ERR_ERR13 field. */
03110 #define BR_DMA_ERR_ERR13(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13)))
03111 
03112 /*! @brief Format value for bitfield DMA_ERR_ERR13. */
03113 #define BF_DMA_ERR_ERR13(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR13) & BM_DMA_ERR_ERR13)
03114 
03115 /*! @brief Set the ERR13 field to a new value. */
03116 #define BW_DMA_ERR_ERR13(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13), v))
03117 /*@}*/
03118 
03119 /*!
03120  * @name Register DMA_ERR, field ERR14[14] (W1C)
03121  *
03122  * Values:
03123  * - 0 - An error in the corresponding channel has not occurred
03124  * - 1 - An error in the corresponding channel has occurred
03125  */
03126 /*@{*/
03127 #define BP_DMA_ERR_ERR14     (14U)         /*!< Bit position for DMA_ERR_ERR14. */
03128 #define BM_DMA_ERR_ERR14     (0x00004000U) /*!< Bit mask for DMA_ERR_ERR14. */
03129 #define BS_DMA_ERR_ERR14     (1U)          /*!< Bit field size in bits for DMA_ERR_ERR14. */
03130 
03131 /*! @brief Read current value of the DMA_ERR_ERR14 field. */
03132 #define BR_DMA_ERR_ERR14(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14)))
03133 
03134 /*! @brief Format value for bitfield DMA_ERR_ERR14. */
03135 #define BF_DMA_ERR_ERR14(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR14) & BM_DMA_ERR_ERR14)
03136 
03137 /*! @brief Set the ERR14 field to a new value. */
03138 #define BW_DMA_ERR_ERR14(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14), v))
03139 /*@}*/
03140 
03141 /*!
03142  * @name Register DMA_ERR, field ERR15[15] (W1C)
03143  *
03144  * Values:
03145  * - 0 - An error in the corresponding channel has not occurred
03146  * - 1 - An error in the corresponding channel has occurred
03147  */
03148 /*@{*/
03149 #define BP_DMA_ERR_ERR15     (15U)         /*!< Bit position for DMA_ERR_ERR15. */
03150 #define BM_DMA_ERR_ERR15     (0x00008000U) /*!< Bit mask for DMA_ERR_ERR15. */
03151 #define BS_DMA_ERR_ERR15     (1U)          /*!< Bit field size in bits for DMA_ERR_ERR15. */
03152 
03153 /*! @brief Read current value of the DMA_ERR_ERR15 field. */
03154 #define BR_DMA_ERR_ERR15(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15)))
03155 
03156 /*! @brief Format value for bitfield DMA_ERR_ERR15. */
03157 #define BF_DMA_ERR_ERR15(v)  ((uint32_t)((uint32_t)(v) << BP_DMA_ERR_ERR15) & BM_DMA_ERR_ERR15)
03158 
03159 /*! @brief Set the ERR15 field to a new value. */
03160 #define BW_DMA_ERR_ERR15(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15), v))
03161 /*@}*/
03162 
03163 /*******************************************************************************
03164  * HW_DMA_HRS - Hardware Request Status Register
03165  ******************************************************************************/
03166 
03167 /*!
03168  * @brief HW_DMA_HRS - Hardware Request Status Register (RO)
03169  *
03170  * Reset value: 0x00000000U
03171  *
03172  * The HRS register provides a bit map for the DMA channels, signaling the
03173  * presence of a hardware request for each channel. The hardware request status bits
03174  * reflect the current state of the register and qualified (via the ERQ fields)
03175  * DMA request signals as seen by the DMA's arbitration logic. This view into the
03176  * hardware request signals may be used for debug purposes. These bits reflect the
03177  * state of the request as seen by the arbitration logic. Therefore, this status
03178  * is affected by the ERQ bits.
03179  */
03180 typedef union _hw_dma_hrs
03181 {
03182     uint32_t U;
03183     struct _hw_dma_hrs_bitfields
03184     {
03185         uint32_t HRS0 : 1;             /*!< [0] Hardware Request Status Channel 0 */
03186         uint32_t HRS1 : 1;             /*!< [1] Hardware Request Status Channel 1 */
03187         uint32_t HRS2 : 1;             /*!< [2] Hardware Request Status Channel 2 */
03188         uint32_t HRS3 : 1;             /*!< [3] Hardware Request Status Channel 3 */
03189         uint32_t HRS4 : 1;             /*!< [4] Hardware Request Status Channel 4 */
03190         uint32_t HRS5 : 1;             /*!< [5] Hardware Request Status Channel 5 */
03191         uint32_t HRS6 : 1;             /*!< [6] Hardware Request Status Channel 6 */
03192         uint32_t HRS7 : 1;             /*!< [7] Hardware Request Status Channel 7 */
03193         uint32_t HRS8 : 1;             /*!< [8] Hardware Request Status Channel 8 */
03194         uint32_t HRS9 : 1;             /*!< [9] Hardware Request Status Channel 9 */
03195         uint32_t HRS10 : 1;            /*!< [10] Hardware Request Status Channel 10 */
03196         uint32_t HRS11 : 1;            /*!< [11] Hardware Request Status Channel 11 */
03197         uint32_t HRS12 : 1;            /*!< [12] Hardware Request Status Channel 12 */
03198         uint32_t HRS13 : 1;            /*!< [13] Hardware Request Status Channel 13 */
03199         uint32_t HRS14 : 1;            /*!< [14] Hardware Request Status Channel 14 */
03200         uint32_t HRS15 : 1;            /*!< [15] Hardware Request Status Channel 15 */
03201         uint32_t RESERVED0 : 16;       /*!< [31:16] Reserved */
03202     } B;
03203 } hw_dma_hrs_t;
03204 
03205 /*!
03206  * @name Constants and macros for entire DMA_HRS register
03207  */
03208 /*@{*/
03209 #define HW_DMA_HRS_ADDR(x)       ((x) + 0x34U)
03210 
03211 #define HW_DMA_HRS(x)            (*(__I hw_dma_hrs_t *) HW_DMA_HRS_ADDR(x))
03212 #define HW_DMA_HRS_RD(x)         (ADDRESS_READ(hw_dma_hrs_t, HW_DMA_HRS_ADDR(x)))
03213 /*@}*/
03214 
03215 /*
03216  * Constants & macros for individual DMA_HRS bitfields
03217  */
03218 
03219 /*!
03220  * @name Register DMA_HRS, field HRS0[0] (RO)
03221  *
03222  * The HRS bit for its respective channel remains asserted for the period when a
03223  * Hardware Request is Present on the Channel. After the Request is completed
03224  * and Channel is free , the HRS bit is automatically cleared by hardware.
03225  *
03226  * Values:
03227  * - 0 - A hardware service request for channel 0 is not present
03228  * - 1 - A hardware service request for channel 0 is present
03229  */
03230 /*@{*/
03231 #define BP_DMA_HRS_HRS0      (0U)          /*!< Bit position for DMA_HRS_HRS0. */
03232 #define BM_DMA_HRS_HRS0      (0x00000001U) /*!< Bit mask for DMA_HRS_HRS0. */
03233 #define BS_DMA_HRS_HRS0      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS0. */
03234 
03235 /*! @brief Read current value of the DMA_HRS_HRS0 field. */
03236 #define BR_DMA_HRS_HRS0(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0)))
03237 /*@}*/
03238 
03239 /*!
03240  * @name Register DMA_HRS, field HRS1[1] (RO)
03241  *
03242  * The HRS bit for its respective channel remains asserted for the period when a
03243  * Hardware Request is Present on the Channel. After the Request is completed
03244  * and Channel is free , the HRS bit is automatically cleared by hardware.
03245  *
03246  * Values:
03247  * - 0 - A hardware service request for channel 1 is not present
03248  * - 1 - A hardware service request for channel 1 is present
03249  */
03250 /*@{*/
03251 #define BP_DMA_HRS_HRS1      (1U)          /*!< Bit position for DMA_HRS_HRS1. */
03252 #define BM_DMA_HRS_HRS1      (0x00000002U) /*!< Bit mask for DMA_HRS_HRS1. */
03253 #define BS_DMA_HRS_HRS1      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS1. */
03254 
03255 /*! @brief Read current value of the DMA_HRS_HRS1 field. */
03256 #define BR_DMA_HRS_HRS1(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1)))
03257 /*@}*/
03258 
03259 /*!
03260  * @name Register DMA_HRS, field HRS2[2] (RO)
03261  *
03262  * The HRS bit for its respective channel remains asserted for the period when a
03263  * Hardware Request is Present on the Channel. After the Request is completed
03264  * and Channel is free , the HRS bit is automatically cleared by hardware.
03265  *
03266  * Values:
03267  * - 0 - A hardware service request for channel 2 is not present
03268  * - 1 - A hardware service request for channel 2 is present
03269  */
03270 /*@{*/
03271 #define BP_DMA_HRS_HRS2      (2U)          /*!< Bit position for DMA_HRS_HRS2. */
03272 #define BM_DMA_HRS_HRS2      (0x00000004U) /*!< Bit mask for DMA_HRS_HRS2. */
03273 #define BS_DMA_HRS_HRS2      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS2. */
03274 
03275 /*! @brief Read current value of the DMA_HRS_HRS2 field. */
03276 #define BR_DMA_HRS_HRS2(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2)))
03277 /*@}*/
03278 
03279 /*!
03280  * @name Register DMA_HRS, field HRS3[3] (RO)
03281  *
03282  * The HRS bit for its respective channel remains asserted for the period when a
03283  * Hardware Request is Present on the Channel. After the Request is completed
03284  * and Channel is free , the HRS bit is automatically cleared by hardware.
03285  *
03286  * Values:
03287  * - 0 - A hardware service request for channel 3 is not present
03288  * - 1 - A hardware service request for channel 3 is present
03289  */
03290 /*@{*/
03291 #define BP_DMA_HRS_HRS3      (3U)          /*!< Bit position for DMA_HRS_HRS3. */
03292 #define BM_DMA_HRS_HRS3      (0x00000008U) /*!< Bit mask for DMA_HRS_HRS3. */
03293 #define BS_DMA_HRS_HRS3      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS3. */
03294 
03295 /*! @brief Read current value of the DMA_HRS_HRS3 field. */
03296 #define BR_DMA_HRS_HRS3(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3)))
03297 /*@}*/
03298 
03299 /*!
03300  * @name Register DMA_HRS, field HRS4[4] (RO)
03301  *
03302  * The HRS bit for its respective channel remains asserted for the period when a
03303  * Hardware Request is Present on the Channel. After the Request is completed
03304  * and Channel is free , the HRS bit is automatically cleared by hardware.
03305  *
03306  * Values:
03307  * - 0 - A hardware service request for channel 4 is not present
03308  * - 1 - A hardware service request for channel 4 is present
03309  */
03310 /*@{*/
03311 #define BP_DMA_HRS_HRS4      (4U)          /*!< Bit position for DMA_HRS_HRS4. */
03312 #define BM_DMA_HRS_HRS4      (0x00000010U) /*!< Bit mask for DMA_HRS_HRS4. */
03313 #define BS_DMA_HRS_HRS4      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS4. */
03314 
03315 /*! @brief Read current value of the DMA_HRS_HRS4 field. */
03316 #define BR_DMA_HRS_HRS4(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4)))
03317 /*@}*/
03318 
03319 /*!
03320  * @name Register DMA_HRS, field HRS5[5] (RO)
03321  *
03322  * The HRS bit for its respective channel remains asserted for the period when a
03323  * Hardware Request is Present on the Channel. After the Request is completed
03324  * and Channel is free , the HRS bit is automatically cleared by hardware.
03325  *
03326  * Values:
03327  * - 0 - A hardware service request for channel 5 is not present
03328  * - 1 - A hardware service request for channel 5 is present
03329  */
03330 /*@{*/
03331 #define BP_DMA_HRS_HRS5      (5U)          /*!< Bit position for DMA_HRS_HRS5. */
03332 #define BM_DMA_HRS_HRS5      (0x00000020U) /*!< Bit mask for DMA_HRS_HRS5. */
03333 #define BS_DMA_HRS_HRS5      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS5. */
03334 
03335 /*! @brief Read current value of the DMA_HRS_HRS5 field. */
03336 #define BR_DMA_HRS_HRS5(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5)))
03337 /*@}*/
03338 
03339 /*!
03340  * @name Register DMA_HRS, field HRS6[6] (RO)
03341  *
03342  * The HRS bit for its respective channel remains asserted for the period when a
03343  * Hardware Request is Present on the Channel. After the Request is completed
03344  * and Channel is free , the HRS bit is automatically cleared by hardware.
03345  *
03346  * Values:
03347  * - 0 - A hardware service request for channel 6 is not present
03348  * - 1 - A hardware service request for channel 6 is present
03349  */
03350 /*@{*/
03351 #define BP_DMA_HRS_HRS6      (6U)          /*!< Bit position for DMA_HRS_HRS6. */
03352 #define BM_DMA_HRS_HRS6      (0x00000040U) /*!< Bit mask for DMA_HRS_HRS6. */
03353 #define BS_DMA_HRS_HRS6      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS6. */
03354 
03355 /*! @brief Read current value of the DMA_HRS_HRS6 field. */
03356 #define BR_DMA_HRS_HRS6(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6)))
03357 /*@}*/
03358 
03359 /*!
03360  * @name Register DMA_HRS, field HRS7[7] (RO)
03361  *
03362  * The HRS bit for its respective channel remains asserted for the period when a
03363  * Hardware Request is Present on the Channel. After the Request is completed
03364  * and Channel is free , the HRS bit is automatically cleared by hardware.
03365  *
03366  * Values:
03367  * - 0 - A hardware service request for channel 7 is not present
03368  * - 1 - A hardware service request for channel 7 is present
03369  */
03370 /*@{*/
03371 #define BP_DMA_HRS_HRS7      (7U)          /*!< Bit position for DMA_HRS_HRS7. */
03372 #define BM_DMA_HRS_HRS7      (0x00000080U) /*!< Bit mask for DMA_HRS_HRS7. */
03373 #define BS_DMA_HRS_HRS7      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS7. */
03374 
03375 /*! @brief Read current value of the DMA_HRS_HRS7 field. */
03376 #define BR_DMA_HRS_HRS7(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7)))
03377 /*@}*/
03378 
03379 /*!
03380  * @name Register DMA_HRS, field HRS8[8] (RO)
03381  *
03382  * The HRS bit for its respective channel remains asserted for the period when a
03383  * Hardware Request is Present on the Channel. After the Request is completed
03384  * and Channel is free , the HRS bit is automatically cleared by hardware.
03385  *
03386  * Values:
03387  * - 0 - A hardware service request for channel 8 is not present
03388  * - 1 - A hardware service request for channel 8 is present
03389  */
03390 /*@{*/
03391 #define BP_DMA_HRS_HRS8      (8U)          /*!< Bit position for DMA_HRS_HRS8. */
03392 #define BM_DMA_HRS_HRS8      (0x00000100U) /*!< Bit mask for DMA_HRS_HRS8. */
03393 #define BS_DMA_HRS_HRS8      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS8. */
03394 
03395 /*! @brief Read current value of the DMA_HRS_HRS8 field. */
03396 #define BR_DMA_HRS_HRS8(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8)))
03397 /*@}*/
03398 
03399 /*!
03400  * @name Register DMA_HRS, field HRS9[9] (RO)
03401  *
03402  * The HRS bit for its respective channel remains asserted for the period when a
03403  * Hardware Request is Present on the Channel. After the Request is completed
03404  * and Channel is free , the HRS bit is automatically cleared by hardware.
03405  *
03406  * Values:
03407  * - 0 - A hardware service request for channel 9 is not present
03408  * - 1 - A hardware service request for channel 9 is present
03409  */
03410 /*@{*/
03411 #define BP_DMA_HRS_HRS9      (9U)          /*!< Bit position for DMA_HRS_HRS9. */
03412 #define BM_DMA_HRS_HRS9      (0x00000200U) /*!< Bit mask for DMA_HRS_HRS9. */
03413 #define BS_DMA_HRS_HRS9      (1U)          /*!< Bit field size in bits for DMA_HRS_HRS9. */
03414 
03415 /*! @brief Read current value of the DMA_HRS_HRS9 field. */
03416 #define BR_DMA_HRS_HRS9(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9)))
03417 /*@}*/
03418 
03419 /*!
03420  * @name Register DMA_HRS, field HRS10[10] (RO)
03421  *
03422  * The HRS bit for its respective channel remains asserted for the period when a
03423  * Hardware Request is Present on the Channel. After the Request is completed
03424  * and Channel is free , the HRS bit is automatically cleared by hardware.
03425  *
03426  * Values:
03427  * - 0 - A hardware service request for channel 10 is not present
03428  * - 1 - A hardware service request for channel 10 is present
03429  */
03430 /*@{*/
03431 #define BP_DMA_HRS_HRS10     (10U)         /*!< Bit position for DMA_HRS_HRS10. */
03432 #define BM_DMA_HRS_HRS10     (0x00000400U) /*!< Bit mask for DMA_HRS_HRS10. */
03433 #define BS_DMA_HRS_HRS10     (1U)          /*!< Bit field size in bits for DMA_HRS_HRS10. */
03434 
03435 /*! @brief Read current value of the DMA_HRS_HRS10 field. */
03436 #define BR_DMA_HRS_HRS10(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10)))
03437 /*@}*/
03438 
03439 /*!
03440  * @name Register DMA_HRS, field HRS11[11] (RO)
03441  *
03442  * The HRS bit for its respective channel remains asserted for the period when a
03443  * Hardware Request is Present on the Channel. After the Request is completed
03444  * and Channel is free , the HRS bit is automatically cleared by hardware.
03445  *
03446  * Values:
03447  * - 0 - A hardware service request for channel 11 is not present
03448  * - 1 - A hardware service request for channel 11 is present
03449  */
03450 /*@{*/
03451 #define BP_DMA_HRS_HRS11     (11U)         /*!< Bit position for DMA_HRS_HRS11. */
03452 #define BM_DMA_HRS_HRS11     (0x00000800U) /*!< Bit mask for DMA_HRS_HRS11. */
03453 #define BS_DMA_HRS_HRS11     (1U)          /*!< Bit field size in bits for DMA_HRS_HRS11. */
03454 
03455 /*! @brief Read current value of the DMA_HRS_HRS11 field. */
03456 #define BR_DMA_HRS_HRS11(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11)))
03457 /*@}*/
03458 
03459 /*!
03460  * @name Register DMA_HRS, field HRS12[12] (RO)
03461  *
03462  * The HRS bit for its respective channel remains asserted for the period when a
03463  * Hardware Request is Present on the Channel. After the Request is completed
03464  * and Channel is free , the HRS bit is automatically cleared by hardware.
03465  *
03466  * Values:
03467  * - 0 - A hardware service request for channel 12 is not present
03468  * - 1 - A hardware service request for channel 12 is present
03469  */
03470 /*@{*/
03471 #define BP_DMA_HRS_HRS12     (12U)         /*!< Bit position for DMA_HRS_HRS12. */
03472 #define BM_DMA_HRS_HRS12     (0x00001000U) /*!< Bit mask for DMA_HRS_HRS12. */
03473 #define BS_DMA_HRS_HRS12     (1U)          /*!< Bit field size in bits for DMA_HRS_HRS12. */
03474 
03475 /*! @brief Read current value of the DMA_HRS_HRS12 field. */
03476 #define BR_DMA_HRS_HRS12(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12)))
03477 /*@}*/
03478 
03479 /*!
03480  * @name Register DMA_HRS, field HRS13[13] (RO)
03481  *
03482  * The HRS bit for its respective channel remains asserted for the period when a
03483  * Hardware Request is Present on the Channel. After the Request is completed
03484  * and Channel is free , the HRS bit is automatically cleared by hardware.
03485  *
03486  * Values:
03487  * - 0 - A hardware service request for channel 13 is not present
03488  * - 1 - A hardware service request for channel 13 is present
03489  */
03490 /*@{*/
03491 #define BP_DMA_HRS_HRS13     (13U)         /*!< Bit position for DMA_HRS_HRS13. */
03492 #define BM_DMA_HRS_HRS13     (0x00002000U) /*!< Bit mask for DMA_HRS_HRS13. */
03493 #define BS_DMA_HRS_HRS13     (1U)          /*!< Bit field size in bits for DMA_HRS_HRS13. */
03494 
03495 /*! @brief Read current value of the DMA_HRS_HRS13 field. */
03496 #define BR_DMA_HRS_HRS13(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13)))
03497 /*@}*/
03498 
03499 /*!
03500  * @name Register DMA_HRS, field HRS14[14] (RO)
03501  *
03502  * The HRS bit for its respective channel remains asserted for the period when a
03503  * Hardware Request is Present on the Channel. After the Request is completed
03504  * and Channel is free , the HRS bit is automatically cleared by hardware.
03505  *
03506  * Values:
03507  * - 0 - A hardware service request for channel 14 is not present
03508  * - 1 - A hardware service request for channel 14 is present
03509  */
03510 /*@{*/
03511 #define BP_DMA_HRS_HRS14     (14U)         /*!< Bit position for DMA_HRS_HRS14. */
03512 #define BM_DMA_HRS_HRS14     (0x00004000U) /*!< Bit mask for DMA_HRS_HRS14. */
03513 #define BS_DMA_HRS_HRS14     (1U)          /*!< Bit field size in bits for DMA_HRS_HRS14. */
03514 
03515 /*! @brief Read current value of the DMA_HRS_HRS14 field. */
03516 #define BR_DMA_HRS_HRS14(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14)))
03517 /*@}*/
03518 
03519 /*!
03520  * @name Register DMA_HRS, field HRS15[15] (RO)
03521  *
03522  * The HRS bit for its respective channel remains asserted for the period when a
03523  * Hardware Request is Present on the Channel. After the Request is completed
03524  * and Channel is free , the HRS bit is automatically cleared by hardware.
03525  *
03526  * Values:
03527  * - 0 - A hardware service request for channel 15 is not present
03528  * - 1 - A hardware service request for channel 15 is present
03529  */
03530 /*@{*/
03531 #define BP_DMA_HRS_HRS15     (15U)         /*!< Bit position for DMA_HRS_HRS15. */
03532 #define BM_DMA_HRS_HRS15     (0x00008000U) /*!< Bit mask for DMA_HRS_HRS15. */
03533 #define BS_DMA_HRS_HRS15     (1U)          /*!< Bit field size in bits for DMA_HRS_HRS15. */
03534 
03535 /*! @brief Read current value of the DMA_HRS_HRS15 field. */
03536 #define BR_DMA_HRS_HRS15(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15)))
03537 /*@}*/
03538 
03539 /*******************************************************************************
03540  * HW_DMA_DCHPRIn - Channel n Priority Register
03541  ******************************************************************************/
03542 
03543 /*!
03544  * @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
03545  *
03546  * Reset value: 0x00U
03547  *
03548  * When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
03549  * contents of these registers define the unique priorities associated with each
03550  * channel . The channel priorities are evaluated by numeric value; for example, 0 is
03551  * the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
03552  * program the channel priorities with unique values; otherwise, a configuration
03553  * error is reported. The range of the priority value is limited to the values of 0
03554  * through 15.
03555  */
03556 typedef union _hw_dma_dchprin
03557 {
03558     uint8_t U;
03559     struct _hw_dma_dchprin_bitfields
03560     {
03561         uint8_t CHPRI : 4;             /*!< [3:0] Channel n Arbitration Priority */
03562         uint8_t RESERVED0 : 2;         /*!< [5:4]  */
03563         uint8_t DPA : 1;               /*!< [6] Disable Preempt Ability */
03564         uint8_t ECP : 1;               /*!< [7] Enable Channel Preemption */
03565     } B;
03566 } hw_dma_dchprin_t;
03567 
03568 /*!
03569  * @name Constants and macros for entire DMA_DCHPRIn register
03570  */
03571 /*@{*/
03572 #define HW_DMA_DCHPRIn_COUNT (16U)
03573 
03574 #define HW_DMA_DCHPRIn_ADDR(x, n) ((x) + 0x100U + (0x1U * (n)))
03575 
03576 /* DMA channel index to DMA channel priority register array index conversion macro */
03577 #define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) | (3 - ((n) & 0x03U)))
03578 
03579 #define HW_DMA_DCHPRIn(x, n)     (*(__IO hw_dma_dchprin_t *) HW_DMA_DCHPRIn_ADDR(x, n))
03580 #define HW_DMA_DCHPRIn_RD(x, n)  (ADDRESS_READ(hw_dma_dchprin_t, HW_DMA_DCHPRIn_ADDR(x, n)))
03581 #define HW_DMA_DCHPRIn_WR(x, n, v) (ADDRESS_WRITE(hw_dma_dchprin_t, HW_DMA_DCHPRIn_ADDR(x, n), v))
03582 #define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) |  (v)))
03583 #define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
03584 #define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^  (v)))
03585 /*@}*/
03586 
03587 /*
03588  * Constants & macros for individual DMA_DCHPRIn bitfields
03589  */
03590 
03591 /*!
03592  * @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
03593  *
03594  * Channel priority when fixed-priority arbitration is enabled Reset value for
03595  * the channel priority fields, CHPRI, is equal to the corresponding channel
03596  * number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
03597  */
03598 /*@{*/
03599 #define BP_DMA_DCHPRIn_CHPRI (0U)          /*!< Bit position for DMA_DCHPRIn_CHPRI. */
03600 #define BM_DMA_DCHPRIn_CHPRI (0x0FU)       /*!< Bit mask for DMA_DCHPRIn_CHPRI. */
03601 #define BS_DMA_DCHPRIn_CHPRI (4U)          /*!< Bit field size in bits for DMA_DCHPRIn_CHPRI. */
03602 
03603 /*! @brief Read current value of the DMA_DCHPRIn_CHPRI field. */
03604 #define BR_DMA_DCHPRIn_CHPRI(x, n) (UNION_READ(hw_dma_dchprin_t, HW_DMA_DCHPRIn_ADDR(x, n), U, B.CHPRI))
03605 
03606 /*! @brief Format value for bitfield DMA_DCHPRIn_CHPRI. */
03607 #define BF_DMA_DCHPRIn_CHPRI(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_CHPRI) & BM_DMA_DCHPRIn_CHPRI)
03608 
03609 /*! @brief Set the CHPRI field to a new value. */
03610 #define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) | BF_DMA_DCHPRIn_CHPRI(v)))
03611 /*@}*/
03612 
03613 /*!
03614  * @name Register DMA_DCHPRIn, field DPA[6] (RW)
03615  *
03616  * Values:
03617  * - 0 - Channel n can suspend a lower priority channel
03618  * - 1 - Channel n cannot suspend any channel, regardless of channel priority
03619  */
03620 /*@{*/
03621 #define BP_DMA_DCHPRIn_DPA   (6U)          /*!< Bit position for DMA_DCHPRIn_DPA. */
03622 #define BM_DMA_DCHPRIn_DPA   (0x40U)       /*!< Bit mask for DMA_DCHPRIn_DPA. */
03623 #define BS_DMA_DCHPRIn_DPA   (1U)          /*!< Bit field size in bits for DMA_DCHPRIn_DPA. */
03624 
03625 /*! @brief Read current value of the DMA_DCHPRIn_DPA field. */
03626 #define BR_DMA_DCHPRIn_DPA(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA)))
03627 
03628 /*! @brief Format value for bitfield DMA_DCHPRIn_DPA. */
03629 #define BF_DMA_DCHPRIn_DPA(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_DPA) & BM_DMA_DCHPRIn_DPA)
03630 
03631 /*! @brief Set the DPA field to a new value. */
03632 #define BW_DMA_DCHPRIn_DPA(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA), v))
03633 /*@}*/
03634 
03635 /*!
03636  * @name Register DMA_DCHPRIn, field ECP[7] (RW)
03637  *
03638  * Values:
03639  * - 0 - Channel n cannot be suspended by a higher priority channel's service
03640  *     request
03641  * - 1 - Channel n can be temporarily suspended by the service request of a
03642  *     higher priority channel
03643  */
03644 /*@{*/
03645 #define BP_DMA_DCHPRIn_ECP   (7U)          /*!< Bit position for DMA_DCHPRIn_ECP. */
03646 #define BM_DMA_DCHPRIn_ECP   (0x80U)       /*!< Bit mask for DMA_DCHPRIn_ECP. */
03647 #define BS_DMA_DCHPRIn_ECP   (1U)          /*!< Bit field size in bits for DMA_DCHPRIn_ECP. */
03648 
03649 /*! @brief Read current value of the DMA_DCHPRIn_ECP field. */
03650 #define BR_DMA_DCHPRIn_ECP(x, n) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP)))
03651 
03652 /*! @brief Format value for bitfield DMA_DCHPRIn_ECP. */
03653 #define BF_DMA_DCHPRIn_ECP(v) ((uint8_t)((uint8_t)(v) << BP_DMA_DCHPRIn_ECP) & BM_DMA_DCHPRIn_ECP)
03654 
03655 /*! @brief Set the ECP field to a new value. */
03656 #define BW_DMA_DCHPRIn_ECP(x, n, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP), v))
03657 /*@}*/
03658 
03659 /*******************************************************************************
03660  * HW_DMA_TCDn_SADDR - TCD Source Address
03661  ******************************************************************************/
03662 
03663 /*!
03664  * @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
03665  *
03666  * Reset value: 0x00000000U
03667  */
03668 typedef union _hw_dma_tcdn_saddr
03669 {
03670     uint32_t U;
03671     struct _hw_dma_tcdn_saddr_bitfields
03672     {
03673         uint32_t SADDR : 32;           /*!< [31:0] Source Address */
03674     } B;
03675 } hw_dma_tcdn_saddr_t;
03676 
03677 /*!
03678  * @name Constants and macros for entire DMA_TCDn_SADDR register
03679  */
03680 /*@{*/
03681 #define HW_DMA_TCDn_SADDR_COUNT (16U)
03682 
03683 #define HW_DMA_TCDn_SADDR_ADDR(x, n) ((x) + 0x1000U + (0x20U * (n)))
03684 
03685 #define HW_DMA_TCDn_SADDR(x, n)  (*(__IO hw_dma_tcdn_saddr_t *) HW_DMA_TCDn_SADDR_ADDR(x, n))
03686 #define HW_DMA_TCDn_SADDR_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_saddr_t, HW_DMA_TCDn_SADDR_ADDR(x, n)))
03687 #define HW_DMA_TCDn_SADDR_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_saddr_t, HW_DMA_TCDn_SADDR_ADDR(x, n), v))
03688 #define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) |  (v)))
03689 #define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
03690 #define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^  (v)))
03691 /*@}*/
03692 
03693 /*
03694  * Constants & macros for individual DMA_TCDn_SADDR bitfields
03695  */
03696 
03697 /*!
03698  * @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
03699  *
03700  * Memory address pointing to the source data.
03701  */
03702 /*@{*/
03703 #define BP_DMA_TCDn_SADDR_SADDR (0U)       /*!< Bit position for DMA_TCDn_SADDR_SADDR. */
03704 #define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SADDR_SADDR. */
03705 #define BS_DMA_TCDn_SADDR_SADDR (32U)      /*!< Bit field size in bits for DMA_TCDn_SADDR_SADDR. */
03706 
03707 /*! @brief Read current value of the DMA_TCDn_SADDR_SADDR field. */
03708 #define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
03709 
03710 /*! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR. */
03711 #define BF_DMA_TCDn_SADDR_SADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SADDR_SADDR) & BM_DMA_TCDn_SADDR_SADDR)
03712 
03713 /*! @brief Set the SADDR field to a new value. */
03714 #define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
03715 /*@}*/
03716 /*******************************************************************************
03717  * HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
03718  ******************************************************************************/
03719 
03720 /*!
03721  * @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
03722  *
03723  * Reset value: 0x0000U
03724  */
03725 typedef union _hw_dma_tcdn_soff
03726 {
03727     uint16_t U;
03728     struct _hw_dma_tcdn_soff_bitfields
03729     {
03730         uint16_t SOFF : 16;            /*!< [15:0] Source address signed offset */
03731     } B;
03732 } hw_dma_tcdn_soff_t;
03733 
03734 /*!
03735  * @name Constants and macros for entire DMA_TCDn_SOFF register
03736  */
03737 /*@{*/
03738 #define HW_DMA_TCDn_SOFF_COUNT (16U)
03739 
03740 #define HW_DMA_TCDn_SOFF_ADDR(x, n) ((x) + 0x1004U + (0x20U * (n)))
03741 
03742 #define HW_DMA_TCDn_SOFF(x, n)   (*(__IO hw_dma_tcdn_soff_t *) HW_DMA_TCDn_SOFF_ADDR(x, n))
03743 #define HW_DMA_TCDn_SOFF_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_soff_t, HW_DMA_TCDn_SOFF_ADDR(x, n)))
03744 #define HW_DMA_TCDn_SOFF_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_soff_t, HW_DMA_TCDn_SOFF_ADDR(x, n), v))
03745 #define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) |  (v)))
03746 #define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
03747 #define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^  (v)))
03748 /*@}*/
03749 
03750 /*
03751  * Constants & macros for individual DMA_TCDn_SOFF bitfields
03752  */
03753 
03754 /*!
03755  * @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
03756  *
03757  * Sign-extended offset applied to the current source address to form the
03758  * next-state value as each source read is completed.
03759  */
03760 /*@{*/
03761 #define BP_DMA_TCDn_SOFF_SOFF (0U)         /*!< Bit position for DMA_TCDn_SOFF_SOFF. */
03762 #define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU)    /*!< Bit mask for DMA_TCDn_SOFF_SOFF. */
03763 #define BS_DMA_TCDn_SOFF_SOFF (16U)        /*!< Bit field size in bits for DMA_TCDn_SOFF_SOFF. */
03764 
03765 /*! @brief Read current value of the DMA_TCDn_SOFF_SOFF field. */
03766 #define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
03767 
03768 /*! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF. */
03769 #define BF_DMA_TCDn_SOFF_SOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_SOFF_SOFF) & BM_DMA_TCDn_SOFF_SOFF)
03770 
03771 /*! @brief Set the SOFF field to a new value. */
03772 #define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
03773 /*@}*/
03774 /*******************************************************************************
03775  * HW_DMA_TCDn_ATTR - TCD Transfer Attributes
03776  ******************************************************************************/
03777 
03778 /*!
03779  * @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
03780  *
03781  * Reset value: 0x0000U
03782  */
03783 typedef union _hw_dma_tcdn_attr
03784 {
03785     uint16_t U;
03786     struct _hw_dma_tcdn_attr_bitfields
03787     {
03788         uint16_t DSIZE : 3;            /*!< [2:0] Destination Data Transfer Size */
03789         uint16_t DMOD : 5;             /*!< [7:3] Destination Address Modulo */
03790         uint16_t SSIZE : 3;            /*!< [10:8] Source data transfer size */
03791         uint16_t SMOD : 5;             /*!< [15:11] Source Address Modulo. */
03792     } B;
03793 } hw_dma_tcdn_attr_t;
03794 
03795 /*!
03796  * @name Constants and macros for entire DMA_TCDn_ATTR register
03797  */
03798 /*@{*/
03799 #define HW_DMA_TCDn_ATTR_COUNT (16U)
03800 
03801 #define HW_DMA_TCDn_ATTR_ADDR(x, n) ((x) + 0x1006U + (0x20U * (n)))
03802 
03803 #define HW_DMA_TCDn_ATTR(x, n)   (*(__IO hw_dma_tcdn_attr_t *) HW_DMA_TCDn_ATTR_ADDR(x, n))
03804 #define HW_DMA_TCDn_ATTR_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_attr_t, HW_DMA_TCDn_ATTR_ADDR(x, n)))
03805 #define HW_DMA_TCDn_ATTR_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_attr_t, HW_DMA_TCDn_ATTR_ADDR(x, n), v))
03806 #define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) |  (v)))
03807 #define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
03808 #define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^  (v)))
03809 /*@}*/
03810 
03811 /*
03812  * Constants & macros for individual DMA_TCDn_ATTR bitfields
03813  */
03814 
03815 /*!
03816  * @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
03817  *
03818  * See the SSIZE definition
03819  */
03820 /*@{*/
03821 #define BP_DMA_TCDn_ATTR_DSIZE (0U)        /*!< Bit position for DMA_TCDn_ATTR_DSIZE. */
03822 #define BM_DMA_TCDn_ATTR_DSIZE (0x0007U)   /*!< Bit mask for DMA_TCDn_ATTR_DSIZE. */
03823 #define BS_DMA_TCDn_ATTR_DSIZE (3U)        /*!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE. */
03824 
03825 /*! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field. */
03826 #define BR_DMA_TCDn_ATTR_DSIZE(x, n) (UNION_READ(hw_dma_tcdn_attr_t, HW_DMA_TCDn_ATTR_ADDR(x, n), U, B.DSIZE))
03827 
03828 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE. */
03829 #define BF_DMA_TCDn_ATTR_DSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DSIZE) & BM_DMA_TCDn_ATTR_DSIZE)
03830 
03831 /*! @brief Set the DSIZE field to a new value. */
03832 #define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) | BF_DMA_TCDn_ATTR_DSIZE(v)))
03833 /*@}*/
03834 
03835 /*!
03836  * @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
03837  *
03838  * See the SMOD definition
03839  */
03840 /*@{*/
03841 #define BP_DMA_TCDn_ATTR_DMOD (3U)         /*!< Bit position for DMA_TCDn_ATTR_DMOD. */
03842 #define BM_DMA_TCDn_ATTR_DMOD (0x00F8U)    /*!< Bit mask for DMA_TCDn_ATTR_DMOD. */
03843 #define BS_DMA_TCDn_ATTR_DMOD (5U)         /*!< Bit field size in bits for DMA_TCDn_ATTR_DMOD. */
03844 
03845 /*! @brief Read current value of the DMA_TCDn_ATTR_DMOD field. */
03846 #define BR_DMA_TCDn_ATTR_DMOD(x, n) (UNION_READ(hw_dma_tcdn_attr_t, HW_DMA_TCDn_ATTR_ADDR(x, n), U, B.DMOD))
03847 
03848 /*! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD. */
03849 #define BF_DMA_TCDn_ATTR_DMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_DMOD) & BM_DMA_TCDn_ATTR_DMOD)
03850 
03851 /*! @brief Set the DMOD field to a new value. */
03852 #define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) | BF_DMA_TCDn_ATTR_DMOD(v)))
03853 /*@}*/
03854 
03855 /*!
03856  * @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
03857  *
03858  * The attempted use of a Reserved encoding causes a configuration error.
03859  *
03860  * Values:
03861  * - 000 - 8-bit
03862  * - 001 - 16-bit
03863  * - 010 - 32-bit
03864  * - 011 - Reserved
03865  * - 100 - 16-byte
03866  * - 101 - 32-byte
03867  * - 110 - Reserved
03868  * - 111 - Reserved
03869  */
03870 /*@{*/
03871 #define BP_DMA_TCDn_ATTR_SSIZE (8U)        /*!< Bit position for DMA_TCDn_ATTR_SSIZE. */
03872 #define BM_DMA_TCDn_ATTR_SSIZE (0x0700U)   /*!< Bit mask for DMA_TCDn_ATTR_SSIZE. */
03873 #define BS_DMA_TCDn_ATTR_SSIZE (3U)        /*!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE. */
03874 
03875 /*! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field. */
03876 #define BR_DMA_TCDn_ATTR_SSIZE(x, n) (UNION_READ(hw_dma_tcdn_attr_t, HW_DMA_TCDn_ATTR_ADDR(x, n), U, B.SSIZE))
03877 
03878 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE. */
03879 #define BF_DMA_TCDn_ATTR_SSIZE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SSIZE) & BM_DMA_TCDn_ATTR_SSIZE)
03880 
03881 /*! @brief Set the SSIZE field to a new value. */
03882 #define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) | BF_DMA_TCDn_ATTR_SSIZE(v)))
03883 /*@}*/
03884 
03885 /*!
03886  * @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
03887  *
03888  * Values:
03889  * - 0 - Source address modulo feature is disabled
03890  */
03891 /*@{*/
03892 #define BP_DMA_TCDn_ATTR_SMOD (11U)        /*!< Bit position for DMA_TCDn_ATTR_SMOD. */
03893 #define BM_DMA_TCDn_ATTR_SMOD (0xF800U)    /*!< Bit mask for DMA_TCDn_ATTR_SMOD. */
03894 #define BS_DMA_TCDn_ATTR_SMOD (5U)         /*!< Bit field size in bits for DMA_TCDn_ATTR_SMOD. */
03895 
03896 /*! @brief Read current value of the DMA_TCDn_ATTR_SMOD field. */
03897 #define BR_DMA_TCDn_ATTR_SMOD(x, n) (UNION_READ(hw_dma_tcdn_attr_t, HW_DMA_TCDn_ATTR_ADDR(x, n), U, B.SMOD))
03898 
03899 /*! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD. */
03900 #define BF_DMA_TCDn_ATTR_SMOD(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_ATTR_SMOD) & BM_DMA_TCDn_ATTR_SMOD)
03901 
03902 /*! @brief Set the SMOD field to a new value. */
03903 #define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) | BF_DMA_TCDn_ATTR_SMOD(v)))
03904 /*@}*/
03905 /*******************************************************************************
03906  * HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
03907  ******************************************************************************/
03908 
03909 /*!
03910  * @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
03911  *
03912  * Reset value: 0x00000000U
03913  *
03914  * This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
03915  * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
03916  * register to use depends on whether minor loop mapping is disabled, enabled but not
03917  * used for this channel, or enabled and used. TCD word 2 is defined as follows
03918  * if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
03919  * enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
03920  * for TCD word 2's definition.
03921  */
03922 typedef union _hw_dma_tcdn_nbytes_mlno
03923 {
03924     uint32_t U;
03925     struct _hw_dma_tcdn_nbytes_mlno_bitfields
03926     {
03927         uint32_t NBYTES : 32;          /*!< [31:0] Minor Byte Transfer Count */
03928     } B;
03929 } hw_dma_tcdn_nbytes_mlno_t;
03930 
03931 /*!
03932  * @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
03933  */
03934 /*@{*/
03935 #define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
03936 
03937 #define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
03938 
03939 #define HW_DMA_TCDn_NBYTES_MLNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mlno_t *) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
03940 #define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_nbytes_mlno_t, HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n)))
03941 #define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_nbytes_mlno_t, HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n), v))
03942 #define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) |  (v)))
03943 #define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
03944 #define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^  (v)))
03945 /*@}*/
03946 
03947 /*
03948  * Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
03949  */
03950 
03951 /*!
03952  * @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
03953  *
03954  * Number of bytes to be transferred in each service request of the channel. As
03955  * a channel activates, the appropriate TCD contents load into the eDMA engine,
03956  * and the appropriate reads and writes perform until the minor byte transfer
03957  * count has transferred. This is an indivisible operation and cannot be halted.
03958  * (Although, it may be stalled by using the bandwidth control field, or via
03959  * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
03960  * written back into the TCD memory, the major iteration count is decremented and
03961  * restored to the TCD memory. If the major iteration count is completed, additional
03962  * processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
03963  * GB transfer.
03964  */
03965 /*@{*/
03966 #define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES. */
03967 #define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES. */
03968 #define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES. */
03969 
03970 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field. */
03971 #define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
03972 
03973 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES. */
03974 #define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
03975 
03976 /*! @brief Set the NBYTES field to a new value. */
03977 #define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
03978 /*@}*/
03979 /*******************************************************************************
03980  * HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
03981  ******************************************************************************/
03982 
03983 /*!
03984  * @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
03985  *
03986  * Reset value: 0x00000000U
03987  *
03988  * One of three registers (this register, TCD_NBYTES_MLNO, or
03989  * TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
03990  * depends on whether minor loop mapping is disabled, enabled but not used for
03991  * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
03992  * loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
03993  * loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
03994  * TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
03995  * the TCD_NBYTES_MLNO register description.
03996  */
03997 typedef union _hw_dma_tcdn_nbytes_mloffno
03998 {
03999     uint32_t U;
04000     struct _hw_dma_tcdn_nbytes_mloffno_bitfields
04001     {
04002         uint32_t NBYTES : 30;          /*!< [29:0] Minor Byte Transfer Count */
04003         uint32_t DMLOE : 1;            /*!< [30] Destination Minor Loop Offset enable */
04004         uint32_t SMLOE : 1;            /*!< [31] Source Minor Loop Offset Enable */
04005     } B;
04006 } hw_dma_tcdn_nbytes_mloffno_t;
04007 
04008 /*!
04009  * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
04010  */
04011 /*@{*/
04012 #define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
04013 
04014 #define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
04015 
04016 #define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffno_t *) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
04017 #define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_nbytes_mloffno_t, HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n)))
04018 #define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_nbytes_mloffno_t, HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), v))
04019 #define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) |  (v)))
04020 #define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
04021 #define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^  (v)))
04022 /*@}*/
04023 
04024 /*
04025  * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
04026  */
04027 
04028 /*!
04029  * @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
04030  *
04031  * Number of bytes to be transferred in each service request of the channel. As
04032  * a channel activates, the appropriate TCD contents load into the eDMA engine,
04033  * and the appropriate reads and writes perform until the minor byte transfer
04034  * count has transferred. This is an indivisible operation and cannot be halted;
04035  * although, it may be stalled by using the bandwidth control field, or via
04036  * preemption. After the minor count is exhausted, the SADDR and DADDR values are written
04037  * back into the TCD memory, the major iteration count is decremented and
04038  * restored to the TCD memory. If the major iteration count is completed, additional
04039  * processing is performed.
04040  */
04041 /*@{*/
04042 #define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
04043 #define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
04044 #define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
04045 
04046 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field. */
04047 #define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (UNION_READ(hw_dma_tcdn_nbytes_mloffno_t, HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), U, B.NBYTES))
04048 
04049 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES. */
04050 #define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
04051 
04052 /*! @brief Set the NBYTES field to a new value. */
04053 #define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
04054 /*@}*/
04055 
04056 /*!
04057  * @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
04058  *
04059  * Selects whether the minor loop offset is applied to the destination address
04060  * upon minor loop completion.
04061  *
04062  * Values:
04063  * - 0 - The minor loop offset is not applied to the DADDR
04064  * - 1 - The minor loop offset is applied to the DADDR
04065  */
04066 /*@{*/
04067 #define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
04068 #define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
04069 #define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
04070 
04071 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field. */
04072 #define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)))
04073 
04074 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE. */
04075 #define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
04076 
04077 /*! @brief Set the DMLOE field to a new value. */
04078 #define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE), v))
04079 /*@}*/
04080 
04081 /*!
04082  * @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
04083  *
04084  * Selects whether the minor loop offset is applied to the source address upon
04085  * minor loop completion.
04086  *
04087  * Values:
04088  * - 0 - The minor loop offset is not applied to the SADDR
04089  * - 1 - The minor loop offset is applied to the SADDR
04090  */
04091 /*@{*/
04092 #define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
04093 #define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
04094 #define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
04095 
04096 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field. */
04097 #define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)))
04098 
04099 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE. */
04100 #define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
04101 
04102 /*! @brief Set the SMLOE field to a new value. */
04103 #define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE), v))
04104 /*@}*/
04105 /*******************************************************************************
04106  * HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
04107  ******************************************************************************/
04108 
04109 /*!
04110  * @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
04111  *
04112  * Reset value: 0x00000000U
04113  *
04114  * One of three registers (this register, TCD_NBYTES_MLNO, or
04115  * TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
04116  * depends on whether minor loop mapping is disabled, enabled but not used for
04117  * this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
04118  * loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
04119  * or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
04120  * then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
04121  * mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
04122  */
04123 typedef union _hw_dma_tcdn_nbytes_mloffyes
04124 {
04125     uint32_t U;
04126     struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
04127     {
04128         uint32_t NBYTES : 10;          /*!< [9:0] Minor Byte Transfer Count */
04129         uint32_t MLOFF : 20;           /*!< [29:10] If SMLOE or DMLOE is set, this
04130                                         * field represents a sign-extended offset applied to the source or destination
04131                                         * address to form the next-state value after the minor loop completes. */
04132         uint32_t DMLOE : 1;            /*!< [30] Destination Minor Loop Offset enable */
04133         uint32_t SMLOE : 1;            /*!< [31] Source Minor Loop Offset Enable */
04134     } B;
04135 } hw_dma_tcdn_nbytes_mloffyes_t;
04136 
04137 /*!
04138  * @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
04139  */
04140 /*@{*/
04141 #define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
04142 
04143 #define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) ((x) + 0x1008U + (0x20U * (n)))
04144 
04145 #define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) (*(__IO hw_dma_tcdn_nbytes_mloffyes_t *) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
04146 #define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_nbytes_mloffyes_t, HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n)))
04147 #define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_nbytes_mloffyes_t, HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), v))
04148 #define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) |  (v)))
04149 #define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
04150 #define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^  (v)))
04151 /*@}*/
04152 
04153 /*
04154  * Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
04155  */
04156 
04157 /*!
04158  * @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
04159  *
04160  * Number of bytes to be transferred in each service request of the channel. As
04161  * a channel activates, the appropriate TCD contents load into the eDMA engine,
04162  * and the appropriate reads and writes perform until the minor byte transfer
04163  * count has transferred. This is an indivisible operation and cannot be halted.
04164  * (Although, it may be stalled by using the bandwidth control field, or via
04165  * preemption.) After the minor count is exhausted, the SADDR and DADDR values are
04166  * written back into the TCD memory, the major iteration count is decremented and
04167  * restored to the TCD memory. If the major iteration count is completed, additional
04168  * processing is performed.
04169  */
04170 /*@{*/
04171 #define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
04172 #define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
04173 #define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
04174 
04175 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field. */
04176 #define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (UNION_READ(hw_dma_tcdn_nbytes_mloffyes_t, HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), U, B.NBYTES))
04177 
04178 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES. */
04179 #define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
04180 
04181 /*! @brief Set the NBYTES field to a new value. */
04182 #define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) | BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
04183 /*@}*/
04184 
04185 /*!
04186  * @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
04187  */
04188 /*@{*/
04189 #define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
04190 #define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
04191 #define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
04192 
04193 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field. */
04194 #define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (UNION_READ(hw_dma_tcdn_nbytes_mloffyes_t, HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), U, B.MLOFF))
04195 
04196 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF. */
04197 #define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
04198 
04199 /*! @brief Set the MLOFF field to a new value. */
04200 #define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) | BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
04201 /*@}*/
04202 
04203 /*!
04204  * @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
04205  *
04206  * Selects whether the minor loop offset is applied to the destination address
04207  * upon minor loop completion.
04208  *
04209  * Values:
04210  * - 0 - The minor loop offset is not applied to the DADDR
04211  * - 1 - The minor loop offset is applied to the DADDR
04212  */
04213 /*@{*/
04214 #define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
04215 #define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
04216 #define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
04217 
04218 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field. */
04219 #define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)))
04220 
04221 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE. */
04222 #define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
04223 
04224 /*! @brief Set the DMLOE field to a new value. */
04225 #define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE), v))
04226 /*@}*/
04227 
04228 /*!
04229  * @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
04230  *
04231  * Selects whether the minor loop offset is applied to the source address upon
04232  * minor loop completion.
04233  *
04234  * Values:
04235  * - 0 - The minor loop offset is not applied to the SADDR
04236  * - 1 - The minor loop offset is applied to the SADDR
04237  */
04238 /*@{*/
04239 #define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) /*!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
04240 #define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) /*!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
04241 #define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) /*!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
04242 
04243 /*! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field. */
04244 #define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)))
04245 
04246 /*! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE. */
04247 #define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
04248 
04249 /*! @brief Set the SMLOE field to a new value. */
04250 #define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE), v))
04251 /*@}*/
04252 /*******************************************************************************
04253  * HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
04254  ******************************************************************************/
04255 
04256 /*!
04257  * @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
04258  *
04259  * Reset value: 0x00000000U
04260  */
04261 typedef union _hw_dma_tcdn_slast
04262 {
04263     uint32_t U;
04264     struct _hw_dma_tcdn_slast_bitfields
04265     {
04266         uint32_t SLAST : 32;           /*!< [31:0] Last source Address Adjustment */
04267     } B;
04268 } hw_dma_tcdn_slast_t;
04269 
04270 /*!
04271  * @name Constants and macros for entire DMA_TCDn_SLAST register
04272  */
04273 /*@{*/
04274 #define HW_DMA_TCDn_SLAST_COUNT (16U)
04275 
04276 #define HW_DMA_TCDn_SLAST_ADDR(x, n) ((x) + 0x100CU + (0x20U * (n)))
04277 
04278 #define HW_DMA_TCDn_SLAST(x, n)  (*(__IO hw_dma_tcdn_slast_t *) HW_DMA_TCDn_SLAST_ADDR(x, n))
04279 #define HW_DMA_TCDn_SLAST_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_slast_t, HW_DMA_TCDn_SLAST_ADDR(x, n)))
04280 #define HW_DMA_TCDn_SLAST_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_slast_t, HW_DMA_TCDn_SLAST_ADDR(x, n), v))
04281 #define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) |  (v)))
04282 #define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
04283 #define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^  (v)))
04284 /*@}*/
04285 
04286 /*
04287  * Constants & macros for individual DMA_TCDn_SLAST bitfields
04288  */
04289 
04290 /*!
04291  * @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
04292  *
04293  * Adjustment value added to the source address at the completion of the major
04294  * iteration count. This value can be applied to restore the source address to the
04295  * initial value, or adjust the address to reference the next data structure.
04296  * This register uses two's complement notation; the overflow bit is discarded.
04297  */
04298 /*@{*/
04299 #define BP_DMA_TCDn_SLAST_SLAST (0U)       /*!< Bit position for DMA_TCDn_SLAST_SLAST. */
04300 #define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_SLAST_SLAST. */
04301 #define BS_DMA_TCDn_SLAST_SLAST (32U)      /*!< Bit field size in bits for DMA_TCDn_SLAST_SLAST. */
04302 
04303 /*! @brief Read current value of the DMA_TCDn_SLAST_SLAST field. */
04304 #define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
04305 
04306 /*! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST. */
04307 #define BF_DMA_TCDn_SLAST_SLAST(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_SLAST_SLAST) & BM_DMA_TCDn_SLAST_SLAST)
04308 
04309 /*! @brief Set the SLAST field to a new value. */
04310 #define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
04311 /*@}*/
04312 /*******************************************************************************
04313  * HW_DMA_TCDn_DADDR - TCD Destination Address
04314  ******************************************************************************/
04315 
04316 /*!
04317  * @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
04318  *
04319  * Reset value: 0x00000000U
04320  */
04321 typedef union _hw_dma_tcdn_daddr
04322 {
04323     uint32_t U;
04324     struct _hw_dma_tcdn_daddr_bitfields
04325     {
04326         uint32_t DADDR : 32;           /*!< [31:0] Destination Address */
04327     } B;
04328 } hw_dma_tcdn_daddr_t;
04329 
04330 /*!
04331  * @name Constants and macros for entire DMA_TCDn_DADDR register
04332  */
04333 /*@{*/
04334 #define HW_DMA_TCDn_DADDR_COUNT (16U)
04335 
04336 #define HW_DMA_TCDn_DADDR_ADDR(x, n) ((x) + 0x1010U + (0x20U * (n)))
04337 
04338 #define HW_DMA_TCDn_DADDR(x, n)  (*(__IO hw_dma_tcdn_daddr_t *) HW_DMA_TCDn_DADDR_ADDR(x, n))
04339 #define HW_DMA_TCDn_DADDR_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_daddr_t, HW_DMA_TCDn_DADDR_ADDR(x, n)))
04340 #define HW_DMA_TCDn_DADDR_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_daddr_t, HW_DMA_TCDn_DADDR_ADDR(x, n), v))
04341 #define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) |  (v)))
04342 #define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
04343 #define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^  (v)))
04344 /*@}*/
04345 
04346 /*
04347  * Constants & macros for individual DMA_TCDn_DADDR bitfields
04348  */
04349 
04350 /*!
04351  * @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
04352  *
04353  * Memory address pointing to the destination data.
04354  */
04355 /*@{*/
04356 #define BP_DMA_TCDn_DADDR_DADDR (0U)       /*!< Bit position for DMA_TCDn_DADDR_DADDR. */
04357 #define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DADDR_DADDR. */
04358 #define BS_DMA_TCDn_DADDR_DADDR (32U)      /*!< Bit field size in bits for DMA_TCDn_DADDR_DADDR. */
04359 
04360 /*! @brief Read current value of the DMA_TCDn_DADDR_DADDR field. */
04361 #define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
04362 
04363 /*! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR. */
04364 #define BF_DMA_TCDn_DADDR_DADDR(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DADDR_DADDR) & BM_DMA_TCDn_DADDR_DADDR)
04365 
04366 /*! @brief Set the DADDR field to a new value. */
04367 #define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
04368 /*@}*/
04369 /*******************************************************************************
04370  * HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
04371  ******************************************************************************/
04372 
04373 /*!
04374  * @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
04375  *
04376  * Reset value: 0x0000U
04377  */
04378 typedef union _hw_dma_tcdn_doff
04379 {
04380     uint16_t U;
04381     struct _hw_dma_tcdn_doff_bitfields
04382     {
04383         uint16_t DOFF : 16;            /*!< [15:0] Destination Address Signed offset */
04384     } B;
04385 } hw_dma_tcdn_doff_t;
04386 
04387 /*!
04388  * @name Constants and macros for entire DMA_TCDn_DOFF register
04389  */
04390 /*@{*/
04391 #define HW_DMA_TCDn_DOFF_COUNT (16U)
04392 
04393 #define HW_DMA_TCDn_DOFF_ADDR(x, n) ((x) + 0x1014U + (0x20U * (n)))
04394 
04395 #define HW_DMA_TCDn_DOFF(x, n)   (*(__IO hw_dma_tcdn_doff_t *) HW_DMA_TCDn_DOFF_ADDR(x, n))
04396 #define HW_DMA_TCDn_DOFF_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_doff_t, HW_DMA_TCDn_DOFF_ADDR(x, n)))
04397 #define HW_DMA_TCDn_DOFF_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_doff_t, HW_DMA_TCDn_DOFF_ADDR(x, n), v))
04398 #define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) |  (v)))
04399 #define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
04400 #define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^  (v)))
04401 /*@}*/
04402 
04403 /*
04404  * Constants & macros for individual DMA_TCDn_DOFF bitfields
04405  */
04406 
04407 /*!
04408  * @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
04409  *
04410  * Sign-extended offset applied to the current destination address to form the
04411  * next-state value as each destination write is completed.
04412  */
04413 /*@{*/
04414 #define BP_DMA_TCDn_DOFF_DOFF (0U)         /*!< Bit position for DMA_TCDn_DOFF_DOFF. */
04415 #define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU)    /*!< Bit mask for DMA_TCDn_DOFF_DOFF. */
04416 #define BS_DMA_TCDn_DOFF_DOFF (16U)        /*!< Bit field size in bits for DMA_TCDn_DOFF_DOFF. */
04417 
04418 /*! @brief Read current value of the DMA_TCDn_DOFF_DOFF field. */
04419 #define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
04420 
04421 /*! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF. */
04422 #define BF_DMA_TCDn_DOFF_DOFF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_DOFF_DOFF) & BM_DMA_TCDn_DOFF_DOFF)
04423 
04424 /*! @brief Set the DOFF field to a new value. */
04425 #define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
04426 /*@}*/
04427 /*******************************************************************************
04428  * HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
04429  ******************************************************************************/
04430 
04431 /*!
04432  * @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
04433  *
04434  * Reset value: 0x0000U
04435  *
04436  * If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
04437  * follows.
04438  */
04439 typedef union _hw_dma_tcdn_citer_elinkno
04440 {
04441     uint16_t U;
04442     struct _hw_dma_tcdn_citer_elinkno_bitfields
04443     {
04444         uint16_t CITER : 15;           /*!< [14:0] Current Major Iteration Count */
04445         uint16_t ELINK : 1;            /*!< [15] Enable channel-to-channel linking on
04446                                         * minor-loop complete */
04447     } B;
04448 } hw_dma_tcdn_citer_elinkno_t;
04449 
04450 /*!
04451  * @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
04452  */
04453 /*@{*/
04454 #define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
04455 
04456 #define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
04457 
04458 #define HW_DMA_TCDn_CITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_citer_elinkno_t *) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
04459 #define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_citer_elinkno_t, HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n)))
04460 #define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_citer_elinkno_t, HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), v))
04461 #define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) |  (v)))
04462 #define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
04463 #define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^  (v)))
04464 /*@}*/
04465 
04466 /*
04467  * Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
04468  */
04469 
04470 /*!
04471  * @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
04472  *
04473  * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
04474  * major loop count for the channel. It is decremented each time the minor loop is
04475  * completed and updated in the transfer control descriptor memory. After the
04476  * major iteration count is exhausted, the channel performs a number of operations
04477  * (e.g., final source and destination address calculations), optionally generating
04478  * an interrupt to signal channel completion before reloading the CITER field
04479  * from the beginning iteration count (BITER) field. When the CITER field is
04480  * initially loaded by software, it must be set to the same value as that contained in
04481  * the BITER field. If the channel is configured to execute a single service
04482  * request, the initial values of BITER and CITER should be 0x0001.
04483  */
04484 /*@{*/
04485 #define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER. */
04486 #define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER. */
04487 #define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER. */
04488 
04489 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field. */
04490 #define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (UNION_READ(hw_dma_tcdn_citer_elinkno_t, HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), U, B.CITER))
04491 
04492 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER. */
04493 #define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_CITER) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
04494 
04495 /*! @brief Set the CITER field to a new value. */
04496 #define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) | BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
04497 /*@}*/
04498 
04499 /*!
04500  * @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
04501  *
04502  * As the channel completes the minor loop, this flag enables linking to another
04503  * channel, defined by the LINKCH field. The link target channel initiates a
04504  * channel service request via an internal mechanism that sets the TCDn_CSR[START]
04505  * bit of the specified channel. If channel linking is disabled, the CITER value
04506  * is extended to 15 bits in place of a link channel number. If the major loop is
04507  * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
04508  * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
04509  * configuration error is reported.
04510  *
04511  * Values:
04512  * - 0 - The channel-to-channel linking is disabled
04513  * - 1 - The channel-to-channel linking is enabled
04514  */
04515 /*@{*/
04516 #define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK. */
04517 #define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK. */
04518 #define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK. */
04519 
04520 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field. */
04521 #define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK)))
04522 
04523 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK. */
04524 #define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKNO_ELINK) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
04525 
04526 /*! @brief Set the ELINK field to a new value. */
04527 #define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK), v))
04528 /*@}*/
04529 /*******************************************************************************
04530  * HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
04531  ******************************************************************************/
04532 
04533 /*!
04534  * @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
04535  *
04536  * Reset value: 0x0000U
04537  *
04538  * If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
04539  */
04540 typedef union _hw_dma_tcdn_citer_elinkyes
04541 {
04542     uint16_t U;
04543     struct _hw_dma_tcdn_citer_elinkyes_bitfields
04544     {
04545         uint16_t CITER : 9;            /*!< [8:0] Current Major Iteration Count */
04546         uint16_t LINKCH : 4;           /*!< [12:9] Link Channel Number */
04547         uint16_t RESERVED0 : 2;        /*!< [14:13]  */
04548         uint16_t ELINK : 1;            /*!< [15] Enable channel-to-channel linking on
04549                                         * minor-loop complete */
04550     } B;
04551 } hw_dma_tcdn_citer_elinkyes_t;
04552 
04553 /*!
04554  * @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
04555  */
04556 /*@{*/
04557 #define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
04558 
04559 #define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) ((x) + 0x1016U + (0x20U * (n)))
04560 
04561 #define HW_DMA_TCDn_CITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_citer_elinkyes_t *) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
04562 #define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_citer_elinkyes_t, HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n)))
04563 #define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_citer_elinkyes_t, HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), v))
04564 #define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) |  (v)))
04565 #define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
04566 #define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^  (v)))
04567 /*@}*/
04568 
04569 /*
04570  * Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
04571  */
04572 
04573 /*!
04574  * @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
04575  *
04576  * This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
04577  * major loop count for the channel. It is decremented each time the minor loop is
04578  * completed and updated in the transfer control descriptor memory. After the
04579  * major iteration count is exhausted, the channel performs a number of operations
04580  * (e.g., final source and destination address calculations), optionally generating
04581  * an interrupt to signal channel completion before reloading the CITER field
04582  * from the beginning iteration count (BITER) field. When the CITER field is
04583  * initially loaded by software, it must be set to the same value as that contained in
04584  * the BITER field. If the channel is configured to execute a single service
04585  * request, the initial values of BITER and CITER should be 0x0001.
04586  */
04587 /*@{*/
04588 #define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER. */
04589 #define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER. */
04590 #define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER. */
04591 
04592 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field. */
04593 #define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (UNION_READ(hw_dma_tcdn_citer_elinkyes_t, HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), U, B.CITER))
04594 
04595 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER. */
04596 #define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_CITER) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
04597 
04598 /*! @brief Set the CITER field to a new value. */
04599 #define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) | BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
04600 /*@}*/
04601 
04602 /*!
04603  * @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
04604  *
04605  * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
04606  * loop is exhausted, the eDMA engine initiates a channel service request to the
04607  * channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
04608  */
04609 /*@{*/
04610 #define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH. */
04611 #define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH. */
04612 #define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH. */
04613 
04614 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field. */
04615 #define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (UNION_READ(hw_dma_tcdn_citer_elinkyes_t, HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), U, B.LINKCH))
04616 
04617 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH. */
04618 #define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
04619 
04620 /*! @brief Set the LINKCH field to a new value. */
04621 #define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) | BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
04622 /*@}*/
04623 
04624 /*!
04625  * @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
04626  *
04627  * As the channel completes the minor loop, this flag enables linking to another
04628  * channel, defined by the LINKCH field. The link target channel initiates a
04629  * channel service request via an internal mechanism that sets the TCDn_CSR[START]
04630  * bit of the specified channel. If channel linking is disabled, the CITER value
04631  * is extended to 15 bits in place of a link channel number. If the major loop is
04632  * exhausted, this link mechanism is suppressed in favor of the MAJORELINK
04633  * channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
04634  * configuration error is reported.
04635  *
04636  * Values:
04637  * - 0 - The channel-to-channel linking is disabled
04638  * - 1 - The channel-to-channel linking is enabled
04639  */
04640 /*@{*/
04641 #define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK. */
04642 #define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK. */
04643 #define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK. */
04644 
04645 /*! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field. */
04646 #define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK)))
04647 
04648 /*! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK. */
04649 #define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CITER_ELINKYES_ELINK) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
04650 
04651 /*! @brief Set the ELINK field to a new value. */
04652 #define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK), v))
04653 /*@}*/
04654 /*******************************************************************************
04655  * HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
04656  ******************************************************************************/
04657 
04658 /*!
04659  * @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
04660  *
04661  * Reset value: 0x00000000U
04662  */
04663 typedef union _hw_dma_tcdn_dlastsga
04664 {
04665     uint32_t U;
04666     struct _hw_dma_tcdn_dlastsga_bitfields
04667     {
04668         uint32_t DLASTSGA : 32;        /*!< [31:0]  */
04669     } B;
04670 } hw_dma_tcdn_dlastsga_t;
04671 
04672 /*!
04673  * @name Constants and macros for entire DMA_TCDn_DLASTSGA register
04674  */
04675 /*@{*/
04676 #define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
04677 
04678 #define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) ((x) + 0x1018U + (0x20U * (n)))
04679 
04680 #define HW_DMA_TCDn_DLASTSGA(x, n) (*(__IO hw_dma_tcdn_dlastsga_t *) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
04681 #define HW_DMA_TCDn_DLASTSGA_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_dlastsga_t, HW_DMA_TCDn_DLASTSGA_ADDR(x, n)))
04682 #define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_dlastsga_t, HW_DMA_TCDn_DLASTSGA_ADDR(x, n), v))
04683 #define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) |  (v)))
04684 #define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
04685 #define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^  (v)))
04686 /*@}*/
04687 
04688 /*
04689  * Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
04690  */
04691 
04692 /*!
04693  * @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
04694  *
04695  * Destination last address adjustment or the memory address for the next
04696  * transfer control descriptor to be loaded into this channel (scatter/gather). If
04697  * (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
04698  * the completion of the major iteration count. This value can apply to restore the
04699  * destination address to the initial value or adjust the address to reference
04700  * the next data structure. This field uses two's complement notation for the
04701  * final destination address adjustment. Otherwise: This address points to the
04702  * beginning of a 0-modulo-32-byte region containing the next transfer control
04703  * descriptor to be loaded into this channel. This channel reload is performed as the
04704  * major iteration count completes. The scatter/gather address must be
04705  * 0-modulo-32-byte, else a configuration error is reported.
04706  */
04707 /*@{*/
04708 #define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) /*!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA. */
04709 #define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) /*!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA. */
04710 #define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) /*!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA. */
04711 
04712 /*! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field. */
04713 #define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
04714 
04715 /*! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA. */
04716 #define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) ((uint32_t)((uint32_t)(v) << BP_DMA_TCDn_DLASTSGA_DLASTSGA) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
04717 
04718 /*! @brief Set the DLASTSGA field to a new value. */
04719 #define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
04720 /*@}*/
04721 /*******************************************************************************
04722  * HW_DMA_TCDn_CSR - TCD Control and Status
04723  ******************************************************************************/
04724 
04725 /*!
04726  * @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
04727  *
04728  * Reset value: 0x0000U
04729  */
04730 typedef union _hw_dma_tcdn_csr
04731 {
04732     uint16_t U;
04733     struct _hw_dma_tcdn_csr_bitfields
04734     {
04735         uint16_t START : 1;            /*!< [0] Channel Start */
04736         uint16_t INTMAJOR : 1;         /*!< [1] Enable an interrupt when major
04737                                         * iteration count completes */
04738         uint16_t INTHALF : 1;          /*!< [2] Enable an interrupt when major counter
04739                                         * is half complete. */
04740         uint16_t DREQ : 1;             /*!< [3] Disable Request */
04741         uint16_t ESG : 1;              /*!< [4] Enable Scatter/Gather Processing */
04742         uint16_t MAJORELINK : 1;       /*!< [5] Enable channel-to-channel linking
04743                                         * on major loop complete */
04744         uint16_t ACTIVE : 1;           /*!< [6] Channel Active */
04745         uint16_t DONE : 1;             /*!< [7] Channel Done */
04746         uint16_t MAJORLINKCH : 4;      /*!< [11:8] Link Channel Number */
04747         uint16_t RESERVED0 : 2;        /*!< [13:12]  */
04748         uint16_t BWC : 2;              /*!< [15:14] Bandwidth Control */
04749     } B;
04750 } hw_dma_tcdn_csr_t;
04751 
04752 /*!
04753  * @name Constants and macros for entire DMA_TCDn_CSR register
04754  */
04755 /*@{*/
04756 #define HW_DMA_TCDn_CSR_COUNT (16U)
04757 
04758 #define HW_DMA_TCDn_CSR_ADDR(x, n) ((x) + 0x101CU + (0x20U * (n)))
04759 
04760 #define HW_DMA_TCDn_CSR(x, n)    (*(__IO hw_dma_tcdn_csr_t *) HW_DMA_TCDn_CSR_ADDR(x, n))
04761 #define HW_DMA_TCDn_CSR_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_csr_t, HW_DMA_TCDn_CSR_ADDR(x, n)))
04762 #define HW_DMA_TCDn_CSR_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_csr_t, HW_DMA_TCDn_CSR_ADDR(x, n), v))
04763 #define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) |  (v)))
04764 #define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
04765 #define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^  (v)))
04766 /*@}*/
04767 
04768 /*
04769  * Constants & macros for individual DMA_TCDn_CSR bitfields
04770  */
04771 
04772 /*!
04773  * @name Register DMA_TCDn_CSR, field START[0] (RW)
04774  *
04775  * If this flag is set, the channel is requesting service. The eDMA hardware
04776  * automatically clears this flag after the channel begins execution.
04777  *
04778  * Values:
04779  * - 0 - The channel is not explicitly started
04780  * - 1 - The channel is explicitly started via a software initiated service
04781  *     request
04782  */
04783 /*@{*/
04784 #define BP_DMA_TCDn_CSR_START (0U)         /*!< Bit position for DMA_TCDn_CSR_START. */
04785 #define BM_DMA_TCDn_CSR_START (0x0001U)    /*!< Bit mask for DMA_TCDn_CSR_START. */
04786 #define BS_DMA_TCDn_CSR_START (1U)         /*!< Bit field size in bits for DMA_TCDn_CSR_START. */
04787 
04788 /*! @brief Read current value of the DMA_TCDn_CSR_START field. */
04789 #define BR_DMA_TCDn_CSR_START(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START)))
04790 
04791 /*! @brief Format value for bitfield DMA_TCDn_CSR_START. */
04792 #define BF_DMA_TCDn_CSR_START(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_START) & BM_DMA_TCDn_CSR_START)
04793 
04794 /*! @brief Set the START field to a new value. */
04795 #define BW_DMA_TCDn_CSR_START(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START), v))
04796 /*@}*/
04797 
04798 /*!
04799  * @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
04800  *
04801  * If this flag is set, the channel generates an interrupt request by setting
04802  * the appropriate bit in the INT when the current major iteration count reaches
04803  * zero.
04804  *
04805  * Values:
04806  * - 0 - The end-of-major loop interrupt is disabled
04807  * - 1 - The end-of-major loop interrupt is enabled
04808  */
04809 /*@{*/
04810 #define BP_DMA_TCDn_CSR_INTMAJOR (1U)      /*!< Bit position for DMA_TCDn_CSR_INTMAJOR. */
04811 #define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) /*!< Bit mask for DMA_TCDn_CSR_INTMAJOR. */
04812 #define BS_DMA_TCDn_CSR_INTMAJOR (1U)      /*!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR. */
04813 
04814 /*! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field. */
04815 #define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR)))
04816 
04817 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR. */
04818 #define BF_DMA_TCDn_CSR_INTMAJOR(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTMAJOR) & BM_DMA_TCDn_CSR_INTMAJOR)
04819 
04820 /*! @brief Set the INTMAJOR field to a new value. */
04821 #define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR), v))
04822 /*@}*/
04823 
04824 /*!
04825  * @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
04826  *
04827  * If this flag is set, the channel generates an interrupt request by setting
04828  * the appropriate bit in the INT register when the current major iteration count
04829  * reaches the halfway point. Specifically, the comparison performed by the eDMA
04830  * engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
04831  * provided to support double-buffered (aka ping-pong) schemes or other types of data
04832  * movement where the processor needs an early indication of the transfer's
04833  * progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
04834  *
04835  * Values:
04836  * - 0 - The half-point interrupt is disabled
04837  * - 1 - The half-point interrupt is enabled
04838  */
04839 /*@{*/
04840 #define BP_DMA_TCDn_CSR_INTHALF (2U)       /*!< Bit position for DMA_TCDn_CSR_INTHALF. */
04841 #define BM_DMA_TCDn_CSR_INTHALF (0x0004U)  /*!< Bit mask for DMA_TCDn_CSR_INTHALF. */
04842 #define BS_DMA_TCDn_CSR_INTHALF (1U)       /*!< Bit field size in bits for DMA_TCDn_CSR_INTHALF. */
04843 
04844 /*! @brief Read current value of the DMA_TCDn_CSR_INTHALF field. */
04845 #define BR_DMA_TCDn_CSR_INTHALF(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF)))
04846 
04847 /*! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF. */
04848 #define BF_DMA_TCDn_CSR_INTHALF(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_INTHALF) & BM_DMA_TCDn_CSR_INTHALF)
04849 
04850 /*! @brief Set the INTHALF field to a new value. */
04851 #define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF), v))
04852 /*@}*/
04853 
04854 /*!
04855  * @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
04856  *
04857  * If this flag is set, the eDMA hardware automatically clears the corresponding
04858  * ERQ bit when the current major iteration count reaches zero.
04859  *
04860  * Values:
04861  * - 0 - The channel's ERQ bit is not affected
04862  * - 1 - The channel's ERQ bit is cleared when the major loop is complete
04863  */
04864 /*@{*/
04865 #define BP_DMA_TCDn_CSR_DREQ (3U)          /*!< Bit position for DMA_TCDn_CSR_DREQ. */
04866 #define BM_DMA_TCDn_CSR_DREQ (0x0008U)     /*!< Bit mask for DMA_TCDn_CSR_DREQ. */
04867 #define BS_DMA_TCDn_CSR_DREQ (1U)          /*!< Bit field size in bits for DMA_TCDn_CSR_DREQ. */
04868 
04869 /*! @brief Read current value of the DMA_TCDn_CSR_DREQ field. */
04870 #define BR_DMA_TCDn_CSR_DREQ(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ)))
04871 
04872 /*! @brief Format value for bitfield DMA_TCDn_CSR_DREQ. */
04873 #define BF_DMA_TCDn_CSR_DREQ(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DREQ) & BM_DMA_TCDn_CSR_DREQ)
04874 
04875 /*! @brief Set the DREQ field to a new value. */
04876 #define BW_DMA_TCDn_CSR_DREQ(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ), v))
04877 /*@}*/
04878 
04879 /*!
04880  * @name Register DMA_TCDn_CSR, field ESG[4] (RW)
04881  *
04882  * As the channel completes the major loop, this flag enables scatter/gather
04883  * processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
04884  * memory pointer to a 0-modulo-32 address containing a 32-byte data structure
04885  * loaded as the transfer control descriptor into the local memory. To support the
04886  * dynamic scatter/gather coherency model, this field is forced to zero when
04887  * written to while the TCDn_CSR[DONE] bit is set.
04888  *
04889  * Values:
04890  * - 0 - The current channel's TCD is normal format.
04891  * - 1 - The current channel's TCD specifies a scatter gather format. The
04892  *     DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
04893  *     channel after the major loop completes its execution.
04894  */
04895 /*@{*/
04896 #define BP_DMA_TCDn_CSR_ESG  (4U)          /*!< Bit position for DMA_TCDn_CSR_ESG. */
04897 #define BM_DMA_TCDn_CSR_ESG  (0x0010U)     /*!< Bit mask for DMA_TCDn_CSR_ESG. */
04898 #define BS_DMA_TCDn_CSR_ESG  (1U)          /*!< Bit field size in bits for DMA_TCDn_CSR_ESG. */
04899 
04900 /*! @brief Read current value of the DMA_TCDn_CSR_ESG field. */
04901 #define BR_DMA_TCDn_CSR_ESG(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG)))
04902 
04903 /*! @brief Format value for bitfield DMA_TCDn_CSR_ESG. */
04904 #define BF_DMA_TCDn_CSR_ESG(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ESG) & BM_DMA_TCDn_CSR_ESG)
04905 
04906 /*! @brief Set the ESG field to a new value. */
04907 #define BW_DMA_TCDn_CSR_ESG(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG), v))
04908 /*@}*/
04909 
04910 /*!
04911  * @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
04912  *
04913  * As the channel completes the major loop, this flag enables the linking to
04914  * another channel, defined by MAJORLINKCH. The link target channel initiates a
04915  * channel service request via an internal mechanism that sets the TCDn_CSR[START]
04916  * bit of the specified channel. To support the dynamic linking coherency model,
04917  * this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
04918  *
04919  * Values:
04920  * - 0 - The channel-to-channel linking is disabled
04921  * - 1 - The channel-to-channel linking is enabled
04922  */
04923 /*@{*/
04924 #define BP_DMA_TCDn_CSR_MAJORELINK (5U)    /*!< Bit position for DMA_TCDn_CSR_MAJORELINK. */
04925 #define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) /*!< Bit mask for DMA_TCDn_CSR_MAJORELINK. */
04926 #define BS_DMA_TCDn_CSR_MAJORELINK (1U)    /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK. */
04927 
04928 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field. */
04929 #define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK)))
04930 
04931 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK. */
04932 #define BF_DMA_TCDn_CSR_MAJORELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORELINK) & BM_DMA_TCDn_CSR_MAJORELINK)
04933 
04934 /*! @brief Set the MAJORELINK field to a new value. */
04935 #define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK), v))
04936 /*@}*/
04937 
04938 /*!
04939  * @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
04940  *
04941  * This flag signals the channel is currently in execution. It is set when
04942  * channel service begins, and the eDMA clears it as the minor loop completes or if
04943  * any error condition is detected. This bit resets to zero.
04944  */
04945 /*@{*/
04946 #define BP_DMA_TCDn_CSR_ACTIVE (6U)        /*!< Bit position for DMA_TCDn_CSR_ACTIVE. */
04947 #define BM_DMA_TCDn_CSR_ACTIVE (0x0040U)   /*!< Bit mask for DMA_TCDn_CSR_ACTIVE. */
04948 #define BS_DMA_TCDn_CSR_ACTIVE (1U)        /*!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE. */
04949 
04950 /*! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field. */
04951 #define BR_DMA_TCDn_CSR_ACTIVE(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE)))
04952 
04953 /*! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE. */
04954 #define BF_DMA_TCDn_CSR_ACTIVE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_ACTIVE) & BM_DMA_TCDn_CSR_ACTIVE)
04955 
04956 /*! @brief Set the ACTIVE field to a new value. */
04957 #define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE), v))
04958 /*@}*/
04959 
04960 /*!
04961  * @name Register DMA_TCDn_CSR, field DONE[7] (RW)
04962  *
04963  * This flag indicates the eDMA has completed the major loop. The eDMA engine
04964  * sets it as the CITER count reaches zero; The software clears it, or the hardware
04965  * when the channel is activated. This bit must be cleared to write the
04966  * MAJORELINK or ESG bits.
04967  */
04968 /*@{*/
04969 #define BP_DMA_TCDn_CSR_DONE (7U)          /*!< Bit position for DMA_TCDn_CSR_DONE. */
04970 #define BM_DMA_TCDn_CSR_DONE (0x0080U)     /*!< Bit mask for DMA_TCDn_CSR_DONE. */
04971 #define BS_DMA_TCDn_CSR_DONE (1U)          /*!< Bit field size in bits for DMA_TCDn_CSR_DONE. */
04972 
04973 /*! @brief Read current value of the DMA_TCDn_CSR_DONE field. */
04974 #define BR_DMA_TCDn_CSR_DONE(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE)))
04975 
04976 /*! @brief Format value for bitfield DMA_TCDn_CSR_DONE. */
04977 #define BF_DMA_TCDn_CSR_DONE(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_DONE) & BM_DMA_TCDn_CSR_DONE)
04978 
04979 /*! @brief Set the DONE field to a new value. */
04980 #define BW_DMA_TCDn_CSR_DONE(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE), v))
04981 /*@}*/
04982 
04983 /*!
04984  * @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
04985  *
04986  * If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
04987  * performed after the major loop counter is exhausted. else After the major loop
04988  * counter is exhausted, the eDMA engine initiates a channel service request at the
04989  * channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
04990  */
04991 /*@{*/
04992 #define BP_DMA_TCDn_CSR_MAJORLINKCH (8U)   /*!< Bit position for DMA_TCDn_CSR_MAJORLINKCH. */
04993 #define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) /*!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH. */
04994 #define BS_DMA_TCDn_CSR_MAJORLINKCH (4U)   /*!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH. */
04995 
04996 /*! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field. */
04997 #define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (UNION_READ(hw_dma_tcdn_csr_t, HW_DMA_TCDn_CSR_ADDR(x, n), U, B.MAJORLINKCH))
04998 
04999 /*! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH. */
05000 #define BF_DMA_TCDn_CSR_MAJORLINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_MAJORLINKCH) & BM_DMA_TCDn_CSR_MAJORLINKCH)
05001 
05002 /*! @brief Set the MAJORLINKCH field to a new value. */
05003 #define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) | BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
05004 /*@}*/
05005 
05006 /*!
05007  * @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
05008  *
05009  * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
05010  * the eDMA processes the minor loop, it continuously generates read/write
05011  * sequences until the minor count is exhausted. This field forces the eDMA to stall
05012  * after the completion of each read/write access to control the bus request
05013  * bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
05014  * this field is ignored between the first and second transfers and after the
05015  * last write of each minor loop. This behavior is a side effect of reducing
05016  * start-up latency.
05017  *
05018  * Values:
05019  * - 00 - No eDMA engine stalls
05020  * - 01 - Reserved
05021  * - 10 - eDMA engine stalls for 4 cycles after each r/w
05022  * - 11 - eDMA engine stalls for 8 cycles after each r/w
05023  */
05024 /*@{*/
05025 #define BP_DMA_TCDn_CSR_BWC  (14U)         /*!< Bit position for DMA_TCDn_CSR_BWC. */
05026 #define BM_DMA_TCDn_CSR_BWC  (0xC000U)     /*!< Bit mask for DMA_TCDn_CSR_BWC. */
05027 #define BS_DMA_TCDn_CSR_BWC  (2U)          /*!< Bit field size in bits for DMA_TCDn_CSR_BWC. */
05028 
05029 /*! @brief Read current value of the DMA_TCDn_CSR_BWC field. */
05030 #define BR_DMA_TCDn_CSR_BWC(x, n) (UNION_READ(hw_dma_tcdn_csr_t, HW_DMA_TCDn_CSR_ADDR(x, n), U, B.BWC))
05031 
05032 /*! @brief Format value for bitfield DMA_TCDn_CSR_BWC. */
05033 #define BF_DMA_TCDn_CSR_BWC(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_CSR_BWC) & BM_DMA_TCDn_CSR_BWC)
05034 
05035 /*! @brief Set the BWC field to a new value. */
05036 #define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) | BF_DMA_TCDn_CSR_BWC(v)))
05037 /*@}*/
05038 /*******************************************************************************
05039  * HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
05040  ******************************************************************************/
05041 
05042 /*!
05043  * @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
05044  *
05045  * Reset value: 0x0000U
05046  *
05047  * If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
05048  * as follows.
05049  */
05050 typedef union _hw_dma_tcdn_biter_elinkno
05051 {
05052     uint16_t U;
05053     struct _hw_dma_tcdn_biter_elinkno_bitfields
05054     {
05055         uint16_t BITER : 15;           /*!< [14:0] Starting Major Iteration Count */
05056         uint16_t ELINK : 1;            /*!< [15] Enables channel-to-channel linking on
05057                                         * minor loop complete */
05058     } B;
05059 } hw_dma_tcdn_biter_elinkno_t;
05060 
05061 /*!
05062  * @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
05063  */
05064 /*@{*/
05065 #define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
05066 
05067 #define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
05068 
05069 #define HW_DMA_TCDn_BITER_ELINKNO(x, n) (*(__IO hw_dma_tcdn_biter_elinkno_t *) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
05070 #define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_biter_elinkno_t, HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n)))
05071 #define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_biter_elinkno_t, HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), v))
05072 #define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) |  (v)))
05073 #define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
05074 #define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^  (v)))
05075 /*@}*/
05076 
05077 /*
05078  * Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
05079  */
05080 
05081 /*!
05082  * @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
05083  *
05084  * As the transfer control descriptor is first loaded by software, this 9-bit
05085  * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
05086  * field. As the major iteration count is exhausted, the contents of this field
05087  * are reloaded into the CITER field. When the software loads the TCD, this field
05088  * must be set equal to the corresponding CITER field; otherwise, a configuration
05089  * error is reported. As the major iteration count is exhausted, the contents of
05090  * this field is reloaded into the CITER field. If the channel is configured to
05091  * execute a single service request, the initial values of BITER and CITER should
05092  * be 0x0001.
05093  */
05094 /*@{*/
05095 #define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER. */
05096 #define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER. */
05097 #define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER. */
05098 
05099 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field. */
05100 #define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (UNION_READ(hw_dma_tcdn_biter_elinkno_t, HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), U, B.BITER))
05101 
05102 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER. */
05103 #define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_BITER) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
05104 
05105 /*! @brief Set the BITER field to a new value. */
05106 #define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) | BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
05107 /*@}*/
05108 
05109 /*!
05110  * @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
05111  *
05112  * As the channel completes the minor loop, this flag enables the linking to
05113  * another channel, defined by BITER[LINKCH]. The link target channel initiates a
05114  * channel service request via an internal mechanism that sets the TCDn_CSR[START]
05115  * bit of the specified channel. If channel linking is disabled, the BITER value
05116  * extends to 15 bits in place of a link channel number. If the major loop is
05117  * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
05118  * linking. When the software loads the TCD, this field must be set equal to the
05119  * corresponding CITER field; otherwise, a configuration error is reported. As the
05120  * major iteration count is exhausted, the contents of this field is reloaded
05121  * into the CITER field.
05122  *
05123  * Values:
05124  * - 0 - The channel-to-channel linking is disabled
05125  * - 1 - The channel-to-channel linking is enabled
05126  */
05127 /*@{*/
05128 #define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK. */
05129 #define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK. */
05130 #define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK. */
05131 
05132 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field. */
05133 #define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK)))
05134 
05135 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK. */
05136 #define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKNO_ELINK) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
05137 
05138 /*! @brief Set the ELINK field to a new value. */
05139 #define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK), v))
05140 /*@}*/
05141 /*******************************************************************************
05142  * HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
05143  ******************************************************************************/
05144 
05145 /*!
05146  * @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
05147  *
05148  * Reset value: 0x0000U
05149  *
05150  * If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
05151  * follows.
05152  */
05153 typedef union _hw_dma_tcdn_biter_elinkyes
05154 {
05155     uint16_t U;
05156     struct _hw_dma_tcdn_biter_elinkyes_bitfields
05157     {
05158         uint16_t BITER : 9;            /*!< [8:0] Starting Major Iteration Count */
05159         uint16_t LINKCH : 4;           /*!< [12:9] Link Channel Number */
05160         uint16_t RESERVED0 : 2;        /*!< [14:13]  */
05161         uint16_t ELINK : 1;            /*!< [15] Enables channel-to-channel linking on
05162                                         * minor loop complete */
05163     } B;
05164 } hw_dma_tcdn_biter_elinkyes_t;
05165 
05166 /*!
05167  * @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
05168  */
05169 /*@{*/
05170 #define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
05171 
05172 #define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) ((x) + 0x101EU + (0x20U * (n)))
05173 
05174 #define HW_DMA_TCDn_BITER_ELINKYES(x, n) (*(__IO hw_dma_tcdn_biter_elinkyes_t *) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
05175 #define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (ADDRESS_READ(hw_dma_tcdn_biter_elinkyes_t, HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n)))
05176 #define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (ADDRESS_WRITE(hw_dma_tcdn_biter_elinkyes_t, HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), v))
05177 #define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) |  (v)))
05178 #define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
05179 #define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^  (v)))
05180 /*@}*/
05181 
05182 /*
05183  * Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
05184  */
05185 
05186 /*!
05187  * @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
05188  *
05189  * As the transfer control descriptor is first loaded by software, this 9-bit
05190  * (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
05191  * field. As the major iteration count is exhausted, the contents of this field
05192  * are reloaded into the CITER field. When the software loads the TCD, this field
05193  * must be set equal to the corresponding CITER field; otherwise, a configuration
05194  * error is reported. As the major iteration count is exhausted, the contents of
05195  * this field is reloaded into the CITER field. If the channel is configured to
05196  * execute a single service request, the initial values of BITER and CITER should
05197  * be 0x0001.
05198  */
05199 /*@{*/
05200 #define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER. */
05201 #define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER. */
05202 #define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER. */
05203 
05204 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field. */
05205 #define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (UNION_READ(hw_dma_tcdn_biter_elinkyes_t, HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), U, B.BITER))
05206 
05207 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER. */
05208 #define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_BITER) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
05209 
05210 /*! @brief Set the BITER field to a new value. */
05211 #define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) | BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
05212 /*@}*/
05213 
05214 /*!
05215  * @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
05216  *
05217  * If channel-to-channel linking is enabled (ELINK = 1), then after the minor
05218  * loop is exhausted, the eDMA engine initiates a channel service request at the
05219  * channel defined by these four bits by setting that channel's TCDn_CSR[START]
05220  * bit. When the software loads the TCD, this field must be set equal to the
05221  * corresponding CITER field; otherwise, a configuration error is reported. As the major
05222  * iteration count is exhausted, the contents of this field is reloaded into the
05223  * CITER field.
05224  */
05225 /*@{*/
05226 #define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH. */
05227 #define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH. */
05228 #define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH. */
05229 
05230 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field. */
05231 #define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (UNION_READ(hw_dma_tcdn_biter_elinkyes_t, HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), U, B.LINKCH))
05232 
05233 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH. */
05234 #define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
05235 
05236 /*! @brief Set the LINKCH field to a new value. */
05237 #define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) | BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
05238 /*@}*/
05239 
05240 /*!
05241  * @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
05242  *
05243  * As the channel completes the minor loop, this flag enables the linking to
05244  * another channel, defined by BITER[LINKCH]. The link target channel initiates a
05245  * channel service request via an internal mechanism that sets the TCDn_CSR[START]
05246  * bit of the specified channel. If channel linking disables, the BITER value
05247  * extends to 15 bits in place of a link channel number. If the major loop is
05248  * exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
05249  * linking. When the software loads the TCD, this field must be set equal to the
05250  * corresponding CITER field; otherwise, a configuration error is reported. As the
05251  * major iteration count is exhausted, the contents of this field is reloaded into
05252  * the CITER field.
05253  *
05254  * Values:
05255  * - 0 - The channel-to-channel linking is disabled
05256  * - 1 - The channel-to-channel linking is enabled
05257  */
05258 /*@{*/
05259 #define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) /*!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK. */
05260 #define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) /*!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK. */
05261 #define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) /*!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK. */
05262 
05263 /*! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field. */
05264 #define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK)))
05265 
05266 /*! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK. */
05267 #define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) ((uint16_t)((uint16_t)(v) << BP_DMA_TCDn_BITER_ELINKYES_ELINK) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
05268 
05269 /*! @brief Set the ELINK field to a new value. */
05270 #define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK), v))
05271 /*@}*/
05272 
05273 /*
05274 ** Start of section using anonymous unions
05275 */
05276 
05277 #if defined(__ARMCC_VERSION)
05278   #pragma push
05279   #pragma anon_unions
05280 #elif defined(__CWCC__)
05281   #pragma push
05282   #pragma cpp_extensions on
05283 #elif defined(__GNUC__)
05284   /* anonymous unions are enabled by default */
05285 #elif defined(__IAR_SYSTEMS_ICC__)
05286   #pragma language=extended
05287 #else
05288   #error Not supported compiler type
05289 #endif
05290 
05291 /*******************************************************************************
05292  * hw_dma_t - module struct
05293  ******************************************************************************/
05294 /*!
05295  * @brief All DMA module registers.
05296  */
05297 #pragma pack(1)
05298 typedef struct _hw_dma
05299 {
05300     __IO hw_dma_cr_t CR ;                   /*!< [0x0] Control Register */
05301     __I hw_dma_es_t ES ;                    /*!< [0x4] Error Status Register */
05302     uint8_t _reserved0[4];
05303     __IO hw_dma_erq_t ERQ ;                 /*!< [0xC] Enable Request Register */
05304     uint8_t _reserved1[4];
05305     __IO hw_dma_eei_t EEI ;                 /*!< [0x14] Enable Error Interrupt Register */
05306     __O hw_dma_ceei_t CEEI ;                /*!< [0x18] Clear Enable Error Interrupt Register */
05307     __O hw_dma_seei_t SEEI ;                /*!< [0x19] Set Enable Error Interrupt Register */
05308     __O hw_dma_cerq_t CERQ ;                /*!< [0x1A] Clear Enable Request Register */
05309     __O hw_dma_serq_t SERQ ;                /*!< [0x1B] Set Enable Request Register */
05310     __O hw_dma_cdne_t CDNE ;                /*!< [0x1C] Clear DONE Status Bit Register */
05311     __O hw_dma_ssrt_t SSRT ;                /*!< [0x1D] Set START Bit Register */
05312     __O hw_dma_cerr_t CERR ;                /*!< [0x1E] Clear Error Register */
05313     __O hw_dma_cint_t CINT ;                /*!< [0x1F] Clear Interrupt Request Register */
05314     uint8_t _reserved2[4];
05315     __IO hw_dma_int_t INT ;                 /*!< [0x24] Interrupt Request Register */
05316     uint8_t _reserved3[4];
05317     __IO hw_dma_err_t ERR ;                 /*!< [0x2C] Error Register */
05318     uint8_t _reserved4[4];
05319     __I hw_dma_hrs_t HRS ;                  /*!< [0x34] Hardware Request Status Register */
05320     uint8_t _reserved5[200];
05321     __IO hw_dma_dchprin_t DCHPRIn [16];     /*!< [0x100] Channel n Priority Register */
05322     uint8_t _reserved6[3824];
05323     struct {
05324         __IO hw_dma_tcdn_saddr_t TCDn_SADDR ; /*!< [0x1000] TCD Source Address */
05325         __IO hw_dma_tcdn_soff_t TCDn_SOFF ; /*!< [0x1004] TCD Signed Source Address Offset */
05326         __IO hw_dma_tcdn_attr_t TCDn_ATTR ; /*!< [0x1006] TCD Transfer Attributes */
05327         union {
05328             __IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO ; /*!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled) */
05329             __IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO ; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
05330             __IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES ; /*!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
05331         };
05332         __IO hw_dma_tcdn_slast_t TCDn_SLAST ; /*!< [0x100C] TCD Last Source Address Adjustment */
05333         __IO hw_dma_tcdn_daddr_t TCDn_DADDR ; /*!< [0x1010] TCD Destination Address */
05334         __IO hw_dma_tcdn_doff_t TCDn_DOFF ; /*!< [0x1014] TCD Signed Destination Address Offset */
05335         union {
05336             __IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO ; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
05337             __IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES ; /*!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
05338         };
05339         __IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA ; /*!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address */
05340         __IO hw_dma_tcdn_csr_t TCDn_CSR ;   /*!< [0x101C] TCD Control and Status */
05341         union {
05342             __IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO ; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
05343             __IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES ; /*!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
05344         };
05345     } TCD[16];
05346 } hw_dma_t;
05347 #pragma pack()
05348 
05349 /*! @brief Macro to access all DMA registers. */
05350 /*! @param x DMA module instance base address. */
05351 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
05352  *     use the '&' operator, like <code>&HW_DMA(DMA_BASE)</code>. */
05353 #define HW_DMA(x)      (*(hw_dma_t *)(x))
05354 
05355 /*
05356 ** End of section using anonymous unions
05357 */
05358 
05359 #if defined(__ARMCC_VERSION)
05360   #pragma pop
05361 #elif defined(__CWCC__)
05362   #pragma pop
05363 #elif defined(__GNUC__)
05364   /* leave anonymous unions enabled */
05365 #elif defined(__IAR_SYSTEMS_ICC__)
05366   #pragma language=default
05367 #else
05368   #error Not supported compiler type
05369 #endif
05370 
05371 #endif /* __HW_DMA_REGISTERS_H__ */
05372 /* EOF */