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_hw_dma_dchprin Union Reference
HW_DMA_DCHPRIn - Channel n Priority Register (RW) More...
#include <MK64F12_dma.h>
Detailed Description
HW_DMA_DCHPRIn - Channel n Priority Register (RW)
Reset value: 0x00U
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these registers define the unique priorities associated with each channel . The channel priorities are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next priority, then 2, 3, etc. Software must program the channel priorities with unique values; otherwise, a configuration error is reported. The range of the priority value is limited to the values of 0 through 15.
Definition at line 3556 of file MK64F12_dma.h.
Generated on Sat Aug 27 2022 17:09:02 by
1.7.2