Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

readerComm.cpp@11:d5e8f47880f1, 2015-04-10 (annotated)

Committer:
soumi_ghsoh
Date:
Fri Apr 10 23:14:55 2015 +0000
Revision:
11:d5e8f47880f1
Parent:
10:98a58968dc7d
Child:
13:16a5b43ac874
pollNFC(), findNFC()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 2 Filename: readerComm.cpp
rwclough 1:1eb96189824d 3 Description: Functions used to communicate with the TRF7970 eval bd.
rwclough 1:1eb96189824d 4 Communication is by means of an SPI interface between
rwclough 1:1eb96189824d 5 the nRF51-DK board (nRF51422 MCU) and the TRF7970 eval bd.
rwclough 1:1eb96189824d 6 Copyright (C) 2015 Gymtrack, Inc.
rwclough 1:1eb96189824d 7 Author: Ron Clough
rwclough 1:1eb96189824d 8 Date: 2015-02-27
rwclough 1:1eb96189824d 9
rwclough 1:1eb96189824d 10 Changes:
rwclough 1:1eb96189824d 11 Rev Date Who Details
rwclough 1:1eb96189824d 12 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
rwclough 2:bd5afc5aa139 13 0.0 2015-02-27 RWC Original version.
rwclough 1:1eb96189824d 14
rwclough 1:1eb96189824d 15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
soumi_ghsoh 6:3c510c297e2f 16 /*==========================================================================
soumi_ghsoh 6:3c510c297e2f 17 Initialize the chipset ISO15693 and read UID:
soumi_ghsoh 6:3c510c297e2f 18 1) Reset
soumi_ghsoh 6:3c510c297e2f 19 [0x83]
soumi_ghsoh 6:3c510c297e2f 20 2) Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz))
soumi_ghsoh 6:3c510c297e2f 21 [0x09 0x31]
soumi_ghsoh 6:3c510c297e2f 22 3) Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4)
soumi_ghsoh 6:3c510c297e2f 23 [0x01 0x02]
soumi_ghsoh 6:3c510c297e2f 24 4) Turn RF ON (Chip Status Control Register (0x00))
soumi_ghsoh 6:3c510c297e2f 25 [0x40 r] [0x00 0x20] [0x40 r]
soumi_ghsoh 6:3c510c297e2f 26 5) Inventory Command (see Figure 5-20. Inventory Command Sent From MCU to TRF7970A)
soumi_ghsoh 6:3c510c297e2f 27 5-1) Send Inventory(8B), Wait 2ms, Read/Clear IRQ Status(0x0C=>0x6C)+dummy read,
soumi_ghsoh 6:3c510c297e2f 28 Read FIFO Status Register(0x1C/0x5C), Read Continuous FIFO from 0x1F to 0x1F+0x0A(0x1F/0x7F),
soumi_ghsoh 6:3c510c297e2f 29 Read/Clear IRQ Status(0x0C=>0x6C)+dummy read, Read FIFO Status Register(0x1C/0x5C),
soumi_ghsoh 6:3c510c297e2f 30 Reset FIFO(0x0F/0x8F), Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 31 [0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00] %:2 [0x6C r:2] [0x5C r] [0x7F r:10] %:10 [0x6C r:2] [0x5C r] [0x8F] [0x4F r]
soumi_ghsoh 6:3c510c297e2f 32 ==============================================================================*/
soumi_ghsoh 6:3c510c297e2f 33
soumi_ghsoh 6:3c510c297e2f 34
soumi_ghsoh 6:3c510c297e2f 35
soumi_ghsoh 6:3c510c297e2f 36
soumi_ghsoh 6:3c510c297e2f 37
rwclough 1:1eb96189824d 38
rwclough 1:1eb96189824d 39 #include "mbed.h"
rwclough 1:1eb96189824d 40 #include "readerComm.h"
soumi_ghsoh 11:d5e8f47880f1 41 uint8_t sg=0;
soumi_ghsoh 9:9266e0109d26 42 DigitalOut EN(p4); // Control EN pin on TRF7970
soumi_ghsoh 9:9266e0109d26 43 DigitalOut EN2(p3); // Control EN2 pin on TRF7970
soumi_ghsoh 5:93c612f43ec2 44 DigitalOut CS(p19);
soumi_ghsoh 5:93c612f43ec2 45 uint8_t turnRFOn[2];
soumi_ghsoh 5:93c612f43ec2 46 uint8_t testcommand[2];
soumi_ghsoh 7:96baf1b2fd07 47 extern uint8_t noBytes;
rwclough 2:bd5afc5aa139 48 extern SPI spi; // main.cpp
rwclough 2:bd5afc5aa139 49 extern Serial pc; // main.cpp
soumi_ghsoh 11:d5e8f47880f1 50 uint8_t buf[300]; // main.cpp
soumi_ghsoh 11:d5e8f47880f1 51 uint8_t found=0;
soumi_ghsoh 11:d5e8f47880f1 52 //extern bool tagFound=0;
soumi_ghsoh 11:d5e8f47880f1 53
rwclough 3:eaae5433ab45 54 extern DigitalOut debug1LED;
rwclough 3:eaae5433ab45 55 extern DigitalOut debug2LED;
rwclough 3:eaae5433ab45 56 extern DigitalOut ISO15693LED;
rwclough 3:eaae5433ab45 57 extern DigitalOut heartbeatLED;
rwclough 3:eaae5433ab45 58 extern DigitalOut testPin;
soumi_ghsoh 7:96baf1b2fd07 59 uint8_t temp;
soumi_ghsoh 7:96baf1b2fd07 60 uint8_t command[2];
rwclough 4:9ab0d84bbd07 61
soumi_ghsoh 11:d5e8f47880f1 62 uint8_t WAIT=0;
rwclough 4:9ab0d84bbd07 63 void trf797xDirectCommand(uint8_t *buffer)
rwclough 1:1eb96189824d 64 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 65 // trf797xDirectCommand()
rwclough 1:1eb96189824d 66 // Description: Transmit a Direct Command to the reader chip.
rwclough 1:1eb96189824d 67 // Parameter: *buffer = the direct command.
rwclough 1:1eb96189824d 68 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 69 {
rwclough 1:1eb96189824d 70 *buffer = (0x80 | *buffer); // Setup command mode
rwclough 2:bd5afc5aa139 71 *buffer = (0x9F & *buffer); // Setup command mode
rwclough 1:1eb96189824d 72 CS = SELECT;
rwclough 1:1eb96189824d 73 spi.write(*buffer);
rwclough 1:1eb96189824d 74 CS = DESELECT;
rwclough 4:9ab0d84bbd07 75 } // End of trf797xDirectCommand()
rwclough 1:1eb96189824d 76
rwclough 4:9ab0d84bbd07 77 void trf797xWriteSingle(uint8_t *buffer, uint8_t length)
rwclough 1:1eb96189824d 78 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 79 // trf797xWriteSingle()
rwclough 1:1eb96189824d 80 // Description: Writes to specified reader registers.
rwclough 1:1eb96189824d 81 // Parameters: *buffer = addresses of the registers followed by the
rwclough 2:bd5afc5aa139 82 // contents to write.
rwclough 1:1eb96189824d 83 // length = number of registers * 2.
rwclough 1:1eb96189824d 84 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 85 {
rwclough 2:bd5afc5aa139 86 uint8_t i=0;
rwclough 1:1eb96189824d 87
rwclough 1:1eb96189824d 88 CS = SELECT;
rwclough 1:1eb96189824d 89 while(length > 0) {
rwclough 2:bd5afc5aa139 90 *buffer = (0x1F & *buffer); // Register address
rwclough 1:1eb96189824d 91 for(i = 0; i < 2; i++) {
rwclough 1:1eb96189824d 92 spi.write(*buffer);
rwclough 1:1eb96189824d 93 buffer++;
rwclough 1:1eb96189824d 94 length--;
rwclough 2:bd5afc5aa139 95 }
rwclough 2:bd5afc5aa139 96 }
rwclough 1:1eb96189824d 97 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 98
rwclough 4:9ab0d84bbd07 99 } // End of trf797xWriteSingle()
rwclough 1:1eb96189824d 100
rwclough 4:9ab0d84bbd07 101 void trf797xReadSingle(uint8_t *buffer, uint8_t number)
rwclough 1:1eb96189824d 102 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 103 // trf797xReadSingle()
rwclough 1:1eb96189824d 104 // Description: Reads specified reader chip registers and
rwclough 1:1eb96189824d 105 // writes register contents to *buffer.
rwclough 1:1eb96189824d 106 // Parameters: *buffer = addresses of the registers.
rwclough 1:1eb96189824d 107 // number = number of registers.
rwclough 1:1eb96189824d 108 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 109 {
rwclough 1:1eb96189824d 110 CS = SELECT;
rwclough 1:1eb96189824d 111 while(number > 0) {
rwclough 1:1eb96189824d 112 *buffer = (0x40 | *buffer); // Address, read, single
rwclough 2:bd5afc5aa139 113 *buffer = (0x5F & *buffer); // Register address
rwclough 3:eaae5433ab45 114 spi.write(*buffer);
rwclough 2:bd5afc5aa139 115 *buffer = spi.write(0x00); // *buffer <- register contents
rwclough 1:1eb96189824d 116 buffer++;
rwclough 1:1eb96189824d 117 number--;
rwclough 2:bd5afc5aa139 118 }
rwclough 2:bd5afc5aa139 119 CS = DESELECT;
rwclough 4:9ab0d84bbd07 120 } // End of trf797xReadSingle()
rwclough 2:bd5afc5aa139 121
rwclough 4:9ab0d84bbd07 122 void trf797xReadContinuous(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 123 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 124 // trf797xReadContinuous()
rwclough 2:bd5afc5aa139 125 // Description: Used in SPI mode to read a specified number of
rwclough 2:bd5afc5aa139 126 // reader chip registers from a specified address upwards.
rwclough 2:bd5afc5aa139 127 // Contents of the registers are stored in *buffer.
rwclough 4:9ab0d84bbd07 128 // 1) Read register(s)
rwclough 4:9ab0d84bbd07 129 // 2) Write contents to *buffer
rwclough 2:bd5afc5aa139 130 // Parameters: *buffer = address of first register.
rwclough 2:bd5afc5aa139 131 // length = number of registers to read.
rwclough 2:bd5afc5aa139 132 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 5:93c612f43ec2 133 { //==================tested wrk $sg
rwclough 2:bd5afc5aa139 134 CS = SELECT;
rwclough 2:bd5afc5aa139 135 *buffer = (0x60 | *buffer); // Address, read, continuous
rwclough 3:eaae5433ab45 136 *buffer = (0x7F & *buffer); // Register address
rwclough 2:bd5afc5aa139 137 spi.write(*buffer);
rwclough 2:bd5afc5aa139 138 while(length > 0) {
rwclough 2:bd5afc5aa139 139 *buffer = spi.write(0x00);
rwclough 2:bd5afc5aa139 140 buffer++;
rwclough 2:bd5afc5aa139 141 length--;
rwclough 3:eaae5433ab45 142 }
rwclough 4:9ab0d84bbd07 143 // spi.write(0x00); spi.write(0x00); // 16 clock cycles, see TRF7970A FW Design Hints SLOA159 section 7.3
rwclough 1:1eb96189824d 144 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 145
soumi_ghsoh 5:93c612f43ec2 146 //=====================tested it wrks $sg
rwclough 4:9ab0d84bbd07 147 } // End of trf797xReadContinuous()
rwclough 2:bd5afc5aa139 148
rwclough 4:9ab0d84bbd07 149 void trf797xRawWrite(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 150 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 151 // trf797xRawWrite()
rwclough 2:bd5afc5aa139 152 // Description: Used in SPI mode to write direct to the reader chip.
rwclough 2:bd5afc5aa139 153 // Parameters: *buffer = raw data
rwclough 2:bd5afc5aa139 154 // length = number of data bytes
rwclough 2:bd5afc5aa139 155 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 156 {
rwclough 2:bd5afc5aa139 157 CS = SELECT;
rwclough 2:bd5afc5aa139 158 while(length > 0) {
rwclough 2:bd5afc5aa139 159 temp = spi.write(*buffer);
rwclough 2:bd5afc5aa139 160 buffer++;
rwclough 2:bd5afc5aa139 161 length--;
rwclough 2:bd5afc5aa139 162 }
rwclough 2:bd5afc5aa139 163 CS = DESELECT;
rwclough 4:9ab0d84bbd07 164 } // End of trf797xRawWrite()
rwclough 2:bd5afc5aa139 165
rwclough 4:9ab0d84bbd07 166 void trf797xStopDecoders(void)
rwclough 2:bd5afc5aa139 167 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 168 // trf797xStopDecoders()
rwclough 2:bd5afc5aa139 169 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 170 {
rwclough 2:bd5afc5aa139 171 command[0] = STOP_DECODERS;
rwclough 4:9ab0d84bbd07 172 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 173 }
rwclough 1:1eb96189824d 174
rwclough 4:9ab0d84bbd07 175 void trf797xRunDecoders(void)
rwclough 2:bd5afc5aa139 176 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 177 // trf797xRunDecoders()
rwclough 2:bd5afc5aa139 178 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 179 {
rwclough 2:bd5afc5aa139 180 command[0] = RUN_DECODERS;
rwclough 4:9ab0d84bbd07 181 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 182 }
rwclough 2:bd5afc5aa139 183
soumi_ghsoh 5:93c612f43ec2 184
soumi_ghsoh 10:98a58968dc7d 185 void PowerUpNFC2(void)
soumi_ghsoh 9:9266e0109d26 186 {//CS = 1;
soumi_ghsoh 9:9266e0109d26 187 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 188 // EN = 1;
soumi_ghsoh 9:9266e0109d26 189 // EN2=1;
soumi_ghsoh 9:9266e0109d26 190
soumi_ghsoh 9:9266e0109d26 191 CS = 0; EN2 = 0; EN = 0;
soumi_ghsoh 9:9266e0109d26 192 wait_ms(2);
soumi_ghsoh 9:9266e0109d26 193 CS = 1;
soumi_ghsoh 9:9266e0109d26 194 wait_ms(3);
soumi_ghsoh 9:9266e0109d26 195 EN2 = 1;
soumi_ghsoh 9:9266e0109d26 196 wait_ms(1);
soumi_ghsoh 9:9266e0109d26 197 EN = 1;
soumi_ghsoh 9:9266e0109d26 198 }
soumi_ghsoh 10:98a58968dc7d 199 void PowerUpNFC(void)
soumi_ghsoh 11:d5e8f47880f1 200 { //CS = 1;
soumi_ghsoh 9:9266e0109d26 201 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 202 // EN = 1;
soumi_ghsoh 11:d5e8f47880f1 203 EN2 = 1;
soumi_ghsoh 11:d5e8f47880f1 204 wait_ms(1);
soumi_ghsoh 11:d5e8f47880f1 205 EN=1;
soumi_ghsoh 6:3c510c297e2f 206 }
soumi_ghsoh 6:3c510c297e2f 207 void PowerDownNFC(void)
soumi_ghsoh 10:98a58968dc7d 208 {///CS=1;
soumi_ghsoh 11:d5e8f47880f1 209 EN=0;
soumi_ghsoh 11:d5e8f47880f1 210 EN2=0;
soumi_ghsoh 9:9266e0109d26 211 //wait_ms(1);
soumi_ghsoh 10:98a58968dc7d 212 //EN2= 0; PowerDown Mode
soumi_ghsoh 10:98a58968dc7d 213 //EN2=1; SleepMode
soumi_ghsoh 10:98a58968dc7d 214 //CS=0;
soumi_ghsoh 5:93c612f43ec2 215 }
soumi_ghsoh 11:d5e8f47880f1 216 void SleepNFC(void)
soumi_ghsoh 11:d5e8f47880f1 217 { EN=0;
soumi_ghsoh 11:d5e8f47880f1 218 EN2=0;
soumi_ghsoh 11:d5e8f47880f1 219 }
soumi_ghsoh 10:98a58968dc7d 220 void StandByNFC(void)
soumi_ghsoh 11:d5e8f47880f1 221 {
soumi_ghsoh 10:98a58968dc7d 222 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 10:98a58968dc7d 223 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 224
soumi_ghsoh 10:98a58968dc7d 225 turnRFOn[1] &= 0x3F;
soumi_ghsoh 10:98a58968dc7d 226 turnRFOn[1] |= 0x80;
soumi_ghsoh 11:d5e8f47880f1 227 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 11:d5e8f47880f1 228 }
soumi_ghsoh 11:d5e8f47880f1 229
soumi_ghsoh 5:93c612f43ec2 230 void SpiInit1(void)
soumi_ghsoh 5:93c612f43ec2 231 {
soumi_ghsoh 5:93c612f43ec2 232 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 233 spi.frequency(250000);
soumi_ghsoh 5:93c612f43ec2 234 }
soumi_ghsoh 5:93c612f43ec2 235
soumi_ghsoh 6:3c510c297e2f 236 void SpiInit(void)
soumi_ghsoh 5:93c612f43ec2 237 {
soumi_ghsoh 5:93c612f43ec2 238 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 239 spi.frequency(1000000);
soumi_ghsoh 5:93c612f43ec2 240 }
soumi_ghsoh 5:93c612f43ec2 241
soumi_ghsoh 5:93c612f43ec2 242 void NFCInit(void)
soumi_ghsoh 9:9266e0109d26 243 {testPin=1;
soumi_ghsoh 6:3c510c297e2f 244 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 245 testcommand[0] = SOFT_INIT;
soumi_ghsoh 5:93c612f43ec2 246 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 247 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 248 testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 249 trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 250 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 251 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 252 testcommand[1] = 0x21; // 6.78 MHz, OOK 100%
soumi_ghsoh 5:93c612f43ec2 253 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 254 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 255 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 256 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 257 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 258 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 259 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 260 turnRFOn[1] |= 0x20;
soumi_ghsoh 10:98a58968dc7d 261
soumi_ghsoh 6:3c510c297e2f 262 // Oroiginal code has 0x20 !!!
soumi_ghsoh 6:3c510c297e2f 263 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 6:3c510c297e2f 264 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 265 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 266 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 267 turnRFOn[1] |= 0x20;
soumi_ghsoh 6:3c510c297e2f 268 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 6:3c510c297e2f 269 //wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 270
soumi_ghsoh 6:3c510c297e2f 271 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 272 testcommand[1] = 0x02; // 6.78 MHz, OOK 100%
soumi_ghsoh 6:3c510c297e2f 273 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 10:98a58968dc7d 274 testcommand[0] = IRQ_MASK;
soumi_ghsoh 10:98a58968dc7d 275 testcommand[1] = 0x3F;
soumi_ghsoh 10:98a58968dc7d 276 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 277 //wait_ms(6);
soumi_ghsoh 9:9266e0109d26 278 testPin=0;}
soumi_ghsoh 5:93c612f43ec2 279
soumi_ghsoh 5:93c612f43ec2 280 void RegisterReInitNFC(void)
soumi_ghsoh 5:93c612f43ec2 281 {testcommand[0] = TX_TIMER_EPC_HIGH;
soumi_ghsoh 5:93c612f43ec2 282 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 283 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 284 testcommand[0] = TX_TIMER_EPC_LOW ;
soumi_ghsoh 5:93c612f43ec2 285 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 286 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 287 testcommand[0] = TX_PULSE_LENGTH_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 288 testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 289 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 290 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 291 testcommand[1] = 0x30;
soumi_ghsoh 5:93c612f43ec2 292 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 293 testcommand[0] = RX_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 294 testcommand[1] = 0x1F;
soumi_ghsoh 5:93c612f43ec2 295 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 296 testcommand[0] = MODULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 297 testcommand[1] = 0x21; //0x34 100%ook@13MHz
soumi_ghsoh 5:93c612f43ec2 298 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 299 testcommand[0] = RX_SPECIAL_SETTINGS ;
soumi_ghsoh 6:3c510c297e2f 300 testcommand[1] = 0x40;
soumi_ghsoh 5:93c612f43ec2 301 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 302 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 303 testcommand[1] = 0x87;
soumi_ghsoh 5:93c612f43ec2 304 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 305 }
soumi_ghsoh 6:3c510c297e2f 306
soumi_ghsoh 6:3c510c297e2f 307
soumi_ghsoh 6:3c510c297e2f 308 void RegistersReadNFC(void)
soumi_ghsoh 10:98a58968dc7d 309 {turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 10:98a58968dc7d 310 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 10:98a58968dc7d 311 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 10:98a58968dc7d 312 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 313 testcommand[0] = TX_TIMER_EPC_HIGH; //0xC1;
soumi_ghsoh 6:3c510c297e2f 314 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 315 testcommand[0] = TX_TIMER_EPC_LOW ; //0xC1;
soumi_ghsoh 6:3c510c297e2f 316 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 317 testcommand[0] = TX_PULSE_LENGTH_CONTROL ; //0x00;
soumi_ghsoh 6:3c510c297e2f 318 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 319 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ; //0x30;
soumi_ghsoh 6:3c510c297e2f 320 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 321 testcommand[0] = RX_WAIT_TIME ; //0x1F;
soumi_ghsoh 6:3c510c297e2f 322 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 323 testcommand[0] = MODULATOR_CONTROL ; //0x21;
soumi_ghsoh 6:3c510c297e2f 324 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 325 testcommand[0] = RX_SPECIAL_SETTINGS ; //0x40;
soumi_ghsoh 6:3c510c297e2f 326 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 327 testcommand[0] = REGULATOR_CONTROL ; //0x87;
soumi_ghsoh 6:3c510c297e2f 328 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 329 }
soumi_ghsoh 6:3c510c297e2f 330
soumi_ghsoh 6:3c510c297e2f 331 void InventoryReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 332 {
soumi_ghsoh 6:3c510c297e2f 333 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 334 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 335 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 336 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 337 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 338 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 339 buf[5]=0x26;
soumi_ghsoh 6:3c510c297e2f 340 buf[6]=0x01;
soumi_ghsoh 6:3c510c297e2f 341 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 342 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 11:d5e8f47880f1 343 //wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 344 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 345 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 346 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 347 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 348 wait_ms(5);
soumi_ghsoh 7:96baf1b2fd07 349 /*====================================read tag ID
soumi_ghsoh 6:3c510c297e2f 350 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 351 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 352 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 353 trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 354 testcommand[0] = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 6:3c510c297e2f 355 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 356 testcommand[0] = 0x7F & testcommand[0]; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 357 buf[0] = FIFO;
soumi_ghsoh 6:3c510c297e2f 358 trf797xReadContinuous(&buf[0], testcommand[0]);
soumi_ghsoh 6:3c510c297e2f 359 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 360 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 361 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 362 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 363 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 364 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 365 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 366 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 367 trf797xStopDecoders();
soumi_ghsoh 7:96baf1b2fd07 368 trf797xRunDecoders(); */
soumi_ghsoh 7:96baf1b2fd07 369 //=====================================read Tag ID
soumi_ghsoh 6:3c510c297e2f 370 //wait(1);
soumi_ghsoh 7:96baf1b2fd07 371 }
soumi_ghsoh 7:96baf1b2fd07 372
soumi_ghsoh 11:d5e8f47880f1 373 void FindNFC(uint8_t *irqStatus)
soumi_ghsoh 11:d5e8f47880f1 374 {//found=0;
soumi_ghsoh 11:d5e8f47880f1 375 //static uint8_t sg;
soumi_ghsoh 11:d5e8f47880f1 376 //printf("%X \r\n", *irqStatus);
soumi_ghsoh 11:d5e8f47880f1 377
soumi_ghsoh 11:d5e8f47880f1 378 switch(*irqStatus)
soumi_ghsoh 11:d5e8f47880f1 379 {case BIT0: found=BIT0; WAIT=10; break;
soumi_ghsoh 11:d5e8f47880f1 380 case BIT1: found=BIT1; break;
soumi_ghsoh 11:d5e8f47880f1 381 // case BIT2://found=BIT2; // break;
soumi_ghsoh 11:d5e8f47880f1 382 //case BIT3:found=BIT3; WAIT=0;break;
soumi_ghsoh 11:d5e8f47880f1 383 // case BIT4:found=BIT4; WAIT=0;break;
soumi_ghsoh 11:d5e8f47880f1 384 // case BIT5:found=BIT5; WAIT=0;break;
soumi_ghsoh 11:d5e8f47880f1 385 case 0x40: found=0x40; break;
soumi_ghsoh 11:d5e8f47880f1 386 case BIT7: found=BIT7; break;
soumi_ghsoh 11:d5e8f47880f1 387 default: found=0;
soumi_ghsoh 11:d5e8f47880f1 388 }
soumi_ghsoh 11:d5e8f47880f1 389
soumi_ghsoh 11:d5e8f47880f1 390
soumi_ghsoh 6:3c510c297e2f 391 }
soumi_ghsoh 7:96baf1b2fd07 392 void handlerNFC(void)
soumi_ghsoh 7:96baf1b2fd07 393 {
soumi_ghsoh 7:96baf1b2fd07 394 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 395 trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 396 FindNFC(testcommand);
soumi_ghsoh 11:d5e8f47880f1 397 //wait_ms(1);
soumi_ghsoh 11:d5e8f47880f1 398 //=============================use if trf7970a irq_status is not cleared
soumi_ghsoh 11:d5e8f47880f1 399 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 11:d5e8f47880f1 400 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 401 //=============================
soumi_ghsoh 7:96baf1b2fd07 402 }
soumi_ghsoh 6:3c510c297e2f 403
soumi_ghsoh 7:96baf1b2fd07 404
soumi_ghsoh 7:96baf1b2fd07 405 void MemReadReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 406 {testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 407 testcommand[1] = 0xFF;
soumi_ghsoh 6:3c510c297e2f 408 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 409 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 410 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 411 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 412 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 413 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 414 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 415 buf[5]=0x02;
soumi_ghsoh 6:3c510c297e2f 416 buf[6]=0x20;
soumi_ghsoh 6:3c510c297e2f 417 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 418 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 11:d5e8f47880f1 419 //wait_ms(2);
soumi_ghsoh 11:d5e8f47880f1 420 //testPin=1;
soumi_ghsoh 11:d5e8f47880f1 421 //=========================use to clear irq_status register of trf7970a
soumi_ghsoh 11:d5e8f47880f1 422 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 11:d5e8f47880f1 423 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 424 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 11:d5e8f47880f1 425 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 426 //==========================
soumi_ghsoh 6:3c510c297e2f 427 wait_ms(5);
soumi_ghsoh 7:96baf1b2fd07 428 }
soumi_ghsoh 7:96baf1b2fd07 429 void ReadNFC(void)
soumi_ghsoh 7:96baf1b2fd07 430 {/*========================================== read irqstatus reg. of trf7970a
soumi_ghsoh 7:96baf1b2fd07 431 //testcommand[0] = IRQ_STATUS; clear irqstatus reg of trf7970a
soumi_ghsoh 7:96baf1b2fd07 432 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 433 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 434 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 435 ===========================================*/
soumi_ghsoh 7:96baf1b2fd07 436
soumi_ghsoh 7:96baf1b2fd07 437 noBytes = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 7:96baf1b2fd07 438 trf797xReadSingle(&noBytes, 1);
soumi_ghsoh 7:96baf1b2fd07 439 noBytes = 0x7F & noBytes; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 440 buf[0] = FIFO;
soumi_ghsoh 7:96baf1b2fd07 441 trf797xReadContinuous(&buf[0],noBytes);
soumi_ghsoh 11:d5e8f47880f1 442 //==use if trf7970a irq_status is not cleared
soumi_ghsoh 11:d5e8f47880f1 443 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 11:d5e8f47880f1 444 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 445 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 11:d5e8f47880f1 446 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 447 //=========================================
soumi_ghsoh 6:3c510c297e2f 448 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 449 trf797xDirectCommand(testcommand);
soumi_ghsoh 7:96baf1b2fd07 450
soumi_ghsoh 6:3c510c297e2f 451 //wait(1);
soumi_ghsoh 9:9266e0109d26 452 }
soumi_ghsoh 11:d5e8f47880f1 453
soumi_ghsoh 11:d5e8f47880f1 454 bool PollNFC(void)
soumi_ghsoh 11:d5e8f47880f1 455 {
soumi_ghsoh 11:d5e8f47880f1 456 CS=1;
soumi_ghsoh 11:d5e8f47880f1 457 PowerUpNFC();
soumi_ghsoh 11:d5e8f47880f1 458 //////wait_ms(1);
soumi_ghsoh 11:d5e8f47880f1 459 NFCInit();
soumi_ghsoh 11:d5e8f47880f1 460 RegisterReInitNFC();
soumi_ghsoh 11:d5e8f47880f1 461 MemReadReqNFC(); //InventoryReqNFC()
soumi_ghsoh 11:d5e8f47880f1 462
soumi_ghsoh 11:d5e8f47880f1 463 wait_ms(WAIT);
soumi_ghsoh 11:d5e8f47880f1 464
soumi_ghsoh 11:d5e8f47880f1 465 switch(found)
soumi_ghsoh 11:d5e8f47880f1 466 {case BIT0:
soumi_ghsoh 11:d5e8f47880f1 467 printf("no response:");
soumi_ghsoh 11:d5e8f47880f1 468 printf("%X \r\n",found);
soumi_ghsoh 11:d5e8f47880f1 469 found=0;
soumi_ghsoh 11:d5e8f47880f1 470 WAIT=0;
soumi_ghsoh 11:d5e8f47880f1 471 break;
soumi_ghsoh 11:d5e8f47880f1 472 // //case BIT1:
soumi_ghsoh 11:d5e8f47880f1 473 // //case BIT2:
soumi_ghsoh 11:d5e8f47880f1 474 // //case BIT3:
soumi_ghsoh 11:d5e8f47880f1 475 //// case BIT4:
soumi_ghsoh 11:d5e8f47880f1 476 //// case BIT5:
soumi_ghsoh 11:d5e8f47880f1 477 case BIT6:
soumi_ghsoh 11:d5e8f47880f1 478 ReadNFC();
soumi_ghsoh 11:d5e8f47880f1 479 PowerDownNFC(); //SleepNFC() //StandByNFC()
soumi_ghsoh 11:d5e8f47880f1 480 found=1;
soumi_ghsoh 11:d5e8f47880f1 481 WAIT=0;
soumi_ghsoh 11:d5e8f47880f1 482 break;
soumi_ghsoh 11:d5e8f47880f1 483 case BIT7:
soumi_ghsoh 11:d5e8f47880f1 484 printf("tx complete:");
soumi_ghsoh 11:d5e8f47880f1 485 printf("%X \r\n",found);
soumi_ghsoh 11:d5e8f47880f1 486 found=0;
soumi_ghsoh 11:d5e8f47880f1 487 WAIT=0;
soumi_ghsoh 11:d5e8f47880f1 488 break;
soumi_ghsoh 11:d5e8f47880f1 489 default: found=0;
soumi_ghsoh 11:d5e8f47880f1 490 }
soumi_ghsoh 11:d5e8f47880f1 491 //
soumi_ghsoh 11:d5e8f47880f1 492 //
soumi_ghsoh 11:d5e8f47880f1 493 ////InventoryReqNFC();
soumi_ghsoh 11:d5e8f47880f1 494 ////if(found==1)
soumi_ghsoh 11:d5e8f47880f1 495 ////{
soumi_ghsoh 11:d5e8f47880f1 496 ////ReadNFC();
soumi_ghsoh 11:d5e8f47880f1 497 ////printf("tag id:");
soumi_ghsoh 11:d5e8f47880f1 498 ////for(uint8_t i=0; i<noBytes; i++)
soumi_ghsoh 11:d5e8f47880f1 499 ////printf("%X ", buf[i]);
soumi_ghsoh 11:d5e8f47880f1 500 ////printf("\r\n");
soumi_ghsoh 11:d5e8f47880f1 501 ////found=0;
soumi_ghsoh 11:d5e8f47880f1 502 ////}
soumi_ghsoh 11:d5e8f47880f1 503 ////else
soumi_ghsoh 11:d5e8f47880f1 504 //{printf("tnf2 \r\n");
soumi_ghsoh 11:d5e8f47880f1 505 //}
soumi_ghsoh 11:d5e8f47880f1 506
soumi_ghsoh 11:d5e8f47880f1 507 return found;
soumi_ghsoh 11:d5e8f47880f1 508
soumi_ghsoh 11:d5e8f47880f1 509 }