Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

readerComm.cpp@13:16a5b43ac874, 2015-04-30 (annotated)

Committer:
soumi_ghsoh
Date:
Thu Apr 30 23:30:55 2015 +0000
Revision:
13:16a5b43ac874
Parent:
11:d5e8f47880f1 
2015apr30

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 2 Filename: readerComm.cpp
rwclough 1:1eb96189824d 3 Description: Functions used to communicate with the TRF7970 eval bd.
rwclough 1:1eb96189824d 4 Communication is by means of an SPI interface between
rwclough 1:1eb96189824d 5 the nRF51-DK board (nRF51422 MCU) and the TRF7970 eval bd.
rwclough 1:1eb96189824d 6 Copyright (C) 2015 Gymtrack, Inc.
rwclough 1:1eb96189824d 7 Author: Ron Clough
rwclough 1:1eb96189824d 8 Date: 2015-02-27
soumi_ghsoh 13:16a5b43ac874 9
rwclough 1:1eb96189824d 10 Changes:
rwclough 1:1eb96189824d 11 Rev Date Who Details
rwclough 1:1eb96189824d 12 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
rwclough 2:bd5afc5aa139 13 0.0 2015-02-27 RWC Original version.
soumi_ghsoh 13:16a5b43ac874 14
rwclough 1:1eb96189824d 15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
soumi_ghsoh 6:3c510c297e2f 16 /*==========================================================================
soumi_ghsoh 6:3c510c297e2f 17 Initialize the chipset ISO15693 and read UID:
soumi_ghsoh 6:3c510c297e2f 18 1) Reset
soumi_ghsoh 6:3c510c297e2f 19 [0x83]
soumi_ghsoh 6:3c510c297e2f 20 2) Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz))
soumi_ghsoh 6:3c510c297e2f 21 [0x09 0x31]
soumi_ghsoh 6:3c510c297e2f 22 3) Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4)
soumi_ghsoh 13:16a5b43ac874 23 [0x01 0x02]
soumi_ghsoh 6:3c510c297e2f 24 4) Turn RF ON (Chip Status Control Register (0x00))
soumi_ghsoh 6:3c510c297e2f 25 [0x40 r] [0x00 0x20] [0x40 r]
soumi_ghsoh 6:3c510c297e2f 26 5) Inventory Command (see Figure 5-20. Inventory Command Sent From MCU to TRF7970A)
soumi_ghsoh 13:16a5b43ac874 27 5-1) Send Inventory(8B), Wait 2ms, Read/Clear IRQ Status(0x0C=>0x6C)+dummy read,
soumi_ghsoh 13:16a5b43ac874 28 Read FIFO Status Register(0x1C/0x5C), Read Continuous FIFO from 0x1F to 0x1F+0x0A(0x1F/0x7F),
soumi_ghsoh 13:16a5b43ac874 29 Read/Clear IRQ Status(0x0C=>0x6C)+dummy read, Read FIFO Status Register(0x1C/0x5C),
soumi_ghsoh 6:3c510c297e2f 30 Reset FIFO(0x0F/0x8F), Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 31 [0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00] %:2 [0x6C r:2] [0x5C r] [0x7F r:10] %:10 [0x6C r:2] [0x5C r] [0x8F] [0x4F r]
soumi_ghsoh 13:16a5b43ac874 32 ==============================================================================*/
soumi_ghsoh 6:3c510c297e2f 33
soumi_ghsoh 6:3c510c297e2f 34
soumi_ghsoh 6:3c510c297e2f 35
soumi_ghsoh 6:3c510c297e2f 36
soumi_ghsoh 6:3c510c297e2f 37
rwclough 1:1eb96189824d 38
rwclough 1:1eb96189824d 39 #include "mbed.h"
rwclough 1:1eb96189824d 40 #include "readerComm.h"
soumi_ghsoh 11:d5e8f47880f1 41 uint8_t sg=0;
soumi_ghsoh 13:16a5b43ac874 42 DigitalOut EN(p0); // Control EN pin on TRF7970
soumi_ghsoh 13:16a5b43ac874 43 DigitalOut EN2(p4); // Control EN2 pin on TRF7970
soumi_ghsoh 13:16a5b43ac874 44 DigitalOut CS(p9);
soumi_ghsoh 13:16a5b43ac874 45 uint8_t turnRFOn[2];
soumi_ghsoh 5:93c612f43ec2 46 uint8_t testcommand[2];
soumi_ghsoh 7:96baf1b2fd07 47 extern uint8_t noBytes;
rwclough 2:bd5afc5aa139 48 extern SPI spi; // main.cpp
rwclough 2:bd5afc5aa139 49 extern Serial pc; // main.cpp
soumi_ghsoh 11:d5e8f47880f1 50 uint8_t buf[300]; // main.cpp
soumi_ghsoh 11:d5e8f47880f1 51 uint8_t found=0;
soumi_ghsoh 13:16a5b43ac874 52 uint8_t rssi_flag=0;
soumi_ghsoh 13:16a5b43ac874 53 uint8_t rssi=0;
soumi_ghsoh 13:16a5b43ac874 54 extern DigitalOut BLED;
soumi_ghsoh 13:16a5b43ac874 55 DigitalOut AO_7970(p29);
soumi_ghsoh 13:16a5b43ac874 56 DigitalOut MOD_7970(p30);
soumi_ghsoh 13:16a5b43ac874 57 int nfc=0;
soumi_ghsoh 11:d5e8f47880f1 58 //extern bool tagFound=0;
soumi_ghsoh 13:16a5b43ac874 59
soumi_ghsoh 13:16a5b43ac874 60 //extern DigitalOut debug1LED;
soumi_ghsoh 13:16a5b43ac874 61 //extern DigitalOut debug2LED;
soumi_ghsoh 13:16a5b43ac874 62 //extern DigitalOut ISO15693LED;
soumi_ghsoh 13:16a5b43ac874 63 //extern DigitalOut heartbeatLED;
soumi_ghsoh 13:16a5b43ac874 64 //extern DigitalOut testPin;
soumi_ghsoh 7:96baf1b2fd07 65 uint8_t temp;
soumi_ghsoh 7:96baf1b2fd07 66 uint8_t command[2];
rwclough 4:9ab0d84bbd07 67
soumi_ghsoh 11:d5e8f47880f1 68 uint8_t WAIT=0;
rwclough 4:9ab0d84bbd07 69 void trf797xDirectCommand(uint8_t *buffer)
rwclough 1:1eb96189824d 70 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 71 // trf797xDirectCommand()
rwclough 1:1eb96189824d 72 // Description: Transmit a Direct Command to the reader chip.
rwclough 1:1eb96189824d 73 // Parameter: *buffer = the direct command.
rwclough 1:1eb96189824d 74 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 75 {
rwclough 1:1eb96189824d 76 *buffer = (0x80 | *buffer); // Setup command mode
rwclough 2:bd5afc5aa139 77 *buffer = (0x9F & *buffer); // Setup command mode
rwclough 1:1eb96189824d 78 CS = SELECT;
rwclough 1:1eb96189824d 79 spi.write(*buffer);
rwclough 1:1eb96189824d 80 CS = DESELECT;
rwclough 4:9ab0d84bbd07 81 } // End of trf797xDirectCommand()
rwclough 1:1eb96189824d 82
rwclough 4:9ab0d84bbd07 83 void trf797xWriteSingle(uint8_t *buffer, uint8_t length)
rwclough 1:1eb96189824d 84 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 85 // trf797xWriteSingle()
rwclough 1:1eb96189824d 86 // Description: Writes to specified reader registers.
rwclough 1:1eb96189824d 87 // Parameters: *buffer = addresses of the registers followed by the
rwclough 2:bd5afc5aa139 88 // contents to write.
rwclough 1:1eb96189824d 89 // length = number of registers * 2.
rwclough 1:1eb96189824d 90 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 91 {
rwclough 2:bd5afc5aa139 92 uint8_t i=0;
soumi_ghsoh 13:16a5b43ac874 93
rwclough 1:1eb96189824d 94 CS = SELECT;
rwclough 1:1eb96189824d 95 while(length > 0) {
rwclough 2:bd5afc5aa139 96 *buffer = (0x1F & *buffer); // Register address
rwclough 1:1eb96189824d 97 for(i = 0; i < 2; i++) {
rwclough 1:1eb96189824d 98 spi.write(*buffer);
rwclough 1:1eb96189824d 99 buffer++;
rwclough 1:1eb96189824d 100 length--;
rwclough 2:bd5afc5aa139 101 }
rwclough 2:bd5afc5aa139 102 }
rwclough 1:1eb96189824d 103 CS = DESELECT;
soumi_ghsoh 13:16a5b43ac874 104
rwclough 4:9ab0d84bbd07 105 } // End of trf797xWriteSingle()
rwclough 1:1eb96189824d 106
rwclough 4:9ab0d84bbd07 107 void trf797xReadSingle(uint8_t *buffer, uint8_t number)
rwclough 1:1eb96189824d 108 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 109 // trf797xReadSingle()
soumi_ghsoh 13:16a5b43ac874 110 // Description: Reads specified reader chip registers and
rwclough 1:1eb96189824d 111 // writes register contents to *buffer.
rwclough 1:1eb96189824d 112 // Parameters: *buffer = addresses of the registers.
rwclough 1:1eb96189824d 113 // number = number of registers.
rwclough 1:1eb96189824d 114 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 115 {
rwclough 1:1eb96189824d 116 CS = SELECT;
rwclough 1:1eb96189824d 117 while(number > 0) {
rwclough 1:1eb96189824d 118 *buffer = (0x40 | *buffer); // Address, read, single
rwclough 2:bd5afc5aa139 119 *buffer = (0x5F & *buffer); // Register address
rwclough 3:eaae5433ab45 120 spi.write(*buffer);
rwclough 2:bd5afc5aa139 121 *buffer = spi.write(0x00); // *buffer <- register contents
rwclough 1:1eb96189824d 122 buffer++;
rwclough 1:1eb96189824d 123 number--;
rwclough 2:bd5afc5aa139 124 }
rwclough 2:bd5afc5aa139 125 CS = DESELECT;
rwclough 4:9ab0d84bbd07 126 } // End of trf797xReadSingle()
rwclough 2:bd5afc5aa139 127
rwclough 4:9ab0d84bbd07 128 void trf797xReadContinuous(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 129 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 130 // trf797xReadContinuous()
rwclough 2:bd5afc5aa139 131 // Description: Used in SPI mode to read a specified number of
rwclough 2:bd5afc5aa139 132 // reader chip registers from a specified address upwards.
rwclough 2:bd5afc5aa139 133 // Contents of the registers are stored in *buffer.
rwclough 4:9ab0d84bbd07 134 // 1) Read register(s)
rwclough 4:9ab0d84bbd07 135 // 2) Write contents to *buffer
rwclough 2:bd5afc5aa139 136 // Parameters: *buffer = address of first register.
rwclough 2:bd5afc5aa139 137 // length = number of registers to read.
rwclough 2:bd5afc5aa139 138 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 13:16a5b43ac874 139 {
soumi_ghsoh 13:16a5b43ac874 140 //==================tested wrk $sg
rwclough 2:bd5afc5aa139 141 CS = SELECT;
rwclough 2:bd5afc5aa139 142 *buffer = (0x60 | *buffer); // Address, read, continuous
rwclough 3:eaae5433ab45 143 *buffer = (0x7F & *buffer); // Register address
rwclough 2:bd5afc5aa139 144 spi.write(*buffer);
rwclough 2:bd5afc5aa139 145 while(length > 0) {
rwclough 2:bd5afc5aa139 146 *buffer = spi.write(0x00);
rwclough 2:bd5afc5aa139 147 buffer++;
rwclough 2:bd5afc5aa139 148 length--;
rwclough 3:eaae5433ab45 149 }
rwclough 4:9ab0d84bbd07 150 // spi.write(0x00); spi.write(0x00); // 16 clock cycles, see TRF7970A FW Design Hints SLOA159 section 7.3
rwclough 1:1eb96189824d 151 CS = DESELECT;
soumi_ghsoh 13:16a5b43ac874 152
soumi_ghsoh 5:93c612f43ec2 153 //=====================tested it wrks $sg
rwclough 4:9ab0d84bbd07 154 } // End of trf797xReadContinuous()
rwclough 2:bd5afc5aa139 155
rwclough 4:9ab0d84bbd07 156 void trf797xRawWrite(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 157 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 158 // trf797xRawWrite()
rwclough 2:bd5afc5aa139 159 // Description: Used in SPI mode to write direct to the reader chip.
rwclough 2:bd5afc5aa139 160 // Parameters: *buffer = raw data
rwclough 2:bd5afc5aa139 161 // length = number of data bytes
rwclough 2:bd5afc5aa139 162 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 163 {
rwclough 2:bd5afc5aa139 164 CS = SELECT;
rwclough 2:bd5afc5aa139 165 while(length > 0) {
rwclough 2:bd5afc5aa139 166 temp = spi.write(*buffer);
rwclough 2:bd5afc5aa139 167 buffer++;
rwclough 2:bd5afc5aa139 168 length--;
rwclough 2:bd5afc5aa139 169 }
rwclough 2:bd5afc5aa139 170 CS = DESELECT;
rwclough 4:9ab0d84bbd07 171 } // End of trf797xRawWrite()
rwclough 2:bd5afc5aa139 172
rwclough 4:9ab0d84bbd07 173 void trf797xStopDecoders(void)
rwclough 2:bd5afc5aa139 174 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 175 // trf797xStopDecoders()
rwclough 2:bd5afc5aa139 176 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 177 {
rwclough 2:bd5afc5aa139 178 command[0] = STOP_DECODERS;
rwclough 4:9ab0d84bbd07 179 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 180 }
rwclough 1:1eb96189824d 181
rwclough 4:9ab0d84bbd07 182 void trf797xRunDecoders(void)
rwclough 2:bd5afc5aa139 183 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 184 // trf797xRunDecoders()
rwclough 2:bd5afc5aa139 185 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 186 {
rwclough 2:bd5afc5aa139 187 command[0] = RUN_DECODERS;
rwclough 4:9ab0d84bbd07 188 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 189 }
rwclough 2:bd5afc5aa139 190
soumi_ghsoh 5:93c612f43ec2 191
soumi_ghsoh 10:98a58968dc7d 192 void PowerUpNFC2(void)
soumi_ghsoh 13:16a5b43ac874 193 {
soumi_ghsoh 13:16a5b43ac874 194 //CS = 1;
soumi_ghsoh 9:9266e0109d26 195 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 196 // EN = 1;
soumi_ghsoh 9:9266e0109d26 197 // EN2=1;
soumi_ghsoh 9:9266e0109d26 198
soumi_ghsoh 13:16a5b43ac874 199 CS = 0;
soumi_ghsoh 13:16a5b43ac874 200 EN2 = 0;
soumi_ghsoh 13:16a5b43ac874 201 EN = 0;
soumi_ghsoh 9:9266e0109d26 202 wait_ms(2);
soumi_ghsoh 9:9266e0109d26 203 CS = 1;
soumi_ghsoh 9:9266e0109d26 204 wait_ms(3);
soumi_ghsoh 9:9266e0109d26 205 EN2 = 1;
soumi_ghsoh 9:9266e0109d26 206 wait_ms(1);
soumi_ghsoh 9:9266e0109d26 207 EN = 1;
soumi_ghsoh 9:9266e0109d26 208 }
soumi_ghsoh 10:98a58968dc7d 209 void PowerUpNFC(void)
soumi_ghsoh 13:16a5b43ac874 210 {
soumi_ghsoh 13:16a5b43ac874 211 //CS = 1;
soumi_ghsoh 9:9266e0109d26 212 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 213 // EN = 1;
soumi_ghsoh 13:16a5b43ac874 214 EN2 = 1;
soumi_ghsoh 13:16a5b43ac874 215 wait_ms(1);
soumi_ghsoh 13:16a5b43ac874 216 EN=1;
soumi_ghsoh 6:3c510c297e2f 217 }
soumi_ghsoh 6:3c510c297e2f 218 void PowerDownNFC(void)
soumi_ghsoh 13:16a5b43ac874 219 {
soumi_ghsoh 13:16a5b43ac874 220 ///CS=1;
soumi_ghsoh 13:16a5b43ac874 221 EN=0;
soumi_ghsoh 13:16a5b43ac874 222 EN2=0;
soumi_ghsoh 9:9266e0109d26 223 //wait_ms(1);
soumi_ghsoh 13:16a5b43ac874 224 //EN2= 0; PowerDown Mode
soumi_ghsoh 13:16a5b43ac874 225 //EN2=1; SleepMode
soumi_ghsoh 13:16a5b43ac874 226 //CS=0;
soumi_ghsoh 5:93c612f43ec2 227 }
soumi_ghsoh 11:d5e8f47880f1 228 void SleepNFC(void)
soumi_ghsoh 13:16a5b43ac874 229 {
soumi_ghsoh 13:16a5b43ac874 230 EN=0;
soumi_ghsoh 13:16a5b43ac874 231 EN2=0;
soumi_ghsoh 13:16a5b43ac874 232 }
soumi_ghsoh 10:98a58968dc7d 233 void StandByNFC(void)
soumi_ghsoh 11:d5e8f47880f1 234 {
soumi_ghsoh 10:98a58968dc7d 235 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 13:16a5b43ac874 236 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 237
soumi_ghsoh 13:16a5b43ac874 238 turnRFOn[1] &= 0x3F;
soumi_ghsoh 13:16a5b43ac874 239 turnRFOn[1] |= 0x80;
soumi_ghsoh 13:16a5b43ac874 240 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 11:d5e8f47880f1 241 }
soumi_ghsoh 11:d5e8f47880f1 242
soumi_ghsoh 5:93c612f43ec2 243 void SpiInit1(void)
soumi_ghsoh 5:93c612f43ec2 244 {
soumi_ghsoh 13:16a5b43ac874 245 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 13:16a5b43ac874 246 spi.frequency(250000);
soumi_ghsoh 5:93c612f43ec2 247 }
soumi_ghsoh 5:93c612f43ec2 248
soumi_ghsoh 6:3c510c297e2f 249 void SpiInit(void)
soumi_ghsoh 5:93c612f43ec2 250 {
soumi_ghsoh 13:16a5b43ac874 251 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 13:16a5b43ac874 252 spi.frequency(1000000);
soumi_ghsoh 5:93c612f43ec2 253 }
soumi_ghsoh 5:93c612f43ec2 254
soumi_ghsoh 5:93c612f43ec2 255 void NFCInit(void)
soumi_ghsoh 13:16a5b43ac874 256 {
soumi_ghsoh 13:16a5b43ac874 257 //testPin=1;
soumi_ghsoh 6:3c510c297e2f 258 //wait_ms(2);
soumi_ghsoh 13:16a5b43ac874 259
soumi_ghsoh 13:16a5b43ac874 260 testcommand[0] = SOFT_INIT;
soumi_ghsoh 13:16a5b43ac874 261 trf797xDirectCommand(testcommand);
soumi_ghsoh 13:16a5b43ac874 262 wait_ms(2);
soumi_ghsoh 13:16a5b43ac874 263 testcommand[0] = IDLE;
soumi_ghsoh 13:16a5b43ac874 264 trf797xDirectCommand(testcommand);
soumi_ghsoh 13:16a5b43ac874 265 wait_ms(2);
soumi_ghsoh 13:16a5b43ac874 266 //testcommand[0] =NFC_TARGET_LEVEL ;
soumi_ghsoh 13:16a5b43ac874 267 //testcommand[1] = 0x00;
soumi_ghsoh 13:16a5b43ac874 268 //trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 269 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 13:16a5b43ac874 270 testcommand[1] = 0x81; // 6.78 MHz, OOK 100%
soumi_ghsoh 13:16a5b43ac874 271 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 272 //wait_ms(2);
soumi_ghsoh 13:16a5b43ac874 273 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 13:16a5b43ac874 274 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 275 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 13:16a5b43ac874 276 testcommand[1] = 0x07;
soumi_ghsoh 13:16a5b43ac874 277 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 278 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 13:16a5b43ac874 279 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 13:16a5b43ac874 280 turnRFOn[1] &= 0x3F;
soumi_ghsoh 13:16a5b43ac874 281 turnRFOn[1] |= 0x00;
soumi_ghsoh 10:98a58968dc7d 282
soumi_ghsoh 6:3c510c297e2f 283 // Oroiginal code has 0x20 !!!
soumi_ghsoh 13:16a5b43ac874 284 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 13:16a5b43ac874 285 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 13:16a5b43ac874 286 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 13:16a5b43ac874 287 turnRFOn[1] &= 0x3F;
soumi_ghsoh 13:16a5b43ac874 288 turnRFOn[1] |= 0x00;
soumi_ghsoh 13:16a5b43ac874 289 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 6:3c510c297e2f 290 //wait_ms(2);
soumi_ghsoh 13:16a5b43ac874 291
soumi_ghsoh 13:16a5b43ac874 292 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 293 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 13:16a5b43ac874 294 testcommand[1] = 0x02; // 6.78 MHz, OOK 100%
soumi_ghsoh 13:16a5b43ac874 295 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 296 testcommand[0] = IRQ_MASK;
soumi_ghsoh 13:16a5b43ac874 297 testcommand[1] = 0x3F;
soumi_ghsoh 13:16a5b43ac874 298 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 299 //wait_ms(6);
soumi_ghsoh 13:16a5b43ac874 300 //testPin=0;
soumi_ghsoh 13:16a5b43ac874 301 }
soumi_ghsoh 5:93c612f43ec2 302
soumi_ghsoh 5:93c612f43ec2 303 void RegisterReInitNFC(void)
soumi_ghsoh 13:16a5b43ac874 304 {
soumi_ghsoh 13:16a5b43ac874 305 //testcommand[0] =NFC_TARGET_LEVEL ;
soumi_ghsoh 13:16a5b43ac874 306 //testcommand[1] = 0x00;
soumi_ghsoh 13:16a5b43ac874 307 //trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 308 testcommand[0] = TX_TIMER_EPC_HIGH;
soumi_ghsoh 13:16a5b43ac874 309 testcommand[1] = 0xC1;
soumi_ghsoh 13:16a5b43ac874 310 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 311 testcommand[0] = TX_TIMER_EPC_LOW ;
soumi_ghsoh 13:16a5b43ac874 312 testcommand[1] = 0xC1;
soumi_ghsoh 13:16a5b43ac874 313 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 314 testcommand[0] = TX_PULSE_LENGTH_CONTROL ;
soumi_ghsoh 13:16a5b43ac874 315 testcommand[1] = 0x00;
soumi_ghsoh 13:16a5b43ac874 316 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 317 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 13:16a5b43ac874 318 testcommand[1] = 0x30;
soumi_ghsoh 13:16a5b43ac874 319 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 320 testcommand[0] = RX_WAIT_TIME ;
soumi_ghsoh 13:16a5b43ac874 321 testcommand[1] = 0x1F;
soumi_ghsoh 13:16a5b43ac874 322 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 323 testcommand[0] = MODULATOR_CONTROL ;
soumi_ghsoh 13:16a5b43ac874 324 testcommand[1] = 0x81; //0x34 100%ook@13MHz
soumi_ghsoh 13:16a5b43ac874 325 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 326 testcommand[0] = RX_SPECIAL_SETTINGS ;
soumi_ghsoh 13:16a5b43ac874 327 testcommand[1] = 0x40;
soumi_ghsoh 13:16a5b43ac874 328 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 329 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 13:16a5b43ac874 330 testcommand[1] = 0x07;
soumi_ghsoh 13:16a5b43ac874 331 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 332 }
soumi_ghsoh 6:3c510c297e2f 333
soumi_ghsoh 6:3c510c297e2f 334
soumi_ghsoh 6:3c510c297e2f 335 void RegistersReadNFC(void)
soumi_ghsoh 13:16a5b43ac874 336 {
soumi_ghsoh 13:16a5b43ac874 337 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 13:16a5b43ac874 338 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 13:16a5b43ac874 339 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 13:16a5b43ac874 340 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 341 testcommand[0] = TX_TIMER_EPC_HIGH; //0xC1;
soumi_ghsoh 13:16a5b43ac874 342 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 343 testcommand[0] = TX_TIMER_EPC_LOW ; //0xC1;
soumi_ghsoh 13:16a5b43ac874 344 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 345 testcommand[0] = TX_PULSE_LENGTH_CONTROL ; //0x00;
soumi_ghsoh 13:16a5b43ac874 346 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 347 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ; //0x30;
soumi_ghsoh 13:16a5b43ac874 348 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 349 testcommand[0] = RX_WAIT_TIME ; //0x1F;
soumi_ghsoh 13:16a5b43ac874 350 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 351 testcommand[0] = MODULATOR_CONTROL ; //0x21;
soumi_ghsoh 13:16a5b43ac874 352 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 353 testcommand[0] = RX_SPECIAL_SETTINGS ; //0x40;
soumi_ghsoh 13:16a5b43ac874 354 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 355 testcommand[0] = REGULATOR_CONTROL ; //0x87;
soumi_ghsoh 13:16a5b43ac874 356 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 357 }
soumi_ghsoh 6:3c510c297e2f 358
soumi_ghsoh 6:3c510c297e2f 359 void InventoryReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 360 {
soumi_ghsoh 6:3c510c297e2f 361 //send inventory command==================================================
soumi_ghsoh 13:16a5b43ac874 362 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 13:16a5b43ac874 363 buf[1]=0x91;
soumi_ghsoh 13:16a5b43ac874 364 buf[2]=0x3D;
soumi_ghsoh 13:16a5b43ac874 365 buf[3]=0x00;
soumi_ghsoh 13:16a5b43ac874 366 buf[4]=0x30;
soumi_ghsoh 13:16a5b43ac874 367 buf[5]=0x26;
soumi_ghsoh 13:16a5b43ac874 368 buf[6]=0x01;
soumi_ghsoh 13:16a5b43ac874 369 buf[7]=0x00;
soumi_ghsoh 13:16a5b43ac874 370 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 13:16a5b43ac874 371 //read rssi register and interchange rx input to main and aux receiver blocks
soumi_ghsoh 13:16a5b43ac874 372 //{add code block here
soumi_ghsoh 13:16a5b43ac874 373 // }
soumi_ghsoh 13:16a5b43ac874 374 wait_ms(2);
soumi_ghsoh 13:16a5b43ac874 375 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 376 trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 377 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 378 trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 379 wait_ms(5);
soumi_ghsoh 13:16a5b43ac874 380 //testcommand[0] = CHECK_EXTERNAL_RF;
soumi_ghsoh 13:16a5b43ac874 381 //trf797xDirectCommand(testcommand);
soumi_ghsoh 13:16a5b43ac874 382 //wait_ms(1);
soumi_ghsoh 13:16a5b43ac874 383 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 13:16a5b43ac874 384 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 385 printf("RSSI:%X \r\n", testcommand[0]);
soumi_ghsoh 13:16a5b43ac874 386 /*====================================read tag ID
soumi_ghsoh 13:16a5b43ac874 387 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 388 trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 389 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 390 trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 391 testcommand[0] = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 13:16a5b43ac874 392 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 393 testcommand[0] = 0x7F & testcommand[0]; // Determine the number of bytes left in FIFO
soumi_ghsoh 13:16a5b43ac874 394 buf[0] = FIFO;
soumi_ghsoh 13:16a5b43ac874 395 trf797xReadContinuous(&buf[0], testcommand[0]);
soumi_ghsoh 13:16a5b43ac874 396 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 13:16a5b43ac874 397 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 398 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 399 trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 400 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 401 trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 402 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 13:16a5b43ac874 403 trf797xDirectCommand(testcommand);
soumi_ghsoh 13:16a5b43ac874 404 trf797xStopDecoders();
soumi_ghsoh 13:16a5b43ac874 405 trf797xRunDecoders(); */
soumi_ghsoh 7:96baf1b2fd07 406 //=====================================read Tag ID
soumi_ghsoh 6:3c510c297e2f 407 //wait(1);
soumi_ghsoh 7:96baf1b2fd07 408 }
soumi_ghsoh 7:96baf1b2fd07 409
soumi_ghsoh 11:d5e8f47880f1 410 void FindNFC(uint8_t *irqStatus)
soumi_ghsoh 13:16a5b43ac874 411 {
soumi_ghsoh 13:16a5b43ac874 412 //found=0;
soumi_ghsoh 11:d5e8f47880f1 413 //static uint8_t sg;
soumi_ghsoh 13:16a5b43ac874 414 //printf("%X \r\n", *irqStatus);
soumi_ghsoh 13:16a5b43ac874 415
soumi_ghsoh 13:16a5b43ac874 416 switch(*irqStatus) {
soumi_ghsoh 13:16a5b43ac874 417 case BIT0:
soumi_ghsoh 13:16a5b43ac874 418 found=BIT0;
soumi_ghsoh 13:16a5b43ac874 419 WAIT=10;
soumi_ghsoh 13:16a5b43ac874 420 break;
soumi_ghsoh 13:16a5b43ac874 421 case BIT1:
soumi_ghsoh 13:16a5b43ac874 422 found=BIT1;
soumi_ghsoh 13:16a5b43ac874 423 break;
soumi_ghsoh 13:16a5b43ac874 424 // case BIT2://found=BIT2; // break;
soumi_ghsoh 13:16a5b43ac874 425 //case BIT3:found=BIT3; WAIT=0;break;
soumi_ghsoh 11:d5e8f47880f1 426 // case BIT4:found=BIT4; WAIT=0;break;
soumi_ghsoh 11:d5e8f47880f1 427 // case BIT5:found=BIT5; WAIT=0;break;
soumi_ghsoh 13:16a5b43ac874 428 case 0x40:
soumi_ghsoh 13:16a5b43ac874 429 found=0x40;
soumi_ghsoh 13:16a5b43ac874 430 break;
soumi_ghsoh 13:16a5b43ac874 431 case BIT7:
soumi_ghsoh 13:16a5b43ac874 432 found=BIT7;
soumi_ghsoh 13:16a5b43ac874 433 break;
soumi_ghsoh 13:16a5b43ac874 434 default:
soumi_ghsoh 13:16a5b43ac874 435 found=0;
soumi_ghsoh 13:16a5b43ac874 436 }
soumi_ghsoh 11:d5e8f47880f1 437
soumi_ghsoh 11:d5e8f47880f1 438
soumi_ghsoh 13:16a5b43ac874 439 }
soumi_ghsoh 7:96baf1b2fd07 440 void handlerNFC(void)
soumi_ghsoh 7:96baf1b2fd07 441 {
soumi_ghsoh 13:16a5b43ac874 442 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 443 trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 444 FindNFC(testcommand);
soumi_ghsoh 11:d5e8f47880f1 445 //wait_ms(1);
soumi_ghsoh 11:d5e8f47880f1 446 //=============================use if trf7970a irq_status is not cleared
soumi_ghsoh 13:16a5b43ac874 447 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 448 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 449 //=============================
soumi_ghsoh 7:96baf1b2fd07 450 }
soumi_ghsoh 6:3c510c297e2f 451
soumi_ghsoh 7:96baf1b2fd07 452
soumi_ghsoh 7:96baf1b2fd07 453 void MemReadReqNFC(void)
soumi_ghsoh 13:16a5b43ac874 454 {
soumi_ghsoh 13:16a5b43ac874 455 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 13:16a5b43ac874 456 testcommand[1] = 0xFF;
soumi_ghsoh 13:16a5b43ac874 457 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 13:16a5b43ac874 458 //send inventory command==================================================
soumi_ghsoh 13:16a5b43ac874 459 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 13:16a5b43ac874 460 buf[1]=0x91;
soumi_ghsoh 13:16a5b43ac874 461 buf[2]=0x3D;
soumi_ghsoh 13:16a5b43ac874 462 buf[3]=0x00;
soumi_ghsoh 13:16a5b43ac874 463 buf[4]=0x30;
soumi_ghsoh 13:16a5b43ac874 464 buf[5]=0x02;
soumi_ghsoh 13:16a5b43ac874 465 buf[6]=0x20;
soumi_ghsoh 13:16a5b43ac874 466 buf[7]=0x00;
soumi_ghsoh 13:16a5b43ac874 467 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 13:16a5b43ac874 468
soumi_ghsoh 13:16a5b43ac874 469 //read rssi register and interchange rx input to main and aux receiver blocks
soumi_ghsoh 13:16a5b43ac874 470 //{add code block here
soumi_ghsoh 13:16a5b43ac874 471 // }
soumi_ghsoh 13:16a5b43ac874 472 //wait_ms(2);
soumi_ghsoh 11:d5e8f47880f1 473 //testPin=1;
soumi_ghsoh 11:d5e8f47880f1 474 //=========================use to clear irq_status register of trf7970a
soumi_ghsoh 13:16a5b43ac874 475 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 476 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 477 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 478 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 479 //==========================
soumi_ghsoh 13:16a5b43ac874 480 wait_ms(5);
soumi_ghsoh 13:16a5b43ac874 481 //testcommand[0] = CHECK_EXTERNAL_RF;
soumi_ghsoh 13:16a5b43ac874 482 //trf797xDirectCommand(testcommand);
soumi_ghsoh 13:16a5b43ac874 483 //wait_us(100);
soumi_ghsoh 13:16a5b43ac874 484 testcommand[0] = RSSI_LEVELS;
soumi_ghsoh 13:16a5b43ac874 485 //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 13:16a5b43ac874 486 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 13:16a5b43ac874 487 rssi=testcommand[0];
soumi_ghsoh 13:16a5b43ac874 488
soumi_ghsoh 13:16a5b43ac874 489 printf("RSSI:%X \r\n", testcommand[0]);
soumi_ghsoh 7:96baf1b2fd07 490 }
soumi_ghsoh 13:16a5b43ac874 491 void ReadNFC(void)
soumi_ghsoh 13:16a5b43ac874 492 {
soumi_ghsoh 13:16a5b43ac874 493 /*========================================== read irqstatus reg. of trf7970a
soumi_ghsoh 13:16a5b43ac874 494 //testcommand[0] = IRQ_STATUS; clear irqstatus reg of trf7970a
soumi_ghsoh 13:16a5b43ac874 495 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 496 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 497 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 498 ===========================================*/
soumi_ghsoh 7:96baf1b2fd07 499
soumi_ghsoh 13:16a5b43ac874 500 noBytes = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 13:16a5b43ac874 501 trf797xReadSingle(&noBytes, 1);
soumi_ghsoh 13:16a5b43ac874 502 noBytes = 0x7F & noBytes; // Determine the number of bytes left in FIFO
soumi_ghsoh 13:16a5b43ac874 503 buf[0] = FIFO;
soumi_ghsoh 13:16a5b43ac874 504 trf797xReadContinuous(&buf[0],noBytes);
soumi_ghsoh 11:d5e8f47880f1 505 //==use if trf7970a irq_status is not cleared
soumi_ghsoh 13:16a5b43ac874 506 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 507 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 13:16a5b43ac874 508 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 13:16a5b43ac874 509 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 11:d5e8f47880f1 510 //=========================================
soumi_ghsoh 13:16a5b43ac874 511 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 13:16a5b43ac874 512 trf797xDirectCommand(testcommand);
soumi_ghsoh 7:96baf1b2fd07 513
soumi_ghsoh 13:16a5b43ac874 514 //wait(1);
soumi_ghsoh 9:9266e0109d26 515 }
soumi_ghsoh 11:d5e8f47880f1 516
soumi_ghsoh 13:16a5b43ac874 517
soumi_ghsoh 13:16a5b43ac874 518
soumi_ghsoh 13:16a5b43ac874 519
soumi_ghsoh 13:16a5b43ac874 520
soumi_ghsoh 13:16a5b43ac874 521
soumi_ghsoh 13:16a5b43ac874 522
soumi_ghsoh 13:16a5b43ac874 523
soumi_ghsoh 11:d5e8f47880f1 524
soumi_ghsoh 13:16a5b43ac874 525 bool PollNFC(void)
soumi_ghsoh 13:16a5b43ac874 526 {
soumi_ghsoh 13:16a5b43ac874 527 printf("PollNFC \r\n");
soumi_ghsoh 13:16a5b43ac874 528 //CS=1;
soumi_ghsoh 13:16a5b43ac874 529 // PowerUpNFC();
soumi_ghsoh 13:16a5b43ac874 530 //////wait_ms(1);
soumi_ghsoh 13:16a5b43ac874 531 // NFCInit();
soumi_ghsoh 13:16a5b43ac874 532 // RegisterReInitNFC();
soumi_ghsoh 13:16a5b43ac874 533 MemReadReqNFC();
soumi_ghsoh 13:16a5b43ac874 534 printf("back from MemReadReqNFC \r\n");
soumi_ghsoh 13:16a5b43ac874 535 if (rssi>0x50)
soumi_ghsoh 13:16a5b43ac874 536 {rssi_flag=1;}
soumi_ghsoh 13:16a5b43ac874 537 else{rssi_flag=0;}
soumi_ghsoh 13:16a5b43ac874 538 nfc++;
soumi_ghsoh 13:16a5b43ac874 539 //InventoryReqNFC();
soumi_ghsoh 13:16a5b43ac874 540 wait_ms(WAIT);
soumi_ghsoh 11:d5e8f47880f1 541
soumi_ghsoh 13:16a5b43ac874 542 switch(found) {
soumi_ghsoh 13:16a5b43ac874 543 case BIT0:
soumi_ghsoh 13:16a5b43ac874 544 printf("no response:");
soumi_ghsoh 13:16a5b43ac874 545 printf("%X \r\n",found);
soumi_ghsoh 13:16a5b43ac874 546 found=0;
soumi_ghsoh 13:16a5b43ac874 547 WAIT=0;
soumi_ghsoh 13:16a5b43ac874 548 break;
soumi_ghsoh 11:d5e8f47880f1 549 // //case BIT1:
soumi_ghsoh 11:d5e8f47880f1 550 // //case BIT2:
soumi_ghsoh 11:d5e8f47880f1 551 // //case BIT3:
soumi_ghsoh 11:d5e8f47880f1 552 //// case BIT4:
soumi_ghsoh 11:d5e8f47880f1 553 //// case BIT5:
soumi_ghsoh 13:16a5b43ac874 554 case BIT6:
soumi_ghsoh 13:16a5b43ac874 555 ReadNFC();
soumi_ghsoh 13:16a5b43ac874 556 //PowerDownNFC(); //SleepNFC() //StandByNFC()
soumi_ghsoh 13:16a5b43ac874 557 found=1;
soumi_ghsoh 13:16a5b43ac874 558 WAIT=0;
soumi_ghsoh 13:16a5b43ac874 559 break;
soumi_ghsoh 13:16a5b43ac874 560 case BIT7:
soumi_ghsoh 13:16a5b43ac874 561 printf("tx complete:");
soumi_ghsoh 13:16a5b43ac874 562 printf("%X \r\n",found);
soumi_ghsoh 13:16a5b43ac874 563 found=0;
soumi_ghsoh 13:16a5b43ac874 564 WAIT=0;
soumi_ghsoh 13:16a5b43ac874 565 break;
soumi_ghsoh 13:16a5b43ac874 566 default:
soumi_ghsoh 13:16a5b43ac874 567 if((nfc>10)&&(rssi_flag=1));
soumi_ghsoh 13:16a5b43ac874 568 {rssi_flag=0;
soumi_ghsoh 13:16a5b43ac874 569 nfc=0;
soumi_ghsoh 13:16a5b43ac874 570 PowerUpNFC();
soumi_ghsoh 13:16a5b43ac874 571 NFCInit();
soumi_ghsoh 13:16a5b43ac874 572 RegisterReInitNFC();
soumi_ghsoh 13:16a5b43ac874 573 printf("resetting 7970 \r\n:");
soumi_ghsoh 13:16a5b43ac874 574 found=0;
soumi_ghsoh 13:16a5b43ac874 575 }
soumi_ghsoh 13:16a5b43ac874 576 }
soumi_ghsoh 11:d5e8f47880f1 577
soumi_ghsoh 13:16a5b43ac874 578 return found;
soumi_ghsoh 11:d5e8f47880f1 579
soumi_ghsoh 11:d5e8f47880f1 580 }