Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

readerComm.cpp@5:93c612f43ec2, 2015-04-01 (annotated)

Committer:
soumi_ghsoh
Date:
Wed Apr 01 22:06:40 2015 +0000
Revision:
5:93c612f43ec2
Parent:
4:9ab0d84bbd07
Child:
6:3c510c297e2f
TAG read with multiple instances of RX complete IRQ; Imp changes: reduced RX wait time, Vin=3V/AGC ON, RX_IN2(main) , RX_IN1(aux)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 2 Filename: readerComm.cpp
rwclough 1:1eb96189824d 3 Description: Functions used to communicate with the TRF7970 eval bd.
rwclough 1:1eb96189824d 4 Communication is by means of an SPI interface between
rwclough 1:1eb96189824d 5 the nRF51-DK board (nRF51422 MCU) and the TRF7970 eval bd.
rwclough 1:1eb96189824d 6 Copyright (C) 2015 Gymtrack, Inc.
rwclough 1:1eb96189824d 7 Author: Ron Clough
rwclough 1:1eb96189824d 8 Date: 2015-02-27
rwclough 1:1eb96189824d 9
rwclough 1:1eb96189824d 10 Changes:
rwclough 1:1eb96189824d 11 Rev Date Who Details
rwclough 1:1eb96189824d 12 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
rwclough 2:bd5afc5aa139 13 0.0 2015-02-27 RWC Original version.
rwclough 1:1eb96189824d 14
rwclough 1:1eb96189824d 15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
rwclough 1:1eb96189824d 16
rwclough 1:1eb96189824d 17 #include "mbed.h"
rwclough 1:1eb96189824d 18 #include "readerComm.h"
rwclough 3:eaae5433ab45 19 #include "interruptStuff.h"
soumi_ghsoh 5:93c612f43ec2 20 //#include "main.h"
soumi_ghsoh 5:93c612f43ec2 21 DigitalOut enable(p4); // Control EN pin on TRF7970
soumi_ghsoh 5:93c612f43ec2 22 //DigitalOut enable2(p3); // Control EN2 pin on TRF7970
soumi_ghsoh 5:93c612f43ec2 23 DigitalOut CS(p19);
soumi_ghsoh 5:93c612f43ec2 24 uint8_t turnRFOn[2];
soumi_ghsoh 5:93c612f43ec2 25 uint8_t testcommand[2];
rwclough 2:bd5afc5aa139 26 uint8_t afi = 0;
rwclough 2:bd5afc5aa139 27 uint8_t flags = 0; // Stores the mask value (used in anticollision)
rwclough 2:bd5afc5aa139 28 uint8_t command[2];
rwclough 2:bd5afc5aa139 29 uint8_t temp;
soumi_ghsoh 5:93c612f43ec2 30
rwclough 2:bd5afc5aa139 31 extern SPI spi; // main.cpp
rwclough 2:bd5afc5aa139 32 extern Serial pc; // main.cpp
soumi_ghsoh 5:93c612f43ec2 33 //extern DigitalOut CS; // main.cpp
rwclough 2:bd5afc5aa139 34 extern InterruptIn readerInt; // main.cpp
rwclough 2:bd5afc5aa139 35 extern int8_t rxtxState; // Transmit/Receive byte count (main.cpp)
rwclough 2:bd5afc5aa139 36 extern uint8_t buf[300]; // main.cpp
rwclough 2:bd5afc5aa139 37 extern uint8_t irqRegister; // Interrupt register (main.cpp)
rwclough 3:eaae5433ab45 38 volatile extern uint8_t irqFlag; // main.cpp
rwclough 2:bd5afc5aa139 39 extern uint8_t rxErrorFlag; // main.cpp
rwclough 2:bd5afc5aa139 40 extern uint8_t readerMode; // Determines how interrupts will be handled (main.cpp)
rwclough 2:bd5afc5aa139 41 extern uint8_t buffer[2];
rwclough 2:bd5afc5aa139 42
rwclough 3:eaae5433ab45 43 extern uint8_t tagFlag;
rwclough 3:eaae5433ab45 44 extern DigitalIn irqPin;
rwclough 3:eaae5433ab45 45 extern DigitalOut debug1LED;
rwclough 3:eaae5433ab45 46 extern DigitalOut debug2LED;
rwclough 3:eaae5433ab45 47 extern DigitalOut ISO15693LED;
rwclough 3:eaae5433ab45 48 extern DigitalOut heartbeatLED;
rwclough 3:eaae5433ab45 49
rwclough 3:eaae5433ab45 50 extern DigitalOut testPin;
rwclough 3:eaae5433ab45 51
rwclough 4:9ab0d84bbd07 52 extern uint8_t debugBuffer[1000]; // Capture data for analysis
rwclough 4:9ab0d84bbd07 53 extern uint8_t bufIdx;
rwclough 4:9ab0d84bbd07 54
rwclough 4:9ab0d84bbd07 55 void trf797xInitialSettings(void)
rwclough 1:1eb96189824d 56 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 57 // trf797xInitialSettings()
rwclough 1:1eb96189824d 58 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 59 {
rwclough 2:bd5afc5aa139 60 uint8_t mod_control[2];
rwclough 1:1eb96189824d 61
rwclough 1:1eb96189824d 62 mod_control[0] = SOFT_INIT;
rwclough 4:9ab0d84bbd07 63 trf797xDirectCommand(mod_control);
rwclough 3:eaae5433ab45 64
rwclough 1:1eb96189824d 65 mod_control[0] = IDLE;
rwclough 4:9ab0d84bbd07 66 trf797xDirectCommand(mod_control);
rwclough 3:eaae5433ab45 67
rwclough 1:1eb96189824d 68 mod_control[0] = MODULATOR_CONTROL;
rwclough 2:bd5afc5aa139 69 mod_control[1] = 0x21; // 6.78 MHz, OOK 100%
rwclough 4:9ab0d84bbd07 70 trf797xWriteSingle(mod_control, 2);
rwclough 3:eaae5433ab45 71
rwclough 1:1eb96189824d 72 mod_control[0] = MODULATOR_CONTROL;
rwclough 4:9ab0d84bbd07 73 trf797xReadSingle(mod_control, 1);
rwclough 4:9ab0d84bbd07 74 // printf("\r\nMOD: 0x%02X 0x%02X\r\n", mod_control[0], mod_control[1]);
rwclough 4:9ab0d84bbd07 75
rwclough 4:9ab0d84bbd07 76 /*
rwclough 4:9ab0d84bbd07 77 mod_control[0] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 78 mod_control[1] = 0x01;
rwclough 4:9ab0d84bbd07 79 trf797xWriteSingle(mod_control, 2);
rwclough 4:9ab0d84bbd07 80
rwclough 4:9ab0d84bbd07 81 mod_control[0] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 82 trf797xReadSingle(mod_control, 1);
rwclough 4:9ab0d84bbd07 83 printf("CHIP: 0x%02X 0x%02X\r\n", mod_control[0], mod_control[1]);
rwclough 4:9ab0d84bbd07 84
rwclough 4:9ab0d84bbd07 85 mod_control[0] = ISO_CONTROL;
rwclough 4:9ab0d84bbd07 86 mod_control[1] = 0x02;
rwclough 4:9ab0d84bbd07 87 trf797xWriteSingle(mod_control, 2);
rwclough 4:9ab0d84bbd07 88
rwclough 4:9ab0d84bbd07 89 mod_control[0] = ISO_CONTROL;
rwclough 4:9ab0d84bbd07 90 mod_control[1] = ISO_CONTROL;
rwclough 4:9ab0d84bbd07 91 trf797xReadSingle(mod_control, 1);
rwclough 4:9ab0d84bbd07 92 printf("ISO: 0x%02X 0x%02X\r\n", mod_control[0], mod_control[1]);
rwclough 4:9ab0d84bbd07 93
rwclough 4:9ab0d84bbd07 94 mod_control[0] = RX_SPECIAL_SETTINGS;
rwclough 4:9ab0d84bbd07 95 mod_control[1] = 0x40;
rwclough 4:9ab0d84bbd07 96 trf797xWriteSingle(mod_control, 2);
rwclough 4:9ab0d84bbd07 97
rwclough 4:9ab0d84bbd07 98 mod_control[0] = RX_SPECIAL_SETTINGS;
rwclough 4:9ab0d84bbd07 99 mod_control[1] = RX_SPECIAL_SETTINGS;
rwclough 4:9ab0d84bbd07 100 trf797xReadSingle(mod_control, 1);
rwclough 4:9ab0d84bbd07 101 printf("RX: 0x%02X 0x%02X\r\n", mod_control[0], mod_control[1]);
rwclough 4:9ab0d84bbd07 102 */
rwclough 4:9ab0d84bbd07 103 /*
rwclough 4:9ab0d84bbd07 104 command[0] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 105 command[1] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 106 command[1] = 0x01; // Set bit 0 => Vin = 5V
rwclough 4:9ab0d84bbd07 107 trf797xWriteSingle(command, 2);
rwclough 1:1eb96189824d 108
rwclough 4:9ab0d84bbd07 109 command[0] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 110 command[1] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 111 trf797xReadSingle(command, 1);
rwclough 4:9ab0d84bbd07 112 printf("CHIP 0x%02X 0x%02X\r\n", command[0], command[1]);
rwclough 4:9ab0d84bbd07 113 */
rwclough 4:9ab0d84bbd07 114 } // End of trf797xInitialSettings()
rwclough 4:9ab0d84bbd07 115
rwclough 4:9ab0d84bbd07 116 void trf797xDirectCommand(uint8_t *buffer)
rwclough 1:1eb96189824d 117 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 118 // trf797xDirectCommand()
rwclough 1:1eb96189824d 119 // Description: Transmit a Direct Command to the reader chip.
rwclough 1:1eb96189824d 120 // Parameter: *buffer = the direct command.
rwclough 1:1eb96189824d 121 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 122 {
rwclough 1:1eb96189824d 123 *buffer = (0x80 | *buffer); // Setup command mode
rwclough 2:bd5afc5aa139 124 *buffer = (0x9F & *buffer); // Setup command mode
rwclough 1:1eb96189824d 125 CS = SELECT;
rwclough 1:1eb96189824d 126 spi.write(*buffer);
rwclough 1:1eb96189824d 127 CS = DESELECT;
rwclough 4:9ab0d84bbd07 128 } // End of trf797xDirectCommand()
rwclough 1:1eb96189824d 129
rwclough 4:9ab0d84bbd07 130 void trf797xWriteSingle(uint8_t *buffer, uint8_t length)
rwclough 1:1eb96189824d 131 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 132 // trf797xWriteSingle()
rwclough 1:1eb96189824d 133 // Description: Writes to specified reader registers.
rwclough 1:1eb96189824d 134 // Parameters: *buffer = addresses of the registers followed by the
rwclough 2:bd5afc5aa139 135 // contents to write.
rwclough 1:1eb96189824d 136 // length = number of registers * 2.
rwclough 1:1eb96189824d 137 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 138 {
rwclough 2:bd5afc5aa139 139 uint8_t i=0;
rwclough 1:1eb96189824d 140
rwclough 1:1eb96189824d 141 CS = SELECT;
rwclough 1:1eb96189824d 142 while(length > 0) {
rwclough 2:bd5afc5aa139 143 *buffer = (0x1F & *buffer); // Register address
rwclough 1:1eb96189824d 144 for(i = 0; i < 2; i++) {
rwclough 1:1eb96189824d 145 spi.write(*buffer);
rwclough 1:1eb96189824d 146 buffer++;
rwclough 1:1eb96189824d 147 length--;
rwclough 2:bd5afc5aa139 148 }
rwclough 2:bd5afc5aa139 149 }
rwclough 1:1eb96189824d 150 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 151
rwclough 4:9ab0d84bbd07 152 } // End of trf797xWriteSingle()
rwclough 1:1eb96189824d 153
rwclough 4:9ab0d84bbd07 154 void trf797xReadSingle(uint8_t *buffer, uint8_t number)
rwclough 1:1eb96189824d 155 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 156 // trf797xReadSingle()
rwclough 1:1eb96189824d 157 // Description: Reads specified reader chip registers and
rwclough 1:1eb96189824d 158 // writes register contents to *buffer.
rwclough 1:1eb96189824d 159 // Parameters: *buffer = addresses of the registers.
rwclough 1:1eb96189824d 160 // number = number of registers.
rwclough 1:1eb96189824d 161 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 162 {
rwclough 1:1eb96189824d 163 CS = SELECT;
rwclough 1:1eb96189824d 164 while(number > 0) {
rwclough 1:1eb96189824d 165 *buffer = (0x40 | *buffer); // Address, read, single
rwclough 2:bd5afc5aa139 166 *buffer = (0x5F & *buffer); // Register address
rwclough 3:eaae5433ab45 167 spi.write(*buffer);
rwclough 2:bd5afc5aa139 168 *buffer = spi.write(0x00); // *buffer <- register contents
rwclough 1:1eb96189824d 169 buffer++;
rwclough 1:1eb96189824d 170 number--;
rwclough 2:bd5afc5aa139 171 }
rwclough 2:bd5afc5aa139 172 CS = DESELECT;
rwclough 4:9ab0d84bbd07 173 } // End of trf797xReadSingle()
rwclough 2:bd5afc5aa139 174
rwclough 4:9ab0d84bbd07 175 void trf797xReadContinuous(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 176 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 177 // trf797xReadContinuous()
rwclough 2:bd5afc5aa139 178 // Description: Used in SPI mode to read a specified number of
rwclough 2:bd5afc5aa139 179 // reader chip registers from a specified address upwards.
rwclough 2:bd5afc5aa139 180 // Contents of the registers are stored in *buffer.
rwclough 4:9ab0d84bbd07 181 // 1) Read register(s)
rwclough 4:9ab0d84bbd07 182 // 2) Write contents to *buffer
rwclough 2:bd5afc5aa139 183 // Parameters: *buffer = address of first register.
rwclough 2:bd5afc5aa139 184 // length = number of registers to read.
rwclough 2:bd5afc5aa139 185 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 5:93c612f43ec2 186 { //==================tested wrk $sg
rwclough 2:bd5afc5aa139 187 CS = SELECT;
rwclough 2:bd5afc5aa139 188 *buffer = (0x60 | *buffer); // Address, read, continuous
rwclough 3:eaae5433ab45 189 *buffer = (0x7F & *buffer); // Register address
rwclough 2:bd5afc5aa139 190 spi.write(*buffer);
rwclough 2:bd5afc5aa139 191 while(length > 0) {
rwclough 2:bd5afc5aa139 192 *buffer = spi.write(0x00);
rwclough 2:bd5afc5aa139 193 buffer++;
rwclough 2:bd5afc5aa139 194 length--;
rwclough 3:eaae5433ab45 195 }
rwclough 4:9ab0d84bbd07 196 // spi.write(0x00); spi.write(0x00); // 16 clock cycles, see TRF7970A FW Design Hints SLOA159 section 7.3
rwclough 1:1eb96189824d 197 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 198
soumi_ghsoh 5:93c612f43ec2 199 //=====================tested it wrks $sg
rwclough 4:9ab0d84bbd07 200 } // End of trf797xReadContinuous()
rwclough 2:bd5afc5aa139 201
rwclough 4:9ab0d84bbd07 202 void trf797xRawWrite(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 203 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 204 // trf797xRawWrite()
rwclough 2:bd5afc5aa139 205 // Description: Used in SPI mode to write direct to the reader chip.
rwclough 2:bd5afc5aa139 206 // Parameters: *buffer = raw data
rwclough 2:bd5afc5aa139 207 // length = number of data bytes
rwclough 2:bd5afc5aa139 208 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 209 {
rwclough 2:bd5afc5aa139 210 CS = SELECT;
rwclough 2:bd5afc5aa139 211 while(length > 0) {
rwclough 2:bd5afc5aa139 212 temp = spi.write(*buffer);
rwclough 2:bd5afc5aa139 213 buffer++;
rwclough 2:bd5afc5aa139 214 length--;
rwclough 2:bd5afc5aa139 215 }
rwclough 2:bd5afc5aa139 216 CS = DESELECT;
rwclough 4:9ab0d84bbd07 217 } // End of trf797xRawWrite()
rwclough 2:bd5afc5aa139 218
rwclough 4:9ab0d84bbd07 219 void trf797xStopDecoders(void)
rwclough 2:bd5afc5aa139 220 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 221 // trf797xStopDecoders()
rwclough 2:bd5afc5aa139 222 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 223 {
rwclough 2:bd5afc5aa139 224 command[0] = STOP_DECODERS;
rwclough 4:9ab0d84bbd07 225 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 226 }
rwclough 1:1eb96189824d 227
rwclough 4:9ab0d84bbd07 228 void trf797xRunDecoders(void)
rwclough 2:bd5afc5aa139 229 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 230 // trf797xRunDecoders()
rwclough 2:bd5afc5aa139 231 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 232 {
rwclough 2:bd5afc5aa139 233 command[0] = RUN_DECODERS;
rwclough 4:9ab0d84bbd07 234 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 235 }
rwclough 2:bd5afc5aa139 236
rwclough 4:9ab0d84bbd07 237 void trf797xTxNextSlot(void)
rwclough 2:bd5afc5aa139 238 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 239 // trf797xTxNextSlot()
rwclough 2:bd5afc5aa139 240 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 241 {
rwclough 2:bd5afc5aa139 242 command[0] = TRANSMIT_NEXT_SLOT;
rwclough 4:9ab0d84bbd07 243 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 244 }
rwclough 2:bd5afc5aa139 245
rwclough 4:9ab0d84bbd07 246 void trf797xDisableSlotCounter(void)
rwclough 2:bd5afc5aa139 247 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 248 // trf797xDisableSlotCounter()
rwclough 2:bd5afc5aa139 249 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 250 {
rwclough 2:bd5afc5aa139 251 buf[40] = IRQ_MASK;
rwclough 2:bd5afc5aa139 252 buf[41] = IRQ_MASK;
rwclough 4:9ab0d84bbd07 253 trf797xReadSingle(&buf[41], 1);
rwclough 2:bd5afc5aa139 254 buf[41] &= 0xFE;
rwclough 4:9ab0d84bbd07 255 trf797xWriteSingle(&buf[40], 2);
rwclough 2:bd5afc5aa139 256 }
rwclough 2:bd5afc5aa139 257
rwclough 4:9ab0d84bbd07 258 void trf797xReset(void)
rwclough 2:bd5afc5aa139 259 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 260 // trf797xReset()
rwclough 2:bd5afc5aa139 261 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 262 {
rwclough 2:bd5afc5aa139 263 command[0] = RESET;
rwclough 4:9ab0d84bbd07 264 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 265 }
rwclough 2:bd5afc5aa139 266
rwclough 4:9ab0d84bbd07 267 void trf797xTurnRfOn(void)
rwclough 1:1eb96189824d 268 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 269 // trf797xTurnRfOn()
rwclough 1:1eb96189824d 270 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 3:eaae5433ab45 271 {
rwclough 3:eaae5433ab45 272 command[0] = CHIP_STATUS_CONTROL;
rwclough 3:eaae5433ab45 273 command[1] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 274 trf797xReadSingle(&command[1], 1);
rwclough 3:eaae5433ab45 275 command[1] &= 0x3F;
rwclough 4:9ab0d84bbd07 276 command[1] |= 0x21; // Oroiginal code has 0x20 !!!
rwclough 4:9ab0d84bbd07 277 // printf("\r\nCHIP 0x%02X 0x%02X\r\n", command[0], command[1]);
rwclough 4:9ab0d84bbd07 278 trf797xWriteSingle(command, 2);
rwclough 4:9ab0d84bbd07 279 // printf("\r\nCHIP 0x%02X 0x%02X\r\n", command[0], command[1]);
rwclough 4:9ab0d84bbd07 280 } // End of trf797xTurnRfOn()
rwclough 1:1eb96189824d 281
rwclough 4:9ab0d84bbd07 282 void trf797xTurnRfOff(void)
rwclough 1:1eb96189824d 283 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 284 // trf797xTurnRfOff()
rwclough 1:1eb96189824d 285 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 286 {
rwclough 3:eaae5433ab45 287 command[0] = CHIP_STATUS_CONTROL;
rwclough 3:eaae5433ab45 288 command[1] = CHIP_STATUS_CONTROL;
rwclough 4:9ab0d84bbd07 289 trf797xReadSingle(&command[1], 1);
rwclough 3:eaae5433ab45 290 command[1] &= 0x1F;
rwclough 4:9ab0d84bbd07 291 trf797xWriteSingle(command, 2);
rwclough 4:9ab0d84bbd07 292 } // End of trf797xTurnRfOff()
rwclough 1:1eb96189824d 293
rwclough 4:9ab0d84bbd07 294 void trf797xWriteIsoControl(uint8_t iso_control)
rwclough 1:1eb96189824d 295 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 296 // trf797xWriteIsoControl()
rwclough 1:1eb96189824d 297 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 298 {
rwclough 2:bd5afc5aa139 299 uint8_t write[4];
rwclough 1:1eb96189824d 300
rwclough 2:bd5afc5aa139 301 if ((iso_control & BIT5) == BIT5) {
rwclough 2:bd5afc5aa139 302 printf("iso_control bit5 != 0\r\n");
rwclough 2:bd5afc5aa139 303 return;
rwclough 2:bd5afc5aa139 304 }
rwclough 1:1eb96189824d 305
rwclough 1:1eb96189824d 306 write[0] = ISO_CONTROL;
rwclough 1:1eb96189824d 307 write[1] = iso_control;
rwclough 2:bd5afc5aa139 308 write[1] &= ~BIT5;
rwclough 4:9ab0d84bbd07 309 trf797xWriteSingle(write, 2);
rwclough 1:1eb96189824d 310 iso_control &= 0x1F;
rwclough 4:9ab0d84bbd07 311 } // End of trf797xWriteIsoControl()
rwclough 1:1eb96189824d 312
rwclough 2:bd5afc5aa139 313 void iso15693FindTag(void)
rwclough 1:1eb96189824d 314 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 1:1eb96189824d 315 // iso15693FindTag()
rwclough 3:eaae5433ab45 316 // Description: Used to detect ISO15693 conforming tags.
rwclough 3:eaae5433ab45 317 // If an ISO15693 conforming tag is found ISO15693LED is turned ON.
rwclough 3:eaae5433ab45 318 // 1) Turn RF ON
rwclough 3:eaae5433ab45 319 // 2) Perform a complete anticollision sequence
rwclough 3:eaae5433ab45 320 // 3) Turn RF OFF
rwclough 1:1eb96189824d 321 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 5:93c612f43ec2 322 { // testPin=1;
rwclough 4:9ab0d84bbd07 323 trf797xTurnRfOn();
soumi_ghsoh 5:93c612f43ec2 324 // testPin=0;
soumi_ghsoh 5:93c612f43ec2 325 //=======================================================diable interrupt from trf797x
soumi_ghsoh 5:93c612f43ec2 326 // readerInt.disable_irq(); // comment: has no effect in detectecting interrupt from trf797x, works without disabling too $SG
soumi_ghsoh 5:93c612f43ec2 327 //=======================================================diable interrupt from trf797x $SG
soumi_ghsoh 5:93c612f43ec2 328 // testPin=1;
rwclough 4:9ab0d84bbd07 329 trf797xWriteIsoControl(0x02);
soumi_ghsoh 5:93c612f43ec2 330 // testPin=0;
rwclough 3:eaae5433ab45 331 wait_ms(6); // The VCD should wait at least 1 ms after it activated the
rwclough 3:eaae5433ab45 332 // powering field before sending the first request, to
rwclough 3:eaae5433ab45 333 // ensure that the VICCs are ready to receive it. (ISO15693-3)
rwclough 3:eaae5433ab45 334 /*
rwclough 3:eaae5433ab45 335 // Field Level Test:
rwclough 4:9ab0d84bbd07 336 buffer[0] = RUN_DECODERS; // Enable receiver
rwclough 4:9ab0d84bbd07 337 trf797xDirectCommand(buffer);
rwclough 3:eaae5433ab45 338 buffer[0] = CHIP_STATUS_CONTROL;
rwclough 3:eaae5433ab45 339 buffer[1] = 0x23;
rwclough 4:9ab0d84bbd07 340 trf797xWriteSingle(buffer, 2);
rwclough 3:eaae5433ab45 341 wait_ms(1);
rwclough 3:eaae5433ab45 342 buffer[0] = CHECK_INTERNAL_RF;
rwclough 4:9ab0d84bbd07 343 trf797xDirectCommand(buffer);
rwclough 3:eaae5433ab45 344 buffer[0] = RSSI_LEVELS;
rwclough 4:9ab0d84bbd07 345 trf797xReadSingle(buffer, 1);
rwclough 3:eaae5433ab45 346 printf("RSSI: 0x%X\r\n", buffer[0]);
rwclough 4:9ab0d84bbd07 347 // Result: RSSI = 0x5C (Range is 0x40 to 0x7F)
rwclough 3:eaae5433ab45 348 */
rwclough 4:9ab0d84bbd07 349
rwclough 3:eaae5433ab45 350 flags = SIXTEEN_SLOTS; // SIXTEEN_SLOTS = 0x06
rwclough 4:9ab0d84bbd07 351 // flags = ONE_SLOT; // ONE_SLOT = 0x26
rwclough 2:bd5afc5aa139 352 buf[20] = 0x00;
soumi_ghsoh 5:93c612f43ec2 353 // debug2LED = LED_ON;
soumi_ghsoh 5:93c612f43ec2 354
soumi_ghsoh 5:93c612f43ec2 355 iso15693Anticollision(&buf[20],0x00); // Send Inventory request
soumi_ghsoh 5:93c612f43ec2 356
rwclough 4:9ab0d84bbd07 357 trf797xTurnRfOff();
soumi_ghsoh 5:93c612f43ec2 358 trf797xResetIrqStatus();
soumi_ghsoh 5:93c612f43ec2 359 // Clear any IRQs
rwclough 1:1eb96189824d 360 } // End of iso15693FindTag()
rwclough 1:1eb96189824d 361
rwclough 4:9ab0d84bbd07 362 void iso15693Anticollision(uint8_t *mask, uint8_t length)
rwclough 1:1eb96189824d 363 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 364 // iso15693Anticollision()
rwclough 2:bd5afc5aa139 365 // Description: Used to perform an inventory cycle of 1 or 16 timeslots.
rwclough 2:bd5afc5aa139 366 // Send command, receive response and send response to host.
rwclough 2:bd5afc5aa139 367 // Parameters: *mask = mask value
rwclough 2:bd5afc5aa139 368 // length = number of significant bits of mask value
rwclough 1:1eb96189824d 369 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 5:93c612f43ec2 370 {
rwclough 3:eaae5433ab45 371 uint8_t i = 1, j = 1, command[2], no_slots, found = 0;
rwclough 3:eaae5433ab45 372 uint8_t *p_slot_no, slot_no[17];
rwclough 3:eaae5433ab45 373 uint8_t new_mask[8], new_length, mask_size;
rwclough 3:eaae5433ab45 374 uint32_t size;
rwclough 3:eaae5433ab45 375 uint8_t fifo_length = 0;
rwclough 4:9ab0d84bbd07 376 uint16_t k = 0;
rwclough 4:9ab0d84bbd07 377 // uint8_t irqStatus[2], iso_control;
rwclough 2:bd5afc5aa139 378
rwclough 2:bd5afc5aa139 379 slot_no[0] = 0x00;
soumi_ghsoh 5:93c612f43ec2 380 if ((flags & BIT5) == 0x00) { // flags<5> is the number of slots testPin
rwclough 3:eaae5433ab45 381 no_slots = 16; // 16 slots if flags<5> is cleared
rwclough 2:bd5afc5aa139 382 }
rwclough 2:bd5afc5aa139 383 else {
rwclough 3:eaae5433ab45 384 no_slots = 1; // 1 slot if flags<5> is set
rwclough 2:bd5afc5aa139 385 }
rwclough 2:bd5afc5aa139 386
rwclough 2:bd5afc5aa139 387 p_slot_no = &slot_no[0]; // slot number pointer
rwclough 2:bd5afc5aa139 388 mask_size = (((length >> 2) + 1) >> 1); // mask_size is 1 for length = 4 or 8
rwclough 2:bd5afc5aa139 389 buf[0] = 0x8F; // RESET
rwclough 2:bd5afc5aa139 390 buf[1] = 0x91; // send with CRC
rwclough 2:bd5afc5aa139 391 buf[2] = 0x3D; // write continuous from 1D
rwclough 2:bd5afc5aa139 392 buf[5] = flags; // ISO15693 flags
rwclough 2:bd5afc5aa139 393 buf[6] = 0x01; // anticollision command code
rwclough 2:bd5afc5aa139 394
rwclough 2:bd5afc5aa139 395 if (flags & 0x10) { // mask_size is 2 for length = 12 or 16 and so on
rwclough 2:bd5afc5aa139 396 size = mask_size + 4; // mask value + mask length + afi + command code + flags
rwclough 2:bd5afc5aa139 397 buf[7] = afi;
rwclough 2:bd5afc5aa139 398 buf[8] = length; // mask length
rwclough 2:bd5afc5aa139 399 if (length > 0) {
rwclough 2:bd5afc5aa139 400 for(i = 0; i < mask_size; i++) {
rwclough 2:bd5afc5aa139 401 buf[9 + i] = *(mask + i);
rwclough 2:bd5afc5aa139 402 }
rwclough 2:bd5afc5aa139 403 }
rwclough 2:bd5afc5aa139 404 fifo_length = 9;
rwclough 2:bd5afc5aa139 405 }
rwclough 2:bd5afc5aa139 406 else { // mask_size is 2 for length = 12 or 16 and so on
rwclough 2:bd5afc5aa139 407 size = mask_size + 3; // mask value + mask length + command code + flags
rwclough 2:bd5afc5aa139 408 buf[7] = length; // mask length
rwclough 2:bd5afc5aa139 409 if(length > 0) {
rwclough 2:bd5afc5aa139 410 for(i = 0; i < mask_size; i++) {
rwclough 2:bd5afc5aa139 411 buf[8 + i] = *(mask + i);
rwclough 2:bd5afc5aa139 412 }
rwclough 2:bd5afc5aa139 413 }
rwclough 2:bd5afc5aa139 414 fifo_length = 8;
rwclough 2:bd5afc5aa139 415 }
rwclough 2:bd5afc5aa139 416
rwclough 2:bd5afc5aa139 417 buf[3] = (char) (size >> 8);
rwclough 2:bd5afc5aa139 418 buf[4] = (char) (size << 4);
soumi_ghsoh 5:93c612f43ec2 419
soumi_ghsoh 5:93c612f43ec2 420
soumi_ghsoh 5:93c612f43ec2 421
rwclough 4:9ab0d84bbd07 422 trf797xResetIrqStatus();
soumi_ghsoh 5:93c612f43ec2 423
rwclough 3:eaae5433ab45 424 // ***** Original code sets up a 30 ms counter here *****
rwclough 3:eaae5433ab45 425 // ***** Original code enables IRQ here *****
rwclough 3:eaae5433ab45 426 // ***** nRF51422 clear IRQ register *****
rwclough 3:eaae5433ab45 427 readerInt.enable_irq();
soumi_ghsoh 5:93c612f43ec2 428
rwclough 4:9ab0d84bbd07 429 trf797xRawWrite(&buf[0], mask_size + fifo_length); // Write to FIFO
rwclough 2:bd5afc5aa139 430
soumi_ghsoh 5:93c612f43ec2 431 //===================================================runs till here !$SG
soumi_ghsoh 5:93c612f43ec2 432 irqRegister = 0x01;
soumi_ghsoh 5:93c612f43ec2 433 irqFlag = 0x00;
soumi_ghsoh 5:93c612f43ec2 434
rwclough 3:eaae5433ab45 435
soumi_ghsoh 5:93c612f43ec2 436
soumi_ghsoh 5:93c612f43ec2 437 //
soumi_ghsoh 5:93c612f43ec2 438 for (j = 1; j <= no_slots; j++) { // 1 or 16 available timeslots
soumi_ghsoh 5:93c612f43ec2 439 rxtxState = 1;
soumi_ghsoh 5:93c612f43ec2 440 // ***** Original code sets up a 20 ms counter and starts it here *****
soumi_ghsoh 5:93c612f43ec2 441 //irqFlag = 0x00;
soumi_ghsoh 5:93c612f43ec2 442 // while(1)
soumi_ghsoh 5:93c612f43ec2 443 while(irqFlag == 0x00)
soumi_ghsoh 5:93c612f43ec2 444 { ;
soumi_ghsoh 5:93c612f43ec2 445 }
rwclough 3:eaae5433ab45 446
soumi_ghsoh 5:93c612f43ec2 447 // ISO15693LED = LED_ON;
soumi_ghsoh 5:93c612f43ec2 448 // wait_ms(1000);
soumi_ghsoh 5:93c612f43ec2 449 // ISO15693LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 450 irqRegister = 0x01;
soumi_ghsoh 5:93c612f43ec2 451 // Wait for interrupt
rwclough 3:eaae5433ab45 452 // ***** Original code stops the counter here *****
soumi_ghsoh 5:93c612f43ec2 453 //
rwclough 2:bd5afc5aa139 454 while(irqRegister == 0x01) { // Wait for RX complete
rwclough 2:bd5afc5aa139 455 k++;
soumi_ghsoh 5:93c612f43ec2 456 if (k == 0xFFF0) { //printf("k == 0xFFF0 _MAIN \r\n");
soumi_ghsoh 5:93c612f43ec2 457 irqRegister = 0x00;
rwclough 2:bd5afc5aa139 458 rxErrorFlag = 0x00;
rwclough 2:bd5afc5aa139 459 }
soumi_ghsoh 5:93c612f43ec2 460 }
soumi_ghsoh 5:93c612f43ec2 461
soumi_ghsoh 5:93c612f43ec2 462
soumi_ghsoh 5:93c612f43ec2 463
soumi_ghsoh 5:93c612f43ec2 464
soumi_ghsoh 5:93c612f43ec2 465 //wait_us(1000);
soumi_ghsoh 5:93c612f43ec2 466
rwclough 2:bd5afc5aa139 467 command[0] = RSSI_LEVELS; // Read RSSI levels
rwclough 4:9ab0d84bbd07 468 trf797xReadSingle(command, 1);
rwclough 3:eaae5433ab45 469
rwclough 2:bd5afc5aa139 470 switch (irqRegister) {
soumi_ghsoh 5:93c612f43ec2 471 case 0xFF: // If received UID in buffer //0xff changed to 0x01 $SG
soumi_ghsoh 5:93c612f43ec2 472 found = 1;
rwclough 3:eaae5433ab45 473 printf("\r\nISO15693: [ ");
rwclough 2:bd5afc5aa139 474 for (i=3; i < 11; i++) {
rwclough 2:bd5afc5aa139 475 printf("%c", buf[i]);
rwclough 2:bd5afc5aa139 476 }
rwclough 2:bd5afc5aa139 477 printf(", %d ]\r\n", command[0]);
rwclough 2:bd5afc5aa139 478 break;
rwclough 2:bd5afc5aa139 479
soumi_ghsoh 5:93c612f43ec2 480 case 0x02: printf("collision occured _MAIN \r\n"); // Collision occurred
rwclough 2:bd5afc5aa139 481 p_slot_no++; // Remember a collision was detected
rwclough 2:bd5afc5aa139 482 *p_slot_no = j;
rwclough 2:bd5afc5aa139 483 break;
rwclough 2:bd5afc5aa139 484
soumi_ghsoh 5:93c612f43ec2 485 case 0x00: // printf("Timer interrupt \r\n"); // Timer interrupt
soumi_ghsoh 5:93c612f43ec2 486 // ***** Original code does nothing! *****
rwclough 2:bd5afc5aa139 487 break;
rwclough 2:bd5afc5aa139 488
soumi_ghsoh 5:93c612f43ec2 489 default:
rwclough 3:eaae5433ab45 490 // ***** Original code does nothing *****
rwclough 2:bd5afc5aa139 491 break;
rwclough 3:eaae5433ab45 492 } // switch (irqRegister)
rwclough 2:bd5afc5aa139 493
rwclough 2:bd5afc5aa139 494 command[0] = RESET; // FIFO must be reset before receiving the next response
rwclough 4:9ab0d84bbd07 495 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 496
rwclough 2:bd5afc5aa139 497 if ((no_slots == 16) && (j < 16)) { // If 16 slots used then send EOF (next slot)
rwclough 4:9ab0d84bbd07 498 trf797xStopDecoders();
rwclough 4:9ab0d84bbd07 499 trf797xRunDecoders();
rwclough 4:9ab0d84bbd07 500 command[0] = RESET; // new
rwclough 4:9ab0d84bbd07 501 trf797xDirectCommand(command); // new
soumi_ghsoh 5:93c612f43ec2 502 trf797xTxNextSlot(); // RESET must precede txNextSlot, see "TRF7970A FW Design Hints SLOA159.
rwclough 2:bd5afc5aa139 503 }
rwclough 2:bd5afc5aa139 504 else if ((no_slots == 16) && (j == 16)) { // At end of slot 16, stop the slot counter
rwclough 4:9ab0d84bbd07 505 trf797xStopDecoders();
rwclough 4:9ab0d84bbd07 506 trf797xDisableSlotCounter();
rwclough 2:bd5afc5aa139 507 }
rwclough 3:eaae5433ab45 508 else if (no_slots == 1) { // 1 slot is used
soumi_ghsoh 5:93c612f43ec2 509 break;
rwclough 2:bd5afc5aa139 510 }
rwclough 3:eaae5433ab45 511 } // for (j = 1; j <= no_slots; j++)
soumi_ghsoh 5:93c612f43ec2 512 //================================================
soumi_ghsoh 5:93c612f43ec2 513 //===================================================
rwclough 2:bd5afc5aa139 514 if (found == 1) {
rwclough 2:bd5afc5aa139 515 ISO15693LED = LED_ON;
soumi_ghsoh 5:93c612f43ec2 516 }
soumi_ghsoh 5:93c612f43ec2 517 else {printf("tag not read \r\n");
soumi_ghsoh 5:93c612f43ec2 518 ISO15693LED = LED_OFF;
soumi_ghsoh 5:93c612f43ec2 519 }
soumi_ghsoh 5:93c612f43ec2 520 //
rwclough 2:bd5afc5aa139 521 new_length = length + 4; // The mask length is a multiple of 4 bits
rwclough 2:bd5afc5aa139 522 mask_size = (((new_length >> 2) + 1) >> 1);
soumi_ghsoh 5:93c612f43ec2 523 while ((*p_slot_no != 0x00) && (no_slots == 16) && (new_length < 61) && (slot_no[16] != 16)) {
rwclough 2:bd5afc5aa139 524 *p_slot_no = *p_slot_no - 1;
rwclough 2:bd5afc5aa139 525
soumi_ghsoh 5:93c612f43ec2 526 for(i = 0; i < 8; i++)
rwclough 2:bd5afc5aa139 527 {
soumi_ghsoh 5:93c612f43ec2 528 new_mask[i] = *(mask + i); // First the whole mask is copied
soumi_ghsoh 5:93c612f43ec2 529 }
rwclough 2:bd5afc5aa139 530
soumi_ghsoh 5:93c612f43ec2 531 if((new_length & BIT2) == 0x00)
rwclough 2:bd5afc5aa139 532 {
rwclough 2:bd5afc5aa139 533 *p_slot_no = *p_slot_no << 4;
rwclough 2:bd5afc5aa139 534 }
rwclough 2:bd5afc5aa139 535 else
rwclough 2:bd5afc5aa139 536 {
rwclough 2:bd5afc5aa139 537 for(i = 7; i > 0; i--)
soumi_ghsoh 5:93c612f43ec2 538 {
soumi_ghsoh 5:93c612f43ec2 539 new_mask[i] = new_mask[i - 1];
soumi_ghsoh 5:93c612f43ec2 540 }
soumi_ghsoh 5:93c612f43ec2 541 new_mask[0] &= 0x00;
soumi_ghsoh 5:93c612f43ec2 542 }
rwclough 2:bd5afc5aa139 543 new_mask[0] |= *p_slot_no; // The mask is changed
soumi_ghsoh 5:93c612f43ec2 544 wait_ms(2);
rwclough 2:bd5afc5aa139 545
rwclough 4:9ab0d84bbd07 546
rwclough 4:9ab0d84bbd07 547 printf("Idx: 0x%02X Buf: 0x%02X, ", bufIdx, debugBuffer[bufIdx-1]);
rwclough 4:9ab0d84bbd07 548
soumi_ghsoh 5:93c612f43ec2 549 iso15693Anticollision(&new_mask[0], new_length); // Recursive call with new Mask
rwclough 2:bd5afc5aa139 550
soumi_ghsoh 5:93c612f43ec2 551 p_slot_no--;
soumi_ghsoh 5:93c612f43ec2 552
soumi_ghsoh 5:93c612f43ec2 553 }
soumi_ghsoh 5:93c612f43ec2 554 //==================================================
rwclough 3:eaae5433ab45 555 // ***** Original code disables IRQ here *****
rwclough 3:eaae5433ab45 556 //readerInt.disable_irq();
soumi_ghsoh 5:93c612f43ec2 557 //debug2LED = LED_OFF;
rwclough 4:9ab0d84bbd07 558 } // End of iso15693Anticollision()
soumi_ghsoh 5:93c612f43ec2 559 /*
soumi_ghsoh 5:93c612f43ec2 560 Header file for main.cpp
soumi_ghsoh 5:93c612f43ec2 561 */
soumi_ghsoh 5:93c612f43ec2 562
soumi_ghsoh 5:93c612f43ec2 563
soumi_ghsoh 5:93c612f43ec2 564 void PowerUpNFC(void)
soumi_ghsoh 5:93c612f43ec2 565 {// CS = 0; enable2 = 0; enable = 0;
soumi_ghsoh 5:93c612f43ec2 566 CS = 1;
soumi_ghsoh 5:93c612f43ec2 567 wait_ms(8);
soumi_ghsoh 5:93c612f43ec2 568 //
soumi_ghsoh 5:93c612f43ec2 569 // wait_ms(3);
soumi_ghsoh 5:93c612f43ec2 570 // enable2 = 1;
soumi_ghsoh 5:93c612f43ec2 571 // wait_ms(3);
soumi_ghsoh 5:93c612f43ec2 572 enable = 1;
soumi_ghsoh 5:93c612f43ec2 573
soumi_ghsoh 5:93c612f43ec2 574 }
soumi_ghsoh 5:93c612f43ec2 575
soumi_ghsoh 5:93c612f43ec2 576 void SpiInit1(void)
soumi_ghsoh 5:93c612f43ec2 577 {
soumi_ghsoh 5:93c612f43ec2 578 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 579 spi.frequency(250000);
soumi_ghsoh 5:93c612f43ec2 580 }
soumi_ghsoh 5:93c612f43ec2 581
soumi_ghsoh 5:93c612f43ec2 582 void SpiInit2(void)
soumi_ghsoh 5:93c612f43ec2 583 {
soumi_ghsoh 5:93c612f43ec2 584 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 585 spi.frequency(1000000);
soumi_ghsoh 5:93c612f43ec2 586 }
soumi_ghsoh 5:93c612f43ec2 587
soumi_ghsoh 5:93c612f43ec2 588 void NFCInit(void)
soumi_ghsoh 5:93c612f43ec2 589 {wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 590 //RESET =================================================================
soumi_ghsoh 5:93c612f43ec2 591 //testcommand[0]=RESET;
soumi_ghsoh 5:93c612f43ec2 592 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 593 //=======================================================================
soumi_ghsoh 5:93c612f43ec2 594
soumi_ghsoh 5:93c612f43ec2 595
soumi_ghsoh 5:93c612f43ec2 596 testcommand[0] = SOFT_INIT;
soumi_ghsoh 5:93c612f43ec2 597 trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 598 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 599 testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 600 trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 601 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 602 //testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 603 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 604 ////Write Modulator and SYS_CLK Control Register (0x09) ====================
soumi_ghsoh 5:93c612f43ec2 605 ////(13.56Mhz SYS_CLK and default Clock 13.56Mhz))==========================
soumi_ghsoh 5:93c612f43ec2 606 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 607 testcommand[1] = 0x21; // 6.78 MHz, OOK 100%
soumi_ghsoh 5:93c612f43ec2 608 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 609 //////========================================================================
soumi_ghsoh 5:93c612f43ec2 610 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 611
soumi_ghsoh 5:93c612f43ec2 612 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 613 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 5:93c612f43ec2 614 //====================================================================8 clk cycles
soumi_ghsoh 5:93c612f43ec2 615 //testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 616 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 617 //testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 618 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 619 //====================================================================
soumi_ghsoh 5:93c612f43ec2 620 ////Turn RF ON (Chip Status Control Register (0x00))========================
soumi_ghsoh 5:93c612f43ec2 621
soumi_ghsoh 5:93c612f43ec2 622 //Configure Mode ISO Control Register (0x01) to 0x02======================
soumi_ghsoh 5:93c612f43ec2 623 //(ISO15693 high bit rate, one subcarrier, 1 out of 4)====================
soumi_ghsoh 5:93c612f43ec2 624
soumi_ghsoh 5:93c612f43ec2 625 //testcommand[0]=0x0F;//reset
soumi_ghsoh 5:93c612f43ec2 626 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 627 //====================================================================8 clk cycles
soumi_ghsoh 5:93c612f43ec2 628 //testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 629 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 630 //testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 631 //trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 632
soumi_ghsoh 5:93c612f43ec2 633 //====================================================================
soumi_ghsoh 5:93c612f43ec2 634
soumi_ghsoh 5:93c612f43ec2 635 ////========================================================================
soumi_ghsoh 5:93c612f43ec2 636 }
soumi_ghsoh 5:93c612f43ec2 637
soumi_ghsoh 5:93c612f43ec2 638 void RegisterReInitNFC(void)
soumi_ghsoh 5:93c612f43ec2 639 {testcommand[0] = TX_TIMER_EPC_HIGH;
soumi_ghsoh 5:93c612f43ec2 640 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 641 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 642 testcommand[0] = TX_TIMER_EPC_LOW ;
soumi_ghsoh 5:93c612f43ec2 643 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 644 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 645 testcommand[0] = TX_PULSE_LENGTH_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 646 testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 647 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 648 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 649 testcommand[1] = 0x30;
soumi_ghsoh 5:93c612f43ec2 650 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 651 testcommand[0] = RX_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 652 testcommand[1] = 0x0F;
soumi_ghsoh 5:93c612f43ec2 653 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 654 testcommand[0] = MODULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 655 testcommand[1] = 0x21; //0x34 100%ook@13MHz
soumi_ghsoh 5:93c612f43ec2 656 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 657 testcommand[0] = RX_SPECIAL_SETTINGS ;
soumi_ghsoh 5:93c612f43ec2 658 testcommand[1] = 0x41;
soumi_ghsoh 5:93c612f43ec2 659 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 660 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 661 testcommand[1] = 0x87;
soumi_ghsoh 5:93c612f43ec2 662 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 663 }