Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

readerComm.cpp@6:3c510c297e2f, 2015-04-02 (annotated)

Committer:
soumi_ghsoh
Date:
Thu Apr 02 21:10:48 2015 +0000
Revision:
6:3c510c297e2f
Parent:
5:93c612f43ec2
Child:
7:96baf1b2fd07
Added ReadNFC(), InventoryReqNFC()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 2 Filename: readerComm.cpp
rwclough 1:1eb96189824d 3 Description: Functions used to communicate with the TRF7970 eval bd.
rwclough 1:1eb96189824d 4 Communication is by means of an SPI interface between
rwclough 1:1eb96189824d 5 the nRF51-DK board (nRF51422 MCU) and the TRF7970 eval bd.
rwclough 1:1eb96189824d 6 Copyright (C) 2015 Gymtrack, Inc.
rwclough 1:1eb96189824d 7 Author: Ron Clough
rwclough 1:1eb96189824d 8 Date: 2015-02-27
rwclough 1:1eb96189824d 9
rwclough 1:1eb96189824d 10 Changes:
rwclough 1:1eb96189824d 11 Rev Date Who Details
rwclough 1:1eb96189824d 12 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
rwclough 2:bd5afc5aa139 13 0.0 2015-02-27 RWC Original version.
rwclough 1:1eb96189824d 14
rwclough 1:1eb96189824d 15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
soumi_ghsoh 6:3c510c297e2f 16 /*==========================================================================
soumi_ghsoh 6:3c510c297e2f 17 Initialize the chipset ISO15693 and read UID:
soumi_ghsoh 6:3c510c297e2f 18 1) Reset
soumi_ghsoh 6:3c510c297e2f 19 [0x83]
soumi_ghsoh 6:3c510c297e2f 20 2) Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz))
soumi_ghsoh 6:3c510c297e2f 21 [0x09 0x31]
soumi_ghsoh 6:3c510c297e2f 22 3) Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4)
soumi_ghsoh 6:3c510c297e2f 23 [0x01 0x02]
soumi_ghsoh 6:3c510c297e2f 24 4) Turn RF ON (Chip Status Control Register (0x00))
soumi_ghsoh 6:3c510c297e2f 25 [0x40 r] [0x00 0x20] [0x40 r]
soumi_ghsoh 6:3c510c297e2f 26 5) Inventory Command (see Figure 5-20. Inventory Command Sent From MCU to TRF7970A)
soumi_ghsoh 6:3c510c297e2f 27 5-1) Send Inventory(8B), Wait 2ms, Read/Clear IRQ Status(0x0C=>0x6C)+dummy read,
soumi_ghsoh 6:3c510c297e2f 28 Read FIFO Status Register(0x1C/0x5C), Read Continuous FIFO from 0x1F to 0x1F+0x0A(0x1F/0x7F),
soumi_ghsoh 6:3c510c297e2f 29 Read/Clear IRQ Status(0x0C=>0x6C)+dummy read, Read FIFO Status Register(0x1C/0x5C),
soumi_ghsoh 6:3c510c297e2f 30 Reset FIFO(0x0F/0x8F), Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 31 [0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00] %:2 [0x6C r:2] [0x5C r] [0x7F r:10] %:10 [0x6C r:2] [0x5C r] [0x8F] [0x4F r]
soumi_ghsoh 6:3c510c297e2f 32 ==============================================================================*/
soumi_ghsoh 6:3c510c297e2f 33
soumi_ghsoh 6:3c510c297e2f 34
soumi_ghsoh 6:3c510c297e2f 35
soumi_ghsoh 6:3c510c297e2f 36
soumi_ghsoh 6:3c510c297e2f 37
rwclough 1:1eb96189824d 38
rwclough 1:1eb96189824d 39 #include "mbed.h"
rwclough 1:1eb96189824d 40 #include "readerComm.h"
rwclough 3:eaae5433ab45 41 #include "interruptStuff.h"
soumi_ghsoh 5:93c612f43ec2 42 //#include "main.h"
soumi_ghsoh 5:93c612f43ec2 43 DigitalOut enable(p4); // Control EN pin on TRF7970
soumi_ghsoh 5:93c612f43ec2 44 //DigitalOut enable2(p3); // Control EN2 pin on TRF7970
soumi_ghsoh 5:93c612f43ec2 45 DigitalOut CS(p19);
soumi_ghsoh 5:93c612f43ec2 46 uint8_t turnRFOn[2];
soumi_ghsoh 5:93c612f43ec2 47 uint8_t testcommand[2];
rwclough 2:bd5afc5aa139 48 uint8_t afi = 0;
rwclough 2:bd5afc5aa139 49 uint8_t flags = 0; // Stores the mask value (used in anticollision)
rwclough 2:bd5afc5aa139 50 uint8_t command[2];
rwclough 2:bd5afc5aa139 51 uint8_t temp;
soumi_ghsoh 5:93c612f43ec2 52
rwclough 2:bd5afc5aa139 53 extern SPI spi; // main.cpp
rwclough 2:bd5afc5aa139 54 extern Serial pc; // main.cpp
soumi_ghsoh 5:93c612f43ec2 55 //extern DigitalOut CS; // main.cpp
rwclough 2:bd5afc5aa139 56 extern InterruptIn readerInt; // main.cpp
rwclough 2:bd5afc5aa139 57 extern int8_t rxtxState; // Transmit/Receive byte count (main.cpp)
rwclough 2:bd5afc5aa139 58 extern uint8_t buf[300]; // main.cpp
rwclough 2:bd5afc5aa139 59 extern uint8_t irqRegister; // Interrupt register (main.cpp)
rwclough 3:eaae5433ab45 60 volatile extern uint8_t irqFlag; // main.cpp
rwclough 2:bd5afc5aa139 61 extern uint8_t rxErrorFlag; // main.cpp
rwclough 2:bd5afc5aa139 62 extern uint8_t readerMode; // Determines how interrupts will be handled (main.cpp)
rwclough 2:bd5afc5aa139 63 extern uint8_t buffer[2];
rwclough 2:bd5afc5aa139 64
rwclough 3:eaae5433ab45 65 extern uint8_t tagFlag;
rwclough 3:eaae5433ab45 66 extern DigitalIn irqPin;
rwclough 3:eaae5433ab45 67 extern DigitalOut debug1LED;
rwclough 3:eaae5433ab45 68 extern DigitalOut debug2LED;
rwclough 3:eaae5433ab45 69 extern DigitalOut ISO15693LED;
rwclough 3:eaae5433ab45 70 extern DigitalOut heartbeatLED;
rwclough 3:eaae5433ab45 71
rwclough 3:eaae5433ab45 72 extern DigitalOut testPin;
rwclough 3:eaae5433ab45 73
rwclough 4:9ab0d84bbd07 74 extern uint8_t debugBuffer[1000]; // Capture data for analysis
rwclough 4:9ab0d84bbd07 75 extern uint8_t bufIdx;
rwclough 4:9ab0d84bbd07 76
rwclough 1:1eb96189824d 77
rwclough 4:9ab0d84bbd07 78
rwclough 4:9ab0d84bbd07 79 void trf797xDirectCommand(uint8_t *buffer)
rwclough 1:1eb96189824d 80 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 81 // trf797xDirectCommand()
rwclough 1:1eb96189824d 82 // Description: Transmit a Direct Command to the reader chip.
rwclough 1:1eb96189824d 83 // Parameter: *buffer = the direct command.
rwclough 1:1eb96189824d 84 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 85 {
rwclough 1:1eb96189824d 86 *buffer = (0x80 | *buffer); // Setup command mode
rwclough 2:bd5afc5aa139 87 *buffer = (0x9F & *buffer); // Setup command mode
rwclough 1:1eb96189824d 88 CS = SELECT;
rwclough 1:1eb96189824d 89 spi.write(*buffer);
rwclough 1:1eb96189824d 90 CS = DESELECT;
rwclough 4:9ab0d84bbd07 91 } // End of trf797xDirectCommand()
rwclough 1:1eb96189824d 92
rwclough 4:9ab0d84bbd07 93 void trf797xWriteSingle(uint8_t *buffer, uint8_t length)
rwclough 1:1eb96189824d 94 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 95 // trf797xWriteSingle()
rwclough 1:1eb96189824d 96 // Description: Writes to specified reader registers.
rwclough 1:1eb96189824d 97 // Parameters: *buffer = addresses of the registers followed by the
rwclough 2:bd5afc5aa139 98 // contents to write.
rwclough 1:1eb96189824d 99 // length = number of registers * 2.
rwclough 1:1eb96189824d 100 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 101 {
rwclough 2:bd5afc5aa139 102 uint8_t i=0;
rwclough 1:1eb96189824d 103
rwclough 1:1eb96189824d 104 CS = SELECT;
rwclough 1:1eb96189824d 105 while(length > 0) {
rwclough 2:bd5afc5aa139 106 *buffer = (0x1F & *buffer); // Register address
rwclough 1:1eb96189824d 107 for(i = 0; i < 2; i++) {
rwclough 1:1eb96189824d 108 spi.write(*buffer);
rwclough 1:1eb96189824d 109 buffer++;
rwclough 1:1eb96189824d 110 length--;
rwclough 2:bd5afc5aa139 111 }
rwclough 2:bd5afc5aa139 112 }
rwclough 1:1eb96189824d 113 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 114
rwclough 4:9ab0d84bbd07 115 } // End of trf797xWriteSingle()
rwclough 1:1eb96189824d 116
rwclough 4:9ab0d84bbd07 117 void trf797xReadSingle(uint8_t *buffer, uint8_t number)
rwclough 1:1eb96189824d 118 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 119 // trf797xReadSingle()
rwclough 1:1eb96189824d 120 // Description: Reads specified reader chip registers and
rwclough 1:1eb96189824d 121 // writes register contents to *buffer.
rwclough 1:1eb96189824d 122 // Parameters: *buffer = addresses of the registers.
rwclough 1:1eb96189824d 123 // number = number of registers.
rwclough 1:1eb96189824d 124 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 125 {
rwclough 1:1eb96189824d 126 CS = SELECT;
rwclough 1:1eb96189824d 127 while(number > 0) {
rwclough 1:1eb96189824d 128 *buffer = (0x40 | *buffer); // Address, read, single
rwclough 2:bd5afc5aa139 129 *buffer = (0x5F & *buffer); // Register address
rwclough 3:eaae5433ab45 130 spi.write(*buffer);
rwclough 2:bd5afc5aa139 131 *buffer = spi.write(0x00); // *buffer <- register contents
rwclough 1:1eb96189824d 132 buffer++;
rwclough 1:1eb96189824d 133 number--;
rwclough 2:bd5afc5aa139 134 }
rwclough 2:bd5afc5aa139 135 CS = DESELECT;
rwclough 4:9ab0d84bbd07 136 } // End of trf797xReadSingle()
rwclough 2:bd5afc5aa139 137
rwclough 4:9ab0d84bbd07 138 void trf797xReadContinuous(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 139 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 140 // trf797xReadContinuous()
rwclough 2:bd5afc5aa139 141 // Description: Used in SPI mode to read a specified number of
rwclough 2:bd5afc5aa139 142 // reader chip registers from a specified address upwards.
rwclough 2:bd5afc5aa139 143 // Contents of the registers are stored in *buffer.
rwclough 4:9ab0d84bbd07 144 // 1) Read register(s)
rwclough 4:9ab0d84bbd07 145 // 2) Write contents to *buffer
rwclough 2:bd5afc5aa139 146 // Parameters: *buffer = address of first register.
rwclough 2:bd5afc5aa139 147 // length = number of registers to read.
rwclough 2:bd5afc5aa139 148 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 5:93c612f43ec2 149 { //==================tested wrk $sg
rwclough 2:bd5afc5aa139 150 CS = SELECT;
rwclough 2:bd5afc5aa139 151 *buffer = (0x60 | *buffer); // Address, read, continuous
rwclough 3:eaae5433ab45 152 *buffer = (0x7F & *buffer); // Register address
rwclough 2:bd5afc5aa139 153 spi.write(*buffer);
rwclough 2:bd5afc5aa139 154 while(length > 0) {
rwclough 2:bd5afc5aa139 155 *buffer = spi.write(0x00);
rwclough 2:bd5afc5aa139 156 buffer++;
rwclough 2:bd5afc5aa139 157 length--;
rwclough 3:eaae5433ab45 158 }
rwclough 4:9ab0d84bbd07 159 // spi.write(0x00); spi.write(0x00); // 16 clock cycles, see TRF7970A FW Design Hints SLOA159 section 7.3
rwclough 1:1eb96189824d 160 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 161
soumi_ghsoh 5:93c612f43ec2 162 //=====================tested it wrks $sg
rwclough 4:9ab0d84bbd07 163 } // End of trf797xReadContinuous()
rwclough 2:bd5afc5aa139 164
rwclough 4:9ab0d84bbd07 165 void trf797xRawWrite(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 166 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 167 // trf797xRawWrite()
rwclough 2:bd5afc5aa139 168 // Description: Used in SPI mode to write direct to the reader chip.
rwclough 2:bd5afc5aa139 169 // Parameters: *buffer = raw data
rwclough 2:bd5afc5aa139 170 // length = number of data bytes
rwclough 2:bd5afc5aa139 171 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 172 {
rwclough 2:bd5afc5aa139 173 CS = SELECT;
rwclough 2:bd5afc5aa139 174 while(length > 0) {
rwclough 2:bd5afc5aa139 175 temp = spi.write(*buffer);
rwclough 2:bd5afc5aa139 176 buffer++;
rwclough 2:bd5afc5aa139 177 length--;
rwclough 2:bd5afc5aa139 178 }
rwclough 2:bd5afc5aa139 179 CS = DESELECT;
rwclough 4:9ab0d84bbd07 180 } // End of trf797xRawWrite()
rwclough 2:bd5afc5aa139 181
rwclough 4:9ab0d84bbd07 182 void trf797xStopDecoders(void)
rwclough 2:bd5afc5aa139 183 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 184 // trf797xStopDecoders()
rwclough 2:bd5afc5aa139 185 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 186 {
rwclough 2:bd5afc5aa139 187 command[0] = STOP_DECODERS;
rwclough 4:9ab0d84bbd07 188 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 189 }
rwclough 1:1eb96189824d 190
rwclough 4:9ab0d84bbd07 191 void trf797xRunDecoders(void)
rwclough 2:bd5afc5aa139 192 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 193 // trf797xRunDecoders()
rwclough 2:bd5afc5aa139 194 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 195 {
rwclough 2:bd5afc5aa139 196 command[0] = RUN_DECODERS;
rwclough 4:9ab0d84bbd07 197 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 198 }
rwclough 2:bd5afc5aa139 199
soumi_ghsoh 5:93c612f43ec2 200
soumi_ghsoh 5:93c612f43ec2 201 void PowerUpNFC(void)
soumi_ghsoh 6:3c510c297e2f 202 {CS = 1;
soumi_ghsoh 6:3c510c297e2f 203 wait_ms(4);
soumi_ghsoh 6:3c510c297e2f 204 enable = 1;
soumi_ghsoh 6:3c510c297e2f 205 }
soumi_ghsoh 6:3c510c297e2f 206 void PowerDownNFC(void)
soumi_ghsoh 6:3c510c297e2f 207 {enable = 0;
soumi_ghsoh 5:93c612f43ec2 208 }
soumi_ghsoh 5:93c612f43ec2 209
soumi_ghsoh 5:93c612f43ec2 210 void SpiInit1(void)
soumi_ghsoh 5:93c612f43ec2 211 {
soumi_ghsoh 5:93c612f43ec2 212 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 213 spi.frequency(250000);
soumi_ghsoh 5:93c612f43ec2 214 }
soumi_ghsoh 5:93c612f43ec2 215
soumi_ghsoh 6:3c510c297e2f 216 void SpiInit(void)
soumi_ghsoh 5:93c612f43ec2 217 {
soumi_ghsoh 5:93c612f43ec2 218 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 219 spi.frequency(1000000);
soumi_ghsoh 5:93c612f43ec2 220 }
soumi_ghsoh 5:93c612f43ec2 221
soumi_ghsoh 5:93c612f43ec2 222 void NFCInit(void)
soumi_ghsoh 6:3c510c297e2f 223 {
soumi_ghsoh 6:3c510c297e2f 224 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 225 testcommand[0] = SOFT_INIT;
soumi_ghsoh 5:93c612f43ec2 226 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 227 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 228 testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 229 trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 230 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 231 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 232 testcommand[1] = 0x21; // 6.78 MHz, OOK 100%
soumi_ghsoh 5:93c612f43ec2 233 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 234 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 235 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 236 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 237 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 238 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 239 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 240 turnRFOn[1] |= 0x20;
soumi_ghsoh 6:3c510c297e2f 241 // Oroiginal code has 0x20 !!!
soumi_ghsoh 6:3c510c297e2f 242 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 6:3c510c297e2f 243 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 244 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 245
soumi_ghsoh 6:3c510c297e2f 246 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 247 turnRFOn[1] |= 0x20;
soumi_ghsoh 6:3c510c297e2f 248 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 6:3c510c297e2f 249 //wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 250
soumi_ghsoh 6:3c510c297e2f 251 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 252 testcommand[1] = 0x02; // 6.78 MHz, OOK 100%
soumi_ghsoh 6:3c510c297e2f 253 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 254 //wait_ms(6);
soumi_ghsoh 5:93c612f43ec2 255 }
soumi_ghsoh 5:93c612f43ec2 256
soumi_ghsoh 5:93c612f43ec2 257 void RegisterReInitNFC(void)
soumi_ghsoh 5:93c612f43ec2 258 {testcommand[0] = TX_TIMER_EPC_HIGH;
soumi_ghsoh 5:93c612f43ec2 259 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 260 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 261 testcommand[0] = TX_TIMER_EPC_LOW ;
soumi_ghsoh 5:93c612f43ec2 262 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 263 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 264 testcommand[0] = TX_PULSE_LENGTH_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 265 testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 266 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 267 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 268 testcommand[1] = 0x30;
soumi_ghsoh 5:93c612f43ec2 269 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 270 testcommand[0] = RX_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 271 testcommand[1] = 0x1F;
soumi_ghsoh 5:93c612f43ec2 272 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 273 testcommand[0] = MODULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 274 testcommand[1] = 0x21; //0x34 100%ook@13MHz
soumi_ghsoh 5:93c612f43ec2 275 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 276 testcommand[0] = RX_SPECIAL_SETTINGS ;
soumi_ghsoh 6:3c510c297e2f 277 testcommand[1] = 0x40;
soumi_ghsoh 5:93c612f43ec2 278 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 279 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 280 testcommand[1] = 0x87;
soumi_ghsoh 5:93c612f43ec2 281 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 282 }
soumi_ghsoh 6:3c510c297e2f 283
soumi_ghsoh 6:3c510c297e2f 284
soumi_ghsoh 6:3c510c297e2f 285 void RegistersReadNFC(void)
soumi_ghsoh 6:3c510c297e2f 286 {
soumi_ghsoh 6:3c510c297e2f 287 testcommand[0] = TX_TIMER_EPC_HIGH; //0xC1;
soumi_ghsoh 6:3c510c297e2f 288 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 289 testcommand[0] = TX_TIMER_EPC_LOW ; //0xC1;
soumi_ghsoh 6:3c510c297e2f 290 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 291 testcommand[0] = TX_PULSE_LENGTH_CONTROL ; //0x00;
soumi_ghsoh 6:3c510c297e2f 292 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 293 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ; //0x30;
soumi_ghsoh 6:3c510c297e2f 294 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 295 testcommand[0] = RX_WAIT_TIME ; //0x1F;
soumi_ghsoh 6:3c510c297e2f 296 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 297 testcommand[0] = MODULATOR_CONTROL ; //0x21;
soumi_ghsoh 6:3c510c297e2f 298 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 299 testcommand[0] = RX_SPECIAL_SETTINGS ; //0x40;
soumi_ghsoh 6:3c510c297e2f 300 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 301 testcommand[0] = REGULATOR_CONTROL ; //0x87;
soumi_ghsoh 6:3c510c297e2f 302 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 303 }
soumi_ghsoh 6:3c510c297e2f 304
soumi_ghsoh 6:3c510c297e2f 305 void InventoryReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 306 {
soumi_ghsoh 6:3c510c297e2f 307 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 308 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 309 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 310 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 311 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 312 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 313 buf[5]=0x26;
soumi_ghsoh 6:3c510c297e2f 314 buf[6]=0x01;
soumi_ghsoh 6:3c510c297e2f 315 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 316 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 6:3c510c297e2f 317 wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 318 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 319 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 320 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 321 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 322 wait_ms(5);
soumi_ghsoh 6:3c510c297e2f 323 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 324 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 325 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 326 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 327 testcommand[0] = FIFO_CONTROL; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 6:3c510c297e2f 328 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 329 testcommand[0] = 0x7F & testcommand[0]; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 330 buf[0] = FIFO;
soumi_ghsoh 6:3c510c297e2f 331 trf797xReadContinuous(&buf[0], testcommand[0]);
soumi_ghsoh 6:3c510c297e2f 332 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 333 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 334 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 335 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 336 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 337 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 338 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 339 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 340 trf797xStopDecoders();
soumi_ghsoh 6:3c510c297e2f 341 trf797xRunDecoders();
soumi_ghsoh 6:3c510c297e2f 342 //wait(1);
soumi_ghsoh 6:3c510c297e2f 343 }
soumi_ghsoh 6:3c510c297e2f 344 //void PollNFC(void)
soumi_ghsoh 6:3c510c297e2f 345 //{
soumi_ghsoh 6:3c510c297e2f 346 //}
soumi_ghsoh 6:3c510c297e2f 347
soumi_ghsoh 6:3c510c297e2f 348 void ReadNFC(void)
soumi_ghsoh 6:3c510c297e2f 349 {testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 350 testcommand[1] = 0xFF;
soumi_ghsoh 6:3c510c297e2f 351 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 352 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 353 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 354 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 355 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 356 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 357 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 358 buf[5]=0x02;
soumi_ghsoh 6:3c510c297e2f 359 buf[6]=0x20;
soumi_ghsoh 6:3c510c297e2f 360 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 361 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 6:3c510c297e2f 362 wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 363 testPin=1;
soumi_ghsoh 6:3c510c297e2f 364 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 365 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 366 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 367 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 368 wait_ms(5);
soumi_ghsoh 6:3c510c297e2f 369 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 370 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 371 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 372 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 373 testcommand[0] = FIFO_CONTROL; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 6:3c510c297e2f 374 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 375 testcommand[0] = 0x7F & testcommand[0]; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 376 buf[0] = FIFO;
soumi_ghsoh 6:3c510c297e2f 377 trf797xReadContinuous(&buf[0], testcommand[0]);
soumi_ghsoh 6:3c510c297e2f 378 testPin=0;
soumi_ghsoh 6:3c510c297e2f 379 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 380 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 381 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 382 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 383 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 384 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 385 //wait(1);
soumi_ghsoh 5:93c612f43ec2 386 }