Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

readerComm.cpp@9:9266e0109d26, 2015-04-08 (annotated)

Committer:
soumi_ghsoh
Date:
Wed Apr 08 20:48:05 2015 +0000
Revision:
9:9266e0109d26
Parent:
7:96baf1b2fd07
Child:
10:98a58968dc7d
power modes sg

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 2 Filename: readerComm.cpp
rwclough 1:1eb96189824d 3 Description: Functions used to communicate with the TRF7970 eval bd.
rwclough 1:1eb96189824d 4 Communication is by means of an SPI interface between
rwclough 1:1eb96189824d 5 the nRF51-DK board (nRF51422 MCU) and the TRF7970 eval bd.
rwclough 1:1eb96189824d 6 Copyright (C) 2015 Gymtrack, Inc.
rwclough 1:1eb96189824d 7 Author: Ron Clough
rwclough 1:1eb96189824d 8 Date: 2015-02-27
rwclough 1:1eb96189824d 9
rwclough 1:1eb96189824d 10 Changes:
rwclough 1:1eb96189824d 11 Rev Date Who Details
rwclough 1:1eb96189824d 12 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
rwclough 2:bd5afc5aa139 13 0.0 2015-02-27 RWC Original version.
rwclough 1:1eb96189824d 14
rwclough 1:1eb96189824d 15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
soumi_ghsoh 6:3c510c297e2f 16 /*==========================================================================
soumi_ghsoh 6:3c510c297e2f 17 Initialize the chipset ISO15693 and read UID:
soumi_ghsoh 6:3c510c297e2f 18 1) Reset
soumi_ghsoh 6:3c510c297e2f 19 [0x83]
soumi_ghsoh 6:3c510c297e2f 20 2) Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz))
soumi_ghsoh 6:3c510c297e2f 21 [0x09 0x31]
soumi_ghsoh 6:3c510c297e2f 22 3) Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4)
soumi_ghsoh 6:3c510c297e2f 23 [0x01 0x02]
soumi_ghsoh 6:3c510c297e2f 24 4) Turn RF ON (Chip Status Control Register (0x00))
soumi_ghsoh 6:3c510c297e2f 25 [0x40 r] [0x00 0x20] [0x40 r]
soumi_ghsoh 6:3c510c297e2f 26 5) Inventory Command (see Figure 5-20. Inventory Command Sent From MCU to TRF7970A)
soumi_ghsoh 6:3c510c297e2f 27 5-1) Send Inventory(8B), Wait 2ms, Read/Clear IRQ Status(0x0C=>0x6C)+dummy read,
soumi_ghsoh 6:3c510c297e2f 28 Read FIFO Status Register(0x1C/0x5C), Read Continuous FIFO from 0x1F to 0x1F+0x0A(0x1F/0x7F),
soumi_ghsoh 6:3c510c297e2f 29 Read/Clear IRQ Status(0x0C=>0x6C)+dummy read, Read FIFO Status Register(0x1C/0x5C),
soumi_ghsoh 6:3c510c297e2f 30 Reset FIFO(0x0F/0x8F), Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 31 [0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00] %:2 [0x6C r:2] [0x5C r] [0x7F r:10] %:10 [0x6C r:2] [0x5C r] [0x8F] [0x4F r]
soumi_ghsoh 6:3c510c297e2f 32 ==============================================================================*/
soumi_ghsoh 6:3c510c297e2f 33
soumi_ghsoh 6:3c510c297e2f 34
soumi_ghsoh 6:3c510c297e2f 35
soumi_ghsoh 6:3c510c297e2f 36
soumi_ghsoh 6:3c510c297e2f 37
rwclough 1:1eb96189824d 38
rwclough 1:1eb96189824d 39 #include "mbed.h"
rwclough 1:1eb96189824d 40 #include "readerComm.h"
soumi_ghsoh 7:96baf1b2fd07 41
soumi_ghsoh 9:9266e0109d26 42 DigitalOut EN(p4); // Control EN pin on TRF7970
soumi_ghsoh 9:9266e0109d26 43 DigitalOut EN2(p3); // Control EN2 pin on TRF7970
soumi_ghsoh 5:93c612f43ec2 44 DigitalOut CS(p19);
soumi_ghsoh 5:93c612f43ec2 45 uint8_t turnRFOn[2];
soumi_ghsoh 5:93c612f43ec2 46 uint8_t testcommand[2];
soumi_ghsoh 7:96baf1b2fd07 47 extern uint8_t noBytes;
rwclough 2:bd5afc5aa139 48 extern SPI spi; // main.cpp
rwclough 2:bd5afc5aa139 49 extern Serial pc; // main.cpp
rwclough 2:bd5afc5aa139 50 extern uint8_t buf[300]; // main.cpp
soumi_ghsoh 7:96baf1b2fd07 51 extern uint8_t found;
rwclough 3:eaae5433ab45 52 extern DigitalOut debug1LED;
rwclough 3:eaae5433ab45 53 extern DigitalOut debug2LED;
rwclough 3:eaae5433ab45 54 extern DigitalOut ISO15693LED;
rwclough 3:eaae5433ab45 55 extern DigitalOut heartbeatLED;
rwclough 3:eaae5433ab45 56 extern DigitalOut testPin;
soumi_ghsoh 7:96baf1b2fd07 57 uint8_t temp;
soumi_ghsoh 7:96baf1b2fd07 58 uint8_t command[2];
rwclough 4:9ab0d84bbd07 59
rwclough 4:9ab0d84bbd07 60 void trf797xDirectCommand(uint8_t *buffer)
rwclough 1:1eb96189824d 61 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 62 // trf797xDirectCommand()
rwclough 1:1eb96189824d 63 // Description: Transmit a Direct Command to the reader chip.
rwclough 1:1eb96189824d 64 // Parameter: *buffer = the direct command.
rwclough 1:1eb96189824d 65 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 66 {
rwclough 1:1eb96189824d 67 *buffer = (0x80 | *buffer); // Setup command mode
rwclough 2:bd5afc5aa139 68 *buffer = (0x9F & *buffer); // Setup command mode
rwclough 1:1eb96189824d 69 CS = SELECT;
rwclough 1:1eb96189824d 70 spi.write(*buffer);
rwclough 1:1eb96189824d 71 CS = DESELECT;
rwclough 4:9ab0d84bbd07 72 } // End of trf797xDirectCommand()
rwclough 1:1eb96189824d 73
rwclough 4:9ab0d84bbd07 74 void trf797xWriteSingle(uint8_t *buffer, uint8_t length)
rwclough 1:1eb96189824d 75 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 76 // trf797xWriteSingle()
rwclough 1:1eb96189824d 77 // Description: Writes to specified reader registers.
rwclough 1:1eb96189824d 78 // Parameters: *buffer = addresses of the registers followed by the
rwclough 2:bd5afc5aa139 79 // contents to write.
rwclough 1:1eb96189824d 80 // length = number of registers * 2.
rwclough 1:1eb96189824d 81 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 82 {
rwclough 2:bd5afc5aa139 83 uint8_t i=0;
rwclough 1:1eb96189824d 84
rwclough 1:1eb96189824d 85 CS = SELECT;
rwclough 1:1eb96189824d 86 while(length > 0) {
rwclough 2:bd5afc5aa139 87 *buffer = (0x1F & *buffer); // Register address
rwclough 1:1eb96189824d 88 for(i = 0; i < 2; i++) {
rwclough 1:1eb96189824d 89 spi.write(*buffer);
rwclough 1:1eb96189824d 90 buffer++;
rwclough 1:1eb96189824d 91 length--;
rwclough 2:bd5afc5aa139 92 }
rwclough 2:bd5afc5aa139 93 }
rwclough 1:1eb96189824d 94 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 95
rwclough 4:9ab0d84bbd07 96 } // End of trf797xWriteSingle()
rwclough 1:1eb96189824d 97
rwclough 4:9ab0d84bbd07 98 void trf797xReadSingle(uint8_t *buffer, uint8_t number)
rwclough 1:1eb96189824d 99 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 100 // trf797xReadSingle()
rwclough 1:1eb96189824d 101 // Description: Reads specified reader chip registers and
rwclough 1:1eb96189824d 102 // writes register contents to *buffer.
rwclough 1:1eb96189824d 103 // Parameters: *buffer = addresses of the registers.
rwclough 1:1eb96189824d 104 // number = number of registers.
rwclough 1:1eb96189824d 105 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 106 {
rwclough 1:1eb96189824d 107 CS = SELECT;
rwclough 1:1eb96189824d 108 while(number > 0) {
rwclough 1:1eb96189824d 109 *buffer = (0x40 | *buffer); // Address, read, single
rwclough 2:bd5afc5aa139 110 *buffer = (0x5F & *buffer); // Register address
rwclough 3:eaae5433ab45 111 spi.write(*buffer);
rwclough 2:bd5afc5aa139 112 *buffer = spi.write(0x00); // *buffer <- register contents
rwclough 1:1eb96189824d 113 buffer++;
rwclough 1:1eb96189824d 114 number--;
rwclough 2:bd5afc5aa139 115 }
rwclough 2:bd5afc5aa139 116 CS = DESELECT;
rwclough 4:9ab0d84bbd07 117 } // End of trf797xReadSingle()
rwclough 2:bd5afc5aa139 118
rwclough 4:9ab0d84bbd07 119 void trf797xReadContinuous(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 120 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 121 // trf797xReadContinuous()
rwclough 2:bd5afc5aa139 122 // Description: Used in SPI mode to read a specified number of
rwclough 2:bd5afc5aa139 123 // reader chip registers from a specified address upwards.
rwclough 2:bd5afc5aa139 124 // Contents of the registers are stored in *buffer.
rwclough 4:9ab0d84bbd07 125 // 1) Read register(s)
rwclough 4:9ab0d84bbd07 126 // 2) Write contents to *buffer
rwclough 2:bd5afc5aa139 127 // Parameters: *buffer = address of first register.
rwclough 2:bd5afc5aa139 128 // length = number of registers to read.
rwclough 2:bd5afc5aa139 129 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 5:93c612f43ec2 130 { //==================tested wrk $sg
rwclough 2:bd5afc5aa139 131 CS = SELECT;
rwclough 2:bd5afc5aa139 132 *buffer = (0x60 | *buffer); // Address, read, continuous
rwclough 3:eaae5433ab45 133 *buffer = (0x7F & *buffer); // Register address
rwclough 2:bd5afc5aa139 134 spi.write(*buffer);
rwclough 2:bd5afc5aa139 135 while(length > 0) {
rwclough 2:bd5afc5aa139 136 *buffer = spi.write(0x00);
rwclough 2:bd5afc5aa139 137 buffer++;
rwclough 2:bd5afc5aa139 138 length--;
rwclough 3:eaae5433ab45 139 }
rwclough 4:9ab0d84bbd07 140 // spi.write(0x00); spi.write(0x00); // 16 clock cycles, see TRF7970A FW Design Hints SLOA159 section 7.3
rwclough 1:1eb96189824d 141 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 142
soumi_ghsoh 5:93c612f43ec2 143 //=====================tested it wrks $sg
rwclough 4:9ab0d84bbd07 144 } // End of trf797xReadContinuous()
rwclough 2:bd5afc5aa139 145
rwclough 4:9ab0d84bbd07 146 void trf797xRawWrite(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 147 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 148 // trf797xRawWrite()
rwclough 2:bd5afc5aa139 149 // Description: Used in SPI mode to write direct to the reader chip.
rwclough 2:bd5afc5aa139 150 // Parameters: *buffer = raw data
rwclough 2:bd5afc5aa139 151 // length = number of data bytes
rwclough 2:bd5afc5aa139 152 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 153 {
rwclough 2:bd5afc5aa139 154 CS = SELECT;
rwclough 2:bd5afc5aa139 155 while(length > 0) {
rwclough 2:bd5afc5aa139 156 temp = spi.write(*buffer);
rwclough 2:bd5afc5aa139 157 buffer++;
rwclough 2:bd5afc5aa139 158 length--;
rwclough 2:bd5afc5aa139 159 }
rwclough 2:bd5afc5aa139 160 CS = DESELECT;
rwclough 4:9ab0d84bbd07 161 } // End of trf797xRawWrite()
rwclough 2:bd5afc5aa139 162
rwclough 4:9ab0d84bbd07 163 void trf797xStopDecoders(void)
rwclough 2:bd5afc5aa139 164 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 165 // trf797xStopDecoders()
rwclough 2:bd5afc5aa139 166 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 167 {
rwclough 2:bd5afc5aa139 168 command[0] = STOP_DECODERS;
rwclough 4:9ab0d84bbd07 169 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 170 }
rwclough 1:1eb96189824d 171
rwclough 4:9ab0d84bbd07 172 void trf797xRunDecoders(void)
rwclough 2:bd5afc5aa139 173 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 174 // trf797xRunDecoders()
rwclough 2:bd5afc5aa139 175 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 176 {
rwclough 2:bd5afc5aa139 177 command[0] = RUN_DECODERS;
rwclough 4:9ab0d84bbd07 178 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 179 }
rwclough 2:bd5afc5aa139 180
soumi_ghsoh 5:93c612f43ec2 181
soumi_ghsoh 5:93c612f43ec2 182 void PowerUpNFC(void)
soumi_ghsoh 9:9266e0109d26 183 {//CS = 1;
soumi_ghsoh 9:9266e0109d26 184 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 185 // EN = 1;
soumi_ghsoh 9:9266e0109d26 186 // EN2=1;
soumi_ghsoh 9:9266e0109d26 187
soumi_ghsoh 9:9266e0109d26 188 CS = 0; EN2 = 0; EN = 0;
soumi_ghsoh 9:9266e0109d26 189 wait_ms(2);
soumi_ghsoh 9:9266e0109d26 190 CS = 1;
soumi_ghsoh 9:9266e0109d26 191 wait_ms(3);
soumi_ghsoh 9:9266e0109d26 192 EN2 = 1;
soumi_ghsoh 9:9266e0109d26 193 wait_ms(1);
soumi_ghsoh 9:9266e0109d26 194 EN = 1;
soumi_ghsoh 9:9266e0109d26 195 }
soumi_ghsoh 9:9266e0109d26 196 void PowerUpNFC2(void)
soumi_ghsoh 9:9266e0109d26 197 {//CS = 1;
soumi_ghsoh 9:9266e0109d26 198 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 199 // EN = 1;
soumi_ghsoh 9:9266e0109d26 200 // EN2=1;
soumi_ghsoh 9:9266e0109d26 201
soumi_ghsoh 9:9266e0109d26 202 EN = 1;
soumi_ghsoh 9:9266e0109d26 203 //wait_ms(1);
soumi_ghsoh 9:9266e0109d26 204 EN2=0;
soumi_ghsoh 9:9266e0109d26 205
soumi_ghsoh 9:9266e0109d26 206 //wait_ms(1);
soumi_ghsoh 9:9266e0109d26 207 //EN2= 0;
soumi_ghsoh 6:3c510c297e2f 208 }
soumi_ghsoh 6:3c510c297e2f 209 void PowerDownNFC(void)
soumi_ghsoh 9:9266e0109d26 210 {EN = 0;
soumi_ghsoh 9:9266e0109d26 211 //wait_ms(1);
soumi_ghsoh 9:9266e0109d26 212 EN2= 0;
soumi_ghsoh 9:9266e0109d26 213
soumi_ghsoh 5:93c612f43ec2 214 }
soumi_ghsoh 5:93c612f43ec2 215
soumi_ghsoh 5:93c612f43ec2 216 void SpiInit1(void)
soumi_ghsoh 5:93c612f43ec2 217 {
soumi_ghsoh 5:93c612f43ec2 218 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 219 spi.frequency(250000);
soumi_ghsoh 5:93c612f43ec2 220 }
soumi_ghsoh 5:93c612f43ec2 221
soumi_ghsoh 6:3c510c297e2f 222 void SpiInit(void)
soumi_ghsoh 5:93c612f43ec2 223 {
soumi_ghsoh 5:93c612f43ec2 224 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 225 spi.frequency(1000000);
soumi_ghsoh 5:93c612f43ec2 226 }
soumi_ghsoh 5:93c612f43ec2 227
soumi_ghsoh 5:93c612f43ec2 228 void NFCInit(void)
soumi_ghsoh 9:9266e0109d26 229 {testPin=1;
soumi_ghsoh 6:3c510c297e2f 230 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 231 testcommand[0] = SOFT_INIT;
soumi_ghsoh 5:93c612f43ec2 232 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 233 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 234 testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 235 trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 236 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 237 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 238 testcommand[1] = 0x21; // 6.78 MHz, OOK 100%
soumi_ghsoh 5:93c612f43ec2 239 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 240 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 241 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 242 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 243 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 244 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 245 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 246 turnRFOn[1] |= 0x20;
soumi_ghsoh 6:3c510c297e2f 247 // Oroiginal code has 0x20 !!!
soumi_ghsoh 6:3c510c297e2f 248 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 6:3c510c297e2f 249 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 250 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 251
soumi_ghsoh 6:3c510c297e2f 252 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 253 turnRFOn[1] |= 0x20;
soumi_ghsoh 6:3c510c297e2f 254 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 6:3c510c297e2f 255 //wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 256
soumi_ghsoh 6:3c510c297e2f 257 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 258 testcommand[1] = 0x02; // 6.78 MHz, OOK 100%
soumi_ghsoh 6:3c510c297e2f 259 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 260 //wait_ms(6);
soumi_ghsoh 9:9266e0109d26 261 testPin=0;}
soumi_ghsoh 5:93c612f43ec2 262
soumi_ghsoh 5:93c612f43ec2 263 void RegisterReInitNFC(void)
soumi_ghsoh 5:93c612f43ec2 264 {testcommand[0] = TX_TIMER_EPC_HIGH;
soumi_ghsoh 5:93c612f43ec2 265 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 266 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 267 testcommand[0] = TX_TIMER_EPC_LOW ;
soumi_ghsoh 5:93c612f43ec2 268 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 269 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 270 testcommand[0] = TX_PULSE_LENGTH_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 271 testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 272 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 273 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 274 testcommand[1] = 0x30;
soumi_ghsoh 5:93c612f43ec2 275 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 276 testcommand[0] = RX_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 277 testcommand[1] = 0x1F;
soumi_ghsoh 5:93c612f43ec2 278 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 279 testcommand[0] = MODULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 280 testcommand[1] = 0x21; //0x34 100%ook@13MHz
soumi_ghsoh 5:93c612f43ec2 281 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 282 testcommand[0] = RX_SPECIAL_SETTINGS ;
soumi_ghsoh 6:3c510c297e2f 283 testcommand[1] = 0x40;
soumi_ghsoh 5:93c612f43ec2 284 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 285 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 286 testcommand[1] = 0x87;
soumi_ghsoh 5:93c612f43ec2 287 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 288 }
soumi_ghsoh 6:3c510c297e2f 289
soumi_ghsoh 6:3c510c297e2f 290
soumi_ghsoh 6:3c510c297e2f 291 void RegistersReadNFC(void)
soumi_ghsoh 6:3c510c297e2f 292 {
soumi_ghsoh 6:3c510c297e2f 293 testcommand[0] = TX_TIMER_EPC_HIGH; //0xC1;
soumi_ghsoh 6:3c510c297e2f 294 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 295 testcommand[0] = TX_TIMER_EPC_LOW ; //0xC1;
soumi_ghsoh 6:3c510c297e2f 296 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 297 testcommand[0] = TX_PULSE_LENGTH_CONTROL ; //0x00;
soumi_ghsoh 6:3c510c297e2f 298 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 299 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ; //0x30;
soumi_ghsoh 6:3c510c297e2f 300 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 301 testcommand[0] = RX_WAIT_TIME ; //0x1F;
soumi_ghsoh 6:3c510c297e2f 302 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 303 testcommand[0] = MODULATOR_CONTROL ; //0x21;
soumi_ghsoh 6:3c510c297e2f 304 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 305 testcommand[0] = RX_SPECIAL_SETTINGS ; //0x40;
soumi_ghsoh 6:3c510c297e2f 306 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 307 testcommand[0] = REGULATOR_CONTROL ; //0x87;
soumi_ghsoh 6:3c510c297e2f 308 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 309 }
soumi_ghsoh 6:3c510c297e2f 310
soumi_ghsoh 6:3c510c297e2f 311 void InventoryReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 312 {
soumi_ghsoh 6:3c510c297e2f 313 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 314 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 315 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 316 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 317 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 318 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 319 buf[5]=0x26;
soumi_ghsoh 6:3c510c297e2f 320 buf[6]=0x01;
soumi_ghsoh 6:3c510c297e2f 321 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 322 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 6:3c510c297e2f 323 wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 324 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 325 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 326 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 327 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 328 wait_ms(5);
soumi_ghsoh 7:96baf1b2fd07 329 /*====================================read tag ID
soumi_ghsoh 6:3c510c297e2f 330 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 331 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 332 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 333 trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 334 testcommand[0] = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 6:3c510c297e2f 335 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 336 testcommand[0] = 0x7F & testcommand[0]; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 337 buf[0] = FIFO;
soumi_ghsoh 6:3c510c297e2f 338 trf797xReadContinuous(&buf[0], testcommand[0]);
soumi_ghsoh 6:3c510c297e2f 339 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 340 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 341 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 342 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 343 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 344 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 345 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 346 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 347 trf797xStopDecoders();
soumi_ghsoh 7:96baf1b2fd07 348 trf797xRunDecoders(); */
soumi_ghsoh 7:96baf1b2fd07 349 //=====================================read Tag ID
soumi_ghsoh 6:3c510c297e2f 350 //wait(1);
soumi_ghsoh 7:96baf1b2fd07 351 }
soumi_ghsoh 7:96baf1b2fd07 352
soumi_ghsoh 7:96baf1b2fd07 353 void PollNFC(uint8_t *irqStatus)
soumi_ghsoh 7:96baf1b2fd07 354 {// printf
soumi_ghsoh 7:96baf1b2fd07 355 if(*irqStatus==0x40)
soumi_ghsoh 7:96baf1b2fd07 356 { found=1;}
soumi_ghsoh 7:96baf1b2fd07 357 else found=0;
soumi_ghsoh 6:3c510c297e2f 358 }
soumi_ghsoh 7:96baf1b2fd07 359 void handlerNFC(void)
soumi_ghsoh 7:96baf1b2fd07 360 {
soumi_ghsoh 7:96baf1b2fd07 361 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 362 trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 363 PollNFC(testcommand);
soumi_ghsoh 7:96baf1b2fd07 364 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 365 trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 366 }
soumi_ghsoh 6:3c510c297e2f 367
soumi_ghsoh 7:96baf1b2fd07 368
soumi_ghsoh 7:96baf1b2fd07 369 void MemReadReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 370 {testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 371 testcommand[1] = 0xFF;
soumi_ghsoh 6:3c510c297e2f 372 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 373 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 374 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 375 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 376 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 377 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 378 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 379 buf[5]=0x02;
soumi_ghsoh 6:3c510c297e2f 380 buf[6]=0x20;
soumi_ghsoh 6:3c510c297e2f 381 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 382 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 6:3c510c297e2f 383 wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 384 testPin=1;
soumi_ghsoh 6:3c510c297e2f 385 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 386 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 387 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 388 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 389 wait_ms(5);
soumi_ghsoh 7:96baf1b2fd07 390 }
soumi_ghsoh 7:96baf1b2fd07 391 void ReadNFC(void)
soumi_ghsoh 7:96baf1b2fd07 392 {/*========================================== read irqstatus reg. of trf7970a
soumi_ghsoh 7:96baf1b2fd07 393 //testcommand[0] = IRQ_STATUS; clear irqstatus reg of trf7970a
soumi_ghsoh 7:96baf1b2fd07 394 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 395 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 396 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 397 ===========================================*/
soumi_ghsoh 7:96baf1b2fd07 398
soumi_ghsoh 7:96baf1b2fd07 399 noBytes = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 7:96baf1b2fd07 400 trf797xReadSingle(&noBytes, 1);
soumi_ghsoh 7:96baf1b2fd07 401 noBytes = 0x7F & noBytes; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 402 buf[0] = FIFO;
soumi_ghsoh 7:96baf1b2fd07 403 trf797xReadContinuous(&buf[0],noBytes);
soumi_ghsoh 7:96baf1b2fd07 404 //testPin=0;
soumi_ghsoh 6:3c510c297e2f 405 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 406 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 407 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 408 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 409 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 410 trf797xDirectCommand(testcommand);
soumi_ghsoh 7:96baf1b2fd07 411
soumi_ghsoh 6:3c510c297e2f 412 //wait(1);
soumi_ghsoh 9:9266e0109d26 413 }