Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

readerComm.cpp@10:98a58968dc7d, 2015-04-09 (annotated)

Committer:
soumi_ghsoh
Date:
Thu Apr 09 22:09:35 2015 +0000
Revision:
10:98a58968dc7d
Parent:
9:9266e0109d26
Child:
11:d5e8f47880f1
sg apr 9/15

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 2 Filename: readerComm.cpp
rwclough 1:1eb96189824d 3 Description: Functions used to communicate with the TRF7970 eval bd.
rwclough 1:1eb96189824d 4 Communication is by means of an SPI interface between
rwclough 1:1eb96189824d 5 the nRF51-DK board (nRF51422 MCU) and the TRF7970 eval bd.
rwclough 1:1eb96189824d 6 Copyright (C) 2015 Gymtrack, Inc.
rwclough 1:1eb96189824d 7 Author: Ron Clough
rwclough 1:1eb96189824d 8 Date: 2015-02-27
rwclough 1:1eb96189824d 9
rwclough 1:1eb96189824d 10 Changes:
rwclough 1:1eb96189824d 11 Rev Date Who Details
rwclough 1:1eb96189824d 12 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
rwclough 2:bd5afc5aa139 13 0.0 2015-02-27 RWC Original version.
rwclough 1:1eb96189824d 14
rwclough 1:1eb96189824d 15 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
soumi_ghsoh 6:3c510c297e2f 16 /*==========================================================================
soumi_ghsoh 6:3c510c297e2f 17 Initialize the chipset ISO15693 and read UID:
soumi_ghsoh 6:3c510c297e2f 18 1) Reset
soumi_ghsoh 6:3c510c297e2f 19 [0x83]
soumi_ghsoh 6:3c510c297e2f 20 2) Write Modulator and SYS_CLK Control Register (0x09) (13.56Mhz SYS_CLK and default Clock 13.56Mhz))
soumi_ghsoh 6:3c510c297e2f 21 [0x09 0x31]
soumi_ghsoh 6:3c510c297e2f 22 3) Configure Mode ISO Control Register (0x01) to 0x02 (ISO15693 high bit rate, one subcarrier, 1 out of 4)
soumi_ghsoh 6:3c510c297e2f 23 [0x01 0x02]
soumi_ghsoh 6:3c510c297e2f 24 4) Turn RF ON (Chip Status Control Register (0x00))
soumi_ghsoh 6:3c510c297e2f 25 [0x40 r] [0x00 0x20] [0x40 r]
soumi_ghsoh 6:3c510c297e2f 26 5) Inventory Command (see Figure 5-20. Inventory Command Sent From MCU to TRF7970A)
soumi_ghsoh 6:3c510c297e2f 27 5-1) Send Inventory(8B), Wait 2ms, Read/Clear IRQ Status(0x0C=>0x6C)+dummy read,
soumi_ghsoh 6:3c510c297e2f 28 Read FIFO Status Register(0x1C/0x5C), Read Continuous FIFO from 0x1F to 0x1F+0x0A(0x1F/0x7F),
soumi_ghsoh 6:3c510c297e2f 29 Read/Clear IRQ Status(0x0C=>0x6C)+dummy read, Read FIFO Status Register(0x1C/0x5C),
soumi_ghsoh 6:3c510c297e2f 30 Reset FIFO(0x0F/0x8F), Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 31 [0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00] %:2 [0x6C r:2] [0x5C r] [0x7F r:10] %:10 [0x6C r:2] [0x5C r] [0x8F] [0x4F r]
soumi_ghsoh 6:3c510c297e2f 32 ==============================================================================*/
soumi_ghsoh 6:3c510c297e2f 33
soumi_ghsoh 6:3c510c297e2f 34
soumi_ghsoh 6:3c510c297e2f 35
soumi_ghsoh 6:3c510c297e2f 36
soumi_ghsoh 6:3c510c297e2f 37
rwclough 1:1eb96189824d 38
rwclough 1:1eb96189824d 39 #include "mbed.h"
rwclough 1:1eb96189824d 40 #include "readerComm.h"
soumi_ghsoh 7:96baf1b2fd07 41
soumi_ghsoh 9:9266e0109d26 42 DigitalOut EN(p4); // Control EN pin on TRF7970
soumi_ghsoh 9:9266e0109d26 43 DigitalOut EN2(p3); // Control EN2 pin on TRF7970
soumi_ghsoh 5:93c612f43ec2 44 DigitalOut CS(p19);
soumi_ghsoh 5:93c612f43ec2 45 uint8_t turnRFOn[2];
soumi_ghsoh 5:93c612f43ec2 46 uint8_t testcommand[2];
soumi_ghsoh 7:96baf1b2fd07 47 extern uint8_t noBytes;
rwclough 2:bd5afc5aa139 48 extern SPI spi; // main.cpp
rwclough 2:bd5afc5aa139 49 extern Serial pc; // main.cpp
rwclough 2:bd5afc5aa139 50 extern uint8_t buf[300]; // main.cpp
soumi_ghsoh 7:96baf1b2fd07 51 extern uint8_t found;
rwclough 3:eaae5433ab45 52 extern DigitalOut debug1LED;
rwclough 3:eaae5433ab45 53 extern DigitalOut debug2LED;
rwclough 3:eaae5433ab45 54 extern DigitalOut ISO15693LED;
rwclough 3:eaae5433ab45 55 extern DigitalOut heartbeatLED;
rwclough 3:eaae5433ab45 56 extern DigitalOut testPin;
soumi_ghsoh 7:96baf1b2fd07 57 uint8_t temp;
soumi_ghsoh 7:96baf1b2fd07 58 uint8_t command[2];
rwclough 4:9ab0d84bbd07 59
soumi_ghsoh 10:98a58968dc7d 60 //standby
soumi_ghsoh 10:98a58968dc7d 61 //powerdown
soumi_ghsoh 10:98a58968dc7d 62 //sleep
soumi_ghsoh 10:98a58968dc7d 63 //
rwclough 4:9ab0d84bbd07 64 void trf797xDirectCommand(uint8_t *buffer)
rwclough 1:1eb96189824d 65 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 66 // trf797xDirectCommand()
rwclough 1:1eb96189824d 67 // Description: Transmit a Direct Command to the reader chip.
rwclough 1:1eb96189824d 68 // Parameter: *buffer = the direct command.
rwclough 1:1eb96189824d 69 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 70 {
rwclough 1:1eb96189824d 71 *buffer = (0x80 | *buffer); // Setup command mode
rwclough 2:bd5afc5aa139 72 *buffer = (0x9F & *buffer); // Setup command mode
rwclough 1:1eb96189824d 73 CS = SELECT;
rwclough 1:1eb96189824d 74 spi.write(*buffer);
rwclough 1:1eb96189824d 75 CS = DESELECT;
rwclough 4:9ab0d84bbd07 76 } // End of trf797xDirectCommand()
rwclough 1:1eb96189824d 77
rwclough 4:9ab0d84bbd07 78 void trf797xWriteSingle(uint8_t *buffer, uint8_t length)
rwclough 1:1eb96189824d 79 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 80 // trf797xWriteSingle()
rwclough 1:1eb96189824d 81 // Description: Writes to specified reader registers.
rwclough 1:1eb96189824d 82 // Parameters: *buffer = addresses of the registers followed by the
rwclough 2:bd5afc5aa139 83 // contents to write.
rwclough 1:1eb96189824d 84 // length = number of registers * 2.
rwclough 1:1eb96189824d 85 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 86 {
rwclough 2:bd5afc5aa139 87 uint8_t i=0;
rwclough 1:1eb96189824d 88
rwclough 1:1eb96189824d 89 CS = SELECT;
rwclough 1:1eb96189824d 90 while(length > 0) {
rwclough 2:bd5afc5aa139 91 *buffer = (0x1F & *buffer); // Register address
rwclough 1:1eb96189824d 92 for(i = 0; i < 2; i++) {
rwclough 1:1eb96189824d 93 spi.write(*buffer);
rwclough 1:1eb96189824d 94 buffer++;
rwclough 1:1eb96189824d 95 length--;
rwclough 2:bd5afc5aa139 96 }
rwclough 2:bd5afc5aa139 97 }
rwclough 1:1eb96189824d 98 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 99
rwclough 4:9ab0d84bbd07 100 } // End of trf797xWriteSingle()
rwclough 1:1eb96189824d 101
rwclough 4:9ab0d84bbd07 102 void trf797xReadSingle(uint8_t *buffer, uint8_t number)
rwclough 1:1eb96189824d 103 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 104 // trf797xReadSingle()
rwclough 1:1eb96189824d 105 // Description: Reads specified reader chip registers and
rwclough 1:1eb96189824d 106 // writes register contents to *buffer.
rwclough 1:1eb96189824d 107 // Parameters: *buffer = addresses of the registers.
rwclough 1:1eb96189824d 108 // number = number of registers.
rwclough 1:1eb96189824d 109 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 110 {
rwclough 1:1eb96189824d 111 CS = SELECT;
rwclough 1:1eb96189824d 112 while(number > 0) {
rwclough 1:1eb96189824d 113 *buffer = (0x40 | *buffer); // Address, read, single
rwclough 2:bd5afc5aa139 114 *buffer = (0x5F & *buffer); // Register address
rwclough 3:eaae5433ab45 115 spi.write(*buffer);
rwclough 2:bd5afc5aa139 116 *buffer = spi.write(0x00); // *buffer <- register contents
rwclough 1:1eb96189824d 117 buffer++;
rwclough 1:1eb96189824d 118 number--;
rwclough 2:bd5afc5aa139 119 }
rwclough 2:bd5afc5aa139 120 CS = DESELECT;
rwclough 4:9ab0d84bbd07 121 } // End of trf797xReadSingle()
rwclough 2:bd5afc5aa139 122
rwclough 4:9ab0d84bbd07 123 void trf797xReadContinuous(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 124 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 125 // trf797xReadContinuous()
rwclough 2:bd5afc5aa139 126 // Description: Used in SPI mode to read a specified number of
rwclough 2:bd5afc5aa139 127 // reader chip registers from a specified address upwards.
rwclough 2:bd5afc5aa139 128 // Contents of the registers are stored in *buffer.
rwclough 4:9ab0d84bbd07 129 // 1) Read register(s)
rwclough 4:9ab0d84bbd07 130 // 2) Write contents to *buffer
rwclough 2:bd5afc5aa139 131 // Parameters: *buffer = address of first register.
rwclough 2:bd5afc5aa139 132 // length = number of registers to read.
rwclough 2:bd5afc5aa139 133 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
soumi_ghsoh 5:93c612f43ec2 134 { //==================tested wrk $sg
rwclough 2:bd5afc5aa139 135 CS = SELECT;
rwclough 2:bd5afc5aa139 136 *buffer = (0x60 | *buffer); // Address, read, continuous
rwclough 3:eaae5433ab45 137 *buffer = (0x7F & *buffer); // Register address
rwclough 2:bd5afc5aa139 138 spi.write(*buffer);
rwclough 2:bd5afc5aa139 139 while(length > 0) {
rwclough 2:bd5afc5aa139 140 *buffer = spi.write(0x00);
rwclough 2:bd5afc5aa139 141 buffer++;
rwclough 2:bd5afc5aa139 142 length--;
rwclough 3:eaae5433ab45 143 }
rwclough 4:9ab0d84bbd07 144 // spi.write(0x00); spi.write(0x00); // 16 clock cycles, see TRF7970A FW Design Hints SLOA159 section 7.3
rwclough 1:1eb96189824d 145 CS = DESELECT;
soumi_ghsoh 5:93c612f43ec2 146
soumi_ghsoh 5:93c612f43ec2 147 //=====================tested it wrks $sg
rwclough 4:9ab0d84bbd07 148 } // End of trf797xReadContinuous()
rwclough 2:bd5afc5aa139 149
rwclough 4:9ab0d84bbd07 150 void trf797xRawWrite(uint8_t *buffer, uint8_t length)
rwclough 2:bd5afc5aa139 151 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 152 // trf797xRawWrite()
rwclough 2:bd5afc5aa139 153 // Description: Used in SPI mode to write direct to the reader chip.
rwclough 2:bd5afc5aa139 154 // Parameters: *buffer = raw data
rwclough 2:bd5afc5aa139 155 // length = number of data bytes
rwclough 2:bd5afc5aa139 156 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 157 {
rwclough 2:bd5afc5aa139 158 CS = SELECT;
rwclough 2:bd5afc5aa139 159 while(length > 0) {
rwclough 2:bd5afc5aa139 160 temp = spi.write(*buffer);
rwclough 2:bd5afc5aa139 161 buffer++;
rwclough 2:bd5afc5aa139 162 length--;
rwclough 2:bd5afc5aa139 163 }
rwclough 2:bd5afc5aa139 164 CS = DESELECT;
rwclough 4:9ab0d84bbd07 165 } // End of trf797xRawWrite()
rwclough 2:bd5afc5aa139 166
rwclough 4:9ab0d84bbd07 167 void trf797xStopDecoders(void)
rwclough 2:bd5afc5aa139 168 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 169 // trf797xStopDecoders()
rwclough 2:bd5afc5aa139 170 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 171 {
rwclough 2:bd5afc5aa139 172 command[0] = STOP_DECODERS;
rwclough 4:9ab0d84bbd07 173 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 174 }
rwclough 1:1eb96189824d 175
rwclough 4:9ab0d84bbd07 176 void trf797xRunDecoders(void)
rwclough 2:bd5afc5aa139 177 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 4:9ab0d84bbd07 178 // trf797xRunDecoders()
rwclough 2:bd5afc5aa139 179 // * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
rwclough 2:bd5afc5aa139 180 {
rwclough 2:bd5afc5aa139 181 command[0] = RUN_DECODERS;
rwclough 4:9ab0d84bbd07 182 trf797xDirectCommand(command);
rwclough 2:bd5afc5aa139 183 }
rwclough 2:bd5afc5aa139 184
soumi_ghsoh 5:93c612f43ec2 185
soumi_ghsoh 10:98a58968dc7d 186 void PowerUpNFC2(void)
soumi_ghsoh 9:9266e0109d26 187 {//CS = 1;
soumi_ghsoh 9:9266e0109d26 188 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 189 // EN = 1;
soumi_ghsoh 9:9266e0109d26 190 // EN2=1;
soumi_ghsoh 9:9266e0109d26 191
soumi_ghsoh 9:9266e0109d26 192 CS = 0; EN2 = 0; EN = 0;
soumi_ghsoh 9:9266e0109d26 193 wait_ms(2);
soumi_ghsoh 9:9266e0109d26 194 CS = 1;
soumi_ghsoh 9:9266e0109d26 195 wait_ms(3);
soumi_ghsoh 9:9266e0109d26 196 EN2 = 1;
soumi_ghsoh 9:9266e0109d26 197 wait_ms(1);
soumi_ghsoh 9:9266e0109d26 198 EN = 1;
soumi_ghsoh 9:9266e0109d26 199 }
soumi_ghsoh 10:98a58968dc7d 200 void PowerUpNFC(void)
soumi_ghsoh 9:9266e0109d26 201 {//CS = 1;
soumi_ghsoh 9:9266e0109d26 202 // wait_ms(4);
soumi_ghsoh 9:9266e0109d26 203 // EN = 1;
soumi_ghsoh 9:9266e0109d26 204 // EN2=1;
soumi_ghsoh 10:98a58968dc7d 205 //CS=1;
soumi_ghsoh 9:9266e0109d26 206 //wait_ms(1);
soumi_ghsoh 10:98a58968dc7d 207 //EN = 1;
soumi_ghsoh 10:98a58968dc7d 208 NFC_ON;
soumi_ghsoh 10:98a58968dc7d 209 //wait_ms(1);
soumi_ghsoh 10:98a58968dc7d 210 //EN2=0;
soumi_ghsoh 9:9266e0109d26 211
soumi_ghsoh 9:9266e0109d26 212 //wait_ms(1);
soumi_ghsoh 9:9266e0109d26 213 //EN2= 0;
soumi_ghsoh 6:3c510c297e2f 214 }
soumi_ghsoh 6:3c510c297e2f 215 void PowerDownNFC(void)
soumi_ghsoh 10:98a58968dc7d 216 {///CS=1;
soumi_ghsoh 10:98a58968dc7d 217 NFC_OFF;
soumi_ghsoh 9:9266e0109d26 218 //wait_ms(1);
soumi_ghsoh 10:98a58968dc7d 219 //EN2= 0; PowerDown Mode
soumi_ghsoh 10:98a58968dc7d 220 //EN2=1; SleepMode
soumi_ghsoh 10:98a58968dc7d 221 //CS=0;
soumi_ghsoh 5:93c612f43ec2 222 }
soumi_ghsoh 10:98a58968dc7d 223 void StandByNFC(void)
soumi_ghsoh 10:98a58968dc7d 224 {//NFC_ON;
soumi_ghsoh 10:98a58968dc7d 225 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 10:98a58968dc7d 226 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 5:93c612f43ec2 227
soumi_ghsoh 10:98a58968dc7d 228 turnRFOn[1] &= 0x3F;
soumi_ghsoh 10:98a58968dc7d 229 //#if NFC_STANDBY//standby
soumi_ghsoh 10:98a58968dc7d 230 //turnRFOn[1] |= 0xA0;
soumi_ghsoh 10:98a58968dc7d 231 //#elif NFC_ACTIVE//active mode
soumi_ghsoh 10:98a58968dc7d 232 turnRFOn[1] |= 0x80;
soumi_ghsoh 10:98a58968dc7d 233 //#endif
soumi_ghsoh 10:98a58968dc7d 234 trf797xWriteSingle(turnRFOn, 2);}
soumi_ghsoh 5:93c612f43ec2 235 void SpiInit1(void)
soumi_ghsoh 5:93c612f43ec2 236 {
soumi_ghsoh 5:93c612f43ec2 237 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 238 spi.frequency(250000);
soumi_ghsoh 5:93c612f43ec2 239 }
soumi_ghsoh 5:93c612f43ec2 240
soumi_ghsoh 6:3c510c297e2f 241 void SpiInit(void)
soumi_ghsoh 5:93c612f43ec2 242 {
soumi_ghsoh 5:93c612f43ec2 243 spi.format(8, 1); // 8 bit data, mode = 1 (transition on rising edge, sample on falling edge)
soumi_ghsoh 5:93c612f43ec2 244 spi.frequency(1000000);
soumi_ghsoh 5:93c612f43ec2 245 }
soumi_ghsoh 5:93c612f43ec2 246
soumi_ghsoh 5:93c612f43ec2 247 void NFCInit(void)
soumi_ghsoh 9:9266e0109d26 248 {testPin=1;
soumi_ghsoh 6:3c510c297e2f 249 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 250 testcommand[0] = SOFT_INIT;
soumi_ghsoh 5:93c612f43ec2 251 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 252 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 253 testcommand[0] = IDLE;
soumi_ghsoh 5:93c612f43ec2 254 trf797xDirectCommand(testcommand);
soumi_ghsoh 5:93c612f43ec2 255 wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 256 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 257 testcommand[1] = 0x21; // 6.78 MHz, OOK 100%
soumi_ghsoh 5:93c612f43ec2 258 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 259 //wait_ms(2);
soumi_ghsoh 5:93c612f43ec2 260 testcommand[0] = MODULATOR_CONTROL;
soumi_ghsoh 5:93c612f43ec2 261 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 262 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 263 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 264 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 265 turnRFOn[1] |= 0x20;
soumi_ghsoh 10:98a58968dc7d 266
soumi_ghsoh 6:3c510c297e2f 267 // Oroiginal code has 0x20 !!!
soumi_ghsoh 6:3c510c297e2f 268 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 6:3c510c297e2f 269 turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 270 turnRFOn[1] = CHIP_STATUS_CONTROL;
soumi_ghsoh 6:3c510c297e2f 271 turnRFOn[1] &= 0x3F;
soumi_ghsoh 6:3c510c297e2f 272 turnRFOn[1] |= 0x20;
soumi_ghsoh 6:3c510c297e2f 273 trf797xWriteSingle(turnRFOn, 2);
soumi_ghsoh 6:3c510c297e2f 274 //wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 275
soumi_ghsoh 6:3c510c297e2f 276 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 6:3c510c297e2f 277 testcommand[1] = 0x02; // 6.78 MHz, OOK 100%
soumi_ghsoh 6:3c510c297e2f 278 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 10:98a58968dc7d 279 testcommand[0] = IRQ_MASK;
soumi_ghsoh 10:98a58968dc7d 280 testcommand[1] = 0x3F;
soumi_ghsoh 10:98a58968dc7d 281 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 282 //wait_ms(6);
soumi_ghsoh 9:9266e0109d26 283 testPin=0;}
soumi_ghsoh 5:93c612f43ec2 284
soumi_ghsoh 5:93c612f43ec2 285 void RegisterReInitNFC(void)
soumi_ghsoh 5:93c612f43ec2 286 {testcommand[0] = TX_TIMER_EPC_HIGH;
soumi_ghsoh 5:93c612f43ec2 287 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 288 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 289 testcommand[0] = TX_TIMER_EPC_LOW ;
soumi_ghsoh 5:93c612f43ec2 290 testcommand[1] = 0xC1;
soumi_ghsoh 5:93c612f43ec2 291 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 292 testcommand[0] = TX_PULSE_LENGTH_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 293 testcommand[1] = 0x00;
soumi_ghsoh 5:93c612f43ec2 294 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 295 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 5:93c612f43ec2 296 testcommand[1] = 0x30;
soumi_ghsoh 5:93c612f43ec2 297 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 298 testcommand[0] = RX_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 299 testcommand[1] = 0x1F;
soumi_ghsoh 5:93c612f43ec2 300 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 301 testcommand[0] = MODULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 302 testcommand[1] = 0x21; //0x34 100%ook@13MHz
soumi_ghsoh 5:93c612f43ec2 303 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 304 testcommand[0] = RX_SPECIAL_SETTINGS ;
soumi_ghsoh 6:3c510c297e2f 305 testcommand[1] = 0x40;
soumi_ghsoh 5:93c612f43ec2 306 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 5:93c612f43ec2 307 testcommand[0] = REGULATOR_CONTROL ;
soumi_ghsoh 5:93c612f43ec2 308 testcommand[1] = 0x87;
soumi_ghsoh 5:93c612f43ec2 309 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 310 }
soumi_ghsoh 6:3c510c297e2f 311
soumi_ghsoh 6:3c510c297e2f 312
soumi_ghsoh 6:3c510c297e2f 313 void RegistersReadNFC(void)
soumi_ghsoh 10:98a58968dc7d 314 {turnRFOn[0] = CHIP_STATUS_CONTROL;
soumi_ghsoh 10:98a58968dc7d 315 trf797xReadSingle(turnRFOn, 1);
soumi_ghsoh 10:98a58968dc7d 316 testcommand[0] = ISO_CONTROL;
soumi_ghsoh 10:98a58968dc7d 317 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 318 testcommand[0] = TX_TIMER_EPC_HIGH; //0xC1;
soumi_ghsoh 6:3c510c297e2f 319 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 320 testcommand[0] = TX_TIMER_EPC_LOW ; //0xC1;
soumi_ghsoh 6:3c510c297e2f 321 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 322 testcommand[0] = TX_PULSE_LENGTH_CONTROL ; //0x00;
soumi_ghsoh 6:3c510c297e2f 323 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 324 testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ; //0x30;
soumi_ghsoh 6:3c510c297e2f 325 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 326 testcommand[0] = RX_WAIT_TIME ; //0x1F;
soumi_ghsoh 6:3c510c297e2f 327 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 328 testcommand[0] = MODULATOR_CONTROL ; //0x21;
soumi_ghsoh 6:3c510c297e2f 329 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 330 testcommand[0] = RX_SPECIAL_SETTINGS ; //0x40;
soumi_ghsoh 6:3c510c297e2f 331 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 332 testcommand[0] = REGULATOR_CONTROL ; //0x87;
soumi_ghsoh 6:3c510c297e2f 333 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 334 }
soumi_ghsoh 6:3c510c297e2f 335
soumi_ghsoh 6:3c510c297e2f 336 void InventoryReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 337 {
soumi_ghsoh 6:3c510c297e2f 338 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 339 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 340 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 341 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 342 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 343 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 344 buf[5]=0x26;
soumi_ghsoh 6:3c510c297e2f 345 buf[6]=0x01;
soumi_ghsoh 6:3c510c297e2f 346 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 347 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 6:3c510c297e2f 348 wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 349 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 350 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 351 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 352 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 353 wait_ms(5);
soumi_ghsoh 7:96baf1b2fd07 354 /*====================================read tag ID
soumi_ghsoh 6:3c510c297e2f 355 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 356 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 357 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 358 trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 359 testcommand[0] = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 6:3c510c297e2f 360 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 361 testcommand[0] = 0x7F & testcommand[0]; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 362 buf[0] = FIFO;
soumi_ghsoh 6:3c510c297e2f 363 trf797xReadContinuous(&buf[0], testcommand[0]);
soumi_ghsoh 6:3c510c297e2f 364 testcommand[0] = RSSI_LEVELS; //Read RSSI levels and oscillator status(0x0F/0x4F)
soumi_ghsoh 6:3c510c297e2f 365 trf797xReadSingle(testcommand, 1);
soumi_ghsoh 6:3c510c297e2f 366 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 367 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 368 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 369 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 370 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 371 trf797xDirectCommand(testcommand);
soumi_ghsoh 6:3c510c297e2f 372 trf797xStopDecoders();
soumi_ghsoh 7:96baf1b2fd07 373 trf797xRunDecoders(); */
soumi_ghsoh 7:96baf1b2fd07 374 //=====================================read Tag ID
soumi_ghsoh 6:3c510c297e2f 375 //wait(1);
soumi_ghsoh 7:96baf1b2fd07 376 }
soumi_ghsoh 7:96baf1b2fd07 377
soumi_ghsoh 7:96baf1b2fd07 378 void PollNFC(uint8_t *irqStatus)
soumi_ghsoh 7:96baf1b2fd07 379 {// printf
soumi_ghsoh 10:98a58968dc7d 380 if(*irqStatus==BIT6)
soumi_ghsoh 10:98a58968dc7d 381 { found=1;}
soumi_ghsoh 10:98a58968dc7d 382 //else if (*irqStatus==BIT1)
soumi_ghsoh 10:98a58968dc7d 383 // found=3;
soumi_ghsoh 10:98a58968dc7d 384 else {found=3;}
soumi_ghsoh 6:3c510c297e2f 385 }
soumi_ghsoh 7:96baf1b2fd07 386 void handlerNFC(void)
soumi_ghsoh 7:96baf1b2fd07 387 {
soumi_ghsoh 7:96baf1b2fd07 388 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 389 trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 390 PollNFC(testcommand);
soumi_ghsoh 7:96baf1b2fd07 391 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 392 trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 393 }
soumi_ghsoh 6:3c510c297e2f 394
soumi_ghsoh 7:96baf1b2fd07 395
soumi_ghsoh 7:96baf1b2fd07 396 void MemReadReqNFC(void)
soumi_ghsoh 6:3c510c297e2f 397 {testcommand[0] = RX_NO_RESPONSE_WAIT_TIME ;
soumi_ghsoh 6:3c510c297e2f 398 testcommand[1] = 0xFF;
soumi_ghsoh 6:3c510c297e2f 399 trf797xWriteSingle(testcommand, 2);
soumi_ghsoh 6:3c510c297e2f 400 //send inventory command==================================================
soumi_ghsoh 6:3c510c297e2f 401 buf[0]=0x8F; //Send Inventory(8B)[0x8F 0x91 0x3D 0x00 0x30 0x26 0x01 0x00]
soumi_ghsoh 6:3c510c297e2f 402 buf[1]=0x91;
soumi_ghsoh 6:3c510c297e2f 403 buf[2]=0x3D;
soumi_ghsoh 6:3c510c297e2f 404 buf[3]=0x00;
soumi_ghsoh 6:3c510c297e2f 405 buf[4]=0x30;
soumi_ghsoh 6:3c510c297e2f 406 buf[5]=0x02;
soumi_ghsoh 6:3c510c297e2f 407 buf[6]=0x20;
soumi_ghsoh 6:3c510c297e2f 408 buf[7]=0x00;
soumi_ghsoh 6:3c510c297e2f 409 trf797xRawWrite(&buf[0],8);
soumi_ghsoh 6:3c510c297e2f 410 wait_ms(2);
soumi_ghsoh 6:3c510c297e2f 411 testPin=1;
soumi_ghsoh 6:3c510c297e2f 412 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 413 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 414 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 415 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 416 wait_ms(5);
soumi_ghsoh 7:96baf1b2fd07 417 }
soumi_ghsoh 7:96baf1b2fd07 418 void ReadNFC(void)
soumi_ghsoh 7:96baf1b2fd07 419 {/*========================================== read irqstatus reg. of trf7970a
soumi_ghsoh 7:96baf1b2fd07 420 //testcommand[0] = IRQ_STATUS; clear irqstatus reg of trf7970a
soumi_ghsoh 7:96baf1b2fd07 421 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 422 //testcommand[0] = IRQ_STATUS;
soumi_ghsoh 7:96baf1b2fd07 423 //trf797xReadSingle(testcommand,1);
soumi_ghsoh 7:96baf1b2fd07 424 ===========================================*/
soumi_ghsoh 7:96baf1b2fd07 425
soumi_ghsoh 7:96baf1b2fd07 426 noBytes = FIFO_COUNTER; //Read FIFO Status Register(0x1C/0x5C)
soumi_ghsoh 7:96baf1b2fd07 427 trf797xReadSingle(&noBytes, 1);
soumi_ghsoh 7:96baf1b2fd07 428 noBytes = 0x7F & noBytes; // Determine the number of bytes left in FIFO
soumi_ghsoh 6:3c510c297e2f 429 buf[0] = FIFO;
soumi_ghsoh 7:96baf1b2fd07 430 trf797xReadContinuous(&buf[0],noBytes);
soumi_ghsoh 7:96baf1b2fd07 431 //testPin=0;
soumi_ghsoh 6:3c510c297e2f 432 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 433 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 434 testcommand[0] = IRQ_STATUS;
soumi_ghsoh 6:3c510c297e2f 435 trf797xReadSingle(testcommand,1);
soumi_ghsoh 6:3c510c297e2f 436 testcommand[0] = RESET; //Reset FIFO(0x0F/0x8F)
soumi_ghsoh 6:3c510c297e2f 437 trf797xDirectCommand(testcommand);
soumi_ghsoh 7:96baf1b2fd07 438
soumi_ghsoh 6:3c510c297e2f 439 //wait(1);
soumi_ghsoh 9:9266e0109d26 440 }