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mbed library sources

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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c@621:9c82b0f79f3d, 2015-09-11 (annotated)

Committer:
mbed_official
Date:
Fri Sep 11 09:30:09 2015 +0100
Revision:
621:9c82b0f79f3d
Parent:
552:a1b9575155a3 
Synchronized with git revision 6c1d63e069ab9bd86de92e8296ca783681257538



Full URL: https://github.com/mbedmicro/mbed/commit/6c1d63e069ab9bd86de92e8296ca783681257538/



ignore target files not supported by the yotta module

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 17 #include <math.h>
mbed_official 390:35c2c1cf29cd 18
mbed_official 390:35c2c1cf29cd 19 #include "spi_api.h"
mbed_official 390:35c2c1cf29cd 20 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 21 #include "pinmap.h"
mbed_official 390:35c2c1cf29cd 22 #include "mbed_error.h"
mbed_official 441:d2c15dda23c1 23 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 24
mbed_official 390:35c2c1cf29cd 25 static const PinMap PinMap_SPI_SCLK[] = {
mbed_official 390:35c2c1cf29cd 26 {P10_12, SPI_0, 4},
mbed_official 500:04797f1feae2 27 {P4_4 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 28 {P11_12, SPI_1, 2},
mbed_official 441:d2c15dda23c1 29 {P8_3 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 30 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 31 };
mbed_official 390:35c2c1cf29cd 32
mbed_official 390:35c2c1cf29cd 33 static const PinMap PinMap_SPI_SSEL[] = {
mbed_official 390:35c2c1cf29cd 34 {P10_13, SPI_0, 4},
mbed_official 500:04797f1feae2 35 {P4_5 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 36 {P11_13, SPI_1, 2},
mbed_official 441:d2c15dda23c1 37 {P8_4 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 38 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 39 };
mbed_official 390:35c2c1cf29cd 40
mbed_official 390:35c2c1cf29cd 41 static const PinMap PinMap_SPI_MOSI[] = {
mbed_official 390:35c2c1cf29cd 42 {P10_14, SPI_0, 4},
mbed_official 500:04797f1feae2 43 {P4_6 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 44 {P11_14, SPI_1, 2},
mbed_official 441:d2c15dda23c1 45 {P8_5 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 46 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 47 };
mbed_official 390:35c2c1cf29cd 48
mbed_official 390:35c2c1cf29cd 49 static const PinMap PinMap_SPI_MISO[] = {
mbed_official 390:35c2c1cf29cd 50 {P10_15, SPI_0, 4},
mbed_official 500:04797f1feae2 51 {P4_7 , SPI_1, 2},
mbed_official 390:35c2c1cf29cd 52 {P11_15, SPI_1, 2},
mbed_official 441:d2c15dda23c1 53 {P8_6 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 54 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 55 };
mbed_official 390:35c2c1cf29cd 56
mbed_official 441:d2c15dda23c1 57 static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
mbed_official 390:35c2c1cf29cd 58
mbed_official 390:35c2c1cf29cd 59 static inline void spi_disable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 60 static inline void spi_enable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 61 static inline int spi_readable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 62 static inline void spi_write(spi_t *obj, int value);
mbed_official 390:35c2c1cf29cd 63 static inline int spi_read(spi_t *obj);
mbed_official 390:35c2c1cf29cd 64
mbed_official 390:35c2c1cf29cd 65 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 390:35c2c1cf29cd 66 // determine the SPI to use
mbed_official 441:d2c15dda23c1 67 volatile uint8_t dummy;
mbed_official 441:d2c15dda23c1 68 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 441:d2c15dda23c1 69 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 441:d2c15dda23c1 70 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 441:d2c15dda23c1 71 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 441:d2c15dda23c1 72 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
mbed_official 441:d2c15dda23c1 73 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
mbed_official 441:d2c15dda23c1 74 uint32_t spi = pinmap_merge(spi_data, spi_cntl);
mbed_official 441:d2c15dda23c1 75
mbed_official 441:d2c15dda23c1 76 MBED_ASSERT((int)spi != NC);
mbed_official 441:d2c15dda23c1 77
mbed_official 441:d2c15dda23c1 78 obj->spi = (struct st_rspi *)RSPI[spi];
mbed_official 441:d2c15dda23c1 79
mbed_official 390:35c2c1cf29cd 80 // enable power and clocking
mbed_official 441:d2c15dda23c1 81 switch (spi) {
mbed_official 390:35c2c1cf29cd 82 case SPI_0: CPGSTBCR10 &= ~(0x80); break;
mbed_official 390:35c2c1cf29cd 83 case SPI_1: CPGSTBCR10 &= ~(0x40); break;
mbed_official 420:8e6e2662709e 84 case SPI_2: CPGSTBCR10 &= ~(0x20); break;
mbed_official 390:35c2c1cf29cd 85 }
mbed_official 390:35c2c1cf29cd 86 dummy = CPGSTBCR10;
mbed_official 390:35c2c1cf29cd 87
mbed_official 441:d2c15dda23c1 88 obj->spi->SPCR = 0x00; // CTRL to 0
mbed_official 441:d2c15dda23c1 89 obj->spi->SPSCR = 0x00; // no sequential operation
mbed_official 441:d2c15dda23c1 90 obj->spi->SSLP = 0x00; // SSL 'L' active
mbed_official 441:d2c15dda23c1 91 obj->spi->SPDCR = 0x20; // byte access
mbed_official 441:d2c15dda23c1 92 obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
mbed_official 441:d2c15dda23c1 93 obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
mbed_official 441:d2c15dda23c1 94 obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
mbed_official 441:d2c15dda23c1 95 obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
mbed_official 441:d2c15dda23c1 96 obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
mbed_official 441:d2c15dda23c1 97 obj->spi->SPBFCR = 0x30; // and reset buffer
mbed_official 390:35c2c1cf29cd 98
mbed_official 390:35c2c1cf29cd 99 // pin out the spi pins
mbed_official 390:35c2c1cf29cd 100 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 390:35c2c1cf29cd 101 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 390:35c2c1cf29cd 102 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 441:d2c15dda23c1 103 if ((int)ssel != NC) {
mbed_official 390:35c2c1cf29cd 104 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 390:35c2c1cf29cd 105 }
mbed_official 390:35c2c1cf29cd 106 }
mbed_official 390:35c2c1cf29cd 107
mbed_official 390:35c2c1cf29cd 108 void spi_free(spi_t *obj) {}
mbed_official 390:35c2c1cf29cd 109
mbed_official 390:35c2c1cf29cd 110 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 441:d2c15dda23c1 111 int DSS; // DSS (data select size)
mbed_official 441:d2c15dda23c1 112 int polarity = (mode & 0x2) ? 1 : 0;
mbed_official 441:d2c15dda23c1 113 int phase = (mode & 0x1) ? 1 : 0;
mbed_official 441:d2c15dda23c1 114 uint16_t tmp = 0;
mbed_official 441:d2c15dda23c1 115 uint16_t mask = 0xf03;
mbed_official 443:ed48b4122bfb 116 uint16_t wk_spcmd0;
mbed_official 441:d2c15dda23c1 117 uint8_t splw;
mbed_official 390:35c2c1cf29cd 118
mbed_official 441:d2c15dda23c1 119 switch (mode) {
mbed_official 441:d2c15dda23c1 120 case 0:
mbed_official 441:d2c15dda23c1 121 case 1:
mbed_official 441:d2c15dda23c1 122 case 2:
mbed_official 441:d2c15dda23c1 123 case 3:
mbed_official 441:d2c15dda23c1 124 // Do Nothing
mbed_official 441:d2c15dda23c1 125 break;
mbed_official 441:d2c15dda23c1 126 default:
mbed_official 441:d2c15dda23c1 127 error("SPI format error");
mbed_official 441:d2c15dda23c1 128 return;
mbed_official 441:d2c15dda23c1 129 }
mbed_official 390:35c2c1cf29cd 130
mbed_official 390:35c2c1cf29cd 131 switch (bits) {
mbed_official 390:35c2c1cf29cd 132 case 8:
mbed_official 441:d2c15dda23c1 133 DSS = 0x7;
mbed_official 441:d2c15dda23c1 134 splw = 0x20;
mbed_official 441:d2c15dda23c1 135 break;
mbed_official 390:35c2c1cf29cd 136 case 16:
mbed_official 441:d2c15dda23c1 137 DSS = 0xf;
mbed_official 441:d2c15dda23c1 138 splw = 0x40;
mbed_official 441:d2c15dda23c1 139 break;
mbed_official 390:35c2c1cf29cd 140 case 32:
mbed_official 441:d2c15dda23c1 141 DSS = 0x2;
mbed_official 441:d2c15dda23c1 142 splw = 0x60;
mbed_official 441:d2c15dda23c1 143 break;
mbed_official 390:35c2c1cf29cd 144 default:
mbed_official 390:35c2c1cf29cd 145 error("SPI module don't support other than 8/16/32bits");
mbed_official 441:d2c15dda23c1 146 return;
mbed_official 390:35c2c1cf29cd 147 }
mbed_official 441:d2c15dda23c1 148 tmp |= phase;
mbed_official 441:d2c15dda23c1 149 tmp |= (polarity << 1);
mbed_official 390:35c2c1cf29cd 150 tmp |= (DSS << 8);
mbed_official 441:d2c15dda23c1 151 obj->bits = bits;
mbed_official 390:35c2c1cf29cd 152
mbed_official 441:d2c15dda23c1 153 spi_disable(obj);
mbed_official 443:ed48b4122bfb 154 wk_spcmd0 = obj->spi->SPCMD0;
mbed_official 443:ed48b4122bfb 155 wk_spcmd0 &= ~mask;
mbed_official 443:ed48b4122bfb 156 wk_spcmd0 |= (mask & tmp);
mbed_official 443:ed48b4122bfb 157 obj->spi->SPCMD0 = wk_spcmd0;
mbed_official 441:d2c15dda23c1 158 obj->spi->SPDCR = splw;
mbed_official 390:35c2c1cf29cd 159 if (slave) {
mbed_official 441:d2c15dda23c1 160 obj->spi->SPCR &=~(1 << 3); // MSTR to 0
mbed_official 390:35c2c1cf29cd 161 } else {
mbed_official 441:d2c15dda23c1 162 obj->spi->SPCR |= (1 << 3); // MSTR to 1
mbed_official 390:35c2c1cf29cd 163 }
mbed_official 390:35c2c1cf29cd 164 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 165 }
mbed_official 390:35c2c1cf29cd 166
mbed_official 390:35c2c1cf29cd 167 void spi_frequency(spi_t *obj, int hz) {
mbed_official 441:d2c15dda23c1 168 uint32_t pclk_base;
mbed_official 441:d2c15dda23c1 169 uint32_t div;
mbed_official 441:d2c15dda23c1 170 uint32_t brdv = 0;
mbed_official 441:d2c15dda23c1 171 uint32_t hz_max;
mbed_official 441:d2c15dda23c1 172 uint32_t hz_min;
mbed_official 441:d2c15dda23c1 173 uint16_t mask = 0x000c;
mbed_official 443:ed48b4122bfb 174 uint16_t wk_spcmd0;
mbed_official 390:35c2c1cf29cd 175
mbed_official 441:d2c15dda23c1 176 /* set PCLK */
mbed_official 441:d2c15dda23c1 177 if (RZ_A1_IsClockMode0() == false) {
mbed_official 441:d2c15dda23c1 178 pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
mbed_official 390:35c2c1cf29cd 179 } else {
mbed_official 441:d2c15dda23c1 180 pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
mbed_official 441:d2c15dda23c1 181 }
mbed_official 441:d2c15dda23c1 182
mbed_official 441:d2c15dda23c1 183 hz_min = pclk_base / 2 / 256 / 8;
mbed_official 441:d2c15dda23c1 184 hz_max = pclk_base / 2;
mbed_official 441:d2c15dda23c1 185 if ((hz < hz_min) || (hz > hz_max)) {
mbed_official 390:35c2c1cf29cd 186 error("Couldn't setup requested SPI frequency");
mbed_official 390:35c2c1cf29cd 187 return;
mbed_official 390:35c2c1cf29cd 188 }
mbed_official 390:35c2c1cf29cd 189
mbed_official 441:d2c15dda23c1 190 div = (pclk_base / hz / 2);
mbed_official 441:d2c15dda23c1 191 while (div > 256) {
mbed_official 441:d2c15dda23c1 192 div >>= 1;
mbed_official 441:d2c15dda23c1 193 brdv++;
mbed_official 441:d2c15dda23c1 194 }
mbed_official 441:d2c15dda23c1 195 div -= 1;
mbed_official 441:d2c15dda23c1 196 brdv = (brdv << 2);
mbed_official 390:35c2c1cf29cd 197
mbed_official 441:d2c15dda23c1 198 spi_disable(obj);
mbed_official 441:d2c15dda23c1 199 obj->spi->SPBR = div;
mbed_official 443:ed48b4122bfb 200 wk_spcmd0 = obj->spi->SPCMD0;
mbed_official 443:ed48b4122bfb 201 wk_spcmd0 &= ~mask;
mbed_official 443:ed48b4122bfb 202 wk_spcmd0 |= (mask & brdv);
mbed_official 443:ed48b4122bfb 203 obj->spi->SPCMD0 = wk_spcmd0;
mbed_official 390:35c2c1cf29cd 204 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 205 }
mbed_official 390:35c2c1cf29cd 206
mbed_official 390:35c2c1cf29cd 207 static inline void spi_disable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 208 obj->spi->SPCR &= ~(1 << 6); // SPE to 0
mbed_official 390:35c2c1cf29cd 209 }
mbed_official 390:35c2c1cf29cd 210
mbed_official 390:35c2c1cf29cd 211 static inline void spi_enable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 212 obj->spi->SPCR |= (1 << 6); // SPE to 1
mbed_official 390:35c2c1cf29cd 213 }
mbed_official 390:35c2c1cf29cd 214
mbed_official 390:35c2c1cf29cd 215 static inline int spi_readable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 216 return obj->spi->SPSR & (1 << 7); // SPRF
mbed_official 390:35c2c1cf29cd 217 }
mbed_official 390:35c2c1cf29cd 218
mbed_official 390:35c2c1cf29cd 219 static inline int spi_tend(spi_t *obj) {
mbed_official 441:d2c15dda23c1 220 return obj->spi->SPSR & (1 << 6); // TEND
mbed_official 390:35c2c1cf29cd 221 }
mbed_official 390:35c2c1cf29cd 222
mbed_official 390:35c2c1cf29cd 223 static inline void spi_write(spi_t *obj, int value) {
mbed_official 441:d2c15dda23c1 224 if (obj->bits == 8) {
mbed_official 441:d2c15dda23c1 225 obj->spi->SPDR.UINT8[0] = (uint8_t)value;
mbed_official 441:d2c15dda23c1 226 } else if (obj->bits == 16) {
mbed_official 441:d2c15dda23c1 227 obj->spi->SPDR.UINT16[0] = (uint16_t)value;
mbed_official 441:d2c15dda23c1 228 } else {
mbed_official 441:d2c15dda23c1 229 obj->spi->SPDR.UINT32 = (uint32_t)value;
mbed_official 441:d2c15dda23c1 230 }
mbed_official 390:35c2c1cf29cd 231 }
mbed_official 390:35c2c1cf29cd 232
mbed_official 390:35c2c1cf29cd 233 static inline int spi_read(spi_t *obj) {
mbed_official 441:d2c15dda23c1 234 int read_data;
mbed_official 441:d2c15dda23c1 235
mbed_official 441:d2c15dda23c1 236 if (obj->bits == 8) {
mbed_official 441:d2c15dda23c1 237 read_data = obj->spi->SPDR.UINT8[0];
mbed_official 441:d2c15dda23c1 238 } else if (obj->bits == 16) {
mbed_official 441:d2c15dda23c1 239 read_data = obj->spi->SPDR.UINT16[0];
mbed_official 441:d2c15dda23c1 240 } else {
mbed_official 441:d2c15dda23c1 241 read_data = obj->spi->SPDR.UINT32;
mbed_official 441:d2c15dda23c1 242 }
mbed_official 441:d2c15dda23c1 243
mbed_official 441:d2c15dda23c1 244 return read_data;
mbed_official 390:35c2c1cf29cd 245 }
mbed_official 390:35c2c1cf29cd 246
mbed_official 390:35c2c1cf29cd 247 int spi_master_write(spi_t *obj, int value) {
mbed_official 390:35c2c1cf29cd 248 spi_write(obj, value);
mbed_official 390:35c2c1cf29cd 249 while(!spi_tend(obj));
mbed_official 390:35c2c1cf29cd 250 return spi_read(obj);
mbed_official 390:35c2c1cf29cd 251 }
mbed_official 390:35c2c1cf29cd 252
mbed_official 390:35c2c1cf29cd 253 int spi_slave_receive(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 254 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
mbed_official 390:35c2c1cf29cd 255 }
mbed_official 390:35c2c1cf29cd 256
mbed_official 390:35c2c1cf29cd 257 int spi_slave_read(spi_t *obj) {
mbed_official 441:d2c15dda23c1 258 return spi_read(obj);
mbed_official 390:35c2c1cf29cd 259 }
mbed_official 390:35c2c1cf29cd 260
mbed_official 390:35c2c1cf29cd 261 void spi_slave_write(spi_t *obj, int value) {
mbed_official 441:d2c15dda23c1 262 spi_write(obj, value);
mbed_official 390:35c2c1cf29cd 263 }
mbed_official 390:35c2c1cf29cd 264
mbed_official 390:35c2c1cf29cd 265 int spi_busy(spi_t *obj) {
mbed_official 441:d2c15dda23c1 266 return 0;
mbed_official 390:35c2c1cf29cd 267 }