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mbed library sources

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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c@420:8e6e2662709e, 2014-11-27 (annotated)

Committer:
mbed_official
Date:
Thu Nov 27 11:45:07 2014 +0000
Revision:
420:8e6e2662709e
Parent:
390:35c2c1cf29cd
Child:
430:d406b7919023
Synchronized with git revision 8a3087825b914b36a82ec694c2caf529295f8ad1



Full URL: https://github.com/mbedmicro/mbed/commit/8a3087825b914b36a82ec694c2caf529295f8ad1/



Targets: RZ_A1H - Fix RTOS build error (Cortex A)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 17 #include <math.h>
mbed_official 390:35c2c1cf29cd 18
mbed_official 390:35c2c1cf29cd 19 #include "spi_api.h"
mbed_official 390:35c2c1cf29cd 20 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 21 #include "pinmap.h"
mbed_official 390:35c2c1cf29cd 22 #include "mbed_error.h"
mbed_official 390:35c2c1cf29cd 23
mbed_official 390:35c2c1cf29cd 24
mbed_official 390:35c2c1cf29cd 25 #include "rspi_iodefine.h"
mbed_official 390:35c2c1cf29cd 26
mbed_official 390:35c2c1cf29cd 27 static const PinMap PinMap_SPI_SCLK[] = {
mbed_official 390:35c2c1cf29cd 28 {P10_12, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 29 {P11_12, SPI_1, 2},
mbed_official 420:8e6e2662709e 30 {P8_3, SPI_2, 3},
mbed_official 390:35c2c1cf29cd 31 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 32 };
mbed_official 390:35c2c1cf29cd 33
mbed_official 390:35c2c1cf29cd 34 static const PinMap PinMap_SPI_SSEL[] = {
mbed_official 390:35c2c1cf29cd 35 {P10_13, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 36 {P11_13, SPI_1, 2},
mbed_official 420:8e6e2662709e 37 {P8_4, SPI_2, 3},
mbed_official 390:35c2c1cf29cd 38 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 39 };
mbed_official 390:35c2c1cf29cd 40
mbed_official 390:35c2c1cf29cd 41 static const PinMap PinMap_SPI_MOSI[] = {
mbed_official 390:35c2c1cf29cd 42 {P10_14, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 43 {P11_14, SPI_1, 2},
mbed_official 420:8e6e2662709e 44 {P8_5, SPI_2, 3},
mbed_official 390:35c2c1cf29cd 45 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 46 };
mbed_official 390:35c2c1cf29cd 47
mbed_official 390:35c2c1cf29cd 48 static const PinMap PinMap_SPI_MISO[] = {
mbed_official 390:35c2c1cf29cd 49 {P10_15, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 50 {P11_15, SPI_1, 2},
mbed_official 420:8e6e2662709e 51 {P8_6, SPI_2, 3},
mbed_official 390:35c2c1cf29cd 52 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 53 };
mbed_official 390:35c2c1cf29cd 54
mbed_official 390:35c2c1cf29cd 55 struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
mbed_official 390:35c2c1cf29cd 56
mbed_official 390:35c2c1cf29cd 57 static inline void spi_disable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 58 static inline void spi_enable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 59 static inline int spi_readable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 60 static inline void spi_write(spi_t *obj, int value);
mbed_official 390:35c2c1cf29cd 61 static inline int spi_writable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 62 static inline int spi_read(spi_t *obj);
mbed_official 390:35c2c1cf29cd 63
mbed_official 390:35c2c1cf29cd 64 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 390:35c2c1cf29cd 65 // determine the SPI to use
mbed_official 390:35c2c1cf29cd 66 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 390:35c2c1cf29cd 67 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 390:35c2c1cf29cd 68 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 390:35c2c1cf29cd 69 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 390:35c2c1cf29cd 70 //SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
mbed_official 390:35c2c1cf29cd 71 //SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
mbed_official 390:35c2c1cf29cd 72 obj->spi = spi_mosi; //pinmap_merge(spi_data, spi_cntl);
mbed_official 390:35c2c1cf29cd 73 MBED_ASSERT((int)obj->spi != NC);
mbed_official 390:35c2c1cf29cd 74
mbed_official 390:35c2c1cf29cd 75 // enable power and clocking
mbed_official 390:35c2c1cf29cd 76 volatile uint8_t dummy;
mbed_official 390:35c2c1cf29cd 77 switch ((int)obj->spi) {
mbed_official 390:35c2c1cf29cd 78 case SPI_0: CPGSTBCR10 &= ~(0x80); break;
mbed_official 390:35c2c1cf29cd 79 case SPI_1: CPGSTBCR10 &= ~(0x40); break;
mbed_official 420:8e6e2662709e 80 case SPI_2: CPGSTBCR10 &= ~(0x20); break;
mbed_official 390:35c2c1cf29cd 81 }
mbed_official 390:35c2c1cf29cd 82 dummy = CPGSTBCR10;
mbed_official 390:35c2c1cf29cd 83
mbed_official 390:35c2c1cf29cd 84 RSPI[obj->spi]->SPCR = 0x00; // CTRL to 0
mbed_official 390:35c2c1cf29cd 85 RSPI[obj->spi]->SPSCR = 0x00; // no sequential operation
mbed_official 390:35c2c1cf29cd 86 RSPI[obj->spi]->SSLP = 0x00; // SSL 'L' active
mbed_official 390:35c2c1cf29cd 87 RSPI[obj->spi]->SPDCR = 0x20; // byte access
mbed_official 390:35c2c1cf29cd 88 RSPI[obj->spi]->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
mbed_official 390:35c2c1cf29cd 89 RSPI[obj->spi]->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
mbed_official 390:35c2c1cf29cd 90 RSPI[obj->spi]->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
mbed_official 390:35c2c1cf29cd 91 RSPI[obj->spi]->SPPCR = 0x20; //
mbed_official 390:35c2c1cf29cd 92
mbed_official 390:35c2c1cf29cd 93 RSPI[obj->spi]->SPBFCR= 0xf0; // and set trigger count: read 1, write 1
mbed_official 390:35c2c1cf29cd 94 RSPI[obj->spi]->SPBFCR= 0x30; // and reset buffer
mbed_official 390:35c2c1cf29cd 95
mbed_official 390:35c2c1cf29cd 96 // set default format and frequency
mbed_official 390:35c2c1cf29cd 97 if (ssel == NC) {
mbed_official 390:35c2c1cf29cd 98 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
mbed_official 390:35c2c1cf29cd 99 } else {
mbed_official 390:35c2c1cf29cd 100 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
mbed_official 390:35c2c1cf29cd 101 }
mbed_official 390:35c2c1cf29cd 102 spi_frequency(obj, 1000000);
mbed_official 390:35c2c1cf29cd 103
mbed_official 390:35c2c1cf29cd 104 // enable the ssp channel
mbed_official 390:35c2c1cf29cd 105 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 106
mbed_official 390:35c2c1cf29cd 107 // pin out the spi pins
mbed_official 390:35c2c1cf29cd 108 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 390:35c2c1cf29cd 109 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 390:35c2c1cf29cd 110 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 390:35c2c1cf29cd 111 if (ssel != NC) {
mbed_official 390:35c2c1cf29cd 112 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 390:35c2c1cf29cd 113 }
mbed_official 390:35c2c1cf29cd 114 }
mbed_official 390:35c2c1cf29cd 115
mbed_official 390:35c2c1cf29cd 116 void spi_free(spi_t *obj) {}
mbed_official 390:35c2c1cf29cd 117
mbed_official 390:35c2c1cf29cd 118 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 390:35c2c1cf29cd 119 spi_disable(obj);
mbed_official 390:35c2c1cf29cd 120 MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3));
mbed_official 390:35c2c1cf29cd 121
mbed_official 390:35c2c1cf29cd 122 int polarity = (mode & 0x2) ? 1 : 0;
mbed_official 390:35c2c1cf29cd 123 int phase = (mode & 0x1) ? 1 : 0;
mbed_official 390:35c2c1cf29cd 124 uint16_t tmp = 0, mask = 0xf03;
mbed_official 390:35c2c1cf29cd 125
mbed_official 390:35c2c1cf29cd 126 tmp |= phase;
mbed_official 390:35c2c1cf29cd 127 tmp |= polarity << 1;
mbed_official 390:35c2c1cf29cd 128
mbed_official 390:35c2c1cf29cd 129 int DSS; // DSS (data select size)
mbed_official 390:35c2c1cf29cd 130 switch (bits) {
mbed_official 390:35c2c1cf29cd 131 case 8:
mbed_official 390:35c2c1cf29cd 132 DSS = 0x7; break;
mbed_official 390:35c2c1cf29cd 133 case 16:
mbed_official 390:35c2c1cf29cd 134 DSS = 0xf; break;
mbed_official 390:35c2c1cf29cd 135 case 32:
mbed_official 390:35c2c1cf29cd 136 DSS = 0x2; break;
mbed_official 390:35c2c1cf29cd 137 default:
mbed_official 390:35c2c1cf29cd 138 error("SPI module don't support other than 8/16/32bits");
mbed_official 390:35c2c1cf29cd 139 return ;
mbed_official 390:35c2c1cf29cd 140 }
mbed_official 390:35c2c1cf29cd 141 tmp |= (DSS << 8);
mbed_official 390:35c2c1cf29cd 142
mbed_official 390:35c2c1cf29cd 143 // set it up
mbed_official 390:35c2c1cf29cd 144 RSPI[obj->spi]->SPCMD0 &= ~mask;
mbed_official 390:35c2c1cf29cd 145 RSPI[obj->spi]->SPCMD0 |= (mask & tmp);
mbed_official 390:35c2c1cf29cd 146
mbed_official 390:35c2c1cf29cd 147 if (slave) {
mbed_official 390:35c2c1cf29cd 148 RSPI[obj->spi]->SPCR &=~(1 << 3);
mbed_official 390:35c2c1cf29cd 149 } else {
mbed_official 390:35c2c1cf29cd 150 RSPI[obj->spi]->SPCR |= (1 << 3);
mbed_official 390:35c2c1cf29cd 151 }
mbed_official 390:35c2c1cf29cd 152
mbed_official 390:35c2c1cf29cd 153 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 154 }
mbed_official 390:35c2c1cf29cd 155
mbed_official 390:35c2c1cf29cd 156 void spi_frequency(spi_t *obj, int hz) {
mbed_official 390:35c2c1cf29cd 157 spi_disable(obj);
mbed_official 390:35c2c1cf29cd 158 const int P1CLK = 66666666; // 66.6666MHz
mbed_official 390:35c2c1cf29cd 159 uint8_t div, brdv;
mbed_official 390:35c2c1cf29cd 160 uint16_t mask = 0x000c0;
mbed_official 390:35c2c1cf29cd 161
mbed_official 390:35c2c1cf29cd 162 if (hz <= P1CLK/2 && hz >= P1CLK/255) {
mbed_official 390:35c2c1cf29cd 163 div = (P1CLK / hz / 2) -1;
mbed_official 390:35c2c1cf29cd 164 brdv = 0x0 << 2;
mbed_official 390:35c2c1cf29cd 165 } else if (hz >= P1CLK/255/2) {
mbed_official 390:35c2c1cf29cd 166 div = (P1CLK / hz / 2 /2) -1;
mbed_official 390:35c2c1cf29cd 167 brdv = 0x1 << 2;
mbed_official 390:35c2c1cf29cd 168 } else if (hz >= P1CLK/255/4) {
mbed_official 390:35c2c1cf29cd 169 div = (P1CLK / hz / 2 /4) -1;
mbed_official 390:35c2c1cf29cd 170 brdv = 0x2 << 2;
mbed_official 390:35c2c1cf29cd 171 } else if (hz >= P1CLK/255/8) {
mbed_official 390:35c2c1cf29cd 172 div = (P1CLK / hz / 2 /8) -1;
mbed_official 390:35c2c1cf29cd 173 brdv = 0x3 << 2;
mbed_official 390:35c2c1cf29cd 174 } else {
mbed_official 390:35c2c1cf29cd 175 error("Couldn't setup requested SPI frequency");
mbed_official 390:35c2c1cf29cd 176 return;
mbed_official 390:35c2c1cf29cd 177 }
mbed_official 390:35c2c1cf29cd 178
mbed_official 390:35c2c1cf29cd 179 RSPI[obj->spi]->SPBR = div;
mbed_official 390:35c2c1cf29cd 180
mbed_official 390:35c2c1cf29cd 181 RSPI[obj->spi]->SPCMD0 &= ~mask;
mbed_official 390:35c2c1cf29cd 182 RSPI[obj->spi]->SPCMD0 |= (mask & brdv);
mbed_official 390:35c2c1cf29cd 183
mbed_official 390:35c2c1cf29cd 184
mbed_official 390:35c2c1cf29cd 185 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 186 }
mbed_official 390:35c2c1cf29cd 187
mbed_official 390:35c2c1cf29cd 188 static inline void spi_disable(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 189 RSPI[obj->spi]->SPCR &= ~(1 << 6); // SPE to 0
mbed_official 390:35c2c1cf29cd 190 }
mbed_official 390:35c2c1cf29cd 191
mbed_official 390:35c2c1cf29cd 192 static inline void spi_enable(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 193 RSPI[obj->spi]->SPCR |= (1 << 6); // SPE to 1
mbed_official 390:35c2c1cf29cd 194 }
mbed_official 390:35c2c1cf29cd 195
mbed_official 390:35c2c1cf29cd 196 static inline int spi_readable(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 197 return RSPI[obj->spi]->SPSR & (1 << 7);
mbed_official 390:35c2c1cf29cd 198 }
mbed_official 390:35c2c1cf29cd 199
mbed_official 390:35c2c1cf29cd 200 static inline int spi_tend(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 201 return RSPI[obj->spi]->SPSR & (1 << 6);
mbed_official 390:35c2c1cf29cd 202 }
mbed_official 390:35c2c1cf29cd 203
mbed_official 390:35c2c1cf29cd 204 static inline int spi_writable(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 205 return RSPI[obj->spi]->SPSR & (1 << 5);
mbed_official 390:35c2c1cf29cd 206 }
mbed_official 390:35c2c1cf29cd 207
mbed_official 390:35c2c1cf29cd 208 static inline void spi_write(spi_t *obj, int value) {
mbed_official 390:35c2c1cf29cd 209 while (!spi_writable(obj));
mbed_official 390:35c2c1cf29cd 210 RSPI[obj->spi]->SPDR.UINT8[0] = value;
mbed_official 390:35c2c1cf29cd 211 }
mbed_official 390:35c2c1cf29cd 212
mbed_official 390:35c2c1cf29cd 213 static inline int spi_read(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 214 //while (!spi_readable(obj));
mbed_official 390:35c2c1cf29cd 215 return RSPI[obj->spi]->SPDR.UINT8[0];
mbed_official 390:35c2c1cf29cd 216 }
mbed_official 390:35c2c1cf29cd 217
mbed_official 390:35c2c1cf29cd 218 int spi_master_write(spi_t *obj, int value) {
mbed_official 390:35c2c1cf29cd 219 spi_write(obj, value);
mbed_official 390:35c2c1cf29cd 220 while(!spi_tend(obj));
mbed_official 390:35c2c1cf29cd 221 return spi_read(obj);
mbed_official 390:35c2c1cf29cd 222 }
mbed_official 390:35c2c1cf29cd 223
mbed_official 390:35c2c1cf29cd 224 int spi_slave_receive(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 225 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
mbed_official 390:35c2c1cf29cd 226 }
mbed_official 390:35c2c1cf29cd 227
mbed_official 390:35c2c1cf29cd 228 int spi_slave_read(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 229 return RSPI[obj->spi]->SPDR.UINT8[0];
mbed_official 390:35c2c1cf29cd 230 }
mbed_official 390:35c2c1cf29cd 231
mbed_official 390:35c2c1cf29cd 232 void spi_slave_write(spi_t *obj, int value) {
mbed_official 390:35c2c1cf29cd 233 while (spi_writable(obj) == 0) ;
mbed_official 390:35c2c1cf29cd 234 RSPI[obj->spi]->SPDR.UINT8[0] = value;
mbed_official 390:35c2c1cf29cd 235 }
mbed_official 390:35c2c1cf29cd 236
mbed_official 390:35c2c1cf29cd 237 int spi_busy(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 238 return (RSPI[obj->spi]->SPSR & (1 << 6)) ? (0) : (1);
mbed_official 390:35c2c1cf29cd 239 }