Kenji Arai / Nucleo_rtos_sample

This is sample program for Nucleo L152RE (and F401RE & F411RE) mbed-rtos. You need to modify mbed-src and mbed-rtos before compile it.

Dependencies:   mbed-rtos mbed-src SetRTC

Fork of GR-PEACH_test_on_rtos_works_well by Kenji Arai

Please refer below link.
/users/kenjiArai/notebook/necleo-l152re-rtos-sample-also-for-f401re--f411re-/

Files at this revision

API Documentation at this revision

Revision 13:d0d1da1fae4c, committed 2015-05-20

Comitter:
kenjiArai
Date:
Wed May 20 10:49:02 2015 +0000
Parent:
12:2db841307633
Commit message:
change L152 System clock (PLL VCO=96MHz) ->32MHz Clock

Changed in this revision

main.cpp Show annotated file Show diff for this revision Revisions of this file
mbed-src.lib Show annotated file Show diff for this revision Revisions of this file
modification_notice.h Show annotated file Show diff for this revision Revisions of this file 
diff -r 2db841307633 -r d0d1da1fae4c main.cpp
--- a/main.cpp	Tue May 19 23:32:57 2015 +0000
+++ b/main.cpp	Wed May 20 10:49:02 2015 +0000
@@ -6,7 +6,7 @@
  *  http://www.page.sannet.ne.jp/kenjia/index.html
  *  http://mbed.org/users/kenjiArai/
  *      Created: November  29th, 2014
- *      Revised: May       16th, 2015
+ *      Revised: May       20th, 2015
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
@@ -46,16 +46,6 @@
 #define READABLE(x)     {;}
 #endif
 
-#if 0
-#define TIMEBASE        12000
-#define FIXED_STEPS     100
-
-#define PI              3.1415926536
-#define RAD_TO_DEG      57.29578
-#define TIME_BASE_MS    ( TIME_BASE_S * 1000)
-#define RATE            0.1
-#endif
-
 #define TIME_BASE_S     0.02
 
 #define step_one        (0.0625f)

diff -r 2db841307633 -r d0d1da1fae4c mbed-src.lib
--- a/mbed-src.lib	Tue May 19 23:32:57 2015 +0000
+++ b/mbed-src.lib	Wed May 20 10:49:02 2015 +0000
@@ -1,1 +1,1 @@
-http://mbed.org/users/mbed_official/code/mbed-src/#6693aa6d3ba3
+http://mbed.org/users/mbed_official/code/mbed-src/#9dba91c44009

diff -r 2db841307633 -r d0d1da1fae4c modification_notice.h
--- a/modification_notice.h	Tue May 19 23:32:57 2015 +0000
+++ b/modification_notice.h	Wed May 20 10:49:02 2015 +0000
@@ -6,7 +6,7 @@
  *  http://www.page.sannet.ne.jp/kenjia/index.html
  *  http://mbed.org/users/kenjiArai/
  *      Created: May       14th, 2015
- *      Revised: May       16th, 2015, 11:05 a.m.(JST)
+ *      Revised: May       20th, 2015
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
  * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
@@ -89,6 +89,16 @@
 
 Currently L152RE has two type of operation, 24MHz and 32MHz.
 
+-> Need to set below
+Case: Use HSE 8MHz                      -> PLLMUL x 12
+Case: Use HSI(internal RC clock) 16MHz  -> PLLMUL x 6
+
+PLL VCO Frequency = 96MHz (8MHz x12 or 16MHz x 6)
+PLLDIV /3
+System Clock = 96/3 = 32MHz
+USB Clock = 96/2(2 is fixed divider) = 48MHz
+
+
 (2) CAUTION!! for Nucleo F411RE mbed
 F411 med has been changed System clock = 96 MHz (former setting 100 MHz).
 Please modify #ifndef OS_CLOCK related part.
@@ -183,26 +193,93 @@
 //-------------------------------------------------------------------------------------------------
 //  (2) /mbed-src/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c
 //-------------------------------------------------------------------------------------------------
+// Comment line
+// Modify (from line 24)
+// Copy & Paste from next line
+#if 0
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 24                     | 32
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+#else
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
+  *                                    | (external 8 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL        |
+  *                                    | (external 8 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | ?(48MHz but?)
+  *-----------------------------------------------------------------------------
+#endif
+
 // inside SetSysClock_PLL_HSE() function (line 483)
 // Modify (from line 511)
 // Copy & Paste from next line
-#if 0
+#if 0   // Updated on May 20th, 2014
+ #if 0   // Do NOT use!
   // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
   // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
   RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-#else
+ #else   // Do NOT use!
   // SYSCLK = 32 MHz ((8 MHz * 8) / 2)
   // USBCLK = 48 MHz (8 MHz * 8) --> USB NG
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
   RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL8;
   RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+ #endif
+#else   // following is best ?
+  // SYSCLK = 32 MHz ((8 MHz * 12) / 3 )
+  // USBCLK = 48 MHz ((8 MHz * 12) / 2 ) --> USB OK
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12;
+  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
 #endif
 // to above line
 
+// inside SetSysClock_PLL_HSI() function (line 546)
+// Modify (from line 561)
+// Copy & Paste from next line
+#if 0
+  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
+  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
+  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+#else   // following is best ?
+  // SYSCLK = 32 MHz ((16 MHz * 6) / 3)
+  // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> 48MHz but nobody know accuracy
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
+  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
+#endif
+// to above line
 //-------------------------------------------------------------------------------------------------
 //  (3) /mbed-src/targets/hal/TARGET_STM/TARGET_STM/TARGET_STM32F4/rtc_api.c
 //-------------------------------------------------------------------------------------------------