Kenji Arai / Nucleo_rtos_sample

This is sample program for Nucleo L152RE (and F401RE & F411RE) mbed-rtos. You need to modify mbed-src and mbed-rtos before compile it.

Dependencies:   mbed-rtos mbed-src SetRTC

Fork of GR-PEACH_test_on_rtos_works_well by Kenji Arai

Please refer below link.
/users/kenjiArai/notebook/necleo-l152re-rtos-sample-also-for-f401re--f411re-/

modification_notice.h@13:d0d1da1fae4c, 2015-05-20 (annotated)

Committer:
kenjiArai
Date:
Wed May 20 10:49:02 2015 +0000
Revision:
13:d0d1da1fae4c
Parent:
12:2db841307633 
change L152 System clock (PLL VCO=96MHz) ->32MHz Clock

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 10:1c0f58b9c048 1 /*
kenjiArai 10:1c0f58b9c048 2 * mbed Application program for the mbed
kenjiArai 10:1c0f58b9c048 3 * Library differ part (This is only information document)
kenjiArai 10:1c0f58b9c048 4 *
kenjiArai 10:1c0f58b9c048 5 * Copyright (c) 2014,'15 Kenji Arai / JH1PJL
kenjiArai 10:1c0f58b9c048 6 * http://www.page.sannet.ne.jp/kenjia/index.html
kenjiArai 10:1c0f58b9c048 7 * http://mbed.org/users/kenjiArai/
kenjiArai 10:1c0f58b9c048 8 * Created: May 14th, 2015
kenjiArai 13:d0d1da1fae4c 9 * Revised: May 20th, 2015
kenjiArai 10:1c0f58b9c048 10 *
kenjiArai 10:1c0f58b9c048 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
kenjiArai 10:1c0f58b9c048 12 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
kenjiArai 10:1c0f58b9c048 13 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
kenjiArai 10:1c0f58b9c048 14 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
kenjiArai 10:1c0f58b9c048 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
kenjiArai 10:1c0f58b9c048 16 */
kenjiArai 10:1c0f58b9c048 17
kenjiArai 10:1c0f58b9c048 18 #if 0 ///////////////////////////////////////////////////////////////////////////////////////////
kenjiArai 10:1c0f58b9c048 19
kenjiArai 10:1c0f58b9c048 20 //-------------------------------------------------------------------------------------------------
kenjiArai 10:1c0f58b9c048 21 // ----- Hardware configuration ---------------
kenjiArai 10:1c0f58b9c048 22 //-------------------------------------------------------------------------------------------------
kenjiArai 10:1c0f58b9c048 23
kenjiArai 10:1c0f58b9c048 24 // Direct connection between below two pins.
kenjiArai 10:1c0f58b9c048 25 // DAC0 output connected to ADC1 input
kenjiArai 10:1c0f58b9c048 26 PA_4 : PA_1
kenjiArai 10:1c0f58b9c048 27 // DAC1 to ADC3
kenjiArai 10:1c0f58b9c048 28 PA_5 : PB_0
kenjiArai 10:1c0f58b9c048 29 // I2C1 master connected to I2C2 slave
kenjiArai 10:1c0f58b9c048 30 PB_8 : PB_10 // Need 3.3Kohm pull-up
kenjiArai 10:1c0f58b9c048 31 PB_9 : PB_11 // Need 3.3Kohm pull-up
kenjiArai 10:1c0f58b9c048 32 // Connecetd with CR network
kenjiArai 10:1c0f58b9c048 33 // LED's connected each pin with R=330Ohm to GND
kenjiArai 10:1c0f58b9c048 34 PC_2
kenjiArai 10:1c0f58b9c048 35 PC_3
kenjiArai 10:1c0f58b9c048 36 PC_10
kenjiArai 10:1c0f58b9c048 37 PC_11
kenjiArai 10:1c0f58b9c048 38 PC_12
kenjiArai 10:1c0f58b9c048 39
kenjiArai 10:1c0f58b9c048 40 //-------------------------------------------------------------------------------------------------
kenjiArai 10:1c0f58b9c048 41 // ----- Software Modification ---------------
kenjiArai 10:1c0f58b9c048 42 //-------------------------------------------------------------------------------------------------
kenjiArai 10:1c0f58b9c048 43 // SUMMARY information
kenjiArai 10:1c0f58b9c048 44 // Nucleo_rtos_sample
kenjiArai 10:1c0f58b9c048 45 + debug_tools_L152_F4x1RE <- Created as new lib.
kenjiArai 10:1c0f58b9c048 46 + SetRTC <- Lib. updated by myself
kenjiArai 10:1c0f58b9c048 47 // + files
kenjiArai 11:587b8f1bab9d 48 + mbed-rtos <- Rev.77 (checked on May 16, 2015)
kenjiArai 10:1c0f58b9c048 49 // + rtos
kenjiArai 10:1c0f58b9c048 50 // + rtx
kenjiArai 10:1c0f58b9c048 51 // + TARGET_CORTEX_M
kenjiArai 11:587b8f1bab9d 52 + RTX_Conf_CM.c <- (1) Need to modify before compile by yourself
kenjiArai 10:1c0f58b9c048 53 // + DIRs & Files
kenjiArai 10:1c0f58b9c048 54 // + DIRs & Files + DIRs & Files
kenjiArai 10:1c0f58b9c048 55 + mbe-src <- Rev.541 (checked on May 16, 2015)
kenjiArai 10:1c0f58b9c048 56 // + targets
kenjiArai 10:1c0f58b9c048 57 // + cmsis
kenjiArai 10:1c0f58b9c048 58 // + TARGET_STM
kenjiArai 10:1c0f58b9c048 59 // + TARGET_STM32L1
kenjiArai 10:1c0f58b9c048 60 // + TARGET_NUCLEO_L152RE
kenjiArai 10:1c0f58b9c048 61 // + system_stm32l1xx.c
kenjiArai 11:587b8f1bab9d 62 <- (2) Need to modify before compile by yourself
kenjiArai 10:1c0f58b9c048 63 // + DIRs & Files
kenjiArai 10:1c0f58b9c048 64 // + hal
kenjiArai 10:1c0f58b9c048 65 // + TARGET_STM
kenjiArai 10:1c0f58b9c048 66 // + TARGET_STM32F4
kenjiArai 10:1c0f58b9c048 67 // + rtc_api.c
kenjiArai 11:587b8f1bab9d 68 <- (3) Need to modify before compile by yourself
kenjiArai 10:1c0f58b9c048 69 // + DIRs & Files
kenjiArai 10:1c0f58b9c048 70 // + TARGET_NUCLEO_L152RE
kenjiArai 10:1c0f58b9c048 71 // + rtc_api.c
kenjiArai 11:587b8f1bab9d 72 <- (4) Need to modify before compile by yourself
kenjiArai 10:1c0f58b9c048 73 // + DIRs & Files
kenjiArai 10:1c0f58b9c048 74 // + DIR & Files + DIRs & Files + DIRs & Files
kenjiArai 10:1c0f58b9c048 75
kenjiArai 10:1c0f58b9c048 76 (1) CAUTION!! for Nucleo L152RE mbed
kenjiArai 10:1c0f58b9c048 77 L152 mbed has following setting both mbed lib. and mbed-src lib.
kenjiArai 10:1c0f58b9c048 78 System Clock = 24 MHz (started as 32 MHz but due to USB clock creation, changed to 24 MHz)
kenjiArai 11:587b8f1bab9d 79 If you would like to use 24 MHz, do NOT modify (1) and (2).
kenjiArai 10:1c0f58b9c048 80
kenjiArai 12:2db841307633 81 As of May 20th, 2015
kenjiArai 12:2db841307633 82 Followings are investigation result.
kenjiArai 12:2db841307633 83 Case L152 (C-01 old ver with internal RC clock)
kenjiArai 12:2db841307633 84 before and rev.81 20140319 -> 16000000Hz
kenjiArai 12:2db841307633 85 rev.82 and after 20140407 -> 32000000Hz
kenjiArai 12:2db841307633 86 Case L152 (C-02 new ver)
kenjiArai 12:2db841307633 87 before and rev.81 20140319 -> 16000000Hz
kenjiArai 12:2db841307633 88 rev.82 and after 20140407 -> 24000000Hz
kenjiArai 12:2db841307633 89
kenjiArai 12:2db841307633 90 Currently L152RE has two type of operation, 24MHz and 32MHz.
kenjiArai 12:2db841307633 91
kenjiArai 13:d0d1da1fae4c 92 -> Need to set below
kenjiArai 13:d0d1da1fae4c 93 Case: Use HSE 8MHz -> PLLMUL x 12
kenjiArai 13:d0d1da1fae4c 94 Case: Use HSI(internal RC clock) 16MHz -> PLLMUL x 6
kenjiArai 13:d0d1da1fae4c 95
kenjiArai 13:d0d1da1fae4c 96 PLL VCO Frequency = 96MHz (8MHz x12 or 16MHz x 6)
kenjiArai 13:d0d1da1fae4c 97 PLLDIV /3
kenjiArai 13:d0d1da1fae4c 98 System Clock = 96/3 = 32MHz
kenjiArai 13:d0d1da1fae4c 99 USB Clock = 96/2(2 is fixed divider) = 48MHz
kenjiArai 13:d0d1da1fae4c 100
kenjiArai 13:d0d1da1fae4c 101
kenjiArai 10:1c0f58b9c048 102 (2) CAUTION!! for Nucleo F411RE mbed
kenjiArai 10:1c0f58b9c048 103 F411 med has been changed System clock = 96 MHz (former setting 100 MHz).
kenjiArai 10:1c0f58b9c048 104 Please modify #ifndef OS_CLOCK related part.
kenjiArai 10:1c0f58b9c048 105
kenjiArai 10:1c0f58b9c048 106 //-------------------------------------------------------------------------------------------------
kenjiArai 11:587b8f1bab9d 107 // (1) /mbed-rtos/mbed-rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
kenjiArai 10:1c0f58b9c048 108 //-------------------------------------------------------------------------------------------------
kenjiArai 10:1c0f58b9c048 109 // Insert & Modifiy (from line 118)
kenjiArai 10:1c0f58b9c048 110 /*
kenjiArai 10:1c0f58b9c048 111 // Insert (below 2 lines)
kenjiArai 10:1c0f58b9c048 112 #elif defined(TARGET_STM32L152RE)
kenjiArai 10:1c0f58b9c048 113 //# define OS_CLOCK 24000000
kenjiArai 10:1c0f58b9c048 114 # define OS_CLOCK 32000000
kenjiArai 10:1c0f58b9c048 115 // Modify (100MHz to 96MHz)
kenjiArai 10:1c0f58b9c048 116 # elif defined(TARGET_STM32F411RE)
kenjiArai 10:1c0f58b9c048 117 # define OS_CLOCK 96000000
kenjiArai 10:1c0f58b9c048 118 */
kenjiArai 10:1c0f58b9c048 119 // Copy & Paste from next line
kenjiArai 10:1c0f58b9c048 120 #ifndef OS_CLOCK
kenjiArai 10:1c0f58b9c048 121 # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
kenjiArai 10:1c0f58b9c048 122 # define OS_CLOCK 96000000
kenjiArai 10:1c0f58b9c048 123
kenjiArai 10:1c0f58b9c048 124 # elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32F303RE)
kenjiArai 10:1c0f58b9c048 125 # define OS_CLOCK 72000000
kenjiArai 10:1c0f58b9c048 126
kenjiArai 10:1c0f58b9c048 127 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) \
kenjiArai 10:1c0f58b9c048 128 || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC)
kenjiArai 10:1c0f58b9c048 129 # define OS_CLOCK 48000000
kenjiArai 10:1c0f58b9c048 130
kenjiArai 10:1c0f58b9c048 131 # elif defined(TARGET_LPC812)
kenjiArai 10:1c0f58b9c048 132 # define OS_CLOCK 36000000
kenjiArai 10:1c0f58b9c048 133
kenjiArai 10:1c0f58b9c048 134 # elif defined(TARGET_LPC824)
kenjiArai 10:1c0f58b9c048 135 # define OS_CLOCK 30000000
kenjiArai 10:1c0f58b9c048 136
kenjiArai 10:1c0f58b9c048 137 # elif defined(TARGET_STM32F100RB)
kenjiArai 10:1c0f58b9c048 138 # define OS_CLOCK 24000000
kenjiArai 10:1c0f58b9c048 139
kenjiArai 10:1c0f58b9c048 140 # elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_K64F) || defined(TARGET_K22F)
kenjiArai 10:1c0f58b9c048 141 # define OS_CLOCK 120000000
kenjiArai 10:1c0f58b9c048 142
kenjiArai 10:1c0f58b9c048 143 # elif defined(TARGET_LPC4330)
kenjiArai 10:1c0f58b9c048 144 # define OS_CLOCK 204000000
kenjiArai 10:1c0f58b9c048 145
kenjiArai 10:1c0f58b9c048 146 # elif defined(TARGET_LPC4337)
kenjiArai 10:1c0f58b9c048 147 # define OS_CLOCK 204000000
kenjiArai 10:1c0f58b9c048 148
kenjiArai 10:1c0f58b9c048 149 # elif defined(TARGET_STM32F407) || defined(TARGET_F407VG)
kenjiArai 10:1c0f58b9c048 150 # define OS_CLOCK 168000000
kenjiArai 10:1c0f58b9c048 151
kenjiArai 10:1c0f58b9c048 152 # elif defined(TARGET_STM32F401RE)
kenjiArai 10:1c0f58b9c048 153 # define OS_CLOCK 84000000
kenjiArai 10:1c0f58b9c048 154
kenjiArai 10:1c0f58b9c048 155 # elif defined(TARGET_STM32F411RE)
kenjiArai 10:1c0f58b9c048 156 # define OS_CLOCK 96000000
kenjiArai 10:1c0f58b9c048 157
kenjiArai 10:1c0f58b9c048 158 #elif defined(TARGET_STM32F103RB)
kenjiArai 10:1c0f58b9c048 159 # define OS_CLOCK 72000000
kenjiArai 10:1c0f58b9c048 160
kenjiArai 10:1c0f58b9c048 161 #elif defined(TARGET_STM32F429ZI)
kenjiArai 10:1c0f58b9c048 162 # define OS_CLOCK 168000000
kenjiArai 10:1c0f58b9c048 163
kenjiArai 10:1c0f58b9c048 164 #elif defined(TARGET_STM32F302R8)
kenjiArai 10:1c0f58b9c048 165 # define OS_CLOCK 64000000
kenjiArai 10:1c0f58b9c048 166
kenjiArai 10:1c0f58b9c048 167 #elif defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8)
kenjiArai 10:1c0f58b9c048 168 # define OS_CLOCK 32000000
kenjiArai 10:1c0f58b9c048 169
kenjiArai 10:1c0f58b9c048 170 #elif defined(TARGET_STM32F401VC)
kenjiArai 10:1c0f58b9c048 171 # define OS_CLOCK 84000000
kenjiArai 10:1c0f58b9c048 172
kenjiArai 10:1c0f58b9c048 173 #elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600)
kenjiArai 10:1c0f58b9c048 174 # define OS_CLOCK 24000000
kenjiArai 10:1c0f58b9c048 175
kenjiArai 10:1c0f58b9c048 176 #elif defined(TARGET_STM32L152RE)
kenjiArai 10:1c0f58b9c048 177 //# define OS_CLOCK 24000000
kenjiArai 10:1c0f58b9c048 178 # define OS_CLOCK 32000000
kenjiArai 10:1c0f58b9c048 179
kenjiArai 10:1c0f58b9c048 180 # else
kenjiArai 10:1c0f58b9c048 181 # error "no target defined"
kenjiArai 10:1c0f58b9c048 182 # endif
kenjiArai 10:1c0f58b9c048 183 #endif
kenjiArai 10:1c0f58b9c048 184
kenjiArai 10:1c0f58b9c048 185 // <o>Timer tick value [us] <1-1000000>
kenjiArai 10:1c0f58b9c048 186 // <i> Defines the timer tick value.
kenjiArai 10:1c0f58b9c048 187 // <i> Default: 1000 (1ms)
kenjiArai 10:1c0f58b9c048 188 #ifndef OS_TICK
kenjiArai 10:1c0f58b9c048 189 #define OS_TICK 1000
kenjiArai 10:1c0f58b9c048 190 #endif
kenjiArai 10:1c0f58b9c048 191 // to above line
kenjiArai 10:1c0f58b9c048 192
kenjiArai 10:1c0f58b9c048 193 //-------------------------------------------------------------------------------------------------
kenjiArai 11:587b8f1bab9d 194 // (2) /mbed-src/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c
kenjiArai 10:1c0f58b9c048 195 //-------------------------------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 196 // Comment line
kenjiArai 13:d0d1da1fae4c 197 // Modify (from line 24)
kenjiArai 13:d0d1da1fae4c 198 // Copy & Paste from next line
kenjiArai 13:d0d1da1fae4c 199 #if 0
kenjiArai 13:d0d1da1fae4c 200 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 201 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
kenjiArai 13:d0d1da1fae4c 202 * | (external 8 MHz clock) | (internal 16 MHz)
kenjiArai 13:d0d1da1fae4c 203 * | 2- PLL_HSE_XTAL |
kenjiArai 13:d0d1da1fae4c 204 * | (external 8 MHz xtal) |
kenjiArai 13:d0d1da1fae4c 205 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 206 * SYSCLK(MHz) | 24 | 32
kenjiArai 13:d0d1da1fae4c 207 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 208 * AHBCLK (MHz) | 24 | 32
kenjiArai 13:d0d1da1fae4c 209 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 210 * APB1CLK (MHz) | 24 | 32
kenjiArai 13:d0d1da1fae4c 211 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 212 * APB2CLK (MHz) | 24 | 32
kenjiArai 13:d0d1da1fae4c 213 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 214 * USB capable (48 MHz precise clock) | YES | NO
kenjiArai 13:d0d1da1fae4c 215 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 216 #else
kenjiArai 13:d0d1da1fae4c 217 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 218 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
kenjiArai 13:d0d1da1fae4c 219 * | (external 8 MHz clock) | (internal 16 MHz)
kenjiArai 13:d0d1da1fae4c 220 * | 2- PLL_HSE_XTAL |
kenjiArai 13:d0d1da1fae4c 221 * | (external 8 MHz xtal) |
kenjiArai 13:d0d1da1fae4c 222 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 223 * SYSCLK(MHz) | 32 | 32
kenjiArai 13:d0d1da1fae4c 224 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 225 * AHBCLK (MHz) | 32 | 32
kenjiArai 13:d0d1da1fae4c 226 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 227 * APB1CLK (MHz) | 32 | 32
kenjiArai 13:d0d1da1fae4c 228 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 229 * APB2CLK (MHz) | 32 | 32
kenjiArai 13:d0d1da1fae4c 230 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 231 * USB capable (48 MHz precise clock) | YES | ?(48MHz but?)
kenjiArai 13:d0d1da1fae4c 232 *-----------------------------------------------------------------------------
kenjiArai 13:d0d1da1fae4c 233 #endif
kenjiArai 13:d0d1da1fae4c 234
kenjiArai 10:1c0f58b9c048 235 // inside SetSysClock_PLL_HSE() function (line 483)
kenjiArai 10:1c0f58b9c048 236 // Modify (from line 511)
kenjiArai 10:1c0f58b9c048 237 // Copy & Paste from next line
kenjiArai 13:d0d1da1fae4c 238 #if 0 // Updated on May 20th, 2014
kenjiArai 13:d0d1da1fae4c 239 #if 0 // Do NOT use!
kenjiArai 10:1c0f58b9c048 240 // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
kenjiArai 10:1c0f58b9c048 241 // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
kenjiArai 10:1c0f58b9c048 242 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
kenjiArai 10:1c0f58b9c048 243 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
kenjiArai 10:1c0f58b9c048 244 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
kenjiArai 10:1c0f58b9c048 245 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
kenjiArai 13:d0d1da1fae4c 246 #else // Do NOT use!
kenjiArai 10:1c0f58b9c048 247 // SYSCLK = 32 MHz ((8 MHz * 8) / 2)
kenjiArai 10:1c0f58b9c048 248 // USBCLK = 48 MHz (8 MHz * 8) --> USB NG
kenjiArai 10:1c0f58b9c048 249 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
kenjiArai 10:1c0f58b9c048 250 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
kenjiArai 10:1c0f58b9c048 251 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL8;
kenjiArai 10:1c0f58b9c048 252 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
kenjiArai 13:d0d1da1fae4c 253 #endif
kenjiArai 13:d0d1da1fae4c 254 #else // following is best ?
kenjiArai 13:d0d1da1fae4c 255 // SYSCLK = 32 MHz ((8 MHz * 12) / 3 )
kenjiArai 13:d0d1da1fae4c 256 // USBCLK = 48 MHz ((8 MHz * 12) / 2 ) --> USB OK
kenjiArai 13:d0d1da1fae4c 257 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
kenjiArai 13:d0d1da1fae4c 258 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
kenjiArai 13:d0d1da1fae4c 259 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
kenjiArai 13:d0d1da1fae4c 260 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
kenjiArai 10:1c0f58b9c048 261 #endif
kenjiArai 10:1c0f58b9c048 262 // to above line
kenjiArai 10:1c0f58b9c048 263
kenjiArai 13:d0d1da1fae4c 264 // inside SetSysClock_PLL_HSI() function (line 546)
kenjiArai 13:d0d1da1fae4c 265 // Modify (from line 561)
kenjiArai 13:d0d1da1fae4c 266 // Copy & Paste from next line
kenjiArai 13:d0d1da1fae4c 267 #if 0
kenjiArai 13:d0d1da1fae4c 268 // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
kenjiArai 13:d0d1da1fae4c 269 // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
kenjiArai 13:d0d1da1fae4c 270 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
kenjiArai 13:d0d1da1fae4c 271 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
kenjiArai 13:d0d1da1fae4c 272 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
kenjiArai 13:d0d1da1fae4c 273 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
kenjiArai 13:d0d1da1fae4c 274 #else // following is best ?
kenjiArai 13:d0d1da1fae4c 275 // SYSCLK = 32 MHz ((16 MHz * 6) / 3)
kenjiArai 13:d0d1da1fae4c 276 // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> 48MHz but nobody know accuracy
kenjiArai 13:d0d1da1fae4c 277 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
kenjiArai 13:d0d1da1fae4c 278 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
kenjiArai 13:d0d1da1fae4c 279 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
kenjiArai 13:d0d1da1fae4c 280 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
kenjiArai 13:d0d1da1fae4c 281 #endif
kenjiArai 13:d0d1da1fae4c 282 // to above line
kenjiArai 10:1c0f58b9c048 283 //-------------------------------------------------------------------------------------------------
kenjiArai 11:587b8f1bab9d 284 // (3) /mbed-src/targets/hal/TARGET_STM/TARGET_STM/TARGET_STM32F4/rtc_api.c
kenjiArai 10:1c0f58b9c048 285 //-------------------------------------------------------------------------------------------------
kenjiArai 10:1c0f58b9c048 286 Please see /debug_tools_L152_F4x1RE/SetRTC/modify_info_F4xx.h
kenjiArai 10:1c0f58b9c048 287
kenjiArai 10:1c0f58b9c048 288 //-------------------------------------------------------------------------------------------------
kenjiArai 11:587b8f1bab9d 289 // (4) /mbed-src/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/rtc_api.c
kenjiArai 10:1c0f58b9c048 290 //-------------------------------------------------------------------------------------------------
kenjiArai 10:1c0f58b9c048 291 Please see /debug_tools_L152_F4x1RE/SetRTC/modify_info_L152.h
kenjiArai 10:1c0f58b9c048 292
kenjiArai 10:1c0f58b9c048 293 #endif ///////////////////////////////////////////////////////////////////////////////////////