John Tarasidis / Mbed 2 deprecated VGA

I2S speed test wip

Dependencies:   mbed

main.cpp@3:c9f3ff8e49c0, 2020-04-25 (annotated)

Committer:
jtarasidis
Date:
Sat Apr 25 23:51:58 2020 +0000
Revision:
3:c9f3ff8e49c0
Parent:
2:8008da2bb047
Child:
4:3bad83de58b3
restruct before adding vsync

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jtarasidis 0:b847a1ffc64f 1 #include "mbed.h"
jtarasidis 0:b847a1ffc64f 2 //#include "SDFileSystem"
jtarasidis 2:8008da2bb047 3 //#include "FastIO.h"
jtarasidis 1:3c1ad60f5cf3 4 //#include "MODDMA.h"
jtarasidis 0:b847a1ffc64f 5
jtarasidis 3:c9f3ff8e49c0 6 //assert PLL0CFG and PLL0CON regs
jtarasidis 3:c9f3ff8e49c0 7 void main_pll_feed() {
jtarasidis 0:b847a1ffc64f 8 __disable_irq();
jtarasidis 0:b847a1ffc64f 9 LPC_SC->PLL0FEED=0x000000aa;
jtarasidis 0:b847a1ffc64f 10 LPC_SC->PLL0FEED=0x00000055;
jtarasidis 0:b847a1ffc64f 11 __enable_irq();
jtarasidis 0:b847a1ffc64f 12 }
jtarasidis 3:c9f3ff8e49c0 13
jtarasidis 3:c9f3ff8e49c0 14 //set 100MHz chip pll
jtarasidis 3:c9f3ff8e49c0 15 void init_main_pll() {
jtarasidis 0:b847a1ffc64f 16 // the MBED crystal oscillator is 12 MHz
jtarasidis 0:b847a1ffc64f 17 // main oscillator frequency 300 MHz: M = (300 x N) / (2 x 12)
jtarasidis 0:b847a1ffc64f 18 int n=2;
jtarasidis 0:b847a1ffc64f 19 int m=25;
jtarasidis 0:b847a1ffc64f 20 // processor clock 100 MHz = 300 MHz / D
jtarasidis 0:b847a1ffc64f 21 int d=3;
jtarasidis 0:b847a1ffc64f 22 // disconnect
jtarasidis 3:c9f3ff8e49c0 23 LPC_SC->PLL0CON=0x00000001; main_pll_feed();
jtarasidis 0:b847a1ffc64f 24 // disable
jtarasidis 3:c9f3ff8e49c0 25 LPC_SC->PLL0CON=0x00000000; main_pll_feed();
jtarasidis 0:b847a1ffc64f 26 // set new PLL values
jtarasidis 3:c9f3ff8e49c0 27 LPC_SC->PLL0CFG=((n-1)<<16)|(m-1); main_pll_feed();
jtarasidis 0:b847a1ffc64f 28 // enable
jtarasidis 3:c9f3ff8e49c0 29 LPC_SC->PLL0CON=0x00000001; main_pll_feed();
jtarasidis 0:b847a1ffc64f 30 // set cpu clock divider
jtarasidis 0:b847a1ffc64f 31 LPC_SC->CCLKCFG=d-1;
jtarasidis 0:b847a1ffc64f 32 // wait for lock
jtarasidis 0:b847a1ffc64f 33 while (LPC_SC->PLL0STAT&0x04000000==0);
jtarasidis 0:b847a1ffc64f 34 // connect
jtarasidis 3:c9f3ff8e49c0 35 LPC_SC->PLL0CON=0x00000003; main_pll_feed();
jtarasidis 0:b847a1ffc64f 36 }
jtarasidis 0:b847a1ffc64f 37
jtarasidis 3:c9f3ff8e49c0 38
jtarasidis 3:c9f3ff8e49c0 39 void init_hsync() {
jtarasidis 2:8008da2bb047 40 LPC_SC -> PCONP = 0;
jtarasidis 2:8008da2bb047 41 //power on pwm
jtarasidis 2:8008da2bb047 42 LPC_SC -> PCONP |= (1<<6);
jtarasidis 2:8008da2bb047 43 //set pwm periph clock
jtarasidis 2:8008da2bb047 44 LPC_SC -> PCLKSEL0 |= (1<<12);
jtarasidis 2:8008da2bb047 45 //pin select (PWM1.2 on P2.1 -> DIP25)
jtarasidis 2:8008da2bb047 46 //LPC_PINCON -> PINMODE_OD2 |= (1<<1);
jtarasidis 2:8008da2bb047 47 LPC_PINCON -> PINSEL4 |= (1<<2);
jtarasidis 2:8008da2bb047 48 //disable internal pull down and pull up resistors
jtarasidis 2:8008da2bb047 49 LPC_PINCON -> PINMODE4 |= (1<<3);
jtarasidis 2:8008da2bb047 50 //set prescale to make 25Mhz timer count (TC)
jtarasidis 2:8008da2bb047 51 LPC_PWM1 -> PR = 3;
jtarasidis 2:8008da2bb047 52 //set trig for PWM TC to reset after each line
jtarasidis 2:8008da2bb047 53 LPC_PWM1 -> MR0 = 800;
jtarasidis 2:8008da2bb047 54 //enable TC reset on MR0 match (end of line)
jtarasidis 2:8008da2bb047 55 LPC_PWM1 -> MCR = 1<<1;
jtarasidis 2:8008da2bb047 56 //set trig for HSYNC to go low after 656 pixels
jtarasidis 2:8008da2bb047 57 LPC_PWM1 -> MR2 = 656;
jtarasidis 2:8008da2bb047 58 //set trig for HSYNC to go high after 752 pixels
jtarasidis 2:8008da2bb047 59 LPC_PWM1 -> MR1 |= 752;
jtarasidis 2:8008da2bb047 60 //enable double edged control on MR2/MR1 trigs
jtarasidis 2:8008da2bb047 61 LPC_PWM1 -> PCR = 1<<2;
jtarasidis 2:8008da2bb047 62 //enable output
jtarasidis 2:8008da2bb047 63 LPC_PWM1 -> PCR |= 1<<10;
jtarasidis 3:c9f3ff8e49c0 64 }
jtarasidis 3:c9f3ff8e49c0 65
jtarasidis 3:c9f3ff8e49c0 66 void hsync_enable() {
jtarasidis 2:8008da2bb047 67 //enable TC
jtarasidis 2:8008da2bb047 68 LPC_PWM1 -> TCR |= 1;
jtarasidis 2:8008da2bb047 69 //enable PWM
jtarasidis 2:8008da2bb047 70 LPC_PWM1 -> TCR |= 8;
jtarasidis 3:c9f3ff8e49c0 71 }
jtarasidis 3:c9f3ff8e49c0 72
jtarasidis 3:c9f3ff8e49c0 73 int main() {
jtarasidis 3:c9f3ff8e49c0 74 init_main_pll();
jtarasidis 3:c9f3ff8e49c0 75 main_pll_feed();
jtarasidis 3:c9f3ff8e49c0 76
jtarasidis 3:c9f3ff8e49c0 77 init_hsync();
jtarasidis 3:c9f3ff8e49c0 78 hsync_enable();
jtarasidis 3:c9f3ff8e49c0 79
jtarasidis 2:8008da2bb047 80
jtarasidis 2:8008da2bb047 81
jtarasidis 2:8008da2bb047 82
jtarasidis 1:3c1ad60f5cf3 83 //char s[] = "I2S CCLK/4 Verification Test";
jtarasidis 0:b847a1ffc64f 84
jtarasidis 0:b847a1ffc64f 85 //turn on i2s periph
jtarasidis 1:3c1ad60f5cf3 86 //LPC_SC -> PCONP |= (1 << 27);
jtarasidis 1:3c1ad60f5cf3 87 //set PCLK_peripheral = CCLK/2 so that serial tx CCLK/4
jtarasidis 1:3c1ad60f5cf3 88 //LPC_SC -> PCLKSEL1 |= (2 << 22);
jtarasidis 1:3c1ad60f5cf3 89 //assign clock pin and probe
jtarasidis 0:b847a1ffc64f 90
jtarasidis 1:3c1ad60f5cf3 91 //LPC_I2S -> I2STXRATE |= (4 | (1 << 8));
jtarasidis 1:3c1ad60f5cf3 92
jtarasidis 0:b847a1ffc64f 93
jtarasidis 0:b847a1ffc64f 94 //monaural format; master mode
jtarasidis 1:3c1ad60f5cf3 95 //LPC_I2S -> I2SDAO |= (0x8);
jtarasidis 0:b847a1ffc64f 96
jtarasidis 0:b847a1ffc64f 97 //connect i2s channel 0 tx to dma
jtarasidis 1:3c1ad60f5cf3 98 //LPC_I2S -> I2SDMA1 |= (0x70002);
jtarasidis 0:b847a1ffc64f 99
jtarasidis 0:b847a1ffc64f 100 //select p5 pin for i2s tx
jtarasidis 1:3c1ad60f5cf3 101 //LPC_PINCON -> PINSEL0 |= (1 << 18);
jtarasidis 1:3c1ad60f5cf3 102 //LPC_PINCON -> PINSEL0 |= (1 << 14);
jtarasidis 0:b847a1ffc64f 103
jtarasidis 0:b847a1ffc64f 104
jtarasidis 1:3c1ad60f5cf3 105 //MODDMA_Config *config = new MODDMA_Config;
jtarasidis 1:3c1ad60f5cf3 106 //config
jtarasidis 1:3c1ad60f5cf3 107 // ->channelNum ( MODDMA::Channel_0 )
jtarasidis 1:3c1ad60f5cf3 108 // ->srcMemAddr ( (uint32_t) &s )
jtarasidis 1:3c1ad60f5cf3 109 // ->dstMemAddr ( LPC_I2S -> I2STXFIFO )
jtarasidis 1:3c1ad60f5cf3 110 // ->transferSize ( sizeof(s) )
jtarasidis 1:3c1ad60f5cf3 111 // ->transferType ( MODDMA::m2p )
jtarasidis 1:3c1ad60f5cf3 112 // ->transferWidth ( 8 )
jtarasidis 1:3c1ad60f5cf3 113 // ->srcConn ( 0 )
jtarasidis 1:3c1ad60f5cf3 114 // ->dstConn ( MODDMA::I2S_Channel_0 )
jtarasidis 1:3c1ad60f5cf3 115 // ->dmaLLI ( 0 )
jtarasidis 1:3c1ad60f5cf3 116 // ->attach_tc ( &TC0_callback )
jtarasidis 1:3c1ad60f5cf3 117 //;
jtarasidis 0:b847a1ffc64f 118
jtarasidis 1:3c1ad60f5cf3 119 //dma.Setup(config);
jtarasidis 1:3c1ad60f5cf3 120 //dma.Enable(config);
jtarasidis 0:b847a1ffc64f 121 while(1) {
jtarasidis 2:8008da2bb047 122
jtarasidis 0:b847a1ffc64f 123 }
jtarasidis 0:b847a1ffc64f 124 }
jtarasidis 0:b847a1ffc64f 125