Diff: main.cpp

Revision:

3:c9f3ff8e49c0

Parent:

2:8008da2bb047

Child:

4:3bad83de58b3

--- a/main.cpp	Sat Apr 25 23:21:07 2020 +0000
+++ b/main.cpp	Sat Apr 25 23:51:58 2020 +0000
@@ -3,13 +3,16 @@
 //#include "FastIO.h"
 //#include "MODDMA.h"
 
-void pllfeed() {
+//assert PLL0CFG and PLL0CON regs
+void main_pll_feed() {
     __disable_irq();
     LPC_SC->PLL0FEED=0x000000aa;
     LPC_SC->PLL0FEED=0x00000055;
     __enable_irq();    
 }
-void setpll() {
+
+//set 100MHz chip pll
+void init_main_pll() {
     // the MBED crystal oscillator is 12 MHz
     // main oscillator frequency 300 MHz: M = (300 x N) / (2 x 12)
     int n=2;
@@ -17,24 +20,23 @@
     // processor clock 100 MHz = 300 MHz / D
     int d=3;
     // disconnect
-    LPC_SC->PLL0CON=0x00000001; pllfeed();
+    LPC_SC->PLL0CON=0x00000001; main_pll_feed();
     // disable
-    LPC_SC->PLL0CON=0x00000000; pllfeed();
+    LPC_SC->PLL0CON=0x00000000; main_pll_feed();
     // set new PLL values
-    LPC_SC->PLL0CFG=((n-1)<<16)|(m-1); pllfeed();
+    LPC_SC->PLL0CFG=((n-1)<<16)|(m-1); main_pll_feed();
     // enable
-    LPC_SC->PLL0CON=0x00000001; pllfeed();
+    LPC_SC->PLL0CON=0x00000001; main_pll_feed();
     // set cpu clock divider
     LPC_SC->CCLKCFG=d-1;
     // wait for lock
     while (LPC_SC->PLL0STAT&0x04000000==0);
     // connect
-    LPC_SC->PLL0CON=0x00000003; pllfeed();
+    LPC_SC->PLL0CON=0x00000003; main_pll_feed();
 }
 
-int main() {
-    setpll();
-    pllfeed();
+
+void init_hsync() {
     LPC_SC -> PCONP = 0;
     //power on pwm
     LPC_SC -> PCONP |= (1<<6);
@@ -59,10 +61,22 @@
     LPC_PWM1 -> PCR = 1<<2;
     //enable output
     LPC_PWM1 -> PCR |= 1<<10;
+}
+
+void hsync_enable() {
     //enable TC
     LPC_PWM1 -> TCR |= 1;
     //enable PWM
     LPC_PWM1 -> TCR |= 8;
+}
+
+int main() {
+    init_main_pll();
+    main_pll_feed();
+    
+    init_hsync();
+    hsync_enable();
+