John Tarasidis / Mbed 2 deprecated VGA

I2S speed test wip

Dependencies:   mbed

main.cpp@1:3c1ad60f5cf3, 2020-04-25 (annotated)

Committer:
jtarasidis
Date:
Sat Apr 25 18:55:54 2020 +0000
Revision:
1:3c1ad60f5cf3
Parent:
0:b847a1ffc64f
Child:
2:8008da2bb047
save poiunt before resrteucyttre

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jtarasidis 0:b847a1ffc64f 1 #include "mbed.h"
jtarasidis 0:b847a1ffc64f 2 //#include "SDFileSystem"
jtarasidis 1:3c1ad60f5cf3 3 #include "FastIO.h"
jtarasidis 1:3c1ad60f5cf3 4 //#include "MODDMA.h"
jtarasidis 0:b847a1ffc64f 5
jtarasidis 0:b847a1ffc64f 6 void pllfeed() {
jtarasidis 0:b847a1ffc64f 7 __disable_irq();
jtarasidis 0:b847a1ffc64f 8 LPC_SC->PLL0FEED=0x000000aa;
jtarasidis 0:b847a1ffc64f 9 LPC_SC->PLL0FEED=0x00000055;
jtarasidis 0:b847a1ffc64f 10 __enable_irq();
jtarasidis 0:b847a1ffc64f 11 }
jtarasidis 0:b847a1ffc64f 12 void setpll() {
jtarasidis 0:b847a1ffc64f 13 // the MBED crystal oscillator is 12 MHz
jtarasidis 0:b847a1ffc64f 14 // main oscillator frequency 300 MHz: M = (300 x N) / (2 x 12)
jtarasidis 0:b847a1ffc64f 15 int n=2;
jtarasidis 0:b847a1ffc64f 16 int m=25;
jtarasidis 0:b847a1ffc64f 17 // processor clock 100 MHz = 300 MHz / D
jtarasidis 0:b847a1ffc64f 18 int d=3;
jtarasidis 0:b847a1ffc64f 19 // disconnect
jtarasidis 0:b847a1ffc64f 20 LPC_SC->PLL0CON=0x00000001; pllfeed();
jtarasidis 0:b847a1ffc64f 21 // disable
jtarasidis 0:b847a1ffc64f 22 LPC_SC->PLL0CON=0x00000000; pllfeed();
jtarasidis 0:b847a1ffc64f 23 // set new PLL values
jtarasidis 0:b847a1ffc64f 24 LPC_SC->PLL0CFG=((n-1)<<16)|(m-1); pllfeed();
jtarasidis 0:b847a1ffc64f 25 // enable
jtarasidis 0:b847a1ffc64f 26 LPC_SC->PLL0CON=0x00000001; pllfeed();
jtarasidis 0:b847a1ffc64f 27 // set cpu clock divider
jtarasidis 0:b847a1ffc64f 28 LPC_SC->CCLKCFG=d-1;
jtarasidis 0:b847a1ffc64f 29 // wait for lock
jtarasidis 0:b847a1ffc64f 30 while (LPC_SC->PLL0STAT&0x04000000==0);
jtarasidis 0:b847a1ffc64f 31 // connect
jtarasidis 0:b847a1ffc64f 32 LPC_SC->PLL0CON=0x00000003; pllfeed();
jtarasidis 0:b847a1ffc64f 33 }
jtarasidis 0:b847a1ffc64f 34
jtarasidis 0:b847a1ffc64f 35
jtarasidis 0:b847a1ffc64f 36 DigitalOut led1(LED1);
jtarasidis 0:b847a1ffc64f 37 DigitalOut led2(LED2);
jtarasidis 0:b847a1ffc64f 38
jtarasidis 1:3c1ad60f5cf3 39 //MODDMA dma;
jtarasidis 0:b847a1ffc64f 40
jtarasidis 0:b847a1ffc64f 41 void TC0_callback(void) {
jtarasidis 0:b847a1ffc64f 42 led1 = 1;
jtarasidis 0:b847a1ffc64f 43 }
jtarasidis 0:b847a1ffc64f 44
jtarasidis 0:b847a1ffc64f 45 Serial test(p13, p14);
jtarasidis 0:b847a1ffc64f 46
jtarasidis 1:3c1ad60f5cf3 47 FastOut<p21> pixel;
jtarasidis 1:3c1ad60f5cf3 48 void pixelout(void) {
jtarasidis 1:3c1ad60f5cf3 49 pixel = 1;
jtarasidis 1:3c1ad60f5cf3 50 wait(0.1);
jtarasidis 1:3c1ad60f5cf3 51 pixel=0;
jtarasidis 1:3c1ad60f5cf3 52 wait(0.1);
jtarasidis 1:3c1ad60f5cf3 53 }
jtarasidis 1:3c1ad60f5cf3 54
jtarasidis 0:b847a1ffc64f 55 int main() {
jtarasidis 0:b847a1ffc64f 56 setpll();
jtarasidis 0:b847a1ffc64f 57 pllfeed();
jtarasidis 1:3c1ad60f5cf3 58 pixelout();
jtarasidis 1:3c1ad60f5cf3 59 //char s[] = "I2S CCLK/4 Verification Test";
jtarasidis 0:b847a1ffc64f 60
jtarasidis 0:b847a1ffc64f 61 //turn on i2s periph
jtarasidis 1:3c1ad60f5cf3 62 //LPC_SC -> PCONP |= (1 << 27);
jtarasidis 1:3c1ad60f5cf3 63 //set PCLK_peripheral = CCLK/2 so that serial tx CCLK/4
jtarasidis 1:3c1ad60f5cf3 64 //LPC_SC -> PCLKSEL1 |= (2 << 22);
jtarasidis 1:3c1ad60f5cf3 65 //assign clock pin and probe
jtarasidis 0:b847a1ffc64f 66
jtarasidis 1:3c1ad60f5cf3 67 //LPC_I2S -> I2STXRATE |= (4 | (1 << 8));
jtarasidis 1:3c1ad60f5cf3 68
jtarasidis 0:b847a1ffc64f 69
jtarasidis 0:b847a1ffc64f 70 //monaural format; master mode
jtarasidis 1:3c1ad60f5cf3 71 //LPC_I2S -> I2SDAO |= (0x8);
jtarasidis 0:b847a1ffc64f 72
jtarasidis 0:b847a1ffc64f 73 //connect i2s channel 0 tx to dma
jtarasidis 1:3c1ad60f5cf3 74 //LPC_I2S -> I2SDMA1 |= (0x70002);
jtarasidis 0:b847a1ffc64f 75
jtarasidis 0:b847a1ffc64f 76 //select p5 pin for i2s tx
jtarasidis 1:3c1ad60f5cf3 77 //LPC_PINCON -> PINSEL0 |= (1 << 18);
jtarasidis 1:3c1ad60f5cf3 78 //LPC_PINCON -> PINSEL0 |= (1 << 14);
jtarasidis 0:b847a1ffc64f 79
jtarasidis 0:b847a1ffc64f 80
jtarasidis 1:3c1ad60f5cf3 81 //MODDMA_Config *config = new MODDMA_Config;
jtarasidis 1:3c1ad60f5cf3 82 //config
jtarasidis 1:3c1ad60f5cf3 83 // ->channelNum ( MODDMA::Channel_0 )
jtarasidis 1:3c1ad60f5cf3 84 // ->srcMemAddr ( (uint32_t) &s )
jtarasidis 1:3c1ad60f5cf3 85 // ->dstMemAddr ( LPC_I2S -> I2STXFIFO )
jtarasidis 1:3c1ad60f5cf3 86 // ->transferSize ( sizeof(s) )
jtarasidis 1:3c1ad60f5cf3 87 // ->transferType ( MODDMA::m2p )
jtarasidis 1:3c1ad60f5cf3 88 // ->transferWidth ( 8 )
jtarasidis 1:3c1ad60f5cf3 89 // ->srcConn ( 0 )
jtarasidis 1:3c1ad60f5cf3 90 // ->dstConn ( MODDMA::I2S_Channel_0 )
jtarasidis 1:3c1ad60f5cf3 91 // ->dmaLLI ( 0 )
jtarasidis 1:3c1ad60f5cf3 92 // ->attach_tc ( &TC0_callback )
jtarasidis 1:3c1ad60f5cf3 93 //;
jtarasidis 0:b847a1ffc64f 94
jtarasidis 1:3c1ad60f5cf3 95 //dma.Setup(config);
jtarasidis 1:3c1ad60f5cf3 96 //dma.Enable(config);
jtarasidis 0:b847a1ffc64f 97 while(1) {
jtarasidis 1:3c1ad60f5cf3 98 //printf("%d ;", LPC_I2S -> I2SSTATE);
jtarasidis 1:3c1ad60f5cf3 99 //wait(0.5);
jtarasidis 1:3c1ad60f5cf3 100 pixelout();
jtarasidis 0:b847a1ffc64f 101 }
jtarasidis 0:b847a1ffc64f 102 }
jtarasidis 0:b847a1ffc64f 103