John Tarasidis / Mbed 2 deprecated VGA

I2S speed test wip

Dependencies:   mbed

main.cpp@4:3bad83de58b3, 2020-04-29 (annotated)

Committer:
jtarasidis
Date:
Wed Apr 29 15:01:23 2020 +0000
Revision:
4:3bad83de58b3
Parent:
3:c9f3ff8e49c0 
newest rev

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jtarasidis 0:b847a1ffc64f 1 #include "mbed.h"
jtarasidis 4:3bad83de58b3 2
jtarasidis 4:3bad83de58b3 3 /////////////////global variables/////////////////////////
jtarasidis 4:3bad83de58b3 4 //create frame buffer in peripheral SRAM bank 0 and bank 1
jtarasidis 4:3bad83de58b3 5 //unsigned char *framebuffer = (unsigned char *)(0x2007C000);
jtarasidis 4:3bad83de58b3 6
jtarasidis 4:3bad83de58b3 7 //volatile unsigned char *pointer = framebuffer;
jtarasidis 4:3bad83de58b3 8
jtarasidis 4:3bad83de58b3 9 //static unsigned line_counter;
jtarasidis 4:3bad83de58b3 10 /////////////////end global variables/////////////////////
jtarasidis 0:b847a1ffc64f 11
jtarasidis 3:c9f3ff8e49c0 12 //assert PLL0CFG and PLL0CON regs
jtarasidis 3:c9f3ff8e49c0 13 void main_pll_feed() {
jtarasidis 0:b847a1ffc64f 14 __disable_irq();
jtarasidis 4:3bad83de58b3 15 LPC_SC -> PLL0FEED = 0x000000aa;
jtarasidis 4:3bad83de58b3 16 LPC_SC -> PLL0FEED = 0x00000055;
jtarasidis 0:b847a1ffc64f 17 __enable_irq();
jtarasidis 0:b847a1ffc64f 18 }
jtarasidis 3:c9f3ff8e49c0 19
jtarasidis 3:c9f3ff8e49c0 20 //set 100MHz chip pll
jtarasidis 3:c9f3ff8e49c0 21 void init_main_pll() {
jtarasidis 0:b847a1ffc64f 22 // the MBED crystal oscillator is 12 MHz
jtarasidis 0:b847a1ffc64f 23 // main oscillator frequency 300 MHz: M = (300 x N) / (2 x 12)
jtarasidis 4:3bad83de58b3 24 int n = 2;
jtarasidis 4:3bad83de58b3 25 int m = 25;
jtarasidis 0:b847a1ffc64f 26 // processor clock 100 MHz = 300 MHz / D
jtarasidis 4:3bad83de58b3 27 int d = 3;
jtarasidis 0:b847a1ffc64f 28 // disconnect
jtarasidis 4:3bad83de58b3 29 LPC_SC -> PLL0CON = 0x00000001; main_pll_feed();
jtarasidis 0:b847a1ffc64f 30 // disable
jtarasidis 4:3bad83de58b3 31 LPC_SC -> PLL0CON = 0x00000000; main_pll_feed();
jtarasidis 0:b847a1ffc64f 32 // set new PLL values
jtarasidis 4:3bad83de58b3 33 LPC_SC -> PLL0CFG = ((n-1)<<16)|(m-1); main_pll_feed();
jtarasidis 0:b847a1ffc64f 34 // enable
jtarasidis 4:3bad83de58b3 35 LPC_SC -> PLL0CON = 0x00000001; main_pll_feed();
jtarasidis 0:b847a1ffc64f 36 // set cpu clock divider
jtarasidis 4:3bad83de58b3 37 LPC_SC -> CCLKCFG = (d-1);
jtarasidis 0:b847a1ffc64f 38 // wait for lock
jtarasidis 4:3bad83de58b3 39 while (LPC_SC -> PLL0STAT&0x04000000==0);
jtarasidis 0:b847a1ffc64f 40 // connect
jtarasidis 4:3bad83de58b3 41 LPC_SC -> PLL0CON = 0x00000003; main_pll_feed();
jtarasidis 0:b847a1ffc64f 42 }
jtarasidis 0:b847a1ffc64f 43
jtarasidis 3:c9f3ff8e49c0 44
jtarasidis 3:c9f3ff8e49c0 45 void init_hsync() {
jtarasidis 4:3bad83de58b3 46 //LPC_SC -> PCONP = 0;
jtarasidis 2:8008da2bb047 47 //power on pwm
jtarasidis 2:8008da2bb047 48 LPC_SC -> PCONP |= (1<<6);
jtarasidis 2:8008da2bb047 49 //set pwm periph clock
jtarasidis 2:8008da2bb047 50 LPC_SC -> PCLKSEL0 |= (1<<12);
jtarasidis 2:8008da2bb047 51 //pin select (PWM1.2 on P2.1 -> DIP25)
jtarasidis 2:8008da2bb047 52 //LPC_PINCON -> PINMODE_OD2 |= (1<<1);
jtarasidis 2:8008da2bb047 53 LPC_PINCON -> PINSEL4 |= (1<<2);
jtarasidis 2:8008da2bb047 54 //disable internal pull down and pull up resistors
jtarasidis 2:8008da2bb047 55 LPC_PINCON -> PINMODE4 |= (1<<3);
jtarasidis 2:8008da2bb047 56 //set prescale to make 25Mhz timer count (TC)
jtarasidis 2:8008da2bb047 57 LPC_PWM1 -> PR = 3;
jtarasidis 2:8008da2bb047 58 //set trig for PWM TC to reset after each line
jtarasidis 2:8008da2bb047 59 LPC_PWM1 -> MR0 = 800;
jtarasidis 2:8008da2bb047 60 //enable TC reset on MR0 match (end of line)
jtarasidis 2:8008da2bb047 61 LPC_PWM1 -> MCR = 1<<1;
jtarasidis 2:8008da2bb047 62 //set trig for HSYNC to go low after 656 pixels
jtarasidis 2:8008da2bb047 63 LPC_PWM1 -> MR2 = 656;
jtarasidis 2:8008da2bb047 64 //set trig for HSYNC to go high after 752 pixels
jtarasidis 2:8008da2bb047 65 LPC_PWM1 -> MR1 |= 752;
jtarasidis 2:8008da2bb047 66 //enable double edged control on MR2/MR1 trigs
jtarasidis 2:8008da2bb047 67 LPC_PWM1 -> PCR = 1<<2;
jtarasidis 2:8008da2bb047 68 //enable output
jtarasidis 2:8008da2bb047 69 LPC_PWM1 -> PCR |= 1<<10;
jtarasidis 3:c9f3ff8e49c0 70 }
jtarasidis 3:c9f3ff8e49c0 71
jtarasidis 3:c9f3ff8e49c0 72 void hsync_enable() {
jtarasidis 2:8008da2bb047 73 //enable TC
jtarasidis 2:8008da2bb047 74 LPC_PWM1 -> TCR |= 1;
jtarasidis 2:8008da2bb047 75 //enable PWM
jtarasidis 2:8008da2bb047 76 LPC_PWM1 -> TCR |= 8;
jtarasidis 3:c9f3ff8e49c0 77 }
jtarasidis 3:c9f3ff8e49c0 78
jtarasidis 4:3bad83de58b3 79 void init_vysnc() {
jtarasidis 4:3bad83de58b3 80 ///////////////////////////
jtarasidis 4:3bad83de58b3 81 //power timer 3 (0/1 used by DMA)
jtarasidis 4:3bad83de58b3 82 //LPC_SC -> PCONP |= (1<<23);
jtarasidis 4:3bad83de58b3 83 //set timer periph clock - CCLK/4 = 25MHz by default
jtarasidis 4:3bad83de58b3 84 //LPC_SC -> PCLKSEL1 |= (0<<12);
jtarasidis 4:3bad83de58b3 85 //pin select (MAT3.1 on 0.11 -> DIP 27)
jtarasidis 4:3bad83de58b3 86 //LPC_PINCON -> PINSEL0 |= (3<<22);
jtarasidis 4:3bad83de58b3 87 //pin mode
jtarasidis 4:3bad83de58b3 88 //LPC_PINCON -> PINMODE0 |= (1<<23);
jtarasidis 4:3bad83de58b3 89 //set TC reset time
jtarasidis 4:3bad83de58b3 90 //LPC_TIM3 -> MR0 = 359200;
jtarasidis 4:3bad83de58b3 91 //set reset on MR0
jtarasidis 4:3bad83de58b3 92 //LPC_TIM3 -> MCR |= (1<<1);
jtarasidis 4:3bad83de58b3 93 //toggle at 331200
jtarasidis 4:3bad83de58b3 94 //LPC_TIM3 -> MR1 = 331200;
jtarasidis 4:3bad83de58b3 95 //set toggle on match
jtarasidis 4:3bad83de58b3 96 //LPC_TIM3 -> EMR |= (1<<1);
jtarasidis 4:3bad83de58b3 97 //enable toggle on match
jtarasidis 4:3bad83de58b3 98 //LPC_TIM3 -> EMR |= (3<<6);
jtarasidis 4:3bad83de58b3 99 //timer enable
jtarasidis 4:3bad83de58b3 100 //LPC_TIM3 -> TCR |= 1;
jtarasidis 4:3bad83de58b3 101 /////////////////////////////
jtarasidis 4:3bad83de58b3 102
jtarasidis 4:3bad83de58b3 103 }
jtarasidis 4:3bad83de58b3 104 DigitalOut vsync(p27);
jtarasidis 4:3bad83de58b3 105 //void init_i2s() {
jtarasidis 4:3bad83de58b3 106 DigitalOut pixel(p21);
jtarasidis 4:3bad83de58b3 107
jtarasidis 3:c9f3ff8e49c0 108 int main() {
jtarasidis 3:c9f3ff8e49c0 109 init_main_pll();
jtarasidis 3:c9f3ff8e49c0 110 main_pll_feed();
jtarasidis 3:c9f3ff8e49c0 111
jtarasidis 3:c9f3ff8e49c0 112 init_hsync();
jtarasidis 3:c9f3ff8e49c0 113 hsync_enable();
jtarasidis 3:c9f3ff8e49c0 114
jtarasidis 4:3bad83de58b3 115 init_vysnc();
jtarasidis 2:8008da2bb047 116
jtarasidis 4:3bad83de58b3 117 pixel = 1;
jtarasidis 1:3c1ad60f5cf3 118 //char s[] = "I2S CCLK/4 Verification Test";
jtarasidis 0:b847a1ffc64f 119
jtarasidis 0:b847a1ffc64f 120 //turn on i2s periph
jtarasidis 1:3c1ad60f5cf3 121 //LPC_SC -> PCONP |= (1 << 27);
jtarasidis 1:3c1ad60f5cf3 122 //set PCLK_peripheral = CCLK/2 so that serial tx CCLK/4
jtarasidis 1:3c1ad60f5cf3 123 //LPC_SC -> PCLKSEL1 |= (2 << 22);
jtarasidis 1:3c1ad60f5cf3 124 //assign clock pin and probe
jtarasidis 0:b847a1ffc64f 125
jtarasidis 1:3c1ad60f5cf3 126 //LPC_I2S -> I2STXRATE |= (4 | (1 << 8));
jtarasidis 1:3c1ad60f5cf3 127
jtarasidis 0:b847a1ffc64f 128
jtarasidis 0:b847a1ffc64f 129 //monaural format; master mode
jtarasidis 1:3c1ad60f5cf3 130 //LPC_I2S -> I2SDAO |= (0x8);
jtarasidis 0:b847a1ffc64f 131
jtarasidis 0:b847a1ffc64f 132 //connect i2s channel 0 tx to dma
jtarasidis 1:3c1ad60f5cf3 133 //LPC_I2S -> I2SDMA1 |= (0x70002);
jtarasidis 0:b847a1ffc64f 134
jtarasidis 0:b847a1ffc64f 135 //select p5 pin for i2s tx
jtarasidis 1:3c1ad60f5cf3 136 //LPC_PINCON -> PINSEL0 |= (1 << 18);
jtarasidis 1:3c1ad60f5cf3 137 //LPC_PINCON -> PINSEL0 |= (1 << 14);
jtarasidis 0:b847a1ffc64f 138
jtarasidis 0:b847a1ffc64f 139
jtarasidis 1:3c1ad60f5cf3 140 //MODDMA_Config *config = new MODDMA_Config;
jtarasidis 1:3c1ad60f5cf3 141 //config
jtarasidis 1:3c1ad60f5cf3 142 // ->channelNum ( MODDMA::Channel_0 )
jtarasidis 1:3c1ad60f5cf3 143 // ->srcMemAddr ( (uint32_t) &s )
jtarasidis 1:3c1ad60f5cf3 144 // ->dstMemAddr ( LPC_I2S -> I2STXFIFO )
jtarasidis 1:3c1ad60f5cf3 145 // ->transferSize ( sizeof(s) )
jtarasidis 1:3c1ad60f5cf3 146 // ->transferType ( MODDMA::m2p )
jtarasidis 1:3c1ad60f5cf3 147 // ->transferWidth ( 8 )
jtarasidis 1:3c1ad60f5cf3 148 // ->srcConn ( 0 )
jtarasidis 1:3c1ad60f5cf3 149 // ->dstConn ( MODDMA::I2S_Channel_0 )
jtarasidis 1:3c1ad60f5cf3 150 // ->dmaLLI ( 0 )
jtarasidis 1:3c1ad60f5cf3 151 // ->attach_tc ( &TC0_callback )
jtarasidis 1:3c1ad60f5cf3 152 //;
jtarasidis 0:b847a1ffc64f 153
jtarasidis 1:3c1ad60f5cf3 154 //dma.Setup(config);
jtarasidis 1:3c1ad60f5cf3 155 //dma.Enable(config);
jtarasidis 0:b847a1ffc64f 156 while(1) {
jtarasidis 4:3bad83de58b3 157 //if (LPC_TIM3 -> TC > 331200) {
jtarasidis 4:3bad83de58b3 158 // LPC_TIM3 -> MR1 = 329600;
jtarasidis 4:3bad83de58b3 159 //} else {
jtarasidis 4:3bad83de58b3 160 // LPC_TIM3 -> MR1 = 331200;
jtarasidis 4:3bad83de58b3 161 //}
jtarasidis 4:3bad83de58b3 162 //printf("%x/n/r", LPC_PWM1 -> TC);
jtarasidis 4:3bad83de58b3 163 vsync = 1;
jtarasidis 4:3bad83de58b3 164 wait_us(13400);
jtarasidis 4:3bad83de58b3 165 vsync = 0;
jtarasidis 4:3bad83de58b3 166 wait_us(80);
jtarasidis 4:3bad83de58b3 167 vsync = 1;
jtarasidis 4:3bad83de58b3 168 wait_us(1300);
jtarasidis 0:b847a1ffc64f 169 }
jtarasidis 0:b847a1ffc64f 170 }
jtarasidis 0:b847a1ffc64f 171