Peter Drescher / FT800_2

Lib for FTDI FT800 graphic controller "EVE" The API is changed from the FTDI original names. It use smaller names now. DL() will add something to the display list instead of Ft_App_WrCoCmd_Buffer ... The FTDI programmer Guide is also using this commands.

Dependents:   FT800_RGB_demo FT800_RGB_demo2 FT800_demo_for_habr Temp_&_RH_at_TFT-demo ... more

Fork of FT800 by Peter Drescher

The mbed is talking thru the SPI interface with the graphic engine. We have to set up a list of Commands and send them to the FT800 to get graphics.

Hardware

1. VM800C development modules from FTDI : http://www.ftdichip.com/Products/Modules/VM800C.html

The modules come with different size lcd. 3.5", 4.3" or 5" or without. /media/uploads/dreschpe/ftdi_eve.jpg The picture shows a modified board, because my lcd had a different pinout. The mbed is connected to the pin header on the bottom.

2. EVBEVE-FT800 board from GLYN: http://www.glyn.com/News-Events/Newsletter/Newsletter-2013/October-2013/A-quick-start-for-EVE-Requires-no-basic-knowledge-graphics-sound-and-touch-can-all-be-learned-in-minutes

The module has a 40 pin flex cable connector to connect a display out of the EDT series.

/media/uploads/dreschpe/glyn_eve.jpg

The mbed is connected via the pin header on the left. If you use this board with a EDT display you have to uncomment the #define Inv_Backlite in FT_LCD_Type.h, because the backlight dimming is inverted.

3. ConnectEVE board from MikroElektronika http://www.mikroe.com/add-on-boards/display/connecteve/#headers_10 The board has also a pin header to connect the mbed. - not tested, but it looks like the other boards.

4. ADAM arduino shield http://www.4dsystems.com.au/product/4DLCD_FT843/ Component page : http://mbed.org/components/ADAM/

Works with the NUCLEO boards, but you have to patch three wires.

/media/uploads/dreschpe/adam.jpg

Connection

We need 5 signals to connect to the mbed. SCK, MOSI and MISO are connected to a SPI channel. SS is the chip select signal and PD work as powerdown. The additional INT signal is not used at the moment. It is possible to generate a interrupt signal, but at the moment you have to poll the status register of the FT800 to see if a command is finished.

Software

This lib is based on the demo code from FTDI. If you want to use it, you have to read the programming manual : http://www.ftdichip.com/Support/Documents/ProgramGuides/FT800%20Programmers%20Guide.pdf

See my demo : http://mbed.org/users/dreschpe/code/FT800_RGB_demo/

FT_Gpu_Hal.cpp@6:16e22c789f7d, 2015-02-10 (annotated)

Committer:
dreschpe
Date:
Tue Feb 10 23:32:22 2015 +0000
Revision:
6:16e22c789f7d
Parent:
4:363ec27cdfaa 
Add function to read/write touch calibration data.; Add color names  ; Add a patch from  Ivano Pelicella to draw flat buttons

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 2:ab74a9a05970 1 /* mbed Library for FTDI FT800 Enbedded Video Engine "EVE"
dreschpe 3:392d2c733c68 2 * based on Original Code Sample from FTDI
dreschpe 2:ab74a9a05970 3 * ported to mbed by Peter Drescher, DC2PD 2014
dreschpe 3:392d2c733c68 4 * Released under the MIT License: http://mbed.org/license/mit
dreschpe 3:392d2c733c68 5 * 19.09.14 changed to shorter function names
dreschpe 3:392d2c733c68 6 * FTDI was using very long names.
dreschpe 3:392d2c733c68 7 * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ... */
dreschpe 3:392d2c733c68 8
dreschpe 0:5e013296b353 9 #include "FT_Platform.h"
dreschpe 0:5e013296b353 10 #include "mbed.h"
dreschpe 0:5e013296b353 11 #include "FT_LCD_Type.h"
dreschpe 0:5e013296b353 12
dreschpe 0:5e013296b353 13 FT800::FT800(PinName mosi,
dreschpe 0:5e013296b353 14 PinName miso,
dreschpe 0:5e013296b353 15 PinName sck,
dreschpe 0:5e013296b353 16 PinName ss,
dreschpe 0:5e013296b353 17 PinName intr,
dreschpe 0:5e013296b353 18 PinName pd)
dreschpe 3:392d2c733c68 19 :
dreschpe 3:392d2c733c68 20 _spi(mosi, miso, sck),
dreschpe 0:5e013296b353 21 _ss(ss),
dreschpe 3:392d2c733c68 22 _pd(pd),
dreschpe 3:392d2c733c68 23 _f800_isr(InterruptIn(intr))
dreschpe 0:5e013296b353 24 {
dreschpe 0:5e013296b353 25 _spi.format(8,0); // 8 bit spi mode 0
dreschpe 6:16e22c789f7d 26 _spi.frequency(2000000); // start with 10 Mhz SPI clock
dreschpe 0:5e013296b353 27 _ss = 1; // cs high
dreschpe 3:392d2c733c68 28 _pd = 1; // PD high
dreschpe 3:392d2c733c68 29 Bootup();
dreschpe 0:5e013296b353 30 }
dreschpe 0:5e013296b353 31
dreschpe 0:5e013296b353 32
dreschpe 0:5e013296b353 33 ft_bool_t FT800::Bootup(void){
dreschpe 3:392d2c733c68 34 Open();
dreschpe 0:5e013296b353 35 BootupConfig();
dreschpe 3:392d2c733c68 36
dreschpe 0:5e013296b353 37 return(1);
dreschpe 0:5e013296b353 38 }
dreschpe 3:392d2c733c68 39
dreschpe 0:5e013296b353 40
dreschpe 0:5e013296b353 41 ft_void_t FT800::BootupConfig(void){
dreschpe 0:5e013296b353 42 ft_uint8_t chipid;
dreschpe 0:5e013296b353 43 /* Do a power cycle for safer side */
dreschpe 3:392d2c733c68 44 Powercycle( FT_TRUE);
dreschpe 0:5e013296b353 45
dreschpe 0:5e013296b353 46 /* Access address 0 to wake up the FT800 */
dreschpe 3:392d2c733c68 47 HostCommand( FT_GPU_ACTIVE_M);
dreschpe 3:392d2c733c68 48 Sleep(20);
dreschpe 0:5e013296b353 49
dreschpe 0:5e013296b353 50 /* Set the clk to external clock */
dreschpe 3:392d2c733c68 51 HostCommand( FT_GPU_EXTERNAL_OSC);
dreschpe 3:392d2c733c68 52 Sleep(10);
dreschpe 3:392d2c733c68 53
dreschpe 0:5e013296b353 54
dreschpe 0:5e013296b353 55 /* Switch PLL output to 48MHz */
dreschpe 3:392d2c733c68 56 HostCommand( FT_GPU_PLL_48M);
dreschpe 3:392d2c733c68 57 Sleep(10);
dreschpe 0:5e013296b353 58
dreschpe 0:5e013296b353 59 /* Do a core reset for safer side */
dreschpe 3:392d2c733c68 60 HostCommand( FT_GPU_CORE_RESET);
dreschpe 0:5e013296b353 61
dreschpe 3:392d2c733c68 62 //Read Register ID to check if FT800 is ready.
dreschpe 3:392d2c733c68 63 chipid = Rd8( REG_ID);
dreschpe 0:5e013296b353 64 while(chipid != 0x7C)
dreschpe 3:392d2c733c68 65 chipid = Rd8( REG_ID);
dreschpe 3:392d2c733c68 66
dreschpe 0:5e013296b353 67
dreschpe 3:392d2c733c68 68 // Speed up
dreschpe 3:392d2c733c68 69 _spi.frequency(20000000); // 20 Mhz SPI clock
dreschpe 3:392d2c733c68 70
dreschpe 0:5e013296b353 71 /* Configuration of LCD display */
dreschpe 3:392d2c733c68 72 DispHCycle = my_DispHCycle;
dreschpe 3:392d2c733c68 73 Wr16( REG_HCYCLE, DispHCycle);
dreschpe 3:392d2c733c68 74 DispHOffset = my_DispHOffset;
dreschpe 3:392d2c733c68 75 Wr16( REG_HOFFSET, DispHOffset);
dreschpe 3:392d2c733c68 76 DispWidth = my_DispWidth;
dreschpe 3:392d2c733c68 77 Wr16( REG_HSIZE, DispWidth);
dreschpe 3:392d2c733c68 78 DispHSync0 = my_DispHSync0;
dreschpe 3:392d2c733c68 79 Wr16( REG_HSYNC0, DispHSync0);
dreschpe 3:392d2c733c68 80 DispHSync1 = my_DispHSync1;
dreschpe 3:392d2c733c68 81 Wr16( REG_HSYNC1, DispHSync1);
dreschpe 3:392d2c733c68 82 DispVCycle = my_DispVCycle;
dreschpe 3:392d2c733c68 83 Wr16( REG_VCYCLE, DispVCycle);
dreschpe 3:392d2c733c68 84 DispVOffset = my_DispVOffset;
dreschpe 3:392d2c733c68 85 Wr16( REG_VOFFSET, DispVOffset);
dreschpe 3:392d2c733c68 86 DispHeight = my_DispHeight;
dreschpe 3:392d2c733c68 87 Wr16( REG_VSIZE, DispHeight);
dreschpe 3:392d2c733c68 88 DispVSync0 = my_DispVSync0;
dreschpe 3:392d2c733c68 89 Wr16( REG_VSYNC0, DispVSync0);
dreschpe 3:392d2c733c68 90 DispVSync1 = my_DispVSync1;
dreschpe 3:392d2c733c68 91 Wr16( REG_VSYNC1, DispVSync1);
dreschpe 3:392d2c733c68 92 DispSwizzle = my_DispSwizzle;
dreschpe 4:363ec27cdfaa 93 Wr8( REG_SWIZZLE, DispSwizzle);
dreschpe 3:392d2c733c68 94 DispPCLKPol = my_DispPCLKPol;
dreschpe 4:363ec27cdfaa 95 Wr8( REG_PCLK_POL, DispPCLKPol);
dreschpe 4:363ec27cdfaa 96 Wr8( REG_CSPREAD, 1);
dreschpe 3:392d2c733c68 97 DispPCLK = my_DispPCLK;
dreschpe 4:363ec27cdfaa 98 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
dreschpe 0:5e013296b353 99
dreschpe 3:392d2c733c68 100 Wr16( REG_PWM_HZ, 1000);
dreschpe 3:392d2c733c68 101
dreschpe 3:392d2c733c68 102 #ifdef Inv_Backlite // turn on backlite
dreschpe 3:392d2c733c68 103 Wr16( REG_PWM_DUTY, 0);
dreschpe 0:5e013296b353 104 #else
dreschpe 3:392d2c733c68 105 Wr16( REG_PWM_DUTY, 100);
dreschpe 3:392d2c733c68 106 #endif
dreschpe 3:392d2c733c68 107
dreschpe 3:392d2c733c68 108 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
dreschpe 3:392d2c733c68 109 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
dreschpe 3:392d2c733c68 110
dreschpe 3:392d2c733c68 111 Wr32( RAM_DL, CLEAR(1,1,1));
dreschpe 3:392d2c733c68 112 Wr32( RAM_DL+4, DISPLAY());
dreschpe 3:392d2c733c68 113 Wr32( REG_DLSWAP,1);
dreschpe 3:392d2c733c68 114
dreschpe 3:392d2c733c68 115 Wr16( REG_PCLK, DispPCLK);
dreschpe 3:392d2c733c68 116
dreschpe 0:5e013296b353 117 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
dreschpe 3:392d2c733c68 118 Wr16( REG_TOUCH_RZTHRESH,1200);
dreschpe 0:5e013296b353 119
dreschpe 0:5e013296b353 120 }
dreschpe 0:5e013296b353 121
dreschpe 0:5e013296b353 122
dreschpe 0:5e013296b353 123
dreschpe 0:5e013296b353 124 /* API to initialize the SPI interface */
dreschpe 3:392d2c733c68 125 ft_bool_t FT800::Init()
dreschpe 0:5e013296b353 126 {
dreschpe 0:5e013296b353 127 // is done in constructor
dreschpe 0:5e013296b353 128 return 1;
dreschpe 0:5e013296b353 129 }
dreschpe 0:5e013296b353 130
dreschpe 0:5e013296b353 131
dreschpe 3:392d2c733c68 132 ft_bool_t FT800::Open()
dreschpe 0:5e013296b353 133 {
dreschpe 3:392d2c733c68 134 cmd_fifo_wp = dl_buff_wp = 0;
dreschpe 3:392d2c733c68 135 status = OPENED;
dreschpe 0:5e013296b353 136 return 1;
dreschpe 0:5e013296b353 137 }
dreschpe 0:5e013296b353 138
dreschpe 3:392d2c733c68 139 ft_void_t FT800::Close( )
dreschpe 0:5e013296b353 140 {
dreschpe 3:392d2c733c68 141 status = CLOSED;
dreschpe 0:5e013296b353 142 }
dreschpe 0:5e013296b353 143
dreschpe 3:392d2c733c68 144 ft_void_t FT800::DeInit()
dreschpe 0:5e013296b353 145 {
dreschpe 0:5e013296b353 146
dreschpe 0:5e013296b353 147 }
dreschpe 0:5e013296b353 148
dreschpe 0:5e013296b353 149 /*The APIs for reading/writing transfer continuously only with small buffer system*/
dreschpe 3:392d2c733c68 150 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
dreschpe 0:5e013296b353 151 {
dreschpe 0:5e013296b353 152 if (FT_GPU_READ == rw){
dreschpe 0:5e013296b353 153 _ss = 0; // cs low
dreschpe 0:5e013296b353 154 _spi.write(addr >> 16);
dreschpe 0:5e013296b353 155 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 156 _spi.write(addr & 0xff);
dreschpe 0:5e013296b353 157 _spi.write(0); //Dummy Read Byte
dreschpe 3:392d2c733c68 158 status = READING;
dreschpe 0:5e013296b353 159 }else{
dreschpe 0:5e013296b353 160 _ss = 0; // cs low
dreschpe 0:5e013296b353 161 _spi.write(0x80 | (addr >> 16));
dreschpe 0:5e013296b353 162 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 163 _spi.write(addr & 0xff);
dreschpe 3:392d2c733c68 164 status = WRITING;
dreschpe 0:5e013296b353 165 }
dreschpe 0:5e013296b353 166 }
dreschpe 0:5e013296b353 167
dreschpe 0:5e013296b353 168
dreschpe 0:5e013296b353 169 /*The APIs for writing transfer continuously only*/
dreschpe 3:392d2c733c68 170 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
dreschpe 0:5e013296b353 171 {
dreschpe 3:392d2c733c68 172 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
dreschpe 0:5e013296b353 173 }
dreschpe 0:5e013296b353 174
dreschpe 3:392d2c733c68 175 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
dreschpe 0:5e013296b353 176 {
dreschpe 0:5e013296b353 177 ft_uint16_t length = strlen(string);
dreschpe 0:5e013296b353 178 while(length --){
dreschpe 3:392d2c733c68 179 Transfer8( *string);
dreschpe 0:5e013296b353 180 string ++;
dreschpe 0:5e013296b353 181 }
dreschpe 0:5e013296b353 182 //Append one null as ending flag
dreschpe 3:392d2c733c68 183 Transfer8( 0);
dreschpe 3:392d2c733c68 184 return(1);
dreschpe 0:5e013296b353 185 }
dreschpe 0:5e013296b353 186
dreschpe 0:5e013296b353 187
dreschpe 3:392d2c733c68 188 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
dreschpe 0:5e013296b353 189 {
dreschpe 3:392d2c733c68 190 return _spi.write(value);
dreschpe 0:5e013296b353 191 }
dreschpe 0:5e013296b353 192
dreschpe 0:5e013296b353 193
dreschpe 3:392d2c733c68 194 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
dreschpe 0:5e013296b353 195 {
dreschpe 0:5e013296b353 196 ft_uint16_t retVal = 0;
dreschpe 0:5e013296b353 197
dreschpe 3:392d2c733c68 198 if (status == WRITING){
dreschpe 3:392d2c733c68 199 Transfer8( value & 0xFF);//LSB first
dreschpe 3:392d2c733c68 200 Transfer8( (value >> 8) & 0xFF);
dreschpe 0:5e013296b353 201 }else{
dreschpe 3:392d2c733c68 202 retVal = Transfer8( 0);
dreschpe 3:392d2c733c68 203 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
dreschpe 0:5e013296b353 204 }
dreschpe 0:5e013296b353 205
dreschpe 0:5e013296b353 206 return retVal;
dreschpe 0:5e013296b353 207 }
dreschpe 0:5e013296b353 208
dreschpe 3:392d2c733c68 209 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
dreschpe 0:5e013296b353 210 {
dreschpe 0:5e013296b353 211 ft_uint32_t retVal = 0;
dreschpe 3:392d2c733c68 212 if (status == WRITING){
dreschpe 3:392d2c733c68 213 Transfer16( value & 0xFFFF);//LSB first
dreschpe 3:392d2c733c68 214 Transfer16( (value >> 16) & 0xFFFF);
dreschpe 0:5e013296b353 215 }else{
dreschpe 3:392d2c733c68 216 retVal = Transfer16( 0);
dreschpe 3:392d2c733c68 217 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
dreschpe 0:5e013296b353 218 }
dreschpe 0:5e013296b353 219 return retVal;
dreschpe 0:5e013296b353 220 }
dreschpe 0:5e013296b353 221
dreschpe 3:392d2c733c68 222 ft_void_t FT800::EndTransfer( )
dreschpe 0:5e013296b353 223 {
dreschpe 3:392d2c733c68 224 _ss = 1;
dreschpe 3:392d2c733c68 225 status = OPENED;
dreschpe 0:5e013296b353 226 }
dreschpe 0:5e013296b353 227
dreschpe 0:5e013296b353 228
dreschpe 3:392d2c733c68 229 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
dreschpe 0:5e013296b353 230 {
dreschpe 0:5e013296b353 231 ft_uint8_t value;
dreschpe 3:392d2c733c68 232 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 233 value = Transfer8( 0);
dreschpe 3:392d2c733c68 234 EndTransfer( );
dreschpe 0:5e013296b353 235 return value;
dreschpe 0:5e013296b353 236 }
dreschpe 3:392d2c733c68 237 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
dreschpe 0:5e013296b353 238 {
dreschpe 0:5e013296b353 239 ft_uint16_t value;
dreschpe 3:392d2c733c68 240 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 241 value = Transfer16( 0);
dreschpe 3:392d2c733c68 242 EndTransfer( );
dreschpe 0:5e013296b353 243 return value;
dreschpe 0:5e013296b353 244 }
dreschpe 3:392d2c733c68 245 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
dreschpe 0:5e013296b353 246 {
dreschpe 0:5e013296b353 247 ft_uint32_t value;
dreschpe 3:392d2c733c68 248 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 249 value = Transfer32( 0);
dreschpe 3:392d2c733c68 250 EndTransfer( );
dreschpe 0:5e013296b353 251 return value;
dreschpe 0:5e013296b353 252 }
dreschpe 0:5e013296b353 253
dreschpe 3:392d2c733c68 254 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
dreschpe 3:392d2c733c68 255 {
dreschpe 3:392d2c733c68 256 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 257 Transfer8( v);
dreschpe 3:392d2c733c68 258 EndTransfer( );
dreschpe 0:5e013296b353 259 }
dreschpe 3:392d2c733c68 260 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
dreschpe 0:5e013296b353 261 {
dreschpe 3:392d2c733c68 262 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 263 Transfer16( v);
dreschpe 3:392d2c733c68 264 EndTransfer( );
dreschpe 0:5e013296b353 265 }
dreschpe 3:392d2c733c68 266 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
dreschpe 0:5e013296b353 267 {
dreschpe 3:392d2c733c68 268 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 269 Transfer32( v);
dreschpe 3:392d2c733c68 270 EndTransfer( );
dreschpe 0:5e013296b353 271 }
dreschpe 0:5e013296b353 272
dreschpe 3:392d2c733c68 273 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
dreschpe 0:5e013296b353 274 {
dreschpe 0:5e013296b353 275 _ss = 0;
dreschpe 0:5e013296b353 276 _spi.write(cmd);
dreschpe 0:5e013296b353 277 _spi.write(0);
dreschpe 0:5e013296b353 278 _spi.write(0);
dreschpe 0:5e013296b353 279 _ss = 1;
dreschpe 0:5e013296b353 280 }
dreschpe 0:5e013296b353 281
dreschpe 3:392d2c733c68 282 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
dreschpe 0:5e013296b353 283 {
dreschpe 3:392d2c733c68 284 HostCommand( pllsource);
dreschpe 0:5e013296b353 285 }
dreschpe 0:5e013296b353 286
dreschpe 3:392d2c733c68 287 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
dreschpe 0:5e013296b353 288 {
dreschpe 3:392d2c733c68 289 HostCommand( freq);
dreschpe 0:5e013296b353 290 }
dreschpe 0:5e013296b353 291
dreschpe 3:392d2c733c68 292 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
dreschpe 0:5e013296b353 293 {
dreschpe 3:392d2c733c68 294 HostCommand( pwrmode);
dreschpe 0:5e013296b353 295 }
dreschpe 0:5e013296b353 296
dreschpe 3:392d2c733c68 297 ft_void_t FT800::CoreReset( )
dreschpe 0:5e013296b353 298 {
dreschpe 3:392d2c733c68 299 HostCommand( 0x68);
dreschpe 0:5e013296b353 300 }
dreschpe 0:5e013296b353 301
dreschpe 0:5e013296b353 302
dreschpe 3:392d2c733c68 303 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
dreschpe 0:5e013296b353 304 {
dreschpe 3:392d2c733c68 305 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
dreschpe 0:5e013296b353 306 //4 byte alignment
dreschpe 3:392d2c733c68 307 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
dreschpe 3:392d2c733c68 308 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
dreschpe 0:5e013296b353 309 }
dreschpe 0:5e013296b353 310
dreschpe 0:5e013296b353 311
dreschpe 3:392d2c733c68 312 ft_uint16_t FT800::fifo_Freespace( )
dreschpe 0:5e013296b353 313 {
dreschpe 0:5e013296b353 314 ft_uint16_t fullness,retval;
dreschpe 0:5e013296b353 315
dreschpe 3:392d2c733c68 316 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
dreschpe 0:5e013296b353 317 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
dreschpe 0:5e013296b353 318 return (retval);
dreschpe 0:5e013296b353 319 }
dreschpe 0:5e013296b353 320
dreschpe 3:392d2c733c68 321 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 322 {
dreschpe 3:392d2c733c68 323 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 324
dreschpe 3:392d2c733c68 325 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 326 do {
dreschpe 0:5e013296b353 327 length = count;
dreschpe 0:5e013296b353 328 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 329 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 330 }
dreschpe 3:392d2c733c68 331 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 332
dreschpe 3:392d2c733c68 333 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 334
dreschpe 0:5e013296b353 335 SizeTransfered = 0;
dreschpe 0:5e013296b353 336 while (length--) {
dreschpe 3:392d2c733c68 337 Transfer8( *buffer);
dreschpe 0:5e013296b353 338 buffer++;
dreschpe 0:5e013296b353 339 SizeTransfered ++;
dreschpe 0:5e013296b353 340 }
dreschpe 0:5e013296b353 341 length = SizeTransfered;
dreschpe 0:5e013296b353 342
dreschpe 3:392d2c733c68 343 EndTransfer( );
dreschpe 3:392d2c733c68 344 Updatecmdfifo( length);
dreschpe 0:5e013296b353 345
dreschpe 3:392d2c733c68 346 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 347
dreschpe 0:5e013296b353 348 count -= length;
dreschpe 0:5e013296b353 349 }while (count > 0);
dreschpe 0:5e013296b353 350 }
dreschpe 0:5e013296b353 351
dreschpe 0:5e013296b353 352
dreschpe 3:392d2c733c68 353 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 354 {
dreschpe 3:392d2c733c68 355 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 356
dreschpe 3:392d2c733c68 357 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 358 do {
dreschpe 0:5e013296b353 359 length = count;
dreschpe 0:5e013296b353 360 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 361 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 362 }
dreschpe 3:392d2c733c68 363 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 364
dreschpe 3:392d2c733c68 365 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 366
dreschpe 0:5e013296b353 367
dreschpe 0:5e013296b353 368 SizeTransfered = 0;
dreschpe 0:5e013296b353 369 while (length--) {
dreschpe 3:392d2c733c68 370 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 371 buffer++;
dreschpe 0:5e013296b353 372 SizeTransfered ++;
dreschpe 0:5e013296b353 373 }
dreschpe 0:5e013296b353 374 length = SizeTransfered;
dreschpe 0:5e013296b353 375
dreschpe 3:392d2c733c68 376 EndTransfer( );
dreschpe 3:392d2c733c68 377 Updatecmdfifo( length);
dreschpe 0:5e013296b353 378
dreschpe 3:392d2c733c68 379 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 380
dreschpe 0:5e013296b353 381 count -= length;
dreschpe 0:5e013296b353 382 }while (count > 0);
dreschpe 0:5e013296b353 383 }
dreschpe 0:5e013296b353 384
dreschpe 0:5e013296b353 385
dreschpe 3:392d2c733c68 386 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
dreschpe 0:5e013296b353 387 {
dreschpe 0:5e013296b353 388 ft_uint16_t getfreespace;
dreschpe 0:5e013296b353 389 do{
dreschpe 3:392d2c733c68 390 getfreespace = fifo_Freespace( );
dreschpe 0:5e013296b353 391 }while(getfreespace < count);
dreschpe 0:5e013296b353 392 }
dreschpe 0:5e013296b353 393
dreschpe 3:392d2c733c68 394 ft_void_t FT800::WaitCmdfifo_empty( )
dreschpe 0:5e013296b353 395 {
dreschpe 3:392d2c733c68 396 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
dreschpe 3:392d2c733c68 397
dreschpe 3:392d2c733c68 398 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 399 }
dreschpe 0:5e013296b353 400
dreschpe 3:392d2c733c68 401 ft_void_t FT800::WaitLogo_Finish( )
dreschpe 0:5e013296b353 402 {
dreschpe 0:5e013296b353 403 ft_int16_t cmdrdptr,cmdwrptr;
dreschpe 0:5e013296b353 404
dreschpe 0:5e013296b353 405 do{
dreschpe 3:392d2c733c68 406 cmdrdptr = Rd16( REG_CMD_READ);
dreschpe 3:392d2c733c68 407 cmdwrptr = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 408 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
dreschpe 3:392d2c733c68 409 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 410 }
dreschpe 0:5e013296b353 411
dreschpe 0:5e013296b353 412
dreschpe 3:392d2c733c68 413 ft_void_t FT800::ResetCmdFifo( )
dreschpe 0:5e013296b353 414 {
dreschpe 3:392d2c733c68 415 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 416 }
dreschpe 0:5e013296b353 417
dreschpe 0:5e013296b353 418
dreschpe 3:392d2c733c68 419 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
dreschpe 0:5e013296b353 420 {
dreschpe 3:392d2c733c68 421 CheckCmdBuffer( sizeof(cmd));
dreschpe 3:392d2c733c68 422
dreschpe 3:392d2c733c68 423 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
dreschpe 3:392d2c733c68 424
dreschpe 3:392d2c733c68 425 Updatecmdfifo( sizeof(cmd));
dreschpe 0:5e013296b353 426 }
dreschpe 0:5e013296b353 427
dreschpe 0:5e013296b353 428
dreschpe 3:392d2c733c68 429 ft_void_t FT800::ResetDLBuffer( )
dreschpe 0:5e013296b353 430 {
dreschpe 3:392d2c733c68 431 dl_buff_wp = 0;
dreschpe 0:5e013296b353 432 }
dreschpe 0:5e013296b353 433
dreschpe 0:5e013296b353 434 /* Toggle PD_N pin of FT800 board for a power cycle*/
dreschpe 3:392d2c733c68 435 ft_void_t FT800::Powercycle( ft_bool_t up)
dreschpe 0:5e013296b353 436 {
dreschpe 0:5e013296b353 437 if (up)
dreschpe 0:5e013296b353 438 {
dreschpe 3:392d2c733c68 439 //Toggle PD_N from low to high for power up switch
dreschpe 3:392d2c733c68 440 _pd = 0;
dreschpe 3:392d2c733c68 441 Sleep(20);
dreschpe 0:5e013296b353 442
dreschpe 0:5e013296b353 443 _pd = 1;
dreschpe 3:392d2c733c68 444 Sleep(20);
dreschpe 0:5e013296b353 445 }else
dreschpe 0:5e013296b353 446 {
dreschpe 0:5e013296b353 447 //Toggle PD_N from high to low for power down switch
dreschpe 0:5e013296b353 448 _pd = 1;
dreschpe 3:392d2c733c68 449 Sleep(20);
dreschpe 3:392d2c733c68 450
dreschpe 0:5e013296b353 451 _pd = 0;
dreschpe 3:392d2c733c68 452 Sleep(20);
dreschpe 0:5e013296b353 453 }
dreschpe 0:5e013296b353 454 }
dreschpe 0:5e013296b353 455
dreschpe 3:392d2c733c68 456 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 457 {
dreschpe 3:392d2c733c68 458 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 459
dreschpe 3:392d2c733c68 460 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 461
dreschpe 0:5e013296b353 462 while (length--) {
dreschpe 3:392d2c733c68 463 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 464 buffer++;
dreschpe 0:5e013296b353 465 }
dreschpe 0:5e013296b353 466
dreschpe 3:392d2c733c68 467 EndTransfer( );
dreschpe 0:5e013296b353 468 }
dreschpe 0:5e013296b353 469
dreschpe 3:392d2c733c68 470 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 471 {
dreschpe 3:392d2c733c68 472 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 473
dreschpe 3:392d2c733c68 474 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 475
dreschpe 0:5e013296b353 476 while (length--) {
dreschpe 3:392d2c733c68 477 Transfer8( *buffer);
dreschpe 0:5e013296b353 478 buffer++;
dreschpe 0:5e013296b353 479 }
dreschpe 0:5e013296b353 480
dreschpe 3:392d2c733c68 481 EndTransfer( );
dreschpe 0:5e013296b353 482 }
dreschpe 0:5e013296b353 483
dreschpe 0:5e013296b353 484
dreschpe 3:392d2c733c68 485 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 486 {
dreschpe 3:392d2c733c68 487 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 488
dreschpe 3:392d2c733c68 489 StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 490
dreschpe 0:5e013296b353 491 while (length--) {
dreschpe 3:392d2c733c68 492 *buffer = Transfer8( 0);
dreschpe 0:5e013296b353 493 buffer++;
dreschpe 0:5e013296b353 494 }
dreschpe 0:5e013296b353 495
dreschpe 3:392d2c733c68 496 EndTransfer( );
dreschpe 0:5e013296b353 497 }
dreschpe 0:5e013296b353 498
dreschpe 3:392d2c733c68 499 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
dreschpe 0:5e013296b353 500 {
dreschpe 0:5e013296b353 501 ft_int16_t Length;
dreschpe 0:5e013296b353 502 ft_char8_t *pdst,charval;
dreschpe 0:5e013296b353 503 ft_int32_t CurrVal = value,tmpval,i;
dreschpe 0:5e013296b353 504 ft_char8_t tmparray[16],idx = 0;
dreschpe 0:5e013296b353 505
dreschpe 0:5e013296b353 506 Length = strlen(pSrc);
dreschpe 0:5e013296b353 507 pdst = pSrc + Length;
dreschpe 0:5e013296b353 508
dreschpe 0:5e013296b353 509 if(0 == value)
dreschpe 0:5e013296b353 510 {
dreschpe 0:5e013296b353 511 *pdst++ = '0';
dreschpe 0:5e013296b353 512 *pdst++ = '\0';
dreschpe 0:5e013296b353 513 return 0;
dreschpe 0:5e013296b353 514 }
dreschpe 0:5e013296b353 515
dreschpe 0:5e013296b353 516 if(CurrVal < 0)
dreschpe 0:5e013296b353 517 {
dreschpe 0:5e013296b353 518 *pdst++ = '-';
dreschpe 0:5e013296b353 519 CurrVal = - CurrVal;
dreschpe 0:5e013296b353 520 }
dreschpe 0:5e013296b353 521 /* insert the value */
dreschpe 0:5e013296b353 522 while(CurrVal > 0){
dreschpe 0:5e013296b353 523 tmpval = CurrVal;
dreschpe 0:5e013296b353 524 CurrVal /= 10;
dreschpe 0:5e013296b353 525 tmpval = tmpval - CurrVal*10;
dreschpe 0:5e013296b353 526 charval = '0' + tmpval;
dreschpe 0:5e013296b353 527 tmparray[idx++] = charval;
dreschpe 0:5e013296b353 528 }
dreschpe 0:5e013296b353 529
dreschpe 0:5e013296b353 530 for(i=0;i<idx;i++)
dreschpe 0:5e013296b353 531 {
dreschpe 0:5e013296b353 532 *pdst++ = tmparray[idx - i - 1];
dreschpe 0:5e013296b353 533 }
dreschpe 0:5e013296b353 534 *pdst++ = '\0';
dreschpe 0:5e013296b353 535
dreschpe 0:5e013296b353 536 return 0;
dreschpe 0:5e013296b353 537 }
dreschpe 0:5e013296b353 538
dreschpe 0:5e013296b353 539
dreschpe 3:392d2c733c68 540 ft_void_t FT800::Sleep(ft_uint16_t ms)
dreschpe 0:5e013296b353 541 {
dreschpe 0:5e013296b353 542 wait_ms(ms);
dreschpe 0:5e013296b353 543 }
dreschpe 0:5e013296b353 544
dreschpe 3:392d2c733c68 545 ft_void_t FT800::Sound_ON(){
dreschpe 3:392d2c733c68 546 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 547 }
dreschpe 1:bd671a31e765 548
dreschpe 3:392d2c733c68 549 ft_void_t FT800::Sound_OFF(){
dreschpe 3:392d2c733c68 550 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 551 }
dreschpe 0:5e013296b353 552
dreschpe 0:5e013296b353 553
dreschpe 0:5e013296b353 554
dreschpe 1:bd671a31e765 555