Peter Drescher / FT800_2

Lib for FTDI FT800 graphic controller "EVE" The API is changed from the FTDI original names. It use smaller names now. DL() will add something to the display list instead of Ft_App_WrCoCmd_Buffer ... The FTDI programmer Guide is also using this commands.

Dependents:   FT800_RGB_demo FT800_RGB_demo2 FT800_demo_for_habr Temp_&_RH_at_TFT-demo ... more

Fork of FT800 by Peter Drescher

The mbed is talking thru the SPI interface with the graphic engine. We have to set up a list of Commands and send them to the FT800 to get graphics.

Hardware

1. VM800C development modules from FTDI : http://www.ftdichip.com/Products/Modules/VM800C.html

The modules come with different size lcd. 3.5", 4.3" or 5" or without. /media/uploads/dreschpe/ftdi_eve.jpg The picture shows a modified board, because my lcd had a different pinout. The mbed is connected to the pin header on the bottom.

2. EVBEVE-FT800 board from GLYN: http://www.glyn.com/News-Events/Newsletter/Newsletter-2013/October-2013/A-quick-start-for-EVE-Requires-no-basic-knowledge-graphics-sound-and-touch-can-all-be-learned-in-minutes

The module has a 40 pin flex cable connector to connect a display out of the EDT series.

/media/uploads/dreschpe/glyn_eve.jpg

The mbed is connected via the pin header on the left. If you use this board with a EDT display you have to uncomment the #define Inv_Backlite in FT_LCD_Type.h, because the backlight dimming is inverted.

3. ConnectEVE board from MikroElektronika http://www.mikroe.com/add-on-boards/display/connecteve/#headers_10 The board has also a pin header to connect the mbed. - not tested, but it looks like the other boards.

4. ADAM arduino shield http://www.4dsystems.com.au/product/4DLCD_FT843/ Component page : http://mbed.org/components/ADAM/

Works with the NUCLEO boards, but you have to patch three wires.

/media/uploads/dreschpe/adam.jpg

Connection

We need 5 signals to connect to the mbed. SCK, MOSI and MISO are connected to a SPI channel. SS is the chip select signal and PD work as powerdown. The additional INT signal is not used at the moment. It is possible to generate a interrupt signal, but at the moment you have to poll the status register of the FT800 to see if a command is finished.

Software

This lib is based on the demo code from FTDI. If you want to use it, you have to read the programming manual : http://www.ftdichip.com/Support/Documents/ProgramGuides/FT800%20Programmers%20Guide.pdf

See my demo : http://mbed.org/users/dreschpe/code/FT800_RGB_demo/

FT_Gpu_Hal.cpp@0:5e013296b353, 2014-01-03 (annotated)

Committer:
dreschpe
Date:
Fri Jan 03 15:26:10 2014 +0000
Revision:
0:5e013296b353
Child:
1:bd671a31e765
Lib for FTDI FT800 Graphic Controller EVE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 0:5e013296b353 1 #include "FT_Platform.h"
dreschpe 0:5e013296b353 2 #include "mbed.h"
dreschpe 0:5e013296b353 3 #include "FT_LCD_Type.h"
dreschpe 0:5e013296b353 4
dreschpe 0:5e013296b353 5
dreschpe 0:5e013296b353 6 FT800::FT800(PinName mosi,
dreschpe 0:5e013296b353 7 PinName miso,
dreschpe 0:5e013296b353 8 PinName sck,
dreschpe 0:5e013296b353 9 PinName ss,
dreschpe 0:5e013296b353 10 PinName intr,
dreschpe 0:5e013296b353 11 PinName pd)
dreschpe 0:5e013296b353 12 :_spi(mosi, miso, sck),
dreschpe 0:5e013296b353 13 _ss(ss),
dreschpe 0:5e013296b353 14 _f800_isr(InterruptIn(intr)),
dreschpe 0:5e013296b353 15 _pd(pd)
dreschpe 0:5e013296b353 16 {
dreschpe 0:5e013296b353 17 _spi.format(8,0); // 8 bit spi mode 0
dreschpe 0:5e013296b353 18 _spi.frequency(10000000); // start with 10 Mhz SPI clock
dreschpe 0:5e013296b353 19 _ss = 1; // cs high
dreschpe 0:5e013296b353 20 _pd = 1; // PD high
dreschpe 0:5e013296b353 21 Bootup();
dreschpe 0:5e013296b353 22 }
dreschpe 0:5e013296b353 23
dreschpe 0:5e013296b353 24
dreschpe 0:5e013296b353 25 ft_bool_t FT800::Bootup(void){
dreschpe 0:5e013296b353 26 Ft_Gpu_Hal_Open();
dreschpe 0:5e013296b353 27 BootupConfig();
dreschpe 0:5e013296b353 28
dreschpe 0:5e013296b353 29 return(1);
dreschpe 0:5e013296b353 30 }
dreschpe 0:5e013296b353 31
dreschpe 0:5e013296b353 32
dreschpe 0:5e013296b353 33 ft_void_t FT800::BootupConfig(void){
dreschpe 0:5e013296b353 34 ft_uint8_t chipid;
dreschpe 0:5e013296b353 35 /* Do a power cycle for safer side */
dreschpe 0:5e013296b353 36 Ft_Gpu_Hal_Powercycle( FT_TRUE);
dreschpe 0:5e013296b353 37
dreschpe 0:5e013296b353 38 /* Access address 0 to wake up the FT800 */
dreschpe 0:5e013296b353 39 Ft_Gpu_HostCommand( FT_GPU_ACTIVE_M);
dreschpe 0:5e013296b353 40 Ft_Gpu_Hal_Sleep(20);
dreschpe 0:5e013296b353 41
dreschpe 0:5e013296b353 42 /* Set the clk to external clock */
dreschpe 0:5e013296b353 43 Ft_Gpu_HostCommand( FT_GPU_EXTERNAL_OSC);
dreschpe 0:5e013296b353 44 Ft_Gpu_Hal_Sleep(10);
dreschpe 0:5e013296b353 45
dreschpe 0:5e013296b353 46
dreschpe 0:5e013296b353 47 /* Switch PLL output to 48MHz */
dreschpe 0:5e013296b353 48 Ft_Gpu_HostCommand( FT_GPU_PLL_48M);
dreschpe 0:5e013296b353 49 Ft_Gpu_Hal_Sleep(10);
dreschpe 0:5e013296b353 50
dreschpe 0:5e013296b353 51 /* Do a core reset for safer side */
dreschpe 0:5e013296b353 52 Ft_Gpu_HostCommand( FT_GPU_CORE_RESET);
dreschpe 0:5e013296b353 53
dreschpe 0:5e013296b353 54 //Read Register ID to check if FT800 is ready.
dreschpe 0:5e013296b353 55 chipid = Ft_Gpu_Hal_Rd8( REG_ID);
dreschpe 0:5e013296b353 56 while(chipid != 0x7C)
dreschpe 0:5e013296b353 57 chipid = Ft_Gpu_Hal_Rd8( REG_ID);
dreschpe 0:5e013296b353 58
dreschpe 0:5e013296b353 59
dreschpe 0:5e013296b353 60 // Speed up
dreschpe 0:5e013296b353 61 _spi.frequency(30000000); // 30 Mhz SPI clock
dreschpe 0:5e013296b353 62
dreschpe 0:5e013296b353 63 /* Configuration of LCD display */
dreschpe 0:5e013296b353 64 FT_DispHCycle = my_DispHCycle;
dreschpe 0:5e013296b353 65 Ft_Gpu_Hal_Wr16( REG_HCYCLE, FT_DispHCycle);
dreschpe 0:5e013296b353 66 FT_DispHOffset = my_DispHOffset;
dreschpe 0:5e013296b353 67 Ft_Gpu_Hal_Wr16( REG_HOFFSET, FT_DispHOffset);
dreschpe 0:5e013296b353 68 FT_DispWidth = my_DispWidth;
dreschpe 0:5e013296b353 69 Ft_Gpu_Hal_Wr16( REG_HSIZE, FT_DispWidth);
dreschpe 0:5e013296b353 70 FT_DispHSync0 = my_DispHSync0;
dreschpe 0:5e013296b353 71 Ft_Gpu_Hal_Wr16( REG_HSYNC0, FT_DispHSync0);
dreschpe 0:5e013296b353 72 FT_DispHSync1 = my_DispHSync1;
dreschpe 0:5e013296b353 73 Ft_Gpu_Hal_Wr16( REG_HSYNC1, FT_DispHSync1);
dreschpe 0:5e013296b353 74 FT_DispVCycle = my_DispVCycle;
dreschpe 0:5e013296b353 75 Ft_Gpu_Hal_Wr16( REG_VCYCLE, FT_DispVCycle);
dreschpe 0:5e013296b353 76 FT_DispVOffset = my_DispVOffset;
dreschpe 0:5e013296b353 77 Ft_Gpu_Hal_Wr16( REG_VOFFSET, FT_DispVOffset);
dreschpe 0:5e013296b353 78 FT_DispHeight = my_DispHeight;
dreschpe 0:5e013296b353 79 Ft_Gpu_Hal_Wr16( REG_VSIZE, FT_DispHeight);
dreschpe 0:5e013296b353 80 FT_DispVSync0 = my_DispVSync0;
dreschpe 0:5e013296b353 81 Ft_Gpu_Hal_Wr16( REG_VSYNC0, FT_DispVSync0);
dreschpe 0:5e013296b353 82 FT_DispVSync1 = my_DispVSync1;
dreschpe 0:5e013296b353 83 Ft_Gpu_Hal_Wr16( REG_VSYNC1, FT_DispVSync1);
dreschpe 0:5e013296b353 84 FT_DispSwizzle = my_DispSwizzle;
dreschpe 0:5e013296b353 85 //Ft_Gpu_Hal_Wr8( REG_SWIZZLE, FT_DispSwizzle);
dreschpe 0:5e013296b353 86 FT_DispPCLKPol = my_DispPCLKPol;
dreschpe 0:5e013296b353 87 //Ft_Gpu_Hal_Wr8( REG_PCLK_POL, FT_DispPCLKPol);
dreschpe 0:5e013296b353 88 FT_DispPCLK = my_DispPCLK;
dreschpe 0:5e013296b353 89 //Ft_Gpu_Hal_Wr8( REG_PCLK,FT_DispPCLK);//after this display is visible on the LCD
dreschpe 0:5e013296b353 90
dreschpe 0:5e013296b353 91 Ft_Gpu_Hal_Wr16( REG_PWM_HZ, 1000);
dreschpe 0:5e013296b353 92
dreschpe 0:5e013296b353 93 #ifdef Inv_Backlite
dreschpe 0:5e013296b353 94 Ft_Gpu_Hal_Wr16( REG_PWM_DUTY, 0);
dreschpe 0:5e013296b353 95 #else
dreschpe 0:5e013296b353 96 Ft_Gpu_Hal_Wr16( REG_PWM_DUTY, 100);
dreschpe 0:5e013296b353 97 #endif
dreschpe 0:5e013296b353 98
dreschpe 0:5e013296b353 99 Ft_Gpu_Hal_Wr8( REG_GPIO_DIR,0x80); //| Ft_Gpu_Hal_Rd8( REG_GPIO_DIR));
dreschpe 0:5e013296b353 100 Ft_Gpu_Hal_Wr8( REG_GPIO,0x080); //| Ft_Gpu_Hal_Rd8( REG_GPIO));
dreschpe 0:5e013296b353 101
dreschpe 0:5e013296b353 102 Ft_Gpu_Hal_Wr32( RAM_DL, CLEAR(1,1,1));
dreschpe 0:5e013296b353 103 Ft_Gpu_Hal_Wr32( RAM_DL+4, DISPLAY());
dreschpe 0:5e013296b353 104 Ft_Gpu_Hal_Wr32( REG_DLSWAP,1);
dreschpe 0:5e013296b353 105
dreschpe 0:5e013296b353 106 Ft_Gpu_Hal_Wr16( REG_PCLK, FT_DispPCLK);
dreschpe 0:5e013296b353 107
dreschpe 0:5e013296b353 108 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
dreschpe 0:5e013296b353 109 Ft_Gpu_Hal_Wr16( REG_TOUCH_RZTHRESH,1200);
dreschpe 0:5e013296b353 110
dreschpe 0:5e013296b353 111 }
dreschpe 0:5e013296b353 112
dreschpe 0:5e013296b353 113
dreschpe 0:5e013296b353 114
dreschpe 0:5e013296b353 115 /* API to initialize the SPI interface */
dreschpe 0:5e013296b353 116 ft_bool_t FT800::Ft_Gpu_Hal_Init()
dreschpe 0:5e013296b353 117 {
dreschpe 0:5e013296b353 118 // is done in constructor
dreschpe 0:5e013296b353 119 return 1;
dreschpe 0:5e013296b353 120 }
dreschpe 0:5e013296b353 121
dreschpe 0:5e013296b353 122
dreschpe 0:5e013296b353 123 ft_bool_t FT800::Ft_Gpu_Hal_Open()
dreschpe 0:5e013296b353 124 {
dreschpe 0:5e013296b353 125 ft_cmd_fifo_wp = ft_dl_buff_wp = 0;
dreschpe 0:5e013296b353 126 status = FT_GPU_HAL_OPENED;
dreschpe 0:5e013296b353 127 return 1;
dreschpe 0:5e013296b353 128 }
dreschpe 0:5e013296b353 129
dreschpe 0:5e013296b353 130 ft_void_t FT800::Ft_Gpu_Hal_Close( )
dreschpe 0:5e013296b353 131 {
dreschpe 0:5e013296b353 132 status = FT_GPU_HAL_CLOSED;
dreschpe 0:5e013296b353 133 }
dreschpe 0:5e013296b353 134
dreschpe 0:5e013296b353 135 ft_void_t FT800::Ft_Gpu_Hal_DeInit()
dreschpe 0:5e013296b353 136 {
dreschpe 0:5e013296b353 137
dreschpe 0:5e013296b353 138 }
dreschpe 0:5e013296b353 139
dreschpe 0:5e013296b353 140 /*The APIs for reading/writing transfer continuously only with small buffer system*/
dreschpe 0:5e013296b353 141 ft_void_t FT800::Ft_Gpu_Hal_StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
dreschpe 0:5e013296b353 142 {
dreschpe 0:5e013296b353 143 if (FT_GPU_READ == rw){
dreschpe 0:5e013296b353 144 _ss = 0; // cs low
dreschpe 0:5e013296b353 145 _spi.write(addr >> 16);
dreschpe 0:5e013296b353 146 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 147 _spi.write(addr & 0xff);
dreschpe 0:5e013296b353 148 _spi.write(0); //Dummy Read Byte
dreschpe 0:5e013296b353 149 status = FT_GPU_HAL_READING;
dreschpe 0:5e013296b353 150 }else{
dreschpe 0:5e013296b353 151 _ss = 0; // cs low
dreschpe 0:5e013296b353 152 _spi.write(0x80 | (addr >> 16));
dreschpe 0:5e013296b353 153 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 154 _spi.write(addr & 0xff);
dreschpe 0:5e013296b353 155 status = FT_GPU_HAL_WRITING;
dreschpe 0:5e013296b353 156 }
dreschpe 0:5e013296b353 157 }
dreschpe 0:5e013296b353 158
dreschpe 0:5e013296b353 159
dreschpe 0:5e013296b353 160 /*The APIs for writing transfer continuously only*/
dreschpe 0:5e013296b353 161 ft_void_t FT800::Ft_Gpu_Hal_StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
dreschpe 0:5e013296b353 162 {
dreschpe 0:5e013296b353 163 Ft_Gpu_Hal_StartTransfer( rw, ft_cmd_fifo_wp + RAM_CMD);
dreschpe 0:5e013296b353 164 }
dreschpe 0:5e013296b353 165
dreschpe 0:5e013296b353 166 ft_uint8_t FT800::Ft_Gpu_Hal_TransferString( const ft_char8_t *string)
dreschpe 0:5e013296b353 167 {
dreschpe 0:5e013296b353 168 ft_uint16_t length = strlen(string);
dreschpe 0:5e013296b353 169 while(length --){
dreschpe 0:5e013296b353 170 Ft_Gpu_Hal_Transfer8( *string);
dreschpe 0:5e013296b353 171 string ++;
dreschpe 0:5e013296b353 172 }
dreschpe 0:5e013296b353 173 //Append one null as ending flag
dreschpe 0:5e013296b353 174 Ft_Gpu_Hal_Transfer8( 0);
dreschpe 0:5e013296b353 175 }
dreschpe 0:5e013296b353 176
dreschpe 0:5e013296b353 177
dreschpe 0:5e013296b353 178 ft_uint8_t FT800::Ft_Gpu_Hal_Transfer8( ft_uint8_t value)
dreschpe 0:5e013296b353 179 {
dreschpe 0:5e013296b353 180 return _spi.write(value);
dreschpe 0:5e013296b353 181 }
dreschpe 0:5e013296b353 182
dreschpe 0:5e013296b353 183
dreschpe 0:5e013296b353 184 ft_uint16_t FT800::Ft_Gpu_Hal_Transfer16( ft_uint16_t value)
dreschpe 0:5e013296b353 185 {
dreschpe 0:5e013296b353 186 ft_uint16_t retVal = 0;
dreschpe 0:5e013296b353 187
dreschpe 0:5e013296b353 188 if (status == FT_GPU_HAL_WRITING){
dreschpe 0:5e013296b353 189 Ft_Gpu_Hal_Transfer8( value & 0xFF);//LSB first
dreschpe 0:5e013296b353 190 Ft_Gpu_Hal_Transfer8( (value >> 8) & 0xFF);
dreschpe 0:5e013296b353 191 }else{
dreschpe 0:5e013296b353 192 retVal = Ft_Gpu_Hal_Transfer8( 0);
dreschpe 0:5e013296b353 193 retVal |= (ft_uint16_t)Ft_Gpu_Hal_Transfer8( 0) << 8;
dreschpe 0:5e013296b353 194 }
dreschpe 0:5e013296b353 195
dreschpe 0:5e013296b353 196 return retVal;
dreschpe 0:5e013296b353 197 }
dreschpe 0:5e013296b353 198
dreschpe 0:5e013296b353 199 ft_uint32_t FT800::Ft_Gpu_Hal_Transfer32( ft_uint32_t value)
dreschpe 0:5e013296b353 200 {
dreschpe 0:5e013296b353 201 ft_uint32_t retVal = 0;
dreschpe 0:5e013296b353 202 if (status == FT_GPU_HAL_WRITING){
dreschpe 0:5e013296b353 203 Ft_Gpu_Hal_Transfer16( value & 0xFFFF);//LSB first
dreschpe 0:5e013296b353 204 Ft_Gpu_Hal_Transfer16( (value >> 16) & 0xFFFF);
dreschpe 0:5e013296b353 205 }else{
dreschpe 0:5e013296b353 206 retVal = Ft_Gpu_Hal_Transfer16( 0);
dreschpe 0:5e013296b353 207 retVal |= (ft_uint32_t)Ft_Gpu_Hal_Transfer16( 0) << 16;
dreschpe 0:5e013296b353 208 }
dreschpe 0:5e013296b353 209 return retVal;
dreschpe 0:5e013296b353 210 }
dreschpe 0:5e013296b353 211
dreschpe 0:5e013296b353 212 ft_void_t FT800::Ft_Gpu_Hal_EndTransfer( )
dreschpe 0:5e013296b353 213 {
dreschpe 0:5e013296b353 214 _ss = 1;
dreschpe 0:5e013296b353 215 status = FT_GPU_HAL_OPENED;
dreschpe 0:5e013296b353 216 }
dreschpe 0:5e013296b353 217
dreschpe 0:5e013296b353 218
dreschpe 0:5e013296b353 219 ft_uint8_t FT800::Ft_Gpu_Hal_Rd8( ft_uint32_t addr)
dreschpe 0:5e013296b353 220 {
dreschpe 0:5e013296b353 221 ft_uint8_t value;
dreschpe 0:5e013296b353 222 Ft_Gpu_Hal_StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 223 value = Ft_Gpu_Hal_Transfer8( 0);
dreschpe 0:5e013296b353 224 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 225 return value;
dreschpe 0:5e013296b353 226 }
dreschpe 0:5e013296b353 227 ft_uint16_t FT800::Ft_Gpu_Hal_Rd16( ft_uint32_t addr)
dreschpe 0:5e013296b353 228 {
dreschpe 0:5e013296b353 229 ft_uint16_t value;
dreschpe 0:5e013296b353 230 Ft_Gpu_Hal_StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 231 value = Ft_Gpu_Hal_Transfer16( 0);
dreschpe 0:5e013296b353 232 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 233 return value;
dreschpe 0:5e013296b353 234 }
dreschpe 0:5e013296b353 235 ft_uint32_t FT800::Ft_Gpu_Hal_Rd32( ft_uint32_t addr)
dreschpe 0:5e013296b353 236 {
dreschpe 0:5e013296b353 237 ft_uint32_t value;
dreschpe 0:5e013296b353 238 Ft_Gpu_Hal_StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 239 value = Ft_Gpu_Hal_Transfer32( 0);
dreschpe 0:5e013296b353 240 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 241 return value;
dreschpe 0:5e013296b353 242 }
dreschpe 0:5e013296b353 243
dreschpe 0:5e013296b353 244 ft_void_t FT800::Ft_Gpu_Hal_Wr8( ft_uint32_t addr, ft_uint8_t v)
dreschpe 0:5e013296b353 245 {
dreschpe 0:5e013296b353 246 Ft_Gpu_Hal_StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 247 Ft_Gpu_Hal_Transfer8( v);
dreschpe 0:5e013296b353 248 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 249 }
dreschpe 0:5e013296b353 250 ft_void_t FT800::Ft_Gpu_Hal_Wr16( ft_uint32_t addr, ft_uint16_t v)
dreschpe 0:5e013296b353 251 {
dreschpe 0:5e013296b353 252 Ft_Gpu_Hal_StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 253 Ft_Gpu_Hal_Transfer16( v);
dreschpe 0:5e013296b353 254 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 255 }
dreschpe 0:5e013296b353 256 ft_void_t FT800::Ft_Gpu_Hal_Wr32( ft_uint32_t addr, ft_uint32_t v)
dreschpe 0:5e013296b353 257 {
dreschpe 0:5e013296b353 258 Ft_Gpu_Hal_StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 259 Ft_Gpu_Hal_Transfer32( v);
dreschpe 0:5e013296b353 260 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 261 }
dreschpe 0:5e013296b353 262
dreschpe 0:5e013296b353 263 ft_void_t FT800::Ft_Gpu_HostCommand( ft_uint8_t cmd)
dreschpe 0:5e013296b353 264 {
dreschpe 0:5e013296b353 265 _ss = 0;
dreschpe 0:5e013296b353 266 _spi.write(cmd);
dreschpe 0:5e013296b353 267 _spi.write(0);
dreschpe 0:5e013296b353 268 _spi.write(0);
dreschpe 0:5e013296b353 269 _ss = 1;
dreschpe 0:5e013296b353 270 }
dreschpe 0:5e013296b353 271
dreschpe 0:5e013296b353 272 ft_void_t FT800::Ft_Gpu_ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
dreschpe 0:5e013296b353 273 {
dreschpe 0:5e013296b353 274 Ft_Gpu_HostCommand( pllsource);
dreschpe 0:5e013296b353 275 }
dreschpe 0:5e013296b353 276
dreschpe 0:5e013296b353 277 ft_void_t FT800::Ft_Gpu_PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
dreschpe 0:5e013296b353 278 {
dreschpe 0:5e013296b353 279 Ft_Gpu_HostCommand( freq);
dreschpe 0:5e013296b353 280 }
dreschpe 0:5e013296b353 281
dreschpe 0:5e013296b353 282 ft_void_t FT800::Ft_Gpu_PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
dreschpe 0:5e013296b353 283 {
dreschpe 0:5e013296b353 284 Ft_Gpu_HostCommand( pwrmode);
dreschpe 0:5e013296b353 285 }
dreschpe 0:5e013296b353 286
dreschpe 0:5e013296b353 287 ft_void_t FT800::Ft_Gpu_CoreReset( )
dreschpe 0:5e013296b353 288 {
dreschpe 0:5e013296b353 289 Ft_Gpu_HostCommand( 0x68);
dreschpe 0:5e013296b353 290 }
dreschpe 0:5e013296b353 291
dreschpe 0:5e013296b353 292
dreschpe 0:5e013296b353 293 ft_void_t FT800::Ft_Gpu_Hal_Updatecmdfifo( ft_uint16_t count)
dreschpe 0:5e013296b353 294 {
dreschpe 0:5e013296b353 295 ft_cmd_fifo_wp = ( ft_cmd_fifo_wp + count) & 4095;
dreschpe 0:5e013296b353 296 //4 byte alignment
dreschpe 0:5e013296b353 297 ft_cmd_fifo_wp = ( ft_cmd_fifo_wp + 3) & 0xffc;
dreschpe 0:5e013296b353 298 Ft_Gpu_Hal_Wr16( REG_CMD_WRITE, ft_cmd_fifo_wp);
dreschpe 0:5e013296b353 299 }
dreschpe 0:5e013296b353 300
dreschpe 0:5e013296b353 301
dreschpe 0:5e013296b353 302 ft_uint16_t FT800::Ft_Gpu_Cmdfifo_Freespace( )
dreschpe 0:5e013296b353 303 {
dreschpe 0:5e013296b353 304 ft_uint16_t fullness,retval;
dreschpe 0:5e013296b353 305
dreschpe 0:5e013296b353 306 fullness = ( ft_cmd_fifo_wp - Ft_Gpu_Hal_Rd16( REG_CMD_READ)) & 4095;
dreschpe 0:5e013296b353 307 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
dreschpe 0:5e013296b353 308 return (retval);
dreschpe 0:5e013296b353 309 }
dreschpe 0:5e013296b353 310
dreschpe 0:5e013296b353 311 ft_void_t FT800::Ft_Gpu_Hal_WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 312 {
dreschpe 0:5e013296b353 313 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 314
dreschpe 0:5e013296b353 315 #define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace( )
dreschpe 0:5e013296b353 316 do {
dreschpe 0:5e013296b353 317 length = count;
dreschpe 0:5e013296b353 318 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 319 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 320 }
dreschpe 0:5e013296b353 321 Ft_Gpu_Hal_CheckCmdBuffer( length);
dreschpe 0:5e013296b353 322
dreschpe 0:5e013296b353 323 Ft_Gpu_Hal_StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 324
dreschpe 0:5e013296b353 325 SizeTransfered = 0;
dreschpe 0:5e013296b353 326 while (length--) {
dreschpe 0:5e013296b353 327 Ft_Gpu_Hal_Transfer8( *buffer);
dreschpe 0:5e013296b353 328 buffer++;
dreschpe 0:5e013296b353 329 SizeTransfered ++;
dreschpe 0:5e013296b353 330 }
dreschpe 0:5e013296b353 331 length = SizeTransfered;
dreschpe 0:5e013296b353 332
dreschpe 0:5e013296b353 333 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 334 Ft_Gpu_Hal_Updatecmdfifo( length);
dreschpe 0:5e013296b353 335
dreschpe 0:5e013296b353 336 Ft_Gpu_Hal_WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 337
dreschpe 0:5e013296b353 338 count -= length;
dreschpe 0:5e013296b353 339 }while (count > 0);
dreschpe 0:5e013296b353 340 }
dreschpe 0:5e013296b353 341
dreschpe 0:5e013296b353 342
dreschpe 0:5e013296b353 343 ft_void_t FT800::Ft_Gpu_Hal_WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 344 {
dreschpe 0:5e013296b353 345 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 346
dreschpe 0:5e013296b353 347 #define MAX_CMD_FIFO_TRANSFER Ft_Gpu_Cmdfifo_Freespace( )
dreschpe 0:5e013296b353 348 do {
dreschpe 0:5e013296b353 349 length = count;
dreschpe 0:5e013296b353 350 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 351 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 352 }
dreschpe 0:5e013296b353 353 Ft_Gpu_Hal_CheckCmdBuffer( length);
dreschpe 0:5e013296b353 354
dreschpe 0:5e013296b353 355 Ft_Gpu_Hal_StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 356
dreschpe 0:5e013296b353 357
dreschpe 0:5e013296b353 358 SizeTransfered = 0;
dreschpe 0:5e013296b353 359 while (length--) {
dreschpe 0:5e013296b353 360 Ft_Gpu_Hal_Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 361 buffer++;
dreschpe 0:5e013296b353 362 SizeTransfered ++;
dreschpe 0:5e013296b353 363 }
dreschpe 0:5e013296b353 364 length = SizeTransfered;
dreschpe 0:5e013296b353 365
dreschpe 0:5e013296b353 366 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 367 Ft_Gpu_Hal_Updatecmdfifo( length);
dreschpe 0:5e013296b353 368
dreschpe 0:5e013296b353 369 Ft_Gpu_Hal_WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 370
dreschpe 0:5e013296b353 371 count -= length;
dreschpe 0:5e013296b353 372 }while (count > 0);
dreschpe 0:5e013296b353 373 }
dreschpe 0:5e013296b353 374
dreschpe 0:5e013296b353 375
dreschpe 0:5e013296b353 376 ft_void_t FT800::Ft_Gpu_Hal_CheckCmdBuffer( ft_uint16_t count)
dreschpe 0:5e013296b353 377 {
dreschpe 0:5e013296b353 378 ft_uint16_t getfreespace;
dreschpe 0:5e013296b353 379 do{
dreschpe 0:5e013296b353 380 getfreespace = Ft_Gpu_Cmdfifo_Freespace( );
dreschpe 0:5e013296b353 381 }while(getfreespace < count);
dreschpe 0:5e013296b353 382 }
dreschpe 0:5e013296b353 383
dreschpe 0:5e013296b353 384 ft_void_t FT800::Ft_Gpu_Hal_WaitCmdfifo_empty( )
dreschpe 0:5e013296b353 385 {
dreschpe 0:5e013296b353 386 while(Ft_Gpu_Hal_Rd16( REG_CMD_READ) != Ft_Gpu_Hal_Rd16( REG_CMD_WRITE));
dreschpe 0:5e013296b353 387
dreschpe 0:5e013296b353 388 ft_cmd_fifo_wp = Ft_Gpu_Hal_Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 389 }
dreschpe 0:5e013296b353 390
dreschpe 0:5e013296b353 391 ft_void_t FT800::Ft_Gpu_Hal_WaitLogo_Finish( )
dreschpe 0:5e013296b353 392 {
dreschpe 0:5e013296b353 393 ft_int16_t cmdrdptr,cmdwrptr;
dreschpe 0:5e013296b353 394
dreschpe 0:5e013296b353 395 do{
dreschpe 0:5e013296b353 396 cmdrdptr = Ft_Gpu_Hal_Rd16( REG_CMD_READ);
dreschpe 0:5e013296b353 397 cmdwrptr = Ft_Gpu_Hal_Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 398 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
dreschpe 0:5e013296b353 399 ft_cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 400 }
dreschpe 0:5e013296b353 401
dreschpe 0:5e013296b353 402
dreschpe 0:5e013296b353 403 ft_void_t FT800::Ft_Gpu_Hal_ResetCmdFifo( )
dreschpe 0:5e013296b353 404 {
dreschpe 0:5e013296b353 405 ft_cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 406 }
dreschpe 0:5e013296b353 407
dreschpe 0:5e013296b353 408
dreschpe 0:5e013296b353 409 ft_void_t FT800::Ft_Gpu_Hal_WrCmd32( ft_uint32_t cmd)
dreschpe 0:5e013296b353 410 {
dreschpe 0:5e013296b353 411 Ft_Gpu_Hal_CheckCmdBuffer( sizeof(cmd));
dreschpe 0:5e013296b353 412
dreschpe 0:5e013296b353 413 Ft_Gpu_Hal_Wr32( RAM_CMD + ft_cmd_fifo_wp,cmd);
dreschpe 0:5e013296b353 414
dreschpe 0:5e013296b353 415 Ft_Gpu_Hal_Updatecmdfifo( sizeof(cmd));
dreschpe 0:5e013296b353 416 }
dreschpe 0:5e013296b353 417
dreschpe 0:5e013296b353 418
dreschpe 0:5e013296b353 419 ft_void_t FT800::Ft_Gpu_Hal_ResetDLBuffer( )
dreschpe 0:5e013296b353 420 {
dreschpe 0:5e013296b353 421 ft_dl_buff_wp = 0;
dreschpe 0:5e013296b353 422 }
dreschpe 0:5e013296b353 423
dreschpe 0:5e013296b353 424 /* Toggle PD_N pin of FT800 board for a power cycle*/
dreschpe 0:5e013296b353 425 ft_void_t FT800::Ft_Gpu_Hal_Powercycle( ft_bool_t up)
dreschpe 0:5e013296b353 426 {
dreschpe 0:5e013296b353 427 if (up)
dreschpe 0:5e013296b353 428 {
dreschpe 0:5e013296b353 429 //Toggle PD_N from low to high for power up switch
dreschpe 0:5e013296b353 430 _pd = 0;
dreschpe 0:5e013296b353 431 Ft_Gpu_Hal_Sleep(20);
dreschpe 0:5e013296b353 432
dreschpe 0:5e013296b353 433 _pd = 1;
dreschpe 0:5e013296b353 434 Ft_Gpu_Hal_Sleep(20);
dreschpe 0:5e013296b353 435 }else
dreschpe 0:5e013296b353 436 {
dreschpe 0:5e013296b353 437 //Toggle PD_N from high to low for power down switch
dreschpe 0:5e013296b353 438 _pd = 1;
dreschpe 0:5e013296b353 439 Ft_Gpu_Hal_Sleep(20);
dreschpe 0:5e013296b353 440
dreschpe 0:5e013296b353 441 _pd = 0;
dreschpe 0:5e013296b353 442 Ft_Gpu_Hal_Sleep(20);
dreschpe 0:5e013296b353 443 }
dreschpe 0:5e013296b353 444 }
dreschpe 0:5e013296b353 445
dreschpe 0:5e013296b353 446 ft_void_t FT800::Ft_Gpu_Hal_WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 447 {
dreschpe 0:5e013296b353 448 ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 449
dreschpe 0:5e013296b353 450 Ft_Gpu_Hal_StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 451
dreschpe 0:5e013296b353 452 while (length--) {
dreschpe 0:5e013296b353 453 Ft_Gpu_Hal_Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 454 buffer++;
dreschpe 0:5e013296b353 455 }
dreschpe 0:5e013296b353 456
dreschpe 0:5e013296b353 457 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 458 }
dreschpe 0:5e013296b353 459
dreschpe 0:5e013296b353 460 ft_void_t FT800::Ft_Gpu_Hal_WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 461 {
dreschpe 0:5e013296b353 462 ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 463
dreschpe 0:5e013296b353 464 Ft_Gpu_Hal_StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 465
dreschpe 0:5e013296b353 466 while (length--) {
dreschpe 0:5e013296b353 467 Ft_Gpu_Hal_Transfer8( *buffer);
dreschpe 0:5e013296b353 468 buffer++;
dreschpe 0:5e013296b353 469 }
dreschpe 0:5e013296b353 470
dreschpe 0:5e013296b353 471 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 472 }
dreschpe 0:5e013296b353 473
dreschpe 0:5e013296b353 474
dreschpe 0:5e013296b353 475 ft_void_t FT800::Ft_Gpu_Hal_RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 476 {
dreschpe 0:5e013296b353 477 ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 478
dreschpe 0:5e013296b353 479 Ft_Gpu_Hal_StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 480
dreschpe 0:5e013296b353 481 while (length--) {
dreschpe 0:5e013296b353 482 *buffer = Ft_Gpu_Hal_Transfer8( 0);
dreschpe 0:5e013296b353 483 buffer++;
dreschpe 0:5e013296b353 484 }
dreschpe 0:5e013296b353 485
dreschpe 0:5e013296b353 486 Ft_Gpu_Hal_EndTransfer( );
dreschpe 0:5e013296b353 487 }
dreschpe 0:5e013296b353 488
dreschpe 0:5e013296b353 489 ft_int32_t FT800::Ft_Gpu_Hal_Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
dreschpe 0:5e013296b353 490 {
dreschpe 0:5e013296b353 491 ft_int16_t Length;
dreschpe 0:5e013296b353 492 ft_char8_t *pdst,charval;
dreschpe 0:5e013296b353 493 ft_int32_t CurrVal = value,tmpval,i;
dreschpe 0:5e013296b353 494 ft_char8_t tmparray[16],idx = 0;
dreschpe 0:5e013296b353 495
dreschpe 0:5e013296b353 496 Length = strlen(pSrc);
dreschpe 0:5e013296b353 497 pdst = pSrc + Length;
dreschpe 0:5e013296b353 498
dreschpe 0:5e013296b353 499 if(0 == value)
dreschpe 0:5e013296b353 500 {
dreschpe 0:5e013296b353 501 *pdst++ = '0';
dreschpe 0:5e013296b353 502 *pdst++ = '\0';
dreschpe 0:5e013296b353 503 return 0;
dreschpe 0:5e013296b353 504 }
dreschpe 0:5e013296b353 505
dreschpe 0:5e013296b353 506 if(CurrVal < 0)
dreschpe 0:5e013296b353 507 {
dreschpe 0:5e013296b353 508 *pdst++ = '-';
dreschpe 0:5e013296b353 509 CurrVal = - CurrVal;
dreschpe 0:5e013296b353 510 }
dreschpe 0:5e013296b353 511 /* insert the value */
dreschpe 0:5e013296b353 512 while(CurrVal > 0){
dreschpe 0:5e013296b353 513 tmpval = CurrVal;
dreschpe 0:5e013296b353 514 CurrVal /= 10;
dreschpe 0:5e013296b353 515 tmpval = tmpval - CurrVal*10;
dreschpe 0:5e013296b353 516 charval = '0' + tmpval;
dreschpe 0:5e013296b353 517 tmparray[idx++] = charval;
dreschpe 0:5e013296b353 518 }
dreschpe 0:5e013296b353 519
dreschpe 0:5e013296b353 520 for(i=0;i<idx;i++)
dreschpe 0:5e013296b353 521 {
dreschpe 0:5e013296b353 522 *pdst++ = tmparray[idx - i - 1];
dreschpe 0:5e013296b353 523 }
dreschpe 0:5e013296b353 524 *pdst++ = '\0';
dreschpe 0:5e013296b353 525
dreschpe 0:5e013296b353 526 return 0;
dreschpe 0:5e013296b353 527 }
dreschpe 0:5e013296b353 528
dreschpe 0:5e013296b353 529
dreschpe 0:5e013296b353 530 ft_void_t FT800::Ft_Gpu_Hal_Sleep(ft_uint16_t ms)
dreschpe 0:5e013296b353 531 {
dreschpe 0:5e013296b353 532 wait_ms(ms);
dreschpe 0:5e013296b353 533 }
dreschpe 0:5e013296b353 534
dreschpe 0:5e013296b353 535
dreschpe 0:5e013296b353 536
dreschpe 0:5e013296b353 537