Peter Drescher / FT800_2

Lib for FTDI FT800 graphic controller "EVE" The API is changed from the FTDI original names. It use smaller names now. DL() will add something to the display list instead of Ft_App_WrCoCmd_Buffer ... The FTDI programmer Guide is also using this commands.

Dependents:   FT800_RGB_demo FT800_RGB_demo2 FT800_demo_for_habr Temp_&_RH_at_TFT-demo ... more

Fork of FT800 by Peter Drescher

The mbed is talking thru the SPI interface with the graphic engine. We have to set up a list of Commands and send them to the FT800 to get graphics.

Hardware

1. VM800C development modules from FTDI : http://www.ftdichip.com/Products/Modules/VM800C.html

The modules come with different size lcd. 3.5", 4.3" or 5" or without. /media/uploads/dreschpe/ftdi_eve.jpg The picture shows a modified board, because my lcd had a different pinout. The mbed is connected to the pin header on the bottom.

2. EVBEVE-FT800 board from GLYN: http://www.glyn.com/News-Events/Newsletter/Newsletter-2013/October-2013/A-quick-start-for-EVE-Requires-no-basic-knowledge-graphics-sound-and-touch-can-all-be-learned-in-minutes

The module has a 40 pin flex cable connector to connect a display out of the EDT series.

/media/uploads/dreschpe/glyn_eve.jpg

The mbed is connected via the pin header on the left. If you use this board with a EDT display you have to uncomment the #define Inv_Backlite in FT_LCD_Type.h, because the backlight dimming is inverted.

3. ConnectEVE board from MikroElektronika http://www.mikroe.com/add-on-boards/display/connecteve/#headers_10 The board has also a pin header to connect the mbed. - not tested, but it looks like the other boards.

4. ADAM arduino shield http://www.4dsystems.com.au/product/4DLCD_FT843/ Component page : http://mbed.org/components/ADAM/

Works with the NUCLEO boards, but you have to patch three wires.

/media/uploads/dreschpe/adam.jpg

Connection

We need 5 signals to connect to the mbed. SCK, MOSI and MISO are connected to a SPI channel. SS is the chip select signal and PD work as powerdown. The additional INT signal is not used at the moment. It is possible to generate a interrupt signal, but at the moment you have to poll the status register of the FT800 to see if a command is finished.

Software

This lib is based on the demo code from FTDI. If you want to use it, you have to read the programming manual : http://www.ftdichip.com/Support/Documents/ProgramGuides/FT800%20Programmers%20Guide.pdf

See my demo : http://mbed.org/users/dreschpe/code/FT800_RGB_demo/

FT_Gpu_Hal.cpp@3:392d2c733c68, 2014-09-19 (annotated)

Committer:
dreschpe
Date:
Fri Sep 19 15:56:15 2014 +0000
Revision:
3:392d2c733c68
Parent:
2:ab74a9a05970
Child:
4:363ec27cdfaa
change function names !

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 2:ab74a9a05970 1 /* mbed Library for FTDI FT800 Enbedded Video Engine "EVE"
dreschpe 3:392d2c733c68 2 * based on Original Code Sample from FTDI
dreschpe 2:ab74a9a05970 3 * ported to mbed by Peter Drescher, DC2PD 2014
dreschpe 3:392d2c733c68 4 * Released under the MIT License: http://mbed.org/license/mit
dreschpe 3:392d2c733c68 5 * 19.09.14 changed to shorter function names
dreschpe 3:392d2c733c68 6 * FTDI was using very long names.
dreschpe 3:392d2c733c68 7 * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ... */
dreschpe 3:392d2c733c68 8
dreschpe 0:5e013296b353 9 #include "FT_Platform.h"
dreschpe 0:5e013296b353 10 #include "mbed.h"
dreschpe 0:5e013296b353 11 #include "FT_LCD_Type.h"
dreschpe 0:5e013296b353 12
dreschpe 0:5e013296b353 13 FT800::FT800(PinName mosi,
dreschpe 0:5e013296b353 14 PinName miso,
dreschpe 0:5e013296b353 15 PinName sck,
dreschpe 0:5e013296b353 16 PinName ss,
dreschpe 0:5e013296b353 17 PinName intr,
dreschpe 0:5e013296b353 18 PinName pd)
dreschpe 3:392d2c733c68 19 :
dreschpe 3:392d2c733c68 20 _spi(mosi, miso, sck),
dreschpe 0:5e013296b353 21 _ss(ss),
dreschpe 3:392d2c733c68 22 _pd(pd),
dreschpe 3:392d2c733c68 23 _f800_isr(InterruptIn(intr))
dreschpe 0:5e013296b353 24 {
dreschpe 0:5e013296b353 25 _spi.format(8,0); // 8 bit spi mode 0
dreschpe 3:392d2c733c68 26 _spi.frequency(4000000); // start with 10 Mhz SPI clock
dreschpe 0:5e013296b353 27 _ss = 1; // cs high
dreschpe 3:392d2c733c68 28 _pd = 1; // PD high
dreschpe 3:392d2c733c68 29 Bootup();
dreschpe 0:5e013296b353 30 }
dreschpe 0:5e013296b353 31
dreschpe 0:5e013296b353 32
dreschpe 0:5e013296b353 33 ft_bool_t FT800::Bootup(void){
dreschpe 3:392d2c733c68 34 Open();
dreschpe 0:5e013296b353 35 BootupConfig();
dreschpe 3:392d2c733c68 36
dreschpe 0:5e013296b353 37 return(1);
dreschpe 0:5e013296b353 38 }
dreschpe 3:392d2c733c68 39
dreschpe 0:5e013296b353 40
dreschpe 0:5e013296b353 41 ft_void_t FT800::BootupConfig(void){
dreschpe 0:5e013296b353 42 ft_uint8_t chipid;
dreschpe 0:5e013296b353 43 /* Do a power cycle for safer side */
dreschpe 3:392d2c733c68 44 Powercycle( FT_TRUE);
dreschpe 0:5e013296b353 45
dreschpe 0:5e013296b353 46 /* Access address 0 to wake up the FT800 */
dreschpe 3:392d2c733c68 47 HostCommand( FT_GPU_ACTIVE_M);
dreschpe 3:392d2c733c68 48 Sleep(20);
dreschpe 0:5e013296b353 49
dreschpe 0:5e013296b353 50 /* Set the clk to external clock */
dreschpe 3:392d2c733c68 51 HostCommand( FT_GPU_EXTERNAL_OSC);
dreschpe 3:392d2c733c68 52 Sleep(10);
dreschpe 3:392d2c733c68 53
dreschpe 0:5e013296b353 54
dreschpe 0:5e013296b353 55 /* Switch PLL output to 48MHz */
dreschpe 3:392d2c733c68 56 HostCommand( FT_GPU_PLL_48M);
dreschpe 3:392d2c733c68 57 Sleep(10);
dreschpe 0:5e013296b353 58
dreschpe 0:5e013296b353 59 /* Do a core reset for safer side */
dreschpe 3:392d2c733c68 60 HostCommand( FT_GPU_CORE_RESET);
dreschpe 0:5e013296b353 61
dreschpe 3:392d2c733c68 62 //Read Register ID to check if FT800 is ready.
dreschpe 3:392d2c733c68 63 chipid = Rd8( REG_ID);
dreschpe 0:5e013296b353 64 while(chipid != 0x7C)
dreschpe 3:392d2c733c68 65 chipid = Rd8( REG_ID);
dreschpe 3:392d2c733c68 66
dreschpe 0:5e013296b353 67
dreschpe 3:392d2c733c68 68 // Speed up
dreschpe 3:392d2c733c68 69 _spi.frequency(20000000); // 20 Mhz SPI clock
dreschpe 3:392d2c733c68 70
dreschpe 0:5e013296b353 71 /* Configuration of LCD display */
dreschpe 3:392d2c733c68 72 DispHCycle = my_DispHCycle;
dreschpe 3:392d2c733c68 73 Wr16( REG_HCYCLE, DispHCycle);
dreschpe 3:392d2c733c68 74 DispHOffset = my_DispHOffset;
dreschpe 3:392d2c733c68 75 Wr16( REG_HOFFSET, DispHOffset);
dreschpe 3:392d2c733c68 76 DispWidth = my_DispWidth;
dreschpe 3:392d2c733c68 77 Wr16( REG_HSIZE, DispWidth);
dreschpe 3:392d2c733c68 78 DispHSync0 = my_DispHSync0;
dreschpe 3:392d2c733c68 79 Wr16( REG_HSYNC0, DispHSync0);
dreschpe 3:392d2c733c68 80 DispHSync1 = my_DispHSync1;
dreschpe 3:392d2c733c68 81 Wr16( REG_HSYNC1, DispHSync1);
dreschpe 3:392d2c733c68 82 DispVCycle = my_DispVCycle;
dreschpe 3:392d2c733c68 83 Wr16( REG_VCYCLE, DispVCycle);
dreschpe 3:392d2c733c68 84 DispVOffset = my_DispVOffset;
dreschpe 3:392d2c733c68 85 Wr16( REG_VOFFSET, DispVOffset);
dreschpe 3:392d2c733c68 86 DispHeight = my_DispHeight;
dreschpe 3:392d2c733c68 87 Wr16( REG_VSIZE, DispHeight);
dreschpe 3:392d2c733c68 88 DispVSync0 = my_DispVSync0;
dreschpe 3:392d2c733c68 89 Wr16( REG_VSYNC0, DispVSync0);
dreschpe 3:392d2c733c68 90 DispVSync1 = my_DispVSync1;
dreschpe 3:392d2c733c68 91 Wr16( REG_VSYNC1, DispVSync1);
dreschpe 3:392d2c733c68 92 DispSwizzle = my_DispSwizzle;
dreschpe 3:392d2c733c68 93 //Wr8( REG_SWIZZLE, FT_DispSwizzle);
dreschpe 3:392d2c733c68 94 DispPCLKPol = my_DispPCLKPol;
dreschpe 3:392d2c733c68 95 //Wr8( REG_PCLK_POL, FT_DispPCLKPol);
dreschpe 3:392d2c733c68 96 DispPCLK = my_DispPCLK;
dreschpe 3:392d2c733c68 97 //Wr8( REG_PCLK,FT_DispPCLK);//after this display is visible on the LCD
dreschpe 0:5e013296b353 98
dreschpe 3:392d2c733c68 99 Wr16( REG_PWM_HZ, 1000);
dreschpe 3:392d2c733c68 100
dreschpe 3:392d2c733c68 101 #ifdef Inv_Backlite // turn on backlite
dreschpe 3:392d2c733c68 102 Wr16( REG_PWM_DUTY, 0);
dreschpe 0:5e013296b353 103 #else
dreschpe 3:392d2c733c68 104 Wr16( REG_PWM_DUTY, 100);
dreschpe 3:392d2c733c68 105 #endif
dreschpe 3:392d2c733c68 106
dreschpe 3:392d2c733c68 107 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
dreschpe 3:392d2c733c68 108 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
dreschpe 3:392d2c733c68 109
dreschpe 3:392d2c733c68 110 Wr32( RAM_DL, CLEAR(1,1,1));
dreschpe 3:392d2c733c68 111 Wr32( RAM_DL+4, DISPLAY());
dreschpe 3:392d2c733c68 112 Wr32( REG_DLSWAP,1);
dreschpe 3:392d2c733c68 113
dreschpe 3:392d2c733c68 114 Wr16( REG_PCLK, DispPCLK);
dreschpe 3:392d2c733c68 115
dreschpe 0:5e013296b353 116 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
dreschpe 3:392d2c733c68 117 Wr16( REG_TOUCH_RZTHRESH,1200);
dreschpe 0:5e013296b353 118
dreschpe 0:5e013296b353 119 }
dreschpe 0:5e013296b353 120
dreschpe 0:5e013296b353 121
dreschpe 0:5e013296b353 122
dreschpe 0:5e013296b353 123 /* API to initialize the SPI interface */
dreschpe 3:392d2c733c68 124 ft_bool_t FT800::Init()
dreschpe 0:5e013296b353 125 {
dreschpe 0:5e013296b353 126 // is done in constructor
dreschpe 0:5e013296b353 127 return 1;
dreschpe 0:5e013296b353 128 }
dreschpe 0:5e013296b353 129
dreschpe 0:5e013296b353 130
dreschpe 3:392d2c733c68 131 ft_bool_t FT800::Open()
dreschpe 0:5e013296b353 132 {
dreschpe 3:392d2c733c68 133 cmd_fifo_wp = dl_buff_wp = 0;
dreschpe 3:392d2c733c68 134 status = OPENED;
dreschpe 0:5e013296b353 135 return 1;
dreschpe 0:5e013296b353 136 }
dreschpe 0:5e013296b353 137
dreschpe 3:392d2c733c68 138 ft_void_t FT800::Close( )
dreschpe 0:5e013296b353 139 {
dreschpe 3:392d2c733c68 140 status = CLOSED;
dreschpe 0:5e013296b353 141 }
dreschpe 0:5e013296b353 142
dreschpe 3:392d2c733c68 143 ft_void_t FT800::DeInit()
dreschpe 0:5e013296b353 144 {
dreschpe 0:5e013296b353 145
dreschpe 0:5e013296b353 146 }
dreschpe 0:5e013296b353 147
dreschpe 0:5e013296b353 148 /*The APIs for reading/writing transfer continuously only with small buffer system*/
dreschpe 3:392d2c733c68 149 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
dreschpe 0:5e013296b353 150 {
dreschpe 0:5e013296b353 151 if (FT_GPU_READ == rw){
dreschpe 0:5e013296b353 152 _ss = 0; // cs low
dreschpe 0:5e013296b353 153 _spi.write(addr >> 16);
dreschpe 0:5e013296b353 154 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 155 _spi.write(addr & 0xff);
dreschpe 0:5e013296b353 156 _spi.write(0); //Dummy Read Byte
dreschpe 3:392d2c733c68 157 status = READING;
dreschpe 0:5e013296b353 158 }else{
dreschpe 0:5e013296b353 159 _ss = 0; // cs low
dreschpe 0:5e013296b353 160 _spi.write(0x80 | (addr >> 16));
dreschpe 0:5e013296b353 161 _spi.write(addr >> 8);
dreschpe 0:5e013296b353 162 _spi.write(addr & 0xff);
dreschpe 3:392d2c733c68 163 status = WRITING;
dreschpe 0:5e013296b353 164 }
dreschpe 0:5e013296b353 165 }
dreschpe 0:5e013296b353 166
dreschpe 0:5e013296b353 167
dreschpe 0:5e013296b353 168 /*The APIs for writing transfer continuously only*/
dreschpe 3:392d2c733c68 169 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
dreschpe 0:5e013296b353 170 {
dreschpe 3:392d2c733c68 171 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
dreschpe 0:5e013296b353 172 }
dreschpe 0:5e013296b353 173
dreschpe 3:392d2c733c68 174 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
dreschpe 0:5e013296b353 175 {
dreschpe 0:5e013296b353 176 ft_uint16_t length = strlen(string);
dreschpe 0:5e013296b353 177 while(length --){
dreschpe 3:392d2c733c68 178 Transfer8( *string);
dreschpe 0:5e013296b353 179 string ++;
dreschpe 0:5e013296b353 180 }
dreschpe 0:5e013296b353 181 //Append one null as ending flag
dreschpe 3:392d2c733c68 182 Transfer8( 0);
dreschpe 3:392d2c733c68 183 return(1);
dreschpe 0:5e013296b353 184 }
dreschpe 0:5e013296b353 185
dreschpe 0:5e013296b353 186
dreschpe 3:392d2c733c68 187 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
dreschpe 0:5e013296b353 188 {
dreschpe 3:392d2c733c68 189 return _spi.write(value);
dreschpe 0:5e013296b353 190 }
dreschpe 0:5e013296b353 191
dreschpe 0:5e013296b353 192
dreschpe 3:392d2c733c68 193 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
dreschpe 0:5e013296b353 194 {
dreschpe 0:5e013296b353 195 ft_uint16_t retVal = 0;
dreschpe 0:5e013296b353 196
dreschpe 3:392d2c733c68 197 if (status == WRITING){
dreschpe 3:392d2c733c68 198 Transfer8( value & 0xFF);//LSB first
dreschpe 3:392d2c733c68 199 Transfer8( (value >> 8) & 0xFF);
dreschpe 0:5e013296b353 200 }else{
dreschpe 3:392d2c733c68 201 retVal = Transfer8( 0);
dreschpe 3:392d2c733c68 202 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
dreschpe 0:5e013296b353 203 }
dreschpe 0:5e013296b353 204
dreschpe 0:5e013296b353 205 return retVal;
dreschpe 0:5e013296b353 206 }
dreschpe 0:5e013296b353 207
dreschpe 3:392d2c733c68 208 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
dreschpe 0:5e013296b353 209 {
dreschpe 0:5e013296b353 210 ft_uint32_t retVal = 0;
dreschpe 3:392d2c733c68 211 if (status == WRITING){
dreschpe 3:392d2c733c68 212 Transfer16( value & 0xFFFF);//LSB first
dreschpe 3:392d2c733c68 213 Transfer16( (value >> 16) & 0xFFFF);
dreschpe 0:5e013296b353 214 }else{
dreschpe 3:392d2c733c68 215 retVal = Transfer16( 0);
dreschpe 3:392d2c733c68 216 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
dreschpe 0:5e013296b353 217 }
dreschpe 0:5e013296b353 218 return retVal;
dreschpe 0:5e013296b353 219 }
dreschpe 0:5e013296b353 220
dreschpe 3:392d2c733c68 221 ft_void_t FT800::EndTransfer( )
dreschpe 0:5e013296b353 222 {
dreschpe 3:392d2c733c68 223 _ss = 1;
dreschpe 3:392d2c733c68 224 status = OPENED;
dreschpe 0:5e013296b353 225 }
dreschpe 0:5e013296b353 226
dreschpe 0:5e013296b353 227
dreschpe 3:392d2c733c68 228 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
dreschpe 0:5e013296b353 229 {
dreschpe 0:5e013296b353 230 ft_uint8_t value;
dreschpe 3:392d2c733c68 231 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 232 value = Transfer8( 0);
dreschpe 3:392d2c733c68 233 EndTransfer( );
dreschpe 0:5e013296b353 234 return value;
dreschpe 0:5e013296b353 235 }
dreschpe 3:392d2c733c68 236 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
dreschpe 0:5e013296b353 237 {
dreschpe 0:5e013296b353 238 ft_uint16_t value;
dreschpe 3:392d2c733c68 239 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 240 value = Transfer16( 0);
dreschpe 3:392d2c733c68 241 EndTransfer( );
dreschpe 0:5e013296b353 242 return value;
dreschpe 0:5e013296b353 243 }
dreschpe 3:392d2c733c68 244 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
dreschpe 0:5e013296b353 245 {
dreschpe 0:5e013296b353 246 ft_uint32_t value;
dreschpe 3:392d2c733c68 247 StartTransfer( FT_GPU_READ,addr);
dreschpe 3:392d2c733c68 248 value = Transfer32( 0);
dreschpe 3:392d2c733c68 249 EndTransfer( );
dreschpe 0:5e013296b353 250 return value;
dreschpe 0:5e013296b353 251 }
dreschpe 0:5e013296b353 252
dreschpe 3:392d2c733c68 253 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
dreschpe 3:392d2c733c68 254 {
dreschpe 3:392d2c733c68 255 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 256 Transfer8( v);
dreschpe 3:392d2c733c68 257 EndTransfer( );
dreschpe 0:5e013296b353 258 }
dreschpe 3:392d2c733c68 259 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
dreschpe 0:5e013296b353 260 {
dreschpe 3:392d2c733c68 261 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 262 Transfer16( v);
dreschpe 3:392d2c733c68 263 EndTransfer( );
dreschpe 0:5e013296b353 264 }
dreschpe 3:392d2c733c68 265 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
dreschpe 0:5e013296b353 266 {
dreschpe 3:392d2c733c68 267 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 3:392d2c733c68 268 Transfer32( v);
dreschpe 3:392d2c733c68 269 EndTransfer( );
dreschpe 0:5e013296b353 270 }
dreschpe 0:5e013296b353 271
dreschpe 3:392d2c733c68 272 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
dreschpe 0:5e013296b353 273 {
dreschpe 0:5e013296b353 274 _ss = 0;
dreschpe 0:5e013296b353 275 _spi.write(cmd);
dreschpe 0:5e013296b353 276 _spi.write(0);
dreschpe 0:5e013296b353 277 _spi.write(0);
dreschpe 0:5e013296b353 278 _ss = 1;
dreschpe 0:5e013296b353 279 }
dreschpe 0:5e013296b353 280
dreschpe 3:392d2c733c68 281 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
dreschpe 0:5e013296b353 282 {
dreschpe 3:392d2c733c68 283 HostCommand( pllsource);
dreschpe 0:5e013296b353 284 }
dreschpe 0:5e013296b353 285
dreschpe 3:392d2c733c68 286 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
dreschpe 0:5e013296b353 287 {
dreschpe 3:392d2c733c68 288 HostCommand( freq);
dreschpe 0:5e013296b353 289 }
dreschpe 0:5e013296b353 290
dreschpe 3:392d2c733c68 291 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
dreschpe 0:5e013296b353 292 {
dreschpe 3:392d2c733c68 293 HostCommand( pwrmode);
dreschpe 0:5e013296b353 294 }
dreschpe 0:5e013296b353 295
dreschpe 3:392d2c733c68 296 ft_void_t FT800::CoreReset( )
dreschpe 0:5e013296b353 297 {
dreschpe 3:392d2c733c68 298 HostCommand( 0x68);
dreschpe 0:5e013296b353 299 }
dreschpe 0:5e013296b353 300
dreschpe 0:5e013296b353 301
dreschpe 3:392d2c733c68 302 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
dreschpe 0:5e013296b353 303 {
dreschpe 3:392d2c733c68 304 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
dreschpe 0:5e013296b353 305 //4 byte alignment
dreschpe 3:392d2c733c68 306 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
dreschpe 3:392d2c733c68 307 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
dreschpe 0:5e013296b353 308 }
dreschpe 0:5e013296b353 309
dreschpe 0:5e013296b353 310
dreschpe 3:392d2c733c68 311 ft_uint16_t FT800::fifo_Freespace( )
dreschpe 0:5e013296b353 312 {
dreschpe 0:5e013296b353 313 ft_uint16_t fullness,retval;
dreschpe 0:5e013296b353 314
dreschpe 3:392d2c733c68 315 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
dreschpe 0:5e013296b353 316 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
dreschpe 0:5e013296b353 317 return (retval);
dreschpe 0:5e013296b353 318 }
dreschpe 0:5e013296b353 319
dreschpe 3:392d2c733c68 320 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 321 {
dreschpe 3:392d2c733c68 322 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 323
dreschpe 3:392d2c733c68 324 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 325 do {
dreschpe 0:5e013296b353 326 length = count;
dreschpe 0:5e013296b353 327 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 328 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 329 }
dreschpe 3:392d2c733c68 330 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 331
dreschpe 3:392d2c733c68 332 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 333
dreschpe 0:5e013296b353 334 SizeTransfered = 0;
dreschpe 0:5e013296b353 335 while (length--) {
dreschpe 3:392d2c733c68 336 Transfer8( *buffer);
dreschpe 0:5e013296b353 337 buffer++;
dreschpe 0:5e013296b353 338 SizeTransfered ++;
dreschpe 0:5e013296b353 339 }
dreschpe 0:5e013296b353 340 length = SizeTransfered;
dreschpe 0:5e013296b353 341
dreschpe 3:392d2c733c68 342 EndTransfer( );
dreschpe 3:392d2c733c68 343 Updatecmdfifo( length);
dreschpe 0:5e013296b353 344
dreschpe 3:392d2c733c68 345 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 346
dreschpe 0:5e013296b353 347 count -= length;
dreschpe 0:5e013296b353 348 }while (count > 0);
dreschpe 0:5e013296b353 349 }
dreschpe 0:5e013296b353 350
dreschpe 0:5e013296b353 351
dreschpe 3:392d2c733c68 352 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
dreschpe 0:5e013296b353 353 {
dreschpe 3:392d2c733c68 354 ft_uint32_t length =0, SizeTransfered = 0;
dreschpe 0:5e013296b353 355
dreschpe 3:392d2c733c68 356 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
dreschpe 3:392d2c733c68 357 do {
dreschpe 0:5e013296b353 358 length = count;
dreschpe 0:5e013296b353 359 if (length > MAX_CMD_FIFO_TRANSFER){
dreschpe 0:5e013296b353 360 length = MAX_CMD_FIFO_TRANSFER;
dreschpe 0:5e013296b353 361 }
dreschpe 3:392d2c733c68 362 CheckCmdBuffer( length);
dreschpe 0:5e013296b353 363
dreschpe 3:392d2c733c68 364 StartCmdTransfer( FT_GPU_WRITE,length);
dreschpe 0:5e013296b353 365
dreschpe 0:5e013296b353 366
dreschpe 0:5e013296b353 367 SizeTransfered = 0;
dreschpe 0:5e013296b353 368 while (length--) {
dreschpe 3:392d2c733c68 369 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 370 buffer++;
dreschpe 0:5e013296b353 371 SizeTransfered ++;
dreschpe 0:5e013296b353 372 }
dreschpe 0:5e013296b353 373 length = SizeTransfered;
dreschpe 0:5e013296b353 374
dreschpe 3:392d2c733c68 375 EndTransfer( );
dreschpe 3:392d2c733c68 376 Updatecmdfifo( length);
dreschpe 0:5e013296b353 377
dreschpe 3:392d2c733c68 378 WaitCmdfifo_empty( );
dreschpe 0:5e013296b353 379
dreschpe 0:5e013296b353 380 count -= length;
dreschpe 0:5e013296b353 381 }while (count > 0);
dreschpe 0:5e013296b353 382 }
dreschpe 0:5e013296b353 383
dreschpe 0:5e013296b353 384
dreschpe 3:392d2c733c68 385 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
dreschpe 0:5e013296b353 386 {
dreschpe 0:5e013296b353 387 ft_uint16_t getfreespace;
dreschpe 0:5e013296b353 388 do{
dreschpe 3:392d2c733c68 389 getfreespace = fifo_Freespace( );
dreschpe 0:5e013296b353 390 }while(getfreespace < count);
dreschpe 0:5e013296b353 391 }
dreschpe 0:5e013296b353 392
dreschpe 3:392d2c733c68 393 ft_void_t FT800::WaitCmdfifo_empty( )
dreschpe 0:5e013296b353 394 {
dreschpe 3:392d2c733c68 395 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
dreschpe 3:392d2c733c68 396
dreschpe 3:392d2c733c68 397 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 398 }
dreschpe 0:5e013296b353 399
dreschpe 3:392d2c733c68 400 ft_void_t FT800::WaitLogo_Finish( )
dreschpe 0:5e013296b353 401 {
dreschpe 0:5e013296b353 402 ft_int16_t cmdrdptr,cmdwrptr;
dreschpe 0:5e013296b353 403
dreschpe 0:5e013296b353 404 do{
dreschpe 3:392d2c733c68 405 cmdrdptr = Rd16( REG_CMD_READ);
dreschpe 3:392d2c733c68 406 cmdwrptr = Rd16( REG_CMD_WRITE);
dreschpe 0:5e013296b353 407 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
dreschpe 3:392d2c733c68 408 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 409 }
dreschpe 0:5e013296b353 410
dreschpe 0:5e013296b353 411
dreschpe 3:392d2c733c68 412 ft_void_t FT800::ResetCmdFifo( )
dreschpe 0:5e013296b353 413 {
dreschpe 3:392d2c733c68 414 cmd_fifo_wp = 0;
dreschpe 0:5e013296b353 415 }
dreschpe 0:5e013296b353 416
dreschpe 0:5e013296b353 417
dreschpe 3:392d2c733c68 418 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
dreschpe 0:5e013296b353 419 {
dreschpe 3:392d2c733c68 420 CheckCmdBuffer( sizeof(cmd));
dreschpe 3:392d2c733c68 421
dreschpe 3:392d2c733c68 422 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
dreschpe 3:392d2c733c68 423
dreschpe 3:392d2c733c68 424 Updatecmdfifo( sizeof(cmd));
dreschpe 0:5e013296b353 425 }
dreschpe 0:5e013296b353 426
dreschpe 0:5e013296b353 427
dreschpe 3:392d2c733c68 428 ft_void_t FT800::ResetDLBuffer( )
dreschpe 0:5e013296b353 429 {
dreschpe 3:392d2c733c68 430 dl_buff_wp = 0;
dreschpe 0:5e013296b353 431 }
dreschpe 0:5e013296b353 432
dreschpe 0:5e013296b353 433 /* Toggle PD_N pin of FT800 board for a power cycle*/
dreschpe 3:392d2c733c68 434 ft_void_t FT800::Powercycle( ft_bool_t up)
dreschpe 0:5e013296b353 435 {
dreschpe 0:5e013296b353 436 if (up)
dreschpe 0:5e013296b353 437 {
dreschpe 3:392d2c733c68 438 //Toggle PD_N from low to high for power up switch
dreschpe 3:392d2c733c68 439 _pd = 0;
dreschpe 3:392d2c733c68 440 Sleep(20);
dreschpe 0:5e013296b353 441
dreschpe 0:5e013296b353 442 _pd = 1;
dreschpe 3:392d2c733c68 443 Sleep(20);
dreschpe 0:5e013296b353 444 }else
dreschpe 0:5e013296b353 445 {
dreschpe 0:5e013296b353 446 //Toggle PD_N from high to low for power down switch
dreschpe 0:5e013296b353 447 _pd = 1;
dreschpe 3:392d2c733c68 448 Sleep(20);
dreschpe 3:392d2c733c68 449
dreschpe 0:5e013296b353 450 _pd = 0;
dreschpe 3:392d2c733c68 451 Sleep(20);
dreschpe 0:5e013296b353 452 }
dreschpe 0:5e013296b353 453 }
dreschpe 0:5e013296b353 454
dreschpe 3:392d2c733c68 455 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 456 {
dreschpe 3:392d2c733c68 457 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 458
dreschpe 3:392d2c733c68 459 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 460
dreschpe 0:5e013296b353 461 while (length--) {
dreschpe 3:392d2c733c68 462 Transfer8( ft_pgm_read_byte_near(buffer));
dreschpe 0:5e013296b353 463 buffer++;
dreschpe 0:5e013296b353 464 }
dreschpe 0:5e013296b353 465
dreschpe 3:392d2c733c68 466 EndTransfer( );
dreschpe 0:5e013296b353 467 }
dreschpe 0:5e013296b353 468
dreschpe 3:392d2c733c68 469 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 470 {
dreschpe 3:392d2c733c68 471 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 472
dreschpe 3:392d2c733c68 473 StartTransfer( FT_GPU_WRITE,addr);
dreschpe 0:5e013296b353 474
dreschpe 0:5e013296b353 475 while (length--) {
dreschpe 3:392d2c733c68 476 Transfer8( *buffer);
dreschpe 0:5e013296b353 477 buffer++;
dreschpe 0:5e013296b353 478 }
dreschpe 0:5e013296b353 479
dreschpe 3:392d2c733c68 480 EndTransfer( );
dreschpe 0:5e013296b353 481 }
dreschpe 0:5e013296b353 482
dreschpe 0:5e013296b353 483
dreschpe 3:392d2c733c68 484 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
dreschpe 0:5e013296b353 485 {
dreschpe 3:392d2c733c68 486 //ft_uint32_t SizeTransfered = 0;
dreschpe 0:5e013296b353 487
dreschpe 3:392d2c733c68 488 StartTransfer( FT_GPU_READ,addr);
dreschpe 0:5e013296b353 489
dreschpe 0:5e013296b353 490 while (length--) {
dreschpe 3:392d2c733c68 491 *buffer = Transfer8( 0);
dreschpe 0:5e013296b353 492 buffer++;
dreschpe 0:5e013296b353 493 }
dreschpe 0:5e013296b353 494
dreschpe 3:392d2c733c68 495 EndTransfer( );
dreschpe 0:5e013296b353 496 }
dreschpe 0:5e013296b353 497
dreschpe 3:392d2c733c68 498 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
dreschpe 0:5e013296b353 499 {
dreschpe 0:5e013296b353 500 ft_int16_t Length;
dreschpe 0:5e013296b353 501 ft_char8_t *pdst,charval;
dreschpe 0:5e013296b353 502 ft_int32_t CurrVal = value,tmpval,i;
dreschpe 0:5e013296b353 503 ft_char8_t tmparray[16],idx = 0;
dreschpe 0:5e013296b353 504
dreschpe 0:5e013296b353 505 Length = strlen(pSrc);
dreschpe 0:5e013296b353 506 pdst = pSrc + Length;
dreschpe 0:5e013296b353 507
dreschpe 0:5e013296b353 508 if(0 == value)
dreschpe 0:5e013296b353 509 {
dreschpe 0:5e013296b353 510 *pdst++ = '0';
dreschpe 0:5e013296b353 511 *pdst++ = '\0';
dreschpe 0:5e013296b353 512 return 0;
dreschpe 0:5e013296b353 513 }
dreschpe 0:5e013296b353 514
dreschpe 0:5e013296b353 515 if(CurrVal < 0)
dreschpe 0:5e013296b353 516 {
dreschpe 0:5e013296b353 517 *pdst++ = '-';
dreschpe 0:5e013296b353 518 CurrVal = - CurrVal;
dreschpe 0:5e013296b353 519 }
dreschpe 0:5e013296b353 520 /* insert the value */
dreschpe 0:5e013296b353 521 while(CurrVal > 0){
dreschpe 0:5e013296b353 522 tmpval = CurrVal;
dreschpe 0:5e013296b353 523 CurrVal /= 10;
dreschpe 0:5e013296b353 524 tmpval = tmpval - CurrVal*10;
dreschpe 0:5e013296b353 525 charval = '0' + tmpval;
dreschpe 0:5e013296b353 526 tmparray[idx++] = charval;
dreschpe 0:5e013296b353 527 }
dreschpe 0:5e013296b353 528
dreschpe 0:5e013296b353 529 for(i=0;i<idx;i++)
dreschpe 0:5e013296b353 530 {
dreschpe 0:5e013296b353 531 *pdst++ = tmparray[idx - i - 1];
dreschpe 0:5e013296b353 532 }
dreschpe 0:5e013296b353 533 *pdst++ = '\0';
dreschpe 0:5e013296b353 534
dreschpe 0:5e013296b353 535 return 0;
dreschpe 0:5e013296b353 536 }
dreschpe 0:5e013296b353 537
dreschpe 0:5e013296b353 538
dreschpe 3:392d2c733c68 539 ft_void_t FT800::Sleep(ft_uint16_t ms)
dreschpe 0:5e013296b353 540 {
dreschpe 0:5e013296b353 541 wait_ms(ms);
dreschpe 0:5e013296b353 542 }
dreschpe 0:5e013296b353 543
dreschpe 3:392d2c733c68 544 ft_void_t FT800::Sound_ON(){
dreschpe 3:392d2c733c68 545 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 546 }
dreschpe 1:bd671a31e765 547
dreschpe 3:392d2c733c68 548 ft_void_t FT800::Sound_OFF(){
dreschpe 3:392d2c733c68 549 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
dreschpe 1:bd671a31e765 550 }
dreschpe 0:5e013296b353 551
dreschpe 0:5e013296b353 552
dreschpe 0:5e013296b353 553
dreschpe 1:bd671a31e765 554