Damien Frost / NRF2401P

My fork during debugging.

Fork of NRF2401P by Malcolm McCulloch

NRF2401P.cpp@19:f7e74aa7d663, 2016-04-15 (annotated)

Committer:
defrost
Date:
Fri Apr 15 11:16:36 2016 +0000
Revision:
19:f7e74aa7d663
Parent:
18:1e0a2fcc4e89 
- Added setPwrDown() function which turns off the NRF chip

Who changed what in which revision?

UserRevisionLine numberNew contents of line
epgmdm 0:8fd0531ae0be 1 /**
epgmdm 0:8fd0531ae0be 2 *@section DESCRIPTION
epgmdm 0:8fd0531ae0be 3 * mbed NRF2401+ Library
epgmdm 0:8fd0531ae0be 4 *@section LICENSE
epgmdm 0:8fd0531ae0be 5 * Copyright (c) 2015, Malcolm McCulloch
epgmdm 0:8fd0531ae0be 6 *
epgmdm 0:8fd0531ae0be 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
epgmdm 0:8fd0531ae0be 8 * of this software and associated documentation files (the "Software"), to deal
epgmdm 0:8fd0531ae0be 9 * in the Software without restriction, including without limitation the rights
epgmdm 0:8fd0531ae0be 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
epgmdm 0:8fd0531ae0be 11 * copies of the Software, and to permit persons to whom the Software is
epgmdm 0:8fd0531ae0be 12 * furnished to do so, subject to the following conditions:
epgmdm 0:8fd0531ae0be 13 *
epgmdm 0:8fd0531ae0be 14 * The above copyright notice and this permission notice shall be included in
epgmdm 0:8fd0531ae0be 15 * all copies or substantial portions of the Software.
epgmdm 0:8fd0531ae0be 16 *
epgmdm 0:8fd0531ae0be 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
epgmdm 0:8fd0531ae0be 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
epgmdm 0:8fd0531ae0be 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
epgmdm 0:8fd0531ae0be 20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
epgmdm 0:8fd0531ae0be 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
epgmdm 0:8fd0531ae0be 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
epgmdm 0:8fd0531ae0be 23 * THE SOFTWARE.
epgmdm 0:8fd0531ae0be 24 * @file "NRF2401P.cpp"
epgmdm 0:8fd0531ae0be 25 */
epgmdm 2:ca0a3c0bba70 26 #include "mbed.h"
epgmdm 2:ca0a3c0bba70 27 #include "NRF2401P.h"
epgmdm 2:ca0a3c0bba70 28 #include "nRF24l01.h"
epgmdm 0:8fd0531ae0be 29
epgmdm 0:8fd0531ae0be 30 NRF2401P::NRF2401P ( PinName mosi, PinName miso, PinName sclk, PinName _csn, PinName _ce ) :
epgmdm 16:a9b83d2b6915 31 csn( DigitalOut( _csn ) ), ce( DigitalOut( _ce ) )
epgmdm 0:8fd0531ae0be 32 {
epgmdm 0:8fd0531ae0be 33 addressWidth = 5;
epgmdm 0:8fd0531ae0be 34 pc = new Serial( USBTX, USBRX ); // tx, rx
nixonkj 6:77ead8abdd1c 35 if (debug) {
nixonkj 6:77ead8abdd1c 36 sprintf(logMsg, "Initialise" );
nixonkj 6:77ead8abdd1c 37 log(logMsg);
nixonkj 6:77ead8abdd1c 38 }
epgmdm 0:8fd0531ae0be 39 spi = new SPI( mosi, miso, sclk, NC ); //SPI (PinName mosi, PinName miso, PinName sclk, PinName _unused=NC)
defrost 18:1e0a2fcc4e89 40 spi->frequency( 10000000 ); // 1 MHz
epgmdm 0:8fd0531ae0be 41 spi->format( 8, 0 ); // 0: 0e 08; 1: 0e 00; 2:0e 00 ;3:1c 00
epgmdm 0:8fd0531ae0be 42 csn = 1;
epgmdm 0:8fd0531ae0be 43 ce = 0;
epgmdm 0:8fd0531ae0be 44 dynamic = false;
nixonkj 6:77ead8abdd1c 45 debug = false;
nixonkj 6:77ead8abdd1c 46 }
epgmdm 0:8fd0531ae0be 47
nixonkj 6:77ead8abdd1c 48 void NRF2401P::log(char *msg)
epgmdm 0:8fd0531ae0be 49 {
epgmdm 0:8fd0531ae0be 50 if(debug) {
nixonkj 8:3e027705ce23 51 printf("\t <%s \t %s>\n\r", statusString(), msg);
epgmdm 1:ff53b1ac3bad 52 wait(0.01);
nixonkj 6:77ead8abdd1c 53 }
epgmdm 0:8fd0531ae0be 54 }
epgmdm 0:8fd0531ae0be 55
epgmdm 0:8fd0531ae0be 56 void NRF2401P::scratch()
epgmdm 0:8fd0531ae0be 57 {
epgmdm 0:8fd0531ae0be 58 int status = 0;
epgmdm 0:8fd0531ae0be 59 int register1 = 0;
epgmdm 0:8fd0531ae0be 60 ce = 0;
epgmdm 0:8fd0531ae0be 61 for ( char i = 0; i < 24; i++ ) {
epgmdm 0:8fd0531ae0be 62 csn = 0;
epgmdm 0:8fd0531ae0be 63 //wait_us(100);
epgmdm 0:8fd0531ae0be 64 status = spi->write( i );
epgmdm 0:8fd0531ae0be 65 register1 = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 66 csn = 1;
epgmdm 0:8fd0531ae0be 67 sprintf(logMsg, " register %02x (%02x) = %02x", i, status, register1 );
epgmdm 0:8fd0531ae0be 68 log(logMsg);
epgmdm 0:8fd0531ae0be 69 }
nixonkj 6:77ead8abdd1c 70 }
epgmdm 0:8fd0531ae0be 71
epgmdm 0:8fd0531ae0be 72 /**
epgmdm 2:ca0a3c0bba70 73 * start here to configure the basics of the NRF
epgmdm 2:ca0a3c0bba70 74 */
epgmdm 2:ca0a3c0bba70 75 void NRF2401P::start()
epgmdm 2:ca0a3c0bba70 76 {
defrost 17:ea1484f5757f 77 //writeReg(CONFIG, 0); // turn off the module
nixonkj 8:3e027705ce23 78 writeReg(CONFIG, 0x0c); // set 16 bit crc
nixonkj 8:3e027705ce23 79 setTxRetry(0x01, 0x0f); // 500 uS, 15 retries
nixonkj 8:3e027705ce23 80 setRadio(0, 0x03); // 1MB/S 0dB
epgmdm 2:ca0a3c0bba70 81 setDynamicPayload();
epgmdm 2:ca0a3c0bba70 82 setChannel(76); // should be clear?
epgmdm 2:ca0a3c0bba70 83 setAddressWidth(5);
epgmdm 2:ca0a3c0bba70 84 flushRx();
epgmdm 2:ca0a3c0bba70 85 flushTx();
epgmdm 2:ca0a3c0bba70 86 setPwrUp();
epgmdm 2:ca0a3c0bba70 87 setTxMode(); // just make sure no spurious reads....
nixonkj 6:77ead8abdd1c 88 }
epgmdm 2:ca0a3c0bba70 89
epgmdm 2:ca0a3c0bba70 90 /**
epgmdm 16:a9b83d2b6915 91 * Sets up a receiver using shockburst and dynamic payload. Uses pipe 0
epgmdm 0:8fd0531ae0be 92 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 93 */
epgmdm 2:ca0a3c0bba70 94 void NRF2401P::quickRxSetup(int channel,long long addrRx)
epgmdm 0:8fd0531ae0be 95 {
epgmdm 2:ca0a3c0bba70 96 start();
epgmdm 0:8fd0531ae0be 97 setChannel(channel);
epgmdm 16:a9b83d2b6915 98 // setRxAddress(addrRx,1);
epgmdm 16:a9b83d2b6915 99 setRxAddress(addrRx,0);
epgmdm 0:8fd0531ae0be 100 setRxMode();
epgmdm 0:8fd0531ae0be 101 ce=1;
nixonkj 6:77ead8abdd1c 102 wait(0.001f);
epgmdm 16:a9b83d2b6915 103 writeReg(FEATURE,0x06); // Enable dynamic ack packets
epgmdm 0:8fd0531ae0be 104 }
nixonkj 6:77ead8abdd1c 105
epgmdm 0:8fd0531ae0be 106 /**
epgmdm 0:8fd0531ae0be 107 * Sets up for receive of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 108 */
epgmdm 0:8fd0531ae0be 109 char NRF2401P::testReceive()
epgmdm 0:8fd0531ae0be 110 {
epgmdm 0:8fd0531ae0be 111 char message[64];
epgmdm 0:8fd0531ae0be 112 char width;
epgmdm 0:8fd0531ae0be 113 int channel = 0x12;
epgmdm 0:8fd0531ae0be 114 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 115 debug = true;
epgmdm 0:8fd0531ae0be 116 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 117
epgmdm 0:8fd0531ae0be 118 while (1) {
epgmdm 0:8fd0531ae0be 119 while (!isRxData()) {
epgmdm 0:8fd0531ae0be 120 //wait(0.5);
epgmdm 0:8fd0531ae0be 121 };
epgmdm 0:8fd0531ae0be 122 width=getRxData(message);
epgmdm 0:8fd0531ae0be 123 message[width]='\0';
epgmdm 0:8fd0531ae0be 124 sprintf(logMsg,"Received= [%s]",message);
epgmdm 0:8fd0531ae0be 125 log(logMsg);
nixonkj 6:77ead8abdd1c 126 }
epgmdm 0:8fd0531ae0be 127 }
epgmdm 0:8fd0531ae0be 128
nixonkj 6:77ead8abdd1c 129 char NRF2401P::setTxRetry(char delay, char numTries)
epgmdm 2:ca0a3c0bba70 130 {
epgmdm 2:ca0a3c0bba70 131 char val = (delay&0xf)<<4 | (numTries&0xf);
nixonkj 6:77ead8abdd1c 132 char chk;
nixonkj 8:3e027705ce23 133 writeReg(SETUP_RETR, val);
nixonkj 8:3e027705ce23 134 readReg(SETUP_RETR, &chk);
nixonkj 6:77ead8abdd1c 135 if (chk&0xff == val) {
nixonkj 6:77ead8abdd1c 136 return 0;
nixonkj 6:77ead8abdd1c 137 } else {
nixonkj 6:77ead8abdd1c 138 return 1;
nixonkj 6:77ead8abdd1c 139 }
epgmdm 2:ca0a3c0bba70 140 }
epgmdm 2:ca0a3c0bba70 141
epgmdm 2:ca0a3c0bba70 142 /**
epgmdm 0:8fd0531ae0be 143 * Sets up a transmitter using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 144 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 145 */
epgmdm 0:8fd0531ae0be 146 void NRF2401P::quickTxSetup(int channel,long long addr)
epgmdm 0:8fd0531ae0be 147 {
epgmdm 2:ca0a3c0bba70 148 start();
epgmdm 0:8fd0531ae0be 149 setChannel(channel);
epgmdm 2:ca0a3c0bba70 150 setTxAddress(addr);
epgmdm 0:8fd0531ae0be 151 setTxMode();
epgmdm 16:a9b83d2b6915 152 writeReg(FEATURE,0x06);
epgmdm 0:8fd0531ae0be 153 ce=1;
epgmdm 0:8fd0531ae0be 154 wait (0.0016f); // wait for pll to settle
epgmdm 16:a9b83d2b6915 155 flushTx();
epgmdm 16:a9b83d2b6915 156 clearStatus();
epgmdm 0:8fd0531ae0be 157 }
epgmdm 0:8fd0531ae0be 158
epgmdm 0:8fd0531ae0be 159 /**
epgmdm 0:8fd0531ae0be 160 * Sets up for transmit of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 161 */
epgmdm 0:8fd0531ae0be 162 char NRF2401P::testTransmit()
epgmdm 0:8fd0531ae0be 163 {
epgmdm 0:8fd0531ae0be 164 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 165 int channel = 0x12;
epgmdm 0:8fd0531ae0be 166 char data[32] ;
epgmdm 0:8fd0531ae0be 167 int i=0;
epgmdm 0:8fd0531ae0be 168 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 169 while (1) {
epgmdm 0:8fd0531ae0be 170 sprintf(data," packet %03d", i++ |100);
epgmdm 0:8fd0531ae0be 171 transmitData(data,18);
epgmdm 0:8fd0531ae0be 172 wait (1.0);
epgmdm 0:8fd0531ae0be 173 }
nixonkj 6:77ead8abdd1c 174 }
epgmdm 0:8fd0531ae0be 175
nixonkj 6:77ead8abdd1c 176 char NRF2401P::setRadio(char speed, char power)
epgmdm 0:8fd0531ae0be 177 {
nixonkj 6:77ead8abdd1c 178 char val=0, chk=0;
nixonkj 8:3e027705ce23 179 if (debug) {
nixonkj 8:3e027705ce23 180 sprintf(logMsg, "Set radio");
nixonkj 8:3e027705ce23 181 log(logMsg);
nixonkj 8:3e027705ce23 182 }
epgmdm 0:8fd0531ae0be 183 if (speed & 0x02) {
epgmdm 0:8fd0531ae0be 184 val |= (1<<5);
epgmdm 0:8fd0531ae0be 185 }
epgmdm 0:8fd0531ae0be 186 val |= (speed & 0x01)<<3;
epgmdm 0:8fd0531ae0be 187
nixonkj 6:77ead8abdd1c 188 val |= ((power & 0x03)<<1);
nixonkj 6:77ead8abdd1c 189 printf("\n\r");
nixonkj 6:77ead8abdd1c 190
nixonkj 8:3e027705ce23 191 writeReg(RF_SETUP, val);
epgmdm 0:8fd0531ae0be 192
nixonkj 6:77ead8abdd1c 193 // read register to verify settings
nixonkj 8:3e027705ce23 194 readReg(RF_SETUP, &chk);
nixonkj 6:77ead8abdd1c 195 if (chk&0x2E == val) {
nixonkj 6:77ead8abdd1c 196 return 0;
nixonkj 6:77ead8abdd1c 197 } else {
nixonkj 6:77ead8abdd1c 198 return 1;
nixonkj 6:77ead8abdd1c 199 }
epgmdm 0:8fd0531ae0be 200 }
nixonkj 6:77ead8abdd1c 201
epgmdm 0:8fd0531ae0be 202 char NRF2401P::setChannel(char chan)
epgmdm 0:8fd0531ae0be 203 {
nixonkj 6:77ead8abdd1c 204 char chk=0;
nixonkj 6:77ead8abdd1c 205 if (debug) {
nixonkj 6:77ead8abdd1c 206 sprintf(logMsg, "Set channel");
nixonkj 6:77ead8abdd1c 207 log(logMsg);
nixonkj 6:77ead8abdd1c 208 }
nixonkj 8:3e027705ce23 209 writeReg(RF_CH, (chan&0x7f));
nixonkj 8:3e027705ce23 210 readReg(RF_CH, &chk);
nixonkj 6:77ead8abdd1c 211 if (chk&0x7f == chan&0x7f) {
nixonkj 6:77ead8abdd1c 212 return 0;
nixonkj 6:77ead8abdd1c 213 } else {
nixonkj 6:77ead8abdd1c 214 return 1;
nixonkj 6:77ead8abdd1c 215 }
epgmdm 0:8fd0531ae0be 216 }
nixonkj 6:77ead8abdd1c 217
nixonkj 13:5cbc726f2bbb 218 bool NRF2401P::isRPDset()
nixonkj 13:5cbc726f2bbb 219 {
nixonkj 13:5cbc726f2bbb 220 char val=0;
nixonkj 13:5cbc726f2bbb 221 if (debug) {
nixonkj 13:5cbc726f2bbb 222 sprintf(logMsg, "Get RPD");
nixonkj 13:5cbc726f2bbb 223 log(logMsg);
nixonkj 13:5cbc726f2bbb 224 }
nixonkj 13:5cbc726f2bbb 225 readReg(RPD, &val);
nixonkj 13:5cbc726f2bbb 226 if (val == 1) {
nixonkj 13:5cbc726f2bbb 227 return true;
nixonkj 13:5cbc726f2bbb 228 } else {
nixonkj 13:5cbc726f2bbb 229 return false;
nixonkj 13:5cbc726f2bbb 230 }
nixonkj 13:5cbc726f2bbb 231 }
nixonkj 13:5cbc726f2bbb 232
epgmdm 0:8fd0531ae0be 233 /**
epgmdm 0:8fd0531ae0be 234 * Transmits width bytes of data. width <32
epgmdm 0:8fd0531ae0be 235 */
nixonkj 6:77ead8abdd1c 236 char NRF2401P::transmitData( char *data, char width )
epgmdm 0:8fd0531ae0be 237 {
nixonkj 6:77ead8abdd1c 238 if (width>32)
nixonkj 6:77ead8abdd1c 239 return 0;
nixonkj 6:77ead8abdd1c 240 checkStatus();
nixonkj 6:77ead8abdd1c 241 if ((status>>4)&1) { // Max retries - flush tx
nixonkj 6:77ead8abdd1c 242 flushTx();
nixonkj 6:77ead8abdd1c 243 }
epgmdm 2:ca0a3c0bba70 244 //clearStatus();
epgmdm 2:ca0a3c0bba70 245 //ce = 1;
epgmdm 0:8fd0531ae0be 246 csn = 0;
nixonkj 8:3e027705ce23 247 char address = 0xA0;
epgmdm 0:8fd0531ae0be 248 int i;
epgmdm 0:8fd0531ae0be 249 // set up for writing
epgmdm 0:8fd0531ae0be 250 status = spi->write( address );
epgmdm 0:8fd0531ae0be 251 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 252 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 253 }
epgmdm 0:8fd0531ae0be 254 csn = 1;
epgmdm 3:afe8d307b5c3 255 wait(0.001);
epgmdm 3:afe8d307b5c3 256 if (debug) {
nixonkj 6:77ead8abdd1c 257 sprintf(logMsg, " Transmit data %d bytes to %02x (%02x) = %10s", width, address, status, data );
epgmdm 3:afe8d307b5c3 258 log(logMsg);
epgmdm 2:ca0a3c0bba70 259 }
epgmdm 0:8fd0531ae0be 260 return status;
epgmdm 0:8fd0531ae0be 261 }
epgmdm 0:8fd0531ae0be 262
epgmdm 0:8fd0531ae0be 263 /**
epgmdm 0:8fd0531ae0be 264 * sets acknowledge data width bytes of data. width <32
epgmdm 0:8fd0531ae0be 265 */
epgmdm 1:ff53b1ac3bad 266 char NRF2401P::acknowledgeData( char *data, char width, char pipe )
epgmdm 0:8fd0531ae0be 267 {
epgmdm 0:8fd0531ae0be 268 ce = 1;
epgmdm 0:8fd0531ae0be 269 csn = 0;
epgmdm 2:ca0a3c0bba70 270 //writeReg(0x1d,0x06); // enable payload with ack
epgmdm 2:ca0a3c0bba70 271 char address = W_ACK_PAYLOAD | (pipe&0x07);
epgmdm 0:8fd0531ae0be 272 int i;
epgmdm 0:8fd0531ae0be 273 // set up for writing
epgmdm 3:afe8d307b5c3 274 csn = 0;
epgmdm 0:8fd0531ae0be 275 status = spi->write( address );
epgmdm 0:8fd0531ae0be 276 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 277 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 278 }
epgmdm 0:8fd0531ae0be 279 csn = 1;
epgmdm 3:afe8d307b5c3 280 if (debug) {
epgmdm 3:afe8d307b5c3 281 sprintf(logMsg, " acknowledge data %d bytes to %02x (%02x) = %c", width, address, status, *data );
epgmdm 3:afe8d307b5c3 282 log(logMsg);
epgmdm 2:ca0a3c0bba70 283 }
epgmdm 0:8fd0531ae0be 284 return status;
nixonkj 6:77ead8abdd1c 285 }
epgmdm 0:8fd0531ae0be 286
epgmdm 0:8fd0531ae0be 287 /**
epgmdm 0:8fd0531ae0be 288 * Writes 1 byte data to a register
epgmdm 0:8fd0531ae0be 289 **/
nixonkj 6:77ead8abdd1c 290 void NRF2401P::writeReg( char address, char data )
epgmdm 0:8fd0531ae0be 291 {
epgmdm 0:8fd0531ae0be 292 char reg;
epgmdm 0:8fd0531ae0be 293 csn = 0;
epgmdm 0:8fd0531ae0be 294 address &= 0x1F;
nixonkj 8:3e027705ce23 295 reg = address | W_REGISTER;
epgmdm 0:8fd0531ae0be 296 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 297 spi->write( data );
epgmdm 0:8fd0531ae0be 298 csn = 1;
nixonkj 6:77ead8abdd1c 299 if (debug) {
nixonkj 6:77ead8abdd1c 300 sprintf(logMsg, " register write %02x (%02x) = %02x", address, status, data );
nixonkj 6:77ead8abdd1c 301 log(logMsg);
nixonkj 6:77ead8abdd1c 302 }
epgmdm 0:8fd0531ae0be 303 }
nixonkj 6:77ead8abdd1c 304
epgmdm 0:8fd0531ae0be 305 /**
epgmdm 0:8fd0531ae0be 306 * Writes width bytes data to a register, ls byte to ms byte /for adressess
epgmdm 0:8fd0531ae0be 307 **/
nixonkj 6:77ead8abdd1c 308 void NRF2401P::writeReg( char address, char *data, char width )
epgmdm 0:8fd0531ae0be 309 {
epgmdm 0:8fd0531ae0be 310 char reg;
epgmdm 0:8fd0531ae0be 311 csn = 0;
epgmdm 0:8fd0531ae0be 312 int i;
epgmdm 0:8fd0531ae0be 313 // set up for writing
epgmdm 0:8fd0531ae0be 314 address &= 0x1F;
nixonkj 8:3e027705ce23 315 reg = address| W_REGISTER;
epgmdm 0:8fd0531ae0be 316 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 317 for ( i = width - 1; i >= 0; i-- ) {
epgmdm 0:8fd0531ae0be 318 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 319 }
epgmdm 0:8fd0531ae0be 320 csn = 1;
epgmdm 2:ca0a3c0bba70 321 if (debug) {
epgmdm 2:ca0a3c0bba70 322 sprintf(logMsg, " register write %d bytes to %02x (%02x) = %02x %02x %02x", width, address, status, data[0], data[1], data[2] );
epgmdm 2:ca0a3c0bba70 323 log(logMsg);
epgmdm 2:ca0a3c0bba70 324 }
epgmdm 0:8fd0531ae0be 325 }
nixonkj 6:77ead8abdd1c 326
epgmdm 0:8fd0531ae0be 327 /**
epgmdm 0:8fd0531ae0be 328 * Reads 1 byte from a register
epgmdm 0:8fd0531ae0be 329 **/
nixonkj 6:77ead8abdd1c 330 void NRF2401P::readReg( char address, char *data )
epgmdm 0:8fd0531ae0be 331 {
epgmdm 0:8fd0531ae0be 332 csn = 0;
epgmdm 0:8fd0531ae0be 333 address &= 0x1F;
epgmdm 0:8fd0531ae0be 334 status = spi->write( address );
epgmdm 0:8fd0531ae0be 335 *data = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 336 csn = 1;
nixonkj 6:77ead8abdd1c 337 if (debug && address != 0x07) { // In debug mode: print out anything other than a status request
nixonkj 6:77ead8abdd1c 338 sprintf(logMsg, " register read %02x (%02x) = %02x", address, status, *data );
nixonkj 6:77ead8abdd1c 339 log(logMsg);
nixonkj 6:77ead8abdd1c 340 }
epgmdm 0:8fd0531ae0be 341 }
nixonkj 6:77ead8abdd1c 342
epgmdm 0:8fd0531ae0be 343 /**
nixonkj 10:8a217441c38e 344 * Reads n bytes from a register
nixonkj 10:8a217441c38e 345 **/
nixonkj 10:8a217441c38e 346 void NRF2401P::readReg( char address, char *data, char width )
epgmdm 16:a9b83d2b6915 347 {
nixonkj 10:8a217441c38e 348 char reg;
nixonkj 10:8a217441c38e 349 csn = 0;
nixonkj 10:8a217441c38e 350 int i;
nixonkj 10:8a217441c38e 351 // set up for writing
nixonkj 10:8a217441c38e 352 address &= 0x1F;
nixonkj 10:8a217441c38e 353 reg = address| R_REGISTER;
nixonkj 10:8a217441c38e 354 status = spi->write( reg );
nixonkj 10:8a217441c38e 355 for ( i = width - 1; i >= 0; i-- ) {
nixonkj 10:8a217441c38e 356 data[i] = spi->write( 0x00 );
nixonkj 10:8a217441c38e 357 }
nixonkj 10:8a217441c38e 358 csn = 1;
nixonkj 10:8a217441c38e 359 if (debug) {
nixonkj 10:8a217441c38e 360 sprintf(logMsg, " register read %d bytes from %02x (%02x) = ", width, address, status );
nixonkj 10:8a217441c38e 361 for ( i=0; i<width; i++)
nixonkj 10:8a217441c38e 362 sprintf(logMsg, "%s %02x", logMsg, data[i]);
nixonkj 10:8a217441c38e 363 log(logMsg);
nixonkj 10:8a217441c38e 364 }
nixonkj 10:8a217441c38e 365 }
nixonkj 10:8a217441c38e 366
nixonkj 10:8a217441c38e 367 /**
epgmdm 0:8fd0531ae0be 368 * Clears the status flags RX_DR, TX_DS, MAX_RT
epgmdm 0:8fd0531ae0be 369 */
nixonkj 6:77ead8abdd1c 370 void NRF2401P::clearStatus()
epgmdm 0:8fd0531ae0be 371 {
nixonkj 8:3e027705ce23 372 writeReg(STATUS, 0x70);
epgmdm 2:ca0a3c0bba70 373 if (debug) {
epgmdm 2:ca0a3c0bba70 374 sprintf(logMsg, "Clear status (%02x)", status );
epgmdm 2:ca0a3c0bba70 375 log(logMsg);
epgmdm 2:ca0a3c0bba70 376 }
epgmdm 0:8fd0531ae0be 377 }
nixonkj 6:77ead8abdd1c 378
epgmdm 0:8fd0531ae0be 379 /**
epgmdm 0:8fd0531ae0be 380 * flushes TX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 381 */
nixonkj 6:77ead8abdd1c 382 void NRF2401P::flushTx()
epgmdm 0:8fd0531ae0be 383 {
epgmdm 0:8fd0531ae0be 384 csn = 0;
epgmdm 2:ca0a3c0bba70 385 status = spi->write( FLUSH_TX );
epgmdm 0:8fd0531ae0be 386 csn = 1;
epgmdm 0:8fd0531ae0be 387 clearStatus();
epgmdm 2:ca0a3c0bba70 388 if (debug) {
epgmdm 2:ca0a3c0bba70 389 sprintf(logMsg, "Flush TX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 390 log(logMsg);
epgmdm 2:ca0a3c0bba70 391 }
epgmdm 0:8fd0531ae0be 392 }
epgmdm 0:8fd0531ae0be 393
epgmdm 0:8fd0531ae0be 394 /**
epgmdm 0:8fd0531ae0be 395 * flushes RX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 396 */
nixonkj 6:77ead8abdd1c 397 void NRF2401P::flushRx()
epgmdm 0:8fd0531ae0be 398 {
epgmdm 0:8fd0531ae0be 399 csn = 0;
epgmdm 2:ca0a3c0bba70 400 status = spi->write( FLUSH_RX );
epgmdm 0:8fd0531ae0be 401 csn = 1;
epgmdm 2:ca0a3c0bba70 402 clearStatus();
epgmdm 2:ca0a3c0bba70 403 if (debug) {
epgmdm 2:ca0a3c0bba70 404 sprintf(logMsg, "Flush RX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 405 log(logMsg);
epgmdm 2:ca0a3c0bba70 406 }
epgmdm 0:8fd0531ae0be 407 }
nixonkj 6:77ead8abdd1c 408
epgmdm 0:8fd0531ae0be 409 /**
epgmdm 0:8fd0531ae0be 410 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 411 */
nixonkj 6:77ead8abdd1c 412 char NRF2401P::setTxMode()
epgmdm 0:8fd0531ae0be 413 {
epgmdm 0:8fd0531ae0be 414 char data;
epgmdm 0:8fd0531ae0be 415 char bit;
epgmdm 2:ca0a3c0bba70 416 if (debug) {
epgmdm 2:ca0a3c0bba70 417 sprintf(logMsg, "Set Tx Mode");
epgmdm 2:ca0a3c0bba70 418 log(logMsg);
epgmdm 2:ca0a3c0bba70 419 }
nixonkj 8:3e027705ce23 420 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 421 data &= ~( 1 << 0 );
epgmdm 2:ca0a3c0bba70 422 flushTx();
epgmdm 2:ca0a3c0bba70 423 flushRx();
nixonkj 8:3e027705ce23 424 writeReg(CONFIG, data);
nixonkj 8:3e027705ce23 425 writeReg(RX_ADDR_P0, txAdd, addressWidth); // reset p0
nixonkj 8:3e027705ce23 426 writeReg(EN_RXADDR, 0x01); // enable pipe 0 for reading
epgmdm 0:8fd0531ae0be 427 // check
nixonkj 8:3e027705ce23 428 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 429 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 430
epgmdm 0:8fd0531ae0be 431 ce=1;
epgmdm 0:8fd0531ae0be 432 wait(0.003);
nixonkj 6:77ead8abdd1c 433 if (bit == 0) {
nixonkj 6:77ead8abdd1c 434 return 0;
nixonkj 6:77ead8abdd1c 435 } else {
nixonkj 6:77ead8abdd1c 436 return 1;
nixonkj 6:77ead8abdd1c 437 }
epgmdm 0:8fd0531ae0be 438 }
epgmdm 0:8fd0531ae0be 439
epgmdm 0:8fd0531ae0be 440 /**
epgmdm 0:8fd0531ae0be 441 * Sets the number of bytes of the address width = 3,4,5
epgmdm 0:8fd0531ae0be 442 */
nixonkj 6:77ead8abdd1c 443 char NRF2401P::setAddressWidth( char width )
epgmdm 0:8fd0531ae0be 444 {
nixonkj 6:77ead8abdd1c 445 char chk=0;
epgmdm 0:8fd0531ae0be 446 addressWidth = width;
epgmdm 0:8fd0531ae0be 447 if ( ( width > 5 ) || ( width < 3 ) )
epgmdm 0:8fd0531ae0be 448 return false;
epgmdm 0:8fd0531ae0be 449 width -= 2;
nixonkj 8:3e027705ce23 450 writeReg(SETUP_AW, width);
nixonkj 8:3e027705ce23 451 readReg(SETUP_AW, &chk);
nixonkj 6:77ead8abdd1c 452 if (chk&0x03 == width) {
nixonkj 6:77ead8abdd1c 453 return 0;
nixonkj 6:77ead8abdd1c 454 } else {
nixonkj 6:77ead8abdd1c 455 return 1;
nixonkj 6:77ead8abdd1c 456 }
epgmdm 0:8fd0531ae0be 457 }
nixonkj 6:77ead8abdd1c 458
epgmdm 0:8fd0531ae0be 459 /**
nixonkj 6:77ead8abdd1c 460 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 461 */
epgmdm 0:8fd0531ae0be 462 char NRF2401P::setTxAddress( char *address )
epgmdm 0:8fd0531ae0be 463 {
epgmdm 2:ca0a3c0bba70 464 memcpy (txAdd,address, addressWidth);
nixonkj 8:3e027705ce23 465 writeReg(RX_ADDR_P0, address, addressWidth);
nixonkj 8:3e027705ce23 466 writeReg(TX_ADDR, address, addressWidth);
nixonkj 6:77ead8abdd1c 467 return 0; // must fix this
epgmdm 0:8fd0531ae0be 468 }
epgmdm 0:8fd0531ae0be 469
epgmdm 0:8fd0531ae0be 470 /**
epgmdm 0:8fd0531ae0be 471 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 472 */
epgmdm 0:8fd0531ae0be 473 char NRF2401P::setTxAddress( long long address )
epgmdm 0:8fd0531ae0be 474 {
epgmdm 0:8fd0531ae0be 475 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 476 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 477 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 478 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 479 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 480 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 481 return setTxAddress( buff );
epgmdm 0:8fd0531ae0be 482 }
epgmdm 0:8fd0531ae0be 483
epgmdm 0:8fd0531ae0be 484 /**
nixonkj 9:c21b80aaf250 485 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 2:ca0a3c0bba70 486 * Enables pipe for receiving;
epgmdm 0:8fd0531ae0be 487 */
epgmdm 0:8fd0531ae0be 488 char NRF2401P::setRxAddress( char *address, char pipe )
epgmdm 0:8fd0531ae0be 489 {
epgmdm 2:ca0a3c0bba70 490 if(debug) {
epgmdm 2:ca0a3c0bba70 491 log ("Set Rx Address");
epgmdm 2:ca0a3c0bba70 492 }
epgmdm 2:ca0a3c0bba70 493 if (pipe>5) return 0xff;
epgmdm 2:ca0a3c0bba70 494 if (pipe ==0) {
nixonkj 8:3e027705ce23 495 memcpy(pipe0Add,address, addressWidth);
epgmdm 2:ca0a3c0bba70 496 }
epgmdm 2:ca0a3c0bba70 497
epgmdm 0:8fd0531ae0be 498 char reg = 0x0A + pipe;
epgmdm 0:8fd0531ae0be 499 switch ( pipe ) {
epgmdm 16:a9b83d2b6915 500 case ( 0 ) :
epgmdm 0:8fd0531ae0be 501 case ( 1 ) : {
epgmdm 16:a9b83d2b6915 502 writeReg(reg, address, addressWidth); //Write to RX_ADDR_P0 or _P1
epgmdm 16:a9b83d2b6915 503 break;
epgmdm 16:a9b83d2b6915 504 }
epgmdm 16:a9b83d2b6915 505 case ( 2 ) :
epgmdm 16:a9b83d2b6915 506 case ( 3 ) :
epgmdm 16:a9b83d2b6915 507 case ( 4 ) :
epgmdm 16:a9b83d2b6915 508 case ( 5 ) : {
epgmdm 16:a9b83d2b6915 509 writeReg(reg, address, 1); //Write to RX_ADDR_P2 ... _P5
epgmdm 16:a9b83d2b6915 510 break;
epgmdm 16:a9b83d2b6915 511 }
epgmdm 0:8fd0531ae0be 512
epgmdm 0:8fd0531ae0be 513 }
nixonkj 8:3e027705ce23 514 readReg(EN_RXADDR, &reg);
epgmdm 2:ca0a3c0bba70 515 reg |= (1<<pipe);
nixonkj 8:3e027705ce23 516 writeReg(EN_RXADDR, reg); //Enable the pipe
nixonkj 6:77ead8abdd1c 517 return 0; // Must fix this
epgmdm 0:8fd0531ae0be 518 }
epgmdm 0:8fd0531ae0be 519
epgmdm 0:8fd0531ae0be 520 /**
epgmdm 0:8fd0531ae0be 521 * Sets the address of pipe (<=5), uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 522 */
epgmdm 0:8fd0531ae0be 523 char NRF2401P::setRxAddress( long long address, char pipe )
epgmdm 0:8fd0531ae0be 524 {
epgmdm 0:8fd0531ae0be 525 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 526 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 527 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 528 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 529 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 530 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 531 return setRxAddress( buff, pipe );
epgmdm 0:8fd0531ae0be 532 }
nixonkj 6:77ead8abdd1c 533
epgmdm 1:ff53b1ac3bad 534 /**
epgmdm 1:ff53b1ac3bad 535 *checks the status flag
epgmdm 1:ff53b1ac3bad 536 */
epgmdm 1:ff53b1ac3bad 537 char NRF2401P::checkStatus()
epgmdm 1:ff53b1ac3bad 538 {
nixonkj 8:3e027705ce23 539 readReg(STATUS, &status);
epgmdm 1:ff53b1ac3bad 540 return status;
epgmdm 1:ff53b1ac3bad 541 }
nixonkj 6:77ead8abdd1c 542
epgmdm 1:ff53b1ac3bad 543 /**
epgmdm 1:ff53b1ac3bad 544 * checks if Ack data available.
epgmdm 1:ff53b1ac3bad 545 */
epgmdm 1:ff53b1ac3bad 546 bool NRF2401P::isAckData()
epgmdm 1:ff53b1ac3bad 547 {
epgmdm 1:ff53b1ac3bad 548 char fifo;
nixonkj 8:3e027705ce23 549 readReg(FIFO_STATUS, &fifo);
epgmdm 1:ff53b1ac3bad 550 bool isData = !(fifo&0x01);
epgmdm 1:ff53b1ac3bad 551 return isData;
epgmdm 1:ff53b1ac3bad 552 }
epgmdm 0:8fd0531ae0be 553
epgmdm 1:ff53b1ac3bad 554 /**
epgmdm 1:ff53b1ac3bad 555 * checks if RX data available.
epgmdm 1:ff53b1ac3bad 556 */
epgmdm 0:8fd0531ae0be 557 bool NRF2401P::isRxData()
epgmdm 0:8fd0531ae0be 558 {
epgmdm 1:ff53b1ac3bad 559 checkStatus();
epgmdm 0:8fd0531ae0be 560 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 561 return isData;
epgmdm 0:8fd0531ae0be 562 }
nixonkj 6:77ead8abdd1c 563
epgmdm 0:8fd0531ae0be 564 char NRF2401P::getRxWidth()
epgmdm 0:8fd0531ae0be 565 {
epgmdm 0:8fd0531ae0be 566 char width;
epgmdm 0:8fd0531ae0be 567 if (dynamic) {
epgmdm 0:8fd0531ae0be 568 csn = 0;
nixonkj 14:976a876819ae 569 status = spi->write( R_RX_PL_WID );
epgmdm 0:8fd0531ae0be 570 width = spi->write(0x00);
epgmdm 0:8fd0531ae0be 571 csn = 1;
epgmdm 0:8fd0531ae0be 572
nixonkj 14:976a876819ae 573 if (width>32) { // as per product spec
epgmdm 0:8fd0531ae0be 574 flushRx();
nixonkj 14:976a876819ae 575 wait(0.002f); // little delay (KJN)
epgmdm 0:8fd0531ae0be 576 width=0;
epgmdm 0:8fd0531ae0be 577 }
epgmdm 0:8fd0531ae0be 578 } else {
nixonkj 8:3e027705ce23 579 readReg(RX_PW_P1, &width); // width of p1
epgmdm 0:8fd0531ae0be 580 }
epgmdm 16:a9b83d2b6915 581
epgmdm 0:8fd0531ae0be 582 return width;
epgmdm 0:8fd0531ae0be 583 }
nixonkj 6:77ead8abdd1c 584
epgmdm 0:8fd0531ae0be 585 /**
epgmdm 0:8fd0531ae0be 586 * return message in buffer, mem for buffer must have been allocated.
epgmdm 0:8fd0531ae0be 587 * Return value is number of bytes of buffer
epgmdm 0:8fd0531ae0be 588 */
epgmdm 0:8fd0531ae0be 589 char NRF2401P::getRxData(char * buffer)
epgmdm 0:8fd0531ae0be 590 {
epgmdm 0:8fd0531ae0be 591 char address = 0x61;
epgmdm 0:8fd0531ae0be 592 char width;
epgmdm 0:8fd0531ae0be 593 width = getRxWidth();
epgmdm 0:8fd0531ae0be 594 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 595 if (isData) {
epgmdm 0:8fd0531ae0be 596 csn = 0;
epgmdm 0:8fd0531ae0be 597 int i;
epgmdm 0:8fd0531ae0be 598 // set up for reading
epgmdm 0:8fd0531ae0be 599 status = spi->write( address );
epgmdm 0:8fd0531ae0be 600 for ( i = 0; i <= width; i++ ) {
epgmdm 0:8fd0531ae0be 601 buffer[i]=spi->write(0x00 );
epgmdm 0:8fd0531ae0be 602 }
epgmdm 0:8fd0531ae0be 603 csn = 1;
nixonkj 6:77ead8abdd1c 604 if (debug) {
nixonkj 6:77ead8abdd1c 605 sprintf(logMsg, "Receive data %d bytes", width );
nixonkj 6:77ead8abdd1c 606 log(logMsg);
nixonkj 6:77ead8abdd1c 607 }
epgmdm 0:8fd0531ae0be 608 clearStatus();
epgmdm 0:8fd0531ae0be 609 return width;
epgmdm 0:8fd0531ae0be 610 } else {
nixonkj 6:77ead8abdd1c 611 if (debug) {
nixonkj 6:77ead8abdd1c 612 sprintf(logMsg, "Receive NO data %d bytes", width );
nixonkj 6:77ead8abdd1c 613 log(logMsg);
nixonkj 6:77ead8abdd1c 614 }
epgmdm 0:8fd0531ae0be 615 clearStatus();
epgmdm 0:8fd0531ae0be 616 return 0;
epgmdm 0:8fd0531ae0be 617 }
epgmdm 0:8fd0531ae0be 618 }
epgmdm 0:8fd0531ae0be 619
epgmdm 0:8fd0531ae0be 620 /**
epgmdm 0:8fd0531ae0be 621 * Sets all the receive pipes to dynamic payload length
epgmdm 0:8fd0531ae0be 622 */
epgmdm 2:ca0a3c0bba70 623 void NRF2401P::setDynamicPayload()
epgmdm 0:8fd0531ae0be 624 {
epgmdm 0:8fd0531ae0be 625 dynamic = true;
nixonkj 8:3e027705ce23 626 writeReg(FEATURE, 0x07); // Enable Dyn payload, Payload with Ack and w_tx_noack command
nixonkj 8:3e027705ce23 627 writeReg(EN_AA, 0x3f); // EN_AA regi for P1 and P0
nixonkj 9:c21b80aaf250 628 writeReg(DYNPD, 0x3F); // KJN - should be 0x3F for all pipes
epgmdm 0:8fd0531ae0be 629 }
epgmdm 2:ca0a3c0bba70 630
epgmdm 0:8fd0531ae0be 631 /**
epgmdm 0:8fd0531ae0be 632 * Sets PWR_UP = 1;
nixonkj 6:77ead8abdd1c 633 * return 0 on success
epgmdm 0:8fd0531ae0be 634 */
nixonkj 6:77ead8abdd1c 635 char NRF2401P::setPwrUp()
epgmdm 0:8fd0531ae0be 636 {
epgmdm 0:8fd0531ae0be 637 char data;
epgmdm 0:8fd0531ae0be 638 char bit;
epgmdm 0:8fd0531ae0be 639 ce=1;
nixonkj 8:3e027705ce23 640 readReg(CONFIG, &data);
epgmdm 2:ca0a3c0bba70 641 if ((data>>1) &0x01) {
epgmdm 2:ca0a3c0bba70 642 return true; // Already powered up
epgmdm 2:ca0a3c0bba70 643 };
nixonkj 8:3e027705ce23 644 data |= (0x02);
nixonkj 8:3e027705ce23 645 writeReg(CONFIG, data);
epgmdm 0:8fd0531ae0be 646 // check
nixonkj 8:3e027705ce23 647 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 648 bit = ( data >> 1 ) & 1;
epgmdm 2:ca0a3c0bba70 649
epgmdm 0:8fd0531ae0be 650 wait(0.005); // wait 5ms
epgmdm 2:ca0a3c0bba70 651 if(debug) {
epgmdm 2:ca0a3c0bba70 652 sprintf(logMsg, "Set PWR_UP to %x", bit);
epgmdm 2:ca0a3c0bba70 653 log(logMsg);
epgmdm 2:ca0a3c0bba70 654 }
nixonkj 6:77ead8abdd1c 655 if (bit == 1) {
nixonkj 6:77ead8abdd1c 656 return 0;
nixonkj 6:77ead8abdd1c 657 } else {
nixonkj 6:77ead8abdd1c 658 return 1;
nixonkj 6:77ead8abdd1c 659 }
nixonkj 6:77ead8abdd1c 660 }
epgmdm 2:ca0a3c0bba70 661
epgmdm 0:8fd0531ae0be 662 /**
defrost 19:f7e74aa7d663 663 * Sets PWR_UP = 1;
defrost 19:f7e74aa7d663 664 * return 0 on success
defrost 19:f7e74aa7d663 665 */
defrost 19:f7e74aa7d663 666
defrost 19:f7e74aa7d663 667 char NRF2401P::setPwrDown()
defrost 19:f7e74aa7d663 668 {
defrost 19:f7e74aa7d663 669 // read the CONFIG register:
defrost 19:f7e74aa7d663 670 char data;
defrost 19:f7e74aa7d663 671 readReg(CONFIG, &data);
defrost 19:f7e74aa7d663 672 // Clear the pwr up bit:
defrost 19:f7e74aa7d663 673 data &= ~(0x1 << PWR_UP);
defrost 19:f7e74aa7d663 674 // Send the new CONFIG register:
defrost 19:f7e74aa7d663 675 writeReg(CONFIG, data);
defrost 19:f7e74aa7d663 676 // check to see if it worked:
defrost 19:f7e74aa7d663 677 readReg(CONFIG, &data);
defrost 19:f7e74aa7d663 678 if(((0x1<<PWR_UP) & data) == 0){
defrost 19:f7e74aa7d663 679 return 0;
defrost 19:f7e74aa7d663 680 }else{
defrost 19:f7e74aa7d663 681 return 1;
defrost 19:f7e74aa7d663 682 }
defrost 19:f7e74aa7d663 683 }
defrost 19:f7e74aa7d663 684
defrost 19:f7e74aa7d663 685 /**
epgmdm 0:8fd0531ae0be 686 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 687 */
nixonkj 6:77ead8abdd1c 688 char NRF2401P::setRxMode()
epgmdm 0:8fd0531ae0be 689 {
epgmdm 0:8fd0531ae0be 690 char data;
epgmdm 0:8fd0531ae0be 691 char bit;
epgmdm 0:8fd0531ae0be 692 ce=1;
nixonkj 8:3e027705ce23 693 readReg(CONFIG, &data);
nixonkj 8:3e027705ce23 694 data |= (0x01);
epgmdm 2:ca0a3c0bba70 695
nixonkj 8:3e027705ce23 696 writeReg(CONFIG, data);
epgmdm 3:afe8d307b5c3 697 if (pipe0Add[0]|pipe0Add[1]|pipe0Add[2]|pipe0Add[3]|pipe0Add[4] >0) {
epgmdm 3:afe8d307b5c3 698 setRxAddress(pipe0Add,0);
epgmdm 2:ca0a3c0bba70 699 }
epgmdm 0:8fd0531ae0be 700 // check
nixonkj 8:3e027705ce23 701 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 702 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 703
epgmdm 2:ca0a3c0bba70 704 wait (0.001);
epgmdm 0:8fd0531ae0be 705 flushRx();
epgmdm 2:ca0a3c0bba70 706 flushTx();
epgmdm 2:ca0a3c0bba70 707 if (debug) {
epgmdm 2:ca0a3c0bba70 708 sprintf(logMsg, " set PRIM_RX to %x", bit);
epgmdm 2:ca0a3c0bba70 709 log(logMsg);
epgmdm 2:ca0a3c0bba70 710 }
nixonkj 6:77ead8abdd1c 711 if ( bit == 1 ) {
nixonkj 6:77ead8abdd1c 712 return 0;
nixonkj 6:77ead8abdd1c 713 } else {
nixonkj 6:77ead8abdd1c 714 return 1;
nixonkj 6:77ead8abdd1c 715 }
epgmdm 0:8fd0531ae0be 716 }
nixonkj 6:77ead8abdd1c 717
epgmdm 0:8fd0531ae0be 718 /**
epgmdm 0:8fd0531ae0be 719 * Prints status string
epgmdm 0:8fd0531ae0be 720 */
epgmdm 0:8fd0531ae0be 721 char * NRF2401P::statusString()
epgmdm 0:8fd0531ae0be 722 {
epgmdm 0:8fd0531ae0be 723 char *msg;
epgmdm 0:8fd0531ae0be 724 msg = statusS;
epgmdm 0:8fd0531ae0be 725 if (((status>>1) & 0x07)==0x07) {
epgmdm 0:8fd0531ae0be 726 sprintf(msg,"RX empty");
epgmdm 0:8fd0531ae0be 727 } else {
epgmdm 0:8fd0531ae0be 728 sprintf(msg,"pipe %02x",(status>>1) & 0x07);
epgmdm 0:8fd0531ae0be 729 }
epgmdm 0:8fd0531ae0be 730
epgmdm 0:8fd0531ae0be 731 if ((status>>6)&0x01) strcat(msg," RX_DR,");
epgmdm 0:8fd0531ae0be 732 if ((status>>5)&0x01) strcat(msg," TX_DS,");
epgmdm 0:8fd0531ae0be 733 if ((status>>4)&0x01) strcat(msg," MAX_RT,");
epgmdm 0:8fd0531ae0be 734 if ((status>>0)&0x01) strcat(msg," TX_FLL,");
epgmdm 0:8fd0531ae0be 735
epgmdm 0:8fd0531ae0be 736 return msg;
nixonkj 9:c21b80aaf250 737 }
nixonkj 9:c21b80aaf250 738
nixonkj 11:07f76589f00a 739 void NRF2401P::printReg(char* name, char address, bool newline)
nixonkj 9:c21b80aaf250 740 {
nixonkj 9:c21b80aaf250 741 char data;
nixonkj 11:07f76589f00a 742 readReg(address, &data);
nixonkj 11:07f76589f00a 743 printf("%s = 0x%02x", name, data);
nixonkj 11:07f76589f00a 744 if (newline) {
nixonkj 11:07f76589f00a 745 printf("\r\n");
nixonkj 11:07f76589f00a 746 }
epgmdm 16:a9b83d2b6915 747 }
epgmdm 16:a9b83d2b6915 748
nixonkj 11:07f76589f00a 749 void NRF2401P::printReg(char* name, char address, char width, bool newline)
nixonkj 11:07f76589f00a 750 {
nixonkj 11:07f76589f00a 751 char data[width];
nixonkj 11:07f76589f00a 752 readReg(address, data, width);
nixonkj 11:07f76589f00a 753 printf("%s = 0x", name);
nixonkj 11:07f76589f00a 754 for (int i=width-1; i>=0; i--) {
nixonkj 11:07f76589f00a 755 printf("%02x", data[i]);
nixonkj 11:07f76589f00a 756 }
nixonkj 11:07f76589f00a 757 if (newline) {
nixonkj 11:07f76589f00a 758 printf("\r\n");
nixonkj 11:07f76589f00a 759 }
nixonkj 11:07f76589f00a 760 }
nixonkj 11:07f76589f00a 761
nixonkj 11:07f76589f00a 762 void NRF2401P::printDetails() {
nixonkj 14:976a876819ae 763 status = checkStatus();
nixonkj 11:07f76589f00a 764 printf("STATUS = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n", status,
nixonkj 9:c21b80aaf250 765 (status & (1<<MASK_RX_DR))?1:0,
nixonkj 9:c21b80aaf250 766 (status & (1<<MASK_TX_DS))?1:0,
nixonkj 9:c21b80aaf250 767 (status & (1<<MASK_MAX_RT))?1:0,
nixonkj 9:c21b80aaf250 768 (status >> RX_P_NO) & 7,
nixonkj 9:c21b80aaf250 769 (status & (1<<TX_FULL))?1:0 );
nixonkj 9:c21b80aaf250 770
nixonkj 11:07f76589f00a 771 printReg("RX_ADDR_P0", RX_ADDR_P0, addressWidth);
nixonkj 11:07f76589f00a 772 printReg("RX_ADDR_P1", RX_ADDR_P1, addressWidth);
nixonkj 11:07f76589f00a 773 printReg("RX_ADDR_P2", RX_ADDR_P2, addressWidth);
nixonkj 11:07f76589f00a 774 printReg("RX_ADDR_P3", RX_ADDR_P3, addressWidth);
nixonkj 11:07f76589f00a 775 printReg("RX_ADDR_P4", RX_ADDR_P4, addressWidth);
nixonkj 11:07f76589f00a 776 printReg("RX_ADDR_P5", RX_ADDR_P5, addressWidth);
nixonkj 11:07f76589f00a 777 printReg("TX_ADDR", TX_ADDR, addressWidth);
nixonkj 10:8a217441c38e 778
nixonkj 11:07f76589f00a 779 printReg("RX_PW_P0", RX_PW_P0, false); // false for no newline, save some space
nixonkj 11:07f76589f00a 780 printReg(" RX_PW_P1", RX_PW_P1, false);
nixonkj 11:07f76589f00a 781 printReg(" RX_PW_P2", RX_PW_P2);
nixonkj 11:07f76589f00a 782 printReg("RX_PW_P3", RX_PW_P3, false);
nixonkj 11:07f76589f00a 783 printReg(" RX_PW_P4", RX_PW_P4, false);
nixonkj 11:07f76589f00a 784 printReg(" RX_PW_P5", RX_PW_P5);
nixonkj 11:07f76589f00a 785
nixonkj 11:07f76589f00a 786 printReg("EN_AA", EN_AA);
nixonkj 11:07f76589f00a 787 printReg("EN_RXADDR", EN_RXADDR);
nixonkj 11:07f76589f00a 788 printReg("RF_CH", RF_CH);
nixonkj 11:07f76589f00a 789 printReg("RF_SETUP", RF_SETUP);
nixonkj 12:ea1345de6478 790 printReg("CONFIG", CONFIG);
nixonkj 11:07f76589f00a 791 printReg("DYNPD", DYNPD);
nixonkj 11:07f76589f00a 792 printReg("FEATURE", FEATURE);
epgmdm 0:8fd0531ae0be 793 }