Damien Frost / NRF2401P

My fork during debugging.

Fork of NRF2401P by Malcolm McCulloch

NRF2401P.cpp@6:77ead8abdd1c, 2015-07-05 (annotated)

Committer:
nixonkj
Date:
Sun Jul 05 21:45:51 2015 +0000
Revision:
6:77ead8abdd1c
Parent:
4:e55807cf840b
Child:
7:621a5b0cf1aa
Minor housekeeping. Tidied up function return values. For functions doing something the convention is to return a char - 0 on success, non-zero for failure. Query functions return bool. Reading and writing registers are now void functions.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
epgmdm 0:8fd0531ae0be 1 /**
epgmdm 0:8fd0531ae0be 2 *@section DESCRIPTION
epgmdm 0:8fd0531ae0be 3 * mbed NRF2401+ Library
epgmdm 0:8fd0531ae0be 4 *@section LICENSE
epgmdm 0:8fd0531ae0be 5 * Copyright (c) 2015, Malcolm McCulloch
epgmdm 0:8fd0531ae0be 6 *
epgmdm 0:8fd0531ae0be 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
epgmdm 0:8fd0531ae0be 8 * of this software and associated documentation files (the "Software"), to deal
epgmdm 0:8fd0531ae0be 9 * in the Software without restriction, including without limitation the rights
epgmdm 0:8fd0531ae0be 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
epgmdm 0:8fd0531ae0be 11 * copies of the Software, and to permit persons to whom the Software is
epgmdm 0:8fd0531ae0be 12 * furnished to do so, subject to the following conditions:
epgmdm 0:8fd0531ae0be 13 *
epgmdm 0:8fd0531ae0be 14 * The above copyright notice and this permission notice shall be included in
epgmdm 0:8fd0531ae0be 15 * all copies or substantial portions of the Software.
epgmdm 0:8fd0531ae0be 16 *
epgmdm 0:8fd0531ae0be 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
epgmdm 0:8fd0531ae0be 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
epgmdm 0:8fd0531ae0be 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
epgmdm 0:8fd0531ae0be 20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
epgmdm 0:8fd0531ae0be 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
epgmdm 0:8fd0531ae0be 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
epgmdm 0:8fd0531ae0be 23 * THE SOFTWARE.
epgmdm 0:8fd0531ae0be 24 * @file "NRF2401P.cpp"
epgmdm 0:8fd0531ae0be 25 */
epgmdm 2:ca0a3c0bba70 26 #include "mbed.h"
epgmdm 2:ca0a3c0bba70 27 #include "NRF2401P.h"
epgmdm 2:ca0a3c0bba70 28 #include "nRF24l01.h"
epgmdm 0:8fd0531ae0be 29
epgmdm 0:8fd0531ae0be 30 NRF2401P::NRF2401P ( PinName mosi, PinName miso, PinName sclk, PinName _csn, PinName _ce ) :
epgmdm 0:8fd0531ae0be 31 csn( DigitalOut( _csn ) ), ce( DigitalOut( _ce ) )
epgmdm 0:8fd0531ae0be 32 {
epgmdm 0:8fd0531ae0be 33 addressWidth = 5;
epgmdm 0:8fd0531ae0be 34 pc = new Serial( USBTX, USBRX ); // tx, rx
nixonkj 6:77ead8abdd1c 35 if (debug) {
nixonkj 6:77ead8abdd1c 36 sprintf(logMsg, "Initialise" );
nixonkj 6:77ead8abdd1c 37 log(logMsg);
nixonkj 6:77ead8abdd1c 38 }
epgmdm 0:8fd0531ae0be 39 spi = new SPI( mosi, miso, sclk, NC ); //SPI (PinName mosi, PinName miso, PinName sclk, PinName _unused=NC)
epgmdm 0:8fd0531ae0be 40 spi->frequency( 10000000 ); // 1MHZ max 10 MHz
epgmdm 0:8fd0531ae0be 41 spi->format( 8, 0 ); // 0: 0e 08; 1: 0e 00; 2:0e 00 ;3:1c 00
epgmdm 0:8fd0531ae0be 42 csn = 1;
epgmdm 0:8fd0531ae0be 43 ce = 0;
epgmdm 0:8fd0531ae0be 44 dynamic = false;
nixonkj 6:77ead8abdd1c 45 debug = false;
nixonkj 6:77ead8abdd1c 46 }
epgmdm 0:8fd0531ae0be 47
epgmdm 0:8fd0531ae0be 48 /**
epgmdm 0:8fd0531ae0be 49 * writes to pc and waits
epgmdm 0:8fd0531ae0be 50 */
nixonkj 6:77ead8abdd1c 51 void NRF2401P::log(char *msg)
epgmdm 0:8fd0531ae0be 52 {
epgmdm 0:8fd0531ae0be 53 if(debug) {
epgmdm 2:ca0a3c0bba70 54 printf("\t <%s \t %s>\n\r",statusString(), msg);
epgmdm 1:ff53b1ac3bad 55 wait(0.01);
nixonkj 6:77ead8abdd1c 56 }
epgmdm 0:8fd0531ae0be 57 }
epgmdm 0:8fd0531ae0be 58
epgmdm 0:8fd0531ae0be 59 void NRF2401P::scratch()
epgmdm 0:8fd0531ae0be 60 {
epgmdm 0:8fd0531ae0be 61 int status = 0;
epgmdm 0:8fd0531ae0be 62 int register1 = 0;
epgmdm 0:8fd0531ae0be 63 ce = 0;
epgmdm 0:8fd0531ae0be 64 for ( char i = 0; i < 24; i++ ) {
epgmdm 0:8fd0531ae0be 65 csn = 0;
epgmdm 0:8fd0531ae0be 66 //wait_us(100);
epgmdm 0:8fd0531ae0be 67 status = spi->write( i );
epgmdm 0:8fd0531ae0be 68 register1 = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 69 csn = 1;
epgmdm 0:8fd0531ae0be 70 sprintf(logMsg, " register %02x (%02x) = %02x", i, status, register1 );
epgmdm 0:8fd0531ae0be 71 log(logMsg);
epgmdm 0:8fd0531ae0be 72 }
nixonkj 6:77ead8abdd1c 73 }
epgmdm 0:8fd0531ae0be 74
epgmdm 0:8fd0531ae0be 75 /**
epgmdm 2:ca0a3c0bba70 76 * start here to configure the basics of the NRF
epgmdm 2:ca0a3c0bba70 77 */
epgmdm 2:ca0a3c0bba70 78 void NRF2401P::start()
epgmdm 2:ca0a3c0bba70 79 {
epgmdm 2:ca0a3c0bba70 80 writeReg( CONFIG, 0x0c ); // set 16 bit crc
epgmdm 2:ca0a3c0bba70 81 setTxRetry(0x01,0x0f); // 500 uS, 15 retries
epgmdm 2:ca0a3c0bba70 82 setRadio(0,0x03); // 1MB/S 0dB
epgmdm 2:ca0a3c0bba70 83 setDynamicPayload();
epgmdm 2:ca0a3c0bba70 84 setChannel(76); // should be clear?
epgmdm 2:ca0a3c0bba70 85 setAddressWidth(5);
epgmdm 2:ca0a3c0bba70 86 flushRx();
epgmdm 2:ca0a3c0bba70 87 flushTx();
epgmdm 2:ca0a3c0bba70 88 setPwrUp();
epgmdm 2:ca0a3c0bba70 89 setTxMode(); // just make sure no spurious reads....
nixonkj 6:77ead8abdd1c 90 }
epgmdm 2:ca0a3c0bba70 91
epgmdm 2:ca0a3c0bba70 92 /**
epgmdm 0:8fd0531ae0be 93 * Sets up a reciever using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 94 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 95 */
epgmdm 2:ca0a3c0bba70 96 void NRF2401P::quickRxSetup(int channel,long long addrRx)
epgmdm 0:8fd0531ae0be 97 {
epgmdm 2:ca0a3c0bba70 98 start();
epgmdm 0:8fd0531ae0be 99 setChannel(channel);
epgmdm 2:ca0a3c0bba70 100 setRxAddress(addrRx,1);
epgmdm 0:8fd0531ae0be 101 setRxMode();
epgmdm 0:8fd0531ae0be 102 ce=1;
nixonkj 6:77ead8abdd1c 103 wait(0.001f);
epgmdm 0:8fd0531ae0be 104 }
nixonkj 6:77ead8abdd1c 105
epgmdm 0:8fd0531ae0be 106 /**
epgmdm 0:8fd0531ae0be 107 * Sets up for receive of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 108 */
epgmdm 0:8fd0531ae0be 109 char NRF2401P::testReceive()
epgmdm 0:8fd0531ae0be 110 {
epgmdm 0:8fd0531ae0be 111 char message[64];
epgmdm 0:8fd0531ae0be 112 char width;
epgmdm 0:8fd0531ae0be 113 int channel = 0x12;
epgmdm 0:8fd0531ae0be 114 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 115 debug = true;
epgmdm 0:8fd0531ae0be 116 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 117
epgmdm 0:8fd0531ae0be 118 while (1) {
epgmdm 0:8fd0531ae0be 119 while (!isRxData()) {
epgmdm 0:8fd0531ae0be 120 //wait(0.5);
epgmdm 0:8fd0531ae0be 121 };
epgmdm 0:8fd0531ae0be 122 width=getRxData(message);
epgmdm 0:8fd0531ae0be 123 message[width]='\0';
epgmdm 0:8fd0531ae0be 124 sprintf(logMsg,"Received= [%s]",message);
epgmdm 0:8fd0531ae0be 125 log(logMsg);
nixonkj 6:77ead8abdd1c 126 }
epgmdm 0:8fd0531ae0be 127 }
epgmdm 0:8fd0531ae0be 128
epgmdm 0:8fd0531ae0be 129 /**
epgmdm 2:ca0a3c0bba70 130 * Sets the number and the timimg of TX retries
epgmdm 2:ca0a3c0bba70 131 */
nixonkj 6:77ead8abdd1c 132 char NRF2401P::setTxRetry(char delay, char numTries)
epgmdm 2:ca0a3c0bba70 133 {
epgmdm 2:ca0a3c0bba70 134 char val = (delay&0xf)<<4 | (numTries&0xf);
nixonkj 6:77ead8abdd1c 135 char chk;
epgmdm 2:ca0a3c0bba70 136 writeReg (SETUP_RETR, val);
nixonkj 6:77ead8abdd1c 137 readReg( SETUP_RETR, &chk );
nixonkj 6:77ead8abdd1c 138 if (chk&0xff == val) {
nixonkj 6:77ead8abdd1c 139 return 0;
nixonkj 6:77ead8abdd1c 140 } else {
nixonkj 6:77ead8abdd1c 141 return 1;
nixonkj 6:77ead8abdd1c 142 }
epgmdm 2:ca0a3c0bba70 143 }
epgmdm 2:ca0a3c0bba70 144
epgmdm 2:ca0a3c0bba70 145 /**
epgmdm 0:8fd0531ae0be 146 * Sets up a transmitter using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 147 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 148 */
epgmdm 0:8fd0531ae0be 149 void NRF2401P::quickTxSetup(int channel,long long addr)
epgmdm 0:8fd0531ae0be 150 {
epgmdm 2:ca0a3c0bba70 151 start();
epgmdm 0:8fd0531ae0be 152 setChannel(channel);
epgmdm 2:ca0a3c0bba70 153 setTxAddress(addr);
epgmdm 0:8fd0531ae0be 154 setTxMode();
epgmdm 0:8fd0531ae0be 155 ce=1;
epgmdm 0:8fd0531ae0be 156 wait (0.0016f); // wait for pll to settle
epgmdm 0:8fd0531ae0be 157 }
epgmdm 0:8fd0531ae0be 158
epgmdm 0:8fd0531ae0be 159 /**
epgmdm 0:8fd0531ae0be 160 * Sets up for transmit of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 161 */
epgmdm 0:8fd0531ae0be 162 char NRF2401P::testTransmit()
epgmdm 0:8fd0531ae0be 163 {
epgmdm 0:8fd0531ae0be 164 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 165 int channel = 0x12;
epgmdm 0:8fd0531ae0be 166 char data[32] ;
epgmdm 0:8fd0531ae0be 167 int i=0;
epgmdm 0:8fd0531ae0be 168 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 169 while (1) {
epgmdm 0:8fd0531ae0be 170 sprintf(data," packet %03d", i++ |100);
epgmdm 0:8fd0531ae0be 171 transmitData(data,18);
epgmdm 0:8fd0531ae0be 172 wait (1.0);
epgmdm 0:8fd0531ae0be 173 }
nixonkj 6:77ead8abdd1c 174 }
epgmdm 0:8fd0531ae0be 175
epgmdm 0:8fd0531ae0be 176 /**
epgmdm 0:8fd0531ae0be 177 *Speed :
epgmdm 0:8fd0531ae0be 178 ‘0x00’ – 1Mbps
epgmdm 0:8fd0531ae0be 179 ‘0x01’ – 2Mbps
epgmdm 0:8fd0531ae0be 180 ‘0x02’ – 250kbps
epgmdm 0:8fd0531ae0be 181 ‘0x03’ – Reserved
epgmdm 0:8fd0531ae0be 182 Power:
epgmdm 0:8fd0531ae0be 183 '0x00' – -18dBm
epgmdm 0:8fd0531ae0be 184 '0x01' – -12dBm
epgmdm 0:8fd0531ae0be 185 '0x02' – -6dBm
epgmdm 0:8fd0531ae0be 186 '0x03' – 0dBm
nixonkj 6:77ead8abdd1c 187 * Return: 0 for success, non-zero for fail
epgmdm 0:8fd0531ae0be 188 */
nixonkj 6:77ead8abdd1c 189 char NRF2401P::setRadio(char speed, char power)
epgmdm 0:8fd0531ae0be 190 {
nixonkj 6:77ead8abdd1c 191 char val=0, chk=0;
epgmdm 0:8fd0531ae0be 192 sprintf(logMsg, "Set radio");
epgmdm 0:8fd0531ae0be 193 log(logMsg);
epgmdm 0:8fd0531ae0be 194 if (speed & 0x02) {
epgmdm 0:8fd0531ae0be 195 val |= (1<<5);
epgmdm 0:8fd0531ae0be 196 }
epgmdm 0:8fd0531ae0be 197 val |= (speed & 0x01)<<3;
epgmdm 0:8fd0531ae0be 198
nixonkj 6:77ead8abdd1c 199 val |= ((power & 0x03)<<1);
nixonkj 6:77ead8abdd1c 200 printf("\n\r");
nixonkj 6:77ead8abdd1c 201
nixonkj 6:77ead8abdd1c 202 writeReg (0x06, val);
epgmdm 0:8fd0531ae0be 203
nixonkj 6:77ead8abdd1c 204 // read register to verify settings
nixonkj 6:77ead8abdd1c 205 readReg( 0x06, &chk );
nixonkj 6:77ead8abdd1c 206 if (chk&0x2E == val) {
nixonkj 6:77ead8abdd1c 207 return 0;
nixonkj 6:77ead8abdd1c 208 } else {
nixonkj 6:77ead8abdd1c 209 return 1;
nixonkj 6:77ead8abdd1c 210 }
epgmdm 0:8fd0531ae0be 211 }
nixonkj 6:77ead8abdd1c 212
epgmdm 0:8fd0531ae0be 213 /**
epgmdm 0:8fd0531ae0be 214 Set RF_CH = chan;
epgmdm 0:8fd0531ae0be 215
epgmdm 0:8fd0531ae0be 216 F0= 2400 + chan [MHz]
epgmdm 0:8fd0531ae0be 217 */
epgmdm 0:8fd0531ae0be 218 char NRF2401P::setChannel(char chan)
epgmdm 0:8fd0531ae0be 219 {
nixonkj 6:77ead8abdd1c 220 char chk=0;
nixonkj 6:77ead8abdd1c 221 if (debug) {
nixonkj 6:77ead8abdd1c 222 sprintf(logMsg, "Set channel");
nixonkj 6:77ead8abdd1c 223 log(logMsg);
nixonkj 6:77ead8abdd1c 224 }
epgmdm 0:8fd0531ae0be 225 writeReg (0x05,(chan&0x7f));
nixonkj 6:77ead8abdd1c 226 readReg(0x05,&chk);
nixonkj 6:77ead8abdd1c 227 if (chk&0x7f == chan&0x7f) {
nixonkj 6:77ead8abdd1c 228 return 0;
nixonkj 6:77ead8abdd1c 229 } else {
nixonkj 6:77ead8abdd1c 230 return 1;
nixonkj 6:77ead8abdd1c 231 }
epgmdm 0:8fd0531ae0be 232 }
nixonkj 6:77ead8abdd1c 233
epgmdm 0:8fd0531ae0be 234 /**
epgmdm 0:8fd0531ae0be 235 * Transmits width bytes of data. width <32
epgmdm 0:8fd0531ae0be 236 */
nixonkj 6:77ead8abdd1c 237 char NRF2401P::transmitData( char *data, char width )
epgmdm 0:8fd0531ae0be 238 {
nixonkj 6:77ead8abdd1c 239 if (width>32)
nixonkj 6:77ead8abdd1c 240 return 0;
nixonkj 6:77ead8abdd1c 241 checkStatus();
nixonkj 6:77ead8abdd1c 242 if ((status>>4)&1) { // Max retries - flush tx
nixonkj 6:77ead8abdd1c 243 flushTx();
nixonkj 6:77ead8abdd1c 244 }
epgmdm 2:ca0a3c0bba70 245 //clearStatus();
epgmdm 2:ca0a3c0bba70 246 //ce = 1;
epgmdm 0:8fd0531ae0be 247 csn = 0;
epgmdm 0:8fd0531ae0be 248 char address = 0XA0;
epgmdm 0:8fd0531ae0be 249 int i;
epgmdm 0:8fd0531ae0be 250 // set up for writing
epgmdm 0:8fd0531ae0be 251 status = spi->write( address );
epgmdm 0:8fd0531ae0be 252 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 253 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 254 }
epgmdm 0:8fd0531ae0be 255 csn = 1;
epgmdm 3:afe8d307b5c3 256 wait(0.001);
epgmdm 3:afe8d307b5c3 257 if (debug) {
nixonkj 6:77ead8abdd1c 258 sprintf(logMsg, " Transmit data %d bytes to %02x (%02x) = %10s", width, address, status, data );
epgmdm 3:afe8d307b5c3 259 log(logMsg);
epgmdm 2:ca0a3c0bba70 260 }
epgmdm 0:8fd0531ae0be 261 return status;
epgmdm 0:8fd0531ae0be 262 }
epgmdm 0:8fd0531ae0be 263
epgmdm 0:8fd0531ae0be 264 /**
epgmdm 0:8fd0531ae0be 265 * sets acknowledge data width bytes of data. width <32
epgmdm 0:8fd0531ae0be 266 */
epgmdm 1:ff53b1ac3bad 267 char NRF2401P::acknowledgeData( char *data, char width, char pipe )
epgmdm 0:8fd0531ae0be 268 {
epgmdm 0:8fd0531ae0be 269 ce = 1;
epgmdm 0:8fd0531ae0be 270 csn = 0;
epgmdm 2:ca0a3c0bba70 271 //writeReg(0x1d,0x06); // enable payload with ack
epgmdm 2:ca0a3c0bba70 272 char address = W_ACK_PAYLOAD | (pipe&0x07);
epgmdm 0:8fd0531ae0be 273 int i;
epgmdm 0:8fd0531ae0be 274 // set up for writing
epgmdm 3:afe8d307b5c3 275 csn = 0;
epgmdm 0:8fd0531ae0be 276 status = spi->write( address );
epgmdm 0:8fd0531ae0be 277 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 278 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 279 }
epgmdm 0:8fd0531ae0be 280 csn = 1;
epgmdm 3:afe8d307b5c3 281 if (debug) {
epgmdm 3:afe8d307b5c3 282 sprintf(logMsg, " acknowledge data %d bytes to %02x (%02x) = %c", width, address, status, *data );
epgmdm 3:afe8d307b5c3 283 log(logMsg);
epgmdm 2:ca0a3c0bba70 284 }
epgmdm 0:8fd0531ae0be 285 return status;
nixonkj 6:77ead8abdd1c 286 }
epgmdm 0:8fd0531ae0be 287
epgmdm 0:8fd0531ae0be 288 /**
epgmdm 0:8fd0531ae0be 289 * Writes 1 byte data to a register
epgmdm 0:8fd0531ae0be 290 **/
nixonkj 6:77ead8abdd1c 291 void NRF2401P::writeReg( char address, char data )
epgmdm 0:8fd0531ae0be 292 {
epgmdm 0:8fd0531ae0be 293 char status = 0;
epgmdm 0:8fd0531ae0be 294 char reg;
epgmdm 0:8fd0531ae0be 295 csn = 0;
epgmdm 0:8fd0531ae0be 296 address &= 0x1F;
epgmdm 0:8fd0531ae0be 297 reg = address | 0x20;
epgmdm 0:8fd0531ae0be 298 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 299 spi->write( data );
epgmdm 0:8fd0531ae0be 300 csn = 1;
nixonkj 6:77ead8abdd1c 301 if (debug) {
nixonkj 6:77ead8abdd1c 302 sprintf(logMsg, " register write %02x (%02x) = %02x", address, status, data );
nixonkj 6:77ead8abdd1c 303 log(logMsg);
nixonkj 6:77ead8abdd1c 304 }
epgmdm 0:8fd0531ae0be 305 }
nixonkj 6:77ead8abdd1c 306
epgmdm 0:8fd0531ae0be 307 /**
epgmdm 0:8fd0531ae0be 308 * Writes width bytes data to a register, ls byte to ms byte /for adressess
epgmdm 0:8fd0531ae0be 309 **/
nixonkj 6:77ead8abdd1c 310 void NRF2401P::writeReg( char address, char *data, char width )
epgmdm 0:8fd0531ae0be 311 {
epgmdm 0:8fd0531ae0be 312 char reg;
epgmdm 0:8fd0531ae0be 313 csn = 0;
epgmdm 0:8fd0531ae0be 314 int i;
epgmdm 0:8fd0531ae0be 315 // set up for writing
epgmdm 0:8fd0531ae0be 316 address &= 0x1F;
epgmdm 0:8fd0531ae0be 317 reg = address| 0x20;
epgmdm 0:8fd0531ae0be 318 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 319 for ( i = width - 1; i >= 0; i-- ) {
epgmdm 0:8fd0531ae0be 320 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 321 }
epgmdm 0:8fd0531ae0be 322 csn = 1;
epgmdm 2:ca0a3c0bba70 323 if (debug) {
epgmdm 2:ca0a3c0bba70 324 sprintf(logMsg, " register write %d bytes to %02x (%02x) = %02x %02x %02x", width, address, status, data[0], data[1], data[2] );
epgmdm 2:ca0a3c0bba70 325 log(logMsg);
epgmdm 2:ca0a3c0bba70 326 }
epgmdm 0:8fd0531ae0be 327 }
nixonkj 6:77ead8abdd1c 328
epgmdm 0:8fd0531ae0be 329 /**
epgmdm 0:8fd0531ae0be 330 * Reads 1 byte from a register
epgmdm 0:8fd0531ae0be 331 **/
nixonkj 6:77ead8abdd1c 332 void NRF2401P::readReg( char address, char *data )
epgmdm 0:8fd0531ae0be 333 {
epgmdm 0:8fd0531ae0be 334 csn = 0;
epgmdm 0:8fd0531ae0be 335 address &= 0x1F;
epgmdm 0:8fd0531ae0be 336 status = spi->write( address );
epgmdm 0:8fd0531ae0be 337 *data = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 338 csn = 1;
nixonkj 6:77ead8abdd1c 339 if (debug && address != 0x07) { // In debug mode: print out anything other than a status request
nixonkj 6:77ead8abdd1c 340 sprintf(logMsg, " register read %02x (%02x) = %02x", address, status, *data );
nixonkj 6:77ead8abdd1c 341 log(logMsg);
nixonkj 6:77ead8abdd1c 342 }
epgmdm 0:8fd0531ae0be 343 }
nixonkj 6:77ead8abdd1c 344
epgmdm 0:8fd0531ae0be 345 /**
epgmdm 0:8fd0531ae0be 346 * Clears the status flags RX_DR, TX_DS, MAX_RT
epgmdm 0:8fd0531ae0be 347 */
nixonkj 6:77ead8abdd1c 348 void NRF2401P::clearStatus()
epgmdm 0:8fd0531ae0be 349 {
nixonkj 6:77ead8abdd1c 350 writeReg(STATUS,0x70);
epgmdm 2:ca0a3c0bba70 351 if (debug) {
epgmdm 2:ca0a3c0bba70 352 sprintf(logMsg, "Clear status (%02x)", status );
epgmdm 2:ca0a3c0bba70 353 log(logMsg);
epgmdm 2:ca0a3c0bba70 354 }
epgmdm 0:8fd0531ae0be 355 }
nixonkj 6:77ead8abdd1c 356
epgmdm 0:8fd0531ae0be 357 /**
epgmdm 0:8fd0531ae0be 358 * flushes TX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 359 */
nixonkj 6:77ead8abdd1c 360 void NRF2401P::flushTx()
epgmdm 0:8fd0531ae0be 361 {
epgmdm 0:8fd0531ae0be 362 csn = 0;
epgmdm 2:ca0a3c0bba70 363 status = spi->write( FLUSH_TX );
epgmdm 0:8fd0531ae0be 364 csn = 1;
epgmdm 0:8fd0531ae0be 365 clearStatus();
epgmdm 2:ca0a3c0bba70 366 if (debug) {
epgmdm 2:ca0a3c0bba70 367 sprintf(logMsg, "Flush TX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 368 log(logMsg);
epgmdm 2:ca0a3c0bba70 369 }
epgmdm 0:8fd0531ae0be 370 }
epgmdm 0:8fd0531ae0be 371
epgmdm 0:8fd0531ae0be 372 /**
epgmdm 0:8fd0531ae0be 373 * flushes RX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 374 */
nixonkj 6:77ead8abdd1c 375 void NRF2401P::flushRx()
epgmdm 0:8fd0531ae0be 376 {
epgmdm 0:8fd0531ae0be 377 csn = 0;
epgmdm 2:ca0a3c0bba70 378 status = spi->write( FLUSH_RX );
epgmdm 0:8fd0531ae0be 379 csn = 1;
epgmdm 2:ca0a3c0bba70 380 clearStatus();
epgmdm 2:ca0a3c0bba70 381 if (debug) {
epgmdm 2:ca0a3c0bba70 382 sprintf(logMsg, "Flush RX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 383 log(logMsg);
epgmdm 2:ca0a3c0bba70 384 }
epgmdm 0:8fd0531ae0be 385 }
nixonkj 6:77ead8abdd1c 386
epgmdm 0:8fd0531ae0be 387 /**
epgmdm 0:8fd0531ae0be 388 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 389 */
nixonkj 6:77ead8abdd1c 390 char NRF2401P::setTxMode()
epgmdm 0:8fd0531ae0be 391 {
epgmdm 0:8fd0531ae0be 392 char data;
epgmdm 0:8fd0531ae0be 393 char bit;
epgmdm 2:ca0a3c0bba70 394 if (debug) {
epgmdm 2:ca0a3c0bba70 395 sprintf(logMsg, "Set Tx Mode");
epgmdm 2:ca0a3c0bba70 396 log(logMsg);
epgmdm 2:ca0a3c0bba70 397 }
epgmdm 2:ca0a3c0bba70 398 readReg( CONFIG, &data );
epgmdm 0:8fd0531ae0be 399 data &= ~( 1 << 0 );
epgmdm 2:ca0a3c0bba70 400 flushTx();
epgmdm 2:ca0a3c0bba70 401 flushRx();
epgmdm 2:ca0a3c0bba70 402 writeReg( CONFIG, data );
epgmdm 3:afe8d307b5c3 403 writeReg( RX_ADDR_P0, txAdd, addressWidth ); // reset p0
epgmdm 2:ca0a3c0bba70 404 writeReg(EN_RXADDR,0x01); // enable pipe 0 for reading
epgmdm 0:8fd0531ae0be 405 // check
epgmdm 0:8fd0531ae0be 406 readReg( 0x00, &data );
epgmdm 0:8fd0531ae0be 407 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 408
epgmdm 0:8fd0531ae0be 409 ce=1;
epgmdm 0:8fd0531ae0be 410 wait(0.003);
nixonkj 6:77ead8abdd1c 411 if (bit == 0) {
nixonkj 6:77ead8abdd1c 412 return 0;
nixonkj 6:77ead8abdd1c 413 } else {
nixonkj 6:77ead8abdd1c 414 return 1;
nixonkj 6:77ead8abdd1c 415 }
epgmdm 0:8fd0531ae0be 416 }
epgmdm 0:8fd0531ae0be 417
epgmdm 0:8fd0531ae0be 418 /**
epgmdm 0:8fd0531ae0be 419 * Sets the number of bytes of the address width = 3,4,5
epgmdm 0:8fd0531ae0be 420 */
nixonkj 6:77ead8abdd1c 421 char NRF2401P::setAddressWidth( char width )
epgmdm 0:8fd0531ae0be 422 {
nixonkj 6:77ead8abdd1c 423 char chk=0;
epgmdm 0:8fd0531ae0be 424 addressWidth = width;
epgmdm 0:8fd0531ae0be 425 if ( ( width > 5 ) || ( width < 3 ) )
epgmdm 0:8fd0531ae0be 426 return false;
epgmdm 0:8fd0531ae0be 427 width -= 2;
nixonkj 6:77ead8abdd1c 428 writeReg( 0x03, width );
nixonkj 6:77ead8abdd1c 429 readReg( 0x03, &chk );
nixonkj 6:77ead8abdd1c 430 if (chk&0x03 == width) {
nixonkj 6:77ead8abdd1c 431 return 0;
nixonkj 6:77ead8abdd1c 432 } else {
nixonkj 6:77ead8abdd1c 433 return 1;
nixonkj 6:77ead8abdd1c 434 }
epgmdm 0:8fd0531ae0be 435 }
nixonkj 6:77ead8abdd1c 436
epgmdm 0:8fd0531ae0be 437 /**
nixonkj 6:77ead8abdd1c 438 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 439 */
epgmdm 0:8fd0531ae0be 440 char NRF2401P::setTxAddress( char *address )
epgmdm 0:8fd0531ae0be 441 {
epgmdm 2:ca0a3c0bba70 442 memcpy (txAdd,address, addressWidth);
epgmdm 0:8fd0531ae0be 443 writeReg( 0x0A, address, addressWidth ); //Write to RX_ADDR_P0
nixonkj 6:77ead8abdd1c 444 writeReg( 0x10, address, addressWidth ); //Write to TX_ADDR
nixonkj 6:77ead8abdd1c 445 return 0; // must fix this
epgmdm 0:8fd0531ae0be 446 }
epgmdm 0:8fd0531ae0be 447
epgmdm 0:8fd0531ae0be 448 /**
epgmdm 0:8fd0531ae0be 449 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 450 */
epgmdm 0:8fd0531ae0be 451 char NRF2401P::setTxAddress( long long address )
epgmdm 0:8fd0531ae0be 452 {
epgmdm 0:8fd0531ae0be 453 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 454 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 455 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 456 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 457 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 458 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 459 return setTxAddress( buff );
epgmdm 0:8fd0531ae0be 460 }
epgmdm 0:8fd0531ae0be 461
epgmdm 0:8fd0531ae0be 462 /**
epgmdm 0:8fd0531ae0be 463 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 2:ca0a3c0bba70 464 * Enables pipe for receiving;
epgmdm 0:8fd0531ae0be 465 */
epgmdm 0:8fd0531ae0be 466 char NRF2401P::setRxAddress( char *address, char pipe )
epgmdm 0:8fd0531ae0be 467 {
epgmdm 2:ca0a3c0bba70 468 if(debug) {
epgmdm 2:ca0a3c0bba70 469 log ("Set Rx Address");
epgmdm 2:ca0a3c0bba70 470 }
epgmdm 2:ca0a3c0bba70 471 if (pipe>5) return 0xff;
epgmdm 2:ca0a3c0bba70 472 if (pipe ==0) {
epgmdm 2:ca0a3c0bba70 473 memcpy (pipe0Add,address, addressWidth);
epgmdm 2:ca0a3c0bba70 474 }
epgmdm 2:ca0a3c0bba70 475
epgmdm 0:8fd0531ae0be 476 char reg = 0x0A + pipe;
epgmdm 0:8fd0531ae0be 477 switch ( pipe ) {
epgmdm 0:8fd0531ae0be 478 case ( 0 ) :
epgmdm 0:8fd0531ae0be 479 case ( 1 ) : {
nixonkj 6:77ead8abdd1c 480 writeReg( reg, address, addressWidth ); //Write to RX_ADDR_P0 or _P1
epgmdm 0:8fd0531ae0be 481 break;
epgmdm 0:8fd0531ae0be 482 }
epgmdm 0:8fd0531ae0be 483 case ( 2 ) :
epgmdm 0:8fd0531ae0be 484 case ( 3 ) :
epgmdm 0:8fd0531ae0be 485 case ( 4 ) :
epgmdm 0:8fd0531ae0be 486 case ( 5 ) : {
nixonkj 6:77ead8abdd1c 487 writeReg( reg, address, 1 ); //Write to RX_ADDR_P2 ... _P5
epgmdm 0:8fd0531ae0be 488 break;
epgmdm 0:8fd0531ae0be 489 }
epgmdm 0:8fd0531ae0be 490
epgmdm 0:8fd0531ae0be 491 }
epgmdm 2:ca0a3c0bba70 492 readReg(EN_RXADDR,&reg);
epgmdm 2:ca0a3c0bba70 493 reg |= (1<<pipe);
epgmdm 2:ca0a3c0bba70 494 writeReg( EN_RXADDR,reg ); //Enable the pipe
nixonkj 6:77ead8abdd1c 495 return 0; // Must fix this
epgmdm 0:8fd0531ae0be 496 }
epgmdm 0:8fd0531ae0be 497
epgmdm 0:8fd0531ae0be 498 /**
epgmdm 0:8fd0531ae0be 499 * Sets the address of pipe (<=5), uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 500 */
epgmdm 0:8fd0531ae0be 501 char NRF2401P::setRxAddress( long long address, char pipe )
epgmdm 0:8fd0531ae0be 502 {
epgmdm 0:8fd0531ae0be 503 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 504 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 505 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 506 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 507 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 508 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 509 return setRxAddress( buff, pipe );
epgmdm 0:8fd0531ae0be 510 }
nixonkj 6:77ead8abdd1c 511
epgmdm 1:ff53b1ac3bad 512 /**
epgmdm 1:ff53b1ac3bad 513 *checks the status flag
epgmdm 1:ff53b1ac3bad 514 */
epgmdm 1:ff53b1ac3bad 515 char NRF2401P::checkStatus()
epgmdm 1:ff53b1ac3bad 516 {
epgmdm 1:ff53b1ac3bad 517 readReg(0x07,&status);
epgmdm 1:ff53b1ac3bad 518 return status;
epgmdm 1:ff53b1ac3bad 519 }
nixonkj 6:77ead8abdd1c 520
epgmdm 1:ff53b1ac3bad 521 /**
epgmdm 1:ff53b1ac3bad 522 * checks if Ack data available.
epgmdm 1:ff53b1ac3bad 523 */
epgmdm 1:ff53b1ac3bad 524 bool NRF2401P::isAckData()
epgmdm 1:ff53b1ac3bad 525 {
epgmdm 1:ff53b1ac3bad 526 char fifo;
epgmdm 1:ff53b1ac3bad 527 readReg(0x17,&fifo);
epgmdm 1:ff53b1ac3bad 528 bool isData = !(fifo&0x01);
epgmdm 1:ff53b1ac3bad 529 return isData;
epgmdm 1:ff53b1ac3bad 530 }
epgmdm 0:8fd0531ae0be 531
epgmdm 1:ff53b1ac3bad 532 /**
epgmdm 1:ff53b1ac3bad 533 * checks if RX data available.
epgmdm 1:ff53b1ac3bad 534 */
epgmdm 0:8fd0531ae0be 535 bool NRF2401P::isRxData()
epgmdm 0:8fd0531ae0be 536 {
epgmdm 1:ff53b1ac3bad 537 checkStatus();
epgmdm 0:8fd0531ae0be 538 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 539 return isData;
epgmdm 0:8fd0531ae0be 540 }
nixonkj 6:77ead8abdd1c 541
epgmdm 0:8fd0531ae0be 542 /**
epgmdm 0:8fd0531ae0be 543 * returns the width of the dynamic payload
epgmdm 0:8fd0531ae0be 544 */
epgmdm 0:8fd0531ae0be 545 char NRF2401P::getRxWidth()
epgmdm 0:8fd0531ae0be 546 {
epgmdm 0:8fd0531ae0be 547 char width;
epgmdm 0:8fd0531ae0be 548 if (dynamic) {
epgmdm 0:8fd0531ae0be 549 csn = 0;
epgmdm 0:8fd0531ae0be 550 status = spi->write( 0x60 );
epgmdm 0:8fd0531ae0be 551 width = spi->write(0x00);
epgmdm 0:8fd0531ae0be 552 csn = 1;
epgmdm 0:8fd0531ae0be 553
epgmdm 0:8fd0531ae0be 554 if (width>32) {
epgmdm 0:8fd0531ae0be 555 flushRx();
epgmdm 0:8fd0531ae0be 556 width=0;
epgmdm 0:8fd0531ae0be 557 }
epgmdm 0:8fd0531ae0be 558 } else {
nixonkj 6:77ead8abdd1c 559 readReg(0x12,&width); // width of p1
epgmdm 0:8fd0531ae0be 560 }
epgmdm 1:ff53b1ac3bad 561 // width=18;
epgmdm 0:8fd0531ae0be 562 return width;
epgmdm 0:8fd0531ae0be 563 }
nixonkj 6:77ead8abdd1c 564
epgmdm 0:8fd0531ae0be 565 /**
epgmdm 0:8fd0531ae0be 566 * return message in buffer, mem for buffer must have been allocated.
epgmdm 0:8fd0531ae0be 567 * Return value is number of bytes of buffer
epgmdm 0:8fd0531ae0be 568 */
epgmdm 0:8fd0531ae0be 569 char NRF2401P::getRxData(char * buffer)
epgmdm 0:8fd0531ae0be 570 {
epgmdm 0:8fd0531ae0be 571 char address = 0x61;
epgmdm 0:8fd0531ae0be 572 char width;
epgmdm 0:8fd0531ae0be 573 width = getRxWidth();
epgmdm 0:8fd0531ae0be 574 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 575 if (isData) {
epgmdm 0:8fd0531ae0be 576 csn = 0;
epgmdm 0:8fd0531ae0be 577 int i;
epgmdm 0:8fd0531ae0be 578 // set up for reading
epgmdm 0:8fd0531ae0be 579 status = spi->write( address );
epgmdm 0:8fd0531ae0be 580 for ( i = 0; i <= width; i++ ) {
epgmdm 0:8fd0531ae0be 581 buffer[i]=spi->write(0x00 );
epgmdm 0:8fd0531ae0be 582 }
epgmdm 0:8fd0531ae0be 583 csn = 1;
nixonkj 6:77ead8abdd1c 584 if (debug) {
nixonkj 6:77ead8abdd1c 585 sprintf(logMsg, "Receive data %d bytes", width );
nixonkj 6:77ead8abdd1c 586 log(logMsg);
nixonkj 6:77ead8abdd1c 587 }
epgmdm 0:8fd0531ae0be 588 clearStatus();
epgmdm 0:8fd0531ae0be 589 return width;
epgmdm 0:8fd0531ae0be 590 } else {
nixonkj 6:77ead8abdd1c 591 if (debug) {
nixonkj 6:77ead8abdd1c 592 sprintf(logMsg, "Receive NO data %d bytes", width );
nixonkj 6:77ead8abdd1c 593 log(logMsg);
nixonkj 6:77ead8abdd1c 594 }
epgmdm 0:8fd0531ae0be 595 clearStatus();
epgmdm 0:8fd0531ae0be 596 return 0;
epgmdm 0:8fd0531ae0be 597 }
epgmdm 0:8fd0531ae0be 598 }
epgmdm 0:8fd0531ae0be 599
epgmdm 0:8fd0531ae0be 600 /**
epgmdm 0:8fd0531ae0be 601 * Sets all the receive pipes to dynamic payload length
epgmdm 0:8fd0531ae0be 602 */
epgmdm 2:ca0a3c0bba70 603 void NRF2401P::setDynamicPayload()
epgmdm 0:8fd0531ae0be 604 {
epgmdm 0:8fd0531ae0be 605 dynamic = true;
epgmdm 2:ca0a3c0bba70 606 writeReg(FEATURE,0x07); // Enable Dyn payload, Payload with Ack and w_tx_noack command
epgmdm 2:ca0a3c0bba70 607 writeReg(EN_AA,0x3f); // EN_AA regi for P1 and P0
epgmdm 2:ca0a3c0bba70 608 writeReg(DYNPD, 0x1F);
epgmdm 0:8fd0531ae0be 609 }
epgmdm 2:ca0a3c0bba70 610
epgmdm 0:8fd0531ae0be 611 /**
epgmdm 0:8fd0531ae0be 612 * Sets PWR_UP = 1;
nixonkj 6:77ead8abdd1c 613 * return 0 on success
epgmdm 0:8fd0531ae0be 614 */
nixonkj 6:77ead8abdd1c 615 char NRF2401P::setPwrUp()
epgmdm 0:8fd0531ae0be 616 {
epgmdm 0:8fd0531ae0be 617 char data;
epgmdm 0:8fd0531ae0be 618 char bit;
epgmdm 0:8fd0531ae0be 619 ce=1;
epgmdm 2:ca0a3c0bba70 620 readReg( CONFIG, &data );
epgmdm 2:ca0a3c0bba70 621 if ((data>>1) &0x01) {
epgmdm 2:ca0a3c0bba70 622 return true; // Already powered up
epgmdm 2:ca0a3c0bba70 623 };
epgmdm 0:8fd0531ae0be 624 data |= ( 0x02 );
epgmdm 0:8fd0531ae0be 625 writeReg( 0x00, data );
epgmdm 0:8fd0531ae0be 626 // check
epgmdm 0:8fd0531ae0be 627 readReg( 0x00, &data );
epgmdm 0:8fd0531ae0be 628 bit = ( data >> 1 ) & 1;
epgmdm 2:ca0a3c0bba70 629
epgmdm 0:8fd0531ae0be 630 wait(0.005); // wait 5ms
epgmdm 2:ca0a3c0bba70 631 if(debug) {
epgmdm 2:ca0a3c0bba70 632 sprintf(logMsg, "Set PWR_UP to %x", bit);
epgmdm 2:ca0a3c0bba70 633 log(logMsg);
epgmdm 2:ca0a3c0bba70 634 }
nixonkj 6:77ead8abdd1c 635 if (bit == 1) {
nixonkj 6:77ead8abdd1c 636 return 0;
nixonkj 6:77ead8abdd1c 637 } else {
nixonkj 6:77ead8abdd1c 638 return 1;
nixonkj 6:77ead8abdd1c 639 }
nixonkj 6:77ead8abdd1c 640 }
epgmdm 2:ca0a3c0bba70 641
epgmdm 0:8fd0531ae0be 642 /**
epgmdm 0:8fd0531ae0be 643 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 644 */
nixonkj 6:77ead8abdd1c 645 char NRF2401P::setRxMode()
epgmdm 0:8fd0531ae0be 646 {
epgmdm 0:8fd0531ae0be 647 char data;
epgmdm 0:8fd0531ae0be 648 char bit;
epgmdm 0:8fd0531ae0be 649 ce=1;
epgmdm 0:8fd0531ae0be 650 readReg( 0x00, &data );
epgmdm 2:ca0a3c0bba70 651 data |= ( 0x01 );
epgmdm 2:ca0a3c0bba70 652
epgmdm 0:8fd0531ae0be 653 writeReg( 0x00, data );
epgmdm 3:afe8d307b5c3 654 if (pipe0Add[0]|pipe0Add[1]|pipe0Add[2]|pipe0Add[3]|pipe0Add[4] >0) {
epgmdm 3:afe8d307b5c3 655 setRxAddress(pipe0Add,0);
epgmdm 2:ca0a3c0bba70 656 }
epgmdm 0:8fd0531ae0be 657 // check
epgmdm 0:8fd0531ae0be 658 readReg( 0x00, &data );
epgmdm 0:8fd0531ae0be 659 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 660
epgmdm 2:ca0a3c0bba70 661 wait (0.001);
epgmdm 0:8fd0531ae0be 662 flushRx();
epgmdm 2:ca0a3c0bba70 663 flushTx();
epgmdm 2:ca0a3c0bba70 664 if (debug) {
epgmdm 2:ca0a3c0bba70 665 sprintf(logMsg, " set PRIM_RX to %x", bit);
epgmdm 2:ca0a3c0bba70 666 log(logMsg);
epgmdm 2:ca0a3c0bba70 667 }
nixonkj 6:77ead8abdd1c 668 if ( bit == 1 ) {
nixonkj 6:77ead8abdd1c 669 return 0;
nixonkj 6:77ead8abdd1c 670 } else {
nixonkj 6:77ead8abdd1c 671 return 1;
nixonkj 6:77ead8abdd1c 672 }
epgmdm 0:8fd0531ae0be 673 }
nixonkj 6:77ead8abdd1c 674
epgmdm 0:8fd0531ae0be 675 /**
epgmdm 0:8fd0531ae0be 676 * Prints status string
epgmdm 0:8fd0531ae0be 677 */
epgmdm 0:8fd0531ae0be 678 char * NRF2401P::statusString()
epgmdm 0:8fd0531ae0be 679 {
epgmdm 0:8fd0531ae0be 680 char *msg;
epgmdm 0:8fd0531ae0be 681 msg = statusS;
epgmdm 0:8fd0531ae0be 682 if (((status>>1) & 0x07)==0x07) {
epgmdm 0:8fd0531ae0be 683 sprintf(msg,"RX empty");
epgmdm 0:8fd0531ae0be 684 } else {
epgmdm 0:8fd0531ae0be 685 sprintf(msg,"pipe %02x",(status>>1) & 0x07);
epgmdm 0:8fd0531ae0be 686 }
epgmdm 0:8fd0531ae0be 687
epgmdm 0:8fd0531ae0be 688 if ((status>>6)&0x01) strcat(msg," RX_DR,");
epgmdm 0:8fd0531ae0be 689 if ((status>>5)&0x01) strcat(msg," TX_DS,");
epgmdm 0:8fd0531ae0be 690 if ((status>>4)&0x01) strcat(msg," MAX_RT,");
epgmdm 0:8fd0531ae0be 691 if ((status>>0)&0x01) strcat(msg," TX_FLL,");
epgmdm 0:8fd0531ae0be 692
epgmdm 0:8fd0531ae0be 693 return msg;
epgmdm 0:8fd0531ae0be 694 }