Damien Frost / NRF2401P

My fork during debugging.

Fork of NRF2401P by Malcolm McCulloch

NRF2401P.cpp@14:976a876819ae, 2015-07-11 (annotated)

Committer:
nixonkj
Date:
Sat Jul 11 22:17:36 2015 +0000
Revision:
14:976a876819ae
Parent:
13:5cbc726f2bbb
Child:
16:a9b83d2b6915
Minro housekeeping.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
epgmdm 0:8fd0531ae0be 1 /**
epgmdm 0:8fd0531ae0be 2 *@section DESCRIPTION
epgmdm 0:8fd0531ae0be 3 * mbed NRF2401+ Library
epgmdm 0:8fd0531ae0be 4 *@section LICENSE
epgmdm 0:8fd0531ae0be 5 * Copyright (c) 2015, Malcolm McCulloch
epgmdm 0:8fd0531ae0be 6 *
epgmdm 0:8fd0531ae0be 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
epgmdm 0:8fd0531ae0be 8 * of this software and associated documentation files (the "Software"), to deal
epgmdm 0:8fd0531ae0be 9 * in the Software without restriction, including without limitation the rights
epgmdm 0:8fd0531ae0be 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
epgmdm 0:8fd0531ae0be 11 * copies of the Software, and to permit persons to whom the Software is
epgmdm 0:8fd0531ae0be 12 * furnished to do so, subject to the following conditions:
epgmdm 0:8fd0531ae0be 13 *
epgmdm 0:8fd0531ae0be 14 * The above copyright notice and this permission notice shall be included in
epgmdm 0:8fd0531ae0be 15 * all copies or substantial portions of the Software.
epgmdm 0:8fd0531ae0be 16 *
epgmdm 0:8fd0531ae0be 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
epgmdm 0:8fd0531ae0be 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
epgmdm 0:8fd0531ae0be 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
epgmdm 0:8fd0531ae0be 20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
epgmdm 0:8fd0531ae0be 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
epgmdm 0:8fd0531ae0be 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
epgmdm 0:8fd0531ae0be 23 * THE SOFTWARE.
epgmdm 0:8fd0531ae0be 24 * @file "NRF2401P.cpp"
epgmdm 0:8fd0531ae0be 25 */
epgmdm 2:ca0a3c0bba70 26 #include "mbed.h"
epgmdm 2:ca0a3c0bba70 27 #include "NRF2401P.h"
epgmdm 2:ca0a3c0bba70 28 #include "nRF24l01.h"
epgmdm 0:8fd0531ae0be 29
epgmdm 0:8fd0531ae0be 30 NRF2401P::NRF2401P ( PinName mosi, PinName miso, PinName sclk, PinName _csn, PinName _ce ) :
epgmdm 0:8fd0531ae0be 31 csn( DigitalOut( _csn ) ), ce( DigitalOut( _ce ) )
epgmdm 0:8fd0531ae0be 32 {
epgmdm 0:8fd0531ae0be 33 addressWidth = 5;
epgmdm 0:8fd0531ae0be 34 pc = new Serial( USBTX, USBRX ); // tx, rx
nixonkj 6:77ead8abdd1c 35 if (debug) {
nixonkj 6:77ead8abdd1c 36 sprintf(logMsg, "Initialise" );
nixonkj 6:77ead8abdd1c 37 log(logMsg);
nixonkj 6:77ead8abdd1c 38 }
epgmdm 0:8fd0531ae0be 39 spi = new SPI( mosi, miso, sclk, NC ); //SPI (PinName mosi, PinName miso, PinName sclk, PinName _unused=NC)
epgmdm 0:8fd0531ae0be 40 spi->frequency( 10000000 ); // 1MHZ max 10 MHz
epgmdm 0:8fd0531ae0be 41 spi->format( 8, 0 ); // 0: 0e 08; 1: 0e 00; 2:0e 00 ;3:1c 00
epgmdm 0:8fd0531ae0be 42 csn = 1;
epgmdm 0:8fd0531ae0be 43 ce = 0;
epgmdm 0:8fd0531ae0be 44 dynamic = false;
nixonkj 6:77ead8abdd1c 45 debug = false;
nixonkj 6:77ead8abdd1c 46 }
epgmdm 0:8fd0531ae0be 47
nixonkj 6:77ead8abdd1c 48 void NRF2401P::log(char *msg)
epgmdm 0:8fd0531ae0be 49 {
epgmdm 0:8fd0531ae0be 50 if(debug) {
nixonkj 8:3e027705ce23 51 printf("\t <%s \t %s>\n\r", statusString(), msg);
epgmdm 1:ff53b1ac3bad 52 wait(0.01);
nixonkj 6:77ead8abdd1c 53 }
epgmdm 0:8fd0531ae0be 54 }
epgmdm 0:8fd0531ae0be 55
epgmdm 0:8fd0531ae0be 56 void NRF2401P::scratch()
epgmdm 0:8fd0531ae0be 57 {
epgmdm 0:8fd0531ae0be 58 int status = 0;
epgmdm 0:8fd0531ae0be 59 int register1 = 0;
epgmdm 0:8fd0531ae0be 60 ce = 0;
epgmdm 0:8fd0531ae0be 61 for ( char i = 0; i < 24; i++ ) {
epgmdm 0:8fd0531ae0be 62 csn = 0;
epgmdm 0:8fd0531ae0be 63 //wait_us(100);
epgmdm 0:8fd0531ae0be 64 status = spi->write( i );
epgmdm 0:8fd0531ae0be 65 register1 = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 66 csn = 1;
epgmdm 0:8fd0531ae0be 67 sprintf(logMsg, " register %02x (%02x) = %02x", i, status, register1 );
epgmdm 0:8fd0531ae0be 68 log(logMsg);
epgmdm 0:8fd0531ae0be 69 }
nixonkj 6:77ead8abdd1c 70 }
epgmdm 0:8fd0531ae0be 71
epgmdm 0:8fd0531ae0be 72 /**
epgmdm 2:ca0a3c0bba70 73 * start here to configure the basics of the NRF
epgmdm 2:ca0a3c0bba70 74 */
epgmdm 2:ca0a3c0bba70 75 void NRF2401P::start()
epgmdm 2:ca0a3c0bba70 76 {
nixonkj 8:3e027705ce23 77 writeReg(CONFIG, 0x0c); // set 16 bit crc
nixonkj 8:3e027705ce23 78 setTxRetry(0x01, 0x0f); // 500 uS, 15 retries
nixonkj 8:3e027705ce23 79 setRadio(0, 0x03); // 1MB/S 0dB
epgmdm 2:ca0a3c0bba70 80 setDynamicPayload();
epgmdm 2:ca0a3c0bba70 81 setChannel(76); // should be clear?
epgmdm 2:ca0a3c0bba70 82 setAddressWidth(5);
epgmdm 2:ca0a3c0bba70 83 flushRx();
epgmdm 2:ca0a3c0bba70 84 flushTx();
epgmdm 2:ca0a3c0bba70 85 setPwrUp();
epgmdm 2:ca0a3c0bba70 86 setTxMode(); // just make sure no spurious reads....
nixonkj 6:77ead8abdd1c 87 }
epgmdm 2:ca0a3c0bba70 88
epgmdm 2:ca0a3c0bba70 89 /**
nixonkj 8:3e027705ce23 90 * Sets up a receiver using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 91 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 92 */
epgmdm 2:ca0a3c0bba70 93 void NRF2401P::quickRxSetup(int channel,long long addrRx)
epgmdm 0:8fd0531ae0be 94 {
epgmdm 2:ca0a3c0bba70 95 start();
epgmdm 0:8fd0531ae0be 96 setChannel(channel);
epgmdm 2:ca0a3c0bba70 97 setRxAddress(addrRx,1);
epgmdm 0:8fd0531ae0be 98 setRxMode();
epgmdm 0:8fd0531ae0be 99 ce=1;
nixonkj 6:77ead8abdd1c 100 wait(0.001f);
epgmdm 0:8fd0531ae0be 101 }
nixonkj 6:77ead8abdd1c 102
epgmdm 0:8fd0531ae0be 103 /**
epgmdm 0:8fd0531ae0be 104 * Sets up for receive of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 105 */
epgmdm 0:8fd0531ae0be 106 char NRF2401P::testReceive()
epgmdm 0:8fd0531ae0be 107 {
epgmdm 0:8fd0531ae0be 108 char message[64];
epgmdm 0:8fd0531ae0be 109 char width;
epgmdm 0:8fd0531ae0be 110 int channel = 0x12;
epgmdm 0:8fd0531ae0be 111 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 112 debug = true;
epgmdm 0:8fd0531ae0be 113 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 114
epgmdm 0:8fd0531ae0be 115 while (1) {
epgmdm 0:8fd0531ae0be 116 while (!isRxData()) {
epgmdm 0:8fd0531ae0be 117 //wait(0.5);
epgmdm 0:8fd0531ae0be 118 };
epgmdm 0:8fd0531ae0be 119 width=getRxData(message);
epgmdm 0:8fd0531ae0be 120 message[width]='\0';
epgmdm 0:8fd0531ae0be 121 sprintf(logMsg,"Received= [%s]",message);
epgmdm 0:8fd0531ae0be 122 log(logMsg);
nixonkj 6:77ead8abdd1c 123 }
epgmdm 0:8fd0531ae0be 124 }
epgmdm 0:8fd0531ae0be 125
nixonkj 6:77ead8abdd1c 126 char NRF2401P::setTxRetry(char delay, char numTries)
epgmdm 2:ca0a3c0bba70 127 {
epgmdm 2:ca0a3c0bba70 128 char val = (delay&0xf)<<4 | (numTries&0xf);
nixonkj 6:77ead8abdd1c 129 char chk;
nixonkj 8:3e027705ce23 130 writeReg(SETUP_RETR, val);
nixonkj 8:3e027705ce23 131 readReg(SETUP_RETR, &chk);
nixonkj 6:77ead8abdd1c 132 if (chk&0xff == val) {
nixonkj 6:77ead8abdd1c 133 return 0;
nixonkj 6:77ead8abdd1c 134 } else {
nixonkj 6:77ead8abdd1c 135 return 1;
nixonkj 6:77ead8abdd1c 136 }
epgmdm 2:ca0a3c0bba70 137 }
epgmdm 2:ca0a3c0bba70 138
epgmdm 2:ca0a3c0bba70 139 /**
epgmdm 0:8fd0531ae0be 140 * Sets up a transmitter using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 141 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 142 */
epgmdm 0:8fd0531ae0be 143 void NRF2401P::quickTxSetup(int channel,long long addr)
epgmdm 0:8fd0531ae0be 144 {
epgmdm 2:ca0a3c0bba70 145 start();
epgmdm 0:8fd0531ae0be 146 setChannel(channel);
epgmdm 2:ca0a3c0bba70 147 setTxAddress(addr);
epgmdm 0:8fd0531ae0be 148 setTxMode();
epgmdm 0:8fd0531ae0be 149 ce=1;
epgmdm 0:8fd0531ae0be 150 wait (0.0016f); // wait for pll to settle
epgmdm 0:8fd0531ae0be 151 }
epgmdm 0:8fd0531ae0be 152
epgmdm 0:8fd0531ae0be 153 /**
epgmdm 0:8fd0531ae0be 154 * Sets up for transmit of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 155 */
epgmdm 0:8fd0531ae0be 156 char NRF2401P::testTransmit()
epgmdm 0:8fd0531ae0be 157 {
epgmdm 0:8fd0531ae0be 158 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 159 int channel = 0x12;
epgmdm 0:8fd0531ae0be 160 char data[32] ;
epgmdm 0:8fd0531ae0be 161 int i=0;
epgmdm 0:8fd0531ae0be 162 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 163 while (1) {
epgmdm 0:8fd0531ae0be 164 sprintf(data," packet %03d", i++ |100);
epgmdm 0:8fd0531ae0be 165 transmitData(data,18);
epgmdm 0:8fd0531ae0be 166 wait (1.0);
epgmdm 0:8fd0531ae0be 167 }
nixonkj 6:77ead8abdd1c 168 }
epgmdm 0:8fd0531ae0be 169
nixonkj 6:77ead8abdd1c 170 char NRF2401P::setRadio(char speed, char power)
epgmdm 0:8fd0531ae0be 171 {
nixonkj 6:77ead8abdd1c 172 char val=0, chk=0;
nixonkj 8:3e027705ce23 173 if (debug) {
nixonkj 8:3e027705ce23 174 sprintf(logMsg, "Set radio");
nixonkj 8:3e027705ce23 175 log(logMsg);
nixonkj 8:3e027705ce23 176 }
epgmdm 0:8fd0531ae0be 177 if (speed & 0x02) {
epgmdm 0:8fd0531ae0be 178 val |= (1<<5);
epgmdm 0:8fd0531ae0be 179 }
epgmdm 0:8fd0531ae0be 180 val |= (speed & 0x01)<<3;
epgmdm 0:8fd0531ae0be 181
nixonkj 6:77ead8abdd1c 182 val |= ((power & 0x03)<<1);
nixonkj 6:77ead8abdd1c 183 printf("\n\r");
nixonkj 6:77ead8abdd1c 184
nixonkj 8:3e027705ce23 185 writeReg(RF_SETUP, val);
epgmdm 0:8fd0531ae0be 186
nixonkj 6:77ead8abdd1c 187 // read register to verify settings
nixonkj 8:3e027705ce23 188 readReg(RF_SETUP, &chk);
nixonkj 6:77ead8abdd1c 189 if (chk&0x2E == val) {
nixonkj 6:77ead8abdd1c 190 return 0;
nixonkj 6:77ead8abdd1c 191 } else {
nixonkj 6:77ead8abdd1c 192 return 1;
nixonkj 6:77ead8abdd1c 193 }
epgmdm 0:8fd0531ae0be 194 }
nixonkj 6:77ead8abdd1c 195
epgmdm 0:8fd0531ae0be 196 char NRF2401P::setChannel(char chan)
epgmdm 0:8fd0531ae0be 197 {
nixonkj 6:77ead8abdd1c 198 char chk=0;
nixonkj 6:77ead8abdd1c 199 if (debug) {
nixonkj 6:77ead8abdd1c 200 sprintf(logMsg, "Set channel");
nixonkj 6:77ead8abdd1c 201 log(logMsg);
nixonkj 6:77ead8abdd1c 202 }
nixonkj 8:3e027705ce23 203 writeReg(RF_CH, (chan&0x7f));
nixonkj 8:3e027705ce23 204 readReg(RF_CH, &chk);
nixonkj 6:77ead8abdd1c 205 if (chk&0x7f == chan&0x7f) {
nixonkj 6:77ead8abdd1c 206 return 0;
nixonkj 6:77ead8abdd1c 207 } else {
nixonkj 6:77ead8abdd1c 208 return 1;
nixonkj 6:77ead8abdd1c 209 }
epgmdm 0:8fd0531ae0be 210 }
nixonkj 6:77ead8abdd1c 211
nixonkj 13:5cbc726f2bbb 212 bool NRF2401P::isRPDset()
nixonkj 13:5cbc726f2bbb 213 {
nixonkj 13:5cbc726f2bbb 214 char val=0;
nixonkj 13:5cbc726f2bbb 215 if (debug) {
nixonkj 13:5cbc726f2bbb 216 sprintf(logMsg, "Get RPD");
nixonkj 13:5cbc726f2bbb 217 log(logMsg);
nixonkj 13:5cbc726f2bbb 218 }
nixonkj 13:5cbc726f2bbb 219 readReg(RPD, &val);
nixonkj 13:5cbc726f2bbb 220 if (val == 1) {
nixonkj 13:5cbc726f2bbb 221 return true;
nixonkj 13:5cbc726f2bbb 222 } else {
nixonkj 13:5cbc726f2bbb 223 return false;
nixonkj 13:5cbc726f2bbb 224 }
nixonkj 13:5cbc726f2bbb 225 }
nixonkj 13:5cbc726f2bbb 226
epgmdm 0:8fd0531ae0be 227 /**
epgmdm 0:8fd0531ae0be 228 * Transmits width bytes of data. width <32
epgmdm 0:8fd0531ae0be 229 */
nixonkj 6:77ead8abdd1c 230 char NRF2401P::transmitData( char *data, char width )
epgmdm 0:8fd0531ae0be 231 {
nixonkj 6:77ead8abdd1c 232 if (width>32)
nixonkj 6:77ead8abdd1c 233 return 0;
nixonkj 6:77ead8abdd1c 234 checkStatus();
nixonkj 6:77ead8abdd1c 235 if ((status>>4)&1) { // Max retries - flush tx
nixonkj 6:77ead8abdd1c 236 flushTx();
nixonkj 6:77ead8abdd1c 237 }
epgmdm 2:ca0a3c0bba70 238 //clearStatus();
epgmdm 2:ca0a3c0bba70 239 //ce = 1;
epgmdm 0:8fd0531ae0be 240 csn = 0;
nixonkj 8:3e027705ce23 241 char address = 0xA0;
epgmdm 0:8fd0531ae0be 242 int i;
epgmdm 0:8fd0531ae0be 243 // set up for writing
epgmdm 0:8fd0531ae0be 244 status = spi->write( address );
epgmdm 0:8fd0531ae0be 245 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 246 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 247 }
epgmdm 0:8fd0531ae0be 248 csn = 1;
epgmdm 3:afe8d307b5c3 249 wait(0.001);
epgmdm 3:afe8d307b5c3 250 if (debug) {
nixonkj 6:77ead8abdd1c 251 sprintf(logMsg, " Transmit data %d bytes to %02x (%02x) = %10s", width, address, status, data );
epgmdm 3:afe8d307b5c3 252 log(logMsg);
epgmdm 2:ca0a3c0bba70 253 }
epgmdm 0:8fd0531ae0be 254 return status;
epgmdm 0:8fd0531ae0be 255 }
epgmdm 0:8fd0531ae0be 256
epgmdm 0:8fd0531ae0be 257 /**
epgmdm 0:8fd0531ae0be 258 * sets acknowledge data width bytes of data. width <32
epgmdm 0:8fd0531ae0be 259 */
epgmdm 1:ff53b1ac3bad 260 char NRF2401P::acknowledgeData( char *data, char width, char pipe )
epgmdm 0:8fd0531ae0be 261 {
epgmdm 0:8fd0531ae0be 262 ce = 1;
epgmdm 0:8fd0531ae0be 263 csn = 0;
epgmdm 2:ca0a3c0bba70 264 //writeReg(0x1d,0x06); // enable payload with ack
epgmdm 2:ca0a3c0bba70 265 char address = W_ACK_PAYLOAD | (pipe&0x07);
epgmdm 0:8fd0531ae0be 266 int i;
epgmdm 0:8fd0531ae0be 267 // set up for writing
epgmdm 3:afe8d307b5c3 268 csn = 0;
epgmdm 0:8fd0531ae0be 269 status = spi->write( address );
epgmdm 0:8fd0531ae0be 270 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 271 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 272 }
epgmdm 0:8fd0531ae0be 273 csn = 1;
epgmdm 3:afe8d307b5c3 274 if (debug) {
epgmdm 3:afe8d307b5c3 275 sprintf(logMsg, " acknowledge data %d bytes to %02x (%02x) = %c", width, address, status, *data );
epgmdm 3:afe8d307b5c3 276 log(logMsg);
epgmdm 2:ca0a3c0bba70 277 }
epgmdm 0:8fd0531ae0be 278 return status;
nixonkj 6:77ead8abdd1c 279 }
epgmdm 0:8fd0531ae0be 280
epgmdm 0:8fd0531ae0be 281 /**
epgmdm 0:8fd0531ae0be 282 * Writes 1 byte data to a register
epgmdm 0:8fd0531ae0be 283 **/
nixonkj 6:77ead8abdd1c 284 void NRF2401P::writeReg( char address, char data )
epgmdm 0:8fd0531ae0be 285 {
epgmdm 0:8fd0531ae0be 286 char reg;
epgmdm 0:8fd0531ae0be 287 csn = 0;
epgmdm 0:8fd0531ae0be 288 address &= 0x1F;
nixonkj 8:3e027705ce23 289 reg = address | W_REGISTER;
epgmdm 0:8fd0531ae0be 290 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 291 spi->write( data );
epgmdm 0:8fd0531ae0be 292 csn = 1;
nixonkj 6:77ead8abdd1c 293 if (debug) {
nixonkj 6:77ead8abdd1c 294 sprintf(logMsg, " register write %02x (%02x) = %02x", address, status, data );
nixonkj 6:77ead8abdd1c 295 log(logMsg);
nixonkj 6:77ead8abdd1c 296 }
epgmdm 0:8fd0531ae0be 297 }
nixonkj 6:77ead8abdd1c 298
epgmdm 0:8fd0531ae0be 299 /**
epgmdm 0:8fd0531ae0be 300 * Writes width bytes data to a register, ls byte to ms byte /for adressess
epgmdm 0:8fd0531ae0be 301 **/
nixonkj 6:77ead8abdd1c 302 void NRF2401P::writeReg( char address, char *data, char width )
epgmdm 0:8fd0531ae0be 303 {
epgmdm 0:8fd0531ae0be 304 char reg;
epgmdm 0:8fd0531ae0be 305 csn = 0;
epgmdm 0:8fd0531ae0be 306 int i;
epgmdm 0:8fd0531ae0be 307 // set up for writing
epgmdm 0:8fd0531ae0be 308 address &= 0x1F;
nixonkj 8:3e027705ce23 309 reg = address| W_REGISTER;
epgmdm 0:8fd0531ae0be 310 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 311 for ( i = width - 1; i >= 0; i-- ) {
epgmdm 0:8fd0531ae0be 312 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 313 }
epgmdm 0:8fd0531ae0be 314 csn = 1;
epgmdm 2:ca0a3c0bba70 315 if (debug) {
epgmdm 2:ca0a3c0bba70 316 sprintf(logMsg, " register write %d bytes to %02x (%02x) = %02x %02x %02x", width, address, status, data[0], data[1], data[2] );
epgmdm 2:ca0a3c0bba70 317 log(logMsg);
epgmdm 2:ca0a3c0bba70 318 }
epgmdm 0:8fd0531ae0be 319 }
nixonkj 6:77ead8abdd1c 320
epgmdm 0:8fd0531ae0be 321 /**
epgmdm 0:8fd0531ae0be 322 * Reads 1 byte from a register
epgmdm 0:8fd0531ae0be 323 **/
nixonkj 6:77ead8abdd1c 324 void NRF2401P::readReg( char address, char *data )
epgmdm 0:8fd0531ae0be 325 {
epgmdm 0:8fd0531ae0be 326 csn = 0;
epgmdm 0:8fd0531ae0be 327 address &= 0x1F;
epgmdm 0:8fd0531ae0be 328 status = spi->write( address );
epgmdm 0:8fd0531ae0be 329 *data = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 330 csn = 1;
nixonkj 6:77ead8abdd1c 331 if (debug && address != 0x07) { // In debug mode: print out anything other than a status request
nixonkj 6:77ead8abdd1c 332 sprintf(logMsg, " register read %02x (%02x) = %02x", address, status, *data );
nixonkj 6:77ead8abdd1c 333 log(logMsg);
nixonkj 6:77ead8abdd1c 334 }
epgmdm 0:8fd0531ae0be 335 }
nixonkj 6:77ead8abdd1c 336
epgmdm 0:8fd0531ae0be 337 /**
nixonkj 10:8a217441c38e 338 * Reads n bytes from a register
nixonkj 10:8a217441c38e 339 **/
nixonkj 10:8a217441c38e 340 void NRF2401P::readReg( char address, char *data, char width )
nixonkj 10:8a217441c38e 341 {
nixonkj 10:8a217441c38e 342 char reg;
nixonkj 10:8a217441c38e 343 csn = 0;
nixonkj 10:8a217441c38e 344 int i;
nixonkj 10:8a217441c38e 345 // set up for writing
nixonkj 10:8a217441c38e 346 address &= 0x1F;
nixonkj 10:8a217441c38e 347 reg = address| R_REGISTER;
nixonkj 10:8a217441c38e 348 status = spi->write( reg );
nixonkj 10:8a217441c38e 349 for ( i = width - 1; i >= 0; i-- ) {
nixonkj 10:8a217441c38e 350 data[i] = spi->write( 0x00 );
nixonkj 10:8a217441c38e 351 }
nixonkj 10:8a217441c38e 352 csn = 1;
nixonkj 10:8a217441c38e 353 if (debug) {
nixonkj 10:8a217441c38e 354 sprintf(logMsg, " register read %d bytes from %02x (%02x) = ", width, address, status );
nixonkj 10:8a217441c38e 355 for ( i=0; i<width; i++)
nixonkj 10:8a217441c38e 356 sprintf(logMsg, "%s %02x", logMsg, data[i]);
nixonkj 10:8a217441c38e 357 log(logMsg);
nixonkj 10:8a217441c38e 358 }
nixonkj 10:8a217441c38e 359 }
nixonkj 10:8a217441c38e 360
nixonkj 10:8a217441c38e 361 /**
epgmdm 0:8fd0531ae0be 362 * Clears the status flags RX_DR, TX_DS, MAX_RT
epgmdm 0:8fd0531ae0be 363 */
nixonkj 6:77ead8abdd1c 364 void NRF2401P::clearStatus()
epgmdm 0:8fd0531ae0be 365 {
nixonkj 8:3e027705ce23 366 writeReg(STATUS, 0x70);
epgmdm 2:ca0a3c0bba70 367 if (debug) {
epgmdm 2:ca0a3c0bba70 368 sprintf(logMsg, "Clear status (%02x)", status );
epgmdm 2:ca0a3c0bba70 369 log(logMsg);
epgmdm 2:ca0a3c0bba70 370 }
epgmdm 0:8fd0531ae0be 371 }
nixonkj 6:77ead8abdd1c 372
epgmdm 0:8fd0531ae0be 373 /**
epgmdm 0:8fd0531ae0be 374 * flushes TX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 375 */
nixonkj 6:77ead8abdd1c 376 void NRF2401P::flushTx()
epgmdm 0:8fd0531ae0be 377 {
epgmdm 0:8fd0531ae0be 378 csn = 0;
epgmdm 2:ca0a3c0bba70 379 status = spi->write( FLUSH_TX );
epgmdm 0:8fd0531ae0be 380 csn = 1;
epgmdm 0:8fd0531ae0be 381 clearStatus();
epgmdm 2:ca0a3c0bba70 382 if (debug) {
epgmdm 2:ca0a3c0bba70 383 sprintf(logMsg, "Flush TX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 384 log(logMsg);
epgmdm 2:ca0a3c0bba70 385 }
epgmdm 0:8fd0531ae0be 386 }
epgmdm 0:8fd0531ae0be 387
epgmdm 0:8fd0531ae0be 388 /**
epgmdm 0:8fd0531ae0be 389 * flushes RX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 390 */
nixonkj 6:77ead8abdd1c 391 void NRF2401P::flushRx()
epgmdm 0:8fd0531ae0be 392 {
epgmdm 0:8fd0531ae0be 393 csn = 0;
epgmdm 2:ca0a3c0bba70 394 status = spi->write( FLUSH_RX );
epgmdm 0:8fd0531ae0be 395 csn = 1;
epgmdm 2:ca0a3c0bba70 396 clearStatus();
epgmdm 2:ca0a3c0bba70 397 if (debug) {
epgmdm 2:ca0a3c0bba70 398 sprintf(logMsg, "Flush RX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 399 log(logMsg);
epgmdm 2:ca0a3c0bba70 400 }
epgmdm 0:8fd0531ae0be 401 }
nixonkj 6:77ead8abdd1c 402
epgmdm 0:8fd0531ae0be 403 /**
epgmdm 0:8fd0531ae0be 404 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 405 */
nixonkj 6:77ead8abdd1c 406 char NRF2401P::setTxMode()
epgmdm 0:8fd0531ae0be 407 {
epgmdm 0:8fd0531ae0be 408 char data;
epgmdm 0:8fd0531ae0be 409 char bit;
epgmdm 2:ca0a3c0bba70 410 if (debug) {
epgmdm 2:ca0a3c0bba70 411 sprintf(logMsg, "Set Tx Mode");
epgmdm 2:ca0a3c0bba70 412 log(logMsg);
epgmdm 2:ca0a3c0bba70 413 }
nixonkj 8:3e027705ce23 414 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 415 data &= ~( 1 << 0 );
epgmdm 2:ca0a3c0bba70 416 flushTx();
epgmdm 2:ca0a3c0bba70 417 flushRx();
nixonkj 8:3e027705ce23 418 writeReg(CONFIG, data);
nixonkj 8:3e027705ce23 419 writeReg(RX_ADDR_P0, txAdd, addressWidth); // reset p0
nixonkj 8:3e027705ce23 420 writeReg(EN_RXADDR, 0x01); // enable pipe 0 for reading
epgmdm 0:8fd0531ae0be 421 // check
nixonkj 8:3e027705ce23 422 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 423 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 424
epgmdm 0:8fd0531ae0be 425 ce=1;
epgmdm 0:8fd0531ae0be 426 wait(0.003);
nixonkj 6:77ead8abdd1c 427 if (bit == 0) {
nixonkj 6:77ead8abdd1c 428 return 0;
nixonkj 6:77ead8abdd1c 429 } else {
nixonkj 6:77ead8abdd1c 430 return 1;
nixonkj 6:77ead8abdd1c 431 }
epgmdm 0:8fd0531ae0be 432 }
epgmdm 0:8fd0531ae0be 433
epgmdm 0:8fd0531ae0be 434 /**
epgmdm 0:8fd0531ae0be 435 * Sets the number of bytes of the address width = 3,4,5
epgmdm 0:8fd0531ae0be 436 */
nixonkj 6:77ead8abdd1c 437 char NRF2401P::setAddressWidth( char width )
epgmdm 0:8fd0531ae0be 438 {
nixonkj 6:77ead8abdd1c 439 char chk=0;
epgmdm 0:8fd0531ae0be 440 addressWidth = width;
epgmdm 0:8fd0531ae0be 441 if ( ( width > 5 ) || ( width < 3 ) )
epgmdm 0:8fd0531ae0be 442 return false;
epgmdm 0:8fd0531ae0be 443 width -= 2;
nixonkj 8:3e027705ce23 444 writeReg(SETUP_AW, width);
nixonkj 8:3e027705ce23 445 readReg(SETUP_AW, &chk);
nixonkj 6:77ead8abdd1c 446 if (chk&0x03 == width) {
nixonkj 6:77ead8abdd1c 447 return 0;
nixonkj 6:77ead8abdd1c 448 } else {
nixonkj 6:77ead8abdd1c 449 return 1;
nixonkj 6:77ead8abdd1c 450 }
epgmdm 0:8fd0531ae0be 451 }
nixonkj 6:77ead8abdd1c 452
epgmdm 0:8fd0531ae0be 453 /**
nixonkj 6:77ead8abdd1c 454 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 455 */
epgmdm 0:8fd0531ae0be 456 char NRF2401P::setTxAddress( char *address )
epgmdm 0:8fd0531ae0be 457 {
epgmdm 2:ca0a3c0bba70 458 memcpy (txAdd,address, addressWidth);
nixonkj 8:3e027705ce23 459 writeReg(RX_ADDR_P0, address, addressWidth);
nixonkj 8:3e027705ce23 460 writeReg(TX_ADDR, address, addressWidth);
nixonkj 6:77ead8abdd1c 461 return 0; // must fix this
epgmdm 0:8fd0531ae0be 462 }
epgmdm 0:8fd0531ae0be 463
epgmdm 0:8fd0531ae0be 464 /**
epgmdm 0:8fd0531ae0be 465 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 466 */
epgmdm 0:8fd0531ae0be 467 char NRF2401P::setTxAddress( long long address )
epgmdm 0:8fd0531ae0be 468 {
epgmdm 0:8fd0531ae0be 469 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 470 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 471 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 472 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 473 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 474 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 475 return setTxAddress( buff );
epgmdm 0:8fd0531ae0be 476 }
epgmdm 0:8fd0531ae0be 477
epgmdm 0:8fd0531ae0be 478 /**
nixonkj 9:c21b80aaf250 479 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 2:ca0a3c0bba70 480 * Enables pipe for receiving;
epgmdm 0:8fd0531ae0be 481 */
epgmdm 0:8fd0531ae0be 482 char NRF2401P::setRxAddress( char *address, char pipe )
epgmdm 0:8fd0531ae0be 483 {
epgmdm 2:ca0a3c0bba70 484 if(debug) {
epgmdm 2:ca0a3c0bba70 485 log ("Set Rx Address");
epgmdm 2:ca0a3c0bba70 486 }
epgmdm 2:ca0a3c0bba70 487 if (pipe>5) return 0xff;
epgmdm 2:ca0a3c0bba70 488 if (pipe ==0) {
nixonkj 8:3e027705ce23 489 memcpy(pipe0Add,address, addressWidth);
epgmdm 2:ca0a3c0bba70 490 }
epgmdm 2:ca0a3c0bba70 491
epgmdm 0:8fd0531ae0be 492 char reg = 0x0A + pipe;
epgmdm 0:8fd0531ae0be 493 switch ( pipe ) {
epgmdm 0:8fd0531ae0be 494 case ( 0 ) :
epgmdm 0:8fd0531ae0be 495 case ( 1 ) : {
nixonkj 8:3e027705ce23 496 writeReg(reg, address, addressWidth); //Write to RX_ADDR_P0 or _P1
epgmdm 0:8fd0531ae0be 497 break;
epgmdm 0:8fd0531ae0be 498 }
epgmdm 0:8fd0531ae0be 499 case ( 2 ) :
epgmdm 0:8fd0531ae0be 500 case ( 3 ) :
epgmdm 0:8fd0531ae0be 501 case ( 4 ) :
epgmdm 0:8fd0531ae0be 502 case ( 5 ) : {
nixonkj 8:3e027705ce23 503 writeReg(reg, address, 1); //Write to RX_ADDR_P2 ... _P5
epgmdm 0:8fd0531ae0be 504 break;
epgmdm 0:8fd0531ae0be 505 }
epgmdm 0:8fd0531ae0be 506
epgmdm 0:8fd0531ae0be 507 }
nixonkj 8:3e027705ce23 508 readReg(EN_RXADDR, &reg);
epgmdm 2:ca0a3c0bba70 509 reg |= (1<<pipe);
nixonkj 8:3e027705ce23 510 writeReg(EN_RXADDR, reg); //Enable the pipe
nixonkj 6:77ead8abdd1c 511 return 0; // Must fix this
epgmdm 0:8fd0531ae0be 512 }
epgmdm 0:8fd0531ae0be 513
epgmdm 0:8fd0531ae0be 514 /**
epgmdm 0:8fd0531ae0be 515 * Sets the address of pipe (<=5), uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 516 */
epgmdm 0:8fd0531ae0be 517 char NRF2401P::setRxAddress( long long address, char pipe )
epgmdm 0:8fd0531ae0be 518 {
epgmdm 0:8fd0531ae0be 519 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 520 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 521 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 522 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 523 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 524 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 525 return setRxAddress( buff, pipe );
epgmdm 0:8fd0531ae0be 526 }
nixonkj 6:77ead8abdd1c 527
epgmdm 1:ff53b1ac3bad 528 /**
epgmdm 1:ff53b1ac3bad 529 *checks the status flag
epgmdm 1:ff53b1ac3bad 530 */
epgmdm 1:ff53b1ac3bad 531 char NRF2401P::checkStatus()
epgmdm 1:ff53b1ac3bad 532 {
nixonkj 8:3e027705ce23 533 readReg(STATUS, &status);
epgmdm 1:ff53b1ac3bad 534 return status;
epgmdm 1:ff53b1ac3bad 535 }
nixonkj 6:77ead8abdd1c 536
epgmdm 1:ff53b1ac3bad 537 /**
epgmdm 1:ff53b1ac3bad 538 * checks if Ack data available.
epgmdm 1:ff53b1ac3bad 539 */
epgmdm 1:ff53b1ac3bad 540 bool NRF2401P::isAckData()
epgmdm 1:ff53b1ac3bad 541 {
epgmdm 1:ff53b1ac3bad 542 char fifo;
nixonkj 8:3e027705ce23 543 readReg(FIFO_STATUS, &fifo);
epgmdm 1:ff53b1ac3bad 544 bool isData = !(fifo&0x01);
epgmdm 1:ff53b1ac3bad 545 return isData;
epgmdm 1:ff53b1ac3bad 546 }
epgmdm 0:8fd0531ae0be 547
epgmdm 1:ff53b1ac3bad 548 /**
epgmdm 1:ff53b1ac3bad 549 * checks if RX data available.
epgmdm 1:ff53b1ac3bad 550 */
epgmdm 0:8fd0531ae0be 551 bool NRF2401P::isRxData()
epgmdm 0:8fd0531ae0be 552 {
epgmdm 1:ff53b1ac3bad 553 checkStatus();
epgmdm 0:8fd0531ae0be 554 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 555 return isData;
epgmdm 0:8fd0531ae0be 556 }
nixonkj 6:77ead8abdd1c 557
epgmdm 0:8fd0531ae0be 558 char NRF2401P::getRxWidth()
epgmdm 0:8fd0531ae0be 559 {
epgmdm 0:8fd0531ae0be 560 char width;
epgmdm 0:8fd0531ae0be 561 if (dynamic) {
epgmdm 0:8fd0531ae0be 562 csn = 0;
nixonkj 14:976a876819ae 563 status = spi->write( R_RX_PL_WID );
epgmdm 0:8fd0531ae0be 564 width = spi->write(0x00);
epgmdm 0:8fd0531ae0be 565 csn = 1;
epgmdm 0:8fd0531ae0be 566
nixonkj 14:976a876819ae 567 if (width>32) { // as per product spec
epgmdm 0:8fd0531ae0be 568 flushRx();
nixonkj 14:976a876819ae 569 wait(0.002f); // little delay (KJN)
epgmdm 0:8fd0531ae0be 570 width=0;
epgmdm 0:8fd0531ae0be 571 }
epgmdm 0:8fd0531ae0be 572 } else {
nixonkj 8:3e027705ce23 573 readReg(RX_PW_P1, &width); // width of p1
epgmdm 0:8fd0531ae0be 574 }
nixonkj 14:976a876819ae 575
epgmdm 0:8fd0531ae0be 576 return width;
epgmdm 0:8fd0531ae0be 577 }
nixonkj 6:77ead8abdd1c 578
epgmdm 0:8fd0531ae0be 579 /**
epgmdm 0:8fd0531ae0be 580 * return message in buffer, mem for buffer must have been allocated.
epgmdm 0:8fd0531ae0be 581 * Return value is number of bytes of buffer
epgmdm 0:8fd0531ae0be 582 */
epgmdm 0:8fd0531ae0be 583 char NRF2401P::getRxData(char * buffer)
epgmdm 0:8fd0531ae0be 584 {
epgmdm 0:8fd0531ae0be 585 char address = 0x61;
epgmdm 0:8fd0531ae0be 586 char width;
epgmdm 0:8fd0531ae0be 587 width = getRxWidth();
epgmdm 0:8fd0531ae0be 588 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 589 if (isData) {
epgmdm 0:8fd0531ae0be 590 csn = 0;
epgmdm 0:8fd0531ae0be 591 int i;
epgmdm 0:8fd0531ae0be 592 // set up for reading
epgmdm 0:8fd0531ae0be 593 status = spi->write( address );
epgmdm 0:8fd0531ae0be 594 for ( i = 0; i <= width; i++ ) {
epgmdm 0:8fd0531ae0be 595 buffer[i]=spi->write(0x00 );
epgmdm 0:8fd0531ae0be 596 }
epgmdm 0:8fd0531ae0be 597 csn = 1;
nixonkj 6:77ead8abdd1c 598 if (debug) {
nixonkj 6:77ead8abdd1c 599 sprintf(logMsg, "Receive data %d bytes", width );
nixonkj 6:77ead8abdd1c 600 log(logMsg);
nixonkj 6:77ead8abdd1c 601 }
epgmdm 0:8fd0531ae0be 602 clearStatus();
epgmdm 0:8fd0531ae0be 603 return width;
epgmdm 0:8fd0531ae0be 604 } else {
nixonkj 6:77ead8abdd1c 605 if (debug) {
nixonkj 6:77ead8abdd1c 606 sprintf(logMsg, "Receive NO data %d bytes", width );
nixonkj 6:77ead8abdd1c 607 log(logMsg);
nixonkj 6:77ead8abdd1c 608 }
epgmdm 0:8fd0531ae0be 609 clearStatus();
epgmdm 0:8fd0531ae0be 610 return 0;
epgmdm 0:8fd0531ae0be 611 }
epgmdm 0:8fd0531ae0be 612 }
epgmdm 0:8fd0531ae0be 613
epgmdm 0:8fd0531ae0be 614 /**
epgmdm 0:8fd0531ae0be 615 * Sets all the receive pipes to dynamic payload length
epgmdm 0:8fd0531ae0be 616 */
epgmdm 2:ca0a3c0bba70 617 void NRF2401P::setDynamicPayload()
epgmdm 0:8fd0531ae0be 618 {
epgmdm 0:8fd0531ae0be 619 dynamic = true;
nixonkj 8:3e027705ce23 620 writeReg(FEATURE, 0x07); // Enable Dyn payload, Payload with Ack and w_tx_noack command
nixonkj 8:3e027705ce23 621 writeReg(EN_AA, 0x3f); // EN_AA regi for P1 and P0
nixonkj 9:c21b80aaf250 622 writeReg(DYNPD, 0x3F); // KJN - should be 0x3F for all pipes
epgmdm 0:8fd0531ae0be 623 }
epgmdm 2:ca0a3c0bba70 624
epgmdm 0:8fd0531ae0be 625 /**
epgmdm 0:8fd0531ae0be 626 * Sets PWR_UP = 1;
nixonkj 6:77ead8abdd1c 627 * return 0 on success
epgmdm 0:8fd0531ae0be 628 */
nixonkj 6:77ead8abdd1c 629 char NRF2401P::setPwrUp()
epgmdm 0:8fd0531ae0be 630 {
epgmdm 0:8fd0531ae0be 631 char data;
epgmdm 0:8fd0531ae0be 632 char bit;
epgmdm 0:8fd0531ae0be 633 ce=1;
nixonkj 8:3e027705ce23 634 readReg(CONFIG, &data);
epgmdm 2:ca0a3c0bba70 635 if ((data>>1) &0x01) {
epgmdm 2:ca0a3c0bba70 636 return true; // Already powered up
epgmdm 2:ca0a3c0bba70 637 };
nixonkj 8:3e027705ce23 638 data |= (0x02);
nixonkj 8:3e027705ce23 639 writeReg(CONFIG, data);
epgmdm 0:8fd0531ae0be 640 // check
nixonkj 8:3e027705ce23 641 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 642 bit = ( data >> 1 ) & 1;
epgmdm 2:ca0a3c0bba70 643
epgmdm 0:8fd0531ae0be 644 wait(0.005); // wait 5ms
epgmdm 2:ca0a3c0bba70 645 if(debug) {
epgmdm 2:ca0a3c0bba70 646 sprintf(logMsg, "Set PWR_UP to %x", bit);
epgmdm 2:ca0a3c0bba70 647 log(logMsg);
epgmdm 2:ca0a3c0bba70 648 }
nixonkj 6:77ead8abdd1c 649 if (bit == 1) {
nixonkj 6:77ead8abdd1c 650 return 0;
nixonkj 6:77ead8abdd1c 651 } else {
nixonkj 6:77ead8abdd1c 652 return 1;
nixonkj 6:77ead8abdd1c 653 }
nixonkj 6:77ead8abdd1c 654 }
epgmdm 2:ca0a3c0bba70 655
epgmdm 0:8fd0531ae0be 656 /**
epgmdm 0:8fd0531ae0be 657 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 658 */
nixonkj 6:77ead8abdd1c 659 char NRF2401P::setRxMode()
epgmdm 0:8fd0531ae0be 660 {
epgmdm 0:8fd0531ae0be 661 char data;
epgmdm 0:8fd0531ae0be 662 char bit;
epgmdm 0:8fd0531ae0be 663 ce=1;
nixonkj 8:3e027705ce23 664 readReg(CONFIG, &data);
nixonkj 8:3e027705ce23 665 data |= (0x01);
epgmdm 2:ca0a3c0bba70 666
nixonkj 8:3e027705ce23 667 writeReg(CONFIG, data);
epgmdm 3:afe8d307b5c3 668 if (pipe0Add[0]|pipe0Add[1]|pipe0Add[2]|pipe0Add[3]|pipe0Add[4] >0) {
epgmdm 3:afe8d307b5c3 669 setRxAddress(pipe0Add,0);
epgmdm 2:ca0a3c0bba70 670 }
epgmdm 0:8fd0531ae0be 671 // check
nixonkj 8:3e027705ce23 672 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 673 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 674
epgmdm 2:ca0a3c0bba70 675 wait (0.001);
epgmdm 0:8fd0531ae0be 676 flushRx();
epgmdm 2:ca0a3c0bba70 677 flushTx();
epgmdm 2:ca0a3c0bba70 678 if (debug) {
epgmdm 2:ca0a3c0bba70 679 sprintf(logMsg, " set PRIM_RX to %x", bit);
epgmdm 2:ca0a3c0bba70 680 log(logMsg);
epgmdm 2:ca0a3c0bba70 681 }
nixonkj 6:77ead8abdd1c 682 if ( bit == 1 ) {
nixonkj 6:77ead8abdd1c 683 return 0;
nixonkj 6:77ead8abdd1c 684 } else {
nixonkj 6:77ead8abdd1c 685 return 1;
nixonkj 6:77ead8abdd1c 686 }
epgmdm 0:8fd0531ae0be 687 }
nixonkj 6:77ead8abdd1c 688
epgmdm 0:8fd0531ae0be 689 /**
epgmdm 0:8fd0531ae0be 690 * Prints status string
epgmdm 0:8fd0531ae0be 691 */
epgmdm 0:8fd0531ae0be 692 char * NRF2401P::statusString()
epgmdm 0:8fd0531ae0be 693 {
epgmdm 0:8fd0531ae0be 694 char *msg;
epgmdm 0:8fd0531ae0be 695 msg = statusS;
epgmdm 0:8fd0531ae0be 696 if (((status>>1) & 0x07)==0x07) {
epgmdm 0:8fd0531ae0be 697 sprintf(msg,"RX empty");
epgmdm 0:8fd0531ae0be 698 } else {
epgmdm 0:8fd0531ae0be 699 sprintf(msg,"pipe %02x",(status>>1) & 0x07);
epgmdm 0:8fd0531ae0be 700 }
epgmdm 0:8fd0531ae0be 701
epgmdm 0:8fd0531ae0be 702 if ((status>>6)&0x01) strcat(msg," RX_DR,");
epgmdm 0:8fd0531ae0be 703 if ((status>>5)&0x01) strcat(msg," TX_DS,");
epgmdm 0:8fd0531ae0be 704 if ((status>>4)&0x01) strcat(msg," MAX_RT,");
epgmdm 0:8fd0531ae0be 705 if ((status>>0)&0x01) strcat(msg," TX_FLL,");
epgmdm 0:8fd0531ae0be 706
epgmdm 0:8fd0531ae0be 707 return msg;
nixonkj 9:c21b80aaf250 708 }
nixonkj 9:c21b80aaf250 709
nixonkj 11:07f76589f00a 710 void NRF2401P::printReg(char* name, char address, bool newline)
nixonkj 9:c21b80aaf250 711 {
nixonkj 9:c21b80aaf250 712 char data;
nixonkj 11:07f76589f00a 713 readReg(address, &data);
nixonkj 11:07f76589f00a 714 printf("%s = 0x%02x", name, data);
nixonkj 11:07f76589f00a 715 if (newline) {
nixonkj 11:07f76589f00a 716 printf("\r\n");
nixonkj 11:07f76589f00a 717 }
nixonkj 11:07f76589f00a 718 }
nixonkj 11:07f76589f00a 719
nixonkj 11:07f76589f00a 720 void NRF2401P::printReg(char* name, char address, char width, bool newline)
nixonkj 11:07f76589f00a 721 {
nixonkj 11:07f76589f00a 722 char data[width];
nixonkj 11:07f76589f00a 723 readReg(address, data, width);
nixonkj 11:07f76589f00a 724 printf("%s = 0x", name);
nixonkj 11:07f76589f00a 725 for (int i=width-1; i>=0; i--) {
nixonkj 11:07f76589f00a 726 printf("%02x", data[i]);
nixonkj 11:07f76589f00a 727 }
nixonkj 11:07f76589f00a 728 if (newline) {
nixonkj 11:07f76589f00a 729 printf("\r\n");
nixonkj 11:07f76589f00a 730 }
nixonkj 11:07f76589f00a 731 }
nixonkj 11:07f76589f00a 732
nixonkj 11:07f76589f00a 733 void NRF2401P::printDetails() {
nixonkj 14:976a876819ae 734 status = checkStatus();
nixonkj 11:07f76589f00a 735 printf("STATUS = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n", status,
nixonkj 9:c21b80aaf250 736 (status & (1<<MASK_RX_DR))?1:0,
nixonkj 9:c21b80aaf250 737 (status & (1<<MASK_TX_DS))?1:0,
nixonkj 9:c21b80aaf250 738 (status & (1<<MASK_MAX_RT))?1:0,
nixonkj 9:c21b80aaf250 739 (status >> RX_P_NO) & 7,
nixonkj 9:c21b80aaf250 740 (status & (1<<TX_FULL))?1:0 );
nixonkj 9:c21b80aaf250 741
nixonkj 11:07f76589f00a 742 printReg("RX_ADDR_P0", RX_ADDR_P0, addressWidth);
nixonkj 11:07f76589f00a 743 printReg("RX_ADDR_P1", RX_ADDR_P1, addressWidth);
nixonkj 11:07f76589f00a 744 printReg("RX_ADDR_P2", RX_ADDR_P2, addressWidth);
nixonkj 11:07f76589f00a 745 printReg("RX_ADDR_P3", RX_ADDR_P3, addressWidth);
nixonkj 11:07f76589f00a 746 printReg("RX_ADDR_P4", RX_ADDR_P4, addressWidth);
nixonkj 11:07f76589f00a 747 printReg("RX_ADDR_P5", RX_ADDR_P5, addressWidth);
nixonkj 11:07f76589f00a 748 printReg("TX_ADDR", TX_ADDR, addressWidth);
nixonkj 10:8a217441c38e 749
nixonkj 11:07f76589f00a 750 printReg("RX_PW_P0", RX_PW_P0, false); // false for no newline, save some space
nixonkj 11:07f76589f00a 751 printReg(" RX_PW_P1", RX_PW_P1, false);
nixonkj 11:07f76589f00a 752 printReg(" RX_PW_P2", RX_PW_P2);
nixonkj 11:07f76589f00a 753 printReg("RX_PW_P3", RX_PW_P3, false);
nixonkj 11:07f76589f00a 754 printReg(" RX_PW_P4", RX_PW_P4, false);
nixonkj 11:07f76589f00a 755 printReg(" RX_PW_P5", RX_PW_P5);
nixonkj 11:07f76589f00a 756
nixonkj 11:07f76589f00a 757 printReg("EN_AA", EN_AA);
nixonkj 11:07f76589f00a 758 printReg("EN_RXADDR", EN_RXADDR);
nixonkj 11:07f76589f00a 759 printReg("RF_CH", RF_CH);
nixonkj 11:07f76589f00a 760 printReg("RF_SETUP", RF_SETUP);
nixonkj 12:ea1345de6478 761 printReg("CONFIG", CONFIG);
nixonkj 11:07f76589f00a 762 printReg("DYNPD", DYNPD);
nixonkj 11:07f76589f00a 763 printReg("FEATURE", FEATURE);
epgmdm 0:8fd0531ae0be 764 }