Damien Frost / NRF2401P

My fork during debugging.

Fork of NRF2401P by Malcolm McCulloch

NRF2401P.cpp@16:a9b83d2b6915, 2016-01-28 (annotated)

Committer:
epgmdm
Date:
Thu Jan 28 14:37:32 2016 +0000
Revision:
16:a9b83d2b6915
Parent:
14:976a876819ae
Child:
17:ea1484f5757f
Makes the easy tx and rx include ack

Who changed what in which revision?

UserRevisionLine numberNew contents of line
epgmdm 0:8fd0531ae0be 1 /**
epgmdm 0:8fd0531ae0be 2 *@section DESCRIPTION
epgmdm 0:8fd0531ae0be 3 * mbed NRF2401+ Library
epgmdm 0:8fd0531ae0be 4 *@section LICENSE
epgmdm 0:8fd0531ae0be 5 * Copyright (c) 2015, Malcolm McCulloch
epgmdm 0:8fd0531ae0be 6 *
epgmdm 0:8fd0531ae0be 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
epgmdm 0:8fd0531ae0be 8 * of this software and associated documentation files (the "Software"), to deal
epgmdm 0:8fd0531ae0be 9 * in the Software without restriction, including without limitation the rights
epgmdm 0:8fd0531ae0be 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
epgmdm 0:8fd0531ae0be 11 * copies of the Software, and to permit persons to whom the Software is
epgmdm 0:8fd0531ae0be 12 * furnished to do so, subject to the following conditions:
epgmdm 0:8fd0531ae0be 13 *
epgmdm 0:8fd0531ae0be 14 * The above copyright notice and this permission notice shall be included in
epgmdm 0:8fd0531ae0be 15 * all copies or substantial portions of the Software.
epgmdm 0:8fd0531ae0be 16 *
epgmdm 0:8fd0531ae0be 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
epgmdm 0:8fd0531ae0be 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
epgmdm 0:8fd0531ae0be 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
epgmdm 0:8fd0531ae0be 20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
epgmdm 0:8fd0531ae0be 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
epgmdm 0:8fd0531ae0be 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
epgmdm 0:8fd0531ae0be 23 * THE SOFTWARE.
epgmdm 0:8fd0531ae0be 24 * @file "NRF2401P.cpp"
epgmdm 0:8fd0531ae0be 25 */
epgmdm 2:ca0a3c0bba70 26 #include "mbed.h"
epgmdm 2:ca0a3c0bba70 27 #include "NRF2401P.h"
epgmdm 2:ca0a3c0bba70 28 #include "nRF24l01.h"
epgmdm 0:8fd0531ae0be 29
epgmdm 0:8fd0531ae0be 30 NRF2401P::NRF2401P ( PinName mosi, PinName miso, PinName sclk, PinName _csn, PinName _ce ) :
epgmdm 16:a9b83d2b6915 31 csn( DigitalOut( _csn ) ), ce( DigitalOut( _ce ) )
epgmdm 0:8fd0531ae0be 32 {
epgmdm 0:8fd0531ae0be 33 addressWidth = 5;
epgmdm 0:8fd0531ae0be 34 pc = new Serial( USBTX, USBRX ); // tx, rx
nixonkj 6:77ead8abdd1c 35 if (debug) {
nixonkj 6:77ead8abdd1c 36 sprintf(logMsg, "Initialise" );
nixonkj 6:77ead8abdd1c 37 log(logMsg);
nixonkj 6:77ead8abdd1c 38 }
epgmdm 0:8fd0531ae0be 39 spi = new SPI( mosi, miso, sclk, NC ); //SPI (PinName mosi, PinName miso, PinName sclk, PinName _unused=NC)
epgmdm 0:8fd0531ae0be 40 spi->frequency( 10000000 ); // 1MHZ max 10 MHz
epgmdm 0:8fd0531ae0be 41 spi->format( 8, 0 ); // 0: 0e 08; 1: 0e 00; 2:0e 00 ;3:1c 00
epgmdm 0:8fd0531ae0be 42 csn = 1;
epgmdm 0:8fd0531ae0be 43 ce = 0;
epgmdm 0:8fd0531ae0be 44 dynamic = false;
nixonkj 6:77ead8abdd1c 45 debug = false;
nixonkj 6:77ead8abdd1c 46 }
epgmdm 0:8fd0531ae0be 47
nixonkj 6:77ead8abdd1c 48 void NRF2401P::log(char *msg)
epgmdm 0:8fd0531ae0be 49 {
epgmdm 0:8fd0531ae0be 50 if(debug) {
nixonkj 8:3e027705ce23 51 printf("\t <%s \t %s>\n\r", statusString(), msg);
epgmdm 1:ff53b1ac3bad 52 wait(0.01);
nixonkj 6:77ead8abdd1c 53 }
epgmdm 0:8fd0531ae0be 54 }
epgmdm 0:8fd0531ae0be 55
epgmdm 0:8fd0531ae0be 56 void NRF2401P::scratch()
epgmdm 0:8fd0531ae0be 57 {
epgmdm 0:8fd0531ae0be 58 int status = 0;
epgmdm 0:8fd0531ae0be 59 int register1 = 0;
epgmdm 0:8fd0531ae0be 60 ce = 0;
epgmdm 0:8fd0531ae0be 61 for ( char i = 0; i < 24; i++ ) {
epgmdm 0:8fd0531ae0be 62 csn = 0;
epgmdm 0:8fd0531ae0be 63 //wait_us(100);
epgmdm 0:8fd0531ae0be 64 status = spi->write( i );
epgmdm 0:8fd0531ae0be 65 register1 = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 66 csn = 1;
epgmdm 0:8fd0531ae0be 67 sprintf(logMsg, " register %02x (%02x) = %02x", i, status, register1 );
epgmdm 0:8fd0531ae0be 68 log(logMsg);
epgmdm 0:8fd0531ae0be 69 }
nixonkj 6:77ead8abdd1c 70 }
epgmdm 0:8fd0531ae0be 71
epgmdm 0:8fd0531ae0be 72 /**
epgmdm 2:ca0a3c0bba70 73 * start here to configure the basics of the NRF
epgmdm 2:ca0a3c0bba70 74 */
epgmdm 2:ca0a3c0bba70 75 void NRF2401P::start()
epgmdm 2:ca0a3c0bba70 76 {
nixonkj 8:3e027705ce23 77 writeReg(CONFIG, 0x0c); // set 16 bit crc
nixonkj 8:3e027705ce23 78 setTxRetry(0x01, 0x0f); // 500 uS, 15 retries
nixonkj 8:3e027705ce23 79 setRadio(0, 0x03); // 1MB/S 0dB
epgmdm 2:ca0a3c0bba70 80 setDynamicPayload();
epgmdm 2:ca0a3c0bba70 81 setChannel(76); // should be clear?
epgmdm 2:ca0a3c0bba70 82 setAddressWidth(5);
epgmdm 2:ca0a3c0bba70 83 flushRx();
epgmdm 2:ca0a3c0bba70 84 flushTx();
epgmdm 2:ca0a3c0bba70 85 setPwrUp();
epgmdm 2:ca0a3c0bba70 86 setTxMode(); // just make sure no spurious reads....
nixonkj 6:77ead8abdd1c 87 }
epgmdm 2:ca0a3c0bba70 88
epgmdm 2:ca0a3c0bba70 89 /**
epgmdm 16:a9b83d2b6915 90 * Sets up a receiver using shockburst and dynamic payload. Uses pipe 0
epgmdm 0:8fd0531ae0be 91 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 92 */
epgmdm 2:ca0a3c0bba70 93 void NRF2401P::quickRxSetup(int channel,long long addrRx)
epgmdm 0:8fd0531ae0be 94 {
epgmdm 2:ca0a3c0bba70 95 start();
epgmdm 0:8fd0531ae0be 96 setChannel(channel);
epgmdm 16:a9b83d2b6915 97 // setRxAddress(addrRx,1);
epgmdm 16:a9b83d2b6915 98 setRxAddress(addrRx,0);
epgmdm 0:8fd0531ae0be 99 setRxMode();
epgmdm 0:8fd0531ae0be 100 ce=1;
nixonkj 6:77ead8abdd1c 101 wait(0.001f);
epgmdm 16:a9b83d2b6915 102 writeReg(FEATURE,0x06); // Enable dynamic ack packets
epgmdm 0:8fd0531ae0be 103 }
nixonkj 6:77ead8abdd1c 104
epgmdm 0:8fd0531ae0be 105 /**
epgmdm 0:8fd0531ae0be 106 * Sets up for receive of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 107 */
epgmdm 0:8fd0531ae0be 108 char NRF2401P::testReceive()
epgmdm 0:8fd0531ae0be 109 {
epgmdm 0:8fd0531ae0be 110 char message[64];
epgmdm 0:8fd0531ae0be 111 char width;
epgmdm 0:8fd0531ae0be 112 int channel = 0x12;
epgmdm 0:8fd0531ae0be 113 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 114 debug = true;
epgmdm 0:8fd0531ae0be 115 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 116
epgmdm 0:8fd0531ae0be 117 while (1) {
epgmdm 0:8fd0531ae0be 118 while (!isRxData()) {
epgmdm 0:8fd0531ae0be 119 //wait(0.5);
epgmdm 0:8fd0531ae0be 120 };
epgmdm 0:8fd0531ae0be 121 width=getRxData(message);
epgmdm 0:8fd0531ae0be 122 message[width]='\0';
epgmdm 0:8fd0531ae0be 123 sprintf(logMsg,"Received= [%s]",message);
epgmdm 0:8fd0531ae0be 124 log(logMsg);
nixonkj 6:77ead8abdd1c 125 }
epgmdm 0:8fd0531ae0be 126 }
epgmdm 0:8fd0531ae0be 127
nixonkj 6:77ead8abdd1c 128 char NRF2401P::setTxRetry(char delay, char numTries)
epgmdm 2:ca0a3c0bba70 129 {
epgmdm 2:ca0a3c0bba70 130 char val = (delay&0xf)<<4 | (numTries&0xf);
nixonkj 6:77ead8abdd1c 131 char chk;
nixonkj 8:3e027705ce23 132 writeReg(SETUP_RETR, val);
nixonkj 8:3e027705ce23 133 readReg(SETUP_RETR, &chk);
nixonkj 6:77ead8abdd1c 134 if (chk&0xff == val) {
nixonkj 6:77ead8abdd1c 135 return 0;
nixonkj 6:77ead8abdd1c 136 } else {
nixonkj 6:77ead8abdd1c 137 return 1;
nixonkj 6:77ead8abdd1c 138 }
epgmdm 2:ca0a3c0bba70 139 }
epgmdm 2:ca0a3c0bba70 140
epgmdm 2:ca0a3c0bba70 141 /**
epgmdm 0:8fd0531ae0be 142 * Sets up a transmitter using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 143 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 144 */
epgmdm 0:8fd0531ae0be 145 void NRF2401P::quickTxSetup(int channel,long long addr)
epgmdm 0:8fd0531ae0be 146 {
epgmdm 2:ca0a3c0bba70 147 start();
epgmdm 0:8fd0531ae0be 148 setChannel(channel);
epgmdm 2:ca0a3c0bba70 149 setTxAddress(addr);
epgmdm 0:8fd0531ae0be 150 setTxMode();
epgmdm 16:a9b83d2b6915 151 writeReg(FEATURE,0x06);
epgmdm 0:8fd0531ae0be 152 ce=1;
epgmdm 0:8fd0531ae0be 153 wait (0.0016f); // wait for pll to settle
epgmdm 16:a9b83d2b6915 154 flushTx();
epgmdm 16:a9b83d2b6915 155 clearStatus();
epgmdm 0:8fd0531ae0be 156 }
epgmdm 0:8fd0531ae0be 157
epgmdm 0:8fd0531ae0be 158 /**
epgmdm 0:8fd0531ae0be 159 * Sets up for transmit of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 160 */
epgmdm 0:8fd0531ae0be 161 char NRF2401P::testTransmit()
epgmdm 0:8fd0531ae0be 162 {
epgmdm 0:8fd0531ae0be 163 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 164 int channel = 0x12;
epgmdm 0:8fd0531ae0be 165 char data[32] ;
epgmdm 0:8fd0531ae0be 166 int i=0;
epgmdm 0:8fd0531ae0be 167 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 168 while (1) {
epgmdm 0:8fd0531ae0be 169 sprintf(data," packet %03d", i++ |100);
epgmdm 0:8fd0531ae0be 170 transmitData(data,18);
epgmdm 0:8fd0531ae0be 171 wait (1.0);
epgmdm 0:8fd0531ae0be 172 }
nixonkj 6:77ead8abdd1c 173 }
epgmdm 0:8fd0531ae0be 174
nixonkj 6:77ead8abdd1c 175 char NRF2401P::setRadio(char speed, char power)
epgmdm 0:8fd0531ae0be 176 {
nixonkj 6:77ead8abdd1c 177 char val=0, chk=0;
nixonkj 8:3e027705ce23 178 if (debug) {
nixonkj 8:3e027705ce23 179 sprintf(logMsg, "Set radio");
nixonkj 8:3e027705ce23 180 log(logMsg);
nixonkj 8:3e027705ce23 181 }
epgmdm 0:8fd0531ae0be 182 if (speed & 0x02) {
epgmdm 0:8fd0531ae0be 183 val |= (1<<5);
epgmdm 0:8fd0531ae0be 184 }
epgmdm 0:8fd0531ae0be 185 val |= (speed & 0x01)<<3;
epgmdm 0:8fd0531ae0be 186
nixonkj 6:77ead8abdd1c 187 val |= ((power & 0x03)<<1);
nixonkj 6:77ead8abdd1c 188 printf("\n\r");
nixonkj 6:77ead8abdd1c 189
nixonkj 8:3e027705ce23 190 writeReg(RF_SETUP, val);
epgmdm 0:8fd0531ae0be 191
nixonkj 6:77ead8abdd1c 192 // read register to verify settings
nixonkj 8:3e027705ce23 193 readReg(RF_SETUP, &chk);
nixonkj 6:77ead8abdd1c 194 if (chk&0x2E == val) {
nixonkj 6:77ead8abdd1c 195 return 0;
nixonkj 6:77ead8abdd1c 196 } else {
nixonkj 6:77ead8abdd1c 197 return 1;
nixonkj 6:77ead8abdd1c 198 }
epgmdm 0:8fd0531ae0be 199 }
nixonkj 6:77ead8abdd1c 200
epgmdm 0:8fd0531ae0be 201 char NRF2401P::setChannel(char chan)
epgmdm 0:8fd0531ae0be 202 {
nixonkj 6:77ead8abdd1c 203 char chk=0;
nixonkj 6:77ead8abdd1c 204 if (debug) {
nixonkj 6:77ead8abdd1c 205 sprintf(logMsg, "Set channel");
nixonkj 6:77ead8abdd1c 206 log(logMsg);
nixonkj 6:77ead8abdd1c 207 }
nixonkj 8:3e027705ce23 208 writeReg(RF_CH, (chan&0x7f));
nixonkj 8:3e027705ce23 209 readReg(RF_CH, &chk);
nixonkj 6:77ead8abdd1c 210 if (chk&0x7f == chan&0x7f) {
nixonkj 6:77ead8abdd1c 211 return 0;
nixonkj 6:77ead8abdd1c 212 } else {
nixonkj 6:77ead8abdd1c 213 return 1;
nixonkj 6:77ead8abdd1c 214 }
epgmdm 0:8fd0531ae0be 215 }
nixonkj 6:77ead8abdd1c 216
nixonkj 13:5cbc726f2bbb 217 bool NRF2401P::isRPDset()
nixonkj 13:5cbc726f2bbb 218 {
nixonkj 13:5cbc726f2bbb 219 char val=0;
nixonkj 13:5cbc726f2bbb 220 if (debug) {
nixonkj 13:5cbc726f2bbb 221 sprintf(logMsg, "Get RPD");
nixonkj 13:5cbc726f2bbb 222 log(logMsg);
nixonkj 13:5cbc726f2bbb 223 }
nixonkj 13:5cbc726f2bbb 224 readReg(RPD, &val);
nixonkj 13:5cbc726f2bbb 225 if (val == 1) {
nixonkj 13:5cbc726f2bbb 226 return true;
nixonkj 13:5cbc726f2bbb 227 } else {
nixonkj 13:5cbc726f2bbb 228 return false;
nixonkj 13:5cbc726f2bbb 229 }
nixonkj 13:5cbc726f2bbb 230 }
nixonkj 13:5cbc726f2bbb 231
epgmdm 0:8fd0531ae0be 232 /**
epgmdm 0:8fd0531ae0be 233 * Transmits width bytes of data. width <32
epgmdm 0:8fd0531ae0be 234 */
nixonkj 6:77ead8abdd1c 235 char NRF2401P::transmitData( char *data, char width )
epgmdm 0:8fd0531ae0be 236 {
nixonkj 6:77ead8abdd1c 237 if (width>32)
nixonkj 6:77ead8abdd1c 238 return 0;
nixonkj 6:77ead8abdd1c 239 checkStatus();
nixonkj 6:77ead8abdd1c 240 if ((status>>4)&1) { // Max retries - flush tx
nixonkj 6:77ead8abdd1c 241 flushTx();
nixonkj 6:77ead8abdd1c 242 }
epgmdm 2:ca0a3c0bba70 243 //clearStatus();
epgmdm 2:ca0a3c0bba70 244 //ce = 1;
epgmdm 0:8fd0531ae0be 245 csn = 0;
nixonkj 8:3e027705ce23 246 char address = 0xA0;
epgmdm 0:8fd0531ae0be 247 int i;
epgmdm 0:8fd0531ae0be 248 // set up for writing
epgmdm 0:8fd0531ae0be 249 status = spi->write( address );
epgmdm 0:8fd0531ae0be 250 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 251 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 252 }
epgmdm 0:8fd0531ae0be 253 csn = 1;
epgmdm 3:afe8d307b5c3 254 wait(0.001);
epgmdm 3:afe8d307b5c3 255 if (debug) {
nixonkj 6:77ead8abdd1c 256 sprintf(logMsg, " Transmit data %d bytes to %02x (%02x) = %10s", width, address, status, data );
epgmdm 3:afe8d307b5c3 257 log(logMsg);
epgmdm 2:ca0a3c0bba70 258 }
epgmdm 0:8fd0531ae0be 259 return status;
epgmdm 0:8fd0531ae0be 260 }
epgmdm 0:8fd0531ae0be 261
epgmdm 0:8fd0531ae0be 262 /**
epgmdm 0:8fd0531ae0be 263 * sets acknowledge data width bytes of data. width <32
epgmdm 0:8fd0531ae0be 264 */
epgmdm 1:ff53b1ac3bad 265 char NRF2401P::acknowledgeData( char *data, char width, char pipe )
epgmdm 0:8fd0531ae0be 266 {
epgmdm 0:8fd0531ae0be 267 ce = 1;
epgmdm 0:8fd0531ae0be 268 csn = 0;
epgmdm 2:ca0a3c0bba70 269 //writeReg(0x1d,0x06); // enable payload with ack
epgmdm 2:ca0a3c0bba70 270 char address = W_ACK_PAYLOAD | (pipe&0x07);
epgmdm 0:8fd0531ae0be 271 int i;
epgmdm 0:8fd0531ae0be 272 // set up for writing
epgmdm 3:afe8d307b5c3 273 csn = 0;
epgmdm 0:8fd0531ae0be 274 status = spi->write( address );
epgmdm 0:8fd0531ae0be 275 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 276 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 277 }
epgmdm 0:8fd0531ae0be 278 csn = 1;
epgmdm 3:afe8d307b5c3 279 if (debug) {
epgmdm 3:afe8d307b5c3 280 sprintf(logMsg, " acknowledge data %d bytes to %02x (%02x) = %c", width, address, status, *data );
epgmdm 3:afe8d307b5c3 281 log(logMsg);
epgmdm 2:ca0a3c0bba70 282 }
epgmdm 0:8fd0531ae0be 283 return status;
nixonkj 6:77ead8abdd1c 284 }
epgmdm 0:8fd0531ae0be 285
epgmdm 0:8fd0531ae0be 286 /**
epgmdm 0:8fd0531ae0be 287 * Writes 1 byte data to a register
epgmdm 0:8fd0531ae0be 288 **/
nixonkj 6:77ead8abdd1c 289 void NRF2401P::writeReg( char address, char data )
epgmdm 0:8fd0531ae0be 290 {
epgmdm 0:8fd0531ae0be 291 char reg;
epgmdm 0:8fd0531ae0be 292 csn = 0;
epgmdm 0:8fd0531ae0be 293 address &= 0x1F;
nixonkj 8:3e027705ce23 294 reg = address | W_REGISTER;
epgmdm 0:8fd0531ae0be 295 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 296 spi->write( data );
epgmdm 0:8fd0531ae0be 297 csn = 1;
nixonkj 6:77ead8abdd1c 298 if (debug) {
nixonkj 6:77ead8abdd1c 299 sprintf(logMsg, " register write %02x (%02x) = %02x", address, status, data );
nixonkj 6:77ead8abdd1c 300 log(logMsg);
nixonkj 6:77ead8abdd1c 301 }
epgmdm 0:8fd0531ae0be 302 }
nixonkj 6:77ead8abdd1c 303
epgmdm 0:8fd0531ae0be 304 /**
epgmdm 0:8fd0531ae0be 305 * Writes width bytes data to a register, ls byte to ms byte /for adressess
epgmdm 0:8fd0531ae0be 306 **/
nixonkj 6:77ead8abdd1c 307 void NRF2401P::writeReg( char address, char *data, char width )
epgmdm 0:8fd0531ae0be 308 {
epgmdm 0:8fd0531ae0be 309 char reg;
epgmdm 0:8fd0531ae0be 310 csn = 0;
epgmdm 0:8fd0531ae0be 311 int i;
epgmdm 0:8fd0531ae0be 312 // set up for writing
epgmdm 0:8fd0531ae0be 313 address &= 0x1F;
nixonkj 8:3e027705ce23 314 reg = address| W_REGISTER;
epgmdm 0:8fd0531ae0be 315 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 316 for ( i = width - 1; i >= 0; i-- ) {
epgmdm 0:8fd0531ae0be 317 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 318 }
epgmdm 0:8fd0531ae0be 319 csn = 1;
epgmdm 2:ca0a3c0bba70 320 if (debug) {
epgmdm 2:ca0a3c0bba70 321 sprintf(logMsg, " register write %d bytes to %02x (%02x) = %02x %02x %02x", width, address, status, data[0], data[1], data[2] );
epgmdm 2:ca0a3c0bba70 322 log(logMsg);
epgmdm 2:ca0a3c0bba70 323 }
epgmdm 0:8fd0531ae0be 324 }
nixonkj 6:77ead8abdd1c 325
epgmdm 0:8fd0531ae0be 326 /**
epgmdm 0:8fd0531ae0be 327 * Reads 1 byte from a register
epgmdm 0:8fd0531ae0be 328 **/
nixonkj 6:77ead8abdd1c 329 void NRF2401P::readReg( char address, char *data )
epgmdm 0:8fd0531ae0be 330 {
epgmdm 0:8fd0531ae0be 331 csn = 0;
epgmdm 0:8fd0531ae0be 332 address &= 0x1F;
epgmdm 0:8fd0531ae0be 333 status = spi->write( address );
epgmdm 0:8fd0531ae0be 334 *data = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 335 csn = 1;
nixonkj 6:77ead8abdd1c 336 if (debug && address != 0x07) { // In debug mode: print out anything other than a status request
nixonkj 6:77ead8abdd1c 337 sprintf(logMsg, " register read %02x (%02x) = %02x", address, status, *data );
nixonkj 6:77ead8abdd1c 338 log(logMsg);
nixonkj 6:77ead8abdd1c 339 }
epgmdm 0:8fd0531ae0be 340 }
nixonkj 6:77ead8abdd1c 341
epgmdm 0:8fd0531ae0be 342 /**
nixonkj 10:8a217441c38e 343 * Reads n bytes from a register
nixonkj 10:8a217441c38e 344 **/
nixonkj 10:8a217441c38e 345 void NRF2401P::readReg( char address, char *data, char width )
epgmdm 16:a9b83d2b6915 346 {
nixonkj 10:8a217441c38e 347 char reg;
nixonkj 10:8a217441c38e 348 csn = 0;
nixonkj 10:8a217441c38e 349 int i;
nixonkj 10:8a217441c38e 350 // set up for writing
nixonkj 10:8a217441c38e 351 address &= 0x1F;
nixonkj 10:8a217441c38e 352 reg = address| R_REGISTER;
nixonkj 10:8a217441c38e 353 status = spi->write( reg );
nixonkj 10:8a217441c38e 354 for ( i = width - 1; i >= 0; i-- ) {
nixonkj 10:8a217441c38e 355 data[i] = spi->write( 0x00 );
nixonkj 10:8a217441c38e 356 }
nixonkj 10:8a217441c38e 357 csn = 1;
nixonkj 10:8a217441c38e 358 if (debug) {
nixonkj 10:8a217441c38e 359 sprintf(logMsg, " register read %d bytes from %02x (%02x) = ", width, address, status );
nixonkj 10:8a217441c38e 360 for ( i=0; i<width; i++)
nixonkj 10:8a217441c38e 361 sprintf(logMsg, "%s %02x", logMsg, data[i]);
nixonkj 10:8a217441c38e 362 log(logMsg);
nixonkj 10:8a217441c38e 363 }
nixonkj 10:8a217441c38e 364 }
nixonkj 10:8a217441c38e 365
nixonkj 10:8a217441c38e 366 /**
epgmdm 0:8fd0531ae0be 367 * Clears the status flags RX_DR, TX_DS, MAX_RT
epgmdm 0:8fd0531ae0be 368 */
nixonkj 6:77ead8abdd1c 369 void NRF2401P::clearStatus()
epgmdm 0:8fd0531ae0be 370 {
nixonkj 8:3e027705ce23 371 writeReg(STATUS, 0x70);
epgmdm 2:ca0a3c0bba70 372 if (debug) {
epgmdm 2:ca0a3c0bba70 373 sprintf(logMsg, "Clear status (%02x)", status );
epgmdm 2:ca0a3c0bba70 374 log(logMsg);
epgmdm 2:ca0a3c0bba70 375 }
epgmdm 0:8fd0531ae0be 376 }
nixonkj 6:77ead8abdd1c 377
epgmdm 0:8fd0531ae0be 378 /**
epgmdm 0:8fd0531ae0be 379 * flushes TX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 380 */
nixonkj 6:77ead8abdd1c 381 void NRF2401P::flushTx()
epgmdm 0:8fd0531ae0be 382 {
epgmdm 0:8fd0531ae0be 383 csn = 0;
epgmdm 2:ca0a3c0bba70 384 status = spi->write( FLUSH_TX );
epgmdm 0:8fd0531ae0be 385 csn = 1;
epgmdm 0:8fd0531ae0be 386 clearStatus();
epgmdm 2:ca0a3c0bba70 387 if (debug) {
epgmdm 2:ca0a3c0bba70 388 sprintf(logMsg, "Flush TX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 389 log(logMsg);
epgmdm 2:ca0a3c0bba70 390 }
epgmdm 0:8fd0531ae0be 391 }
epgmdm 0:8fd0531ae0be 392
epgmdm 0:8fd0531ae0be 393 /**
epgmdm 0:8fd0531ae0be 394 * flushes RX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 395 */
nixonkj 6:77ead8abdd1c 396 void NRF2401P::flushRx()
epgmdm 0:8fd0531ae0be 397 {
epgmdm 0:8fd0531ae0be 398 csn = 0;
epgmdm 2:ca0a3c0bba70 399 status = spi->write( FLUSH_RX );
epgmdm 0:8fd0531ae0be 400 csn = 1;
epgmdm 2:ca0a3c0bba70 401 clearStatus();
epgmdm 2:ca0a3c0bba70 402 if (debug) {
epgmdm 2:ca0a3c0bba70 403 sprintf(logMsg, "Flush RX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 404 log(logMsg);
epgmdm 2:ca0a3c0bba70 405 }
epgmdm 0:8fd0531ae0be 406 }
nixonkj 6:77ead8abdd1c 407
epgmdm 0:8fd0531ae0be 408 /**
epgmdm 0:8fd0531ae0be 409 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 410 */
nixonkj 6:77ead8abdd1c 411 char NRF2401P::setTxMode()
epgmdm 0:8fd0531ae0be 412 {
epgmdm 0:8fd0531ae0be 413 char data;
epgmdm 0:8fd0531ae0be 414 char bit;
epgmdm 2:ca0a3c0bba70 415 if (debug) {
epgmdm 2:ca0a3c0bba70 416 sprintf(logMsg, "Set Tx Mode");
epgmdm 2:ca0a3c0bba70 417 log(logMsg);
epgmdm 2:ca0a3c0bba70 418 }
nixonkj 8:3e027705ce23 419 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 420 data &= ~( 1 << 0 );
epgmdm 2:ca0a3c0bba70 421 flushTx();
epgmdm 2:ca0a3c0bba70 422 flushRx();
nixonkj 8:3e027705ce23 423 writeReg(CONFIG, data);
nixonkj 8:3e027705ce23 424 writeReg(RX_ADDR_P0, txAdd, addressWidth); // reset p0
nixonkj 8:3e027705ce23 425 writeReg(EN_RXADDR, 0x01); // enable pipe 0 for reading
epgmdm 0:8fd0531ae0be 426 // check
nixonkj 8:3e027705ce23 427 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 428 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 429
epgmdm 0:8fd0531ae0be 430 ce=1;
epgmdm 0:8fd0531ae0be 431 wait(0.003);
nixonkj 6:77ead8abdd1c 432 if (bit == 0) {
nixonkj 6:77ead8abdd1c 433 return 0;
nixonkj 6:77ead8abdd1c 434 } else {
nixonkj 6:77ead8abdd1c 435 return 1;
nixonkj 6:77ead8abdd1c 436 }
epgmdm 0:8fd0531ae0be 437 }
epgmdm 0:8fd0531ae0be 438
epgmdm 0:8fd0531ae0be 439 /**
epgmdm 0:8fd0531ae0be 440 * Sets the number of bytes of the address width = 3,4,5
epgmdm 0:8fd0531ae0be 441 */
nixonkj 6:77ead8abdd1c 442 char NRF2401P::setAddressWidth( char width )
epgmdm 0:8fd0531ae0be 443 {
nixonkj 6:77ead8abdd1c 444 char chk=0;
epgmdm 0:8fd0531ae0be 445 addressWidth = width;
epgmdm 0:8fd0531ae0be 446 if ( ( width > 5 ) || ( width < 3 ) )
epgmdm 0:8fd0531ae0be 447 return false;
epgmdm 0:8fd0531ae0be 448 width -= 2;
nixonkj 8:3e027705ce23 449 writeReg(SETUP_AW, width);
nixonkj 8:3e027705ce23 450 readReg(SETUP_AW, &chk);
nixonkj 6:77ead8abdd1c 451 if (chk&0x03 == width) {
nixonkj 6:77ead8abdd1c 452 return 0;
nixonkj 6:77ead8abdd1c 453 } else {
nixonkj 6:77ead8abdd1c 454 return 1;
nixonkj 6:77ead8abdd1c 455 }
epgmdm 0:8fd0531ae0be 456 }
nixonkj 6:77ead8abdd1c 457
epgmdm 0:8fd0531ae0be 458 /**
nixonkj 6:77ead8abdd1c 459 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 460 */
epgmdm 0:8fd0531ae0be 461 char NRF2401P::setTxAddress( char *address )
epgmdm 0:8fd0531ae0be 462 {
epgmdm 2:ca0a3c0bba70 463 memcpy (txAdd,address, addressWidth);
nixonkj 8:3e027705ce23 464 writeReg(RX_ADDR_P0, address, addressWidth);
nixonkj 8:3e027705ce23 465 writeReg(TX_ADDR, address, addressWidth);
nixonkj 6:77ead8abdd1c 466 return 0; // must fix this
epgmdm 0:8fd0531ae0be 467 }
epgmdm 0:8fd0531ae0be 468
epgmdm 0:8fd0531ae0be 469 /**
epgmdm 0:8fd0531ae0be 470 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 471 */
epgmdm 0:8fd0531ae0be 472 char NRF2401P::setTxAddress( long long address )
epgmdm 0:8fd0531ae0be 473 {
epgmdm 0:8fd0531ae0be 474 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 475 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 476 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 477 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 478 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 479 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 480 return setTxAddress( buff );
epgmdm 0:8fd0531ae0be 481 }
epgmdm 0:8fd0531ae0be 482
epgmdm 0:8fd0531ae0be 483 /**
nixonkj 9:c21b80aaf250 484 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 2:ca0a3c0bba70 485 * Enables pipe for receiving;
epgmdm 0:8fd0531ae0be 486 */
epgmdm 0:8fd0531ae0be 487 char NRF2401P::setRxAddress( char *address, char pipe )
epgmdm 0:8fd0531ae0be 488 {
epgmdm 2:ca0a3c0bba70 489 if(debug) {
epgmdm 2:ca0a3c0bba70 490 log ("Set Rx Address");
epgmdm 2:ca0a3c0bba70 491 }
epgmdm 2:ca0a3c0bba70 492 if (pipe>5) return 0xff;
epgmdm 2:ca0a3c0bba70 493 if (pipe ==0) {
nixonkj 8:3e027705ce23 494 memcpy(pipe0Add,address, addressWidth);
epgmdm 2:ca0a3c0bba70 495 }
epgmdm 2:ca0a3c0bba70 496
epgmdm 0:8fd0531ae0be 497 char reg = 0x0A + pipe;
epgmdm 0:8fd0531ae0be 498 switch ( pipe ) {
epgmdm 16:a9b83d2b6915 499 case ( 0 ) :
epgmdm 0:8fd0531ae0be 500 case ( 1 ) : {
epgmdm 16:a9b83d2b6915 501 writeReg(reg, address, addressWidth); //Write to RX_ADDR_P0 or _P1
epgmdm 16:a9b83d2b6915 502 break;
epgmdm 16:a9b83d2b6915 503 }
epgmdm 16:a9b83d2b6915 504 case ( 2 ) :
epgmdm 16:a9b83d2b6915 505 case ( 3 ) :
epgmdm 16:a9b83d2b6915 506 case ( 4 ) :
epgmdm 16:a9b83d2b6915 507 case ( 5 ) : {
epgmdm 16:a9b83d2b6915 508 writeReg(reg, address, 1); //Write to RX_ADDR_P2 ... _P5
epgmdm 16:a9b83d2b6915 509 break;
epgmdm 16:a9b83d2b6915 510 }
epgmdm 0:8fd0531ae0be 511
epgmdm 0:8fd0531ae0be 512 }
nixonkj 8:3e027705ce23 513 readReg(EN_RXADDR, &reg);
epgmdm 2:ca0a3c0bba70 514 reg |= (1<<pipe);
nixonkj 8:3e027705ce23 515 writeReg(EN_RXADDR, reg); //Enable the pipe
nixonkj 6:77ead8abdd1c 516 return 0; // Must fix this
epgmdm 0:8fd0531ae0be 517 }
epgmdm 0:8fd0531ae0be 518
epgmdm 0:8fd0531ae0be 519 /**
epgmdm 0:8fd0531ae0be 520 * Sets the address of pipe (<=5), uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 521 */
epgmdm 0:8fd0531ae0be 522 char NRF2401P::setRxAddress( long long address, char pipe )
epgmdm 0:8fd0531ae0be 523 {
epgmdm 0:8fd0531ae0be 524 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 525 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 526 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 527 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 528 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 529 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 530 return setRxAddress( buff, pipe );
epgmdm 0:8fd0531ae0be 531 }
nixonkj 6:77ead8abdd1c 532
epgmdm 1:ff53b1ac3bad 533 /**
epgmdm 1:ff53b1ac3bad 534 *checks the status flag
epgmdm 1:ff53b1ac3bad 535 */
epgmdm 1:ff53b1ac3bad 536 char NRF2401P::checkStatus()
epgmdm 1:ff53b1ac3bad 537 {
nixonkj 8:3e027705ce23 538 readReg(STATUS, &status);
epgmdm 1:ff53b1ac3bad 539 return status;
epgmdm 1:ff53b1ac3bad 540 }
nixonkj 6:77ead8abdd1c 541
epgmdm 1:ff53b1ac3bad 542 /**
epgmdm 1:ff53b1ac3bad 543 * checks if Ack data available.
epgmdm 1:ff53b1ac3bad 544 */
epgmdm 1:ff53b1ac3bad 545 bool NRF2401P::isAckData()
epgmdm 1:ff53b1ac3bad 546 {
epgmdm 1:ff53b1ac3bad 547 char fifo;
nixonkj 8:3e027705ce23 548 readReg(FIFO_STATUS, &fifo);
epgmdm 1:ff53b1ac3bad 549 bool isData = !(fifo&0x01);
epgmdm 1:ff53b1ac3bad 550 return isData;
epgmdm 1:ff53b1ac3bad 551 }
epgmdm 0:8fd0531ae0be 552
epgmdm 1:ff53b1ac3bad 553 /**
epgmdm 1:ff53b1ac3bad 554 * checks if RX data available.
epgmdm 1:ff53b1ac3bad 555 */
epgmdm 0:8fd0531ae0be 556 bool NRF2401P::isRxData()
epgmdm 0:8fd0531ae0be 557 {
epgmdm 1:ff53b1ac3bad 558 checkStatus();
epgmdm 0:8fd0531ae0be 559 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 560 return isData;
epgmdm 0:8fd0531ae0be 561 }
nixonkj 6:77ead8abdd1c 562
epgmdm 0:8fd0531ae0be 563 char NRF2401P::getRxWidth()
epgmdm 0:8fd0531ae0be 564 {
epgmdm 0:8fd0531ae0be 565 char width;
epgmdm 0:8fd0531ae0be 566 if (dynamic) {
epgmdm 0:8fd0531ae0be 567 csn = 0;
nixonkj 14:976a876819ae 568 status = spi->write( R_RX_PL_WID );
epgmdm 0:8fd0531ae0be 569 width = spi->write(0x00);
epgmdm 0:8fd0531ae0be 570 csn = 1;
epgmdm 0:8fd0531ae0be 571
nixonkj 14:976a876819ae 572 if (width>32) { // as per product spec
epgmdm 0:8fd0531ae0be 573 flushRx();
nixonkj 14:976a876819ae 574 wait(0.002f); // little delay (KJN)
epgmdm 0:8fd0531ae0be 575 width=0;
epgmdm 0:8fd0531ae0be 576 }
epgmdm 0:8fd0531ae0be 577 } else {
nixonkj 8:3e027705ce23 578 readReg(RX_PW_P1, &width); // width of p1
epgmdm 0:8fd0531ae0be 579 }
epgmdm 16:a9b83d2b6915 580
epgmdm 0:8fd0531ae0be 581 return width;
epgmdm 0:8fd0531ae0be 582 }
nixonkj 6:77ead8abdd1c 583
epgmdm 0:8fd0531ae0be 584 /**
epgmdm 0:8fd0531ae0be 585 * return message in buffer, mem for buffer must have been allocated.
epgmdm 0:8fd0531ae0be 586 * Return value is number of bytes of buffer
epgmdm 0:8fd0531ae0be 587 */
epgmdm 0:8fd0531ae0be 588 char NRF2401P::getRxData(char * buffer)
epgmdm 0:8fd0531ae0be 589 {
epgmdm 0:8fd0531ae0be 590 char address = 0x61;
epgmdm 0:8fd0531ae0be 591 char width;
epgmdm 0:8fd0531ae0be 592 width = getRxWidth();
epgmdm 0:8fd0531ae0be 593 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 594 if (isData) {
epgmdm 0:8fd0531ae0be 595 csn = 0;
epgmdm 0:8fd0531ae0be 596 int i;
epgmdm 0:8fd0531ae0be 597 // set up for reading
epgmdm 0:8fd0531ae0be 598 status = spi->write( address );
epgmdm 0:8fd0531ae0be 599 for ( i = 0; i <= width; i++ ) {
epgmdm 0:8fd0531ae0be 600 buffer[i]=spi->write(0x00 );
epgmdm 0:8fd0531ae0be 601 }
epgmdm 0:8fd0531ae0be 602 csn = 1;
nixonkj 6:77ead8abdd1c 603 if (debug) {
nixonkj 6:77ead8abdd1c 604 sprintf(logMsg, "Receive data %d bytes", width );
nixonkj 6:77ead8abdd1c 605 log(logMsg);
nixonkj 6:77ead8abdd1c 606 }
epgmdm 0:8fd0531ae0be 607 clearStatus();
epgmdm 0:8fd0531ae0be 608 return width;
epgmdm 0:8fd0531ae0be 609 } else {
nixonkj 6:77ead8abdd1c 610 if (debug) {
nixonkj 6:77ead8abdd1c 611 sprintf(logMsg, "Receive NO data %d bytes", width );
nixonkj 6:77ead8abdd1c 612 log(logMsg);
nixonkj 6:77ead8abdd1c 613 }
epgmdm 0:8fd0531ae0be 614 clearStatus();
epgmdm 0:8fd0531ae0be 615 return 0;
epgmdm 0:8fd0531ae0be 616 }
epgmdm 0:8fd0531ae0be 617 }
epgmdm 0:8fd0531ae0be 618
epgmdm 0:8fd0531ae0be 619 /**
epgmdm 0:8fd0531ae0be 620 * Sets all the receive pipes to dynamic payload length
epgmdm 0:8fd0531ae0be 621 */
epgmdm 2:ca0a3c0bba70 622 void NRF2401P::setDynamicPayload()
epgmdm 0:8fd0531ae0be 623 {
epgmdm 0:8fd0531ae0be 624 dynamic = true;
nixonkj 8:3e027705ce23 625 writeReg(FEATURE, 0x07); // Enable Dyn payload, Payload with Ack and w_tx_noack command
nixonkj 8:3e027705ce23 626 writeReg(EN_AA, 0x3f); // EN_AA regi for P1 and P0
nixonkj 9:c21b80aaf250 627 writeReg(DYNPD, 0x3F); // KJN - should be 0x3F for all pipes
epgmdm 0:8fd0531ae0be 628 }
epgmdm 2:ca0a3c0bba70 629
epgmdm 0:8fd0531ae0be 630 /**
epgmdm 0:8fd0531ae0be 631 * Sets PWR_UP = 1;
nixonkj 6:77ead8abdd1c 632 * return 0 on success
epgmdm 0:8fd0531ae0be 633 */
nixonkj 6:77ead8abdd1c 634 char NRF2401P::setPwrUp()
epgmdm 0:8fd0531ae0be 635 {
epgmdm 0:8fd0531ae0be 636 char data;
epgmdm 0:8fd0531ae0be 637 char bit;
epgmdm 0:8fd0531ae0be 638 ce=1;
nixonkj 8:3e027705ce23 639 readReg(CONFIG, &data);
epgmdm 2:ca0a3c0bba70 640 if ((data>>1) &0x01) {
epgmdm 2:ca0a3c0bba70 641 return true; // Already powered up
epgmdm 2:ca0a3c0bba70 642 };
nixonkj 8:3e027705ce23 643 data |= (0x02);
nixonkj 8:3e027705ce23 644 writeReg(CONFIG, data);
epgmdm 0:8fd0531ae0be 645 // check
nixonkj 8:3e027705ce23 646 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 647 bit = ( data >> 1 ) & 1;
epgmdm 2:ca0a3c0bba70 648
epgmdm 0:8fd0531ae0be 649 wait(0.005); // wait 5ms
epgmdm 2:ca0a3c0bba70 650 if(debug) {
epgmdm 2:ca0a3c0bba70 651 sprintf(logMsg, "Set PWR_UP to %x", bit);
epgmdm 2:ca0a3c0bba70 652 log(logMsg);
epgmdm 2:ca0a3c0bba70 653 }
nixonkj 6:77ead8abdd1c 654 if (bit == 1) {
nixonkj 6:77ead8abdd1c 655 return 0;
nixonkj 6:77ead8abdd1c 656 } else {
nixonkj 6:77ead8abdd1c 657 return 1;
nixonkj 6:77ead8abdd1c 658 }
nixonkj 6:77ead8abdd1c 659 }
epgmdm 2:ca0a3c0bba70 660
epgmdm 0:8fd0531ae0be 661 /**
epgmdm 0:8fd0531ae0be 662 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 663 */
nixonkj 6:77ead8abdd1c 664 char NRF2401P::setRxMode()
epgmdm 0:8fd0531ae0be 665 {
epgmdm 0:8fd0531ae0be 666 char data;
epgmdm 0:8fd0531ae0be 667 char bit;
epgmdm 0:8fd0531ae0be 668 ce=1;
nixonkj 8:3e027705ce23 669 readReg(CONFIG, &data);
nixonkj 8:3e027705ce23 670 data |= (0x01);
epgmdm 2:ca0a3c0bba70 671
nixonkj 8:3e027705ce23 672 writeReg(CONFIG, data);
epgmdm 3:afe8d307b5c3 673 if (pipe0Add[0]|pipe0Add[1]|pipe0Add[2]|pipe0Add[3]|pipe0Add[4] >0) {
epgmdm 3:afe8d307b5c3 674 setRxAddress(pipe0Add,0);
epgmdm 2:ca0a3c0bba70 675 }
epgmdm 0:8fd0531ae0be 676 // check
nixonkj 8:3e027705ce23 677 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 678 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 679
epgmdm 2:ca0a3c0bba70 680 wait (0.001);
epgmdm 0:8fd0531ae0be 681 flushRx();
epgmdm 2:ca0a3c0bba70 682 flushTx();
epgmdm 2:ca0a3c0bba70 683 if (debug) {
epgmdm 2:ca0a3c0bba70 684 sprintf(logMsg, " set PRIM_RX to %x", bit);
epgmdm 2:ca0a3c0bba70 685 log(logMsg);
epgmdm 2:ca0a3c0bba70 686 }
nixonkj 6:77ead8abdd1c 687 if ( bit == 1 ) {
nixonkj 6:77ead8abdd1c 688 return 0;
nixonkj 6:77ead8abdd1c 689 } else {
nixonkj 6:77ead8abdd1c 690 return 1;
nixonkj 6:77ead8abdd1c 691 }
epgmdm 0:8fd0531ae0be 692 }
nixonkj 6:77ead8abdd1c 693
epgmdm 0:8fd0531ae0be 694 /**
epgmdm 0:8fd0531ae0be 695 * Prints status string
epgmdm 0:8fd0531ae0be 696 */
epgmdm 0:8fd0531ae0be 697 char * NRF2401P::statusString()
epgmdm 0:8fd0531ae0be 698 {
epgmdm 0:8fd0531ae0be 699 char *msg;
epgmdm 0:8fd0531ae0be 700 msg = statusS;
epgmdm 0:8fd0531ae0be 701 if (((status>>1) & 0x07)==0x07) {
epgmdm 0:8fd0531ae0be 702 sprintf(msg,"RX empty");
epgmdm 0:8fd0531ae0be 703 } else {
epgmdm 0:8fd0531ae0be 704 sprintf(msg,"pipe %02x",(status>>1) & 0x07);
epgmdm 0:8fd0531ae0be 705 }
epgmdm 0:8fd0531ae0be 706
epgmdm 0:8fd0531ae0be 707 if ((status>>6)&0x01) strcat(msg," RX_DR,");
epgmdm 0:8fd0531ae0be 708 if ((status>>5)&0x01) strcat(msg," TX_DS,");
epgmdm 0:8fd0531ae0be 709 if ((status>>4)&0x01) strcat(msg," MAX_RT,");
epgmdm 0:8fd0531ae0be 710 if ((status>>0)&0x01) strcat(msg," TX_FLL,");
epgmdm 0:8fd0531ae0be 711
epgmdm 0:8fd0531ae0be 712 return msg;
nixonkj 9:c21b80aaf250 713 }
nixonkj 9:c21b80aaf250 714
nixonkj 11:07f76589f00a 715 void NRF2401P::printReg(char* name, char address, bool newline)
nixonkj 9:c21b80aaf250 716 {
nixonkj 9:c21b80aaf250 717 char data;
nixonkj 11:07f76589f00a 718 readReg(address, &data);
nixonkj 11:07f76589f00a 719 printf("%s = 0x%02x", name, data);
nixonkj 11:07f76589f00a 720 if (newline) {
nixonkj 11:07f76589f00a 721 printf("\r\n");
nixonkj 11:07f76589f00a 722 }
epgmdm 16:a9b83d2b6915 723 }
epgmdm 16:a9b83d2b6915 724
nixonkj 11:07f76589f00a 725 void NRF2401P::printReg(char* name, char address, char width, bool newline)
nixonkj 11:07f76589f00a 726 {
nixonkj 11:07f76589f00a 727 char data[width];
nixonkj 11:07f76589f00a 728 readReg(address, data, width);
nixonkj 11:07f76589f00a 729 printf("%s = 0x", name);
nixonkj 11:07f76589f00a 730 for (int i=width-1; i>=0; i--) {
nixonkj 11:07f76589f00a 731 printf("%02x", data[i]);
nixonkj 11:07f76589f00a 732 }
nixonkj 11:07f76589f00a 733 if (newline) {
nixonkj 11:07f76589f00a 734 printf("\r\n");
nixonkj 11:07f76589f00a 735 }
nixonkj 11:07f76589f00a 736 }
nixonkj 11:07f76589f00a 737
nixonkj 11:07f76589f00a 738 void NRF2401P::printDetails() {
nixonkj 14:976a876819ae 739 status = checkStatus();
nixonkj 11:07f76589f00a 740 printf("STATUS = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n", status,
nixonkj 9:c21b80aaf250 741 (status & (1<<MASK_RX_DR))?1:0,
nixonkj 9:c21b80aaf250 742 (status & (1<<MASK_TX_DS))?1:0,
nixonkj 9:c21b80aaf250 743 (status & (1<<MASK_MAX_RT))?1:0,
nixonkj 9:c21b80aaf250 744 (status >> RX_P_NO) & 7,
nixonkj 9:c21b80aaf250 745 (status & (1<<TX_FULL))?1:0 );
nixonkj 9:c21b80aaf250 746
nixonkj 11:07f76589f00a 747 printReg("RX_ADDR_P0", RX_ADDR_P0, addressWidth);
nixonkj 11:07f76589f00a 748 printReg("RX_ADDR_P1", RX_ADDR_P1, addressWidth);
nixonkj 11:07f76589f00a 749 printReg("RX_ADDR_P2", RX_ADDR_P2, addressWidth);
nixonkj 11:07f76589f00a 750 printReg("RX_ADDR_P3", RX_ADDR_P3, addressWidth);
nixonkj 11:07f76589f00a 751 printReg("RX_ADDR_P4", RX_ADDR_P4, addressWidth);
nixonkj 11:07f76589f00a 752 printReg("RX_ADDR_P5", RX_ADDR_P5, addressWidth);
nixonkj 11:07f76589f00a 753 printReg("TX_ADDR", TX_ADDR, addressWidth);
nixonkj 10:8a217441c38e 754
nixonkj 11:07f76589f00a 755 printReg("RX_PW_P0", RX_PW_P0, false); // false for no newline, save some space
nixonkj 11:07f76589f00a 756 printReg(" RX_PW_P1", RX_PW_P1, false);
nixonkj 11:07f76589f00a 757 printReg(" RX_PW_P2", RX_PW_P2);
nixonkj 11:07f76589f00a 758 printReg("RX_PW_P3", RX_PW_P3, false);
nixonkj 11:07f76589f00a 759 printReg(" RX_PW_P4", RX_PW_P4, false);
nixonkj 11:07f76589f00a 760 printReg(" RX_PW_P5", RX_PW_P5);
nixonkj 11:07f76589f00a 761
nixonkj 11:07f76589f00a 762 printReg("EN_AA", EN_AA);
nixonkj 11:07f76589f00a 763 printReg("EN_RXADDR", EN_RXADDR);
nixonkj 11:07f76589f00a 764 printReg("RF_CH", RF_CH);
nixonkj 11:07f76589f00a 765 printReg("RF_SETUP", RF_SETUP);
nixonkj 12:ea1345de6478 766 printReg("CONFIG", CONFIG);
nixonkj 11:07f76589f00a 767 printReg("DYNPD", DYNPD);
nixonkj 11:07f76589f00a 768 printReg("FEATURE", FEATURE);
epgmdm 0:8fd0531ae0be 769 }