Damien Frost / NRF2401P

My fork during debugging.

Fork of NRF2401P by Malcolm McCulloch

NRF2401P.cpp@13:5cbc726f2bbb, 2015-07-11 (annotated)

Committer:
nixonkj
Date:
Sat Jul 11 21:20:56 2015 +0000
Revision:
13:5cbc726f2bbb
Parent:
12:ea1345de6478
Child:
14:976a876819ae
Provides isRPDset() - check if radio signal > -64dBm.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
epgmdm 0:8fd0531ae0be 1 /**
epgmdm 0:8fd0531ae0be 2 *@section DESCRIPTION
epgmdm 0:8fd0531ae0be 3 * mbed NRF2401+ Library
epgmdm 0:8fd0531ae0be 4 *@section LICENSE
epgmdm 0:8fd0531ae0be 5 * Copyright (c) 2015, Malcolm McCulloch
epgmdm 0:8fd0531ae0be 6 *
epgmdm 0:8fd0531ae0be 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
epgmdm 0:8fd0531ae0be 8 * of this software and associated documentation files (the "Software"), to deal
epgmdm 0:8fd0531ae0be 9 * in the Software without restriction, including without limitation the rights
epgmdm 0:8fd0531ae0be 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
epgmdm 0:8fd0531ae0be 11 * copies of the Software, and to permit persons to whom the Software is
epgmdm 0:8fd0531ae0be 12 * furnished to do so, subject to the following conditions:
epgmdm 0:8fd0531ae0be 13 *
epgmdm 0:8fd0531ae0be 14 * The above copyright notice and this permission notice shall be included in
epgmdm 0:8fd0531ae0be 15 * all copies or substantial portions of the Software.
epgmdm 0:8fd0531ae0be 16 *
epgmdm 0:8fd0531ae0be 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
epgmdm 0:8fd0531ae0be 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
epgmdm 0:8fd0531ae0be 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
epgmdm 0:8fd0531ae0be 20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
epgmdm 0:8fd0531ae0be 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
epgmdm 0:8fd0531ae0be 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
epgmdm 0:8fd0531ae0be 23 * THE SOFTWARE.
epgmdm 0:8fd0531ae0be 24 * @file "NRF2401P.cpp"
epgmdm 0:8fd0531ae0be 25 */
epgmdm 2:ca0a3c0bba70 26 #include "mbed.h"
epgmdm 2:ca0a3c0bba70 27 #include "NRF2401P.h"
epgmdm 2:ca0a3c0bba70 28 #include "nRF24l01.h"
epgmdm 0:8fd0531ae0be 29
epgmdm 0:8fd0531ae0be 30 NRF2401P::NRF2401P ( PinName mosi, PinName miso, PinName sclk, PinName _csn, PinName _ce ) :
epgmdm 0:8fd0531ae0be 31 csn( DigitalOut( _csn ) ), ce( DigitalOut( _ce ) )
epgmdm 0:8fd0531ae0be 32 {
epgmdm 0:8fd0531ae0be 33 addressWidth = 5;
epgmdm 0:8fd0531ae0be 34 pc = new Serial( USBTX, USBRX ); // tx, rx
nixonkj 6:77ead8abdd1c 35 if (debug) {
nixonkj 6:77ead8abdd1c 36 sprintf(logMsg, "Initialise" );
nixonkj 6:77ead8abdd1c 37 log(logMsg);
nixonkj 6:77ead8abdd1c 38 }
epgmdm 0:8fd0531ae0be 39 spi = new SPI( mosi, miso, sclk, NC ); //SPI (PinName mosi, PinName miso, PinName sclk, PinName _unused=NC)
epgmdm 0:8fd0531ae0be 40 spi->frequency( 10000000 ); // 1MHZ max 10 MHz
epgmdm 0:8fd0531ae0be 41 spi->format( 8, 0 ); // 0: 0e 08; 1: 0e 00; 2:0e 00 ;3:1c 00
epgmdm 0:8fd0531ae0be 42 csn = 1;
epgmdm 0:8fd0531ae0be 43 ce = 0;
epgmdm 0:8fd0531ae0be 44 dynamic = false;
nixonkj 6:77ead8abdd1c 45 debug = false;
nixonkj 6:77ead8abdd1c 46 }
epgmdm 0:8fd0531ae0be 47
nixonkj 6:77ead8abdd1c 48 void NRF2401P::log(char *msg)
epgmdm 0:8fd0531ae0be 49 {
epgmdm 0:8fd0531ae0be 50 if(debug) {
nixonkj 8:3e027705ce23 51 printf("\t <%s \t %s>\n\r", statusString(), msg);
epgmdm 1:ff53b1ac3bad 52 wait(0.01);
nixonkj 6:77ead8abdd1c 53 }
epgmdm 0:8fd0531ae0be 54 }
epgmdm 0:8fd0531ae0be 55
epgmdm 0:8fd0531ae0be 56 void NRF2401P::scratch()
epgmdm 0:8fd0531ae0be 57 {
epgmdm 0:8fd0531ae0be 58 int status = 0;
epgmdm 0:8fd0531ae0be 59 int register1 = 0;
epgmdm 0:8fd0531ae0be 60 ce = 0;
epgmdm 0:8fd0531ae0be 61 for ( char i = 0; i < 24; i++ ) {
epgmdm 0:8fd0531ae0be 62 csn = 0;
epgmdm 0:8fd0531ae0be 63 //wait_us(100);
epgmdm 0:8fd0531ae0be 64 status = spi->write( i );
epgmdm 0:8fd0531ae0be 65 register1 = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 66 csn = 1;
epgmdm 0:8fd0531ae0be 67 sprintf(logMsg, " register %02x (%02x) = %02x", i, status, register1 );
epgmdm 0:8fd0531ae0be 68 log(logMsg);
epgmdm 0:8fd0531ae0be 69 }
nixonkj 6:77ead8abdd1c 70 }
epgmdm 0:8fd0531ae0be 71
epgmdm 0:8fd0531ae0be 72 /**
epgmdm 2:ca0a3c0bba70 73 * start here to configure the basics of the NRF
epgmdm 2:ca0a3c0bba70 74 */
epgmdm 2:ca0a3c0bba70 75 void NRF2401P::start()
epgmdm 2:ca0a3c0bba70 76 {
nixonkj 8:3e027705ce23 77 writeReg(CONFIG, 0x0c); // set 16 bit crc
nixonkj 8:3e027705ce23 78 setTxRetry(0x01, 0x0f); // 500 uS, 15 retries
nixonkj 8:3e027705ce23 79 setRadio(0, 0x03); // 1MB/S 0dB
epgmdm 2:ca0a3c0bba70 80 setDynamicPayload();
epgmdm 2:ca0a3c0bba70 81 setChannel(76); // should be clear?
epgmdm 2:ca0a3c0bba70 82 setAddressWidth(5);
epgmdm 2:ca0a3c0bba70 83 flushRx();
epgmdm 2:ca0a3c0bba70 84 flushTx();
epgmdm 2:ca0a3c0bba70 85 setPwrUp();
epgmdm 2:ca0a3c0bba70 86 setTxMode(); // just make sure no spurious reads....
nixonkj 6:77ead8abdd1c 87 }
epgmdm 2:ca0a3c0bba70 88
epgmdm 2:ca0a3c0bba70 89 /**
nixonkj 8:3e027705ce23 90 * Sets up a receiver using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 91 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 92 */
epgmdm 2:ca0a3c0bba70 93 void NRF2401P::quickRxSetup(int channel,long long addrRx)
epgmdm 0:8fd0531ae0be 94 {
epgmdm 2:ca0a3c0bba70 95 start();
epgmdm 0:8fd0531ae0be 96 setChannel(channel);
epgmdm 2:ca0a3c0bba70 97 setRxAddress(addrRx,1);
epgmdm 0:8fd0531ae0be 98 setRxMode();
epgmdm 0:8fd0531ae0be 99 ce=1;
nixonkj 6:77ead8abdd1c 100 wait(0.001f);
epgmdm 0:8fd0531ae0be 101 }
nixonkj 6:77ead8abdd1c 102
epgmdm 0:8fd0531ae0be 103 /**
epgmdm 0:8fd0531ae0be 104 * Sets up for receive of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 105 */
epgmdm 0:8fd0531ae0be 106 char NRF2401P::testReceive()
epgmdm 0:8fd0531ae0be 107 {
epgmdm 0:8fd0531ae0be 108 char message[64];
epgmdm 0:8fd0531ae0be 109 char width;
epgmdm 0:8fd0531ae0be 110 int channel = 0x12;
epgmdm 0:8fd0531ae0be 111 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 112 debug = true;
epgmdm 0:8fd0531ae0be 113 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 114
epgmdm 0:8fd0531ae0be 115 while (1) {
epgmdm 0:8fd0531ae0be 116 while (!isRxData()) {
epgmdm 0:8fd0531ae0be 117 //wait(0.5);
epgmdm 0:8fd0531ae0be 118 };
epgmdm 0:8fd0531ae0be 119 width=getRxData(message);
epgmdm 0:8fd0531ae0be 120 message[width]='\0';
epgmdm 0:8fd0531ae0be 121 sprintf(logMsg,"Received= [%s]",message);
epgmdm 0:8fd0531ae0be 122 log(logMsg);
nixonkj 6:77ead8abdd1c 123 }
epgmdm 0:8fd0531ae0be 124 }
epgmdm 0:8fd0531ae0be 125
nixonkj 6:77ead8abdd1c 126 char NRF2401P::setTxRetry(char delay, char numTries)
epgmdm 2:ca0a3c0bba70 127 {
epgmdm 2:ca0a3c0bba70 128 char val = (delay&0xf)<<4 | (numTries&0xf);
nixonkj 6:77ead8abdd1c 129 char chk;
nixonkj 8:3e027705ce23 130 writeReg(SETUP_RETR, val);
nixonkj 8:3e027705ce23 131 readReg(SETUP_RETR, &chk);
nixonkj 6:77ead8abdd1c 132 if (chk&0xff == val) {
nixonkj 6:77ead8abdd1c 133 return 0;
nixonkj 6:77ead8abdd1c 134 } else {
nixonkj 6:77ead8abdd1c 135 return 1;
nixonkj 6:77ead8abdd1c 136 }
epgmdm 2:ca0a3c0bba70 137 }
epgmdm 2:ca0a3c0bba70 138
epgmdm 2:ca0a3c0bba70 139 /**
epgmdm 0:8fd0531ae0be 140 * Sets up a transmitter using shockburst and dynamic payload. Uses pipe 1
epgmdm 0:8fd0531ae0be 141 * defaults to 5 bytes
epgmdm 0:8fd0531ae0be 142 */
epgmdm 0:8fd0531ae0be 143 void NRF2401P::quickTxSetup(int channel,long long addr)
epgmdm 0:8fd0531ae0be 144 {
epgmdm 2:ca0a3c0bba70 145 start();
epgmdm 0:8fd0531ae0be 146 setChannel(channel);
epgmdm 2:ca0a3c0bba70 147 setTxAddress(addr);
epgmdm 0:8fd0531ae0be 148 setTxMode();
epgmdm 0:8fd0531ae0be 149 ce=1;
epgmdm 0:8fd0531ae0be 150 wait (0.0016f); // wait for pll to settle
epgmdm 0:8fd0531ae0be 151 }
epgmdm 0:8fd0531ae0be 152
epgmdm 0:8fd0531ae0be 153 /**
epgmdm 0:8fd0531ae0be 154 * Sets up for transmit of a message to address 0XA0A0A0
epgmdm 0:8fd0531ae0be 155 */
epgmdm 0:8fd0531ae0be 156 char NRF2401P::testTransmit()
epgmdm 0:8fd0531ae0be 157 {
epgmdm 0:8fd0531ae0be 158 long long addr=0xA0B0C0;
epgmdm 0:8fd0531ae0be 159 int channel = 0x12;
epgmdm 0:8fd0531ae0be 160 char data[32] ;
epgmdm 0:8fd0531ae0be 161 int i=0;
epgmdm 0:8fd0531ae0be 162 quickRxSetup(channel, addr);
epgmdm 0:8fd0531ae0be 163 while (1) {
epgmdm 0:8fd0531ae0be 164 sprintf(data," packet %03d", i++ |100);
epgmdm 0:8fd0531ae0be 165 transmitData(data,18);
epgmdm 0:8fd0531ae0be 166 wait (1.0);
epgmdm 0:8fd0531ae0be 167 }
nixonkj 6:77ead8abdd1c 168 }
epgmdm 0:8fd0531ae0be 169
nixonkj 6:77ead8abdd1c 170 char NRF2401P::setRadio(char speed, char power)
epgmdm 0:8fd0531ae0be 171 {
nixonkj 6:77ead8abdd1c 172 char val=0, chk=0;
nixonkj 8:3e027705ce23 173 if (debug) {
nixonkj 8:3e027705ce23 174 sprintf(logMsg, "Set radio");
nixonkj 8:3e027705ce23 175 log(logMsg);
nixonkj 8:3e027705ce23 176 }
epgmdm 0:8fd0531ae0be 177 if (speed & 0x02) {
epgmdm 0:8fd0531ae0be 178 val |= (1<<5);
epgmdm 0:8fd0531ae0be 179 }
epgmdm 0:8fd0531ae0be 180 val |= (speed & 0x01)<<3;
epgmdm 0:8fd0531ae0be 181
nixonkj 6:77ead8abdd1c 182 val |= ((power & 0x03)<<1);
nixonkj 6:77ead8abdd1c 183 printf("\n\r");
nixonkj 6:77ead8abdd1c 184
nixonkj 8:3e027705ce23 185 writeReg(RF_SETUP, val);
epgmdm 0:8fd0531ae0be 186
nixonkj 6:77ead8abdd1c 187 // read register to verify settings
nixonkj 8:3e027705ce23 188 readReg(RF_SETUP, &chk);
nixonkj 6:77ead8abdd1c 189 if (chk&0x2E == val) {
nixonkj 6:77ead8abdd1c 190 return 0;
nixonkj 6:77ead8abdd1c 191 } else {
nixonkj 6:77ead8abdd1c 192 return 1;
nixonkj 6:77ead8abdd1c 193 }
epgmdm 0:8fd0531ae0be 194 }
nixonkj 6:77ead8abdd1c 195
epgmdm 0:8fd0531ae0be 196 char NRF2401P::setChannel(char chan)
epgmdm 0:8fd0531ae0be 197 {
nixonkj 6:77ead8abdd1c 198 char chk=0;
nixonkj 6:77ead8abdd1c 199 if (debug) {
nixonkj 6:77ead8abdd1c 200 sprintf(logMsg, "Set channel");
nixonkj 6:77ead8abdd1c 201 log(logMsg);
nixonkj 6:77ead8abdd1c 202 }
nixonkj 8:3e027705ce23 203 writeReg(RF_CH, (chan&0x7f));
nixonkj 8:3e027705ce23 204 readReg(RF_CH, &chk);
nixonkj 6:77ead8abdd1c 205 if (chk&0x7f == chan&0x7f) {
nixonkj 6:77ead8abdd1c 206 return 0;
nixonkj 6:77ead8abdd1c 207 } else {
nixonkj 6:77ead8abdd1c 208 return 1;
nixonkj 6:77ead8abdd1c 209 }
epgmdm 0:8fd0531ae0be 210 }
nixonkj 6:77ead8abdd1c 211
nixonkj 13:5cbc726f2bbb 212 bool NRF2401P::isRPDset()
nixonkj 13:5cbc726f2bbb 213 {
nixonkj 13:5cbc726f2bbb 214 char val=0;
nixonkj 13:5cbc726f2bbb 215 if (debug) {
nixonkj 13:5cbc726f2bbb 216 sprintf(logMsg, "Get RPD");
nixonkj 13:5cbc726f2bbb 217 log(logMsg);
nixonkj 13:5cbc726f2bbb 218 }
nixonkj 13:5cbc726f2bbb 219 readReg(RPD, &val);
nixonkj 13:5cbc726f2bbb 220 if (val == 1) {
nixonkj 13:5cbc726f2bbb 221 return true;
nixonkj 13:5cbc726f2bbb 222 } else {
nixonkj 13:5cbc726f2bbb 223 return false;
nixonkj 13:5cbc726f2bbb 224 }
nixonkj 13:5cbc726f2bbb 225 }
nixonkj 13:5cbc726f2bbb 226
epgmdm 0:8fd0531ae0be 227 /**
epgmdm 0:8fd0531ae0be 228 * Transmits width bytes of data. width <32
epgmdm 0:8fd0531ae0be 229 */
nixonkj 6:77ead8abdd1c 230 char NRF2401P::transmitData( char *data, char width )
epgmdm 0:8fd0531ae0be 231 {
nixonkj 6:77ead8abdd1c 232 if (width>32)
nixonkj 6:77ead8abdd1c 233 return 0;
nixonkj 6:77ead8abdd1c 234 checkStatus();
nixonkj 6:77ead8abdd1c 235 if ((status>>4)&1) { // Max retries - flush tx
nixonkj 6:77ead8abdd1c 236 flushTx();
nixonkj 6:77ead8abdd1c 237 }
epgmdm 2:ca0a3c0bba70 238 //clearStatus();
epgmdm 2:ca0a3c0bba70 239 //ce = 1;
epgmdm 0:8fd0531ae0be 240 csn = 0;
nixonkj 8:3e027705ce23 241 char address = 0xA0;
epgmdm 0:8fd0531ae0be 242 int i;
epgmdm 0:8fd0531ae0be 243 // set up for writing
epgmdm 0:8fd0531ae0be 244 status = spi->write( address );
epgmdm 0:8fd0531ae0be 245 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 246 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 247 }
epgmdm 0:8fd0531ae0be 248 csn = 1;
epgmdm 3:afe8d307b5c3 249 wait(0.001);
epgmdm 3:afe8d307b5c3 250 if (debug) {
nixonkj 6:77ead8abdd1c 251 sprintf(logMsg, " Transmit data %d bytes to %02x (%02x) = %10s", width, address, status, data );
epgmdm 3:afe8d307b5c3 252 log(logMsg);
epgmdm 2:ca0a3c0bba70 253 }
epgmdm 0:8fd0531ae0be 254 return status;
epgmdm 0:8fd0531ae0be 255 }
epgmdm 0:8fd0531ae0be 256
epgmdm 0:8fd0531ae0be 257 /**
epgmdm 0:8fd0531ae0be 258 * sets acknowledge data width bytes of data. width <32
epgmdm 0:8fd0531ae0be 259 */
epgmdm 1:ff53b1ac3bad 260 char NRF2401P::acknowledgeData( char *data, char width, char pipe )
epgmdm 0:8fd0531ae0be 261 {
epgmdm 0:8fd0531ae0be 262 ce = 1;
epgmdm 0:8fd0531ae0be 263 csn = 0;
epgmdm 2:ca0a3c0bba70 264 //writeReg(0x1d,0x06); // enable payload with ack
epgmdm 2:ca0a3c0bba70 265 char address = W_ACK_PAYLOAD | (pipe&0x07);
epgmdm 0:8fd0531ae0be 266 int i;
epgmdm 0:8fd0531ae0be 267 // set up for writing
epgmdm 3:afe8d307b5c3 268 csn = 0;
epgmdm 0:8fd0531ae0be 269 status = spi->write( address );
epgmdm 0:8fd0531ae0be 270 for ( i = 0; i <width; i++ ) {
epgmdm 0:8fd0531ae0be 271 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 272 }
epgmdm 0:8fd0531ae0be 273 csn = 1;
epgmdm 3:afe8d307b5c3 274 if (debug) {
epgmdm 3:afe8d307b5c3 275 sprintf(logMsg, " acknowledge data %d bytes to %02x (%02x) = %c", width, address, status, *data );
epgmdm 3:afe8d307b5c3 276 log(logMsg);
epgmdm 2:ca0a3c0bba70 277 }
epgmdm 0:8fd0531ae0be 278 return status;
nixonkj 6:77ead8abdd1c 279 }
epgmdm 0:8fd0531ae0be 280
epgmdm 0:8fd0531ae0be 281 /**
epgmdm 0:8fd0531ae0be 282 * Writes 1 byte data to a register
epgmdm 0:8fd0531ae0be 283 **/
nixonkj 6:77ead8abdd1c 284 void NRF2401P::writeReg( char address, char data )
epgmdm 0:8fd0531ae0be 285 {
epgmdm 0:8fd0531ae0be 286 char status = 0;
epgmdm 0:8fd0531ae0be 287 char reg;
epgmdm 0:8fd0531ae0be 288 csn = 0;
epgmdm 0:8fd0531ae0be 289 address &= 0x1F;
nixonkj 8:3e027705ce23 290 reg = address | W_REGISTER;
epgmdm 0:8fd0531ae0be 291 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 292 spi->write( data );
epgmdm 0:8fd0531ae0be 293 csn = 1;
nixonkj 6:77ead8abdd1c 294 if (debug) {
nixonkj 6:77ead8abdd1c 295 sprintf(logMsg, " register write %02x (%02x) = %02x", address, status, data );
nixonkj 6:77ead8abdd1c 296 log(logMsg);
nixonkj 6:77ead8abdd1c 297 }
epgmdm 0:8fd0531ae0be 298 }
nixonkj 6:77ead8abdd1c 299
epgmdm 0:8fd0531ae0be 300 /**
epgmdm 0:8fd0531ae0be 301 * Writes width bytes data to a register, ls byte to ms byte /for adressess
epgmdm 0:8fd0531ae0be 302 **/
nixonkj 6:77ead8abdd1c 303 void NRF2401P::writeReg( char address, char *data, char width )
epgmdm 0:8fd0531ae0be 304 {
epgmdm 0:8fd0531ae0be 305 char reg;
epgmdm 0:8fd0531ae0be 306 csn = 0;
epgmdm 0:8fd0531ae0be 307 int i;
epgmdm 0:8fd0531ae0be 308 // set up for writing
epgmdm 0:8fd0531ae0be 309 address &= 0x1F;
nixonkj 8:3e027705ce23 310 reg = address| W_REGISTER;
epgmdm 0:8fd0531ae0be 311 status = spi->write( reg );
epgmdm 0:8fd0531ae0be 312 for ( i = width - 1; i >= 0; i-- ) {
epgmdm 0:8fd0531ae0be 313 spi->write( data[ i ] );
epgmdm 0:8fd0531ae0be 314 }
epgmdm 0:8fd0531ae0be 315 csn = 1;
epgmdm 2:ca0a3c0bba70 316 if (debug) {
epgmdm 2:ca0a3c0bba70 317 sprintf(logMsg, " register write %d bytes to %02x (%02x) = %02x %02x %02x", width, address, status, data[0], data[1], data[2] );
epgmdm 2:ca0a3c0bba70 318 log(logMsg);
epgmdm 2:ca0a3c0bba70 319 }
epgmdm 0:8fd0531ae0be 320 }
nixonkj 6:77ead8abdd1c 321
epgmdm 0:8fd0531ae0be 322 /**
epgmdm 0:8fd0531ae0be 323 * Reads 1 byte from a register
epgmdm 0:8fd0531ae0be 324 **/
nixonkj 6:77ead8abdd1c 325 void NRF2401P::readReg( char address, char *data )
epgmdm 0:8fd0531ae0be 326 {
epgmdm 0:8fd0531ae0be 327 csn = 0;
epgmdm 0:8fd0531ae0be 328 address &= 0x1F;
epgmdm 0:8fd0531ae0be 329 status = spi->write( address );
epgmdm 0:8fd0531ae0be 330 *data = spi->write( 0x00 );
epgmdm 0:8fd0531ae0be 331 csn = 1;
nixonkj 6:77ead8abdd1c 332 if (debug && address != 0x07) { // In debug mode: print out anything other than a status request
nixonkj 6:77ead8abdd1c 333 sprintf(logMsg, " register read %02x (%02x) = %02x", address, status, *data );
nixonkj 6:77ead8abdd1c 334 log(logMsg);
nixonkj 6:77ead8abdd1c 335 }
epgmdm 0:8fd0531ae0be 336 }
nixonkj 6:77ead8abdd1c 337
epgmdm 0:8fd0531ae0be 338 /**
nixonkj 10:8a217441c38e 339 * Reads n bytes from a register
nixonkj 10:8a217441c38e 340 **/
nixonkj 10:8a217441c38e 341 void NRF2401P::readReg( char address, char *data, char width )
nixonkj 10:8a217441c38e 342 {
nixonkj 10:8a217441c38e 343 char reg;
nixonkj 10:8a217441c38e 344 csn = 0;
nixonkj 10:8a217441c38e 345 int i;
nixonkj 10:8a217441c38e 346 // set up for writing
nixonkj 10:8a217441c38e 347 address &= 0x1F;
nixonkj 10:8a217441c38e 348 reg = address| R_REGISTER;
nixonkj 10:8a217441c38e 349 status = spi->write( reg );
nixonkj 10:8a217441c38e 350 for ( i = width - 1; i >= 0; i-- ) {
nixonkj 10:8a217441c38e 351 data[i] = spi->write( 0x00 );
nixonkj 10:8a217441c38e 352 }
nixonkj 10:8a217441c38e 353 csn = 1;
nixonkj 10:8a217441c38e 354 if (debug) {
nixonkj 10:8a217441c38e 355 sprintf(logMsg, " register read %d bytes from %02x (%02x) = ", width, address, status );
nixonkj 10:8a217441c38e 356 for ( i=0; i<width; i++)
nixonkj 10:8a217441c38e 357 sprintf(logMsg, "%s %02x", logMsg, data[i]);
nixonkj 10:8a217441c38e 358 log(logMsg);
nixonkj 10:8a217441c38e 359 }
nixonkj 10:8a217441c38e 360 }
nixonkj 10:8a217441c38e 361
nixonkj 10:8a217441c38e 362 /**
epgmdm 0:8fd0531ae0be 363 * Clears the status flags RX_DR, TX_DS, MAX_RT
epgmdm 0:8fd0531ae0be 364 */
nixonkj 6:77ead8abdd1c 365 void NRF2401P::clearStatus()
epgmdm 0:8fd0531ae0be 366 {
nixonkj 8:3e027705ce23 367 writeReg(STATUS, 0x70);
epgmdm 2:ca0a3c0bba70 368 if (debug) {
epgmdm 2:ca0a3c0bba70 369 sprintf(logMsg, "Clear status (%02x)", status );
epgmdm 2:ca0a3c0bba70 370 log(logMsg);
epgmdm 2:ca0a3c0bba70 371 }
epgmdm 0:8fd0531ae0be 372 }
nixonkj 6:77ead8abdd1c 373
epgmdm 0:8fd0531ae0be 374 /**
epgmdm 0:8fd0531ae0be 375 * flushes TX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 376 */
nixonkj 6:77ead8abdd1c 377 void NRF2401P::flushTx()
epgmdm 0:8fd0531ae0be 378 {
epgmdm 0:8fd0531ae0be 379 csn = 0;
epgmdm 2:ca0a3c0bba70 380 status = spi->write( FLUSH_TX );
epgmdm 0:8fd0531ae0be 381 csn = 1;
epgmdm 0:8fd0531ae0be 382 clearStatus();
epgmdm 2:ca0a3c0bba70 383 if (debug) {
epgmdm 2:ca0a3c0bba70 384 sprintf(logMsg, "Flush TX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 385 log(logMsg);
epgmdm 2:ca0a3c0bba70 386 }
epgmdm 0:8fd0531ae0be 387 }
epgmdm 0:8fd0531ae0be 388
epgmdm 0:8fd0531ae0be 389 /**
epgmdm 0:8fd0531ae0be 390 * flushes RX FIFO and resets status flags
epgmdm 0:8fd0531ae0be 391 */
nixonkj 6:77ead8abdd1c 392 void NRF2401P::flushRx()
epgmdm 0:8fd0531ae0be 393 {
epgmdm 0:8fd0531ae0be 394 csn = 0;
epgmdm 2:ca0a3c0bba70 395 status = spi->write( FLUSH_RX );
epgmdm 0:8fd0531ae0be 396 csn = 1;
epgmdm 2:ca0a3c0bba70 397 clearStatus();
epgmdm 2:ca0a3c0bba70 398 if (debug) {
epgmdm 2:ca0a3c0bba70 399 sprintf(logMsg, "Flush RX FIFO (%02x)", status );
epgmdm 2:ca0a3c0bba70 400 log(logMsg);
epgmdm 2:ca0a3c0bba70 401 }
epgmdm 0:8fd0531ae0be 402 }
nixonkj 6:77ead8abdd1c 403
epgmdm 0:8fd0531ae0be 404 /**
epgmdm 0:8fd0531ae0be 405 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 406 */
nixonkj 6:77ead8abdd1c 407 char NRF2401P::setTxMode()
epgmdm 0:8fd0531ae0be 408 {
epgmdm 0:8fd0531ae0be 409 char data;
epgmdm 0:8fd0531ae0be 410 char bit;
epgmdm 2:ca0a3c0bba70 411 if (debug) {
epgmdm 2:ca0a3c0bba70 412 sprintf(logMsg, "Set Tx Mode");
epgmdm 2:ca0a3c0bba70 413 log(logMsg);
epgmdm 2:ca0a3c0bba70 414 }
nixonkj 8:3e027705ce23 415 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 416 data &= ~( 1 << 0 );
epgmdm 2:ca0a3c0bba70 417 flushTx();
epgmdm 2:ca0a3c0bba70 418 flushRx();
nixonkj 8:3e027705ce23 419 writeReg(CONFIG, data);
nixonkj 8:3e027705ce23 420 writeReg(RX_ADDR_P0, txAdd, addressWidth); // reset p0
nixonkj 8:3e027705ce23 421 writeReg(EN_RXADDR, 0x01); // enable pipe 0 for reading
epgmdm 0:8fd0531ae0be 422 // check
nixonkj 8:3e027705ce23 423 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 424 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 425
epgmdm 0:8fd0531ae0be 426 ce=1;
epgmdm 0:8fd0531ae0be 427 wait(0.003);
nixonkj 6:77ead8abdd1c 428 if (bit == 0) {
nixonkj 6:77ead8abdd1c 429 return 0;
nixonkj 6:77ead8abdd1c 430 } else {
nixonkj 6:77ead8abdd1c 431 return 1;
nixonkj 6:77ead8abdd1c 432 }
epgmdm 0:8fd0531ae0be 433 }
epgmdm 0:8fd0531ae0be 434
epgmdm 0:8fd0531ae0be 435 /**
epgmdm 0:8fd0531ae0be 436 * Sets the number of bytes of the address width = 3,4,5
epgmdm 0:8fd0531ae0be 437 */
nixonkj 6:77ead8abdd1c 438 char NRF2401P::setAddressWidth( char width )
epgmdm 0:8fd0531ae0be 439 {
nixonkj 6:77ead8abdd1c 440 char chk=0;
epgmdm 0:8fd0531ae0be 441 addressWidth = width;
epgmdm 0:8fd0531ae0be 442 if ( ( width > 5 ) || ( width < 3 ) )
epgmdm 0:8fd0531ae0be 443 return false;
epgmdm 0:8fd0531ae0be 444 width -= 2;
nixonkj 8:3e027705ce23 445 writeReg(SETUP_AW, width);
nixonkj 8:3e027705ce23 446 readReg(SETUP_AW, &chk);
nixonkj 6:77ead8abdd1c 447 if (chk&0x03 == width) {
nixonkj 6:77ead8abdd1c 448 return 0;
nixonkj 6:77ead8abdd1c 449 } else {
nixonkj 6:77ead8abdd1c 450 return 1;
nixonkj 6:77ead8abdd1c 451 }
epgmdm 0:8fd0531ae0be 452 }
nixonkj 6:77ead8abdd1c 453
epgmdm 0:8fd0531ae0be 454 /**
nixonkj 6:77ead8abdd1c 455 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 456 */
epgmdm 0:8fd0531ae0be 457 char NRF2401P::setTxAddress( char *address )
epgmdm 0:8fd0531ae0be 458 {
epgmdm 2:ca0a3c0bba70 459 memcpy (txAdd,address, addressWidth);
nixonkj 8:3e027705ce23 460 writeReg(RX_ADDR_P0, address, addressWidth);
nixonkj 8:3e027705ce23 461 writeReg(TX_ADDR, address, addressWidth);
nixonkj 6:77ead8abdd1c 462 return 0; // must fix this
epgmdm 0:8fd0531ae0be 463 }
epgmdm 0:8fd0531ae0be 464
epgmdm 0:8fd0531ae0be 465 /**
epgmdm 0:8fd0531ae0be 466 * Sets the address, uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 467 */
epgmdm 0:8fd0531ae0be 468 char NRF2401P::setTxAddress( long long address )
epgmdm 0:8fd0531ae0be 469 {
epgmdm 0:8fd0531ae0be 470 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 471 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 472 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 473 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 474 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 475 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 476 return setTxAddress( buff );
epgmdm 0:8fd0531ae0be 477 }
epgmdm 0:8fd0531ae0be 478
epgmdm 0:8fd0531ae0be 479 /**
nixonkj 9:c21b80aaf250 480 * Sets the address, uses address width set (either 3,4 or 5)
epgmdm 2:ca0a3c0bba70 481 * Enables pipe for receiving;
epgmdm 0:8fd0531ae0be 482 */
epgmdm 0:8fd0531ae0be 483 char NRF2401P::setRxAddress( char *address, char pipe )
epgmdm 0:8fd0531ae0be 484 {
epgmdm 2:ca0a3c0bba70 485 if(debug) {
epgmdm 2:ca0a3c0bba70 486 log ("Set Rx Address");
epgmdm 2:ca0a3c0bba70 487 }
epgmdm 2:ca0a3c0bba70 488 if (pipe>5) return 0xff;
epgmdm 2:ca0a3c0bba70 489 if (pipe ==0) {
nixonkj 8:3e027705ce23 490 memcpy(pipe0Add,address, addressWidth);
epgmdm 2:ca0a3c0bba70 491 }
epgmdm 2:ca0a3c0bba70 492
epgmdm 0:8fd0531ae0be 493 char reg = 0x0A + pipe;
epgmdm 0:8fd0531ae0be 494 switch ( pipe ) {
epgmdm 0:8fd0531ae0be 495 case ( 0 ) :
epgmdm 0:8fd0531ae0be 496 case ( 1 ) : {
nixonkj 8:3e027705ce23 497 writeReg(reg, address, addressWidth); //Write to RX_ADDR_P0 or _P1
epgmdm 0:8fd0531ae0be 498 break;
epgmdm 0:8fd0531ae0be 499 }
epgmdm 0:8fd0531ae0be 500 case ( 2 ) :
epgmdm 0:8fd0531ae0be 501 case ( 3 ) :
epgmdm 0:8fd0531ae0be 502 case ( 4 ) :
epgmdm 0:8fd0531ae0be 503 case ( 5 ) : {
nixonkj 8:3e027705ce23 504 writeReg(reg, address, 1); //Write to RX_ADDR_P2 ... _P5
epgmdm 0:8fd0531ae0be 505 break;
epgmdm 0:8fd0531ae0be 506 }
epgmdm 0:8fd0531ae0be 507
epgmdm 0:8fd0531ae0be 508 }
nixonkj 8:3e027705ce23 509 readReg(EN_RXADDR, &reg);
epgmdm 2:ca0a3c0bba70 510 reg |= (1<<pipe);
nixonkj 8:3e027705ce23 511 writeReg(EN_RXADDR, reg); //Enable the pipe
nixonkj 6:77ead8abdd1c 512 return 0; // Must fix this
epgmdm 0:8fd0531ae0be 513 }
epgmdm 0:8fd0531ae0be 514
epgmdm 0:8fd0531ae0be 515 /**
epgmdm 0:8fd0531ae0be 516 * Sets the address of pipe (<=5), uses addess width set (either 3,4 or 5)
epgmdm 0:8fd0531ae0be 517 */
epgmdm 0:8fd0531ae0be 518 char NRF2401P::setRxAddress( long long address, char pipe )
epgmdm 0:8fd0531ae0be 519 {
epgmdm 0:8fd0531ae0be 520 char buff[ 5 ];
epgmdm 0:8fd0531ae0be 521 buff[ 0 ] = address & 0xff;
epgmdm 0:8fd0531ae0be 522 buff[ 1 ] = ( address >> 8 ) & 0xFF;
epgmdm 0:8fd0531ae0be 523 buff[ 2 ] = ( address >> 16 ) & 0xFF;
epgmdm 0:8fd0531ae0be 524 buff[ 3 ] = ( address >> 24 ) & 0xFF;
epgmdm 0:8fd0531ae0be 525 buff[ 4 ] = ( address >> 32 ) & 0xFF;
epgmdm 0:8fd0531ae0be 526 return setRxAddress( buff, pipe );
epgmdm 0:8fd0531ae0be 527 }
nixonkj 6:77ead8abdd1c 528
epgmdm 1:ff53b1ac3bad 529 /**
epgmdm 1:ff53b1ac3bad 530 *checks the status flag
epgmdm 1:ff53b1ac3bad 531 */
epgmdm 1:ff53b1ac3bad 532 char NRF2401P::checkStatus()
epgmdm 1:ff53b1ac3bad 533 {
nixonkj 8:3e027705ce23 534 readReg(STATUS, &status);
epgmdm 1:ff53b1ac3bad 535 return status;
epgmdm 1:ff53b1ac3bad 536 }
nixonkj 6:77ead8abdd1c 537
epgmdm 1:ff53b1ac3bad 538 /**
epgmdm 1:ff53b1ac3bad 539 * checks if Ack data available.
epgmdm 1:ff53b1ac3bad 540 */
epgmdm 1:ff53b1ac3bad 541 bool NRF2401P::isAckData()
epgmdm 1:ff53b1ac3bad 542 {
epgmdm 1:ff53b1ac3bad 543 char fifo;
nixonkj 8:3e027705ce23 544 readReg(FIFO_STATUS, &fifo);
epgmdm 1:ff53b1ac3bad 545 bool isData = !(fifo&0x01);
epgmdm 1:ff53b1ac3bad 546 return isData;
epgmdm 1:ff53b1ac3bad 547 }
epgmdm 0:8fd0531ae0be 548
epgmdm 1:ff53b1ac3bad 549 /**
epgmdm 1:ff53b1ac3bad 550 * checks if RX data available.
epgmdm 1:ff53b1ac3bad 551 */
epgmdm 0:8fd0531ae0be 552 bool NRF2401P::isRxData()
epgmdm 0:8fd0531ae0be 553 {
epgmdm 1:ff53b1ac3bad 554 checkStatus();
epgmdm 0:8fd0531ae0be 555 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 556 return isData;
epgmdm 0:8fd0531ae0be 557 }
nixonkj 6:77ead8abdd1c 558
epgmdm 0:8fd0531ae0be 559 /**
epgmdm 0:8fd0531ae0be 560 * returns the width of the dynamic payload
epgmdm 0:8fd0531ae0be 561 */
epgmdm 0:8fd0531ae0be 562 char NRF2401P::getRxWidth()
epgmdm 0:8fd0531ae0be 563 {
epgmdm 0:8fd0531ae0be 564 char width;
epgmdm 0:8fd0531ae0be 565 if (dynamic) {
epgmdm 0:8fd0531ae0be 566 csn = 0;
epgmdm 0:8fd0531ae0be 567 status = spi->write( 0x60 );
epgmdm 0:8fd0531ae0be 568 width = spi->write(0x00);
epgmdm 0:8fd0531ae0be 569 csn = 1;
epgmdm 0:8fd0531ae0be 570
epgmdm 0:8fd0531ae0be 571 if (width>32) {
epgmdm 0:8fd0531ae0be 572 flushRx();
epgmdm 0:8fd0531ae0be 573 width=0;
epgmdm 0:8fd0531ae0be 574 }
epgmdm 0:8fd0531ae0be 575 } else {
nixonkj 8:3e027705ce23 576 readReg(RX_PW_P1, &width); // width of p1
epgmdm 0:8fd0531ae0be 577 }
epgmdm 1:ff53b1ac3bad 578 // width=18;
epgmdm 0:8fd0531ae0be 579 return width;
epgmdm 0:8fd0531ae0be 580 }
nixonkj 6:77ead8abdd1c 581
epgmdm 0:8fd0531ae0be 582 /**
epgmdm 0:8fd0531ae0be 583 * return message in buffer, mem for buffer must have been allocated.
epgmdm 0:8fd0531ae0be 584 * Return value is number of bytes of buffer
epgmdm 0:8fd0531ae0be 585 */
epgmdm 0:8fd0531ae0be 586 char NRF2401P::getRxData(char * buffer)
epgmdm 0:8fd0531ae0be 587 {
epgmdm 0:8fd0531ae0be 588 char address = 0x61;
epgmdm 0:8fd0531ae0be 589 char width;
epgmdm 0:8fd0531ae0be 590 width = getRxWidth();
epgmdm 0:8fd0531ae0be 591 bool isData = (status>>6)&0x01;
epgmdm 0:8fd0531ae0be 592 if (isData) {
epgmdm 0:8fd0531ae0be 593 csn = 0;
epgmdm 0:8fd0531ae0be 594 int i;
epgmdm 0:8fd0531ae0be 595 // set up for reading
epgmdm 0:8fd0531ae0be 596 status = spi->write( address );
epgmdm 0:8fd0531ae0be 597 for ( i = 0; i <= width; i++ ) {
epgmdm 0:8fd0531ae0be 598 buffer[i]=spi->write(0x00 );
epgmdm 0:8fd0531ae0be 599 }
epgmdm 0:8fd0531ae0be 600 csn = 1;
nixonkj 6:77ead8abdd1c 601 if (debug) {
nixonkj 6:77ead8abdd1c 602 sprintf(logMsg, "Receive data %d bytes", width );
nixonkj 6:77ead8abdd1c 603 log(logMsg);
nixonkj 6:77ead8abdd1c 604 }
epgmdm 0:8fd0531ae0be 605 clearStatus();
epgmdm 0:8fd0531ae0be 606 return width;
epgmdm 0:8fd0531ae0be 607 } else {
nixonkj 6:77ead8abdd1c 608 if (debug) {
nixonkj 6:77ead8abdd1c 609 sprintf(logMsg, "Receive NO data %d bytes", width );
nixonkj 6:77ead8abdd1c 610 log(logMsg);
nixonkj 6:77ead8abdd1c 611 }
epgmdm 0:8fd0531ae0be 612 clearStatus();
epgmdm 0:8fd0531ae0be 613 return 0;
epgmdm 0:8fd0531ae0be 614 }
epgmdm 0:8fd0531ae0be 615 }
epgmdm 0:8fd0531ae0be 616
epgmdm 0:8fd0531ae0be 617 /**
epgmdm 0:8fd0531ae0be 618 * Sets all the receive pipes to dynamic payload length
epgmdm 0:8fd0531ae0be 619 */
epgmdm 2:ca0a3c0bba70 620 void NRF2401P::setDynamicPayload()
epgmdm 0:8fd0531ae0be 621 {
epgmdm 0:8fd0531ae0be 622 dynamic = true;
nixonkj 8:3e027705ce23 623 writeReg(FEATURE, 0x07); // Enable Dyn payload, Payload with Ack and w_tx_noack command
nixonkj 8:3e027705ce23 624 writeReg(EN_AA, 0x3f); // EN_AA regi for P1 and P0
nixonkj 9:c21b80aaf250 625 writeReg(DYNPD, 0x3F); // KJN - should be 0x3F for all pipes
epgmdm 0:8fd0531ae0be 626 }
epgmdm 2:ca0a3c0bba70 627
epgmdm 0:8fd0531ae0be 628 /**
epgmdm 0:8fd0531ae0be 629 * Sets PWR_UP = 1;
nixonkj 6:77ead8abdd1c 630 * return 0 on success
epgmdm 0:8fd0531ae0be 631 */
nixonkj 6:77ead8abdd1c 632 char NRF2401P::setPwrUp()
epgmdm 0:8fd0531ae0be 633 {
epgmdm 0:8fd0531ae0be 634 char data;
epgmdm 0:8fd0531ae0be 635 char bit;
epgmdm 0:8fd0531ae0be 636 ce=1;
nixonkj 8:3e027705ce23 637 readReg(CONFIG, &data);
epgmdm 2:ca0a3c0bba70 638 if ((data>>1) &0x01) {
epgmdm 2:ca0a3c0bba70 639 return true; // Already powered up
epgmdm 2:ca0a3c0bba70 640 };
nixonkj 8:3e027705ce23 641 data |= (0x02);
nixonkj 8:3e027705ce23 642 writeReg(CONFIG, data);
epgmdm 0:8fd0531ae0be 643 // check
nixonkj 8:3e027705ce23 644 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 645 bit = ( data >> 1 ) & 1;
epgmdm 2:ca0a3c0bba70 646
epgmdm 0:8fd0531ae0be 647 wait(0.005); // wait 5ms
epgmdm 2:ca0a3c0bba70 648 if(debug) {
epgmdm 2:ca0a3c0bba70 649 sprintf(logMsg, "Set PWR_UP to %x", bit);
epgmdm 2:ca0a3c0bba70 650 log(logMsg);
epgmdm 2:ca0a3c0bba70 651 }
nixonkj 6:77ead8abdd1c 652 if (bit == 1) {
nixonkj 6:77ead8abdd1c 653 return 0;
nixonkj 6:77ead8abdd1c 654 } else {
nixonkj 6:77ead8abdd1c 655 return 1;
nixonkj 6:77ead8abdd1c 656 }
nixonkj 6:77ead8abdd1c 657 }
epgmdm 2:ca0a3c0bba70 658
epgmdm 0:8fd0531ae0be 659 /**
epgmdm 0:8fd0531ae0be 660 * Sets PRIM_RX = 0;
epgmdm 0:8fd0531ae0be 661 */
nixonkj 6:77ead8abdd1c 662 char NRF2401P::setRxMode()
epgmdm 0:8fd0531ae0be 663 {
epgmdm 0:8fd0531ae0be 664 char data;
epgmdm 0:8fd0531ae0be 665 char bit;
epgmdm 0:8fd0531ae0be 666 ce=1;
nixonkj 8:3e027705ce23 667 readReg(CONFIG, &data);
nixonkj 8:3e027705ce23 668 data |= (0x01);
epgmdm 2:ca0a3c0bba70 669
nixonkj 8:3e027705ce23 670 writeReg(CONFIG, data);
epgmdm 3:afe8d307b5c3 671 if (pipe0Add[0]|pipe0Add[1]|pipe0Add[2]|pipe0Add[3]|pipe0Add[4] >0) {
epgmdm 3:afe8d307b5c3 672 setRxAddress(pipe0Add,0);
epgmdm 2:ca0a3c0bba70 673 }
epgmdm 0:8fd0531ae0be 674 // check
nixonkj 8:3e027705ce23 675 readReg(CONFIG, &data);
epgmdm 0:8fd0531ae0be 676 bit = ( data >> 0 ) & 1;
epgmdm 2:ca0a3c0bba70 677
epgmdm 2:ca0a3c0bba70 678 wait (0.001);
epgmdm 0:8fd0531ae0be 679 flushRx();
epgmdm 2:ca0a3c0bba70 680 flushTx();
epgmdm 2:ca0a3c0bba70 681 if (debug) {
epgmdm 2:ca0a3c0bba70 682 sprintf(logMsg, " set PRIM_RX to %x", bit);
epgmdm 2:ca0a3c0bba70 683 log(logMsg);
epgmdm 2:ca0a3c0bba70 684 }
nixonkj 6:77ead8abdd1c 685 if ( bit == 1 ) {
nixonkj 6:77ead8abdd1c 686 return 0;
nixonkj 6:77ead8abdd1c 687 } else {
nixonkj 6:77ead8abdd1c 688 return 1;
nixonkj 6:77ead8abdd1c 689 }
epgmdm 0:8fd0531ae0be 690 }
nixonkj 6:77ead8abdd1c 691
epgmdm 0:8fd0531ae0be 692 /**
epgmdm 0:8fd0531ae0be 693 * Prints status string
epgmdm 0:8fd0531ae0be 694 */
epgmdm 0:8fd0531ae0be 695 char * NRF2401P::statusString()
epgmdm 0:8fd0531ae0be 696 {
epgmdm 0:8fd0531ae0be 697 char *msg;
epgmdm 0:8fd0531ae0be 698 msg = statusS;
epgmdm 0:8fd0531ae0be 699 if (((status>>1) & 0x07)==0x07) {
epgmdm 0:8fd0531ae0be 700 sprintf(msg,"RX empty");
epgmdm 0:8fd0531ae0be 701 } else {
epgmdm 0:8fd0531ae0be 702 sprintf(msg,"pipe %02x",(status>>1) & 0x07);
epgmdm 0:8fd0531ae0be 703 }
epgmdm 0:8fd0531ae0be 704
epgmdm 0:8fd0531ae0be 705 if ((status>>6)&0x01) strcat(msg," RX_DR,");
epgmdm 0:8fd0531ae0be 706 if ((status>>5)&0x01) strcat(msg," TX_DS,");
epgmdm 0:8fd0531ae0be 707 if ((status>>4)&0x01) strcat(msg," MAX_RT,");
epgmdm 0:8fd0531ae0be 708 if ((status>>0)&0x01) strcat(msg," TX_FLL,");
epgmdm 0:8fd0531ae0be 709
epgmdm 0:8fd0531ae0be 710 return msg;
nixonkj 9:c21b80aaf250 711 }
nixonkj 9:c21b80aaf250 712
nixonkj 11:07f76589f00a 713 void NRF2401P::printReg(char* name, char address, bool newline)
nixonkj 9:c21b80aaf250 714 {
nixonkj 9:c21b80aaf250 715 char data;
nixonkj 11:07f76589f00a 716 readReg(address, &data);
nixonkj 11:07f76589f00a 717 printf("%s = 0x%02x", name, data);
nixonkj 11:07f76589f00a 718 if (newline) {
nixonkj 11:07f76589f00a 719 printf("\r\n");
nixonkj 11:07f76589f00a 720 }
nixonkj 11:07f76589f00a 721 }
nixonkj 11:07f76589f00a 722
nixonkj 11:07f76589f00a 723 void NRF2401P::printReg(char* name, char address, char width, bool newline)
nixonkj 11:07f76589f00a 724 {
nixonkj 11:07f76589f00a 725 char data[width];
nixonkj 11:07f76589f00a 726 readReg(address, data, width);
nixonkj 11:07f76589f00a 727 printf("%s = 0x", name);
nixonkj 11:07f76589f00a 728 for (int i=width-1; i>=0; i--) {
nixonkj 11:07f76589f00a 729 printf("%02x", data[i]);
nixonkj 11:07f76589f00a 730 }
nixonkj 11:07f76589f00a 731 if (newline) {
nixonkj 11:07f76589f00a 732 printf("\r\n");
nixonkj 11:07f76589f00a 733 }
nixonkj 11:07f76589f00a 734 }
nixonkj 11:07f76589f00a 735
nixonkj 11:07f76589f00a 736 void NRF2401P::printDetails() {
nixonkj 9:c21b80aaf250 737 char status = checkStatus();
nixonkj 11:07f76589f00a 738 printf("STATUS = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n", status,
nixonkj 9:c21b80aaf250 739 (status & (1<<MASK_RX_DR))?1:0,
nixonkj 9:c21b80aaf250 740 (status & (1<<MASK_TX_DS))?1:0,
nixonkj 9:c21b80aaf250 741 (status & (1<<MASK_MAX_RT))?1:0,
nixonkj 9:c21b80aaf250 742 (status >> RX_P_NO) & 7,
nixonkj 9:c21b80aaf250 743 (status & (1<<TX_FULL))?1:0 );
nixonkj 9:c21b80aaf250 744
nixonkj 11:07f76589f00a 745 printReg("RX_ADDR_P0", RX_ADDR_P0, addressWidth);
nixonkj 11:07f76589f00a 746 printReg("RX_ADDR_P1", RX_ADDR_P1, addressWidth);
nixonkj 11:07f76589f00a 747 printReg("RX_ADDR_P2", RX_ADDR_P2, addressWidth);
nixonkj 11:07f76589f00a 748 printReg("RX_ADDR_P3", RX_ADDR_P3, addressWidth);
nixonkj 11:07f76589f00a 749 printReg("RX_ADDR_P4", RX_ADDR_P4, addressWidth);
nixonkj 11:07f76589f00a 750 printReg("RX_ADDR_P5", RX_ADDR_P5, addressWidth);
nixonkj 11:07f76589f00a 751 printReg("TX_ADDR", TX_ADDR, addressWidth);
nixonkj 10:8a217441c38e 752
nixonkj 11:07f76589f00a 753 printReg("RX_PW_P0", RX_PW_P0, false); // false for no newline, save some space
nixonkj 11:07f76589f00a 754 printReg(" RX_PW_P1", RX_PW_P1, false);
nixonkj 11:07f76589f00a 755 printReg(" RX_PW_P2", RX_PW_P2);
nixonkj 11:07f76589f00a 756 printReg("RX_PW_P3", RX_PW_P3, false);
nixonkj 11:07f76589f00a 757 printReg(" RX_PW_P4", RX_PW_P4, false);
nixonkj 11:07f76589f00a 758 printReg(" RX_PW_P5", RX_PW_P5);
nixonkj 11:07f76589f00a 759
nixonkj 11:07f76589f00a 760 printReg("EN_AA", EN_AA);
nixonkj 11:07f76589f00a 761 printReg("EN_RXADDR", EN_RXADDR);
nixonkj 11:07f76589f00a 762 printReg("RF_CH", RF_CH);
nixonkj 11:07f76589f00a 763 printReg("RF_SETUP", RF_SETUP);
nixonkj 12:ea1345de6478 764 printReg("CONFIG", CONFIG);
nixonkj 11:07f76589f00a 765 printReg("DYNPD", DYNPD);
nixonkj 11:07f76589f00a 766 printReg("FEATURE", FEATURE);
epgmdm 0:8fd0531ae0be 767 }