Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Impedance Fast Circuitry Software

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

DMA_sampling/dma.cpp@87:80c9169acb85, 2018-06-27 (annotated)

Committer:
baxterja
Date:
Wed Jun 27 19:23:32 2018 +0000
Revision:
87:80c9169acb85
Parent:
77:1ee17a9e9f8b 
Changed frequencies for different probe number.  I also ordered frequencies from smallest to largest (I don't know if this is a good idea or not)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 45:d591d138cdeb 1 /**
timmey9 45:d591d138cdeb 2 * Setup triggering for DMA2 and PortC
timmey9 34:44cc9b76a507 3 */
timmey9 34:44cc9b76a507 4 #include "dma.h"
timmey9 34:44cc9b76a507 5
bmazzeo 65:f022535bed5d 6 #define TOTAL_SAMPLES 64
bmazzeo 65:f022535bed5d 7 #define SAMPLE_BUFFER_LENGTH 128
timmey9 45:d591d138cdeb 8 int len = TOTAL_SAMPLES;
bmazzeo 63:7903a33e2fd4 9 uint16_t sample_array0[SAMPLE_BUFFER_LENGTH];
bmazzeo 63:7903a33e2fd4 10 uint16_t sample_array1[SAMPLE_BUFFER_LENGTH];
timmey9 51:43143a3fc2d7 11
bmazzeo 54:1697dc574b96 12 uint16_t static_input_array0[TOTAL_SAMPLES];
bmazzeo 54:1697dc574b96 13 uint16_t static_input_array1[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 14
bmazzeo 55:2526b3317bc8 15 uint16_t static_output_array0[TOTAL_SAMPLES];
bmazzeo 63:7903a33e2fd4 16 uint16_t output_array0[SAMPLE_BUFFER_LENGTH];
baxterja 70:8cd7a8a2c153 17 uint32_t ADC0_LOCATION[2];
timmey9 45:d591d138cdeb 18
bmazzeo 57:7b8c49e1c1f6 19 uint16_t sampling_status;
bmazzeo 57:7b8c49e1c1f6 20 uint16_t sampling_status_done = 1;
bmazzeo 57:7b8c49e1c1f6 21
bmazzeo 63:7903a33e2fd4 22 uint16_t intermediate_status;
bmazzeo 63:7903a33e2fd4 23 uint16_t intermediate_status_done = 1;
bmazzeo 63:7903a33e2fd4 24
baxterja 74:ebc9f09fda11 25 void dma_init2()
timmey9 34:44cc9b76a507 26 {
baxterja 70:8cd7a8a2c153 27 ADC0_LOCATION[0] = 0x0C;
baxterja 70:8cd7a8a2c153 28 ADC0_LOCATION[1] = 0x0D;
bmazzeo 54:1697dc574b96 29 // Enable clock for DMAMUX and DMA - all the peripherals need clocks to function
baxterja 74:ebc9f09fda11 30 SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
baxterja 74:ebc9f09fda11 31 SIM->SCGC7 |= SIM_SCGC7_DMA_MASK;
bmazzeo 54:1697dc574b96 32
bmazzeo 54:1697dc574b96 33
timmey9 45:d591d138cdeb 34 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
baxterja 74:ebc9f09fda11 35 DMAMUX->CHCFG[0] = 0;
baxterja 74:ebc9f09fda11 36 DMAMUX->CHCFG[1] = 0;
baxterja 74:ebc9f09fda11 37 DMAMUX->CHCFG[2] = 0;
baxterja 74:ebc9f09fda11 38 DMAMUX->CHCFG[3] = 0;
baxterja 74:ebc9f09fda11 39 DMAMUX->CHCFG[4] = 0;
baxterja 74:ebc9f09fda11 40 DMAMUX->CHCFG[5] = 0;
baxterja 74:ebc9f09fda11 41 DMAMUX->CHCFG[6] = 0;
baxterja 74:ebc9f09fda11 42 DMAMUX->CHCFG[7] = 0;
baxterja 74:ebc9f09fda11 43 DMAMUX->CHCFG[8] = 0;
baxterja 74:ebc9f09fda11 44 DMAMUX->CHCFG[9] = 0;
baxterja 74:ebc9f09fda11 45 DMAMUX->CHCFG[10] = 0;
bmazzeo 54:1697dc574b96 46
bmazzeo 63:7903a33e2fd4 47
bmazzeo 54:1697dc574b96 48 // Enable request signal for channel 0, 1
baxterja 74:ebc9f09fda11 49 DMA0->ERQ = 0;
baxterja 74:ebc9f09fda11 50 DMA0->ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK;
timmey9 45:d591d138cdeb 51
timmey9 45:d591d138cdeb 52 // select round-robin arbitration priority
baxterja 74:ebc9f09fda11 53 DMA0->CR |= DMA_CR_ERCA_MASK;
timmey9 45:d591d138cdeb 54
bmazzeo 55:2526b3317bc8 55 // Disable minor loop
bmazzeo 60:873a6d60c5d5 56 //DMA_CR &= ~DMA_CR_EMLM_MASK;
baxterja 74:ebc9f09fda11 57 DMA0->CR |= DMA_CR_EMLM_MASK;
bmazzeo 56:7e08cbc3a4f1 58
baxterja 74:ebc9f09fda11 59 DMA0->TCD[0].CSR = 0;
baxterja 74:ebc9f09fda11 60 DMA0->TCD[1].CSR = 0;
baxterja 74:ebc9f09fda11 61 DMA0->TCD[2].CSR = 0;
baxterja 74:ebc9f09fda11 62 DMA0->TCD[3].CSR = 0;
baxterja 74:ebc9f09fda11 63 DMA0->TCD[4].CSR = 0;
baxterja 74:ebc9f09fda11 64 DMA0->TCD[5].CSR = 0;
baxterja 74:ebc9f09fda11 65 DMA0->TCD[6].CSR = 0;
baxterja 74:ebc9f09fda11 66 DMA0->TCD[7].CSR = 0;
baxterja 74:ebc9f09fda11 67 DMA0->TCD[8].CSR = 0;
baxterja 74:ebc9f09fda11 68 DMA0->TCD[9].CSR = 0;
baxterja 74:ebc9f09fda11 69 DMA0->TCD[10].CSR = 0;
bmazzeo 63:7903a33e2fd4 70
bmazzeo 63:7903a33e2fd4 71
bmazzeo 56:7e08cbc3a4f1 72 // DMA setup for ADC sampling
bmazzeo 54:1697dc574b96 73 // Set memory address for source and destination for DMA0 and DMA1
baxterja 74:ebc9f09fda11 74 DMA0->TCD[0].SADDR = (uint32_t) &ADC0->R[0];
baxterja 74:ebc9f09fda11 75 DMA0->TCD[0].DADDR = (uint32_t) sample_array0;
baxterja 74:ebc9f09fda11 76 DMA0->TCD[1].SADDR = (uint32_t) &ADC1->R[0];
baxterja 74:ebc9f09fda11 77 DMA0->TCD[1].DADDR = (uint32_t) sample_array1;
timmey9 36:07d8a3143967 78
timmey9 34:44cc9b76a507 79 // Set an offset for source and destination address
baxterja 74:ebc9f09fda11 80 DMA0->TCD[0].SOFF = 0x00; // Source address offset of 0 bytes per transaction
baxterja 74:ebc9f09fda11 81 DMA0->TCD[0].DOFF = 0x02; // Destination address offset of 2 bytes per transaction
baxterja 74:ebc9f09fda11 82 DMA0->TCD[1].SOFF = 0x00; // Source address offset of 0 bytes per transaction
baxterja 74:ebc9f09fda11 83 DMA0->TCD[1].DOFF = 0x02; // Destination address offset of 2 bytes per transaction
timmey9 34:44cc9b76a507 84
timmey9 34:44cc9b76a507 85 // Set source and destination data transfer size
baxterja 74:ebc9f09fda11 86 DMA0->TCD[0].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
baxterja 74:ebc9f09fda11 87 DMA0->TCD[1].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 88
timmey9 34:44cc9b76a507 89 // Number of bytes to be transfered in each service request of the channel
baxterja 74:ebc9f09fda11 90 DMA0->TCD[0].NBYTES_MLNO = 0x02;
baxterja 74:ebc9f09fda11 91 DMA0->TCD[1].NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 92
bmazzeo 63:7903a33e2fd4 93
baxterja 74:ebc9f09fda11 94 DMA0->TCD[0].SLAST = 0; // Source address adjustment
baxterja 74:ebc9f09fda11 95 DMA0->TCD[0].DLAST_SGA = -len*2*2; // Destination address adjustment
baxterja 74:ebc9f09fda11 96 DMA0->TCD[1].SLAST = 0; // Source address adjustment
baxterja 74:ebc9f09fda11 97 DMA0->TCD[1].DLAST_SGA = -len*2*2; // Destination address adjustment
baxterja 74:ebc9f09fda11 98 // DMA_TCD[2].SLAST = 0; // Source address adjustment
baxterja 74:ebc9f09fda11 99 // DMA_TCD[2].DLAST_SGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 100
bmazzeo 62:51f722ef9cb1 101 //DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
bmazzeo 61:a56cca07d4a6 102 //DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
bmazzeo 54:1697dc574b96 103 /* Source number Source module
bmazzeo 54:1697dc574b96 104 40 ADC0
bmazzeo 54:1697dc574b96 105 41 ADC1
bmazzeo 54:1697dc574b96 106 */
bmazzeo 54:1697dc574b96 107
baxterja 74:ebc9f09fda11 108 DMA0->TCD[0].BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(1) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
baxterja 74:ebc9f09fda11 109 DMA0->TCD[0].CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(1) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
baxterja 74:ebc9f09fda11 110 DMA0->TCD[0].CSR = DMA_CSR_MAJORLINKCH(1) | DMA_CSR_MAJORELINK_MASK;
baxterja 77:1ee17a9e9f8b 111 DMA0->TCD[1].BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(8) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
baxterja 77:1ee17a9e9f8b 112 DMA0->TCD[1].CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(8) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
baxterja 77:1ee17a9e9f8b 113 DMA0->TCD[1].CSR = DMA_CSR_MAJORLINKCH(8) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 114
bmazzeo 61:a56cca07d4a6 115 // Setup control and status register
bmazzeo 54:1697dc574b96 116
bmazzeo 56:7e08cbc3a4f1 117 //
bmazzeo 56:7e08cbc3a4f1 118 // Now set up DAC DMA outputs from the output array
bmazzeo 56:7e08cbc3a4f1 119 //
baxterja 74:ebc9f09fda11 120 DMA0->ERQ |= DMA_ERQ_ERQ2_MASK;
baxterja 74:ebc9f09fda11 121 //DMA_TCD[1].CSR |= DMA_CSR_MAJORLINKCH(2) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 59:1cfd9d9fb99d 122
bmazzeo 54:1697dc574b96 123 // Set memory address for source and destination for DMA0 and DMA1
baxterja 74:ebc9f09fda11 124 DMA0->TCD[2].SADDR = (uint32_t) output_array0;
baxterja 74:ebc9f09fda11 125 DMA0->TCD[2].DADDR = (uint32_t) &DAC0->DAT[0].DATL;
bmazzeo 54:1697dc574b96 126
bmazzeo 54:1697dc574b96 127 // Set an offset for source and destination address
baxterja 74:ebc9f09fda11 128 DMA0->TCD[2].SOFF = 0x02; // Source address offset of 1 per transaction
baxterja 74:ebc9f09fda11 129 DMA0->TCD[2].DOFF = 0x00; // Destination address offset of 0 bytes per transaction
bmazzeo 54:1697dc574b96 130
bmazzeo 54:1697dc574b96 131 // Set source and destination data transfer size
baxterja 74:ebc9f09fda11 132 DMA0->TCD[2].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 54:1697dc574b96 133
bmazzeo 54:1697dc574b96 134 // Number of bytes to be transfered in each service request of the channel
baxterja 74:ebc9f09fda11 135 DMA0->TCD[2].NBYTES_MLNO = 0x02;
baxterja 74:ebc9f09fda11 136 //DMA_TCD[2].NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x00) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
baxterja 74:ebc9f09fda11 137 //DMA_TCD[1].NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x02) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
bmazzeo 63:7903a33e2fd4 138
bmazzeo 54:1697dc574b96 139
bmazzeo 56:7e08cbc3a4f1 140 // Major iteration count
baxterja 74:ebc9f09fda11 141 //DMA_TCD[2].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
baxterja 74:ebc9f09fda11 142 //DMA_TCD[2].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 54:1697dc574b96 143
bmazzeo 54:1697dc574b96 144 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 54:1697dc574b96 145 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 54:1697dc574b96 146
baxterja 74:ebc9f09fda11 147 DMA0->TCD[2].SLAST = -len*2*2; // Source address adjustment
baxterja 74:ebc9f09fda11 148 DMA0->TCD[2].DLAST_SGA = 0; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 149
baxterja 74:ebc9f09fda11 150 DMAMUX->CHCFG[2] |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // ADC0 Source Jared's Note I think that this is actually the pdb timer
bmazzeo 62:51f722ef9cb1 151
baxterja 74:ebc9f09fda11 152 DMA0->TCD[2].BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(0) | DMA_BITER_ELINKYES_BITER(len*2);
baxterja 74:ebc9f09fda11 153 DMA0->TCD[2].CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(0) | DMA_CITER_ELINKYES_CITER(len*2);
baxterja 74:ebc9f09fda11 154 DMA0->TCD[2].CSR |= DMA_CSR_MAJORLINKCH(0) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 155
bmazzeo 56:7e08cbc3a4f1 156 //
bmazzeo 56:7e08cbc3a4f1 157 // Now set up static dataset linking once the ADC samples are recorded
bmazzeo 56:7e08cbc3a4f1 158 //
bmazzeo 56:7e08cbc3a4f1 159 // DMA Channels 4 and 5 now will be enabled
baxterja 74:ebc9f09fda11 160 DMA0->ERQ |= DMA_ERQ_ERQ4_MASK | DMA_ERQ_ERQ5_MASK;
bmazzeo 54:1697dc574b96 161
bmazzeo 56:7e08cbc3a4f1 162 // Set memory address for source and destination for DMA4 and DMA5
baxterja 74:ebc9f09fda11 163 DMA0->TCD[4].SADDR = (uint32_t) &sample_array0;
baxterja 74:ebc9f09fda11 164 DMA0->TCD[4].DADDR = (uint32_t) &static_input_array0;
baxterja 74:ebc9f09fda11 165 DMA0->TCD[5].SADDR = (uint32_t) &sample_array1;
baxterja 74:ebc9f09fda11 166 DMA0->TCD[5].DADDR = (uint32_t) &static_input_array1;
bmazzeo 56:7e08cbc3a4f1 167
bmazzeo 56:7e08cbc3a4f1 168 // Set an offset for source and destination address
baxterja 74:ebc9f09fda11 169 DMA0->TCD[4].SOFF = 0x02; // Source address offset of 2 bits per transaction
baxterja 74:ebc9f09fda11 170 DMA0->TCD[4].DOFF = 0x02; // Destination address offset of 1 bit per transaction
baxterja 74:ebc9f09fda11 171 DMA0->TCD[5].SOFF = 0x02; // Source address offset of 2 bits per transaction
baxterja 74:ebc9f09fda11 172 DMA0->TCD[5].DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 173
bmazzeo 56:7e08cbc3a4f1 174 // Set source and destination data transfer size
baxterja 74:ebc9f09fda11 175 DMA0->TCD[4].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
baxterja 74:ebc9f09fda11 176 DMA0->TCD[5].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 177
baxterja 74:ebc9f09fda11 178 DMA0->TCD[4].NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
baxterja 74:ebc9f09fda11 179 DMA0->TCD[5].NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 56:7e08cbc3a4f1 180
baxterja 74:ebc9f09fda11 181 DMA0->TCD[4].SLAST = -len*2*2; // Source address adjustment
baxterja 74:ebc9f09fda11 182 DMA0->TCD[4].DLAST_SGA = -len*2; // Destination address adjustment
baxterja 74:ebc9f09fda11 183 //DMA_TCD[4].DLAST_SGA = 0; // Destination address adjustment
baxterja 74:ebc9f09fda11 184 DMA0->TCD[5].SLAST = -len*2*2; // Source address adjustment
baxterja 74:ebc9f09fda11 185 DMA0->TCD[5].DLAST_SGA = -len*2; // Destination address adjustment
baxterja 74:ebc9f09fda11 186 //DMA_TCD[5].DLAST_SGA = 0; // Destination address adjustment
bmazzeo 54:1697dc574b96 187
baxterja 74:ebc9f09fda11 188 //DMA_TCD[4].CSR |= DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
baxterja 74:ebc9f09fda11 189 DMA0->TCD[4].BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(5) | DMA_BITER_ELINKYES_BITER(2);
baxterja 74:ebc9f09fda11 190 DMA0->TCD[4].CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(5) | DMA_CITER_ELINKYES_CITER(2);
baxterja 74:ebc9f09fda11 191 DMA0->TCD[4].CSR = DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
baxterja 74:ebc9f09fda11 192 DMA0->TCD[5].BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(6) | DMA_BITER_ELINKYES_BITER(2);
baxterja 74:ebc9f09fda11 193 DMA0->TCD[5].CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(6) | DMA_CITER_ELINKYES_CITER(2);
baxterja 74:ebc9f09fda11 194 DMA0->TCD[5].CSR = DMA_CSR_MAJORLINKCH(6) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 56:7e08cbc3a4f1 195
bmazzeo 56:7e08cbc3a4f1 196 //
bmazzeo 56:7e08cbc3a4f1 197 // Now set up linking from static DAC to memory for output through DMA
bmazzeo 56:7e08cbc3a4f1 198 //
bmazzeo 56:7e08cbc3a4f1 199 // DMA Channel 6 will be enabled
bmazzeo 56:7e08cbc3a4f1 200
baxterja 74:ebc9f09fda11 201 DMA0->ERQ |= DMA_ERQ_ERQ6_MASK;
bmazzeo 55:2526b3317bc8 202
bmazzeo 56:7e08cbc3a4f1 203 // Set memory address for source and destination for DMA6
baxterja 74:ebc9f09fda11 204 DMA0->TCD[6].SADDR = (uint32_t) static_output_array0;
baxterja 74:ebc9f09fda11 205 DMA0->TCD[6].DADDR = (uint32_t) output_array0;
bmazzeo 56:7e08cbc3a4f1 206
bmazzeo 56:7e08cbc3a4f1 207 // Set an offset for source and destination address
baxterja 74:ebc9f09fda11 208 DMA0->TCD[6].SOFF = 0x02; // Source address offset of 2 bits per transaction
baxterja 74:ebc9f09fda11 209 DMA0->TCD[6].DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 210
bmazzeo 56:7e08cbc3a4f1 211 // Set source and destination data transfer size
baxterja 74:ebc9f09fda11 212 DMA0->TCD[6].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
baxterja 74:ebc9f09fda11 213 DMA0->TCD[6].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 214
bmazzeo 56:7e08cbc3a4f1 215
baxterja 74:ebc9f09fda11 216 DMA0->TCD[6].NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 56:7e08cbc3a4f1 217
baxterja 74:ebc9f09fda11 218 DMA0->TCD[6].SLAST = -len*2; // Source address adjustment
baxterja 74:ebc9f09fda11 219 //DMA_TCD[6].SLAST = 0; // Source address adjustment
baxterja 74:ebc9f09fda11 220 DMA0->TCD[6].DLAST_SGA = -len*2*2; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 221
baxterja 74:ebc9f09fda11 222 DMA0->TCD[6].BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(9) | DMA_BITER_ELINKYES_BITER(2);
baxterja 74:ebc9f09fda11 223 DMA0->TCD[6].CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(9) | DMA_CITER_ELINKYES_CITER(2);
bmazzeo 63:7903a33e2fd4 224
baxterja 74:ebc9f09fda11 225 DMA0->TCD[6].CSR |= DMA_CSR_MAJORLINKCH(9) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 226
bmazzeo 57:7b8c49e1c1f6 227 //
bmazzeo 63:7903a33e2fd4 228 // Provide control for intermediate loops
bmazzeo 57:7b8c49e1c1f6 229 //
bmazzeo 57:7b8c49e1c1f6 230
bmazzeo 57:7b8c49e1c1f6 231 // DMA Channel 8
baxterja 74:ebc9f09fda11 232 DMA0->ERQ |= DMA_ERQ_ERQ8_MASK;
bmazzeo 57:7b8c49e1c1f6 233
bmazzeo 57:7b8c49e1c1f6 234 // Set memory address for source and destiantion for DMA 8
baxterja 74:ebc9f09fda11 235 DMA0->TCD[8].SADDR = (uint32_t) &intermediate_status_done;
baxterja 74:ebc9f09fda11 236 DMA0->TCD[8].DADDR = (uint32_t) &intermediate_status;
bmazzeo 57:7b8c49e1c1f6 237
bmazzeo 57:7b8c49e1c1f6 238 // Set an offset for source and destination address
baxterja 74:ebc9f09fda11 239 DMA0->TCD[8].SOFF = 0x00; // Source address offset of 2 bits per transaction
baxterja 74:ebc9f09fda11 240 DMA0->TCD[8].DOFF = 0x00; // Destination address offset of 1 bit per transaction
bmazzeo 57:7b8c49e1c1f6 241
bmazzeo 57:7b8c49e1c1f6 242 // Set source and destination data transfer size
baxterja 74:ebc9f09fda11 243 DMA0->TCD[8].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
baxterja 74:ebc9f09fda11 244 DMA0->TCD[8].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 57:7b8c49e1c1f6 245
bmazzeo 57:7b8c49e1c1f6 246 // Number of bytes to be transfered in each service request of the channel
baxterja 74:ebc9f09fda11 247 DMA0->TCD[8].NBYTES_MLNO = 0x02;
bmazzeo 57:7b8c49e1c1f6 248
bmazzeo 57:7b8c49e1c1f6 249 // Current major iteration count
baxterja 74:ebc9f09fda11 250 DMA0->TCD[8].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
baxterja 74:ebc9f09fda11 251 DMA0->TCD[8].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 63:7903a33e2fd4 252
baxterja 74:ebc9f09fda11 253 DMA0->TCD[8].SLAST = 0; // Source address adjustment
baxterja 74:ebc9f09fda11 254 DMA0->TCD[8].DLAST_SGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 255
baxterja 74:ebc9f09fda11 256 DMA0->TCD[8].CSR |= DMA_CSR_MAJORLINKCH(4) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 57:7b8c49e1c1f6 257
bmazzeo 63:7903a33e2fd4 258 //
bmazzeo 63:7903a33e2fd4 259 // Provide status
bmazzeo 63:7903a33e2fd4 260 //
bmazzeo 63:7903a33e2fd4 261
bmazzeo 63:7903a33e2fd4 262 // DMA Channel 9
baxterja 74:ebc9f09fda11 263 DMA0->ERQ |= DMA_ERQ_ERQ9_MASK;
bmazzeo 63:7903a33e2fd4 264
bmazzeo 63:7903a33e2fd4 265 // Set memory address for source and destiantion for DMA 8
baxterja 74:ebc9f09fda11 266 DMA0->TCD[9].SADDR = (uint32_t) &sampling_status_done;
baxterja 74:ebc9f09fda11 267 DMA0->TCD[9].DADDR = (uint32_t) &sampling_status;
bmazzeo 57:7b8c49e1c1f6 268
bmazzeo 63:7903a33e2fd4 269 // Set an offset for source and destination address
baxterja 74:ebc9f09fda11 270 DMA0->TCD[9].SOFF = 0x00; // Source address offset of 2 bits per transaction
baxterja 74:ebc9f09fda11 271 DMA0->TCD[9].DOFF = 0x00; // Destination address offset of 1 bit per transaction
bmazzeo 63:7903a33e2fd4 272
bmazzeo 63:7903a33e2fd4 273 // Set source and destination data transfer size
baxterja 74:ebc9f09fda11 274 DMA0->TCD[9].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
baxterja 74:ebc9f09fda11 275 DMA0->TCD[9].ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 63:7903a33e2fd4 276
bmazzeo 63:7903a33e2fd4 277 // Number of bytes to be transfered in each service request of the channel
baxterja 74:ebc9f09fda11 278 DMA0->TCD[9].NBYTES_MLNO = 0x02;
bmazzeo 63:7903a33e2fd4 279
bmazzeo 63:7903a33e2fd4 280 // Current major iteration count
baxterja 74:ebc9f09fda11 281 DMA0->TCD[9].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
baxterja 74:ebc9f09fda11 282 DMA0->TCD[9].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 63:7903a33e2fd4 283
baxterja 74:ebc9f09fda11 284 DMA0->TCD[9].SLAST = 0; // Source address adjustment
baxterja 74:ebc9f09fda11 285 DMA0->TCD[9].DLAST_SGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 286
baxterja 72:0b554f5026b9 287
baxterja 72:0b554f5026b9 288
baxterja 72:0b554f5026b9 289
baxterja 72:0b554f5026b9 290
baxterja 70:8cd7a8a2c153 291 //JARED THIS IS WHERE YOU STARTED TO CHANGE THINGS
baxterja 70:8cd7a8a2c153 292 // Enable request signal for channel 10 this DMA swaps ADC0 between a0 and a1.
baxterja 74:ebc9f09fda11 293 DMA0->ERQ |= DMA_ERQ_ERQ10_MASK;
baxterja 70:8cd7a8a2c153 294
baxterja 70:8cd7a8a2c153 295
baxterja 70:8cd7a8a2c153 296 // DMA setup for ADC sampling
baxterja 70:8cd7a8a2c153 297 // Set memory address for source and destination for DMA0 and DMA1
baxterja 74:ebc9f09fda11 298 //DMA_TCD[10].SADDR = (uint32_t) &ADC0_RA;
baxterja 74:ebc9f09fda11 299 //DMA_TCD[10].DADDR = (uint32_t) sample_array0;
baxterja 74:ebc9f09fda11 300 DMA0->TCD[10].SADDR = (uint32_t) ADC0_LOCATION;
baxterja 74:ebc9f09fda11 301 DMA0->TCD[10].DADDR = (uint32_t) &ADC0->SC1[0];
baxterja 70:8cd7a8a2c153 302
baxterja 70:8cd7a8a2c153 303
baxterja 70:8cd7a8a2c153 304
baxterja 70:8cd7a8a2c153 305 // Set an offset for source and destination address
baxterja 74:ebc9f09fda11 306 DMA0->TCD[10].SOFF = 0x04; // Source address offset of 0 bytes per transaction
baxterja 74:ebc9f09fda11 307 DMA0->TCD[10].DOFF = 0x00; // Destination address offset of 2 bytes per transaction
baxterja 70:8cd7a8a2c153 308
baxterja 70:8cd7a8a2c153 309
baxterja 70:8cd7a8a2c153 310 // Set source and destination data transfer size
baxterja 74:ebc9f09fda11 311 DMA0->TCD[10].ATTR = DMA_ATTR_SSIZE(2) | DMA_ATTR_DSIZE(2);
baxterja 70:8cd7a8a2c153 312
baxterja 70:8cd7a8a2c153 313 // Number of bytes to be transfered in each service request of the channel
baxterja 74:ebc9f09fda11 314 DMA0->TCD[10].NBYTES_MLNO = 0x04;
baxterja 70:8cd7a8a2c153 315
baxterja 70:8cd7a8a2c153 316
baxterja 70:8cd7a8a2c153 317
baxterja 74:ebc9f09fda11 318 DMA0->TCD[10].SLAST = -(4*2); // Source address adjustment
baxterja 74:ebc9f09fda11 319 DMA0->TCD[10].DLAST_SGA = 0; // Destination address adjustment
baxterja 70:8cd7a8a2c153 320
baxterja 72:0b554f5026b9 321 //DMAMUX_CHCFG10 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC0 Source Jared's Note I think that this is actually the pdb timer
baxterja 70:8cd7a8a2c153 322
baxterja 74:ebc9f09fda11 323 //DMA_TCD[10].CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(2);
baxterja 74:ebc9f09fda11 324 //DMA_TCD[10].BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(2);
baxterja 74:ebc9f09fda11 325 DMA0->TCD[10].BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(8) | DMA_BITER_ELINKYES_BITER(2);
baxterja 74:ebc9f09fda11 326 DMA0->TCD[10].CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(8) | DMA_CITER_ELINKYES_CITER(2);
baxterja 74:ebc9f09fda11 327 DMA0->TCD[10].CSR |= DMA_CSR_MAJORLINKCH(8) | DMA_CSR_MAJORELINK_MASK;
baxterja 69:014d4bbd4e03 328
baxterja 69:014d4bbd4e03 329
timmey9 51:43143a3fc2d7 330 }
timmey9 51:43143a3fc2d7 331
timmey9 51:43143a3fc2d7 332 void dma_reset() {
timmey9 51:43143a3fc2d7 333 // Set memory address for destinations back to the beginning
timmey9 51:43143a3fc2d7 334 dma_init();
timmey9 51:43143a3fc2d7 335 }
timmey9 51:43143a3fc2d7 336
timmey9 51:43143a3fc2d7 337
timmey9 51:43143a3fc2d7 338
timmey9 51:43143a3fc2d7 339
timmey9 51:43143a3fc2d7 340 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 50:33524a27e08c 341 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 50:33524a27e08c 342 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 50:33524a27e08c 343 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 50:33524a27e08c 344 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 50:33524a27e08c 345 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 50:33524a27e08c 346 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 50:33524a27e08c 347 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 50:33524a27e08c 348 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 50:33524a27e08c 349 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 50:33524a27e08c 350 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 50:33524a27e08c 351 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 50:33524a27e08c 352 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 50:33524a27e08c 353 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 51:43143a3fc2d7 354 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/