Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

DMA_sampling/dma.cpp@54:1697dc574b96, 2016-02-16 (annotated)

Committer:
bmazzeo
Date:
Tue Feb 16 18:33:44 2016 +0000
Revision:
54:1697dc574b96
Parent:
53:83a90a47c1fd
Child:
55:2526b3317bc8
Using continuous conversion - before changing to clocked sampling

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 45:d591d138cdeb 1 /**
timmey9 45:d591d138cdeb 2 * Setup triggering for DMA2 and PortC
timmey9 34:44cc9b76a507 3 */
timmey9 34:44cc9b76a507 4 #include "dma.h"
timmey9 34:44cc9b76a507 5
bmazzeo 54:1697dc574b96 6 #define TOTAL_SAMPLES 1024
timmey9 45:d591d138cdeb 7 int len = TOTAL_SAMPLES;
timmey9 45:d591d138cdeb 8 uint16_t sample_array0[TOTAL_SAMPLES];
timmey9 45:d591d138cdeb 9 uint16_t sample_array1[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 10
bmazzeo 54:1697dc574b96 11 uint16_t static_input_array0[TOTAL_SAMPLES];
bmazzeo 54:1697dc574b96 12 uint16_t static_input_array1[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 13
timmey9 45:d591d138cdeb 14
timmey9 45:d591d138cdeb 15 void dma_init()
timmey9 34:44cc9b76a507 16 {
bmazzeo 54:1697dc574b96 17 // Enable clock for DMAMUX and DMA - all the peripherals need clocks to function
bmazzeo 54:1697dc574b96 18 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
bmazzeo 54:1697dc574b96 19 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
bmazzeo 54:1697dc574b96 20
bmazzeo 54:1697dc574b96 21
bmazzeo 54:1697dc574b96 22 // This first loop is what allows the DMA to get ADC samples
timmey9 45:d591d138cdeb 23 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
bmazzeo 54:1697dc574b96 24 DMAMUX_CHCFG0 = 0;
bmazzeo 54:1697dc574b96 25 DMAMUX_CHCFG1 = 0;
bmazzeo 54:1697dc574b96 26
timmey9 36:07d8a3143967 27
bmazzeo 54:1697dc574b96 28 // Enable request signal for channel 0, 1
bmazzeo 54:1697dc574b96 29 DMA_ERQ = 0;
bmazzeo 54:1697dc574b96 30 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK;
timmey9 45:d591d138cdeb 31
timmey9 45:d591d138cdeb 32 // select round-robin arbitration priority
timmey9 45:d591d138cdeb 33 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 45:d591d138cdeb 34
bmazzeo 54:1697dc574b96 35 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 54:1697dc574b96 36 DMA_TCD0_SADDR = (uint32_t) &ADC0_RA;
timmey9 45:d591d138cdeb 37 DMA_TCD0_DADDR = (uint32_t) sample_array0;
timmey9 50:33524a27e08c 38 DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
timmey9 45:d591d138cdeb 39 DMA_TCD1_DADDR = (uint32_t) sample_array1;
timmey9 36:07d8a3143967 40
timmey9 34:44cc9b76a507 41 // Set an offset for source and destination address
timmey9 34:44cc9b76a507 42 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 34:44cc9b76a507 43 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 44 DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 45 DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 34:44cc9b76a507 46
timmey9 34:44cc9b76a507 47 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 48 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 49 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 50
timmey9 34:44cc9b76a507 51 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 52 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 53 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 54
bmazzeo 54:1697dc574b96 55 // Major iteration count
timmey9 45:d591d138cdeb 56 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 57 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 45:d591d138cdeb 58 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 59 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 34:44cc9b76a507 60
timmey9 34:44cc9b76a507 61 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 45:d591d138cdeb 62 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
timmey9 45:d591d138cdeb 63
timmey9 44:41c262caf898 64 DMA_TCD0_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 65 DMA_TCD0_DLASTSGA = -len*2; // Destination address adjustment
timmey9 44:41c262caf898 66 DMA_TCD1_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 67 DMA_TCD1_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 68 // DMA_TCD2_SLAST = 0; // Source address adjustment
bmazzeo 54:1697dc574b96 69 // DMA_TCD2_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 70
bmazzeo 54:1697dc574b96 71 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
bmazzeo 54:1697dc574b96 72 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
bmazzeo 54:1697dc574b96 73 /* Source number Source module
bmazzeo 54:1697dc574b96 74 40 ADC0
bmazzeo 54:1697dc574b96 75 41 ADC1
bmazzeo 54:1697dc574b96 76 */
bmazzeo 54:1697dc574b96 77
bmazzeo 54:1697dc574b96 78
timmey9 34:44cc9b76a507 79 // Setup control and status register
timmey9 34:44cc9b76a507 80 DMA_TCD0_CSR = 0;
timmey9 36:07d8a3143967 81 DMA_TCD1_CSR = 0;
bmazzeo 54:1697dc574b96 82
bmazzeo 54:1697dc574b96 83
bmazzeo 54:1697dc574b96 84 // Now set up linking once the ADC samples are recorded
bmazzeo 54:1697dc574b96 85 // DMA Channels 2 and 3 now will be enabled
bmazzeo 54:1697dc574b96 86 DMA_ERQ |= DMA_ERQ_ERQ2_MASK | DMA_ERQ_ERQ3_MASK;
bmazzeo 54:1697dc574b96 87 DMA_TCD0_CSR |= DMA_CSR_MAJORLINKCH(2) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 54:1697dc574b96 88 DMA_TCD1_CSR |= DMA_CSR_MAJORLINKCH(3) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 54:1697dc574b96 89
bmazzeo 54:1697dc574b96 90 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 54:1697dc574b96 91 DMA_TCD2_SADDR = (uint32_t) sample_array0;
bmazzeo 54:1697dc574b96 92 DMA_TCD2_DADDR = (uint32_t) static_input_array0;
bmazzeo 54:1697dc574b96 93 DMA_TCD3_SADDR = (uint32_t) sample_array1;
bmazzeo 54:1697dc574b96 94 DMA_TCD3_DADDR = (uint32_t) static_input_array1;
bmazzeo 54:1697dc574b96 95
bmazzeo 54:1697dc574b96 96 // Set an offset for source and destination address
bmazzeo 54:1697dc574b96 97 DMA_TCD2_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 54:1697dc574b96 98 DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 54:1697dc574b96 99 DMA_TCD3_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 54:1697dc574b96 100 DMA_TCD3_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 54:1697dc574b96 101
bmazzeo 54:1697dc574b96 102 // Set source and destination data transfer size
bmazzeo 54:1697dc574b96 103 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 54:1697dc574b96 104 DMA_TCD3_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 54:1697dc574b96 105
bmazzeo 54:1697dc574b96 106 // Number of bytes to be transfered in each service request of the channel
bmazzeo 54:1697dc574b96 107 DMA_TCD2_NBYTES_MLNO = 0x02;
bmazzeo 54:1697dc574b96 108 DMA_TCD3_NBYTES_MLNO = 0x02;
bmazzeo 54:1697dc574b96 109
bmazzeo 54:1697dc574b96 110 // Current major iteration count
bmazzeo 54:1697dc574b96 111 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 54:1697dc574b96 112 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 54:1697dc574b96 113 DMA_TCD3_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 54:1697dc574b96 114 DMA_TCD3_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 54:1697dc574b96 115
bmazzeo 54:1697dc574b96 116 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 54:1697dc574b96 117 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 54:1697dc574b96 118
bmazzeo 54:1697dc574b96 119 DMA_TCD2_SLAST = -len*2; // Source address adjustment
bmazzeo 54:1697dc574b96 120 DMA_TCD2_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 121 DMA_TCD3_SLAST = -len*2; // Source address adjustment
bmazzeo 54:1697dc574b96 122 DMA_TCD3_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 123
timmey9 46:a015ebf4663b 124 DMA_TCD2_CSR = 0;
bmazzeo 54:1697dc574b96 125 DMA_TCD3_CSR = 0;
bmazzeo 54:1697dc574b96 126
bmazzeo 54:1697dc574b96 127
timmey9 51:43143a3fc2d7 128 }
timmey9 51:43143a3fc2d7 129
timmey9 51:43143a3fc2d7 130 void dma_reset() {
timmey9 51:43143a3fc2d7 131 // Set memory address for destinations back to the beginning
timmey9 51:43143a3fc2d7 132 dma_init();
timmey9 51:43143a3fc2d7 133 }
timmey9 51:43143a3fc2d7 134
timmey9 51:43143a3fc2d7 135
timmey9 51:43143a3fc2d7 136
timmey9 51:43143a3fc2d7 137
timmey9 51:43143a3fc2d7 138 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 50:33524a27e08c 139 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 50:33524a27e08c 140 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 50:33524a27e08c 141 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 50:33524a27e08c 142 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 50:33524a27e08c 143 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 50:33524a27e08c 144 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 50:33524a27e08c 145 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 50:33524a27e08c 146 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 50:33524a27e08c 147 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 50:33524a27e08c 148 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 50:33524a27e08c 149 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 50:33524a27e08c 150 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 50:33524a27e08c 151 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 51:43143a3fc2d7 152 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/