Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

dma.cpp@50:33524a27e08c, 2015-01-31 (annotated)

Committer:
timmey9
Date:
Sat Jan 31 19:46:00 2015 +0000
Revision:
50:33524a27e08c
Parent:
49:4dcf4717a8bb
Child:
51:43143a3fc2d7
Continuous sampling started by the PCB is working.  It is successfully triggering ADC0, ADC1, and the DMA is doing its job for the ADCs and FTM quad decoder.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 45:d591d138cdeb 1 /**
timmey9 45:d591d138cdeb 2 * Setup triggering for DMA2 and PortC
timmey9 34:44cc9b76a507 3 */
timmey9 34:44cc9b76a507 4 #include "dma.h"
timmey9 34:44cc9b76a507 5
timmey9 45:d591d138cdeb 6 #define TOTAL_SAMPLES 10
timmey9 45:d591d138cdeb 7 int len = TOTAL_SAMPLES;
timmey9 45:d591d138cdeb 8 uint16_t sample_array0[TOTAL_SAMPLES];
timmey9 45:d591d138cdeb 9 uint16_t sample_array1[TOTAL_SAMPLES];
timmey9 45:d591d138cdeb 10 uint16_t angle_array[TOTAL_SAMPLES];
timmey9 46:a015ebf4663b 11 //DigitalIn AMT20_A(PTB18); // FTM2_QD_PHA, apparently the k64f has a quadrature decoder. look into this (page 264)
timmey9 46:a015ebf4663b 12 //DigitalIn AMT20_B(PTB10); // FTM2_QD_PHB
timmey9 45:d591d138cdeb 13
timmey9 45:d591d138cdeb 14 void dma_init()
timmey9 34:44cc9b76a507 15 {
timmey9 34:44cc9b76a507 16 // Enable clock for DMAMUX and DMA
timmey9 34:44cc9b76a507 17 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
timmey9 45:d591d138cdeb 18 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
timmey9 46:a015ebf4663b 19 SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK; // make sure clock is enabled for FTM2
timmey9 34:44cc9b76a507 20
timmey9 45:d591d138cdeb 21 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
timmey9 45:d591d138cdeb 22 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
timmey9 45:d591d138cdeb 23 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
timmey9 48:29f14bc30ba6 24 DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // Set trigger source to PDB (Don't set DMA Trig Enable because that is for the PIT)
timmey9 46:a015ebf4663b 25 /* Source number Source module Source description
timmey9 48:29f14bc30ba6 26 40 ADC0
timmey9 48:29f14bc30ba6 27 41 ADC1
timmey9 46:a015ebf4663b 28 30 FTM2 Channel 0
timmey9 46:a015ebf4663b 29 31 FTM2 Channel 1
timmey9 46:a015ebf4663b 30 48 PDB -
timmey9 46:a015ebf4663b 31 */
timmey9 36:07d8a3143967 32
timmey9 36:07d8a3143967 33
timmey9 34:44cc9b76a507 34 // Enable request signal for channel 0
timmey9 36:07d8a3143967 35 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK | DMA_ERQ_ERQ2_MASK;
timmey9 45:d591d138cdeb 36
timmey9 45:d591d138cdeb 37 // select round-robin arbitration priority
timmey9 45:d591d138cdeb 38 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 45:d591d138cdeb 39
timmey9 36:07d8a3143967 40 // Set memory address for source and destination for DMA0, DMA1, and DMA2
timmey9 48:29f14bc30ba6 41 DMA_TCD0_SADDR = (uint32_t) &ADC0_RB;
timmey9 45:d591d138cdeb 42 DMA_TCD0_DADDR = (uint32_t) sample_array0;
timmey9 50:33524a27e08c 43 DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
timmey9 45:d591d138cdeb 44 DMA_TCD1_DADDR = (uint32_t) sample_array1;
timmey9 45:d591d138cdeb 45 DMA_TCD2_SADDR = (uint32_t) &FTM2_CNT;
timmey9 45:d591d138cdeb 46 DMA_TCD2_DADDR = (uint32_t) angle_array;
timmey9 36:07d8a3143967 47
timmey9 34:44cc9b76a507 48 // Set an offset for source and destination address
timmey9 34:44cc9b76a507 49 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 34:44cc9b76a507 50 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 51 DMA_TCD1_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 52 DMA_TCD1_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 36:07d8a3143967 53 DMA_TCD2_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 36:07d8a3143967 54 DMA_TCD2_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 34:44cc9b76a507 55
timmey9 34:44cc9b76a507 56 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 57 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 58 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 59 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 60
timmey9 34:44cc9b76a507 61 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 62 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 63 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 64 DMA_TCD2_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 65
timmey9 34:44cc9b76a507 66 // Current major iteration count (a single iteration of 5 bytes)
timmey9 45:d591d138cdeb 67 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 68 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 45:d591d138cdeb 69 DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 70 DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 45:d591d138cdeb 71 DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
timmey9 45:d591d138cdeb 72 DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
timmey9 34:44cc9b76a507 73
timmey9 34:44cc9b76a507 74 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 45:d591d138cdeb 75 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
timmey9 45:d591d138cdeb 76
timmey9 44:41c262caf898 77 DMA_TCD0_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 78 DMA_TCD0_DLASTSGA = -len*2; // Destination address adjustment
timmey9 44:41c262caf898 79 DMA_TCD1_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 80 DMA_TCD1_DLASTSGA = -len*2; // Destination address adjustment
timmey9 44:41c262caf898 81 DMA_TCD2_SLAST = 0; // Source address adjustment
timmey9 45:d591d138cdeb 82 DMA_TCD2_DLASTSGA = -len*2; // Destination address adjustment
timmey9 34:44cc9b76a507 83
timmey9 34:44cc9b76a507 84 // Setup control and status register
timmey9 34:44cc9b76a507 85 DMA_TCD0_CSR = 0;
timmey9 36:07d8a3143967 86 DMA_TCD1_CSR = 0;
timmey9 46:a015ebf4663b 87 DMA_TCD2_CSR = 0;
timmey9 39:82dc3daecf32 88
timmey9 45:d591d138cdeb 89
timmey9 50:33524a27e08c 90 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 50:33524a27e08c 91 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 50:33524a27e08c 92 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 50:33524a27e08c 93 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 50:33524a27e08c 94 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 50:33524a27e08c 95 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 50:33524a27e08c 96 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 50:33524a27e08c 97 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 50:33524a27e08c 98 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 50:33524a27e08c 99 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 50:33524a27e08c 100 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 50:33524a27e08c 101 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 50:33524a27e08c 102 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 50:33524a27e08c 103 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 50:33524a27e08c 104 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/
timmey9 34:44cc9b76a507 105 }
timmey9 40:bd6d8c35e822 106
timmey9 45:d591d138cdeb 107 void dma_reset() {
timmey9 40:bd6d8c35e822 108 // Set memory address for destinations back to the beginning
timmey9 45:d591d138cdeb 109 dma_init();
timmey9 40:bd6d8c35e822 110 }