Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

DMA_sampling/dma.cpp@63:7903a33e2fd4, 2016-02-23 (annotated)

Committer:
bmazzeo
Date:
Tue Feb 23 19:49:42 2016 +0000
Revision:
63:7903a33e2fd4
Parent:
62:51f722ef9cb1
Child:
65:f022535bed5d
Double length buffers appear to work now.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 45:d591d138cdeb 1 /**
timmey9 45:d591d138cdeb 2 * Setup triggering for DMA2 and PortC
timmey9 34:44cc9b76a507 3 */
timmey9 34:44cc9b76a507 4 #include "dma.h"
timmey9 34:44cc9b76a507 5
bmazzeo 63:7903a33e2fd4 6 #define TOTAL_SAMPLES 16
bmazzeo 63:7903a33e2fd4 7 #define SAMPLE_BUFFER_LENGTH 32
timmey9 45:d591d138cdeb 8 int len = TOTAL_SAMPLES;
bmazzeo 63:7903a33e2fd4 9 uint16_t sample_array0[SAMPLE_BUFFER_LENGTH];
bmazzeo 63:7903a33e2fd4 10 uint16_t sample_array1[SAMPLE_BUFFER_LENGTH];
timmey9 51:43143a3fc2d7 11
bmazzeo 54:1697dc574b96 12 uint16_t static_input_array0[TOTAL_SAMPLES];
bmazzeo 54:1697dc574b96 13 uint16_t static_input_array1[TOTAL_SAMPLES];
timmey9 51:43143a3fc2d7 14
bmazzeo 55:2526b3317bc8 15 uint16_t static_output_array0[TOTAL_SAMPLES];
bmazzeo 63:7903a33e2fd4 16 uint16_t output_array0[SAMPLE_BUFFER_LENGTH];
timmey9 45:d591d138cdeb 17
bmazzeo 57:7b8c49e1c1f6 18 uint16_t sampling_status;
bmazzeo 57:7b8c49e1c1f6 19 uint16_t sampling_status_done = 1;
bmazzeo 57:7b8c49e1c1f6 20
bmazzeo 63:7903a33e2fd4 21 uint16_t intermediate_status;
bmazzeo 63:7903a33e2fd4 22 uint16_t intermediate_status_done = 1;
bmazzeo 63:7903a33e2fd4 23
timmey9 45:d591d138cdeb 24 void dma_init()
timmey9 34:44cc9b76a507 25 {
bmazzeo 54:1697dc574b96 26 // Enable clock for DMAMUX and DMA - all the peripherals need clocks to function
bmazzeo 54:1697dc574b96 27 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
bmazzeo 54:1697dc574b96 28 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
bmazzeo 54:1697dc574b96 29
bmazzeo 54:1697dc574b96 30
timmey9 45:d591d138cdeb 31 // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
bmazzeo 54:1697dc574b96 32 DMAMUX_CHCFG0 = 0;
bmazzeo 54:1697dc574b96 33 DMAMUX_CHCFG1 = 0;
bmazzeo 63:7903a33e2fd4 34 DMAMUX_CHCFG2 = 0;
bmazzeo 63:7903a33e2fd4 35 DMAMUX_CHCFG3 = 0;
bmazzeo 63:7903a33e2fd4 36 DMAMUX_CHCFG4 = 0;
bmazzeo 63:7903a33e2fd4 37 DMAMUX_CHCFG5 = 0;
bmazzeo 63:7903a33e2fd4 38 DMAMUX_CHCFG6 = 0;
bmazzeo 63:7903a33e2fd4 39 DMAMUX_CHCFG7 = 0;
bmazzeo 63:7903a33e2fd4 40 DMAMUX_CHCFG8 = 0;
bmazzeo 63:7903a33e2fd4 41 DMAMUX_CHCFG9 = 0;
bmazzeo 63:7903a33e2fd4 42
bmazzeo 54:1697dc574b96 43
bmazzeo 63:7903a33e2fd4 44
bmazzeo 54:1697dc574b96 45 // Enable request signal for channel 0, 1
bmazzeo 54:1697dc574b96 46 DMA_ERQ = 0;
bmazzeo 54:1697dc574b96 47 DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK;
timmey9 45:d591d138cdeb 48
timmey9 45:d591d138cdeb 49 // select round-robin arbitration priority
timmey9 45:d591d138cdeb 50 DMA_CR |= DMA_CR_ERCA_MASK;
timmey9 45:d591d138cdeb 51
bmazzeo 55:2526b3317bc8 52 // Disable minor loop
bmazzeo 60:873a6d60c5d5 53 //DMA_CR &= ~DMA_CR_EMLM_MASK;
bmazzeo 60:873a6d60c5d5 54 DMA_CR |= DMA_CR_EMLM_MASK;
bmazzeo 56:7e08cbc3a4f1 55
bmazzeo 63:7903a33e2fd4 56 DMA_TCD0_CSR = 0;
bmazzeo 63:7903a33e2fd4 57 DMA_TCD1_CSR = 0;
bmazzeo 63:7903a33e2fd4 58 DMA_TCD2_CSR = 0;
bmazzeo 63:7903a33e2fd4 59 DMA_TCD3_CSR = 0;
bmazzeo 63:7903a33e2fd4 60 DMA_TCD4_CSR = 0;
bmazzeo 63:7903a33e2fd4 61 DMA_TCD5_CSR = 0;
bmazzeo 63:7903a33e2fd4 62 DMA_TCD6_CSR = 0;
bmazzeo 63:7903a33e2fd4 63 DMA_TCD7_CSR = 0;
bmazzeo 63:7903a33e2fd4 64 DMA_TCD8_CSR = 0;
bmazzeo 63:7903a33e2fd4 65 DMA_TCD9_CSR = 0;
bmazzeo 63:7903a33e2fd4 66
bmazzeo 63:7903a33e2fd4 67
bmazzeo 56:7e08cbc3a4f1 68 // DMA setup for ADC sampling
bmazzeo 54:1697dc574b96 69 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 54:1697dc574b96 70 DMA_TCD0_SADDR = (uint32_t) &ADC0_RA;
timmey9 45:d591d138cdeb 71 DMA_TCD0_DADDR = (uint32_t) sample_array0;
timmey9 50:33524a27e08c 72 DMA_TCD1_SADDR = (uint32_t) &ADC1_RA;
timmey9 45:d591d138cdeb 73 DMA_TCD1_DADDR = (uint32_t) sample_array1;
timmey9 36:07d8a3143967 74
timmey9 34:44cc9b76a507 75 // Set an offset for source and destination address
bmazzeo 55:2526b3317bc8 76 DMA_TCD0_SOFF = 0x00; // Source address offset of 0 bytes per transaction
bmazzeo 55:2526b3317bc8 77 DMA_TCD0_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
bmazzeo 55:2526b3317bc8 78 DMA_TCD1_SOFF = 0x00; // Source address offset of 0 bytes per transaction
bmazzeo 55:2526b3317bc8 79 DMA_TCD1_DOFF = 0x02; // Destination address offset of 2 bytes per transaction
timmey9 34:44cc9b76a507 80
timmey9 34:44cc9b76a507 81 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 82 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 36:07d8a3143967 83 DMA_TCD1_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 84
timmey9 34:44cc9b76a507 85 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 86 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 36:07d8a3143967 87 DMA_TCD1_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 88
bmazzeo 63:7903a33e2fd4 89
timmey9 44:41c262caf898 90 DMA_TCD0_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 91 DMA_TCD0_DLASTSGA = -len*2*2; // Destination address adjustment
timmey9 44:41c262caf898 92 DMA_TCD1_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 93 DMA_TCD1_DLASTSGA = -len*2*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 94 // DMA_TCD2_SLAST = 0; // Source address adjustment
bmazzeo 54:1697dc574b96 95 // DMA_TCD2_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 54:1697dc574b96 96
bmazzeo 62:51f722ef9cb1 97 //DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0
bmazzeo 61:a56cca07d4a6 98 //DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(41); // ADC1
bmazzeo 54:1697dc574b96 99 /* Source number Source module
bmazzeo 54:1697dc574b96 100 40 ADC0
bmazzeo 54:1697dc574b96 101 41 ADC1
bmazzeo 54:1697dc574b96 102 */
bmazzeo 54:1697dc574b96 103
bmazzeo 63:7903a33e2fd4 104 DMA_TCD0_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(1) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 105 DMA_TCD0_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(1) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 106 DMA_TCD0_CSR = DMA_CSR_MAJORLINKCH(1) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 107 DMA_TCD1_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(8) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 108 DMA_TCD1_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(8) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
bmazzeo 63:7903a33e2fd4 109 DMA_TCD1_CSR = DMA_CSR_MAJORLINKCH(8) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 110
bmazzeo 61:a56cca07d4a6 111 // Setup control and status register
bmazzeo 54:1697dc574b96 112
bmazzeo 56:7e08cbc3a4f1 113 //
bmazzeo 56:7e08cbc3a4f1 114 // Now set up DAC DMA outputs from the output array
bmazzeo 56:7e08cbc3a4f1 115 //
bmazzeo 56:7e08cbc3a4f1 116 DMA_ERQ |= DMA_ERQ_ERQ2_MASK;
bmazzeo 59:1cfd9d9fb99d 117 //DMA_TCD1_CSR |= DMA_CSR_MAJORLINKCH(2) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 59:1cfd9d9fb99d 118
bmazzeo 54:1697dc574b96 119 // Set memory address for source and destination for DMA0 and DMA1
bmazzeo 56:7e08cbc3a4f1 120 DMA_TCD2_SADDR = (uint32_t) output_array0;
bmazzeo 56:7e08cbc3a4f1 121 DMA_TCD2_DADDR = (uint32_t) &DAC0_DAT0L;
bmazzeo 54:1697dc574b96 122
bmazzeo 54:1697dc574b96 123 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 124 DMA_TCD2_SOFF = 0x02; // Source address offset of 1 per transaction
bmazzeo 56:7e08cbc3a4f1 125 DMA_TCD2_DOFF = 0x00; // Destination address offset of 0 bytes per transaction
bmazzeo 54:1697dc574b96 126
bmazzeo 54:1697dc574b96 127 // Set source and destination data transfer size
bmazzeo 54:1697dc574b96 128 DMA_TCD2_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 54:1697dc574b96 129
bmazzeo 54:1697dc574b96 130 // Number of bytes to be transfered in each service request of the channel
bmazzeo 56:7e08cbc3a4f1 131 DMA_TCD2_NBYTES_MLNO = 0x02;
bmazzeo 63:7903a33e2fd4 132 //DMA_TCD2_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x00) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
bmazzeo 63:7903a33e2fd4 133 //DMA_TCD1_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x02) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
bmazzeo 63:7903a33e2fd4 134
bmazzeo 54:1697dc574b96 135
bmazzeo 56:7e08cbc3a4f1 136 // Major iteration count
bmazzeo 62:51f722ef9cb1 137 //DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 62:51f722ef9cb1 138 //DMA_TCD2_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 54:1697dc574b96 139
bmazzeo 54:1697dc574b96 140 // Adjustment value used to restore the source and destiny address to the initial value
bmazzeo 54:1697dc574b96 141 // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
bmazzeo 54:1697dc574b96 142
bmazzeo 63:7903a33e2fd4 143 DMA_TCD2_SLAST = -len*2*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 144 DMA_TCD2_DLASTSGA = 0; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 145
bmazzeo 63:7903a33e2fd4 146 DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // ADC0 Source
bmazzeo 62:51f722ef9cb1 147
bmazzeo 63:7903a33e2fd4 148 DMA_TCD2_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(0) | DMA_BITER_ELINKYES_BITER(len*2);
bmazzeo 63:7903a33e2fd4 149 DMA_TCD2_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(0) | DMA_CITER_ELINKYES_CITER(len*2);
bmazzeo 63:7903a33e2fd4 150 DMA_TCD2_CSR |= DMA_CSR_MAJORLINKCH(0) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 151
bmazzeo 56:7e08cbc3a4f1 152 //
bmazzeo 56:7e08cbc3a4f1 153 // Now set up static dataset linking once the ADC samples are recorded
bmazzeo 56:7e08cbc3a4f1 154 //
bmazzeo 56:7e08cbc3a4f1 155 // DMA Channels 4 and 5 now will be enabled
bmazzeo 56:7e08cbc3a4f1 156 DMA_ERQ |= DMA_ERQ_ERQ4_MASK | DMA_ERQ_ERQ5_MASK;
bmazzeo 54:1697dc574b96 157
bmazzeo 56:7e08cbc3a4f1 158 // Set memory address for source and destination for DMA4 and DMA5
bmazzeo 63:7903a33e2fd4 159 DMA_TCD4_SADDR = (uint32_t) &sample_array0;
bmazzeo 63:7903a33e2fd4 160 DMA_TCD4_DADDR = (uint32_t) &static_input_array0;
bmazzeo 63:7903a33e2fd4 161 DMA_TCD5_SADDR = (uint32_t) &sample_array1;
bmazzeo 63:7903a33e2fd4 162 DMA_TCD5_DADDR = (uint32_t) &static_input_array1;
bmazzeo 56:7e08cbc3a4f1 163
bmazzeo 56:7e08cbc3a4f1 164 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 165 DMA_TCD4_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 166 DMA_TCD4_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 167 DMA_TCD5_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 168 DMA_TCD5_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 169
bmazzeo 56:7e08cbc3a4f1 170 // Set source and destination data transfer size
bmazzeo 56:7e08cbc3a4f1 171 DMA_TCD4_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 172 DMA_TCD5_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 173
bmazzeo 63:7903a33e2fd4 174 DMA_TCD4_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 63:7903a33e2fd4 175 DMA_TCD5_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 56:7e08cbc3a4f1 176
bmazzeo 63:7903a33e2fd4 177 DMA_TCD4_SLAST = -len*2*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 178 DMA_TCD4_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 179 //DMA_TCD4_DLASTSGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 180 DMA_TCD5_SLAST = -len*2*2; // Source address adjustment
bmazzeo 56:7e08cbc3a4f1 181 DMA_TCD5_DLASTSGA = -len*2; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 182 //DMA_TCD5_DLASTSGA = 0; // Destination address adjustment
bmazzeo 54:1697dc574b96 183
bmazzeo 63:7903a33e2fd4 184 //DMA_TCD4_CSR |= DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 185 DMA_TCD4_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(5) | DMA_BITER_ELINKYES_BITER(2);
bmazzeo 63:7903a33e2fd4 186 DMA_TCD4_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(5) | DMA_CITER_ELINKYES_CITER(2);
bmazzeo 63:7903a33e2fd4 187 DMA_TCD4_CSR = DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 188 DMA_TCD5_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(6) | DMA_BITER_ELINKYES_BITER(2);
bmazzeo 63:7903a33e2fd4 189 DMA_TCD5_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(6) | DMA_CITER_ELINKYES_CITER(2);
bmazzeo 63:7903a33e2fd4 190 DMA_TCD5_CSR = DMA_CSR_MAJORLINKCH(6) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 56:7e08cbc3a4f1 191
bmazzeo 56:7e08cbc3a4f1 192 //
bmazzeo 56:7e08cbc3a4f1 193 // Now set up linking from static DAC to memory for output through DMA
bmazzeo 56:7e08cbc3a4f1 194 //
bmazzeo 56:7e08cbc3a4f1 195 // DMA Channel 6 will be enabled
bmazzeo 56:7e08cbc3a4f1 196
bmazzeo 56:7e08cbc3a4f1 197 DMA_ERQ |= DMA_ERQ_ERQ6_MASK;
bmazzeo 55:2526b3317bc8 198
bmazzeo 56:7e08cbc3a4f1 199 // Set memory address for source and destination for DMA6
bmazzeo 56:7e08cbc3a4f1 200 DMA_TCD6_SADDR = (uint32_t) static_output_array0;
bmazzeo 56:7e08cbc3a4f1 201 DMA_TCD6_DADDR = (uint32_t) output_array0;
bmazzeo 56:7e08cbc3a4f1 202
bmazzeo 56:7e08cbc3a4f1 203 // Set an offset for source and destination address
bmazzeo 56:7e08cbc3a4f1 204 DMA_TCD6_SOFF = 0x02; // Source address offset of 2 bits per transaction
bmazzeo 56:7e08cbc3a4f1 205 DMA_TCD6_DOFF = 0x02; // Destination address offset of 1 bit per transaction
bmazzeo 56:7e08cbc3a4f1 206
bmazzeo 56:7e08cbc3a4f1 207 // Set source and destination data transfer size
bmazzeo 56:7e08cbc3a4f1 208 DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 209 DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 56:7e08cbc3a4f1 210
bmazzeo 56:7e08cbc3a4f1 211
bmazzeo 63:7903a33e2fd4 212 DMA_TCD6_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
bmazzeo 56:7e08cbc3a4f1 213
bmazzeo 56:7e08cbc3a4f1 214 DMA_TCD6_SLAST = -len*2; // Source address adjustment
bmazzeo 63:7903a33e2fd4 215 //DMA_TCD6_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 216 DMA_TCD6_DLASTSGA = -len*2*2; // Destination address adjustment
bmazzeo 56:7e08cbc3a4f1 217
bmazzeo 63:7903a33e2fd4 218 DMA_TCD6_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(9) | DMA_BITER_ELINKYES_BITER(2);
bmazzeo 63:7903a33e2fd4 219 DMA_TCD6_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(9) | DMA_CITER_ELINKYES_CITER(2);
bmazzeo 63:7903a33e2fd4 220
bmazzeo 63:7903a33e2fd4 221 DMA_TCD6_CSR |= DMA_CSR_MAJORLINKCH(9) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 63:7903a33e2fd4 222
bmazzeo 57:7b8c49e1c1f6 223 //
bmazzeo 63:7903a33e2fd4 224 // Provide control for intermediate loops
bmazzeo 57:7b8c49e1c1f6 225 //
bmazzeo 57:7b8c49e1c1f6 226
bmazzeo 57:7b8c49e1c1f6 227 // DMA Channel 8
bmazzeo 57:7b8c49e1c1f6 228 DMA_ERQ |= DMA_ERQ_ERQ8_MASK;
bmazzeo 57:7b8c49e1c1f6 229
bmazzeo 57:7b8c49e1c1f6 230 // Set memory address for source and destiantion for DMA 8
bmazzeo 63:7903a33e2fd4 231 DMA_TCD8_SADDR = (uint32_t) &intermediate_status_done;
bmazzeo 63:7903a33e2fd4 232 DMA_TCD8_DADDR = (uint32_t) &intermediate_status;
bmazzeo 57:7b8c49e1c1f6 233
bmazzeo 57:7b8c49e1c1f6 234 // Set an offset for source and destination address
bmazzeo 57:7b8c49e1c1f6 235 DMA_TCD8_SOFF = 0x00; // Source address offset of 2 bits per transaction
bmazzeo 57:7b8c49e1c1f6 236 DMA_TCD8_DOFF = 0x00; // Destination address offset of 1 bit per transaction
bmazzeo 57:7b8c49e1c1f6 237
bmazzeo 57:7b8c49e1c1f6 238 // Set source and destination data transfer size
bmazzeo 57:7b8c49e1c1f6 239 DMA_TCD8_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 57:7b8c49e1c1f6 240 DMA_TCD8_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 57:7b8c49e1c1f6 241
bmazzeo 57:7b8c49e1c1f6 242 // Number of bytes to be transfered in each service request of the channel
bmazzeo 57:7b8c49e1c1f6 243 DMA_TCD8_NBYTES_MLNO = 0x02;
bmazzeo 57:7b8c49e1c1f6 244
bmazzeo 57:7b8c49e1c1f6 245 // Current major iteration count
bmazzeo 63:7903a33e2fd4 246 DMA_TCD8_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 63:7903a33e2fd4 247 DMA_TCD8_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 63:7903a33e2fd4 248
bmazzeo 57:7b8c49e1c1f6 249 DMA_TCD8_SLAST = 0; // Source address adjustment
bmazzeo 57:7b8c49e1c1f6 250 DMA_TCD8_DLASTSGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 251
bmazzeo 63:7903a33e2fd4 252 DMA_TCD8_CSR |= DMA_CSR_MAJORLINKCH(4) | DMA_CSR_MAJORELINK_MASK;
bmazzeo 57:7b8c49e1c1f6 253
bmazzeo 63:7903a33e2fd4 254 //
bmazzeo 63:7903a33e2fd4 255 // Provide status
bmazzeo 63:7903a33e2fd4 256 //
bmazzeo 63:7903a33e2fd4 257
bmazzeo 63:7903a33e2fd4 258 // DMA Channel 9
bmazzeo 63:7903a33e2fd4 259 DMA_ERQ |= DMA_ERQ_ERQ9_MASK;
bmazzeo 63:7903a33e2fd4 260
bmazzeo 63:7903a33e2fd4 261 // Set memory address for source and destiantion for DMA 8
bmazzeo 63:7903a33e2fd4 262 DMA_TCD9_SADDR = (uint32_t) &sampling_status_done;
bmazzeo 63:7903a33e2fd4 263 DMA_TCD9_DADDR = (uint32_t) &sampling_status;
bmazzeo 57:7b8c49e1c1f6 264
bmazzeo 63:7903a33e2fd4 265 // Set an offset for source and destination address
bmazzeo 63:7903a33e2fd4 266 DMA_TCD9_SOFF = 0x00; // Source address offset of 2 bits per transaction
bmazzeo 63:7903a33e2fd4 267 DMA_TCD9_DOFF = 0x00; // Destination address offset of 1 bit per transaction
bmazzeo 63:7903a33e2fd4 268
bmazzeo 63:7903a33e2fd4 269 // Set source and destination data transfer size
bmazzeo 63:7903a33e2fd4 270 DMA_TCD9_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 63:7903a33e2fd4 271 DMA_TCD9_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
bmazzeo 63:7903a33e2fd4 272
bmazzeo 63:7903a33e2fd4 273 // Number of bytes to be transfered in each service request of the channel
bmazzeo 63:7903a33e2fd4 274 DMA_TCD9_NBYTES_MLNO = 0x02;
bmazzeo 63:7903a33e2fd4 275
bmazzeo 63:7903a33e2fd4 276 // Current major iteration count
bmazzeo 63:7903a33e2fd4 277 DMA_TCD9_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
bmazzeo 63:7903a33e2fd4 278 DMA_TCD9_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
bmazzeo 63:7903a33e2fd4 279
bmazzeo 63:7903a33e2fd4 280 DMA_TCD9_SLAST = 0; // Source address adjustment
bmazzeo 63:7903a33e2fd4 281 DMA_TCD9_DLASTSGA = 0; // Destination address adjustment
bmazzeo 63:7903a33e2fd4 282
bmazzeo 63:7903a33e2fd4 283
timmey9 51:43143a3fc2d7 284 }
timmey9 51:43143a3fc2d7 285
timmey9 51:43143a3fc2d7 286 void dma_reset() {
timmey9 51:43143a3fc2d7 287 // Set memory address for destinations back to the beginning
timmey9 51:43143a3fc2d7 288 dma_init();
timmey9 51:43143a3fc2d7 289 }
timmey9 51:43143a3fc2d7 290
timmey9 51:43143a3fc2d7 291
timmey9 51:43143a3fc2d7 292
timmey9 51:43143a3fc2d7 293
timmey9 51:43143a3fc2d7 294 /*pc.printf("DMA_CR: %08x\r\n", DMA_CR);
timmey9 50:33524a27e08c 295 pc.printf("DMA_ES: %08x\r\n", DMA_ES);
timmey9 50:33524a27e08c 296 pc.printf("DMA_ERQ: %08x\r\n", DMA_ERQ);
timmey9 50:33524a27e08c 297 pc.printf("DMA_EEI: %08x\r\n", DMA_EEI);
timmey9 50:33524a27e08c 298 pc.printf("DMA_CEEI: %02x\r\n", DMA_CEEI);
timmey9 50:33524a27e08c 299 pc.printf("DMA_SEEI: %02x\r\n", DMA_SEEI);
timmey9 50:33524a27e08c 300 pc.printf("DMA_CERQ: %02x\r\n", DMA_CERQ);
timmey9 50:33524a27e08c 301 pc.printf("DMA_SERQ: %02x\r\n", DMA_SERQ);
timmey9 50:33524a27e08c 302 pc.printf("DMA_CDNE: %02x\r\n", DMA_CDNE);
timmey9 50:33524a27e08c 303 pc.printf("DMA_SSRT: %02x\r\n", DMA_SSRT);
timmey9 50:33524a27e08c 304 pc.printf("DMA_CERR: %02x\r\n", DMA_CERR);
timmey9 50:33524a27e08c 305 pc.printf("DMA_CINT: %02x\r\n", DMA_CINT);
timmey9 50:33524a27e08c 306 pc.printf("DMA_INT: %08x\r\n", DMA_INT);
timmey9 50:33524a27e08c 307 pc.printf("DMA_ERR: %08x\r\n", DMA_ERR);
timmey9 51:43143a3fc2d7 308 pc.printf("DMA_HRS: %08x\r\n", DMA_HRS);*/