Jared Baxter / Mbed 2 deprecated Impedance_Fast_Circuitry

Dependencies:   mbed-dsp mbed

Fork of DSP_200kHz by Mazzeo Research Group

dma.cpp@34:44cc9b76a507, 2015-01-25 (annotated)

Committer:
timmey9
Date:
Sun Jan 25 02:45:58 2015 +0000
Revision:
34:44cc9b76a507
Child:
35:df40c4566826
Analog reading works.  Trying to add DMA capabilities.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
timmey9 34:44cc9b76a507 1 /*
timmey9 34:44cc9b76a507 2 * dma.c
timmey9 34:44cc9b76a507 3 *
timmey9 34:44cc9b76a507 4 * Created on: Nov 25, 2014
timmey9 34:44cc9b76a507 5 * Author: Manuel Alejandro
timmey9 34:44cc9b76a507 6 */
timmey9 34:44cc9b76a507 7 #include "dma.h"
timmey9 34:44cc9b76a507 8
timmey9 34:44cc9b76a507 9 /* dma_init()
timmey9 34:44cc9b76a507 10 * Initializes the DMA module to read the ADC results every time a conversion has
timmey9 34:44cc9b76a507 11 * finished and stores its value in a buffer
timmey9 34:44cc9b76a507 12 *
timmey9 34:44cc9b76a507 13 * @buffer = destination where DMA writes
timmey9 34:44cc9b76a507 14 * @adc_reads = the length of buffer and the number of reads the DMA completes
timmey9 34:44cc9b76a507 15 * */
timmey9 34:44cc9b76a507 16
timmey9 34:44cc9b76a507 17 void dma_init(uint16_t* buffer,int adc_reads)
timmey9 34:44cc9b76a507 18 {
timmey9 34:44cc9b76a507 19 // Enable clock for DMAMUX and DMA
timmey9 34:44cc9b76a507 20 SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
timmey9 34:44cc9b76a507 21 SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
timmey9 34:44cc9b76a507 22
timmey9 34:44cc9b76a507 23 // Enable Channel 0 and set ADC0 as DMA request source
timmey9 34:44cc9b76a507 24 DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40);
timmey9 34:44cc9b76a507 25
timmey9 34:44cc9b76a507 26 // Enable request signal for channel 0
timmey9 34:44cc9b76a507 27 DMA_ERQ = DMA_ERQ_ERQ0_MASK;
timmey9 34:44cc9b76a507 28
timmey9 34:44cc9b76a507 29 // Set memory address for source and destination
timmey9 34:44cc9b76a507 30 DMA_TCD0_SADDR = (uint32_t)&ADC0_RA;
timmey9 34:44cc9b76a507 31 DMA_TCD0_DADDR = (uint32_t) buffer;
timmey9 34:44cc9b76a507 32
timmey9 34:44cc9b76a507 33 // Set an offset for source and destination address
timmey9 34:44cc9b76a507 34 DMA_TCD0_SOFF = 0x00; // Source address offset of 2 bits per transaction
timmey9 34:44cc9b76a507 35 DMA_TCD0_DOFF = 0x02; // Destination address offset of 1 bit per transaction
timmey9 34:44cc9b76a507 36
timmey9 34:44cc9b76a507 37 // Set source and destination data transfer size
timmey9 34:44cc9b76a507 38 DMA_TCD0_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
timmey9 34:44cc9b76a507 39
timmey9 34:44cc9b76a507 40 // Number of bytes to be transfered in each service request of the channel
timmey9 34:44cc9b76a507 41 DMA_TCD0_NBYTES_MLNO = 0x02;
timmey9 34:44cc9b76a507 42
timmey9 34:44cc9b76a507 43 // Current major iteration count (a single iteration of 5 bytes)
timmey9 34:44cc9b76a507 44 DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(adc_reads);
timmey9 34:44cc9b76a507 45 DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(adc_reads);
timmey9 34:44cc9b76a507 46
timmey9 34:44cc9b76a507 47 // Adjustment value used to restore the source and destiny address to the initial value
timmey9 34:44cc9b76a507 48 DMA_TCD0_SLAST = 0x00; // Source address adjustment
timmey9 34:44cc9b76a507 49 DMA_TCD0_DLASTSGA = -0x10; // Destination address adjustment
timmey9 34:44cc9b76a507 50
timmey9 34:44cc9b76a507 51 // Setup control and status register
timmey9 34:44cc9b76a507 52 DMA_TCD0_CSR = 0;
timmey9 34:44cc9b76a507 53 }