Diff: DMA_sampling/dma.cpp

Revision:

63:7903a33e2fd4

Parent:

62:51f722ef9cb1

Child:

65:f022535bed5d

--- a/DMA_sampling/dma.cpp	Mon Feb 22 19:52:12 2016 +0000
+++ b/DMA_sampling/dma.cpp	Tue Feb 23 19:49:42 2016 +0000
@@ -3,20 +3,24 @@
  */
 #include "dma.h"
 
-#define TOTAL_SAMPLES 256
+#define TOTAL_SAMPLES 16
+#define SAMPLE_BUFFER_LENGTH 32
 int len = TOTAL_SAMPLES;
-uint16_t sample_array0[TOTAL_SAMPLES];
-uint16_t sample_array1[TOTAL_SAMPLES];
+uint16_t sample_array0[SAMPLE_BUFFER_LENGTH];
+uint16_t sample_array1[SAMPLE_BUFFER_LENGTH];
 
 uint16_t static_input_array0[TOTAL_SAMPLES];
 uint16_t static_input_array1[TOTAL_SAMPLES];
 
 uint16_t static_output_array0[TOTAL_SAMPLES];
-uint16_t output_array0[TOTAL_SAMPLES];
+uint16_t output_array0[SAMPLE_BUFFER_LENGTH];
 
 uint16_t sampling_status;
 uint16_t sampling_status_done = 1;
 
+uint16_t intermediate_status;
+uint16_t intermediate_status_done = 1;
+
 void dma_init()
 {
     // Enable clock for DMAMUX and DMA - all the peripherals need clocks to function
@@ -27,8 +31,17 @@
     // Enable DMA channels and select MUX to the correct source (see page 95 of user manual
     DMAMUX_CHCFG0 = 0;
     DMAMUX_CHCFG1 = 0;
+    DMAMUX_CHCFG2 = 0;
+    DMAMUX_CHCFG3 = 0;
+    DMAMUX_CHCFG4 = 0;
+    DMAMUX_CHCFG5 = 0;
+    DMAMUX_CHCFG6 = 0;
+    DMAMUX_CHCFG7 = 0;
+    DMAMUX_CHCFG8 = 0;
+    DMAMUX_CHCFG9 = 0;
+
   
-    
+   
     // Enable request signal for channel 0, 1
     DMA_ERQ = 0;
     DMA_ERQ = DMA_ERQ_ERQ0_MASK | DMA_ERQ_ERQ1_MASK;
@@ -40,6 +53,18 @@
     //DMA_CR &= ~DMA_CR_EMLM_MASK;
     DMA_CR |= DMA_CR_EMLM_MASK;
 
+    DMA_TCD0_CSR = 0;
+    DMA_TCD1_CSR = 0;
+    DMA_TCD2_CSR = 0;
+    DMA_TCD3_CSR = 0;
+    DMA_TCD4_CSR = 0;
+    DMA_TCD5_CSR = 0;
+    DMA_TCD6_CSR = 0;
+    DMA_TCD7_CSR = 0;
+    DMA_TCD8_CSR = 0;
+    DMA_TCD9_CSR = 0;
+
+
 // DMA setup for ADC sampling    
     // Set memory address for source and destination for DMA0 and DMA1
     DMA_TCD0_SADDR = (uint32_t) &ADC0_RA;
@@ -61,19 +86,11 @@
     DMA_TCD0_NBYTES_MLNO = 0x02;
     DMA_TCD1_NBYTES_MLNO = 0x02;
         
-    // Major iteration count
-//    DMA_TCD0_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
-//    DMA_TCD0_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
-    DMA_TCD1_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
-    DMA_TCD1_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
-    
-    // Adjustment value used to restore the source and destiny address to the initial value
-    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
-    
+   
     DMA_TCD0_SLAST = 0;      // Source address adjustment
-    DMA_TCD0_DLASTSGA = -len*2;  // Destination address adjustment
+    DMA_TCD0_DLASTSGA = -len*2*2;  // Destination address adjustment
     DMA_TCD1_SLAST = 0;      // Source address adjustment
-    DMA_TCD1_DLASTSGA = -len*2;  // Destination address adjustment
+    DMA_TCD1_DLASTSGA = -len*2*2;  // Destination address adjustment
 //    DMA_TCD2_SLAST = 0;      // Source address adjustment
 //    DMA_TCD2_DLASTSGA = -len*2;  // Destination address adjustment
 
@@ -84,14 +101,13 @@
            41                ADC1
     */
 
-    DMA_TCD0_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(1) | DMA_BITER_ELINKYES_BITER(len);
-    DMA_TCD0_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(1) | DMA_CITER_ELINKYES_CITER(len);
-//    DMA_TCD1_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(2) | DMA_BITER_ELINKYES_BITER(len);
-//    DMA_TCD1_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(2) | DMA_CITER_ELINKYES_CITER(len);
-
-    DMA_TCD0_CSR = 0;
-    DMA_TCD1_CSR = 0;
-  
+    DMA_TCD0_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(1) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
+    DMA_TCD0_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(1) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
+    DMA_TCD0_CSR = DMA_CSR_MAJORLINKCH(1) | DMA_CSR_MAJORELINK_MASK;
+    DMA_TCD1_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(8) | DMA_BITER_ELINKYES_BITER(SAMPLE_BUFFER_LENGTH);
+    DMA_TCD1_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(8) | DMA_CITER_ELINKYES_CITER(SAMPLE_BUFFER_LENGTH);
+    DMA_TCD1_CSR = DMA_CSR_MAJORLINKCH(8) | DMA_CSR_MAJORELINK_MASK;
+ 
     // Setup control and status register
 
 //
@@ -113,6 +129,9 @@
         
     // Number of bytes to be transfered in each service request of the channel
     DMA_TCD2_NBYTES_MLNO = 0x02;
+    //DMA_TCD2_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x00) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
+    //DMA_TCD1_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(0x02) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02);
+
         
     // Major iteration count
     //DMA_TCD2_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
@@ -121,27 +140,26 @@
     // Adjustment value used to restore the source and destiny address to the initial value
     // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
     
-    DMA_TCD2_SLAST = -len*2;      // Source address adjustment
+    DMA_TCD2_SLAST = -len*2*2;      // Source address adjustment
     DMA_TCD2_DLASTSGA = 0;  // Destination address adjustment
 
-    DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(40); // ADC0 Source
+    DMAMUX_CHCFG2 |= DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_SOURCE(48); // ADC0 Source
 
-    DMA_TCD2_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(0) | DMA_BITER_ELINKYES_BITER(len);
-    DMA_TCD2_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(0) | DMA_CITER_ELINKYES_CITER(len);
-
-    DMA_TCD2_CSR = 0;
+    DMA_TCD2_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(0) | DMA_BITER_ELINKYES_BITER(len*2);
+    DMA_TCD2_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(0) | DMA_CITER_ELINKYES_CITER(len*2);
+    DMA_TCD2_CSR |= DMA_CSR_MAJORLINKCH(0) | DMA_CSR_MAJORELINK_MASK;
+    
 //
 // Now set up static dataset linking once the ADC samples are recorded
 //
     // DMA Channels 4 and 5 now will be enabled
     DMA_ERQ |= DMA_ERQ_ERQ4_MASK | DMA_ERQ_ERQ5_MASK;
-    DMA_TCD1_CSR |= DMA_CSR_MAJORLINKCH(4) | DMA_CSR_MAJORELINK_MASK;
 
     // Set memory address for source and destination for DMA4 and DMA5
-    DMA_TCD4_SADDR = (uint32_t) sample_array0;
-    DMA_TCD4_DADDR = (uint32_t) static_input_array0;
-    DMA_TCD5_SADDR = (uint32_t) sample_array1;
-    DMA_TCD5_DADDR = (uint32_t) static_input_array1;
+    DMA_TCD4_SADDR = (uint32_t) &sample_array0;
+    DMA_TCD4_DADDR = (uint32_t) &static_input_array0;
+    DMA_TCD5_SADDR = (uint32_t) &sample_array1;
+    DMA_TCD5_DADDR = (uint32_t) &static_input_array1;
     
     // Set an offset for source and destination address
     DMA_TCD4_SOFF = 0x02; // Source address offset of 2 bits per transaction
@@ -153,29 +171,23 @@
     DMA_TCD4_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
     DMA_TCD5_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
         
-    // Number of bytes to be transfered in each service request of the channel
-    //DMA_TCD4_NBYTES_MLNO = 0x02 * TOTAL_SAMPLES;
-    //DMA_TCD5_NBYTES_MLNO = 0x02 * TOTAL_SAMPLES;
-    DMA_TCD4_NBYTES_MLNO = 0x02 * len; 
-    DMA_TCD5_NBYTES_MLNO = 0x02 * len; 
-        
-    // Current major iteration count
-    DMA_TCD4_CITER_ELINKNO = 0x01;
-    DMA_TCD4_BITER_ELINKNO = 0x01;
-    DMA_TCD5_CITER_ELINKNO = 0x01;
-    DMA_TCD5_BITER_ELINKNO = 0x01;
+    DMA_TCD4_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
+    DMA_TCD5_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
     
-    // Adjustment value used to restore the source and destiny address to the initial value
-    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
-    
-    DMA_TCD4_SLAST = -len*2;      // Source address adjustment
+    DMA_TCD4_SLAST = -len*2*2;      // Source address adjustment
     DMA_TCD4_DLASTSGA = -len*2;  // Destination address adjustment
-    DMA_TCD5_SLAST = -len*2;      // Source address adjustment
+    //DMA_TCD4_DLASTSGA = 0;  // Destination address adjustment
+    DMA_TCD5_SLAST = -len*2*2;      // Source address adjustment
     DMA_TCD5_DLASTSGA = -len*2;  // Destination address adjustment
+    //DMA_TCD5_DLASTSGA = 0;  // Destination address adjustment
 
-    DMA_TCD4_CSR = 0;
-    DMA_TCD4_CSR |= DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
-    DMA_TCD5_CSR = 0;
+    //DMA_TCD4_CSR |= DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
+    DMA_TCD4_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(5) | DMA_BITER_ELINKYES_BITER(2);
+    DMA_TCD4_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(5) | DMA_CITER_ELINKYES_CITER(2);
+    DMA_TCD4_CSR = DMA_CSR_MAJORLINKCH(5) | DMA_CSR_MAJORELINK_MASK;
+    DMA_TCD5_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(6) | DMA_BITER_ELINKYES_BITER(2);
+    DMA_TCD5_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(6) | DMA_CITER_ELINKYES_CITER(2);
+    DMA_TCD5_CSR = DMA_CSR_MAJORLINKCH(6) | DMA_CSR_MAJORELINK_MASK;
 
 //
 // Now set up linking from static DAC to memory for output through DMA
@@ -183,7 +195,6 @@
     // DMA Channel 6 will be enabled
 
     DMA_ERQ |= DMA_ERQ_ERQ6_MASK;
-    DMA_TCD5_CSR |= DMA_CSR_MAJORLINKCH(6) | DMA_CSR_MAJORELINK_MASK;
 
     // Set memory address for source and destination for DMA6
     DMA_TCD6_SADDR = (uint32_t) static_output_array0;
@@ -197,32 +208,28 @@
     DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
     DMA_TCD6_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
         
-    // Number of bytes to be transfered in each service request of the channel
-    DMA_TCD6_NBYTES_MLNO = 0x02 * len; 
-        
-    // Current major iteration count
-    DMA_TCD6_CITER_ELINKNO = 0x01;
-    DMA_TCD6_BITER_ELINKNO = 0x01;
     
-    // Adjustment value used to restore the source and destiny address to the initial value
-    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
+    DMA_TCD6_NBYTES_MLOFFYES = DMA_NBYTES_MLOFFYES_MLOFF(-len*2) | DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_NBYTES(0x02*len);
     
     DMA_TCD6_SLAST = -len*2;      // Source address adjustment
-    DMA_TCD6_DLASTSGA = -len*2;  // Destination address adjustment
+    //DMA_TCD6_SLAST = 0;      // Source address adjustment
+    DMA_TCD6_DLASTSGA = -len*2*2;  // Destination address adjustment
 
-    DMA_TCD6_CSR = 0;
-    
+    DMA_TCD6_BITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_BITER_ELINKYES_LINKCH(9) | DMA_BITER_ELINKYES_BITER(2);
+    DMA_TCD6_CITER_ELINKYES = DMA_CITER_ELINKYES_ELINK_MASK | DMA_CITER_ELINKYES_LINKCH(9) | DMA_CITER_ELINKYES_CITER(2);
+
+    DMA_TCD6_CSR |= DMA_CSR_MAJORLINKCH(9) | DMA_CSR_MAJORELINK_MASK;    
+   
 //
-// Provide status
+// Provide control for intermediate loops
 //    
 
     // DMA Channel 8
     DMA_ERQ |= DMA_ERQ_ERQ8_MASK;
-    DMA_TCD6_CSR |= DMA_CSR_MAJORLINKCH(8) | DMA_CSR_MAJORELINK_MASK;
     
     // Set memory address for source and destiantion for DMA 8
-    DMA_TCD8_SADDR = (uint32_t) &sampling_status_done;
-    DMA_TCD8_DADDR = (uint32_t) &sampling_status;
+    DMA_TCD8_SADDR = (uint32_t) &intermediate_status_done;
+    DMA_TCD8_DADDR = (uint32_t) &intermediate_status;
     
     // Set an offset for source and destination address
     DMA_TCD8_SOFF = 0x00; // Source address offset of 2 bits per transaction
@@ -236,17 +243,44 @@
     DMA_TCD8_NBYTES_MLNO = 0x02; 
         
     // Current major iteration count
-    DMA_TCD8_CITER_ELINKNO = 0x01;
-    DMA_TCD8_BITER_ELINKNO = 0x01;
-    
-    // Adjustment value used to restore the source and destiny address to the initial value
-    // After reading 'len' number of times, the DMA goes back to the beginning by subtracting len*2 from the address (going back to the original address)
-    
+    DMA_TCD8_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    DMA_TCD8_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+      
     DMA_TCD8_SLAST = 0;      // Source address adjustment
     DMA_TCD8_DLASTSGA = 0;  // Destination address adjustment
+   
+    DMA_TCD8_CSR |= DMA_CSR_MAJORLINKCH(4) | DMA_CSR_MAJORELINK_MASK;
 
-    DMA_TCD8_CSR = 0;
+//
+//  Provide status
+//   
+
+    // DMA Channel 9
+    DMA_ERQ |= DMA_ERQ_ERQ9_MASK;
+    
+    // Set memory address for source and destiantion for DMA 8
+    DMA_TCD9_SADDR = (uint32_t) &sampling_status_done;
+    DMA_TCD9_DADDR = (uint32_t) &sampling_status;
     
+    // Set an offset for source and destination address
+    DMA_TCD9_SOFF = 0x00; // Source address offset of 2 bits per transaction
+    DMA_TCD9_DOFF = 0x00; // Destination address offset of 1 bit per transaction
+        
+    // Set source and destination data transfer size
+    DMA_TCD9_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
+    DMA_TCD9_ATTR = DMA_ATTR_SSIZE(1) | DMA_ATTR_DSIZE(1);
+        
+    // Number of bytes to be transfered in each service request of the channel
+    DMA_TCD9_NBYTES_MLNO = 0x02; 
+        
+    // Current major iteration count
+    DMA_TCD9_CITER_ELINKNO = DMA_CITER_ELINKNO_CITER(len);
+    DMA_TCD9_BITER_ELINKNO = DMA_BITER_ELINKNO_BITER(len);
+    
+    DMA_TCD9_SLAST = 0;      // Source address adjustment
+    DMA_TCD9_DLASTSGA = 0;  // Destination address adjustment
+   
+  
 }
 
 void dma_reset() {