Dual CANbus monitor and instrumentation cluster. Presently tuned for the Nissan Leaf EV.

Dependencies:   SPI_TFTx2_ILI9341 TFT_fonts TOUCH_TFTx2_ILI9341 mbed

Fork of CANary_corrupt by Tick Tock

After adding the LPC1768 platform, import as a program and do not select the "update to latest revision" box

User Guide

Eagle Schematic and Board design

/media/uploads/TickTock/canaryr6.zip

/media/uploads/TickTock/canary_sch.jpg

/media/uploads/TickTock/canaryr6brd.jpg

For LCD Rev 1.01:

/media/uploads/TickTock/lcdsch.jpg

For VCD Rev 2.00:

/media/uploads/TickTock/lcdr2.jpg

Parts List

qtyinstancepart #packagesupplierDescription
1BAT3Vhttp://www.ebay.com/itm/10x-CR2032-SMD-Battery-Holder-for-CR2032-Battery-/180938057979?pt=LH_DefaultDomain_0&hash=item2a20bfa8fbLithium 2032 coin battery holder
4C1-C4ECST1DC106R6032Tantalium capacitor 10uF
3FC1-FC3ZF1-20-01-T-WThttp://www.samtec.com/cable-systems/idc-ffc/ffc/zero-insertion.aspx20 conductor 1mm pitch flex cable connector (optional)
1FJ-20-R-08.00-4http://www.samtec.com/cable-systems/idc-ffc/ffc/zero-insertion.aspx8\" 20 conductor 1mm pitch flex connector, end reversed (optional)
2H1-H4(DON'T populate H1-H4 headers - solder mbed directly)
1H5http://www.ebay.com/itm/221186042943?ssPageName=STRK:MEWNX:IT&_trksid=p3984.m1497.l26491x12 .1\" pitch header (optional)
1H62x6 .1\" pitch header (optional)
2IC1,IC2VP230LMDSOP8http://www.ebay.com/itm/130488665247?ssPageName=STRK:MEWNX:IT&_trksid=p3984.m1497.l2649canbus transciever
1IC3LM1117-5VSOT2235V regulator
5JP*2 pin .1\" jumper header
1mbedLPC1768http://www.ebay.com/itm/200830573509?ssPageName=STRK:MEWNX:IT&_trksid=p3984.m1497.l2649mbed uC
2Q1,Q22N2222SOT23General purpose NPN transistor
1R1R393M120639K resistor
1R2R103M120610K resistor
4R4-R6R102M12061K resistor
1R3R500M120650 Ohm resistor
2TR1-TR5ZJYS81R5-2PL51TG01http://www.digikey.com/product-detail/en/ZJYS81R5-2PL51T-G01/445-2223-1-ND/765232CM Choke
1Z11N5340BGC1702-15http://www.ebay.com/itm/150878122425?ssPageName=STRK:MEWNX:IT&_trksid=p3984.m1497.l26496V, 5W Zener Diode
1Z1DC-DC conveterhttp://www.ebay.com/itm/251142727849?ssPageName=STRK:MEWNX:IT&_trksid=p3984.m1497.l264912V-7V, 3W DC-DC converter
1X1USBhttp://www.ebay.com/itm/New-Vertical-USB-2-0-A-pcb-connector-socket-USB-A-Type-/300553895292?pt=LH_DefaultDomain_0&hash=item45fa687d7cvertical USB connector
2LCD0,LCD1TFThttp://www.mikroe.com/add-on-boards/display/tft-proto/320x240 LCD with touch screen
1E0Enclosurehttp://www.shapeways.com/model/1077799/canary.html?li=user-profile&materialId=63d printed enclosure

Assembly

1) LCD Displays

I found ribbon cable is a nice way to organize the wires to the displays. There are two versions of the display and each must be wired differently. The original project used HW REV. 1.01. For that version, you'll need 12 conductors and I connected them in the following order:

1LED+
2LED-
3RST
4SDI
5WR/SCLK
6CS
7X+
8X-
9Y+
10Y-
11VDD
12GND

If, instead, you have HW REV 2.0, you will need 13 conductors with the following order:

1LED+
2LED-
3RST
4SDI
5RS (SCLK)
6WR (DC)
7CS
8X+
9X-
10Y+
11Y-
12VDD
13GND

First I connected all the GND connections (2 GND & IM0, IM1, IM3 for REV1.01 or 2 GND, RD, & IM0 for REV2.00). Do not connect the bottom GND until you have the ribbon cable connected. After making all the ribbon cable connections (connecting the GND of the ribbon cable to the bottom GND pad), solder the GND bar from the previous step to the back of the bottom GND connection. Finally, make a connection from the back side 3.3V pin to IM2 for REV1.01 or to IM1,IM2,&IM3 for REV2.00. Take a break and repeat for the second display.

Examples of REV1.01 boards:

/media/uploads/TickTock/lcdtop.jpg /media/uploads/TickTock/lcdbot.jpg

Examples of REV2.00:

/media/uploads/TickTock/rev2front.jpg /media/uploads/TickTock/rev2back.jpg

Once the two displays are complete combine all wires except CS0, CS1, X+, X-, Y+, and Y-. Connect X- of the left display to X+ of the right. Similarly connect Y- of the left display to Y+ of the right. Insulate any exposed wires.

2) PCB

Refer to the schematics to place all the components on the board. If you plan to install into the CANary 3D enclosure, DO NOT install the battery holder or the socket for the mbed and, instead, connect two wires to the VB and GND pads nearby. You will have to install the battery holder against the back wall to avoid interfering with the right-hand display and the mbed will have to be directly soldered. I have not found a socket with a low enough profile to fit in the space provided (depth of enclosure is limited by the space behind the center console). Also, I recommend keeping as much lead as possible on the Zener diode (bending it as shown to clear the back wall). Although it is operating well within parameters, the Zener gets quite hot during extended operation and the leads help dissipate the heat and keep it away from the PCB and other components.Update: Several Zeners have failed resulting in damage to some users boards so I recommend using a DC-DC converter instead to bring the 12V down to 7V.

/media/uploads/TickTock/pcbtop.jpg /media/uploads/TickTock/pcbbot.jpg

Once the PCB is populated, solder the LCDs to the PCB. CS0 connects to the right display and CS1 connects to the left. /media/uploads/TickTock/brddis.jpg

Update: The Zener diodes tended to fail after a few months so I am recommending removing them and replacing with a DC-DC converter. This will run cooler and waste less energy, too. To install, remove the left display panel to gain access to the Zener. From there, the Zener can be removed and it's pads used to connect to the DC-DC converter. I recommend setting the output voltage on the bench before installing since the trim pot is tricky to reach once installed. Set it to 7V. The input can be connected to the left pad previously occupied by the zener and the output can connect to the right. GND(-) can be connected to the bottom right pad on the 2x6 header below the flex cable connector. Make sure the GND wire lies flat so it doesn't interfere with the connection of the flex cable. /media/uploads/TickTock/dcdcinst2.jpg

Once soldered in place, the DC-DC converter can easily be mounted to the back wall with double sided tape above the battery holder. /media/uploads/TickTock/dcdcinst3.jpg

3) Testing

1)First step is to buzz out all connections from the LCDs to the pins in the main board
2)Next check the touch screen connections. On the main board, place an Ohm meter across X+ and X-. You should read 700 Ohms. Repeat for Y+ and Y-. Then test the resistance from X+ to Y+. With nothing touching the screens, it should read >100K Ohms and <1K when touching either screen.
3)When all connections are checked, solder in the mbed. Download and install the touch2 program http://mbed.org/users/TickTock/code/touch2/ to test the basic operation of the mbed and touch screens.
tips:
Touch screen is sensitive - excess flux on X+,X-,Y+,Y- connection on mbed can result in flakey operation
If touch is not working, double-check the LCD0_CS and LCD1_CS are not swapped. LCD0_CS must connect to the CS of the LCD that has X- & Y- connected to the mbed. LCD1_CS must connect to the CS of the LCD that has X+ & Y+ connected to the mbed.
4)Once touch2 works, it is time to connect to the OBD connector. I highly recommend double checking all connections from the OBD to the PCB with the cable in place before connecting to the Leaf. Buzz out all the pins in the OBS to make sure none are shorting to each other, Check that the 12V goes to the Zener (and nothing else) and the switched 12V to the resistor divider (and nothing else). Test the ground connection properly connects to ground and nothing else.
5)Once you are confident there are no shorts or wrong connections from the OBD connector, take a deep breath and plug it into your leaf. Touch2 program should come up and function. Unplug and install the latest CANary firmware. If you have the REV2.00 LCD boards, you will need to edit the precompile.h file in the TOUCH_TFTx2_w9341 library and set USE_ILI9341 to 1. Test all features before installing into the enclosure (gids, cellpair, menu system, logging) since installing and removing from the enclosure is a PITA.

/media/uploads/TickTock/pcbdone.jpg /media/uploads/TickTock/functioning.jpg

4) Enclosure

The 3D printer leaves a lot of powder behind - I used a strong spray of water to get it out of all the cracks. The enclosure comes with a rather rough finish. I recommend convincing yourself you like it, then simply lightly sand then paint before assembly. Sanding is very difficult - the nylon is very nicely fused and doesn't want to sand. I tried sandblasting and that didn't work either. I had some limited success with filler and then sanding, but only on the outside - it is too difficult to sand the face. /media/uploads/TickTock/enclosure.jpg

5) Final Assembly

Make sure you are well rested with lots of patience before attempting assembly. It is a puzzle figuring out how to get both displays and the PCB in place. Enclosure was too expensive for me to keep iterating to optimize for assembly. I ended up snipping the thin display posts shorter and using various tools to push the displays into place. Also, some USB connectors are taller than others. If you have one of the taller ones, you will have to deflect the back wall a bit while inserting the PCB (being careful not to bend the housing) to get it to it's opening in the back wall. Do use a screw in the provided post to secure the PCB as USB insertion will otherwise dislodge it.

I added an additional safety line which wraps around the center post to prevent the enclosure from becoming a projectile in the event of an accident. /media/uploads/TickTock/safety.jpg Installed: /media/uploads/TickTock/installed.jpg

Committer:
TickTock
Date:
Wed Jul 01 22:21:52 2015 +0000
Revision:
208:bfb6b68d1677
Parent:
4:8d7759f4fe7a
Added option to auto delete logs older that a configurable number of days.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
TickTock 4:8d7759f4fe7a 1 /* mbed PowerControl Library
TickTock 4:8d7759f4fe7a 2 * Copyright (c) 2010 Michael Wei
TickTock 4:8d7759f4fe7a 3 */
TickTock 4:8d7759f4fe7a 4
TickTock 4:8d7759f4fe7a 5 #ifndef MBED_POWERCONTROL_ETH_H
TickTock 4:8d7759f4fe7a 6 #define MBED_POWERCONTROL_ETH_H
TickTock 4:8d7759f4fe7a 7
TickTock 4:8d7759f4fe7a 8 #include "mbed.h"
TickTock 4:8d7759f4fe7a 9 #include "PowerControl.h"
TickTock 4:8d7759f4fe7a 10
TickTock 4:8d7759f4fe7a 11 #define PHY_REG_BMCR_POWERDOWN 0xB
TickTock 4:8d7759f4fe7a 12 #define PHY_REG_EDCR_ENABLE 0xF
TickTock 4:8d7759f4fe7a 13
TickTock 4:8d7759f4fe7a 14
TickTock 4:8d7759f4fe7a 15 void EMAC_Init();
TickTock 4:8d7759f4fe7a 16 static unsigned short read_PHY (unsigned int PhyReg);
TickTock 4:8d7759f4fe7a 17 static void write_PHY (unsigned int PhyReg, unsigned short Value);
TickTock 4:8d7759f4fe7a 18
TickTock 4:8d7759f4fe7a 19 void PHY_PowerDown(void);
TickTock 4:8d7759f4fe7a 20 void PHY_PowerUp(void);
TickTock 4:8d7759f4fe7a 21 void PHY_EnergyDetect_Enable(void);
TickTock 4:8d7759f4fe7a 22 void PHY_EnergyDetect_Disable(void);
TickTock 4:8d7759f4fe7a 23
TickTock 4:8d7759f4fe7a 24 //From NXP Sample Code .... Probably from KEIL sample code
TickTock 4:8d7759f4fe7a 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
TickTock 4:8d7759f4fe7a 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
TickTock 4:8d7759f4fe7a 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
TickTock 4:8d7759f4fe7a 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
TickTock 4:8d7759f4fe7a 29
TickTock 4:8d7759f4fe7a 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
TickTock 4:8d7759f4fe7a 31
TickTock 4:8d7759f4fe7a 32 /* EMAC variables located in 16K Ethernet SRAM */
TickTock 4:8d7759f4fe7a 33 #define RX_DESC_BASE 0x20080000
TickTock 4:8d7759f4fe7a 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
TickTock 4:8d7759f4fe7a 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
TickTock 4:8d7759f4fe7a 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
TickTock 4:8d7759f4fe7a 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
TickTock 4:8d7759f4fe7a 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
TickTock 4:8d7759f4fe7a 39
TickTock 4:8d7759f4fe7a 40 /* RX and TX descriptor and status definitions. */
TickTock 4:8d7759f4fe7a 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
TickTock 4:8d7759f4fe7a 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
TickTock 4:8d7759f4fe7a 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
TickTock 4:8d7759f4fe7a 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
TickTock 4:8d7759f4fe7a 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
TickTock 4:8d7759f4fe7a 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
TickTock 4:8d7759f4fe7a 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
TickTock 4:8d7759f4fe7a 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
TickTock 4:8d7759f4fe7a 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
TickTock 4:8d7759f4fe7a 50
TickTock 4:8d7759f4fe7a 51 /* MAC Configuration Register 1 */
TickTock 4:8d7759f4fe7a 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
TickTock 4:8d7759f4fe7a 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
TickTock 4:8d7759f4fe7a 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
TickTock 4:8d7759f4fe7a 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
TickTock 4:8d7759f4fe7a 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
TickTock 4:8d7759f4fe7a 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
TickTock 4:8d7759f4fe7a 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
TickTock 4:8d7759f4fe7a 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
TickTock 4:8d7759f4fe7a 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
TickTock 4:8d7759f4fe7a 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
TickTock 4:8d7759f4fe7a 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
TickTock 4:8d7759f4fe7a 63
TickTock 4:8d7759f4fe7a 64 /* MAC Configuration Register 2 */
TickTock 4:8d7759f4fe7a 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
TickTock 4:8d7759f4fe7a 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
TickTock 4:8d7759f4fe7a 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
TickTock 4:8d7759f4fe7a 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
TickTock 4:8d7759f4fe7a 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
TickTock 4:8d7759f4fe7a 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
TickTock 4:8d7759f4fe7a 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
TickTock 4:8d7759f4fe7a 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
TickTock 4:8d7759f4fe7a 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
TickTock 4:8d7759f4fe7a 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
TickTock 4:8d7759f4fe7a 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
TickTock 4:8d7759f4fe7a 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
TickTock 4:8d7759f4fe7a 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
TickTock 4:8d7759f4fe7a 78
TickTock 4:8d7759f4fe7a 79 /* Back-to-Back Inter-Packet-Gap Register */
TickTock 4:8d7759f4fe7a 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
TickTock 4:8d7759f4fe7a 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
TickTock 4:8d7759f4fe7a 82
TickTock 4:8d7759f4fe7a 83 /* Non Back-to-Back Inter-Packet-Gap Register */
TickTock 4:8d7759f4fe7a 84 #define IPGR_DEF 0x00000012 /* Recommended value */
TickTock 4:8d7759f4fe7a 85
TickTock 4:8d7759f4fe7a 86 /* Collision Window/Retry Register */
TickTock 4:8d7759f4fe7a 87 #define CLRT_DEF 0x0000370F /* Default value */
TickTock 4:8d7759f4fe7a 88
TickTock 4:8d7759f4fe7a 89 /* PHY Support Register */
TickTock 4:8d7759f4fe7a 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
TickTock 4:8d7759f4fe7a 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
TickTock 4:8d7759f4fe7a 92
TickTock 4:8d7759f4fe7a 93 /* Test Register */
TickTock 4:8d7759f4fe7a 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
TickTock 4:8d7759f4fe7a 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
TickTock 4:8d7759f4fe7a 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
TickTock 4:8d7759f4fe7a 97
TickTock 4:8d7759f4fe7a 98 /* MII Management Configuration Register */
TickTock 4:8d7759f4fe7a 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
TickTock 4:8d7759f4fe7a 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
TickTock 4:8d7759f4fe7a 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
TickTock 4:8d7759f4fe7a 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
TickTock 4:8d7759f4fe7a 103
TickTock 4:8d7759f4fe7a 104 /* MII Management Command Register */
TickTock 4:8d7759f4fe7a 105 #define MCMD_READ 0x00000001 /* MII Read */
TickTock 4:8d7759f4fe7a 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
TickTock 4:8d7759f4fe7a 107
TickTock 4:8d7759f4fe7a 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
TickTock 4:8d7759f4fe7a 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
TickTock 4:8d7759f4fe7a 110
TickTock 4:8d7759f4fe7a 111 /* MII Management Address Register */
TickTock 4:8d7759f4fe7a 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
TickTock 4:8d7759f4fe7a 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
TickTock 4:8d7759f4fe7a 114
TickTock 4:8d7759f4fe7a 115 /* MII Management Indicators Register */
TickTock 4:8d7759f4fe7a 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
TickTock 4:8d7759f4fe7a 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
TickTock 4:8d7759f4fe7a 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
TickTock 4:8d7759f4fe7a 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
TickTock 4:8d7759f4fe7a 120
TickTock 4:8d7759f4fe7a 121 /* Command Register */
TickTock 4:8d7759f4fe7a 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
TickTock 4:8d7759f4fe7a 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
TickTock 4:8d7759f4fe7a 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
TickTock 4:8d7759f4fe7a 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
TickTock 4:8d7759f4fe7a 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
TickTock 4:8d7759f4fe7a 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
TickTock 4:8d7759f4fe7a 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
TickTock 4:8d7759f4fe7a 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
TickTock 4:8d7759f4fe7a 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
TickTock 4:8d7759f4fe7a 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
TickTock 4:8d7759f4fe7a 132
TickTock 4:8d7759f4fe7a 133 /* Status Register */
TickTock 4:8d7759f4fe7a 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
TickTock 4:8d7759f4fe7a 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
TickTock 4:8d7759f4fe7a 136
TickTock 4:8d7759f4fe7a 137 /* Transmit Status Vector 0 Register */
TickTock 4:8d7759f4fe7a 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
TickTock 4:8d7759f4fe7a 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
TickTock 4:8d7759f4fe7a 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
TickTock 4:8d7759f4fe7a 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
TickTock 4:8d7759f4fe7a 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
TickTock 4:8d7759f4fe7a 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
TickTock 4:8d7759f4fe7a 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
TickTock 4:8d7759f4fe7a 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
TickTock 4:8d7759f4fe7a 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
TickTock 4:8d7759f4fe7a 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
TickTock 4:8d7759f4fe7a 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
TickTock 4:8d7759f4fe7a 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
TickTock 4:8d7759f4fe7a 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
TickTock 4:8d7759f4fe7a 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
TickTock 4:8d7759f4fe7a 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
TickTock 4:8d7759f4fe7a 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
TickTock 4:8d7759f4fe7a 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
TickTock 4:8d7759f4fe7a 155
TickTock 4:8d7759f4fe7a 156 /* Transmit Status Vector 1 Register */
TickTock 4:8d7759f4fe7a 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
TickTock 4:8d7759f4fe7a 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
TickTock 4:8d7759f4fe7a 159
TickTock 4:8d7759f4fe7a 160 /* Receive Status Vector Register */
TickTock 4:8d7759f4fe7a 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
TickTock 4:8d7759f4fe7a 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
TickTock 4:8d7759f4fe7a 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
TickTock 4:8d7759f4fe7a 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
TickTock 4:8d7759f4fe7a 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
TickTock 4:8d7759f4fe7a 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
TickTock 4:8d7759f4fe7a 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
TickTock 4:8d7759f4fe7a 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
TickTock 4:8d7759f4fe7a 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
TickTock 4:8d7759f4fe7a 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
TickTock 4:8d7759f4fe7a 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
TickTock 4:8d7759f4fe7a 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
TickTock 4:8d7759f4fe7a 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
TickTock 4:8d7759f4fe7a 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
TickTock 4:8d7759f4fe7a 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
TickTock 4:8d7759f4fe7a 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
TickTock 4:8d7759f4fe7a 177
TickTock 4:8d7759f4fe7a 178 /* Flow Control Counter Register */
TickTock 4:8d7759f4fe7a 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
TickTock 4:8d7759f4fe7a 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
TickTock 4:8d7759f4fe7a 181
TickTock 4:8d7759f4fe7a 182 /* Flow Control Status Register */
TickTock 4:8d7759f4fe7a 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
TickTock 4:8d7759f4fe7a 184
TickTock 4:8d7759f4fe7a 185 /* Receive Filter Control Register */
TickTock 4:8d7759f4fe7a 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
TickTock 4:8d7759f4fe7a 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
TickTock 4:8d7759f4fe7a 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
TickTock 4:8d7759f4fe7a 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
TickTock 4:8d7759f4fe7a 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
TickTock 4:8d7759f4fe7a 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
TickTock 4:8d7759f4fe7a 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
TickTock 4:8d7759f4fe7a 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
TickTock 4:8d7759f4fe7a 194
TickTock 4:8d7759f4fe7a 195 /* Receive Filter WoL Status/Clear Registers */
TickTock 4:8d7759f4fe7a 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
TickTock 4:8d7759f4fe7a 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
TickTock 4:8d7759f4fe7a 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
TickTock 4:8d7759f4fe7a 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
TickTock 4:8d7759f4fe7a 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
TickTock 4:8d7759f4fe7a 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
TickTock 4:8d7759f4fe7a 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
TickTock 4:8d7759f4fe7a 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
TickTock 4:8d7759f4fe7a 204
TickTock 4:8d7759f4fe7a 205 /* Interrupt Status/Enable/Clear/Set Registers */
TickTock 4:8d7759f4fe7a 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
TickTock 4:8d7759f4fe7a 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
TickTock 4:8d7759f4fe7a 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
TickTock 4:8d7759f4fe7a 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
TickTock 4:8d7759f4fe7a 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
TickTock 4:8d7759f4fe7a 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
TickTock 4:8d7759f4fe7a 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
TickTock 4:8d7759f4fe7a 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
TickTock 4:8d7759f4fe7a 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
TickTock 4:8d7759f4fe7a 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
TickTock 4:8d7759f4fe7a 216
TickTock 4:8d7759f4fe7a 217 /* Power Down Register */
TickTock 4:8d7759f4fe7a 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
TickTock 4:8d7759f4fe7a 219
TickTock 4:8d7759f4fe7a 220 /* RX Descriptor Control Word */
TickTock 4:8d7759f4fe7a 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
TickTock 4:8d7759f4fe7a 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
TickTock 4:8d7759f4fe7a 223
TickTock 4:8d7759f4fe7a 224 /* RX Status Hash CRC Word */
TickTock 4:8d7759f4fe7a 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
TickTock 4:8d7759f4fe7a 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
TickTock 4:8d7759f4fe7a 227
TickTock 4:8d7759f4fe7a 228 /* RX Status Information Word */
TickTock 4:8d7759f4fe7a 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
TickTock 4:8d7759f4fe7a 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
TickTock 4:8d7759f4fe7a 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
TickTock 4:8d7759f4fe7a 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
TickTock 4:8d7759f4fe7a 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
TickTock 4:8d7759f4fe7a 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
TickTock 4:8d7759f4fe7a 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
TickTock 4:8d7759f4fe7a 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
TickTock 4:8d7759f4fe7a 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
TickTock 4:8d7759f4fe7a 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
TickTock 4:8d7759f4fe7a 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
TickTock 4:8d7759f4fe7a 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
TickTock 4:8d7759f4fe7a 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
TickTock 4:8d7759f4fe7a 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
TickTock 4:8d7759f4fe7a 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
TickTock 4:8d7759f4fe7a 244
TickTock 4:8d7759f4fe7a 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
TickTock 4:8d7759f4fe7a 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
TickTock 4:8d7759f4fe7a 247
TickTock 4:8d7759f4fe7a 248 /* TX Descriptor Control Word */
TickTock 4:8d7759f4fe7a 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
TickTock 4:8d7759f4fe7a 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
TickTock 4:8d7759f4fe7a 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
TickTock 4:8d7759f4fe7a 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
TickTock 4:8d7759f4fe7a 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
TickTock 4:8d7759f4fe7a 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
TickTock 4:8d7759f4fe7a 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
TickTock 4:8d7759f4fe7a 256
TickTock 4:8d7759f4fe7a 257 /* TX Status Information Word */
TickTock 4:8d7759f4fe7a 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
TickTock 4:8d7759f4fe7a 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
TickTock 4:8d7759f4fe7a 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
TickTock 4:8d7759f4fe7a 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
TickTock 4:8d7759f4fe7a 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
TickTock 4:8d7759f4fe7a 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
TickTock 4:8d7759f4fe7a 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
TickTock 4:8d7759f4fe7a 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
TickTock 4:8d7759f4fe7a 266
TickTock 4:8d7759f4fe7a 267 /* DP83848C PHY Registers */
TickTock 4:8d7759f4fe7a 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
TickTock 4:8d7759f4fe7a 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
TickTock 4:8d7759f4fe7a 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
TickTock 4:8d7759f4fe7a 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
TickTock 4:8d7759f4fe7a 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
TickTock 4:8d7759f4fe7a 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
TickTock 4:8d7759f4fe7a 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
TickTock 4:8d7759f4fe7a 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
TickTock 4:8d7759f4fe7a 276
TickTock 4:8d7759f4fe7a 277 /* PHY Extended Registers */
TickTock 4:8d7759f4fe7a 278 #define PHY_REG_STS 0x10 /* Status Register */
TickTock 4:8d7759f4fe7a 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
TickTock 4:8d7759f4fe7a 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
TickTock 4:8d7759f4fe7a 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
TickTock 4:8d7759f4fe7a 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
TickTock 4:8d7759f4fe7a 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
TickTock 4:8d7759f4fe7a 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
TickTock 4:8d7759f4fe7a 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
TickTock 4:8d7759f4fe7a 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
TickTock 4:8d7759f4fe7a 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
TickTock 4:8d7759f4fe7a 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
TickTock 4:8d7759f4fe7a 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
TickTock 4:8d7759f4fe7a 290
TickTock 4:8d7759f4fe7a 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
TickTock 4:8d7759f4fe7a 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
TickTock 4:8d7759f4fe7a 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
TickTock 4:8d7759f4fe7a 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
TickTock 4:8d7759f4fe7a 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
TickTock 4:8d7759f4fe7a 296
TickTock 4:8d7759f4fe7a 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
TickTock 4:8d7759f4fe7a 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
TickTock 4:8d7759f4fe7a 299 #endif