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mbed-src-I2CWaitFix
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MKL25Z4.h
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00001 /* 00002 ** ################################################################### 00003 ** Processor: MKL25Z128VLK4 00004 ** Compilers: ARM Compiler 00005 ** Freescale C/C++ for Embedded ARM 00006 ** GNU C Compiler 00007 ** IAR ANSI C/C++ Compiler for ARM 00008 ** 00009 ** Reference manual: KL25RM, Rev.1, Jun 2012 00010 ** Version: rev. 1.1, 2012-06-21 00011 ** 00012 ** Abstract: 00013 ** CMSIS Peripheral Access Layer for MKL25Z4 00014 ** 00015 ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. 00016 ** 00017 ** http: www.freescale.com 00018 ** mail: support@freescale.com 00019 ** 00020 ** Revisions: 00021 ** - rev. 1.0 (2012-06-13) 00022 ** Initial version. 00023 ** - rev. 1.1 (2012-06-21) 00024 ** Update according to reference manual rev. 1. 00025 ** 00026 ** ################################################################### 00027 */ 00028 00029 /** 00030 * @file MKL25Z4.h 00031 * @version 1.1 00032 * @date 2012-06-21 00033 * @brief CMSIS Peripheral Access Layer for MKL25Z4 00034 * 00035 * CMSIS Peripheral Access Layer for MKL25Z4 00036 */ 00037 00038 #if !defined(MKL25Z4_H_) 00039 #define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */ 00040 00041 /** Memory map major version (memory maps with equal major version number are 00042 * compatible) */ 00043 #define MCU_MEM_MAP_VERSION 0x0100u 00044 /** Memory map minor version */ 00045 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u 00046 00047 00048 /* ---------------------------------------------------------------------------- 00049 -- Interrupt vector numbers 00050 ---------------------------------------------------------------------------- */ 00051 00052 /** 00053 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 00054 * @{ 00055 */ 00056 00057 /** Interrupt Number Definitions */ 00058 typedef enum IRQn { 00059 /* Core interrupts */ 00060 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 00061 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 00062 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 00063 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 00064 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 00065 00066 /* Device specific interrupts */ 00067 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */ 00068 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */ 00069 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */ 00070 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */ 00071 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */ 00072 FTFA_IRQn = 5, /**< FTFA interrupt */ 00073 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */ 00074 LLW_IRQn = 7, /**< Low Leakage Wakeup */ 00075 I2C0_IRQn = 8, /**< I2C0 interrupt */ 00076 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */ 00077 SPI0_IRQn = 10, /**< SPI0 interrupt */ 00078 SPI1_IRQn = 11, /**< SPI1 interrupt */ 00079 UART0_IRQn = 12, /**< UART0 status/error interrupt */ 00080 UART1_IRQn = 13, /**< UART1 status/error interrupt */ 00081 UART2_IRQn = 14, /**< UART2 status/error interrupt */ 00082 ADC0_IRQn = 15, /**< ADC0 interrupt */ 00083 CMP0_IRQn = 16, /**< CMP0 interrupt */ 00084 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */ 00085 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */ 00086 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */ 00087 RTC_IRQn = 20, /**< RTC interrupt */ 00088 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */ 00089 PIT_IRQn = 22, /**< PIT timer interrupt */ 00090 Reserved39_IRQn = 23, /**< Reserved interrupt 39 */ 00091 USB0_IRQn = 24, /**< USB0 interrupt */ 00092 DAC0_IRQn = 25, /**< DAC interrupt */ 00093 TSI0_IRQn = 26, /**< TSI0 interrupt */ 00094 MCG_IRQn = 27, /**< MCG interrupt */ 00095 LPTimer_IRQn = 28, /**< LPTimer interrupt */ 00096 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */ 00097 PORTA_IRQn = 30, /**< Port A interrupt */ 00098 PORTD_IRQn = 31 /**< Port D interrupt */ 00099 } IRQn_Type ; 00100 00101 /** 00102 * @} 00103 */ /* end of group Interrupt_vector_numbers */ 00104 00105 00106 /* ---------------------------------------------------------------------------- 00107 -- Cortex M0 Core Configuration 00108 ---------------------------------------------------------------------------- */ 00109 00110 /** 00111 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 00112 * @{ 00113 */ 00114 00115 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 00116 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 00117 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ 00118 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 00119 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 00120 00121 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 00122 #include "system_MKL25Z4.h" /* Device specific configuration file */ 00123 00124 /** 00125 * @} 00126 */ /* end of group Cortex_Core_Configuration */ 00127 00128 00129 /* ---------------------------------------------------------------------------- 00130 -- Device Peripheral Access Layer 00131 ---------------------------------------------------------------------------- */ 00132 00133 /** 00134 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 00135 * @{ 00136 */ 00137 00138 00139 /* 00140 ** Start of section using anonymous unions 00141 */ 00142 00143 #if defined(__ARMCC_VERSION) 00144 #pragma push 00145 #pragma anon_unions 00146 #elif defined(__CWCC__) 00147 #pragma push 00148 #pragma cpp_extensions on 00149 #elif defined(__GNUC__) 00150 /* anonymous unions are enabled by default */ 00151 #elif defined(__IAR_SYSTEMS_ICC__) 00152 #pragma language=extended 00153 #else 00154 #error Not supported compiler type 00155 #endif 00156 00157 /* ---------------------------------------------------------------------------- 00158 -- ADC Peripheral Access Layer 00159 ---------------------------------------------------------------------------- */ 00160 00161 /** 00162 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 00163 * @{ 00164 */ 00165 00166 /** ADC - Register Layout Typedef */ 00167 typedef struct { 00168 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 00169 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 00170 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 00171 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 00172 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 00173 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 00174 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 00175 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 00176 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 00177 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 00178 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 00179 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 00180 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 00181 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 00182 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 00183 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 00184 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 00185 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 00186 uint8_t RESERVED_0[4]; 00187 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 00188 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 00189 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 00190 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 00191 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 00192 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 00193 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 00194 } ADC_Type; 00195 00196 /* ---------------------------------------------------------------------------- 00197 -- ADC Register Masks 00198 ---------------------------------------------------------------------------- */ 00199 00200 /** 00201 * @addtogroup ADC_Register_Masks ADC Register Masks 00202 * @{ 00203 */ 00204 00205 /* SC1 Bit Fields */ 00206 #define ADC_SC1_ADCH_MASK 0x1Fu 00207 #define ADC_SC1_ADCH_SHIFT 0 00208 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) 00209 #define ADC_SC1_DIFF_MASK 0x20u 00210 #define ADC_SC1_DIFF_SHIFT 5 00211 #define ADC_SC1_AIEN_MASK 0x40u 00212 #define ADC_SC1_AIEN_SHIFT 6 00213 #define ADC_SC1_COCO_MASK 0x80u 00214 #define ADC_SC1_COCO_SHIFT 7 00215 /* CFG1 Bit Fields */ 00216 #define ADC_CFG1_ADICLK_MASK 0x3u 00217 #define ADC_CFG1_ADICLK_SHIFT 0 00218 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) 00219 #define ADC_CFG1_MODE_MASK 0xCu 00220 #define ADC_CFG1_MODE_SHIFT 2 00221 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) 00222 #define ADC_CFG1_ADLSMP_MASK 0x10u 00223 #define ADC_CFG1_ADLSMP_SHIFT 4 00224 #define ADC_CFG1_ADIV_MASK 0x60u 00225 #define ADC_CFG1_ADIV_SHIFT 5 00226 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) 00227 #define ADC_CFG1_ADLPC_MASK 0x80u 00228 #define ADC_CFG1_ADLPC_SHIFT 7 00229 /* CFG2 Bit Fields */ 00230 #define ADC_CFG2_ADLSTS_MASK 0x3u 00231 #define ADC_CFG2_ADLSTS_SHIFT 0 00232 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) 00233 #define ADC_CFG2_ADHSC_MASK 0x4u 00234 #define ADC_CFG2_ADHSC_SHIFT 2 00235 #define ADC_CFG2_ADACKEN_MASK 0x8u 00236 #define ADC_CFG2_ADACKEN_SHIFT 3 00237 #define ADC_CFG2_MUXSEL_MASK 0x10u 00238 #define ADC_CFG2_MUXSEL_SHIFT 4 00239 /* R Bit Fields */ 00240 #define ADC_R_D_MASK 0xFFFFu 00241 #define ADC_R_D_SHIFT 0 00242 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) 00243 /* CV1 Bit Fields */ 00244 #define ADC_CV1_CV_MASK 0xFFFFu 00245 #define ADC_CV1_CV_SHIFT 0 00246 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) 00247 /* CV2 Bit Fields */ 00248 #define ADC_CV2_CV_MASK 0xFFFFu 00249 #define ADC_CV2_CV_SHIFT 0 00250 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) 00251 /* SC2 Bit Fields */ 00252 #define ADC_SC2_REFSEL_MASK 0x3u 00253 #define ADC_SC2_REFSEL_SHIFT 0 00254 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) 00255 #define ADC_SC2_DMAEN_MASK 0x4u 00256 #define ADC_SC2_DMAEN_SHIFT 2 00257 #define ADC_SC2_ACREN_MASK 0x8u 00258 #define ADC_SC2_ACREN_SHIFT 3 00259 #define ADC_SC2_ACFGT_MASK 0x10u 00260 #define ADC_SC2_ACFGT_SHIFT 4 00261 #define ADC_SC2_ACFE_MASK 0x20u 00262 #define ADC_SC2_ACFE_SHIFT 5 00263 #define ADC_SC2_ADTRG_MASK 0x40u 00264 #define ADC_SC2_ADTRG_SHIFT 6 00265 #define ADC_SC2_ADACT_MASK 0x80u 00266 #define ADC_SC2_ADACT_SHIFT 7 00267 /* SC3 Bit Fields */ 00268 #define ADC_SC3_AVGS_MASK 0x3u 00269 #define ADC_SC3_AVGS_SHIFT 0 00270 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) 00271 #define ADC_SC3_AVGE_MASK 0x4u 00272 #define ADC_SC3_AVGE_SHIFT 2 00273 #define ADC_SC3_ADCO_MASK 0x8u 00274 #define ADC_SC3_ADCO_SHIFT 3 00275 #define ADC_SC3_CALF_MASK 0x40u 00276 #define ADC_SC3_CALF_SHIFT 6 00277 #define ADC_SC3_CAL_MASK 0x80u 00278 #define ADC_SC3_CAL_SHIFT 7 00279 /* OFS Bit Fields */ 00280 #define ADC_OFS_OFS_MASK 0xFFFFu 00281 #define ADC_OFS_OFS_SHIFT 0 00282 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) 00283 /* PG Bit Fields */ 00284 #define ADC_PG_PG_MASK 0xFFFFu 00285 #define ADC_PG_PG_SHIFT 0 00286 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) 00287 /* MG Bit Fields */ 00288 #define ADC_MG_MG_MASK 0xFFFFu 00289 #define ADC_MG_MG_SHIFT 0 00290 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) 00291 /* CLPD Bit Fields */ 00292 #define ADC_CLPD_CLPD_MASK 0x3Fu 00293 #define ADC_CLPD_CLPD_SHIFT 0 00294 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) 00295 /* CLPS Bit Fields */ 00296 #define ADC_CLPS_CLPS_MASK 0x3Fu 00297 #define ADC_CLPS_CLPS_SHIFT 0 00298 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) 00299 /* CLP4 Bit Fields */ 00300 #define ADC_CLP4_CLP4_MASK 0x3FFu 00301 #define ADC_CLP4_CLP4_SHIFT 0 00302 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) 00303 /* CLP3 Bit Fields */ 00304 #define ADC_CLP3_CLP3_MASK 0x1FFu 00305 #define ADC_CLP3_CLP3_SHIFT 0 00306 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) 00307 /* CLP2 Bit Fields */ 00308 #define ADC_CLP2_CLP2_MASK 0xFFu 00309 #define ADC_CLP2_CLP2_SHIFT 0 00310 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) 00311 /* CLP1 Bit Fields */ 00312 #define ADC_CLP1_CLP1_MASK 0x7Fu 00313 #define ADC_CLP1_CLP1_SHIFT 0 00314 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) 00315 /* CLP0 Bit Fields */ 00316 #define ADC_CLP0_CLP0_MASK 0x3Fu 00317 #define ADC_CLP0_CLP0_SHIFT 0 00318 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) 00319 /* CLMD Bit Fields */ 00320 #define ADC_CLMD_CLMD_MASK 0x3Fu 00321 #define ADC_CLMD_CLMD_SHIFT 0 00322 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) 00323 /* CLMS Bit Fields */ 00324 #define ADC_CLMS_CLMS_MASK 0x3Fu 00325 #define ADC_CLMS_CLMS_SHIFT 0 00326 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) 00327 /* CLM4 Bit Fields */ 00328 #define ADC_CLM4_CLM4_MASK 0x3FFu 00329 #define ADC_CLM4_CLM4_SHIFT 0 00330 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) 00331 /* CLM3 Bit Fields */ 00332 #define ADC_CLM3_CLM3_MASK 0x1FFu 00333 #define ADC_CLM3_CLM3_SHIFT 0 00334 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) 00335 /* CLM2 Bit Fields */ 00336 #define ADC_CLM2_CLM2_MASK 0xFFu 00337 #define ADC_CLM2_CLM2_SHIFT 0 00338 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) 00339 /* CLM1 Bit Fields */ 00340 #define ADC_CLM1_CLM1_MASK 0x7Fu 00341 #define ADC_CLM1_CLM1_SHIFT 0 00342 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) 00343 /* CLM0 Bit Fields */ 00344 #define ADC_CLM0_CLM0_MASK 0x3Fu 00345 #define ADC_CLM0_CLM0_SHIFT 0 00346 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) 00347 00348 /** 00349 * @} 00350 */ /* end of group ADC_Register_Masks */ 00351 00352 00353 /* ADC - Peripheral instance base addresses */ 00354 /** Peripheral ADC0 base address */ 00355 #define ADC0_BASE (0x4003B000u) 00356 /** Peripheral ADC0 base pointer */ 00357 #define ADC0 ((ADC_Type *)ADC0_BASE) 00358 /** Array initializer of ADC peripheral base pointers */ 00359 #define ADC_BASES { ADC0 } 00360 00361 /** 00362 * @} 00363 */ /* end of group ADC_Peripheral_Access_Layer */ 00364 00365 00366 /* ---------------------------------------------------------------------------- 00367 -- CMP Peripheral Access Layer 00368 ---------------------------------------------------------------------------- */ 00369 00370 /** 00371 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 00372 * @{ 00373 */ 00374 00375 /** CMP - Register Layout Typedef */ 00376 typedef struct { 00377 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 00378 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 00379 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 00380 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 00381 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 00382 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 00383 } CMP_Type; 00384 00385 /* ---------------------------------------------------------------------------- 00386 -- CMP Register Masks 00387 ---------------------------------------------------------------------------- */ 00388 00389 /** 00390 * @addtogroup CMP_Register_Masks CMP Register Masks 00391 * @{ 00392 */ 00393 00394 /* CR0 Bit Fields */ 00395 #define CMP_CR0_HYSTCTR_MASK 0x3u 00396 #define CMP_CR0_HYSTCTR_SHIFT 0 00397 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) 00398 #define CMP_CR0_FILTER_CNT_MASK 0x70u 00399 #define CMP_CR0_FILTER_CNT_SHIFT 4 00400 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) 00401 /* CR1 Bit Fields */ 00402 #define CMP_CR1_EN_MASK 0x1u 00403 #define CMP_CR1_EN_SHIFT 0 00404 #define CMP_CR1_OPE_MASK 0x2u 00405 #define CMP_CR1_OPE_SHIFT 1 00406 #define CMP_CR1_COS_MASK 0x4u 00407 #define CMP_CR1_COS_SHIFT 2 00408 #define CMP_CR1_INV_MASK 0x8u 00409 #define CMP_CR1_INV_SHIFT 3 00410 #define CMP_CR1_PMODE_MASK 0x10u 00411 #define CMP_CR1_PMODE_SHIFT 4 00412 #define CMP_CR1_TRIGM_MASK 0x20u 00413 #define CMP_CR1_TRIGM_SHIFT 5 00414 #define CMP_CR1_WE_MASK 0x40u 00415 #define CMP_CR1_WE_SHIFT 6 00416 #define CMP_CR1_SE_MASK 0x80u 00417 #define CMP_CR1_SE_SHIFT 7 00418 /* FPR Bit Fields */ 00419 #define CMP_FPR_FILT_PER_MASK 0xFFu 00420 #define CMP_FPR_FILT_PER_SHIFT 0 00421 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) 00422 /* SCR Bit Fields */ 00423 #define CMP_SCR_COUT_MASK 0x1u 00424 #define CMP_SCR_COUT_SHIFT 0 00425 #define CMP_SCR_CFF_MASK 0x2u 00426 #define CMP_SCR_CFF_SHIFT 1 00427 #define CMP_SCR_CFR_MASK 0x4u 00428 #define CMP_SCR_CFR_SHIFT 2 00429 #define CMP_SCR_IEF_MASK 0x8u 00430 #define CMP_SCR_IEF_SHIFT 3 00431 #define CMP_SCR_IER_MASK 0x10u 00432 #define CMP_SCR_IER_SHIFT 4 00433 #define CMP_SCR_DMAEN_MASK 0x40u 00434 #define CMP_SCR_DMAEN_SHIFT 6 00435 /* DACCR Bit Fields */ 00436 #define CMP_DACCR_VOSEL_MASK 0x3Fu 00437 #define CMP_DACCR_VOSEL_SHIFT 0 00438 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) 00439 #define CMP_DACCR_VRSEL_MASK 0x40u 00440 #define CMP_DACCR_VRSEL_SHIFT 6 00441 #define CMP_DACCR_DACEN_MASK 0x80u 00442 #define CMP_DACCR_DACEN_SHIFT 7 00443 /* MUXCR Bit Fields */ 00444 #define CMP_MUXCR_MSEL_MASK 0x7u 00445 #define CMP_MUXCR_MSEL_SHIFT 0 00446 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) 00447 #define CMP_MUXCR_PSEL_MASK 0x38u 00448 #define CMP_MUXCR_PSEL_SHIFT 3 00449 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) 00450 #define CMP_MUXCR_PSTM_MASK 0x40u 00451 #define CMP_MUXCR_PSTM_SHIFT 6 00452 00453 /** 00454 * @} 00455 */ /* end of group CMP_Register_Masks */ 00456 00457 00458 /* CMP - Peripheral instance base addresses */ 00459 /** Peripheral CMP0 base address */ 00460 #define CMP0_BASE (0x40073000u) 00461 /** Peripheral CMP0 base pointer */ 00462 #define CMP0 ((CMP_Type *)CMP0_BASE) 00463 /** Array initializer of CMP peripheral base pointers */ 00464 #define CMP_BASES { CMP0 } 00465 00466 /** 00467 * @} 00468 */ /* end of group CMP_Peripheral_Access_Layer */ 00469 00470 00471 /* ---------------------------------------------------------------------------- 00472 -- DAC Peripheral Access Layer 00473 ---------------------------------------------------------------------------- */ 00474 00475 /** 00476 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 00477 * @{ 00478 */ 00479 00480 /** DAC - Register Layout Typedef */ 00481 typedef struct { 00482 struct { /* offset: 0x0, array step: 0x2 */ 00483 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 00484 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 00485 } DAT[2]; 00486 uint8_t RESERVED_0[28]; 00487 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 00488 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 00489 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 00490 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 00491 } DAC_Type; 00492 00493 /* ---------------------------------------------------------------------------- 00494 -- DAC Register Masks 00495 ---------------------------------------------------------------------------- */ 00496 00497 /** 00498 * @addtogroup DAC_Register_Masks DAC Register Masks 00499 * @{ 00500 */ 00501 00502 /* DATL Bit Fields */ 00503 #define DAC_DATL_DATA0_MASK 0xFFu 00504 #define DAC_DATL_DATA0_SHIFT 0 00505 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK) 00506 /* DATH Bit Fields */ 00507 #define DAC_DATH_DATA1_MASK 0xFu 00508 #define DAC_DATH_DATA1_SHIFT 0 00509 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK) 00510 /* SR Bit Fields */ 00511 #define DAC_SR_DACBFRPBF_MASK 0x1u 00512 #define DAC_SR_DACBFRPBF_SHIFT 0 00513 #define DAC_SR_DACBFRPTF_MASK 0x2u 00514 #define DAC_SR_DACBFRPTF_SHIFT 1 00515 /* C0 Bit Fields */ 00516 #define DAC_C0_DACBBIEN_MASK 0x1u 00517 #define DAC_C0_DACBBIEN_SHIFT 0 00518 #define DAC_C0_DACBTIEN_MASK 0x2u 00519 #define DAC_C0_DACBTIEN_SHIFT 1 00520 #define DAC_C0_LPEN_MASK 0x8u 00521 #define DAC_C0_LPEN_SHIFT 3 00522 #define DAC_C0_DACSWTRG_MASK 0x10u 00523 #define DAC_C0_DACSWTRG_SHIFT 4 00524 #define DAC_C0_DACTRGSEL_MASK 0x20u 00525 #define DAC_C0_DACTRGSEL_SHIFT 5 00526 #define DAC_C0_DACRFS_MASK 0x40u 00527 #define DAC_C0_DACRFS_SHIFT 6 00528 #define DAC_C0_DACEN_MASK 0x80u 00529 #define DAC_C0_DACEN_SHIFT 7 00530 /* C1 Bit Fields */ 00531 #define DAC_C1_DACBFEN_MASK 0x1u 00532 #define DAC_C1_DACBFEN_SHIFT 0 00533 #define DAC_C1_DACBFMD_MASK 0x4u 00534 #define DAC_C1_DACBFMD_SHIFT 2 00535 #define DAC_C1_DMAEN_MASK 0x80u 00536 #define DAC_C1_DMAEN_SHIFT 7 00537 /* C2 Bit Fields */ 00538 #define DAC_C2_DACBFUP_MASK 0x1u 00539 #define DAC_C2_DACBFUP_SHIFT 0 00540 #define DAC_C2_DACBFRP_MASK 0x10u 00541 #define DAC_C2_DACBFRP_SHIFT 4 00542 00543 /** 00544 * @} 00545 */ /* end of group DAC_Register_Masks */ 00546 00547 00548 /* DAC - Peripheral instance base addresses */ 00549 /** Peripheral DAC0 base address */ 00550 #define DAC0_BASE (0x4003F000u) 00551 /** Peripheral DAC0 base pointer */ 00552 #define DAC0 ((DAC_Type *)DAC0_BASE) 00553 /** Array initializer of DAC peripheral base pointers */ 00554 #define DAC_BASES { DAC0 } 00555 00556 /** 00557 * @} 00558 */ /* end of group DAC_Peripheral_Access_Layer */ 00559 00560 00561 /* ---------------------------------------------------------------------------- 00562 -- DMA Peripheral Access Layer 00563 ---------------------------------------------------------------------------- */ 00564 00565 /** 00566 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 00567 * @{ 00568 */ 00569 00570 /** DMA - Register Layout Typedef */ 00571 typedef struct { 00572 union { /* offset: 0x0 */ 00573 __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */ 00574 }; 00575 uint8_t RESERVED_0[252]; 00576 struct { /* offset: 0x100, array step: 0x10 */ 00577 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ 00578 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ 00579 union { /* offset: 0x108, array step: 0x10 */ 00580 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ 00581 struct { /* offset: 0x108, array step: 0x10 */ 00582 uint8_t RESERVED_0[3]; 00583 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ 00584 } DMA_DSR_ACCESS8BIT; 00585 }; 00586 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ 00587 } DMA[4]; 00588 } DMA_Type; 00589 00590 /* ---------------------------------------------------------------------------- 00591 -- DMA Register Masks 00592 ---------------------------------------------------------------------------- */ 00593 00594 /** 00595 * @addtogroup DMA_Register_Masks DMA Register Masks 00596 * @{ 00597 */ 00598 00599 /* REQC_ARR Bit Fields */ 00600 #define DMA_REQC_ARR_DMAC_MASK 0xFu 00601 #define DMA_REQC_ARR_DMAC_SHIFT 0 00602 #define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK) 00603 #define DMA_REQC_ARR_CFSM_MASK 0x80u 00604 #define DMA_REQC_ARR_CFSM_SHIFT 7 00605 /* SAR Bit Fields */ 00606 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu 00607 #define DMA_SAR_SAR_SHIFT 0 00608 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK) 00609 /* DAR Bit Fields */ 00610 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu 00611 #define DMA_DAR_DAR_SHIFT 0 00612 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK) 00613 /* DSR_BCR Bit Fields */ 00614 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu 00615 #define DMA_DSR_BCR_BCR_SHIFT 0 00616 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK) 00617 #define DMA_DSR_BCR_DONE_MASK 0x1000000u 00618 #define DMA_DSR_BCR_DONE_SHIFT 24 00619 #define DMA_DSR_BCR_BSY_MASK 0x2000000u 00620 #define DMA_DSR_BCR_BSY_SHIFT 25 00621 #define DMA_DSR_BCR_REQ_MASK 0x4000000u 00622 #define DMA_DSR_BCR_REQ_SHIFT 26 00623 #define DMA_DSR_BCR_BED_MASK 0x10000000u 00624 #define DMA_DSR_BCR_BED_SHIFT 28 00625 #define DMA_DSR_BCR_BES_MASK 0x20000000u 00626 #define DMA_DSR_BCR_BES_SHIFT 29 00627 #define DMA_DSR_BCR_CE_MASK 0x40000000u 00628 #define DMA_DSR_BCR_CE_SHIFT 30 00629 /* DCR Bit Fields */ 00630 #define DMA_DCR_LCH2_MASK 0x3u 00631 #define DMA_DCR_LCH2_SHIFT 0 00632 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK) 00633 #define DMA_DCR_LCH1_MASK 0xCu 00634 #define DMA_DCR_LCH1_SHIFT 2 00635 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK) 00636 #define DMA_DCR_LINKCC_MASK 0x30u 00637 #define DMA_DCR_LINKCC_SHIFT 4 00638 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK) 00639 #define DMA_DCR_D_REQ_MASK 0x80u 00640 #define DMA_DCR_D_REQ_SHIFT 7 00641 #define DMA_DCR_DMOD_MASK 0xF00u 00642 #define DMA_DCR_DMOD_SHIFT 8 00643 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK) 00644 #define DMA_DCR_SMOD_MASK 0xF000u 00645 #define DMA_DCR_SMOD_SHIFT 12 00646 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK) 00647 #define DMA_DCR_START_MASK 0x10000u 00648 #define DMA_DCR_START_SHIFT 16 00649 #define DMA_DCR_DSIZE_MASK 0x60000u 00650 #define DMA_DCR_DSIZE_SHIFT 17 00651 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK) 00652 #define DMA_DCR_DINC_MASK 0x80000u 00653 #define DMA_DCR_DINC_SHIFT 19 00654 #define DMA_DCR_SSIZE_MASK 0x300000u 00655 #define DMA_DCR_SSIZE_SHIFT 20 00656 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK) 00657 #define DMA_DCR_SINC_MASK 0x400000u 00658 #define DMA_DCR_SINC_SHIFT 22 00659 #define DMA_DCR_EADREQ_MASK 0x800000u 00660 #define DMA_DCR_EADREQ_SHIFT 23 00661 #define DMA_DCR_AA_MASK 0x10000000u 00662 #define DMA_DCR_AA_SHIFT 28 00663 #define DMA_DCR_CS_MASK 0x20000000u 00664 #define DMA_DCR_CS_SHIFT 29 00665 #define DMA_DCR_ERQ_MASK 0x40000000u 00666 #define DMA_DCR_ERQ_SHIFT 30 00667 #define DMA_DCR_EINT_MASK 0x80000000u 00668 #define DMA_DCR_EINT_SHIFT 31 00669 00670 /** 00671 * @} 00672 */ /* end of group DMA_Register_Masks */ 00673 00674 00675 /* DMA - Peripheral instance base addresses */ 00676 /** Peripheral DMA base address */ 00677 #define DMA_BASE (0x40008000u) 00678 /** Peripheral DMA base pointer */ 00679 #define DMA0 ((DMA_Type *)DMA_BASE) 00680 /** Array initializer of DMA peripheral base pointers */ 00681 #define DMA_BASES { DMA0 } 00682 00683 /** 00684 * @} 00685 */ /* end of group DMA_Peripheral_Access_Layer */ 00686 00687 00688 /* ---------------------------------------------------------------------------- 00689 -- DMAMUX Peripheral Access Layer 00690 ---------------------------------------------------------------------------- */ 00691 00692 /** 00693 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 00694 * @{ 00695 */ 00696 00697 /** DMAMUX - Register Layout Typedef */ 00698 typedef struct { 00699 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 00700 } DMAMUX_Type; 00701 00702 /* ---------------------------------------------------------------------------- 00703 -- DMAMUX Register Masks 00704 ---------------------------------------------------------------------------- */ 00705 00706 /** 00707 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 00708 * @{ 00709 */ 00710 00711 /* CHCFG Bit Fields */ 00712 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu 00713 #define DMAMUX_CHCFG_SOURCE_SHIFT 0 00714 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) 00715 #define DMAMUX_CHCFG_TRIG_MASK 0x40u 00716 #define DMAMUX_CHCFG_TRIG_SHIFT 6 00717 #define DMAMUX_CHCFG_ENBL_MASK 0x80u 00718 #define DMAMUX_CHCFG_ENBL_SHIFT 7 00719 00720 /** 00721 * @} 00722 */ /* end of group DMAMUX_Register_Masks */ 00723 00724 00725 /* DMAMUX - Peripheral instance base addresses */ 00726 /** Peripheral DMAMUX0 base address */ 00727 #define DMAMUX0_BASE (0x40021000u) 00728 /** Peripheral DMAMUX0 base pointer */ 00729 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) 00730 /** Array initializer of DMAMUX peripheral base pointers */ 00731 #define DMAMUX_BASES { DMAMUX0 } 00732 00733 /** 00734 * @} 00735 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 00736 00737 00738 /* ---------------------------------------------------------------------------- 00739 -- FGPIO Peripheral Access Layer 00740 ---------------------------------------------------------------------------- */ 00741 00742 /** 00743 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 00744 * @{ 00745 */ 00746 00747 /** FGPIO - Register Layout Typedef */ 00748 typedef struct { 00749 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 00750 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 00751 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 00752 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 00753 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 00754 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 00755 } FGPIO_Type; 00756 00757 /* ---------------------------------------------------------------------------- 00758 -- FGPIO Register Masks 00759 ---------------------------------------------------------------------------- */ 00760 00761 /** 00762 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 00763 * @{ 00764 */ 00765 00766 /* PDOR Bit Fields */ 00767 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu 00768 #define FGPIO_PDOR_PDO_SHIFT 0 00769 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK) 00770 /* PSOR Bit Fields */ 00771 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu 00772 #define FGPIO_PSOR_PTSO_SHIFT 0 00773 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK) 00774 /* PCOR Bit Fields */ 00775 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu 00776 #define FGPIO_PCOR_PTCO_SHIFT 0 00777 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK) 00778 /* PTOR Bit Fields */ 00779 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu 00780 #define FGPIO_PTOR_PTTO_SHIFT 0 00781 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK) 00782 /* PDIR Bit Fields */ 00783 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu 00784 #define FGPIO_PDIR_PDI_SHIFT 0 00785 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK) 00786 /* PDDR Bit Fields */ 00787 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu 00788 #define FGPIO_PDDR_PDD_SHIFT 0 00789 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK) 00790 00791 /** 00792 * @} 00793 */ /* end of group FGPIO_Register_Masks */ 00794 00795 00796 /* FGPIO - Peripheral instance base addresses */ 00797 /** Peripheral FPTA base address */ 00798 #define FPTA_BASE (0xF80FF000u) 00799 /** Peripheral FPTA base pointer */ 00800 #define FPTA ((FGPIO_Type *)FPTA_BASE) 00801 /** Peripheral FPTB base address */ 00802 #define FPTB_BASE (0xF80FF040u) 00803 /** Peripheral FPTB base pointer */ 00804 #define FPTB ((FGPIO_Type *)FPTB_BASE) 00805 /** Peripheral FPTC base address */ 00806 #define FPTC_BASE (0xF80FF080u) 00807 /** Peripheral FPTC base pointer */ 00808 #define FPTC ((FGPIO_Type *)FPTC_BASE) 00809 /** Peripheral FPTD base address */ 00810 #define FPTD_BASE (0xF80FF0C0u) 00811 /** Peripheral FPTD base pointer */ 00812 #define FPTD ((FGPIO_Type *)FPTD_BASE) 00813 /** Peripheral FPTE base address */ 00814 #define FPTE_BASE (0xF80FF100u) 00815 /** Peripheral FPTE base pointer */ 00816 #define FPTE ((FGPIO_Type *)FPTE_BASE) 00817 /** Array initializer of FGPIO peripheral base pointers */ 00818 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE } 00819 00820 /** 00821 * @} 00822 */ /* end of group FGPIO_Peripheral_Access_Layer */ 00823 00824 00825 /* ---------------------------------------------------------------------------- 00826 -- FTFA Peripheral Access Layer 00827 ---------------------------------------------------------------------------- */ 00828 00829 /** 00830 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 00831 * @{ 00832 */ 00833 00834 /** FTFA - Register Layout Typedef */ 00835 typedef struct { 00836 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 00837 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 00838 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 00839 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 00840 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 00841 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 00842 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 00843 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 00844 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 00845 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 00846 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 00847 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 00848 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 00849 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 00850 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 00851 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 00852 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 00853 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 00854 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 00855 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 00856 } FTFA_Type; 00857 00858 /* ---------------------------------------------------------------------------- 00859 -- FTFA Register Masks 00860 ---------------------------------------------------------------------------- */ 00861 00862 /** 00863 * @addtogroup FTFA_Register_Masks FTFA Register Masks 00864 * @{ 00865 */ 00866 00867 /* FSTAT Bit Fields */ 00868 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u 00869 #define FTFA_FSTAT_MGSTAT0_SHIFT 0 00870 #define FTFA_FSTAT_FPVIOL_MASK 0x10u 00871 #define FTFA_FSTAT_FPVIOL_SHIFT 4 00872 #define FTFA_FSTAT_ACCERR_MASK 0x20u 00873 #define FTFA_FSTAT_ACCERR_SHIFT 5 00874 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u 00875 #define FTFA_FSTAT_RDCOLERR_SHIFT 6 00876 #define FTFA_FSTAT_CCIF_MASK 0x80u 00877 #define FTFA_FSTAT_CCIF_SHIFT 7 00878 /* FCNFG Bit Fields */ 00879 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u 00880 #define FTFA_FCNFG_ERSSUSP_SHIFT 4 00881 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u 00882 #define FTFA_FCNFG_ERSAREQ_SHIFT 5 00883 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u 00884 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6 00885 #define FTFA_FCNFG_CCIE_MASK 0x80u 00886 #define FTFA_FCNFG_CCIE_SHIFT 7 00887 /* FSEC Bit Fields */ 00888 #define FTFA_FSEC_SEC_MASK 0x3u 00889 #define FTFA_FSEC_SEC_SHIFT 0 00890 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK) 00891 #define FTFA_FSEC_FSLACC_MASK 0xCu 00892 #define FTFA_FSEC_FSLACC_SHIFT 2 00893 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK) 00894 #define FTFA_FSEC_MEEN_MASK 0x30u 00895 #define FTFA_FSEC_MEEN_SHIFT 4 00896 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK) 00897 #define FTFA_FSEC_KEYEN_MASK 0xC0u 00898 #define FTFA_FSEC_KEYEN_SHIFT 6 00899 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK) 00900 /* FOPT Bit Fields */ 00901 #define FTFA_FOPT_OPT_MASK 0xFFu 00902 #define FTFA_FOPT_OPT_SHIFT 0 00903 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK) 00904 /* FCCOB3 Bit Fields */ 00905 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu 00906 #define FTFA_FCCOB3_CCOBn_SHIFT 0 00907 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK) 00908 /* FCCOB2 Bit Fields */ 00909 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu 00910 #define FTFA_FCCOB2_CCOBn_SHIFT 0 00911 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK) 00912 /* FCCOB1 Bit Fields */ 00913 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu 00914 #define FTFA_FCCOB1_CCOBn_SHIFT 0 00915 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK) 00916 /* FCCOB0 Bit Fields */ 00917 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu 00918 #define FTFA_FCCOB0_CCOBn_SHIFT 0 00919 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK) 00920 /* FCCOB7 Bit Fields */ 00921 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu 00922 #define FTFA_FCCOB7_CCOBn_SHIFT 0 00923 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK) 00924 /* FCCOB6 Bit Fields */ 00925 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu 00926 #define FTFA_FCCOB6_CCOBn_SHIFT 0 00927 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK) 00928 /* FCCOB5 Bit Fields */ 00929 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu 00930 #define FTFA_FCCOB5_CCOBn_SHIFT 0 00931 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK) 00932 /* FCCOB4 Bit Fields */ 00933 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu 00934 #define FTFA_FCCOB4_CCOBn_SHIFT 0 00935 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK) 00936 /* FCCOBB Bit Fields */ 00937 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu 00938 #define FTFA_FCCOBB_CCOBn_SHIFT 0 00939 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK) 00940 /* FCCOBA Bit Fields */ 00941 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu 00942 #define FTFA_FCCOBA_CCOBn_SHIFT 0 00943 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK) 00944 /* FCCOB9 Bit Fields */ 00945 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu 00946 #define FTFA_FCCOB9_CCOBn_SHIFT 0 00947 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK) 00948 /* FCCOB8 Bit Fields */ 00949 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu 00950 #define FTFA_FCCOB8_CCOBn_SHIFT 0 00951 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK) 00952 /* FPROT3 Bit Fields */ 00953 #define FTFA_FPROT3_PROT_MASK 0xFFu 00954 #define FTFA_FPROT3_PROT_SHIFT 0 00955 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK) 00956 /* FPROT2 Bit Fields */ 00957 #define FTFA_FPROT2_PROT_MASK 0xFFu 00958 #define FTFA_FPROT2_PROT_SHIFT 0 00959 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK) 00960 /* FPROT1 Bit Fields */ 00961 #define FTFA_FPROT1_PROT_MASK 0xFFu 00962 #define FTFA_FPROT1_PROT_SHIFT 0 00963 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK) 00964 /* FPROT0 Bit Fields */ 00965 #define FTFA_FPROT0_PROT_MASK 0xFFu 00966 #define FTFA_FPROT0_PROT_SHIFT 0 00967 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK) 00968 00969 /** 00970 * @} 00971 */ /* end of group FTFA_Register_Masks */ 00972 00973 00974 /* FTFA - Peripheral instance base addresses */ 00975 /** Peripheral FTFA base address */ 00976 #define FTFA_BASE (0x40020000u) 00977 /** Peripheral FTFA base pointer */ 00978 #define FTFA ((FTFA_Type *)FTFA_BASE) 00979 /** Array initializer of FTFA peripheral base pointers */ 00980 #define FTFA_BASES { FTFA } 00981 00982 /** 00983 * @} 00984 */ /* end of group FTFA_Peripheral_Access_Layer */ 00985 00986 00987 /* ---------------------------------------------------------------------------- 00988 -- GPIO Peripheral Access Layer 00989 ---------------------------------------------------------------------------- */ 00990 00991 /** 00992 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 00993 * @{ 00994 */ 00995 00996 /** GPIO - Register Layout Typedef */ 00997 typedef struct { 00998 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 00999 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 01000 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 01001 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 01002 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 01003 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 01004 } GPIO_Type; 01005 01006 /* ---------------------------------------------------------------------------- 01007 -- GPIO Register Masks 01008 ---------------------------------------------------------------------------- */ 01009 01010 /** 01011 * @addtogroup GPIO_Register_Masks GPIO Register Masks 01012 * @{ 01013 */ 01014 01015 /* PDOR Bit Fields */ 01016 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu 01017 #define GPIO_PDOR_PDO_SHIFT 0 01018 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) 01019 /* PSOR Bit Fields */ 01020 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu 01021 #define GPIO_PSOR_PTSO_SHIFT 0 01022 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) 01023 /* PCOR Bit Fields */ 01024 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu 01025 #define GPIO_PCOR_PTCO_SHIFT 0 01026 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) 01027 /* PTOR Bit Fields */ 01028 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu 01029 #define GPIO_PTOR_PTTO_SHIFT 0 01030 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) 01031 /* PDIR Bit Fields */ 01032 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu 01033 #define GPIO_PDIR_PDI_SHIFT 0 01034 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) 01035 /* PDDR Bit Fields */ 01036 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu 01037 #define GPIO_PDDR_PDD_SHIFT 0 01038 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) 01039 01040 /** 01041 * @} 01042 */ /* end of group GPIO_Register_Masks */ 01043 01044 01045 /* GPIO - Peripheral instance base addresses */ 01046 /** Peripheral PTA base address */ 01047 #define PTA_BASE (0x400FF000u) 01048 /** Peripheral PTA base pointer */ 01049 #define PTA ((GPIO_Type *)PTA_BASE) 01050 /** Peripheral PTB base address */ 01051 #define PTB_BASE (0x400FF040u) 01052 /** Peripheral PTB base pointer */ 01053 #define PTB ((GPIO_Type *)PTB_BASE) 01054 /** Peripheral PTC base address */ 01055 #define PTC_BASE (0x400FF080u) 01056 /** Peripheral PTC base pointer */ 01057 #define PTC ((GPIO_Type *)PTC_BASE) 01058 /** Peripheral PTD base address */ 01059 #define PTD_BASE (0x400FF0C0u) 01060 /** Peripheral PTD base pointer */ 01061 #define PTD ((GPIO_Type *)PTD_BASE) 01062 /** Peripheral PTE base address */ 01063 #define PTE_BASE (0x400FF100u) 01064 /** Peripheral PTE base pointer */ 01065 #define PTE ((GPIO_Type *)PTE_BASE) 01066 /** Array initializer of GPIO peripheral base pointers */ 01067 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE } 01068 01069 /** 01070 * @} 01071 */ /* end of group GPIO_Peripheral_Access_Layer */ 01072 01073 01074 /* ---------------------------------------------------------------------------- 01075 -- I2C Peripheral Access Layer 01076 ---------------------------------------------------------------------------- */ 01077 01078 /** 01079 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 01080 * @{ 01081 */ 01082 01083 /** I2C - Register Layout Typedef */ 01084 typedef struct { 01085 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 01086 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 01087 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 01088 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 01089 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 01090 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 01091 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 01092 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 01093 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 01094 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 01095 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 01096 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 01097 } I2C_Type; 01098 01099 /* ---------------------------------------------------------------------------- 01100 -- I2C Register Masks 01101 ---------------------------------------------------------------------------- */ 01102 01103 /** 01104 * @addtogroup I2C_Register_Masks I2C Register Masks 01105 * @{ 01106 */ 01107 01108 /* A1 Bit Fields */ 01109 #define I2C_A1_AD_MASK 0xFEu 01110 #define I2C_A1_AD_SHIFT 1 01111 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) 01112 /* F Bit Fields */ 01113 #define I2C_F_ICR_MASK 0x3Fu 01114 #define I2C_F_ICR_SHIFT 0 01115 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) 01116 #define I2C_F_MULT_MASK 0xC0u 01117 #define I2C_F_MULT_SHIFT 6 01118 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) 01119 /* C1 Bit Fields */ 01120 #define I2C_C1_DMAEN_MASK 0x1u 01121 #define I2C_C1_DMAEN_SHIFT 0 01122 #define I2C_C1_WUEN_MASK 0x2u 01123 #define I2C_C1_WUEN_SHIFT 1 01124 #define I2C_C1_RSTA_MASK 0x4u 01125 #define I2C_C1_RSTA_SHIFT 2 01126 #define I2C_C1_TXAK_MASK 0x8u 01127 #define I2C_C1_TXAK_SHIFT 3 01128 #define I2C_C1_TX_MASK 0x10u 01129 #define I2C_C1_TX_SHIFT 4 01130 #define I2C_C1_MST_MASK 0x20u 01131 #define I2C_C1_MST_SHIFT 5 01132 #define I2C_C1_IICIE_MASK 0x40u 01133 #define I2C_C1_IICIE_SHIFT 6 01134 #define I2C_C1_IICEN_MASK 0x80u 01135 #define I2C_C1_IICEN_SHIFT 7 01136 /* S Bit Fields */ 01137 #define I2C_S_RXAK_MASK 0x1u 01138 #define I2C_S_RXAK_SHIFT 0 01139 #define I2C_S_IICIF_MASK 0x2u 01140 #define I2C_S_IICIF_SHIFT 1 01141 #define I2C_S_SRW_MASK 0x4u 01142 #define I2C_S_SRW_SHIFT 2 01143 #define I2C_S_RAM_MASK 0x8u 01144 #define I2C_S_RAM_SHIFT 3 01145 #define I2C_S_ARBL_MASK 0x10u 01146 #define I2C_S_ARBL_SHIFT 4 01147 #define I2C_S_BUSY_MASK 0x20u 01148 #define I2C_S_BUSY_SHIFT 5 01149 #define I2C_S_IAAS_MASK 0x40u 01150 #define I2C_S_IAAS_SHIFT 6 01151 #define I2C_S_TCF_MASK 0x80u 01152 #define I2C_S_TCF_SHIFT 7 01153 /* D Bit Fields */ 01154 #define I2C_D_DATA_MASK 0xFFu 01155 #define I2C_D_DATA_SHIFT 0 01156 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) 01157 /* C2 Bit Fields */ 01158 #define I2C_C2_AD_MASK 0x7u 01159 #define I2C_C2_AD_SHIFT 0 01160 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) 01161 #define I2C_C2_RMEN_MASK 0x8u 01162 #define I2C_C2_RMEN_SHIFT 3 01163 #define I2C_C2_SBRC_MASK 0x10u 01164 #define I2C_C2_SBRC_SHIFT 4 01165 #define I2C_C2_HDRS_MASK 0x20u 01166 #define I2C_C2_HDRS_SHIFT 5 01167 #define I2C_C2_ADEXT_MASK 0x40u 01168 #define I2C_C2_ADEXT_SHIFT 6 01169 #define I2C_C2_GCAEN_MASK 0x80u 01170 #define I2C_C2_GCAEN_SHIFT 7 01171 /* FLT Bit Fields */ 01172 #define I2C_FLT_FLT_MASK 0x1Fu 01173 #define I2C_FLT_FLT_SHIFT 0 01174 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) 01175 #define I2C_FLT_STOPIE_MASK 0x20u 01176 #define I2C_FLT_STOPIE_SHIFT 5 01177 #define I2C_FLT_STOPF_MASK 0x40u 01178 #define I2C_FLT_STOPF_SHIFT 6 01179 #define I2C_FLT_SHEN_MASK 0x80u 01180 #define I2C_FLT_SHEN_SHIFT 7 01181 /* RA Bit Fields */ 01182 #define I2C_RA_RAD_MASK 0xFEu 01183 #define I2C_RA_RAD_SHIFT 1 01184 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) 01185 /* SMB Bit Fields */ 01186 #define I2C_SMB_SHTF2IE_MASK 0x1u 01187 #define I2C_SMB_SHTF2IE_SHIFT 0 01188 #define I2C_SMB_SHTF2_MASK 0x2u 01189 #define I2C_SMB_SHTF2_SHIFT 1 01190 #define I2C_SMB_SHTF1_MASK 0x4u 01191 #define I2C_SMB_SHTF1_SHIFT 2 01192 #define I2C_SMB_SLTF_MASK 0x8u 01193 #define I2C_SMB_SLTF_SHIFT 3 01194 #define I2C_SMB_TCKSEL_MASK 0x10u 01195 #define I2C_SMB_TCKSEL_SHIFT 4 01196 #define I2C_SMB_SIICAEN_MASK 0x20u 01197 #define I2C_SMB_SIICAEN_SHIFT 5 01198 #define I2C_SMB_ALERTEN_MASK 0x40u 01199 #define I2C_SMB_ALERTEN_SHIFT 6 01200 #define I2C_SMB_FACK_MASK 0x80u 01201 #define I2C_SMB_FACK_SHIFT 7 01202 /* A2 Bit Fields */ 01203 #define I2C_A2_SAD_MASK 0xFEu 01204 #define I2C_A2_SAD_SHIFT 1 01205 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) 01206 /* SLTH Bit Fields */ 01207 #define I2C_SLTH_SSLT_MASK 0xFFu 01208 #define I2C_SLTH_SSLT_SHIFT 0 01209 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) 01210 /* SLTL Bit Fields */ 01211 #define I2C_SLTL_SSLT_MASK 0xFFu 01212 #define I2C_SLTL_SSLT_SHIFT 0 01213 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) 01214 01215 /** 01216 * @} 01217 */ /* end of group I2C_Register_Masks */ 01218 01219 01220 /* I2C - Peripheral instance base addresses */ 01221 /** Peripheral I2C0 base address */ 01222 #define I2C0_BASE (0x40066000u) 01223 /** Peripheral I2C0 base pointer */ 01224 #define I2C0 ((I2C_Type *)I2C0_BASE) 01225 /** Peripheral I2C1 base address */ 01226 #define I2C1_BASE (0x40067000u) 01227 /** Peripheral I2C1 base pointer */ 01228 #define I2C1 ((I2C_Type *)I2C1_BASE) 01229 /** Array initializer of I2C peripheral base pointers */ 01230 #define I2C_BASES { I2C0, I2C1 } 01231 01232 /** 01233 * @} 01234 */ /* end of group I2C_Peripheral_Access_Layer */ 01235 01236 01237 /* ---------------------------------------------------------------------------- 01238 -- LLWU Peripheral Access Layer 01239 ---------------------------------------------------------------------------- */ 01240 01241 /** 01242 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 01243 * @{ 01244 */ 01245 01246 /** LLWU - Register Layout Typedef */ 01247 typedef struct { 01248 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 01249 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 01250 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 01251 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 01252 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 01253 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 01254 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 01255 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 01256 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 01257 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 01258 } LLWU_Type; 01259 01260 /* ---------------------------------------------------------------------------- 01261 -- LLWU Register Masks 01262 ---------------------------------------------------------------------------- */ 01263 01264 /** 01265 * @addtogroup LLWU_Register_Masks LLWU Register Masks 01266 * @{ 01267 */ 01268 01269 /* PE1 Bit Fields */ 01270 #define LLWU_PE1_WUPE0_MASK 0x3u 01271 #define LLWU_PE1_WUPE0_SHIFT 0 01272 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) 01273 #define LLWU_PE1_WUPE1_MASK 0xCu 01274 #define LLWU_PE1_WUPE1_SHIFT 2 01275 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) 01276 #define LLWU_PE1_WUPE2_MASK 0x30u 01277 #define LLWU_PE1_WUPE2_SHIFT 4 01278 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) 01279 #define LLWU_PE1_WUPE3_MASK 0xC0u 01280 #define LLWU_PE1_WUPE3_SHIFT 6 01281 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) 01282 /* PE2 Bit Fields */ 01283 #define LLWU_PE2_WUPE4_MASK 0x3u 01284 #define LLWU_PE2_WUPE4_SHIFT 0 01285 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) 01286 #define LLWU_PE2_WUPE5_MASK 0xCu 01287 #define LLWU_PE2_WUPE5_SHIFT 2 01288 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) 01289 #define LLWU_PE2_WUPE6_MASK 0x30u 01290 #define LLWU_PE2_WUPE6_SHIFT 4 01291 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) 01292 #define LLWU_PE2_WUPE7_MASK 0xC0u 01293 #define LLWU_PE2_WUPE7_SHIFT 6 01294 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) 01295 /* PE3 Bit Fields */ 01296 #define LLWU_PE3_WUPE8_MASK 0x3u 01297 #define LLWU_PE3_WUPE8_SHIFT 0 01298 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) 01299 #define LLWU_PE3_WUPE9_MASK 0xCu 01300 #define LLWU_PE3_WUPE9_SHIFT 2 01301 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) 01302 #define LLWU_PE3_WUPE10_MASK 0x30u 01303 #define LLWU_PE3_WUPE10_SHIFT 4 01304 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) 01305 #define LLWU_PE3_WUPE11_MASK 0xC0u 01306 #define LLWU_PE3_WUPE11_SHIFT 6 01307 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) 01308 /* PE4 Bit Fields */ 01309 #define LLWU_PE4_WUPE12_MASK 0x3u 01310 #define LLWU_PE4_WUPE12_SHIFT 0 01311 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) 01312 #define LLWU_PE4_WUPE13_MASK 0xCu 01313 #define LLWU_PE4_WUPE13_SHIFT 2 01314 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) 01315 #define LLWU_PE4_WUPE14_MASK 0x30u 01316 #define LLWU_PE4_WUPE14_SHIFT 4 01317 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) 01318 #define LLWU_PE4_WUPE15_MASK 0xC0u 01319 #define LLWU_PE4_WUPE15_SHIFT 6 01320 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) 01321 /* ME Bit Fields */ 01322 #define LLWU_ME_WUME0_MASK 0x1u 01323 #define LLWU_ME_WUME0_SHIFT 0 01324 #define LLWU_ME_WUME1_MASK 0x2u 01325 #define LLWU_ME_WUME1_SHIFT 1 01326 #define LLWU_ME_WUME2_MASK 0x4u 01327 #define LLWU_ME_WUME2_SHIFT 2 01328 #define LLWU_ME_WUME3_MASK 0x8u 01329 #define LLWU_ME_WUME3_SHIFT 3 01330 #define LLWU_ME_WUME4_MASK 0x10u 01331 #define LLWU_ME_WUME4_SHIFT 4 01332 #define LLWU_ME_WUME5_MASK 0x20u 01333 #define LLWU_ME_WUME5_SHIFT 5 01334 #define LLWU_ME_WUME6_MASK 0x40u 01335 #define LLWU_ME_WUME6_SHIFT 6 01336 #define LLWU_ME_WUME7_MASK 0x80u 01337 #define LLWU_ME_WUME7_SHIFT 7 01338 /* F1 Bit Fields */ 01339 #define LLWU_F1_WUF0_MASK 0x1u 01340 #define LLWU_F1_WUF0_SHIFT 0 01341 #define LLWU_F1_WUF1_MASK 0x2u 01342 #define LLWU_F1_WUF1_SHIFT 1 01343 #define LLWU_F1_WUF2_MASK 0x4u 01344 #define LLWU_F1_WUF2_SHIFT 2 01345 #define LLWU_F1_WUF3_MASK 0x8u 01346 #define LLWU_F1_WUF3_SHIFT 3 01347 #define LLWU_F1_WUF4_MASK 0x10u 01348 #define LLWU_F1_WUF4_SHIFT 4 01349 #define LLWU_F1_WUF5_MASK 0x20u 01350 #define LLWU_F1_WUF5_SHIFT 5 01351 #define LLWU_F1_WUF6_MASK 0x40u 01352 #define LLWU_F1_WUF6_SHIFT 6 01353 #define LLWU_F1_WUF7_MASK 0x80u 01354 #define LLWU_F1_WUF7_SHIFT 7 01355 /* F2 Bit Fields */ 01356 #define LLWU_F2_WUF8_MASK 0x1u 01357 #define LLWU_F2_WUF8_SHIFT 0 01358 #define LLWU_F2_WUF9_MASK 0x2u 01359 #define LLWU_F2_WUF9_SHIFT 1 01360 #define LLWU_F2_WUF10_MASK 0x4u 01361 #define LLWU_F2_WUF10_SHIFT 2 01362 #define LLWU_F2_WUF11_MASK 0x8u 01363 #define LLWU_F2_WUF11_SHIFT 3 01364 #define LLWU_F2_WUF12_MASK 0x10u 01365 #define LLWU_F2_WUF12_SHIFT 4 01366 #define LLWU_F2_WUF13_MASK 0x20u 01367 #define LLWU_F2_WUF13_SHIFT 5 01368 #define LLWU_F2_WUF14_MASK 0x40u 01369 #define LLWU_F2_WUF14_SHIFT 6 01370 #define LLWU_F2_WUF15_MASK 0x80u 01371 #define LLWU_F2_WUF15_SHIFT 7 01372 /* F3 Bit Fields */ 01373 #define LLWU_F3_MWUF0_MASK 0x1u 01374 #define LLWU_F3_MWUF0_SHIFT 0 01375 #define LLWU_F3_MWUF1_MASK 0x2u 01376 #define LLWU_F3_MWUF1_SHIFT 1 01377 #define LLWU_F3_MWUF2_MASK 0x4u 01378 #define LLWU_F3_MWUF2_SHIFT 2 01379 #define LLWU_F3_MWUF3_MASK 0x8u 01380 #define LLWU_F3_MWUF3_SHIFT 3 01381 #define LLWU_F3_MWUF4_MASK 0x10u 01382 #define LLWU_F3_MWUF4_SHIFT 4 01383 #define LLWU_F3_MWUF5_MASK 0x20u 01384 #define LLWU_F3_MWUF5_SHIFT 5 01385 #define LLWU_F3_MWUF6_MASK 0x40u 01386 #define LLWU_F3_MWUF6_SHIFT 6 01387 #define LLWU_F3_MWUF7_MASK 0x80u 01388 #define LLWU_F3_MWUF7_SHIFT 7 01389 /* FILT1 Bit Fields */ 01390 #define LLWU_FILT1_FILTSEL_MASK 0xFu 01391 #define LLWU_FILT1_FILTSEL_SHIFT 0 01392 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) 01393 #define LLWU_FILT1_FILTE_MASK 0x60u 01394 #define LLWU_FILT1_FILTE_SHIFT 5 01395 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) 01396 #define LLWU_FILT1_FILTF_MASK 0x80u 01397 #define LLWU_FILT1_FILTF_SHIFT 7 01398 /* FILT2 Bit Fields */ 01399 #define LLWU_FILT2_FILTSEL_MASK 0xFu 01400 #define LLWU_FILT2_FILTSEL_SHIFT 0 01401 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) 01402 #define LLWU_FILT2_FILTE_MASK 0x60u 01403 #define LLWU_FILT2_FILTE_SHIFT 5 01404 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) 01405 #define LLWU_FILT2_FILTF_MASK 0x80u 01406 #define LLWU_FILT2_FILTF_SHIFT 7 01407 01408 /** 01409 * @} 01410 */ /* end of group LLWU_Register_Masks */ 01411 01412 01413 /* LLWU - Peripheral instance base addresses */ 01414 /** Peripheral LLWU base address */ 01415 #define LLWU_BASE (0x4007C000u) 01416 /** Peripheral LLWU base pointer */ 01417 #define LLWU ((LLWU_Type *)LLWU_BASE) 01418 /** Array initializer of LLWU peripheral base pointers */ 01419 #define LLWU_BASES { LLWU } 01420 01421 /** 01422 * @} 01423 */ /* end of group LLWU_Peripheral_Access_Layer */ 01424 01425 01426 /* ---------------------------------------------------------------------------- 01427 -- LPTMR Peripheral Access Layer 01428 ---------------------------------------------------------------------------- */ 01429 01430 /** 01431 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 01432 * @{ 01433 */ 01434 01435 /** LPTMR - Register Layout Typedef */ 01436 typedef struct { 01437 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 01438 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 01439 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 01440 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 01441 } LPTMR_Type; 01442 01443 /* ---------------------------------------------------------------------------- 01444 -- LPTMR Register Masks 01445 ---------------------------------------------------------------------------- */ 01446 01447 /** 01448 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 01449 * @{ 01450 */ 01451 01452 /* CSR Bit Fields */ 01453 #define LPTMR_CSR_TEN_MASK 0x1u 01454 #define LPTMR_CSR_TEN_SHIFT 0 01455 #define LPTMR_CSR_TMS_MASK 0x2u 01456 #define LPTMR_CSR_TMS_SHIFT 1 01457 #define LPTMR_CSR_TFC_MASK 0x4u 01458 #define LPTMR_CSR_TFC_SHIFT 2 01459 #define LPTMR_CSR_TPP_MASK 0x8u 01460 #define LPTMR_CSR_TPP_SHIFT 3 01461 #define LPTMR_CSR_TPS_MASK 0x30u 01462 #define LPTMR_CSR_TPS_SHIFT 4 01463 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) 01464 #define LPTMR_CSR_TIE_MASK 0x40u 01465 #define LPTMR_CSR_TIE_SHIFT 6 01466 #define LPTMR_CSR_TCF_MASK 0x80u 01467 #define LPTMR_CSR_TCF_SHIFT 7 01468 /* PSR Bit Fields */ 01469 #define LPTMR_PSR_PCS_MASK 0x3u 01470 #define LPTMR_PSR_PCS_SHIFT 0 01471 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) 01472 #define LPTMR_PSR_PBYP_MASK 0x4u 01473 #define LPTMR_PSR_PBYP_SHIFT 2 01474 #define LPTMR_PSR_PRESCALE_MASK 0x78u 01475 #define LPTMR_PSR_PRESCALE_SHIFT 3 01476 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) 01477 /* CMR Bit Fields */ 01478 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu 01479 #define LPTMR_CMR_COMPARE_SHIFT 0 01480 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) 01481 /* CNR Bit Fields */ 01482 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu 01483 #define LPTMR_CNR_COUNTER_SHIFT 0 01484 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) 01485 01486 /** 01487 * @} 01488 */ /* end of group LPTMR_Register_Masks */ 01489 01490 01491 /* LPTMR - Peripheral instance base addresses */ 01492 /** Peripheral LPTMR0 base address */ 01493 #define LPTMR0_BASE (0x40040000u) 01494 /** Peripheral LPTMR0 base pointer */ 01495 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 01496 /** Array initializer of LPTMR peripheral base pointers */ 01497 #define LPTMR_BASES { LPTMR0 } 01498 01499 /** 01500 * @} 01501 */ /* end of group LPTMR_Peripheral_Access_Layer */ 01502 01503 01504 /* ---------------------------------------------------------------------------- 01505 -- MCG Peripheral Access Layer 01506 ---------------------------------------------------------------------------- */ 01507 01508 /** 01509 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 01510 * @{ 01511 */ 01512 01513 /** MCG - Register Layout Typedef */ 01514 typedef struct { 01515 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 01516 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 01517 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 01518 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 01519 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 01520 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 01521 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ 01522 uint8_t RESERVED_0[1]; 01523 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 01524 uint8_t RESERVED_1[1]; 01525 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 01526 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 01527 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 01528 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 01529 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */ 01530 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */ 01531 } MCG_Type; 01532 01533 /* ---------------------------------------------------------------------------- 01534 -- MCG Register Masks 01535 ---------------------------------------------------------------------------- */ 01536 01537 /** 01538 * @addtogroup MCG_Register_Masks MCG Register Masks 01539 * @{ 01540 */ 01541 01542 /* C1 Bit Fields */ 01543 #define MCG_C1_IREFSTEN_MASK 0x1u 01544 #define MCG_C1_IREFSTEN_SHIFT 0 01545 #define MCG_C1_IRCLKEN_MASK 0x2u 01546 #define MCG_C1_IRCLKEN_SHIFT 1 01547 #define MCG_C1_IREFS_MASK 0x4u 01548 #define MCG_C1_IREFS_SHIFT 2 01549 #define MCG_C1_FRDIV_MASK 0x38u 01550 #define MCG_C1_FRDIV_SHIFT 3 01551 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK) 01552 #define MCG_C1_CLKS_MASK 0xC0u 01553 #define MCG_C1_CLKS_SHIFT 6 01554 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) 01555 /* C2 Bit Fields */ 01556 #define MCG_C2_IRCS_MASK 0x1u 01557 #define MCG_C2_IRCS_SHIFT 0 01558 #define MCG_C2_LP_MASK 0x2u 01559 #define MCG_C2_LP_SHIFT 1 01560 #define MCG_C2_EREFS0_MASK 0x4u 01561 #define MCG_C2_EREFS0_SHIFT 2 01562 #define MCG_C2_HGO0_MASK 0x8u 01563 #define MCG_C2_HGO0_SHIFT 3 01564 #define MCG_C2_RANGE0_MASK 0x30u 01565 #define MCG_C2_RANGE0_SHIFT 4 01566 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK) 01567 #define MCG_C2_LOCRE0_MASK 0x80u 01568 #define MCG_C2_LOCRE0_SHIFT 7 01569 /* C3 Bit Fields */ 01570 #define MCG_C3_SCTRIM_MASK 0xFFu 01571 #define MCG_C3_SCTRIM_SHIFT 0 01572 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK) 01573 /* C4 Bit Fields */ 01574 #define MCG_C4_SCFTRIM_MASK 0x1u 01575 #define MCG_C4_SCFTRIM_SHIFT 0 01576 #define MCG_C4_FCTRIM_MASK 0x1Eu 01577 #define MCG_C4_FCTRIM_SHIFT 1 01578 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK) 01579 #define MCG_C4_DRST_DRS_MASK 0x60u 01580 #define MCG_C4_DRST_DRS_SHIFT 5 01581 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK) 01582 #define MCG_C4_DMX32_MASK 0x80u 01583 #define MCG_C4_DMX32_SHIFT 7 01584 /* C5 Bit Fields */ 01585 #define MCG_C5_PRDIV0_MASK 0x1Fu 01586 #define MCG_C5_PRDIV0_SHIFT 0 01587 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK) 01588 #define MCG_C5_PLLSTEN0_MASK 0x20u 01589 #define MCG_C5_PLLSTEN0_SHIFT 5 01590 #define MCG_C5_PLLCLKEN0_MASK 0x40u 01591 #define MCG_C5_PLLCLKEN0_SHIFT 6 01592 /* C6 Bit Fields */ 01593 #define MCG_C6_VDIV0_MASK 0x1Fu 01594 #define MCG_C6_VDIV0_SHIFT 0 01595 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK) 01596 #define MCG_C6_CME0_MASK 0x20u 01597 #define MCG_C6_CME0_SHIFT 5 01598 #define MCG_C6_PLLS_MASK 0x40u 01599 #define MCG_C6_PLLS_SHIFT 6 01600 #define MCG_C6_LOLIE0_MASK 0x80u 01601 #define MCG_C6_LOLIE0_SHIFT 7 01602 /* S Bit Fields */ 01603 #define MCG_S_IRCST_MASK 0x1u 01604 #define MCG_S_IRCST_SHIFT 0 01605 #define MCG_S_OSCINIT0_MASK 0x2u 01606 #define MCG_S_OSCINIT0_SHIFT 1 01607 #define MCG_S_CLKST_MASK 0xCu 01608 #define MCG_S_CLKST_SHIFT 2 01609 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) 01610 #define MCG_S_IREFST_MASK 0x10u 01611 #define MCG_S_IREFST_SHIFT 4 01612 #define MCG_S_PLLST_MASK 0x20u 01613 #define MCG_S_PLLST_SHIFT 5 01614 #define MCG_S_LOCK0_MASK 0x40u 01615 #define MCG_S_LOCK0_SHIFT 6 01616 #define MCG_S_LOLS_MASK 0x80u 01617 #define MCG_S_LOLS_SHIFT 7 01618 /* SC Bit Fields */ 01619 #define MCG_SC_LOCS0_MASK 0x1u 01620 #define MCG_SC_LOCS0_SHIFT 0 01621 #define MCG_SC_FCRDIV_MASK 0xEu 01622 #define MCG_SC_FCRDIV_SHIFT 1 01623 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) 01624 #define MCG_SC_FLTPRSRV_MASK 0x10u 01625 #define MCG_SC_FLTPRSRV_SHIFT 4 01626 #define MCG_SC_ATMF_MASK 0x20u 01627 #define MCG_SC_ATMF_SHIFT 5 01628 #define MCG_SC_ATMS_MASK 0x40u 01629 #define MCG_SC_ATMS_SHIFT 6 01630 #define MCG_SC_ATME_MASK 0x80u 01631 #define MCG_SC_ATME_SHIFT 7 01632 /* ATCVH Bit Fields */ 01633 #define MCG_ATCVH_ATCVH_MASK 0xFFu 01634 #define MCG_ATCVH_ATCVH_SHIFT 0 01635 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK) 01636 /* ATCVL Bit Fields */ 01637 #define MCG_ATCVL_ATCVL_MASK 0xFFu 01638 #define MCG_ATCVL_ATCVL_SHIFT 0 01639 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK) 01640 /* C8 Bit Fields */ 01641 #define MCG_C8_LOLRE_MASK 0x40u 01642 #define MCG_C8_LOLRE_SHIFT 6 01643 01644 /** 01645 * @} 01646 */ /* end of group MCG_Register_Masks */ 01647 01648 01649 /* MCG - Peripheral instance base addresses */ 01650 /** Peripheral MCG base address */ 01651 #define MCG_BASE (0x40064000u) 01652 /** Peripheral MCG base pointer */ 01653 #define MCG ((MCG_Type *)MCG_BASE) 01654 /** Array initializer of MCG peripheral base pointers */ 01655 #define MCG_BASES { MCG } 01656 01657 /** 01658 * @} 01659 */ /* end of group MCG_Peripheral_Access_Layer */ 01660 01661 01662 /* ---------------------------------------------------------------------------- 01663 -- MCM Peripheral Access Layer 01664 ---------------------------------------------------------------------------- */ 01665 01666 /** 01667 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 01668 * @{ 01669 */ 01670 01671 /** MCM - Register Layout Typedef */ 01672 typedef struct { 01673 uint8_t RESERVED_0[8]; 01674 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 01675 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 01676 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 01677 uint8_t RESERVED_1[48]; 01678 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 01679 } MCM_Type; 01680 01681 /* ---------------------------------------------------------------------------- 01682 -- MCM Register Masks 01683 ---------------------------------------------------------------------------- */ 01684 01685 /** 01686 * @addtogroup MCM_Register_Masks MCM Register Masks 01687 * @{ 01688 */ 01689 01690 /* PLASC Bit Fields */ 01691 #define MCM_PLASC_ASC_MASK 0xFFu 01692 #define MCM_PLASC_ASC_SHIFT 0 01693 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) 01694 /* PLAMC Bit Fields */ 01695 #define MCM_PLAMC_AMC_MASK 0xFFu 01696 #define MCM_PLAMC_AMC_SHIFT 0 01697 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) 01698 /* PLACR Bit Fields */ 01699 #define MCM_PLACR_ARB_MASK 0x200u 01700 #define MCM_PLACR_ARB_SHIFT 9 01701 #define MCM_PLACR_CFCC_MASK 0x400u 01702 #define MCM_PLACR_CFCC_SHIFT 10 01703 #define MCM_PLACR_DFCDA_MASK 0x800u 01704 #define MCM_PLACR_DFCDA_SHIFT 11 01705 #define MCM_PLACR_DFCIC_MASK 0x1000u 01706 #define MCM_PLACR_DFCIC_SHIFT 12 01707 #define MCM_PLACR_DFCC_MASK 0x2000u 01708 #define MCM_PLACR_DFCC_SHIFT 13 01709 #define MCM_PLACR_EFDS_MASK 0x4000u 01710 #define MCM_PLACR_EFDS_SHIFT 14 01711 #define MCM_PLACR_DFCS_MASK 0x8000u 01712 #define MCM_PLACR_DFCS_SHIFT 15 01713 #define MCM_PLACR_ESFC_MASK 0x10000u 01714 #define MCM_PLACR_ESFC_SHIFT 16 01715 /* CPO Bit Fields */ 01716 #define MCM_CPO_CPOREQ_MASK 0x1u 01717 #define MCM_CPO_CPOREQ_SHIFT 0 01718 #define MCM_CPO_CPOACK_MASK 0x2u 01719 #define MCM_CPO_CPOACK_SHIFT 1 01720 #define MCM_CPO_CPOWOI_MASK 0x4u 01721 #define MCM_CPO_CPOWOI_SHIFT 2 01722 01723 /** 01724 * @} 01725 */ /* end of group MCM_Register_Masks */ 01726 01727 01728 /* MCM - Peripheral instance base addresses */ 01729 /** Peripheral MCM base address */ 01730 #define MCM_BASE (0xF0003000u) 01731 /** Peripheral MCM base pointer */ 01732 #define MCM ((MCM_Type *)MCM_BASE) 01733 /** Array initializer of MCM peripheral base pointers */ 01734 #define MCM_BASES { MCM } 01735 01736 /** 01737 * @} 01738 */ /* end of group MCM_Peripheral_Access_Layer */ 01739 01740 01741 /* ---------------------------------------------------------------------------- 01742 -- MTB Peripheral Access Layer 01743 ---------------------------------------------------------------------------- */ 01744 01745 /** 01746 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 01747 * @{ 01748 */ 01749 01750 /** MTB - Register Layout Typedef */ 01751 typedef struct { 01752 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 01753 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 01754 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 01755 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 01756 uint8_t RESERVED_0[3824]; 01757 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 01758 uint8_t RESERVED_1[156]; 01759 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 01760 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 01761 uint8_t RESERVED_2[8]; 01762 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 01763 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 01764 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 01765 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 01766 uint8_t RESERVED_3[8]; 01767 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 01768 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 01769 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ 01770 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 01771 } MTB_Type; 01772 01773 /* ---------------------------------------------------------------------------- 01774 -- MTB Register Masks 01775 ---------------------------------------------------------------------------- */ 01776 01777 /** 01778 * @addtogroup MTB_Register_Masks MTB Register Masks 01779 * @{ 01780 */ 01781 01782 /* POSITION Bit Fields */ 01783 #define MTB_POSITION_WRAP_MASK 0x4u 01784 #define MTB_POSITION_WRAP_SHIFT 2 01785 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u 01786 #define MTB_POSITION_POINTER_SHIFT 3 01787 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK) 01788 /* MASTER Bit Fields */ 01789 #define MTB_MASTER_MASK_MASK 0x1Fu 01790 #define MTB_MASTER_MASK_SHIFT 0 01791 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK) 01792 #define MTB_MASTER_TSTARTEN_MASK 0x20u 01793 #define MTB_MASTER_TSTARTEN_SHIFT 5 01794 #define MTB_MASTER_TSTOPEN_MASK 0x40u 01795 #define MTB_MASTER_TSTOPEN_SHIFT 6 01796 #define MTB_MASTER_SFRWPRIV_MASK 0x80u 01797 #define MTB_MASTER_SFRWPRIV_SHIFT 7 01798 #define MTB_MASTER_RAMPRIV_MASK 0x100u 01799 #define MTB_MASTER_RAMPRIV_SHIFT 8 01800 #define MTB_MASTER_HALTREQ_MASK 0x200u 01801 #define MTB_MASTER_HALTREQ_SHIFT 9 01802 #define MTB_MASTER_EN_MASK 0x80000000u 01803 #define MTB_MASTER_EN_SHIFT 31 01804 /* FLOW Bit Fields */ 01805 #define MTB_FLOW_AUTOSTOP_MASK 0x1u 01806 #define MTB_FLOW_AUTOSTOP_SHIFT 0 01807 #define MTB_FLOW_AUTOHALT_MASK 0x2u 01808 #define MTB_FLOW_AUTOHALT_SHIFT 1 01809 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u 01810 #define MTB_FLOW_WATERMARK_SHIFT 3 01811 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK) 01812 /* BASE Bit Fields */ 01813 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu 01814 #define MTB_BASE_BASEADDR_SHIFT 0 01815 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK) 01816 /* MODECTRL Bit Fields */ 01817 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu 01818 #define MTB_MODECTRL_MODECTRL_SHIFT 0 01819 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK) 01820 /* TAGSET Bit Fields */ 01821 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu 01822 #define MTB_TAGSET_TAGSET_SHIFT 0 01823 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK) 01824 /* TAGCLEAR Bit Fields */ 01825 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu 01826 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0 01827 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK) 01828 /* LOCKACCESS Bit Fields */ 01829 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu 01830 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0 01831 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK) 01832 /* LOCKSTAT Bit Fields */ 01833 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu 01834 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0 01835 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK) 01836 /* AUTHSTAT Bit Fields */ 01837 #define MTB_AUTHSTAT_BIT0_MASK 0x1u 01838 #define MTB_AUTHSTAT_BIT0_SHIFT 0 01839 #define MTB_AUTHSTAT_BIT1_MASK 0x2u 01840 #define MTB_AUTHSTAT_BIT1_SHIFT 1 01841 #define MTB_AUTHSTAT_BIT2_MASK 0x4u 01842 #define MTB_AUTHSTAT_BIT2_SHIFT 2 01843 #define MTB_AUTHSTAT_BIT3_MASK 0x8u 01844 #define MTB_AUTHSTAT_BIT3_SHIFT 3 01845 /* DEVICEARCH Bit Fields */ 01846 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu 01847 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0 01848 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK) 01849 /* DEVICECFG Bit Fields */ 01850 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu 01851 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0 01852 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK) 01853 /* DEVICETYPID Bit Fields */ 01854 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu 01855 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0 01856 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK) 01857 /* PERIPHID Bit Fields */ 01858 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu 01859 #define MTB_PERIPHID_PERIPHID_SHIFT 0 01860 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK) 01861 /* COMPID Bit Fields */ 01862 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu 01863 #define MTB_COMPID_COMPID_SHIFT 0 01864 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK) 01865 01866 /** 01867 * @} 01868 */ /* end of group MTB_Register_Masks */ 01869 01870 01871 /* MTB - Peripheral instance base addresses */ 01872 /** Peripheral MTB base address */ 01873 #define MTB_BASE (0xF0000000u) 01874 /** Peripheral MTB base pointer */ 01875 #define MTB ((MTB_Type *)MTB_BASE) 01876 /** Array initializer of MTB peripheral base pointers */ 01877 #define MTB_BASES { MTB } 01878 01879 /** 01880 * @} 01881 */ /* end of group MTB_Peripheral_Access_Layer */ 01882 01883 01884 /* ---------------------------------------------------------------------------- 01885 -- MTBDWT Peripheral Access Layer 01886 ---------------------------------------------------------------------------- */ 01887 01888 /** 01889 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 01890 * @{ 01891 */ 01892 01893 /** MTBDWT - Register Layout Typedef */ 01894 typedef struct { 01895 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 01896 uint8_t RESERVED_0[28]; 01897 struct { /* offset: 0x20, array step: 0x10 */ 01898 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 01899 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 01900 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 01901 uint8_t RESERVED_0[4]; 01902 } COMPARATOR[2]; 01903 uint8_t RESERVED_1[448]; 01904 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 01905 uint8_t RESERVED_2[3524]; 01906 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 01907 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 01908 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ 01909 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 01910 } MTBDWT_Type; 01911 01912 /* ---------------------------------------------------------------------------- 01913 -- MTBDWT Register Masks 01914 ---------------------------------------------------------------------------- */ 01915 01916 /** 01917 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 01918 * @{ 01919 */ 01920 01921 /* CTRL Bit Fields */ 01922 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu 01923 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0 01924 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK) 01925 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u 01926 #define MTBDWT_CTRL_NUMCMP_SHIFT 28 01927 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK) 01928 /* COMP Bit Fields */ 01929 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu 01930 #define MTBDWT_COMP_COMP_SHIFT 0 01931 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK) 01932 /* MASK Bit Fields */ 01933 #define MTBDWT_MASK_MASK_MASK 0x1Fu 01934 #define MTBDWT_MASK_MASK_SHIFT 0 01935 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK) 01936 /* FCT Bit Fields */ 01937 #define MTBDWT_FCT_FUNCTION_MASK 0xFu 01938 #define MTBDWT_FCT_FUNCTION_SHIFT 0 01939 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK) 01940 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u 01941 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8 01942 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u 01943 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10 01944 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK) 01945 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u 01946 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12 01947 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK) 01948 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u 01949 #define MTBDWT_FCT_MATCHED_SHIFT 24 01950 /* TBCTRL Bit Fields */ 01951 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u 01952 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0 01953 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u 01954 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1 01955 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u 01956 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28 01957 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK) 01958 /* DEVICECFG Bit Fields */ 01959 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu 01960 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0 01961 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK) 01962 /* DEVICETYPID Bit Fields */ 01963 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu 01964 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0 01965 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 01966 /* PERIPHID Bit Fields */ 01967 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu 01968 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0 01969 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK) 01970 /* COMPID Bit Fields */ 01971 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu 01972 #define MTBDWT_COMPID_COMPID_SHIFT 0 01973 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK) 01974 01975 /** 01976 * @} 01977 */ /* end of group MTBDWT_Register_Masks */ 01978 01979 01980 /* MTBDWT - Peripheral instance base addresses */ 01981 /** Peripheral MTBDWT base address */ 01982 #define MTBDWT_BASE (0xF0001000u) 01983 /** Peripheral MTBDWT base pointer */ 01984 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 01985 /** Array initializer of MTBDWT peripheral base pointers */ 01986 #define MTBDWT_BASES { MTBDWT } 01987 01988 /** 01989 * @} 01990 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 01991 01992 01993 /* ---------------------------------------------------------------------------- 01994 -- NV Peripheral Access Layer 01995 ---------------------------------------------------------------------------- */ 01996 01997 /** 01998 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 01999 * @{ 02000 */ 02001 02002 /** NV - Register Layout Typedef */ 02003 typedef struct { 02004 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 02005 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 02006 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 02007 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 02008 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 02009 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 02010 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 02011 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 02012 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 02013 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 02014 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 02015 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 02016 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 02017 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 02018 } NV_Type; 02019 02020 /* ---------------------------------------------------------------------------- 02021 -- NV Register Masks 02022 ---------------------------------------------------------------------------- */ 02023 02024 /** 02025 * @addtogroup NV_Register_Masks NV Register Masks 02026 * @{ 02027 */ 02028 02029 /* BACKKEY3 Bit Fields */ 02030 #define NV_BACKKEY3_KEY_MASK 0xFFu 02031 #define NV_BACKKEY3_KEY_SHIFT 0 02032 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) 02033 /* BACKKEY2 Bit Fields */ 02034 #define NV_BACKKEY2_KEY_MASK 0xFFu 02035 #define NV_BACKKEY2_KEY_SHIFT 0 02036 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) 02037 /* BACKKEY1 Bit Fields */ 02038 #define NV_BACKKEY1_KEY_MASK 0xFFu 02039 #define NV_BACKKEY1_KEY_SHIFT 0 02040 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) 02041 /* BACKKEY0 Bit Fields */ 02042 #define NV_BACKKEY0_KEY_MASK 0xFFu 02043 #define NV_BACKKEY0_KEY_SHIFT 0 02044 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) 02045 /* BACKKEY7 Bit Fields */ 02046 #define NV_BACKKEY7_KEY_MASK 0xFFu 02047 #define NV_BACKKEY7_KEY_SHIFT 0 02048 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) 02049 /* BACKKEY6 Bit Fields */ 02050 #define NV_BACKKEY6_KEY_MASK 0xFFu 02051 #define NV_BACKKEY6_KEY_SHIFT 0 02052 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) 02053 /* BACKKEY5 Bit Fields */ 02054 #define NV_BACKKEY5_KEY_MASK 0xFFu 02055 #define NV_BACKKEY5_KEY_SHIFT 0 02056 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) 02057 /* BACKKEY4 Bit Fields */ 02058 #define NV_BACKKEY4_KEY_MASK 0xFFu 02059 #define NV_BACKKEY4_KEY_SHIFT 0 02060 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) 02061 /* FPROT3 Bit Fields */ 02062 #define NV_FPROT3_PROT_MASK 0xFFu 02063 #define NV_FPROT3_PROT_SHIFT 0 02064 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) 02065 /* FPROT2 Bit Fields */ 02066 #define NV_FPROT2_PROT_MASK 0xFFu 02067 #define NV_FPROT2_PROT_SHIFT 0 02068 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) 02069 /* FPROT1 Bit Fields */ 02070 #define NV_FPROT1_PROT_MASK 0xFFu 02071 #define NV_FPROT1_PROT_SHIFT 0 02072 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) 02073 /* FPROT0 Bit Fields */ 02074 #define NV_FPROT0_PROT_MASK 0xFFu 02075 #define NV_FPROT0_PROT_SHIFT 0 02076 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) 02077 /* FSEC Bit Fields */ 02078 #define NV_FSEC_SEC_MASK 0x3u 02079 #define NV_FSEC_SEC_SHIFT 0 02080 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) 02081 #define NV_FSEC_FSLACC_MASK 0xCu 02082 #define NV_FSEC_FSLACC_SHIFT 2 02083 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) 02084 #define NV_FSEC_MEEN_MASK 0x30u 02085 #define NV_FSEC_MEEN_SHIFT 4 02086 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) 02087 #define NV_FSEC_KEYEN_MASK 0xC0u 02088 #define NV_FSEC_KEYEN_SHIFT 6 02089 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) 02090 /* FOPT Bit Fields */ 02091 #define NV_FOPT_LPBOOT0_MASK 0x1u 02092 #define NV_FOPT_LPBOOT0_SHIFT 0 02093 #define NV_FOPT_NMI_DIS_MASK 0x4u 02094 #define NV_FOPT_NMI_DIS_SHIFT 2 02095 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u 02096 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3 02097 #define NV_FOPT_LPBOOT1_MASK 0x10u 02098 #define NV_FOPT_LPBOOT1_SHIFT 4 02099 #define NV_FOPT_FAST_INIT_MASK 0x20u 02100 #define NV_FOPT_FAST_INIT_SHIFT 5 02101 02102 /** 02103 * @} 02104 */ /* end of group NV_Register_Masks */ 02105 02106 02107 /* NV - Peripheral instance base addresses */ 02108 /** Peripheral FTFA_FlashConfig base address */ 02109 #define FTFA_FlashConfig_BASE (0x400u) 02110 /** Peripheral FTFA_FlashConfig base pointer */ 02111 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 02112 /** Array initializer of NV peripheral base pointers */ 02113 #define NV_BASES { FTFA_FlashConfig } 02114 02115 /** 02116 * @} 02117 */ /* end of group NV_Peripheral_Access_Layer */ 02118 02119 02120 /* ---------------------------------------------------------------------------- 02121 -- OSC Peripheral Access Layer 02122 ---------------------------------------------------------------------------- */ 02123 02124 /** 02125 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 02126 * @{ 02127 */ 02128 02129 /** OSC - Register Layout Typedef */ 02130 typedef struct { 02131 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 02132 } OSC_Type; 02133 02134 /* ---------------------------------------------------------------------------- 02135 -- OSC Register Masks 02136 ---------------------------------------------------------------------------- */ 02137 02138 /** 02139 * @addtogroup OSC_Register_Masks OSC Register Masks 02140 * @{ 02141 */ 02142 02143 /* CR Bit Fields */ 02144 #define OSC_CR_SC16P_MASK 0x1u 02145 #define OSC_CR_SC16P_SHIFT 0 02146 #define OSC_CR_SC8P_MASK 0x2u 02147 #define OSC_CR_SC8P_SHIFT 1 02148 #define OSC_CR_SC4P_MASK 0x4u 02149 #define OSC_CR_SC4P_SHIFT 2 02150 #define OSC_CR_SC2P_MASK 0x8u 02151 #define OSC_CR_SC2P_SHIFT 3 02152 #define OSC_CR_EREFSTEN_MASK 0x20u 02153 #define OSC_CR_EREFSTEN_SHIFT 5 02154 #define OSC_CR_ERCLKEN_MASK 0x80u 02155 #define OSC_CR_ERCLKEN_SHIFT 7 02156 02157 /** 02158 * @} 02159 */ /* end of group OSC_Register_Masks */ 02160 02161 02162 /* OSC - Peripheral instance base addresses */ 02163 /** Peripheral OSC0 base address */ 02164 #define OSC0_BASE (0x40065000u) 02165 /** Peripheral OSC0 base pointer */ 02166 #define OSC0 ((OSC_Type *)OSC0_BASE) 02167 /** Array initializer of OSC peripheral base pointers */ 02168 #define OSC_BASES { OSC0 } 02169 02170 /** 02171 * @} 02172 */ /* end of group OSC_Peripheral_Access_Layer */ 02173 02174 02175 /* ---------------------------------------------------------------------------- 02176 -- PIT Peripheral Access Layer 02177 ---------------------------------------------------------------------------- */ 02178 02179 /** 02180 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 02181 * @{ 02182 */ 02183 02184 /** PIT - Register Layout Typedef */ 02185 typedef struct { 02186 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 02187 uint8_t RESERVED_0[220]; 02188 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 02189 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 02190 uint8_t RESERVED_1[24]; 02191 struct { /* offset: 0x100, array step: 0x10 */ 02192 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 02193 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 02194 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 02195 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 02196 } CHANNEL[2]; 02197 } PIT_Type; 02198 02199 /* ---------------------------------------------------------------------------- 02200 -- PIT Register Masks 02201 ---------------------------------------------------------------------------- */ 02202 02203 /** 02204 * @addtogroup PIT_Register_Masks PIT Register Masks 02205 * @{ 02206 */ 02207 02208 /* MCR Bit Fields */ 02209 #define PIT_MCR_FRZ_MASK 0x1u 02210 #define PIT_MCR_FRZ_SHIFT 0 02211 #define PIT_MCR_MDIS_MASK 0x2u 02212 #define PIT_MCR_MDIS_SHIFT 1 02213 /* LTMR64H Bit Fields */ 02214 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu 02215 #define PIT_LTMR64H_LTH_SHIFT 0 02216 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK) 02217 /* LTMR64L Bit Fields */ 02218 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu 02219 #define PIT_LTMR64L_LTL_SHIFT 0 02220 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK) 02221 /* LDVAL Bit Fields */ 02222 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu 02223 #define PIT_LDVAL_TSV_SHIFT 0 02224 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) 02225 /* CVAL Bit Fields */ 02226 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu 02227 #define PIT_CVAL_TVL_SHIFT 0 02228 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) 02229 /* TCTRL Bit Fields */ 02230 #define PIT_TCTRL_TEN_MASK 0x1u 02231 #define PIT_TCTRL_TEN_SHIFT 0 02232 #define PIT_TCTRL_TIE_MASK 0x2u 02233 #define PIT_TCTRL_TIE_SHIFT 1 02234 #define PIT_TCTRL_CHN_MASK 0x4u 02235 #define PIT_TCTRL_CHN_SHIFT 2 02236 /* TFLG Bit Fields */ 02237 #define PIT_TFLG_TIF_MASK 0x1u 02238 #define PIT_TFLG_TIF_SHIFT 0 02239 02240 /** 02241 * @} 02242 */ /* end of group PIT_Register_Masks */ 02243 02244 02245 /* PIT - Peripheral instance base addresses */ 02246 /** Peripheral PIT base address */ 02247 #define PIT_BASE (0x40037000u) 02248 /** Peripheral PIT base pointer */ 02249 #define PIT ((PIT_Type *)PIT_BASE) 02250 /** Array initializer of PIT peripheral base pointers */ 02251 #define PIT_BASES { PIT } 02252 02253 /** 02254 * @} 02255 */ /* end of group PIT_Peripheral_Access_Layer */ 02256 02257 02258 /* ---------------------------------------------------------------------------- 02259 -- PMC Peripheral Access Layer 02260 ---------------------------------------------------------------------------- */ 02261 02262 /** 02263 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 02264 * @{ 02265 */ 02266 02267 /** PMC - Register Layout Typedef */ 02268 typedef struct { 02269 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 02270 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 02271 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 02272 } PMC_Type; 02273 02274 /* ---------------------------------------------------------------------------- 02275 -- PMC Register Masks 02276 ---------------------------------------------------------------------------- */ 02277 02278 /** 02279 * @addtogroup PMC_Register_Masks PMC Register Masks 02280 * @{ 02281 */ 02282 02283 /* LVDSC1 Bit Fields */ 02284 #define PMC_LVDSC1_LVDV_MASK 0x3u 02285 #define PMC_LVDSC1_LVDV_SHIFT 0 02286 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) 02287 #define PMC_LVDSC1_LVDRE_MASK 0x10u 02288 #define PMC_LVDSC1_LVDRE_SHIFT 4 02289 #define PMC_LVDSC1_LVDIE_MASK 0x20u 02290 #define PMC_LVDSC1_LVDIE_SHIFT 5 02291 #define PMC_LVDSC1_LVDACK_MASK 0x40u 02292 #define PMC_LVDSC1_LVDACK_SHIFT 6 02293 #define PMC_LVDSC1_LVDF_MASK 0x80u 02294 #define PMC_LVDSC1_LVDF_SHIFT 7 02295 /* LVDSC2 Bit Fields */ 02296 #define PMC_LVDSC2_LVWV_MASK 0x3u 02297 #define PMC_LVDSC2_LVWV_SHIFT 0 02298 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) 02299 #define PMC_LVDSC2_LVWIE_MASK 0x20u 02300 #define PMC_LVDSC2_LVWIE_SHIFT 5 02301 #define PMC_LVDSC2_LVWACK_MASK 0x40u 02302 #define PMC_LVDSC2_LVWACK_SHIFT 6 02303 #define PMC_LVDSC2_LVWF_MASK 0x80u 02304 #define PMC_LVDSC2_LVWF_SHIFT 7 02305 /* REGSC Bit Fields */ 02306 #define PMC_REGSC_BGBE_MASK 0x1u 02307 #define PMC_REGSC_BGBE_SHIFT 0 02308 #define PMC_REGSC_REGONS_MASK 0x4u 02309 #define PMC_REGSC_REGONS_SHIFT 2 02310 #define PMC_REGSC_ACKISO_MASK 0x8u 02311 #define PMC_REGSC_ACKISO_SHIFT 3 02312 #define PMC_REGSC_BGEN_MASK 0x10u 02313 #define PMC_REGSC_BGEN_SHIFT 4 02314 02315 /** 02316 * @} 02317 */ /* end of group PMC_Register_Masks */ 02318 02319 02320 /* PMC - Peripheral instance base addresses */ 02321 /** Peripheral PMC base address */ 02322 #define PMC_BASE (0x4007D000u) 02323 /** Peripheral PMC base pointer */ 02324 #define PMC ((PMC_Type *)PMC_BASE) 02325 /** Array initializer of PMC peripheral base pointers */ 02326 #define PMC_BASES { PMC } 02327 02328 /** 02329 * @} 02330 */ /* end of group PMC_Peripheral_Access_Layer */ 02331 02332 02333 /* ---------------------------------------------------------------------------- 02334 -- PORT Peripheral Access Layer 02335 ---------------------------------------------------------------------------- */ 02336 02337 /** 02338 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 02339 * @{ 02340 */ 02341 02342 /** PORT - Register Layout Typedef */ 02343 typedef struct { 02344 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 02345 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 02346 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 02347 uint8_t RESERVED_0[24]; 02348 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 02349 } PORT_Type; 02350 02351 /* ---------------------------------------------------------------------------- 02352 -- PORT Register Masks 02353 ---------------------------------------------------------------------------- */ 02354 02355 /** 02356 * @addtogroup PORT_Register_Masks PORT Register Masks 02357 * @{ 02358 */ 02359 02360 /* PCR Bit Fields */ 02361 #define PORT_PCR_PS_MASK 0x1u 02362 #define PORT_PCR_PS_SHIFT 0 02363 #define PORT_PCR_PE_MASK 0x2u 02364 #define PORT_PCR_PE_SHIFT 1 02365 #define PORT_PCR_SRE_MASK 0x4u 02366 #define PORT_PCR_SRE_SHIFT 2 02367 #define PORT_PCR_PFE_MASK 0x10u 02368 #define PORT_PCR_PFE_SHIFT 4 02369 #define PORT_PCR_DSE_MASK 0x40u 02370 #define PORT_PCR_DSE_SHIFT 6 02371 #define PORT_PCR_MUX_MASK 0x700u 02372 #define PORT_PCR_MUX_SHIFT 8 02373 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) 02374 #define PORT_PCR_IRQC_MASK 0xF0000u 02375 #define PORT_PCR_IRQC_SHIFT 16 02376 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) 02377 #define PORT_PCR_ISF_MASK 0x1000000u 02378 #define PORT_PCR_ISF_SHIFT 24 02379 /* GPCLR Bit Fields */ 02380 #define PORT_GPCLR_GPWD_MASK 0xFFFFu 02381 #define PORT_GPCLR_GPWD_SHIFT 0 02382 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) 02383 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u 02384 #define PORT_GPCLR_GPWE_SHIFT 16 02385 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) 02386 /* GPCHR Bit Fields */ 02387 #define PORT_GPCHR_GPWD_MASK 0xFFFFu 02388 #define PORT_GPCHR_GPWD_SHIFT 0 02389 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) 02390 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u 02391 #define PORT_GPCHR_GPWE_SHIFT 16 02392 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) 02393 /* ISFR Bit Fields */ 02394 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu 02395 #define PORT_ISFR_ISF_SHIFT 0 02396 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) 02397 02398 /** 02399 * @} 02400 */ /* end of group PORT_Register_Masks */ 02401 02402 02403 /* PORT - Peripheral instance base addresses */ 02404 /** Peripheral PORTA base address */ 02405 #define PORTA_BASE (0x40049000u) 02406 /** Peripheral PORTA base pointer */ 02407 #define PORTA ((PORT_Type *)PORTA_BASE) 02408 /** Peripheral PORTB base address */ 02409 #define PORTB_BASE (0x4004A000u) 02410 /** Peripheral PORTB base pointer */ 02411 #define PORTB ((PORT_Type *)PORTB_BASE) 02412 /** Peripheral PORTC base address */ 02413 #define PORTC_BASE (0x4004B000u) 02414 /** Peripheral PORTC base pointer */ 02415 #define PORTC ((PORT_Type *)PORTC_BASE) 02416 /** Peripheral PORTD base address */ 02417 #define PORTD_BASE (0x4004C000u) 02418 /** Peripheral PORTD base pointer */ 02419 #define PORTD ((PORT_Type *)PORTD_BASE) 02420 /** Peripheral PORTE base address */ 02421 #define PORTE_BASE (0x4004D000u) 02422 /** Peripheral PORTE base pointer */ 02423 #define PORTE ((PORT_Type *)PORTE_BASE) 02424 /** Array initializer of PORT peripheral base pointers */ 02425 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE } 02426 02427 /** 02428 * @} 02429 */ /* end of group PORT_Peripheral_Access_Layer */ 02430 02431 02432 /* ---------------------------------------------------------------------------- 02433 -- RCM Peripheral Access Layer 02434 ---------------------------------------------------------------------------- */ 02435 02436 /** 02437 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 02438 * @{ 02439 */ 02440 02441 /** RCM - Register Layout Typedef */ 02442 typedef struct { 02443 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 02444 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 02445 uint8_t RESERVED_0[2]; 02446 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 02447 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 02448 } RCM_Type; 02449 02450 /* ---------------------------------------------------------------------------- 02451 -- RCM Register Masks 02452 ---------------------------------------------------------------------------- */ 02453 02454 /** 02455 * @addtogroup RCM_Register_Masks RCM Register Masks 02456 * @{ 02457 */ 02458 02459 /* SRS0 Bit Fields */ 02460 #define RCM_SRS0_WAKEUP_MASK 0x1u 02461 #define RCM_SRS0_WAKEUP_SHIFT 0 02462 #define RCM_SRS0_LVD_MASK 0x2u 02463 #define RCM_SRS0_LVD_SHIFT 1 02464 #define RCM_SRS0_LOC_MASK 0x4u 02465 #define RCM_SRS0_LOC_SHIFT 2 02466 #define RCM_SRS0_LOL_MASK 0x8u 02467 #define RCM_SRS0_LOL_SHIFT 3 02468 #define RCM_SRS0_WDOG_MASK 0x20u 02469 #define RCM_SRS0_WDOG_SHIFT 5 02470 #define RCM_SRS0_PIN_MASK 0x40u 02471 #define RCM_SRS0_PIN_SHIFT 6 02472 #define RCM_SRS0_POR_MASK 0x80u 02473 #define RCM_SRS0_POR_SHIFT 7 02474 /* SRS1 Bit Fields */ 02475 #define RCM_SRS1_LOCKUP_MASK 0x2u 02476 #define RCM_SRS1_LOCKUP_SHIFT 1 02477 #define RCM_SRS1_SW_MASK 0x4u 02478 #define RCM_SRS1_SW_SHIFT 2 02479 #define RCM_SRS1_MDM_AP_MASK 0x8u 02480 #define RCM_SRS1_MDM_AP_SHIFT 3 02481 #define RCM_SRS1_SACKERR_MASK 0x20u 02482 #define RCM_SRS1_SACKERR_SHIFT 5 02483 /* RPFC Bit Fields */ 02484 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u 02485 #define RCM_RPFC_RSTFLTSRW_SHIFT 0 02486 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) 02487 #define RCM_RPFC_RSTFLTSS_MASK 0x4u 02488 #define RCM_RPFC_RSTFLTSS_SHIFT 2 02489 /* RPFW Bit Fields */ 02490 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu 02491 #define RCM_RPFW_RSTFLTSEL_SHIFT 0 02492 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) 02493 02494 /** 02495 * @} 02496 */ /* end of group RCM_Register_Masks */ 02497 02498 02499 /* RCM - Peripheral instance base addresses */ 02500 /** Peripheral RCM base address */ 02501 #define RCM_BASE (0x4007F000u) 02502 /** Peripheral RCM base pointer */ 02503 #define RCM ((RCM_Type *)RCM_BASE) 02504 /** Array initializer of RCM peripheral base pointers */ 02505 #define RCM_BASES { RCM } 02506 02507 /** 02508 * @} 02509 */ /* end of group RCM_Peripheral_Access_Layer */ 02510 02511 02512 /* ---------------------------------------------------------------------------- 02513 -- ROM Peripheral Access Layer 02514 ---------------------------------------------------------------------------- */ 02515 02516 /** 02517 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 02518 * @{ 02519 */ 02520 02521 /** ROM - Register Layout Typedef */ 02522 typedef struct { 02523 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 02524 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 02525 uint8_t RESERVED_0[4028]; 02526 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 02527 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 02528 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 02529 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 02530 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 02531 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 02532 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 02533 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 02534 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 02535 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 02536 } ROM_Type; 02537 02538 /* ---------------------------------------------------------------------------- 02539 -- ROM Register Masks 02540 ---------------------------------------------------------------------------- */ 02541 02542 /** 02543 * @addtogroup ROM_Register_Masks ROM Register Masks 02544 * @{ 02545 */ 02546 02547 /* ENTRY Bit Fields */ 02548 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu 02549 #define ROM_ENTRY_ENTRY_SHIFT 0 02550 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK) 02551 /* TABLEMARK Bit Fields */ 02552 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu 02553 #define ROM_TABLEMARK_MARK_SHIFT 0 02554 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK) 02555 /* SYSACCESS Bit Fields */ 02556 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu 02557 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0 02558 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK) 02559 /* PERIPHID4 Bit Fields */ 02560 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu 02561 #define ROM_PERIPHID4_PERIPHID_SHIFT 0 02562 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK) 02563 /* PERIPHID5 Bit Fields */ 02564 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu 02565 #define ROM_PERIPHID5_PERIPHID_SHIFT 0 02566 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK) 02567 /* PERIPHID6 Bit Fields */ 02568 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu 02569 #define ROM_PERIPHID6_PERIPHID_SHIFT 0 02570 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK) 02571 /* PERIPHID7 Bit Fields */ 02572 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu 02573 #define ROM_PERIPHID7_PERIPHID_SHIFT 0 02574 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK) 02575 /* PERIPHID0 Bit Fields */ 02576 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu 02577 #define ROM_PERIPHID0_PERIPHID_SHIFT 0 02578 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK) 02579 /* PERIPHID1 Bit Fields */ 02580 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu 02581 #define ROM_PERIPHID1_PERIPHID_SHIFT 0 02582 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK) 02583 /* PERIPHID2 Bit Fields */ 02584 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu 02585 #define ROM_PERIPHID2_PERIPHID_SHIFT 0 02586 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK) 02587 /* PERIPHID3 Bit Fields */ 02588 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu 02589 #define ROM_PERIPHID3_PERIPHID_SHIFT 0 02590 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK) 02591 /* COMPID Bit Fields */ 02592 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu 02593 #define ROM_COMPID_COMPID_SHIFT 0 02594 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK) 02595 02596 /** 02597 * @} 02598 */ /* end of group ROM_Register_Masks */ 02599 02600 02601 /* ROM - Peripheral instance base addresses */ 02602 /** Peripheral ROM base address */ 02603 #define ROM_BASE (0xF0002000u) 02604 /** Peripheral ROM base pointer */ 02605 #define ROM ((ROM_Type *)ROM_BASE) 02606 /** Array initializer of ROM peripheral base pointers */ 02607 #define ROM_BASES { ROM } 02608 02609 /** 02610 * @} 02611 */ /* end of group ROM_Peripheral_Access_Layer */ 02612 02613 02614 /* ---------------------------------------------------------------------------- 02615 -- RTC Peripheral Access Layer 02616 ---------------------------------------------------------------------------- */ 02617 02618 /** 02619 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 02620 * @{ 02621 */ 02622 02623 /** RTC - Register Layout Typedef */ 02624 typedef struct { 02625 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 02626 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 02627 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 02628 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 02629 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 02630 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 02631 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 02632 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 02633 } RTC_Type; 02634 02635 /* ---------------------------------------------------------------------------- 02636 -- RTC Register Masks 02637 ---------------------------------------------------------------------------- */ 02638 02639 /** 02640 * @addtogroup RTC_Register_Masks RTC Register Masks 02641 * @{ 02642 */ 02643 02644 /* TSR Bit Fields */ 02645 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu 02646 #define RTC_TSR_TSR_SHIFT 0 02647 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) 02648 /* TPR Bit Fields */ 02649 #define RTC_TPR_TPR_MASK 0xFFFFu 02650 #define RTC_TPR_TPR_SHIFT 0 02651 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) 02652 /* TAR Bit Fields */ 02653 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu 02654 #define RTC_TAR_TAR_SHIFT 0 02655 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) 02656 /* TCR Bit Fields */ 02657 #define RTC_TCR_TCR_MASK 0xFFu 02658 #define RTC_TCR_TCR_SHIFT 0 02659 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) 02660 #define RTC_TCR_CIR_MASK 0xFF00u 02661 #define RTC_TCR_CIR_SHIFT 8 02662 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) 02663 #define RTC_TCR_TCV_MASK 0xFF0000u 02664 #define RTC_TCR_TCV_SHIFT 16 02665 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) 02666 #define RTC_TCR_CIC_MASK 0xFF000000u 02667 #define RTC_TCR_CIC_SHIFT 24 02668 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) 02669 /* CR Bit Fields */ 02670 #define RTC_CR_SWR_MASK 0x1u 02671 #define RTC_CR_SWR_SHIFT 0 02672 #define RTC_CR_WPE_MASK 0x2u 02673 #define RTC_CR_WPE_SHIFT 1 02674 #define RTC_CR_SUP_MASK 0x4u 02675 #define RTC_CR_SUP_SHIFT 2 02676 #define RTC_CR_UM_MASK 0x8u 02677 #define RTC_CR_UM_SHIFT 3 02678 #define RTC_CR_OSCE_MASK 0x100u 02679 #define RTC_CR_OSCE_SHIFT 8 02680 #define RTC_CR_CLKO_MASK 0x200u 02681 #define RTC_CR_CLKO_SHIFT 9 02682 #define RTC_CR_SC16P_MASK 0x400u 02683 #define RTC_CR_SC16P_SHIFT 10 02684 #define RTC_CR_SC8P_MASK 0x800u 02685 #define RTC_CR_SC8P_SHIFT 11 02686 #define RTC_CR_SC4P_MASK 0x1000u 02687 #define RTC_CR_SC4P_SHIFT 12 02688 #define RTC_CR_SC2P_MASK 0x2000u 02689 #define RTC_CR_SC2P_SHIFT 13 02690 /* SR Bit Fields */ 02691 #define RTC_SR_TIF_MASK 0x1u 02692 #define RTC_SR_TIF_SHIFT 0 02693 #define RTC_SR_TOF_MASK 0x2u 02694 #define RTC_SR_TOF_SHIFT 1 02695 #define RTC_SR_TAF_MASK 0x4u 02696 #define RTC_SR_TAF_SHIFT 2 02697 #define RTC_SR_TCE_MASK 0x10u 02698 #define RTC_SR_TCE_SHIFT 4 02699 /* LR Bit Fields */ 02700 #define RTC_LR_TCL_MASK 0x8u 02701 #define RTC_LR_TCL_SHIFT 3 02702 #define RTC_LR_CRL_MASK 0x10u 02703 #define RTC_LR_CRL_SHIFT 4 02704 #define RTC_LR_SRL_MASK 0x20u 02705 #define RTC_LR_SRL_SHIFT 5 02706 #define RTC_LR_LRL_MASK 0x40u 02707 #define RTC_LR_LRL_SHIFT 6 02708 /* IER Bit Fields */ 02709 #define RTC_IER_TIIE_MASK 0x1u 02710 #define RTC_IER_TIIE_SHIFT 0 02711 #define RTC_IER_TOIE_MASK 0x2u 02712 #define RTC_IER_TOIE_SHIFT 1 02713 #define RTC_IER_TAIE_MASK 0x4u 02714 #define RTC_IER_TAIE_SHIFT 2 02715 #define RTC_IER_TSIE_MASK 0x10u 02716 #define RTC_IER_TSIE_SHIFT 4 02717 #define RTC_IER_WPON_MASK 0x80u 02718 #define RTC_IER_WPON_SHIFT 7 02719 02720 /** 02721 * @} 02722 */ /* end of group RTC_Register_Masks */ 02723 02724 02725 /* RTC - Peripheral instance base addresses */ 02726 /** Peripheral RTC base address */ 02727 #define RTC_BASE (0x4003D000u) 02728 /** Peripheral RTC base pointer */ 02729 #define RTC ((RTC_Type *)RTC_BASE) 02730 /** Array initializer of RTC peripheral base pointers */ 02731 #define RTC_BASES { RTC } 02732 02733 /** 02734 * @} 02735 */ /* end of group RTC_Peripheral_Access_Layer */ 02736 02737 02738 /* ---------------------------------------------------------------------------- 02739 -- SIM Peripheral Access Layer 02740 ---------------------------------------------------------------------------- */ 02741 02742 /** 02743 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 02744 * @{ 02745 */ 02746 02747 /** SIM - Register Layout Typedef */ 02748 typedef struct { 02749 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 02750 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 02751 uint8_t RESERVED_0[4092]; 02752 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 02753 uint8_t RESERVED_1[4]; 02754 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 02755 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 02756 uint8_t RESERVED_2[4]; 02757 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 02758 uint8_t RESERVED_3[8]; 02759 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 02760 uint8_t RESERVED_4[12]; 02761 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 02762 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 02763 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 02764 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 02765 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 02766 uint8_t RESERVED_5[4]; 02767 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 02768 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 02769 uint8_t RESERVED_6[4]; 02770 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 02771 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 02772 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 02773 uint8_t RESERVED_7[156]; 02774 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ 02775 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */ 02776 } SIM_Type; 02777 02778 /* ---------------------------------------------------------------------------- 02779 -- SIM Register Masks 02780 ---------------------------------------------------------------------------- */ 02781 02782 /** 02783 * @addtogroup SIM_Register_Masks SIM Register Masks 02784 * @{ 02785 */ 02786 02787 /* SOPT1 Bit Fields */ 02788 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u 02789 #define SIM_SOPT1_OSC32KSEL_SHIFT 18 02790 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) 02791 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u 02792 #define SIM_SOPT1_USBVSTBY_SHIFT 29 02793 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u 02794 #define SIM_SOPT1_USBSSTBY_SHIFT 30 02795 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u 02796 #define SIM_SOPT1_USBREGEN_SHIFT 31 02797 /* SOPT1CFG Bit Fields */ 02798 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u 02799 #define SIM_SOPT1CFG_URWE_SHIFT 24 02800 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u 02801 #define SIM_SOPT1CFG_UVSWE_SHIFT 25 02802 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u 02803 #define SIM_SOPT1CFG_USSWE_SHIFT 26 02804 /* SOPT2 Bit Fields */ 02805 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u 02806 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 02807 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u 02808 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5 02809 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) 02810 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u 02811 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16 02812 #define SIM_SOPT2_USBSRC_MASK 0x40000u 02813 #define SIM_SOPT2_USBSRC_SHIFT 18 02814 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u 02815 #define SIM_SOPT2_TPMSRC_SHIFT 24 02816 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK) 02817 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u 02818 #define SIM_SOPT2_UART0SRC_SHIFT 26 02819 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK) 02820 /* SOPT4 Bit Fields */ 02821 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u 02822 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 02823 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u 02824 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20 02825 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u 02826 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24 02827 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u 02828 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25 02829 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u 02830 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26 02831 /* SOPT5 Bit Fields */ 02832 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u 02833 #define SIM_SOPT5_UART0TXSRC_SHIFT 0 02834 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK) 02835 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u 02836 #define SIM_SOPT5_UART0RXSRC_SHIFT 2 02837 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u 02838 #define SIM_SOPT5_UART1TXSRC_SHIFT 4 02839 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK) 02840 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u 02841 #define SIM_SOPT5_UART1RXSRC_SHIFT 6 02842 #define SIM_SOPT5_UART0ODE_MASK 0x10000u 02843 #define SIM_SOPT5_UART0ODE_SHIFT 16 02844 #define SIM_SOPT5_UART1ODE_MASK 0x20000u 02845 #define SIM_SOPT5_UART1ODE_SHIFT 17 02846 #define SIM_SOPT5_UART2ODE_MASK 0x40000u 02847 #define SIM_SOPT5_UART2ODE_SHIFT 18 02848 /* SOPT7 Bit Fields */ 02849 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu 02850 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 02851 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) 02852 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u 02853 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 02854 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u 02855 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 02856 /* SDID Bit Fields */ 02857 #define SIM_SDID_PINID_MASK 0xFu 02858 #define SIM_SDID_PINID_SHIFT 0 02859 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) 02860 #define SIM_SDID_DIEID_MASK 0xF80u 02861 #define SIM_SDID_DIEID_SHIFT 7 02862 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK) 02863 #define SIM_SDID_REVID_MASK 0xF000u 02864 #define SIM_SDID_REVID_SHIFT 12 02865 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) 02866 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u 02867 #define SIM_SDID_SRAMSIZE_SHIFT 16 02868 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK) 02869 #define SIM_SDID_SERIESID_MASK 0xF00000u 02870 #define SIM_SDID_SERIESID_SHIFT 20 02871 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK) 02872 #define SIM_SDID_SUBFAMID_MASK 0xF000000u 02873 #define SIM_SDID_SUBFAMID_SHIFT 24 02874 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK) 02875 #define SIM_SDID_FAMID_MASK 0xF0000000u 02876 #define SIM_SDID_FAMID_SHIFT 28 02877 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) 02878 /* SCGC4 Bit Fields */ 02879 #define SIM_SCGC4_I2C0_MASK 0x40u 02880 #define SIM_SCGC4_I2C0_SHIFT 6 02881 #define SIM_SCGC4_I2C1_MASK 0x80u 02882 #define SIM_SCGC4_I2C1_SHIFT 7 02883 #define SIM_SCGC4_UART0_MASK 0x400u 02884 #define SIM_SCGC4_UART0_SHIFT 10 02885 #define SIM_SCGC4_UART1_MASK 0x800u 02886 #define SIM_SCGC4_UART1_SHIFT 11 02887 #define SIM_SCGC4_UART2_MASK 0x1000u 02888 #define SIM_SCGC4_UART2_SHIFT 12 02889 #define SIM_SCGC4_USBOTG_MASK 0x40000u 02890 #define SIM_SCGC4_USBOTG_SHIFT 18 02891 #define SIM_SCGC4_CMP_MASK 0x80000u 02892 #define SIM_SCGC4_CMP_SHIFT 19 02893 #define SIM_SCGC4_SPI0_MASK 0x400000u 02894 #define SIM_SCGC4_SPI0_SHIFT 22 02895 #define SIM_SCGC4_SPI1_MASK 0x800000u 02896 #define SIM_SCGC4_SPI1_SHIFT 23 02897 /* SCGC5 Bit Fields */ 02898 #define SIM_SCGC5_LPTMR_MASK 0x1u 02899 #define SIM_SCGC5_LPTMR_SHIFT 0 02900 #define SIM_SCGC5_TSI_MASK 0x20u 02901 #define SIM_SCGC5_TSI_SHIFT 5 02902 #define SIM_SCGC5_PORTA_MASK 0x200u 02903 #define SIM_SCGC5_PORTA_SHIFT 9 02904 #define SIM_SCGC5_PORTB_MASK 0x400u 02905 #define SIM_SCGC5_PORTB_SHIFT 10 02906 #define SIM_SCGC5_PORTC_MASK 0x800u 02907 #define SIM_SCGC5_PORTC_SHIFT 11 02908 #define SIM_SCGC5_PORTD_MASK 0x1000u 02909 #define SIM_SCGC5_PORTD_SHIFT 12 02910 #define SIM_SCGC5_PORTE_MASK 0x2000u 02911 #define SIM_SCGC5_PORTE_SHIFT 13 02912 /* SCGC6 Bit Fields */ 02913 #define SIM_SCGC6_FTF_MASK 0x1u 02914 #define SIM_SCGC6_FTF_SHIFT 0 02915 #define SIM_SCGC6_DMAMUX_MASK 0x2u 02916 #define SIM_SCGC6_DMAMUX_SHIFT 1 02917 #define SIM_SCGC6_PIT_MASK 0x800000u 02918 #define SIM_SCGC6_PIT_SHIFT 23 02919 #define SIM_SCGC6_TPM0_MASK 0x1000000u 02920 #define SIM_SCGC6_TPM0_SHIFT 24 02921 #define SIM_SCGC6_TPM1_MASK 0x2000000u 02922 #define SIM_SCGC6_TPM1_SHIFT 25 02923 #define SIM_SCGC6_TPM2_MASK 0x4000000u 02924 #define SIM_SCGC6_TPM2_SHIFT 26 02925 #define SIM_SCGC6_ADC0_MASK 0x8000000u 02926 #define SIM_SCGC6_ADC0_SHIFT 27 02927 #define SIM_SCGC6_RTC_MASK 0x20000000u 02928 #define SIM_SCGC6_RTC_SHIFT 29 02929 #define SIM_SCGC6_DAC0_MASK 0x80000000u 02930 #define SIM_SCGC6_DAC0_SHIFT 31 02931 /* SCGC7 Bit Fields */ 02932 #define SIM_SCGC7_DMA_MASK 0x100u 02933 #define SIM_SCGC7_DMA_SHIFT 8 02934 /* CLKDIV1 Bit Fields */ 02935 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u 02936 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16 02937 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) 02938 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u 02939 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28 02940 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) 02941 /* FCFG1 Bit Fields */ 02942 #define SIM_FCFG1_FLASHDIS_MASK 0x1u 02943 #define SIM_FCFG1_FLASHDIS_SHIFT 0 02944 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u 02945 #define SIM_FCFG1_FLASHDOZE_SHIFT 1 02946 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u 02947 #define SIM_FCFG1_PFSIZE_SHIFT 24 02948 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) 02949 /* FCFG2 Bit Fields */ 02950 #define SIM_FCFG2_MAXADDR_MASK 0x7F000000u 02951 #define SIM_FCFG2_MAXADDR_SHIFT 24 02952 #define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK) 02953 /* UIDMH Bit Fields */ 02954 #define SIM_UIDMH_UID_MASK 0xFFFFu 02955 #define SIM_UIDMH_UID_SHIFT 0 02956 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) 02957 /* UIDML Bit Fields */ 02958 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu 02959 #define SIM_UIDML_UID_SHIFT 0 02960 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) 02961 /* UIDL Bit Fields */ 02962 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu 02963 #define SIM_UIDL_UID_SHIFT 0 02964 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) 02965 /* COPC Bit Fields */ 02966 #define SIM_COPC_COPW_MASK 0x1u 02967 #define SIM_COPC_COPW_SHIFT 0 02968 #define SIM_COPC_COPCLKS_MASK 0x2u 02969 #define SIM_COPC_COPCLKS_SHIFT 1 02970 #define SIM_COPC_COPT_MASK 0xCu 02971 #define SIM_COPC_COPT_SHIFT 2 02972 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK) 02973 /* SRVCOP Bit Fields */ 02974 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu 02975 #define SIM_SRVCOP_SRVCOP_SHIFT 0 02976 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK) 02977 02978 /** 02979 * @} 02980 */ /* end of group SIM_Register_Masks */ 02981 02982 02983 /* SIM - Peripheral instance base addresses */ 02984 /** Peripheral SIM base address */ 02985 #define SIM_BASE (0x40047000u) 02986 /** Peripheral SIM base pointer */ 02987 #define SIM ((SIM_Type *)SIM_BASE) 02988 /** Array initializer of SIM peripheral base pointers */ 02989 #define SIM_BASES { SIM } 02990 02991 /** 02992 * @} 02993 */ /* end of group SIM_Peripheral_Access_Layer */ 02994 02995 02996 /* ---------------------------------------------------------------------------- 02997 -- SMC Peripheral Access Layer 02998 ---------------------------------------------------------------------------- */ 02999 03000 /** 03001 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 03002 * @{ 03003 */ 03004 03005 /** SMC - Register Layout Typedef */ 03006 typedef struct { 03007 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 03008 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 03009 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 03010 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 03011 } SMC_Type; 03012 03013 /* ---------------------------------------------------------------------------- 03014 -- SMC Register Masks 03015 ---------------------------------------------------------------------------- */ 03016 03017 /** 03018 * @addtogroup SMC_Register_Masks SMC Register Masks 03019 * @{ 03020 */ 03021 03022 /* PMPROT Bit Fields */ 03023 #define SMC_PMPROT_AVLLS_MASK 0x2u 03024 #define SMC_PMPROT_AVLLS_SHIFT 1 03025 #define SMC_PMPROT_ALLS_MASK 0x8u 03026 #define SMC_PMPROT_ALLS_SHIFT 3 03027 #define SMC_PMPROT_AVLP_MASK 0x20u 03028 #define SMC_PMPROT_AVLP_SHIFT 5 03029 /* PMCTRL Bit Fields */ 03030 #define SMC_PMCTRL_STOPM_MASK 0x7u 03031 #define SMC_PMCTRL_STOPM_SHIFT 0 03032 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) 03033 #define SMC_PMCTRL_STOPA_MASK 0x8u 03034 #define SMC_PMCTRL_STOPA_SHIFT 3 03035 #define SMC_PMCTRL_RUNM_MASK 0x60u 03036 #define SMC_PMCTRL_RUNM_SHIFT 5 03037 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) 03038 /* STOPCTRL Bit Fields */ 03039 #define SMC_STOPCTRL_VLLSM_MASK 0x7u 03040 #define SMC_STOPCTRL_VLLSM_SHIFT 0 03041 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK) 03042 #define SMC_STOPCTRL_PORPO_MASK 0x20u 03043 #define SMC_STOPCTRL_PORPO_SHIFT 5 03044 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u 03045 #define SMC_STOPCTRL_PSTOPO_SHIFT 6 03046 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK) 03047 /* PMSTAT Bit Fields */ 03048 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu 03049 #define SMC_PMSTAT_PMSTAT_SHIFT 0 03050 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) 03051 03052 /** 03053 * @} 03054 */ /* end of group SMC_Register_Masks */ 03055 03056 03057 /* SMC - Peripheral instance base addresses */ 03058 /** Peripheral SMC base address */ 03059 #define SMC_BASE (0x4007E000u) 03060 /** Peripheral SMC base pointer */ 03061 #define SMC ((SMC_Type *)SMC_BASE) 03062 /** Array initializer of SMC peripheral base pointers */ 03063 #define SMC_BASES { SMC } 03064 03065 /** 03066 * @} 03067 */ /* end of group SMC_Peripheral_Access_Layer */ 03068 03069 03070 /* ---------------------------------------------------------------------------- 03071 -- SPI Peripheral Access Layer 03072 ---------------------------------------------------------------------------- */ 03073 03074 /** 03075 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 03076 * @{ 03077 */ 03078 03079 /** SPI - Register Layout Typedef */ 03080 typedef struct { 03081 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */ 03082 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */ 03083 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */ 03084 __I uint8_t S; /**< SPI status register, offset: 0x3 */ 03085 uint8_t RESERVED_0[1]; 03086 __IO uint8_t D; /**< SPI data register, offset: 0x5 */ 03087 uint8_t RESERVED_1[1]; 03088 __IO uint8_t M; /**< SPI match register, offset: 0x7 */ 03089 } SPI_Type; 03090 03091 /* ---------------------------------------------------------------------------- 03092 -- SPI Register Masks 03093 ---------------------------------------------------------------------------- */ 03094 03095 /** 03096 * @addtogroup SPI_Register_Masks SPI Register Masks 03097 * @{ 03098 */ 03099 03100 /* C1 Bit Fields */ 03101 #define SPI_C1_LSBFE_MASK 0x1u 03102 #define SPI_C1_LSBFE_SHIFT 0 03103 #define SPI_C1_SSOE_MASK 0x2u 03104 #define SPI_C1_SSOE_SHIFT 1 03105 #define SPI_C1_CPHA_MASK 0x4u 03106 #define SPI_C1_CPHA_SHIFT 2 03107 #define SPI_C1_CPOL_MASK 0x8u 03108 #define SPI_C1_CPOL_SHIFT 3 03109 #define SPI_C1_MSTR_MASK 0x10u 03110 #define SPI_C1_MSTR_SHIFT 4 03111 #define SPI_C1_SPTIE_MASK 0x20u 03112 #define SPI_C1_SPTIE_SHIFT 5 03113 #define SPI_C1_SPE_MASK 0x40u 03114 #define SPI_C1_SPE_SHIFT 6 03115 #define SPI_C1_SPIE_MASK 0x80u 03116 #define SPI_C1_SPIE_SHIFT 7 03117 /* C2 Bit Fields */ 03118 #define SPI_C2_SPC0_MASK 0x1u 03119 #define SPI_C2_SPC0_SHIFT 0 03120 #define SPI_C2_SPISWAI_MASK 0x2u 03121 #define SPI_C2_SPISWAI_SHIFT 1 03122 #define SPI_C2_RXDMAE_MASK 0x4u 03123 #define SPI_C2_RXDMAE_SHIFT 2 03124 #define SPI_C2_BIDIROE_MASK 0x8u 03125 #define SPI_C2_BIDIROE_SHIFT 3 03126 #define SPI_C2_MODFEN_MASK 0x10u 03127 #define SPI_C2_MODFEN_SHIFT 4 03128 #define SPI_C2_TXDMAE_MASK 0x20u 03129 #define SPI_C2_TXDMAE_SHIFT 5 03130 #define SPI_C2_SPLPIE_MASK 0x40u 03131 #define SPI_C2_SPLPIE_SHIFT 6 03132 #define SPI_C2_SPMIE_MASK 0x80u 03133 #define SPI_C2_SPMIE_SHIFT 7 03134 /* BR Bit Fields */ 03135 #define SPI_BR_SPR_MASK 0xFu 03136 #define SPI_BR_SPR_SHIFT 0 03137 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK) 03138 #define SPI_BR_SPPR_MASK 0x70u 03139 #define SPI_BR_SPPR_SHIFT 4 03140 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK) 03141 /* S Bit Fields */ 03142 #define SPI_S_MODF_MASK 0x10u 03143 #define SPI_S_MODF_SHIFT 4 03144 #define SPI_S_SPTEF_MASK 0x20u 03145 #define SPI_S_SPTEF_SHIFT 5 03146 #define SPI_S_SPMF_MASK 0x40u 03147 #define SPI_S_SPMF_SHIFT 6 03148 #define SPI_S_SPRF_MASK 0x80u 03149 #define SPI_S_SPRF_SHIFT 7 03150 /* D Bit Fields */ 03151 #define SPI_D_Bits_MASK 0xFFu 03152 #define SPI_D_Bits_SHIFT 0 03153 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK) 03154 /* M Bit Fields */ 03155 #define SPI_M_Bits_MASK 0xFFu 03156 #define SPI_M_Bits_SHIFT 0 03157 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK) 03158 03159 /** 03160 * @} 03161 */ /* end of group SPI_Register_Masks */ 03162 03163 03164 /* SPI - Peripheral instance base addresses */ 03165 /** Peripheral SPI0 base address */ 03166 #define SPI0_BASE (0x40076000u) 03167 /** Peripheral SPI0 base pointer */ 03168 #define SPI0 ((SPI_Type *)SPI0_BASE) 03169 /** Peripheral SPI1 base address */ 03170 #define SPI1_BASE (0x40077000u) 03171 /** Peripheral SPI1 base pointer */ 03172 #define SPI1 ((SPI_Type *)SPI1_BASE) 03173 /** Array initializer of SPI peripheral base pointers */ 03174 #define SPI_BASES { SPI0, SPI1 } 03175 03176 /** 03177 * @} 03178 */ /* end of group SPI_Peripheral_Access_Layer */ 03179 03180 03181 /* ---------------------------------------------------------------------------- 03182 -- TPM Peripheral Access Layer 03183 ---------------------------------------------------------------------------- */ 03184 03185 /** 03186 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer 03187 * @{ 03188 */ 03189 03190 /** TPM - Register Layout Typedef */ 03191 typedef struct { 03192 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ 03193 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 03194 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 03195 struct { /* offset: 0xC, array step: 0x8 */ 03196 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ 03197 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 03198 } CONTROLS[6]; 03199 uint8_t RESERVED_0[20]; 03200 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ 03201 uint8_t RESERVED_1[48]; 03202 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 03203 } TPM_Type; 03204 03205 /* ---------------------------------------------------------------------------- 03206 -- TPM Register Masks 03207 ---------------------------------------------------------------------------- */ 03208 03209 /** 03210 * @addtogroup TPM_Register_Masks TPM Register Masks 03211 * @{ 03212 */ 03213 03214 /* SC Bit Fields */ 03215 #define TPM_SC_PS_MASK 0x7u 03216 #define TPM_SC_PS_SHIFT 0 03217 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK) 03218 #define TPM_SC_CMOD_MASK 0x18u 03219 #define TPM_SC_CMOD_SHIFT 3 03220 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK) 03221 #define TPM_SC_CPWMS_MASK 0x20u 03222 #define TPM_SC_CPWMS_SHIFT 5 03223 #define TPM_SC_TOIE_MASK 0x40u 03224 #define TPM_SC_TOIE_SHIFT 6 03225 #define TPM_SC_TOF_MASK 0x80u 03226 #define TPM_SC_TOF_SHIFT 7 03227 #define TPM_SC_DMA_MASK 0x100u 03228 #define TPM_SC_DMA_SHIFT 8 03229 /* CNT Bit Fields */ 03230 #define TPM_CNT_COUNT_MASK 0xFFFFu 03231 #define TPM_CNT_COUNT_SHIFT 0 03232 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK) 03233 /* MOD Bit Fields */ 03234 #define TPM_MOD_MOD_MASK 0xFFFFu 03235 #define TPM_MOD_MOD_SHIFT 0 03236 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK) 03237 /* CnSC Bit Fields */ 03238 #define TPM_CnSC_DMA_MASK 0x1u 03239 #define TPM_CnSC_DMA_SHIFT 0 03240 #define TPM_CnSC_ELSA_MASK 0x4u 03241 #define TPM_CnSC_ELSA_SHIFT 2 03242 #define TPM_CnSC_ELSB_MASK 0x8u 03243 #define TPM_CnSC_ELSB_SHIFT 3 03244 #define TPM_CnSC_MSA_MASK 0x10u 03245 #define TPM_CnSC_MSA_SHIFT 4 03246 #define TPM_CnSC_MSB_MASK 0x20u 03247 #define TPM_CnSC_MSB_SHIFT 5 03248 #define TPM_CnSC_CHIE_MASK 0x40u 03249 #define TPM_CnSC_CHIE_SHIFT 6 03250 #define TPM_CnSC_CHF_MASK 0x80u 03251 #define TPM_CnSC_CHF_SHIFT 7 03252 /* CnV Bit Fields */ 03253 #define TPM_CnV_VAL_MASK 0xFFFFu 03254 #define TPM_CnV_VAL_SHIFT 0 03255 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK) 03256 /* STATUS Bit Fields */ 03257 #define TPM_STATUS_CH0F_MASK 0x1u 03258 #define TPM_STATUS_CH0F_SHIFT 0 03259 #define TPM_STATUS_CH1F_MASK 0x2u 03260 #define TPM_STATUS_CH1F_SHIFT 1 03261 #define TPM_STATUS_CH2F_MASK 0x4u 03262 #define TPM_STATUS_CH2F_SHIFT 2 03263 #define TPM_STATUS_CH3F_MASK 0x8u 03264 #define TPM_STATUS_CH3F_SHIFT 3 03265 #define TPM_STATUS_CH4F_MASK 0x10u 03266 #define TPM_STATUS_CH4F_SHIFT 4 03267 #define TPM_STATUS_CH5F_MASK 0x20u 03268 #define TPM_STATUS_CH5F_SHIFT 5 03269 #define TPM_STATUS_TOF_MASK 0x100u 03270 #define TPM_STATUS_TOF_SHIFT 8 03271 /* CONF Bit Fields */ 03272 #define TPM_CONF_DOZEEN_MASK 0x20u 03273 #define TPM_CONF_DOZEEN_SHIFT 5 03274 #define TPM_CONF_DBGMODE_MASK 0xC0u 03275 #define TPM_CONF_DBGMODE_SHIFT 6 03276 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK) 03277 #define TPM_CONF_GTBEEN_MASK 0x200u 03278 #define TPM_CONF_GTBEEN_SHIFT 9 03279 #define TPM_CONF_CSOT_MASK 0x10000u 03280 #define TPM_CONF_CSOT_SHIFT 16 03281 #define TPM_CONF_CSOO_MASK 0x20000u 03282 #define TPM_CONF_CSOO_SHIFT 17 03283 #define TPM_CONF_CROT_MASK 0x40000u 03284 #define TPM_CONF_CROT_SHIFT 18 03285 #define TPM_CONF_TRGSEL_MASK 0xF000000u 03286 #define TPM_CONF_TRGSEL_SHIFT 24 03287 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK) 03288 03289 /** 03290 * @} 03291 */ /* end of group TPM_Register_Masks */ 03292 03293 03294 /* TPM - Peripheral instance base addresses */ 03295 /** Peripheral TPM0 base address */ 03296 #define TPM0_BASE (0x40038000u) 03297 /** Peripheral TPM0 base pointer */ 03298 #define TPM0 ((TPM_Type *)TPM0_BASE) 03299 /** Peripheral TPM1 base address */ 03300 #define TPM1_BASE (0x40039000u) 03301 /** Peripheral TPM1 base pointer */ 03302 #define TPM1 ((TPM_Type *)TPM1_BASE) 03303 /** Peripheral TPM2 base address */ 03304 #define TPM2_BASE (0x4003A000u) 03305 /** Peripheral TPM2 base pointer */ 03306 #define TPM2 ((TPM_Type *)TPM2_BASE) 03307 /** Array initializer of TPM peripheral base pointers */ 03308 #define TPM_BASES { TPM0, TPM1, TPM2 } 03309 03310 /** 03311 * @} 03312 */ /* end of group TPM_Peripheral_Access_Layer */ 03313 03314 03315 /* ---------------------------------------------------------------------------- 03316 -- TSI Peripheral Access Layer 03317 ---------------------------------------------------------------------------- */ 03318 03319 /** 03320 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer 03321 * @{ 03322 */ 03323 03324 /** TSI - Register Layout Typedef */ 03325 typedef struct { 03326 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ 03327 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ 03328 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ 03329 } TSI_Type; 03330 03331 /* ---------------------------------------------------------------------------- 03332 -- TSI Register Masks 03333 ---------------------------------------------------------------------------- */ 03334 03335 /** 03336 * @addtogroup TSI_Register_Masks TSI Register Masks 03337 * @{ 03338 */ 03339 03340 /* GENCS Bit Fields */ 03341 #define TSI_GENCS_CURSW_MASK 0x2u 03342 #define TSI_GENCS_CURSW_SHIFT 1 03343 #define TSI_GENCS_EOSF_MASK 0x4u 03344 #define TSI_GENCS_EOSF_SHIFT 2 03345 #define TSI_GENCS_SCNIP_MASK 0x8u 03346 #define TSI_GENCS_SCNIP_SHIFT 3 03347 #define TSI_GENCS_STM_MASK 0x10u 03348 #define TSI_GENCS_STM_SHIFT 4 03349 #define TSI_GENCS_STPE_MASK 0x20u 03350 #define TSI_GENCS_STPE_SHIFT 5 03351 #define TSI_GENCS_TSIIEN_MASK 0x40u 03352 #define TSI_GENCS_TSIIEN_SHIFT 6 03353 #define TSI_GENCS_TSIEN_MASK 0x80u 03354 #define TSI_GENCS_TSIEN_SHIFT 7 03355 #define TSI_GENCS_NSCN_MASK 0x1F00u 03356 #define TSI_GENCS_NSCN_SHIFT 8 03357 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK) 03358 #define TSI_GENCS_PS_MASK 0xE000u 03359 #define TSI_GENCS_PS_SHIFT 13 03360 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK) 03361 #define TSI_GENCS_EXTCHRG_MASK 0x70000u 03362 #define TSI_GENCS_EXTCHRG_SHIFT 16 03363 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK) 03364 #define TSI_GENCS_DVOLT_MASK 0x180000u 03365 #define TSI_GENCS_DVOLT_SHIFT 19 03366 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK) 03367 #define TSI_GENCS_REFCHRG_MASK 0xE00000u 03368 #define TSI_GENCS_REFCHRG_SHIFT 21 03369 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK) 03370 #define TSI_GENCS_MODE_MASK 0xF000000u 03371 #define TSI_GENCS_MODE_SHIFT 24 03372 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK) 03373 #define TSI_GENCS_ESOR_MASK 0x10000000u 03374 #define TSI_GENCS_ESOR_SHIFT 28 03375 #define TSI_GENCS_OUTRGF_MASK 0x80000000u 03376 #define TSI_GENCS_OUTRGF_SHIFT 31 03377 /* DATA Bit Fields */ 03378 #define TSI_DATA_TSICNT_MASK 0xFFFFu 03379 #define TSI_DATA_TSICNT_SHIFT 0 03380 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK) 03381 #define TSI_DATA_SWTS_MASK 0x400000u 03382 #define TSI_DATA_SWTS_SHIFT 22 03383 #define TSI_DATA_DMAEN_MASK 0x800000u 03384 #define TSI_DATA_DMAEN_SHIFT 23 03385 #define TSI_DATA_TSICH_MASK 0xF0000000u 03386 #define TSI_DATA_TSICH_SHIFT 28 03387 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK) 03388 /* TSHD Bit Fields */ 03389 #define TSI_TSHD_THRESL_MASK 0xFFFFu 03390 #define TSI_TSHD_THRESL_SHIFT 0 03391 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK) 03392 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u 03393 #define TSI_TSHD_THRESH_SHIFT 16 03394 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK) 03395 03396 /** 03397 * @} 03398 */ /* end of group TSI_Register_Masks */ 03399 03400 03401 /* TSI - Peripheral instance base addresses */ 03402 /** Peripheral TSI0 base address */ 03403 #define TSI0_BASE (0x40045000u) 03404 /** Peripheral TSI0 base pointer */ 03405 #define TSI0 ((TSI_Type *)TSI0_BASE) 03406 /** Array initializer of TSI peripheral base pointers */ 03407 #define TSI_BASES { TSI0 } 03408 03409 /** 03410 * @} 03411 */ /* end of group TSI_Peripheral_Access_Layer */ 03412 03413 03414 /* ---------------------------------------------------------------------------- 03415 -- UART Peripheral Access Layer 03416 ---------------------------------------------------------------------------- */ 03417 03418 /** 03419 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 03420 * @{ 03421 */ 03422 03423 /** UART - Register Layout Typedef */ 03424 typedef struct { 03425 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 03426 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 03427 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 03428 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 03429 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 03430 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 03431 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 03432 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 03433 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */ 03434 } UART_Type; 03435 03436 /* ---------------------------------------------------------------------------- 03437 -- UART Register Masks 03438 ---------------------------------------------------------------------------- */ 03439 03440 /** 03441 * @addtogroup UART_Register_Masks UART Register Masks 03442 * @{ 03443 */ 03444 03445 /* BDH Bit Fields */ 03446 #define UART_BDH_SBR_MASK 0x1Fu 03447 #define UART_BDH_SBR_SHIFT 0 03448 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) 03449 #define UART_BDH_SBNS_MASK 0x20u 03450 #define UART_BDH_SBNS_SHIFT 5 03451 #define UART_BDH_RXEDGIE_MASK 0x40u 03452 #define UART_BDH_RXEDGIE_SHIFT 6 03453 #define UART_BDH_LBKDIE_MASK 0x80u 03454 #define UART_BDH_LBKDIE_SHIFT 7 03455 /* BDL Bit Fields */ 03456 #define UART_BDL_SBR_MASK 0xFFu 03457 #define UART_BDL_SBR_SHIFT 0 03458 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) 03459 /* C1 Bit Fields */ 03460 #define UART_C1_PT_MASK 0x1u 03461 #define UART_C1_PT_SHIFT 0 03462 #define UART_C1_PE_MASK 0x2u 03463 #define UART_C1_PE_SHIFT 1 03464 #define UART_C1_ILT_MASK 0x4u 03465 #define UART_C1_ILT_SHIFT 2 03466 #define UART_C1_WAKE_MASK 0x8u 03467 #define UART_C1_WAKE_SHIFT 3 03468 #define UART_C1_M_MASK 0x10u 03469 #define UART_C1_M_SHIFT 4 03470 #define UART_C1_RSRC_MASK 0x20u 03471 #define UART_C1_RSRC_SHIFT 5 03472 #define UART_C1_UARTSWAI_MASK 0x40u 03473 #define UART_C1_UARTSWAI_SHIFT 6 03474 #define UART_C1_LOOPS_MASK 0x80u 03475 #define UART_C1_LOOPS_SHIFT 7 03476 /* C2 Bit Fields */ 03477 #define UART_C2_SBK_MASK 0x1u 03478 #define UART_C2_SBK_SHIFT 0 03479 #define UART_C2_RWU_MASK 0x2u 03480 #define UART_C2_RWU_SHIFT 1 03481 #define UART_C2_RE_MASK 0x4u 03482 #define UART_C2_RE_SHIFT 2 03483 #define UART_C2_TE_MASK 0x8u 03484 #define UART_C2_TE_SHIFT 3 03485 #define UART_C2_ILIE_MASK 0x10u 03486 #define UART_C2_ILIE_SHIFT 4 03487 #define UART_C2_RIE_MASK 0x20u 03488 #define UART_C2_RIE_SHIFT 5 03489 #define UART_C2_TCIE_MASK 0x40u 03490 #define UART_C2_TCIE_SHIFT 6 03491 #define UART_C2_TIE_MASK 0x80u 03492 #define UART_C2_TIE_SHIFT 7 03493 /* S1 Bit Fields */ 03494 #define UART_S1_PF_MASK 0x1u 03495 #define UART_S1_PF_SHIFT 0 03496 #define UART_S1_FE_MASK 0x2u 03497 #define UART_S1_FE_SHIFT 1 03498 #define UART_S1_NF_MASK 0x4u 03499 #define UART_S1_NF_SHIFT 2 03500 #define UART_S1_OR_MASK 0x8u 03501 #define UART_S1_OR_SHIFT 3 03502 #define UART_S1_IDLE_MASK 0x10u 03503 #define UART_S1_IDLE_SHIFT 4 03504 #define UART_S1_RDRF_MASK 0x20u 03505 #define UART_S1_RDRF_SHIFT 5 03506 #define UART_S1_TC_MASK 0x40u 03507 #define UART_S1_TC_SHIFT 6 03508 #define UART_S1_TDRE_MASK 0x80u 03509 #define UART_S1_TDRE_SHIFT 7 03510 /* S2 Bit Fields */ 03511 #define UART_S2_RAF_MASK 0x1u 03512 #define UART_S2_RAF_SHIFT 0 03513 #define UART_S2_LBKDE_MASK 0x2u 03514 #define UART_S2_LBKDE_SHIFT 1 03515 #define UART_S2_BRK13_MASK 0x4u 03516 #define UART_S2_BRK13_SHIFT 2 03517 #define UART_S2_RWUID_MASK 0x8u 03518 #define UART_S2_RWUID_SHIFT 3 03519 #define UART_S2_RXINV_MASK 0x10u 03520 #define UART_S2_RXINV_SHIFT 4 03521 #define UART_S2_RXEDGIF_MASK 0x40u 03522 #define UART_S2_RXEDGIF_SHIFT 6 03523 #define UART_S2_LBKDIF_MASK 0x80u 03524 #define UART_S2_LBKDIF_SHIFT 7 03525 /* C3 Bit Fields */ 03526 #define UART_C3_PEIE_MASK 0x1u 03527 #define UART_C3_PEIE_SHIFT 0 03528 #define UART_C3_FEIE_MASK 0x2u 03529 #define UART_C3_FEIE_SHIFT 1 03530 #define UART_C3_NEIE_MASK 0x4u 03531 #define UART_C3_NEIE_SHIFT 2 03532 #define UART_C3_ORIE_MASK 0x8u 03533 #define UART_C3_ORIE_SHIFT 3 03534 #define UART_C3_TXINV_MASK 0x10u 03535 #define UART_C3_TXINV_SHIFT 4 03536 #define UART_C3_TXDIR_MASK 0x20u 03537 #define UART_C3_TXDIR_SHIFT 5 03538 #define UART_C3_T8_MASK 0x40u 03539 #define UART_C3_T8_SHIFT 6 03540 #define UART_C3_R8_MASK 0x80u 03541 #define UART_C3_R8_SHIFT 7 03542 /* D Bit Fields */ 03543 #define UART_D_R0T0_MASK 0x1u 03544 #define UART_D_R0T0_SHIFT 0 03545 #define UART_D_R1T1_MASK 0x2u 03546 #define UART_D_R1T1_SHIFT 1 03547 #define UART_D_R2T2_MASK 0x4u 03548 #define UART_D_R2T2_SHIFT 2 03549 #define UART_D_R3T3_MASK 0x8u 03550 #define UART_D_R3T3_SHIFT 3 03551 #define UART_D_R4T4_MASK 0x10u 03552 #define UART_D_R4T4_SHIFT 4 03553 #define UART_D_R5T5_MASK 0x20u 03554 #define UART_D_R5T5_SHIFT 5 03555 #define UART_D_R6T6_MASK 0x40u 03556 #define UART_D_R6T6_SHIFT 6 03557 #define UART_D_R7T7_MASK 0x80u 03558 #define UART_D_R7T7_SHIFT 7 03559 /* C4 Bit Fields */ 03560 #define UART_C4_LBKDDMAS_MASK 0x8u 03561 #define UART_C4_LBKDDMAS_SHIFT 3 03562 #define UART_C4_ILDMAS_MASK 0x10u 03563 #define UART_C4_ILDMAS_SHIFT 4 03564 #define UART_C4_RDMAS_MASK 0x20u 03565 #define UART_C4_RDMAS_SHIFT 5 03566 #define UART_C4_TCDMAS_MASK 0x40u 03567 #define UART_C4_TCDMAS_SHIFT 6 03568 #define UART_C4_TDMAS_MASK 0x80u 03569 #define UART_C4_TDMAS_SHIFT 7 03570 03571 /** 03572 * @} 03573 */ /* end of group UART_Register_Masks */ 03574 03575 03576 /* UART - Peripheral instance base addresses */ 03577 /** Peripheral UART1 base address */ 03578 #define UART1_BASE (0x4006B000u) 03579 /** Peripheral UART1 base pointer */ 03580 #define UART1 ((UART_Type *)UART1_BASE) 03581 /** Peripheral UART2 base address */ 03582 #define UART2_BASE (0x4006C000u) 03583 /** Peripheral UART2 base pointer */ 03584 #define UART2 ((UART_Type *)UART2_BASE) 03585 /** Array initializer of UART peripheral base pointers */ 03586 #define UART_BASES { UART1, UART2 } 03587 03588 /** 03589 * @} 03590 */ /* end of group UART_Peripheral_Access_Layer */ 03591 03592 03593 /* ---------------------------------------------------------------------------- 03594 -- UARTLP Peripheral Access Layer 03595 ---------------------------------------------------------------------------- */ 03596 03597 /** 03598 * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer 03599 * @{ 03600 */ 03601 03602 /** UARTLP - Register Layout Typedef */ 03603 typedef struct { 03604 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */ 03605 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */ 03606 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 03607 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 03608 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 03609 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 03610 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 03611 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 03612 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 03613 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 03614 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 03615 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 03616 } UARTLP_Type; 03617 03618 /* ---------------------------------------------------------------------------- 03619 -- UARTLP Register Masks 03620 ---------------------------------------------------------------------------- */ 03621 03622 /** 03623 * @addtogroup UARTLP_Register_Masks UARTLP Register Masks 03624 * @{ 03625 */ 03626 03627 /* BDH Bit Fields */ 03628 #define UARTLP_BDH_SBR_MASK 0x1Fu 03629 #define UARTLP_BDH_SBR_SHIFT 0 03630 #define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK) 03631 #define UARTLP_BDH_SBNS_MASK 0x20u 03632 #define UARTLP_BDH_SBNS_SHIFT 5 03633 #define UARTLP_BDH_RXEDGIE_MASK 0x40u 03634 #define UARTLP_BDH_RXEDGIE_SHIFT 6 03635 #define UARTLP_BDH_LBKDIE_MASK 0x80u 03636 #define UARTLP_BDH_LBKDIE_SHIFT 7 03637 /* BDL Bit Fields */ 03638 #define UARTLP_BDL_SBR_MASK 0xFFu 03639 #define UARTLP_BDL_SBR_SHIFT 0 03640 #define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK) 03641 /* C1 Bit Fields */ 03642 #define UARTLP_C1_PT_MASK 0x1u 03643 #define UARTLP_C1_PT_SHIFT 0 03644 #define UARTLP_C1_PE_MASK 0x2u 03645 #define UARTLP_C1_PE_SHIFT 1 03646 #define UARTLP_C1_ILT_MASK 0x4u 03647 #define UARTLP_C1_ILT_SHIFT 2 03648 #define UARTLP_C1_WAKE_MASK 0x8u 03649 #define UARTLP_C1_WAKE_SHIFT 3 03650 #define UARTLP_C1_M_MASK 0x10u 03651 #define UARTLP_C1_M_SHIFT 4 03652 #define UARTLP_C1_RSRC_MASK 0x20u 03653 #define UARTLP_C1_RSRC_SHIFT 5 03654 #define UARTLP_C1_DOZEEN_MASK 0x40u 03655 #define UARTLP_C1_DOZEEN_SHIFT 6 03656 #define UARTLP_C1_LOOPS_MASK 0x80u 03657 #define UARTLP_C1_LOOPS_SHIFT 7 03658 /* C2 Bit Fields */ 03659 #define UARTLP_C2_SBK_MASK 0x1u 03660 #define UARTLP_C2_SBK_SHIFT 0 03661 #define UARTLP_C2_RWU_MASK 0x2u 03662 #define UARTLP_C2_RWU_SHIFT 1 03663 #define UARTLP_C2_RE_MASK 0x4u 03664 #define UARTLP_C2_RE_SHIFT 2 03665 #define UARTLP_C2_TE_MASK 0x8u 03666 #define UARTLP_C2_TE_SHIFT 3 03667 #define UARTLP_C2_ILIE_MASK 0x10u 03668 #define UARTLP_C2_ILIE_SHIFT 4 03669 #define UARTLP_C2_RIE_MASK 0x20u 03670 #define UARTLP_C2_RIE_SHIFT 5 03671 #define UARTLP_C2_TCIE_MASK 0x40u 03672 #define UARTLP_C2_TCIE_SHIFT 6 03673 #define UARTLP_C2_TIE_MASK 0x80u 03674 #define UARTLP_C2_TIE_SHIFT 7 03675 /* S1 Bit Fields */ 03676 #define UARTLP_S1_PF_MASK 0x1u 03677 #define UARTLP_S1_PF_SHIFT 0 03678 #define UARTLP_S1_FE_MASK 0x2u 03679 #define UARTLP_S1_FE_SHIFT 1 03680 #define UARTLP_S1_NF_MASK 0x4u 03681 #define UARTLP_S1_NF_SHIFT 2 03682 #define UARTLP_S1_OR_MASK 0x8u 03683 #define UARTLP_S1_OR_SHIFT 3 03684 #define UARTLP_S1_IDLE_MASK 0x10u 03685 #define UARTLP_S1_IDLE_SHIFT 4 03686 #define UARTLP_S1_RDRF_MASK 0x20u 03687 #define UARTLP_S1_RDRF_SHIFT 5 03688 #define UARTLP_S1_TC_MASK 0x40u 03689 #define UARTLP_S1_TC_SHIFT 6 03690 #define UARTLP_S1_TDRE_MASK 0x80u 03691 #define UARTLP_S1_TDRE_SHIFT 7 03692 /* S2 Bit Fields */ 03693 #define UARTLP_S2_RAF_MASK 0x1u 03694 #define UARTLP_S2_RAF_SHIFT 0 03695 #define UARTLP_S2_LBKDE_MASK 0x2u 03696 #define UARTLP_S2_LBKDE_SHIFT 1 03697 #define UARTLP_S2_BRK13_MASK 0x4u 03698 #define UARTLP_S2_BRK13_SHIFT 2 03699 #define UARTLP_S2_RWUID_MASK 0x8u 03700 #define UARTLP_S2_RWUID_SHIFT 3 03701 #define UARTLP_S2_RXINV_MASK 0x10u 03702 #define UARTLP_S2_RXINV_SHIFT 4 03703 #define UARTLP_S2_MSBF_MASK 0x20u 03704 #define UARTLP_S2_MSBF_SHIFT 5 03705 #define UARTLP_S2_RXEDGIF_MASK 0x40u 03706 #define UARTLP_S2_RXEDGIF_SHIFT 6 03707 #define UARTLP_S2_LBKDIF_MASK 0x80u 03708 #define UARTLP_S2_LBKDIF_SHIFT 7 03709 /* C3 Bit Fields */ 03710 #define UARTLP_C3_PEIE_MASK 0x1u 03711 #define UARTLP_C3_PEIE_SHIFT 0 03712 #define UARTLP_C3_FEIE_MASK 0x2u 03713 #define UARTLP_C3_FEIE_SHIFT 1 03714 #define UARTLP_C3_NEIE_MASK 0x4u 03715 #define UARTLP_C3_NEIE_SHIFT 2 03716 #define UARTLP_C3_ORIE_MASK 0x8u 03717 #define UARTLP_C3_ORIE_SHIFT 3 03718 #define UARTLP_C3_TXINV_MASK 0x10u 03719 #define UARTLP_C3_TXINV_SHIFT 4 03720 #define UARTLP_C3_TXDIR_MASK 0x20u 03721 #define UARTLP_C3_TXDIR_SHIFT 5 03722 #define UARTLP_C3_R9T8_MASK 0x40u 03723 #define UARTLP_C3_R9T8_SHIFT 6 03724 #define UARTLP_C3_R8T9_MASK 0x80u 03725 #define UARTLP_C3_R8T9_SHIFT 7 03726 /* D Bit Fields */ 03727 #define UARTLP_D_R0T0_MASK 0x1u 03728 #define UARTLP_D_R0T0_SHIFT 0 03729 #define UARTLP_D_R1T1_MASK 0x2u 03730 #define UARTLP_D_R1T1_SHIFT 1 03731 #define UARTLP_D_R2T2_MASK 0x4u 03732 #define UARTLP_D_R2T2_SHIFT 2 03733 #define UARTLP_D_R3T3_MASK 0x8u 03734 #define UARTLP_D_R3T3_SHIFT 3 03735 #define UARTLP_D_R4T4_MASK 0x10u 03736 #define UARTLP_D_R4T4_SHIFT 4 03737 #define UARTLP_D_R5T5_MASK 0x20u 03738 #define UARTLP_D_R5T5_SHIFT 5 03739 #define UARTLP_D_R6T6_MASK 0x40u 03740 #define UARTLP_D_R6T6_SHIFT 6 03741 #define UARTLP_D_R7T7_MASK 0x80u 03742 #define UARTLP_D_R7T7_SHIFT 7 03743 /* MA1 Bit Fields */ 03744 #define UARTLP_MA1_MA_MASK 0xFFu 03745 #define UARTLP_MA1_MA_SHIFT 0 03746 #define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK) 03747 /* MA2 Bit Fields */ 03748 #define UARTLP_MA2_MA_MASK 0xFFu 03749 #define UARTLP_MA2_MA_SHIFT 0 03750 #define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK) 03751 /* C4 Bit Fields */ 03752 #define UARTLP_C4_OSR_MASK 0x1Fu 03753 #define UARTLP_C4_OSR_SHIFT 0 03754 #define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK) 03755 #define UARTLP_C4_M10_MASK 0x20u 03756 #define UARTLP_C4_M10_SHIFT 5 03757 #define UARTLP_C4_MAEN2_MASK 0x40u 03758 #define UARTLP_C4_MAEN2_SHIFT 6 03759 #define UARTLP_C4_MAEN1_MASK 0x80u 03760 #define UARTLP_C4_MAEN1_SHIFT 7 03761 /* C5 Bit Fields */ 03762 #define UARTLP_C5_RESYNCDIS_MASK 0x1u 03763 #define UARTLP_C5_RESYNCDIS_SHIFT 0 03764 #define UARTLP_C5_BOTHEDGE_MASK 0x2u 03765 #define UARTLP_C5_BOTHEDGE_SHIFT 1 03766 #define UARTLP_C5_RDMAE_MASK 0x20u 03767 #define UARTLP_C5_RDMAE_SHIFT 5 03768 #define UARTLP_C5_TDMAE_MASK 0x80u 03769 #define UARTLP_C5_TDMAE_SHIFT 7 03770 03771 /** 03772 * @} 03773 */ /* end of group UARTLP_Register_Masks */ 03774 03775 03776 /* UARTLP - Peripheral instance base addresses */ 03777 /** Peripheral UART0 base address */ 03778 #define UART0_BASE (0x4006A000u) 03779 /** Peripheral UART0 base pointer */ 03780 #define UART0 ((UARTLP_Type *)UART0_BASE) 03781 /** Array initializer of UARTLP peripheral base pointers */ 03782 #define UARTLP_BASES { UART0 } 03783 03784 /** 03785 * @} 03786 */ /* end of group UARTLP_Peripheral_Access_Layer */ 03787 03788 03789 /* ---------------------------------------------------------------------------- 03790 -- USB Peripheral Access Layer 03791 ---------------------------------------------------------------------------- */ 03792 03793 /** 03794 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 03795 * @{ 03796 */ 03797 03798 /** USB - Register Layout Typedef */ 03799 typedef struct { 03800 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ 03801 uint8_t RESERVED_0[3]; 03802 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ 03803 uint8_t RESERVED_1[3]; 03804 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ 03805 uint8_t RESERVED_2[3]; 03806 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ 03807 uint8_t RESERVED_3[3]; 03808 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ 03809 uint8_t RESERVED_4[3]; 03810 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ 03811 uint8_t RESERVED_5[3]; 03812 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ 03813 uint8_t RESERVED_6[3]; 03814 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ 03815 uint8_t RESERVED_7[99]; 03816 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ 03817 uint8_t RESERVED_8[3]; 03818 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ 03819 uint8_t RESERVED_9[3]; 03820 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ 03821 uint8_t RESERVED_10[3]; 03822 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ 03823 uint8_t RESERVED_11[3]; 03824 __I uint8_t STAT; /**< Status register, offset: 0x90 */ 03825 uint8_t RESERVED_12[3]; 03826 __IO uint8_t CTL; /**< Control register, offset: 0x94 */ 03827 uint8_t RESERVED_13[3]; 03828 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ 03829 uint8_t RESERVED_14[3]; 03830 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ 03831 uint8_t RESERVED_15[3]; 03832 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ 03833 uint8_t RESERVED_16[3]; 03834 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ 03835 uint8_t RESERVED_17[3]; 03836 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ 03837 uint8_t RESERVED_18[3]; 03838 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ 03839 uint8_t RESERVED_19[3]; 03840 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 03841 uint8_t RESERVED_20[3]; 03842 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 03843 uint8_t RESERVED_21[11]; 03844 struct { /* offset: 0xC0, array step: 0x4 */ 03845 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ 03846 uint8_t RESERVED_0[3]; 03847 } ENDPOINT[16]; 03848 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ 03849 uint8_t RESERVED_22[3]; 03850 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ 03851 uint8_t RESERVED_23[3]; 03852 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ 03853 uint8_t RESERVED_24[3]; 03854 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ 03855 } USB_Type; 03856 03857 /* ---------------------------------------------------------------------------- 03858 -- USB Register Masks 03859 ---------------------------------------------------------------------------- */ 03860 03861 /** 03862 * @addtogroup USB_Register_Masks USB Register Masks 03863 * @{ 03864 */ 03865 03866 /* PERID Bit Fields */ 03867 #define USB_PERID_ID_MASK 0x3Fu 03868 #define USB_PERID_ID_SHIFT 0 03869 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) 03870 /* IDCOMP Bit Fields */ 03871 #define USB_IDCOMP_NID_MASK 0x3Fu 03872 #define USB_IDCOMP_NID_SHIFT 0 03873 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) 03874 /* REV Bit Fields */ 03875 #define USB_REV_REV_MASK 0xFFu 03876 #define USB_REV_REV_SHIFT 0 03877 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) 03878 /* ADDINFO Bit Fields */ 03879 #define USB_ADDINFO_IEHOST_MASK 0x1u 03880 #define USB_ADDINFO_IEHOST_SHIFT 0 03881 #define USB_ADDINFO_IRQNUM_MASK 0xF8u 03882 #define USB_ADDINFO_IRQNUM_SHIFT 3 03883 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK) 03884 /* OTGISTAT Bit Fields */ 03885 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u 03886 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0 03887 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u 03888 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2 03889 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u 03890 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3 03891 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u 03892 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5 03893 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u 03894 #define USB_OTGISTAT_ONEMSEC_SHIFT 6 03895 #define USB_OTGISTAT_IDCHG_MASK 0x80u 03896 #define USB_OTGISTAT_IDCHG_SHIFT 7 03897 /* OTGICR Bit Fields */ 03898 #define USB_OTGICR_AVBUSEN_MASK 0x1u 03899 #define USB_OTGICR_AVBUSEN_SHIFT 0 03900 #define USB_OTGICR_BSESSEN_MASK 0x4u 03901 #define USB_OTGICR_BSESSEN_SHIFT 2 03902 #define USB_OTGICR_SESSVLDEN_MASK 0x8u 03903 #define USB_OTGICR_SESSVLDEN_SHIFT 3 03904 #define USB_OTGICR_LINESTATEEN_MASK 0x20u 03905 #define USB_OTGICR_LINESTATEEN_SHIFT 5 03906 #define USB_OTGICR_ONEMSECEN_MASK 0x40u 03907 #define USB_OTGICR_ONEMSECEN_SHIFT 6 03908 #define USB_OTGICR_IDEN_MASK 0x80u 03909 #define USB_OTGICR_IDEN_SHIFT 7 03910 /* OTGSTAT Bit Fields */ 03911 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u 03912 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0 03913 #define USB_OTGSTAT_BSESSEND_MASK 0x4u 03914 #define USB_OTGSTAT_BSESSEND_SHIFT 2 03915 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u 03916 #define USB_OTGSTAT_SESS_VLD_SHIFT 3 03917 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u 03918 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5 03919 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u 03920 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6 03921 #define USB_OTGSTAT_ID_MASK 0x80u 03922 #define USB_OTGSTAT_ID_SHIFT 7 03923 /* OTGCTL Bit Fields */ 03924 #define USB_OTGCTL_OTGEN_MASK 0x4u 03925 #define USB_OTGCTL_OTGEN_SHIFT 2 03926 #define USB_OTGCTL_DMLOW_MASK 0x10u 03927 #define USB_OTGCTL_DMLOW_SHIFT 4 03928 #define USB_OTGCTL_DPLOW_MASK 0x20u 03929 #define USB_OTGCTL_DPLOW_SHIFT 5 03930 #define USB_OTGCTL_DPHIGH_MASK 0x80u 03931 #define USB_OTGCTL_DPHIGH_SHIFT 7 03932 /* ISTAT Bit Fields */ 03933 #define USB_ISTAT_USBRST_MASK 0x1u 03934 #define USB_ISTAT_USBRST_SHIFT 0 03935 #define USB_ISTAT_ERROR_MASK 0x2u 03936 #define USB_ISTAT_ERROR_SHIFT 1 03937 #define USB_ISTAT_SOFTOK_MASK 0x4u 03938 #define USB_ISTAT_SOFTOK_SHIFT 2 03939 #define USB_ISTAT_TOKDNE_MASK 0x8u 03940 #define USB_ISTAT_TOKDNE_SHIFT 3 03941 #define USB_ISTAT_SLEEP_MASK 0x10u 03942 #define USB_ISTAT_SLEEP_SHIFT 4 03943 #define USB_ISTAT_RESUME_MASK 0x20u 03944 #define USB_ISTAT_RESUME_SHIFT 5 03945 #define USB_ISTAT_ATTACH_MASK 0x40u 03946 #define USB_ISTAT_ATTACH_SHIFT 6 03947 #define USB_ISTAT_STALL_MASK 0x80u 03948 #define USB_ISTAT_STALL_SHIFT 7 03949 /* INTEN Bit Fields */ 03950 #define USB_INTEN_USBRSTEN_MASK 0x1u 03951 #define USB_INTEN_USBRSTEN_SHIFT 0 03952 #define USB_INTEN_ERROREN_MASK 0x2u 03953 #define USB_INTEN_ERROREN_SHIFT 1 03954 #define USB_INTEN_SOFTOKEN_MASK 0x4u 03955 #define USB_INTEN_SOFTOKEN_SHIFT 2 03956 #define USB_INTEN_TOKDNEEN_MASK 0x8u 03957 #define USB_INTEN_TOKDNEEN_SHIFT 3 03958 #define USB_INTEN_SLEEPEN_MASK 0x10u 03959 #define USB_INTEN_SLEEPEN_SHIFT 4 03960 #define USB_INTEN_RESUMEEN_MASK 0x20u 03961 #define USB_INTEN_RESUMEEN_SHIFT 5 03962 #define USB_INTEN_ATTACHEN_MASK 0x40u 03963 #define USB_INTEN_ATTACHEN_SHIFT 6 03964 #define USB_INTEN_STALLEN_MASK 0x80u 03965 #define USB_INTEN_STALLEN_SHIFT 7 03966 /* ERRSTAT Bit Fields */ 03967 #define USB_ERRSTAT_PIDERR_MASK 0x1u 03968 #define USB_ERRSTAT_PIDERR_SHIFT 0 03969 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u 03970 #define USB_ERRSTAT_CRC5EOF_SHIFT 1 03971 #define USB_ERRSTAT_CRC16_MASK 0x4u 03972 #define USB_ERRSTAT_CRC16_SHIFT 2 03973 #define USB_ERRSTAT_DFN8_MASK 0x8u 03974 #define USB_ERRSTAT_DFN8_SHIFT 3 03975 #define USB_ERRSTAT_BTOERR_MASK 0x10u 03976 #define USB_ERRSTAT_BTOERR_SHIFT 4 03977 #define USB_ERRSTAT_DMAERR_MASK 0x20u 03978 #define USB_ERRSTAT_DMAERR_SHIFT 5 03979 #define USB_ERRSTAT_BTSERR_MASK 0x80u 03980 #define USB_ERRSTAT_BTSERR_SHIFT 7 03981 /* ERREN Bit Fields */ 03982 #define USB_ERREN_PIDERREN_MASK 0x1u 03983 #define USB_ERREN_PIDERREN_SHIFT 0 03984 #define USB_ERREN_CRC5EOFEN_MASK 0x2u 03985 #define USB_ERREN_CRC5EOFEN_SHIFT 1 03986 #define USB_ERREN_CRC16EN_MASK 0x4u 03987 #define USB_ERREN_CRC16EN_SHIFT 2 03988 #define USB_ERREN_DFN8EN_MASK 0x8u 03989 #define USB_ERREN_DFN8EN_SHIFT 3 03990 #define USB_ERREN_BTOERREN_MASK 0x10u 03991 #define USB_ERREN_BTOERREN_SHIFT 4 03992 #define USB_ERREN_DMAERREN_MASK 0x20u 03993 #define USB_ERREN_DMAERREN_SHIFT 5 03994 #define USB_ERREN_BTSERREN_MASK 0x80u 03995 #define USB_ERREN_BTSERREN_SHIFT 7 03996 /* STAT Bit Fields */ 03997 #define USB_STAT_ODD_MASK 0x4u 03998 #define USB_STAT_ODD_SHIFT 2 03999 #define USB_STAT_TX_MASK 0x8u 04000 #define USB_STAT_TX_SHIFT 3 04001 #define USB_STAT_ENDP_MASK 0xF0u 04002 #define USB_STAT_ENDP_SHIFT 4 04003 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) 04004 /* CTL Bit Fields */ 04005 #define USB_CTL_USBENSOFEN_MASK 0x1u 04006 #define USB_CTL_USBENSOFEN_SHIFT 0 04007 #define USB_CTL_ODDRST_MASK 0x2u 04008 #define USB_CTL_ODDRST_SHIFT 1 04009 #define USB_CTL_RESUME_MASK 0x4u 04010 #define USB_CTL_RESUME_SHIFT 2 04011 #define USB_CTL_HOSTMODEEN_MASK 0x8u 04012 #define USB_CTL_HOSTMODEEN_SHIFT 3 04013 #define USB_CTL_RESET_MASK 0x10u 04014 #define USB_CTL_RESET_SHIFT 4 04015 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u 04016 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 04017 #define USB_CTL_SE0_MASK 0x40u 04018 #define USB_CTL_SE0_SHIFT 6 04019 #define USB_CTL_JSTATE_MASK 0x80u 04020 #define USB_CTL_JSTATE_SHIFT 7 04021 /* ADDR Bit Fields */ 04022 #define USB_ADDR_ADDR_MASK 0x7Fu 04023 #define USB_ADDR_ADDR_SHIFT 0 04024 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) 04025 #define USB_ADDR_LSEN_MASK 0x80u 04026 #define USB_ADDR_LSEN_SHIFT 7 04027 /* BDTPAGE1 Bit Fields */ 04028 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu 04029 #define USB_BDTPAGE1_BDTBA_SHIFT 1 04030 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) 04031 /* FRMNUML Bit Fields */ 04032 #define USB_FRMNUML_FRM_MASK 0xFFu 04033 #define USB_FRMNUML_FRM_SHIFT 0 04034 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) 04035 /* FRMNUMH Bit Fields */ 04036 #define USB_FRMNUMH_FRM_MASK 0x7u 04037 #define USB_FRMNUMH_FRM_SHIFT 0 04038 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) 04039 /* TOKEN Bit Fields */ 04040 #define USB_TOKEN_TOKENENDPT_MASK 0xFu 04041 #define USB_TOKEN_TOKENENDPT_SHIFT 0 04042 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK) 04043 #define USB_TOKEN_TOKENPID_MASK 0xF0u 04044 #define USB_TOKEN_TOKENPID_SHIFT 4 04045 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK) 04046 /* SOFTHLD Bit Fields */ 04047 #define USB_SOFTHLD_CNT_MASK 0xFFu 04048 #define USB_SOFTHLD_CNT_SHIFT 0 04049 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK) 04050 /* BDTPAGE2 Bit Fields */ 04051 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu 04052 #define USB_BDTPAGE2_BDTBA_SHIFT 0 04053 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) 04054 /* BDTPAGE3 Bit Fields */ 04055 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu 04056 #define USB_BDTPAGE3_BDTBA_SHIFT 0 04057 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) 04058 /* ENDPT Bit Fields */ 04059 #define USB_ENDPT_EPHSHK_MASK 0x1u 04060 #define USB_ENDPT_EPHSHK_SHIFT 0 04061 #define USB_ENDPT_EPSTALL_MASK 0x2u 04062 #define USB_ENDPT_EPSTALL_SHIFT 1 04063 #define USB_ENDPT_EPTXEN_MASK 0x4u 04064 #define USB_ENDPT_EPTXEN_SHIFT 2 04065 #define USB_ENDPT_EPRXEN_MASK 0x8u 04066 #define USB_ENDPT_EPRXEN_SHIFT 3 04067 #define USB_ENDPT_EPCTLDIS_MASK 0x10u 04068 #define USB_ENDPT_EPCTLDIS_SHIFT 4 04069 #define USB_ENDPT_RETRYDIS_MASK 0x40u 04070 #define USB_ENDPT_RETRYDIS_SHIFT 6 04071 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u 04072 #define USB_ENDPT_HOSTWOHUB_SHIFT 7 04073 /* USBCTRL Bit Fields */ 04074 #define USB_USBCTRL_PDE_MASK 0x40u 04075 #define USB_USBCTRL_PDE_SHIFT 6 04076 #define USB_USBCTRL_SUSP_MASK 0x80u 04077 #define USB_USBCTRL_SUSP_SHIFT 7 04078 /* OBSERVE Bit Fields */ 04079 #define USB_OBSERVE_DMPD_MASK 0x10u 04080 #define USB_OBSERVE_DMPD_SHIFT 4 04081 #define USB_OBSERVE_DPPD_MASK 0x40u 04082 #define USB_OBSERVE_DPPD_SHIFT 6 04083 #define USB_OBSERVE_DPPU_MASK 0x80u 04084 #define USB_OBSERVE_DPPU_SHIFT 7 04085 /* CONTROL Bit Fields */ 04086 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u 04087 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 04088 /* USBTRC0 Bit Fields */ 04089 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u 04090 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 04091 #define USB_USBTRC0_SYNC_DET_MASK 0x2u 04092 #define USB_USBTRC0_SYNC_DET_SHIFT 1 04093 #define USB_USBTRC0_USBRESMEN_MASK 0x20u 04094 #define USB_USBTRC0_USBRESMEN_SHIFT 5 04095 #define USB_USBTRC0_USBRESET_MASK 0x80u 04096 #define USB_USBTRC0_USBRESET_SHIFT 7 04097 04098 /** 04099 * @} 04100 */ /* end of group USB_Register_Masks */ 04101 04102 04103 /* USB - Peripheral instance base addresses */ 04104 /** Peripheral USB0 base address */ 04105 #define USB0_BASE (0x40072000u) 04106 /** Peripheral USB0 base pointer */ 04107 #define USB0 ((USB_Type *)USB0_BASE) 04108 /** Array initializer of USB peripheral base pointers */ 04109 #define USB_BASES { USB0 } 04110 04111 /** 04112 * @} 04113 */ /* end of group USB_Peripheral_Access_Layer */ 04114 04115 04116 /* 04117 ** End of section using anonymous unions 04118 */ 04119 04120 #if defined(__ARMCC_VERSION) 04121 #pragma pop 04122 #elif defined(__CWCC__) 04123 #pragma pop 04124 #elif defined(__GNUC__) 04125 /* leave anonymous unions enabled */ 04126 #elif defined(__IAR_SYSTEMS_ICC__) 04127 #pragma language=default 04128 #else 04129 #error Not supported compiler type 04130 #endif 04131 04132 /** 04133 * @} 04134 */ /* end of group Peripheral_access_layer */ 04135 04136 04137 /* ---------------------------------------------------------------------------- 04138 -- Backward Compatibility 04139 ---------------------------------------------------------------------------- */ 04140 04141 /** 04142 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility 04143 * @{ 04144 */ 04145 04146 /* No backward compatibility issues. */ 04147 04148 /** 04149 * @} 04150 */ /* end of group Backward_Compatibility_Symbols */ 04151 04152 04153 #endif /* #if !defined(MKL25Z4_H_) */ 04154 04155 /* MKL25Z4.h, eof. */
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