rau cha / mbed-src-I2CWaitFix

fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088

Fork of mbed-src by mbed official

Embed: (wiki syntax)

« Back to documentation index

ADC_Type Struct Reference
Data Fields

ADC_Type Struct Reference
[ADC Peripheral Access Layer]

ADC - Register Layout Typedef. More...

#include <MKL25Z4.h>

Data Fields

__IO uint32_t SC1 [2]
 ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4.
__IO uint32_t CFG1
 ADC Configuration Register 1, offset: 0x8.
__IO uint32_t CFG2
 ADC Configuration Register 2, offset: 0xC.
__I uint32_t R [2]
 ADC Data Result Register, array offset: 0x10, array step: 0x4.
__IO uint32_t CV1
 Compare Value Registers, offset: 0x18.
__IO uint32_t CV2
 Compare Value Registers, offset: 0x1C.
__IO uint32_t SC2
 Status and Control Register 2, offset: 0x20.
__IO uint32_t SC3
 Status and Control Register 3, offset: 0x24.
__IO uint32_t OFS
 ADC Offset Correction Register, offset: 0x28.
__IO uint32_t PG
 ADC Plus-Side Gain Register, offset: 0x2C.
__IO uint32_t MG
 ADC Minus-Side Gain Register, offset: 0x30.
__IO uint32_t CLPD
 ADC Plus-Side General Calibration Value Register, offset: 0x34.
__IO uint32_t CLPS
 ADC Plus-Side General Calibration Value Register, offset: 0x38.
__IO uint32_t CLP4
 ADC Plus-Side General Calibration Value Register, offset: 0x3C.
__IO uint32_t CLP3
 ADC Plus-Side General Calibration Value Register, offset: 0x40.
__IO uint32_t CLP2
 ADC Plus-Side General Calibration Value Register, offset: 0x44.
__IO uint32_t CLP1
 ADC Plus-Side General Calibration Value Register, offset: 0x48.
__IO uint32_t CLP0
 ADC Plus-Side General Calibration Value Register, offset: 0x4C.
__IO uint32_t CLMD
 ADC Minus-Side General Calibration Value Register, offset: 0x54.
__IO uint32_t CLMS
 ADC Minus-Side General Calibration Value Register, offset: 0x58.
__IO uint32_t CLM4
 ADC Minus-Side General Calibration Value Register, offset: 0x5C.
__IO uint32_t CLM3
 ADC Minus-Side General Calibration Value Register, offset: 0x60.
__IO uint32_t CLM2
 ADC Minus-Side General Calibration Value Register, offset: 0x64.
__IO uint32_t CLM1
 ADC Minus-Side General Calibration Value Register, offset: 0x68.
__IO uint32_t CLM0
 ADC Minus-Side General Calibration Value Register, offset: 0x6C.

Detailed Description

ADC - Register Layout Typedef.

Definition at line 167 of file MKL25Z4.h.

Field Documentation

__IO uint32_t CFG1

ADC Configuration Register 1, offset: 0x8.

Definition at line 169 of file MKL25Z4.h.

__IO uint32_t CFG2

ADC Configuration Register 2, offset: 0xC.

Definition at line 170 of file MKL25Z4.h.

__IO uint32_t CLM0

ADC Minus-Side General Calibration Value Register, offset: 0x6C.

Definition at line 193 of file MKL25Z4.h.

__IO uint32_t CLM1

ADC Minus-Side General Calibration Value Register, offset: 0x68.

Definition at line 192 of file MKL25Z4.h.

__IO uint32_t CLM2

ADC Minus-Side General Calibration Value Register, offset: 0x64.

Definition at line 191 of file MKL25Z4.h.

__IO uint32_t CLM3

ADC Minus-Side General Calibration Value Register, offset: 0x60.

Definition at line 190 of file MKL25Z4.h.

__IO uint32_t CLM4

ADC Minus-Side General Calibration Value Register, offset: 0x5C.

Definition at line 189 of file MKL25Z4.h.

__IO uint32_t CLMD

ADC Minus-Side General Calibration Value Register, offset: 0x54.

Definition at line 187 of file MKL25Z4.h.

__IO uint32_t CLMS

ADC Minus-Side General Calibration Value Register, offset: 0x58.

Definition at line 188 of file MKL25Z4.h.

__IO uint32_t CLP0

ADC Plus-Side General Calibration Value Register, offset: 0x4C.

Definition at line 185 of file MKL25Z4.h.

__IO uint32_t CLP1

ADC Plus-Side General Calibration Value Register, offset: 0x48.

Definition at line 184 of file MKL25Z4.h.

__IO uint32_t CLP2

ADC Plus-Side General Calibration Value Register, offset: 0x44.

Definition at line 183 of file MKL25Z4.h.

__IO uint32_t CLP3

ADC Plus-Side General Calibration Value Register, offset: 0x40.

Definition at line 182 of file MKL25Z4.h.

__IO uint32_t CLP4

ADC Plus-Side General Calibration Value Register, offset: 0x3C.

Definition at line 181 of file MKL25Z4.h.

__IO uint32_t CLPD

ADC Plus-Side General Calibration Value Register, offset: 0x34.

Definition at line 179 of file MKL25Z4.h.

__IO uint32_t CLPS

ADC Plus-Side General Calibration Value Register, offset: 0x38.

Definition at line 180 of file MKL25Z4.h.

__IO uint32_t CV1

Compare Value Registers, offset: 0x18.

Definition at line 172 of file MKL25Z4.h.

__IO uint32_t CV2

Compare Value Registers, offset: 0x1C.

Definition at line 173 of file MKL25Z4.h.

__IO uint32_t MG

ADC Minus-Side Gain Register, offset: 0x30.

Definition at line 178 of file MKL25Z4.h.

__IO uint32_t OFS

ADC Offset Correction Register, offset: 0x28.

Definition at line 176 of file MKL25Z4.h.

__IO uint32_t PG

ADC Plus-Side Gain Register, offset: 0x2C.

Definition at line 177 of file MKL25Z4.h.

__I uint32_t R[2]

ADC Data Result Register, array offset: 0x10, array step: 0x4.

Definition at line 171 of file MKL25Z4.h.

__IO uint32_t SC1[2]

ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4.

Definition at line 168 of file MKL25Z4.h.

__IO uint32_t SC2

Status and Control Register 2, offset: 0x20.

Definition at line 174 of file MKL25Z4.h.

__IO uint32_t SC3

Status and Control Register 3, offset: 0x24.

Definition at line 175 of file MKL25Z4.h.

Generated on Tue Jul 12 2022 13:47:03 by  doxygen 1.7.2