fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088

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PIT_Type Struct Reference

PIT_Type Struct Reference
[PIT Peripheral Access Layer]

PIT - Register Layout Typedef. More...

#include <MKL25Z4.h>

Data Fields

__IO uint32_t MCR
 PIT Module Control Register, offset: 0x0.
__I uint32_t LTMR64H
 PIT Upper Lifetime Timer Register, offset: 0xE0.
__I uint32_t LTMR64L
 PIT Lower Lifetime Timer Register, offset: 0xE4.
__IO uint32_t LDVAL
 Timer Load Value Register, array offset: 0x100, array step: 0x10.
__I uint32_t CVAL
 Current Timer Value Register, array offset: 0x104, array step: 0x10.
__IO uint32_t TCTRL
 Timer Control Register, array offset: 0x108, array step: 0x10.
__IO uint32_t TFLG
 Timer Flag Register, array offset: 0x10C, array step: 0x10.

Detailed Description

PIT - Register Layout Typedef.

Definition at line 2185 of file MKL25Z4.h.


Field Documentation

__I uint32_t CVAL

Current Timer Value Register, array offset: 0x104, array step: 0x10.

Definition at line 2193 of file MKL25Z4.h.

__IO uint32_t LDVAL

Timer Load Value Register, array offset: 0x100, array step: 0x10.

Definition at line 2192 of file MKL25Z4.h.

__I uint32_t LTMR64H

PIT Upper Lifetime Timer Register, offset: 0xE0.

Definition at line 2188 of file MKL25Z4.h.

__I uint32_t LTMR64L

PIT Lower Lifetime Timer Register, offset: 0xE4.

Definition at line 2189 of file MKL25Z4.h.

__IO uint32_t MCR

PIT Module Control Register, offset: 0x0.

Definition at line 2186 of file MKL25Z4.h.

__IO uint32_t TCTRL

Timer Control Register, array offset: 0x108, array step: 0x10.

Definition at line 2194 of file MKL25Z4.h.

__IO uint32_t TFLG

Timer Flag Register, array offset: 0x10C, array step: 0x10.

Definition at line 2195 of file MKL25Z4.h.