fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088
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SIM_Type Struct Reference
SIM - Register Layout Typedef.
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#include <MKL25Z4.h >
__IO uint32_t SOPT1 System Options Register 1, offset: 0x0. __IO uint32_t SOPT1CFG SOPT1 Configuration Register, offset: 0x4. __IO uint32_t SOPT2 System Options Register 2, offset: 0x1004. __IO uint32_t SOPT4 System Options Register 4, offset: 0x100C. __IO uint32_t SOPT5 System Options Register 5, offset: 0x1010. __IO uint32_t SOPT7 System Options Register 7, offset: 0x1018. __I uint32_t SDID System Device Identification Register, offset: 0x1024. __IO uint32_t SCGC4 System Clock Gating Control Register 4, offset: 0x1034. __IO uint32_t SCGC5 System Clock Gating Control Register 5, offset: 0x1038. __IO uint32_t SCGC6 System Clock Gating Control Register 6, offset: 0x103C. __IO uint32_t SCGC7 System Clock Gating Control Register 7, offset: 0x1040. __IO uint32_t CLKDIV1 System Clock Divider Register 1, offset: 0x1044. __IO uint32_t FCFG1 Flash Configuration Register 1, offset: 0x104C. __I uint32_t FCFG2 Flash Configuration Register 2, offset: 0x1050. __I uint32_t UIDMH Unique Identification Register Mid-High, offset: 0x1058. __I uint32_t UIDML Unique Identification Register Mid Low, offset: 0x105C. __I uint32_t UIDL Unique Identification Register Low, offset: 0x1060. __IO uint32_t COPC COP Control Register, offset: 0x1100. __O uint32_t SRVCOP Service COP Register, offset: 0x1104.
Detailed Description
SIM - Register Layout Typedef.
Definition at line 2748 of file MKL25Z4.h .
Field Documentation
System Clock Divider Register 1, offset: 0x1044.
Definition at line 2765 of file MKL25Z4.h .
COP Control Register, offset: 0x1100.
Definition at line 2774 of file MKL25Z4.h .
Flash Configuration Register 1, offset: 0x104C.
Definition at line 2767 of file MKL25Z4.h .
Flash Configuration Register 2, offset: 0x1050.
Definition at line 2768 of file MKL25Z4.h .
System Clock Gating Control Register 4, offset: 0x1034.
Definition at line 2761 of file MKL25Z4.h .
System Clock Gating Control Register 5, offset: 0x1038.
Definition at line 2762 of file MKL25Z4.h .
System Clock Gating Control Register 6, offset: 0x103C.
Definition at line 2763 of file MKL25Z4.h .
System Clock Gating Control Register 7, offset: 0x1040.
Definition at line 2764 of file MKL25Z4.h .
System Device Identification Register, offset: 0x1024.
Definition at line 2759 of file MKL25Z4.h .
System Options Register 1, offset: 0x0.
Definition at line 2749 of file MKL25Z4.h .
SOPT1 Configuration Register, offset: 0x4.
Definition at line 2750 of file MKL25Z4.h .
System Options Register 2, offset: 0x1004.
Definition at line 2752 of file MKL25Z4.h .
System Options Register 4, offset: 0x100C.
Definition at line 2754 of file MKL25Z4.h .
System Options Register 5, offset: 0x1010.
Definition at line 2755 of file MKL25Z4.h .
System Options Register 7, offset: 0x1018.
Definition at line 2757 of file MKL25Z4.h .
Service COP Register, offset: 0x1104.
Definition at line 2775 of file MKL25Z4.h .
Unique Identification Register Low, offset: 0x1060.
Definition at line 2772 of file MKL25Z4.h .
Unique Identification Register Mid-High, offset: 0x1058.
Definition at line 2770 of file MKL25Z4.h .
Unique Identification Register Mid Low, offset: 0x105C.
Definition at line 2771 of file MKL25Z4.h .
rau cha
mbed official
1.7.2