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target-mcu-k64f
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MK64F12_sim.h
00001 /* 00002 ** ################################################################### 00003 ** Compilers: Keil ARM C/C++ Compiler 00004 ** Freescale C/C++ for Embedded ARM 00005 ** GNU C Compiler 00006 ** IAR ANSI C/C++ Compiler for ARM 00007 ** 00008 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 00009 ** Version: rev. 2.5, 2014-02-10 00010 ** Build: b140604 00011 ** 00012 ** Abstract: 00013 ** Extension to the CMSIS register access layer header. 00014 ** 00015 ** Copyright (c) 2014 Freescale Semiconductor, Inc. 00016 ** All rights reserved. 00017 ** 00018 ** (C) COPYRIGHT 2015-2015 ARM Limited 00019 ** ALL RIGHTS RESERVED 00020 ** 00021 ** Redistribution and use in source and binary forms, with or without modification, 00022 ** are permitted provided that the following conditions are met: 00023 ** 00024 ** o Redistributions of source code must retain the above copyright notice, this list 00025 ** of conditions and the following disclaimer. 00026 ** 00027 ** o Redistributions in binary form must reproduce the above copyright notice, this 00028 ** list of conditions and the following disclaimer in the documentation and/or 00029 ** other materials provided with the distribution. 00030 ** 00031 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00032 ** contributors may be used to endorse or promote products derived from this 00033 ** software without specific prior written permission. 00034 ** 00035 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00036 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00037 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00038 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00039 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00040 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00041 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00042 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00043 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00044 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00045 ** 00046 ** http: www.freescale.com 00047 ** mail: support@freescale.com 00048 ** 00049 ** Revisions: 00050 ** - rev. 1.0 (2013-08-12) 00051 ** Initial version. 00052 ** - rev. 2.0 (2013-10-29) 00053 ** Register accessor macros added to the memory map. 00054 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00055 ** Startup file for gcc has been updated according to CMSIS 3.2. 00056 ** System initialization updated. 00057 ** MCG - registers updated. 00058 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00059 ** - rev. 2.1 (2013-10-30) 00060 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00061 ** - rev. 2.2 (2013-12-09) 00062 ** DMA - EARS register removed. 00063 ** AIPS0, AIPS1 - MPRA register updated. 00064 ** - rev. 2.3 (2014-01-24) 00065 ** Update according to reference manual rev. 2 00066 ** ENET, MCG, MCM, SIM, USB - registers updated 00067 ** - rev. 2.4 (2014-02-10) 00068 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00069 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00070 ** - rev. 2.5 (2014-02-10) 00071 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00072 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00073 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00074 ** - rev. 2.6 (2015-08-03) (ARM) 00075 ** All accesses to memory are replaced by equivalent macros; this allows 00076 ** memory read/write operations to be re-defined if needed (for example, 00077 ** to implement new security features 00078 ** 00079 ** ################################################################### 00080 */ 00081 00082 /* 00083 * WARNING! DO NOT EDIT THIS FILE DIRECTLY! 00084 * 00085 * This file was generated automatically and any changes may be lost. 00086 */ 00087 #ifndef __HW_SIM_REGISTERS_H__ 00088 #define __HW_SIM_REGISTERS_H__ 00089 00090 #include "MK64F12.h" 00091 #include "fsl_bitaccess.h" 00092 00093 /* 00094 * MK64F12 SIM 00095 * 00096 * System Integration Module 00097 * 00098 * Registers defined in this header file: 00099 * - HW_SIM_SOPT1 - System Options Register 1 00100 * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register 00101 * - HW_SIM_SOPT2 - System Options Register 2 00102 * - HW_SIM_SOPT4 - System Options Register 4 00103 * - HW_SIM_SOPT5 - System Options Register 5 00104 * - HW_SIM_SOPT7 - System Options Register 7 00105 * - HW_SIM_SDID - System Device Identification Register 00106 * - HW_SIM_SCGC1 - System Clock Gating Control Register 1 00107 * - HW_SIM_SCGC2 - System Clock Gating Control Register 2 00108 * - HW_SIM_SCGC3 - System Clock Gating Control Register 3 00109 * - HW_SIM_SCGC4 - System Clock Gating Control Register 4 00110 * - HW_SIM_SCGC5 - System Clock Gating Control Register 5 00111 * - HW_SIM_SCGC6 - System Clock Gating Control Register 6 00112 * - HW_SIM_SCGC7 - System Clock Gating Control Register 7 00113 * - HW_SIM_CLKDIV1 - System Clock Divider Register 1 00114 * - HW_SIM_CLKDIV2 - System Clock Divider Register 2 00115 * - HW_SIM_FCFG1 - Flash Configuration Register 1 00116 * - HW_SIM_FCFG2 - Flash Configuration Register 2 00117 * - HW_SIM_UIDH - Unique Identification Register High 00118 * - HW_SIM_UIDMH - Unique Identification Register Mid-High 00119 * - HW_SIM_UIDML - Unique Identification Register Mid Low 00120 * - HW_SIM_UIDL - Unique Identification Register Low 00121 * 00122 * - hw_sim_t - Struct containing all module registers. 00123 */ 00124 00125 #define HW_SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */ 00126 00127 /******************************************************************************* 00128 * HW_SIM_SOPT1 - System Options Register 1 00129 ******************************************************************************/ 00130 00131 /*! 00132 * @brief HW_SIM_SOPT1 - System Options Register 1 (RW) 00133 * 00134 * Reset value: 0x80000000U 00135 * 00136 * The SOPT1 register is only reset on POR or LVD. 00137 */ 00138 typedef union _hw_sim_sopt1 00139 { 00140 uint32_t U; 00141 struct _hw_sim_sopt1_bitfields 00142 { 00143 uint32_t RESERVED0 : 12; /*!< [11:0] */ 00144 uint32_t RAMSIZE : 4; /*!< [15:12] RAM size */ 00145 uint32_t RESERVED1 : 2; /*!< [17:16] */ 00146 uint32_t OSC32KSEL : 2; /*!< [19:18] 32K oscillator clock select */ 00147 uint32_t RESERVED2 : 9; /*!< [28:20] */ 00148 uint32_t USBVSTBY : 1; /*!< [29] USB voltage regulator in standby 00149 * mode during VLPR and VLPW modes */ 00150 uint32_t USBSSTBY : 1; /*!< [30] USB voltage regulator in standby 00151 * mode during Stop, VLPS, LLS and VLLS modes. */ 00152 uint32_t USBREGEN : 1; /*!< [31] USB voltage regulator enable */ 00153 } B; 00154 } hw_sim_sopt1_t; 00155 00156 /*! 00157 * @name Constants and macros for entire SIM_SOPT1 register 00158 */ 00159 /*@{*/ 00160 #define HW_SIM_SOPT1_ADDR(x) ((x) + 0x0U) 00161 00162 #define HW_SIM_SOPT1(x) (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR(x)) 00163 #define HW_SIM_SOPT1_RD(x) (ADDRESS_READ(hw_sim_sopt1_t, HW_SIM_SOPT1_ADDR(x))) 00164 #define HW_SIM_SOPT1_WR(x, v) (ADDRESS_WRITE(hw_sim_sopt1_t, HW_SIM_SOPT1_ADDR(x), v)) 00165 #define HW_SIM_SOPT1_SET(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) | (v))) 00166 #define HW_SIM_SOPT1_CLR(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) & ~(v))) 00167 #define HW_SIM_SOPT1_TOG(x, v) (HW_SIM_SOPT1_WR(x, HW_SIM_SOPT1_RD(x) ^ (v))) 00168 /*@}*/ 00169 00170 /* 00171 * Constants & macros for individual SIM_SOPT1 bitfields 00172 */ 00173 00174 /*! 00175 * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO) 00176 * 00177 * This field specifies the amount of system RAM available on the device. 00178 * 00179 * Values: 00180 * - 0001 - 8 KB 00181 * - 0011 - 16 KB 00182 * - 0100 - 24 KB 00183 * - 0101 - 32 KB 00184 * - 0110 - 48 KB 00185 * - 0111 - 64 KB 00186 * - 1000 - 96 KB 00187 * - 1001 - 128 KB 00188 * - 1011 - 256 KB 00189 */ 00190 /*@{*/ 00191 #define BP_SIM_SOPT1_RAMSIZE (12U) /*!< Bit position for SIM_SOPT1_RAMSIZE. */ 00192 #define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) /*!< Bit mask for SIM_SOPT1_RAMSIZE. */ 00193 #define BS_SIM_SOPT1_RAMSIZE (4U) /*!< Bit field size in bits for SIM_SOPT1_RAMSIZE. */ 00194 00195 /*! @brief Read current value of the SIM_SOPT1_RAMSIZE field. */ 00196 #define BR_SIM_SOPT1_RAMSIZE(x) (UNION_READ(hw_sim_sopt1_t, HW_SIM_SOPT1_ADDR(x), U, B.RAMSIZE)) 00197 /*@}*/ 00198 00199 /*! 00200 * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW) 00201 * 00202 * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset 00203 * only on POR/LVD. 00204 * 00205 * Values: 00206 * - 00 - System oscillator (OSC32KCLK) 00207 * - 01 - Reserved 00208 * - 10 - RTC 32.768kHz oscillator 00209 * - 11 - LPO 1 kHz 00210 */ 00211 /*@{*/ 00212 #define BP_SIM_SOPT1_OSC32KSEL (18U) /*!< Bit position for SIM_SOPT1_OSC32KSEL. */ 00213 #define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) /*!< Bit mask for SIM_SOPT1_OSC32KSEL. */ 00214 #define BS_SIM_SOPT1_OSC32KSEL (2U) /*!< Bit field size in bits for SIM_SOPT1_OSC32KSEL. */ 00215 00216 /*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */ 00217 #define BR_SIM_SOPT1_OSC32KSEL(x) (UNION_READ(hw_sim_sopt1_t, HW_SIM_SOPT1_ADDR(x), U, B.OSC32KSEL)) 00218 00219 /*! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL. */ 00220 #define BF_SIM_SOPT1_OSC32KSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_OSC32KSEL) & BM_SIM_SOPT1_OSC32KSEL) 00221 00222 /*! @brief Set the OSC32KSEL field to a new value. */ 00223 #define BW_SIM_SOPT1_OSC32KSEL(x, v) (HW_SIM_SOPT1_WR(x, (HW_SIM_SOPT1_RD(x) & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v))) 00224 /*@}*/ 00225 00226 /*! 00227 * @name Register SIM_SOPT1, field USBVSTBY[29] (RW) 00228 * 00229 * Controls whether the USB voltage regulator is placed in standby mode during 00230 * VLPR and VLPW modes. 00231 * 00232 * Values: 00233 * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes. 00234 * - 1 - USB voltage regulator in standby during VLPR and VLPW modes. 00235 */ 00236 /*@{*/ 00237 #define BP_SIM_SOPT1_USBVSTBY (29U) /*!< Bit position for SIM_SOPT1_USBVSTBY. */ 00238 #define BM_SIM_SOPT1_USBVSTBY (0x20000000U) /*!< Bit mask for SIM_SOPT1_USBVSTBY. */ 00239 #define BS_SIM_SOPT1_USBVSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBVSTBY. */ 00240 00241 /*! @brief Read current value of the SIM_SOPT1_USBVSTBY field. */ 00242 #define BR_SIM_SOPT1_USBVSTBY(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY))) 00243 00244 /*! @brief Format value for bitfield SIM_SOPT1_USBVSTBY. */ 00245 #define BF_SIM_SOPT1_USBVSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBVSTBY) & BM_SIM_SOPT1_USBVSTBY) 00246 00247 /*! @brief Set the USBVSTBY field to a new value. */ 00248 #define BW_SIM_SOPT1_USBVSTBY(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBVSTBY), v)) 00249 /*@}*/ 00250 00251 /*! 00252 * @name Register SIM_SOPT1, field USBSSTBY[30] (RW) 00253 * 00254 * Controls whether the USB voltage regulator is placed in standby mode during 00255 * Stop, VLPS, LLS and VLLS modes. 00256 * 00257 * Values: 00258 * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS 00259 * modes. 00260 * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. 00261 */ 00262 /*@{*/ 00263 #define BP_SIM_SOPT1_USBSSTBY (30U) /*!< Bit position for SIM_SOPT1_USBSSTBY. */ 00264 #define BM_SIM_SOPT1_USBSSTBY (0x40000000U) /*!< Bit mask for SIM_SOPT1_USBSSTBY. */ 00265 #define BS_SIM_SOPT1_USBSSTBY (1U) /*!< Bit field size in bits for SIM_SOPT1_USBSSTBY. */ 00266 00267 /*! @brief Read current value of the SIM_SOPT1_USBSSTBY field. */ 00268 #define BR_SIM_SOPT1_USBSSTBY(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY))) 00269 00270 /*! @brief Format value for bitfield SIM_SOPT1_USBSSTBY. */ 00271 #define BF_SIM_SOPT1_USBSSTBY(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBSSTBY) & BM_SIM_SOPT1_USBSSTBY) 00272 00273 /*! @brief Set the USBSSTBY field to a new value. */ 00274 #define BW_SIM_SOPT1_USBSSTBY(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBSSTBY), v)) 00275 /*@}*/ 00276 00277 /*! 00278 * @name Register SIM_SOPT1, field USBREGEN[31] (RW) 00279 * 00280 * Controls whether the USB voltage regulator is enabled. 00281 * 00282 * Values: 00283 * - 0 - USB voltage regulator is disabled. 00284 * - 1 - USB voltage regulator is enabled. 00285 */ 00286 /*@{*/ 00287 #define BP_SIM_SOPT1_USBREGEN (31U) /*!< Bit position for SIM_SOPT1_USBREGEN. */ 00288 #define BM_SIM_SOPT1_USBREGEN (0x80000000U) /*!< Bit mask for SIM_SOPT1_USBREGEN. */ 00289 #define BS_SIM_SOPT1_USBREGEN (1U) /*!< Bit field size in bits for SIM_SOPT1_USBREGEN. */ 00290 00291 /*! @brief Read current value of the SIM_SOPT1_USBREGEN field. */ 00292 #define BR_SIM_SOPT1_USBREGEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN))) 00293 00294 /*! @brief Format value for bitfield SIM_SOPT1_USBREGEN. */ 00295 #define BF_SIM_SOPT1_USBREGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1_USBREGEN) & BM_SIM_SOPT1_USBREGEN) 00296 00297 /*! @brief Set the USBREGEN field to a new value. */ 00298 #define BW_SIM_SOPT1_USBREGEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1_ADDR(x), BP_SIM_SOPT1_USBREGEN), v)) 00299 /*@}*/ 00300 00301 /******************************************************************************* 00302 * HW_SIM_SOPT1CFG - SOPT1 Configuration Register 00303 ******************************************************************************/ 00304 00305 /*! 00306 * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW) 00307 * 00308 * Reset value: 0x00000000U 00309 * 00310 * The SOPT1CFG register is reset on System Reset not VLLS. 00311 */ 00312 typedef union _hw_sim_sopt1cfg 00313 { 00314 uint32_t U; 00315 struct _hw_sim_sopt1cfg_bitfields 00316 { 00317 uint32_t RESERVED0 : 24; /*!< [23:0] */ 00318 uint32_t URWE : 1; /*!< [24] USB voltage regulator enable write 00319 * enable */ 00320 uint32_t UVSWE : 1; /*!< [25] USB voltage regulator VLP standby write 00321 * enable */ 00322 uint32_t USSWE : 1; /*!< [26] USB voltage regulator stop standby 00323 * write enable */ 00324 uint32_t RESERVED1 : 5; /*!< [31:27] */ 00325 } B; 00326 } hw_sim_sopt1cfg_t; 00327 00328 /*! 00329 * @name Constants and macros for entire SIM_SOPT1CFG register 00330 */ 00331 /*@{*/ 00332 #define HW_SIM_SOPT1CFG_ADDR(x) ((x) + 0x4U) 00333 00334 #define HW_SIM_SOPT1CFG(x) (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR(x)) 00335 #define HW_SIM_SOPT1CFG_RD(x) (ADDRESS_READ(hw_sim_sopt1cfg_t, HW_SIM_SOPT1CFG_ADDR(x))) 00336 #define HW_SIM_SOPT1CFG_WR(x, v) (ADDRESS_WRITE(hw_sim_sopt1cfg_t, HW_SIM_SOPT1CFG_ADDR(x), v)) 00337 #define HW_SIM_SOPT1CFG_SET(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) | (v))) 00338 #define HW_SIM_SOPT1CFG_CLR(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) & ~(v))) 00339 #define HW_SIM_SOPT1CFG_TOG(x, v) (HW_SIM_SOPT1CFG_WR(x, HW_SIM_SOPT1CFG_RD(x) ^ (v))) 00340 /*@}*/ 00341 00342 /* 00343 * Constants & macros for individual SIM_SOPT1CFG bitfields 00344 */ 00345 00346 /*! 00347 * @name Register SIM_SOPT1CFG, field URWE[24] (RW) 00348 * 00349 * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This 00350 * register bit clears after a write to USBREGEN. 00351 * 00352 * Values: 00353 * - 0 - SOPT1 USBREGEN cannot be written. 00354 * - 1 - SOPT1 USBREGEN can be written. 00355 */ 00356 /*@{*/ 00357 #define BP_SIM_SOPT1CFG_URWE (24U) /*!< Bit position for SIM_SOPT1CFG_URWE. */ 00358 #define BM_SIM_SOPT1CFG_URWE (0x01000000U) /*!< Bit mask for SIM_SOPT1CFG_URWE. */ 00359 #define BS_SIM_SOPT1CFG_URWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_URWE. */ 00360 00361 /*! @brief Read current value of the SIM_SOPT1CFG_URWE field. */ 00362 #define BR_SIM_SOPT1CFG_URWE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE))) 00363 00364 /*! @brief Format value for bitfield SIM_SOPT1CFG_URWE. */ 00365 #define BF_SIM_SOPT1CFG_URWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_URWE) & BM_SIM_SOPT1CFG_URWE) 00366 00367 /*! @brief Set the URWE field to a new value. */ 00368 #define BW_SIM_SOPT1CFG_URWE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_URWE), v)) 00369 /*@}*/ 00370 00371 /*! 00372 * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW) 00373 * 00374 * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. 00375 * This register bit clears after a write to USBVSTBY. 00376 * 00377 * Values: 00378 * - 0 - SOPT1 USBVSTBY cannot be written. 00379 * - 1 - SOPT1 USBVSTBY can be written. 00380 */ 00381 /*@{*/ 00382 #define BP_SIM_SOPT1CFG_UVSWE (25U) /*!< Bit position for SIM_SOPT1CFG_UVSWE. */ 00383 #define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) /*!< Bit mask for SIM_SOPT1CFG_UVSWE. */ 00384 #define BS_SIM_SOPT1CFG_UVSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_UVSWE. */ 00385 00386 /*! @brief Read current value of the SIM_SOPT1CFG_UVSWE field. */ 00387 #define BR_SIM_SOPT1CFG_UVSWE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE))) 00388 00389 /*! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE. */ 00390 #define BF_SIM_SOPT1CFG_UVSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_UVSWE) & BM_SIM_SOPT1CFG_UVSWE) 00391 00392 /*! @brief Set the UVSWE field to a new value. */ 00393 #define BW_SIM_SOPT1CFG_UVSWE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_UVSWE), v)) 00394 /*@}*/ 00395 00396 /*! 00397 * @name Register SIM_SOPT1CFG, field USSWE[26] (RW) 00398 * 00399 * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. 00400 * This register bit clears after a write to USBSSTBY. 00401 * 00402 * Values: 00403 * - 0 - SOPT1 USBSSTBY cannot be written. 00404 * - 1 - SOPT1 USBSSTBY can be written. 00405 */ 00406 /*@{*/ 00407 #define BP_SIM_SOPT1CFG_USSWE (26U) /*!< Bit position for SIM_SOPT1CFG_USSWE. */ 00408 #define BM_SIM_SOPT1CFG_USSWE (0x04000000U) /*!< Bit mask for SIM_SOPT1CFG_USSWE. */ 00409 #define BS_SIM_SOPT1CFG_USSWE (1U) /*!< Bit field size in bits for SIM_SOPT1CFG_USSWE. */ 00410 00411 /*! @brief Read current value of the SIM_SOPT1CFG_USSWE field. */ 00412 #define BR_SIM_SOPT1CFG_USSWE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE))) 00413 00414 /*! @brief Format value for bitfield SIM_SOPT1CFG_USSWE. */ 00415 #define BF_SIM_SOPT1CFG_USSWE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT1CFG_USSWE) & BM_SIM_SOPT1CFG_USSWE) 00416 00417 /*! @brief Set the USSWE field to a new value. */ 00418 #define BW_SIM_SOPT1CFG_USSWE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT1CFG_ADDR(x), BP_SIM_SOPT1CFG_USSWE), v)) 00419 /*@}*/ 00420 00421 /******************************************************************************* 00422 * HW_SIM_SOPT2 - System Options Register 2 00423 ******************************************************************************/ 00424 00425 /*! 00426 * @brief HW_SIM_SOPT2 - System Options Register 2 (RW) 00427 * 00428 * Reset value: 0x00001000U 00429 * 00430 * SOPT2 contains the controls for selecting many of the module clock source 00431 * options on this device. See the Clock Distribution chapter for more information 00432 * including clocking diagrams and definitions of device clocks. 00433 */ 00434 typedef union _hw_sim_sopt2 00435 { 00436 uint32_t U; 00437 struct _hw_sim_sopt2_bitfields 00438 { 00439 uint32_t RESERVED0 : 4; /*!< [3:0] */ 00440 uint32_t RTCCLKOUTSEL : 1; /*!< [4] RTC clock out select */ 00441 uint32_t CLKOUTSEL : 3; /*!< [7:5] CLKOUT select */ 00442 uint32_t FBSL : 2; /*!< [9:8] FlexBus security level */ 00443 uint32_t RESERVED1 : 1; /*!< [10] */ 00444 uint32_t PTD7PAD : 1; /*!< [11] PTD7 pad drive strength */ 00445 uint32_t TRACECLKSEL : 1; /*!< [12] Debug trace clock select */ 00446 uint32_t RESERVED2 : 3; /*!< [15:13] */ 00447 uint32_t PLLFLLSEL : 2; /*!< [17:16] PLL/FLL clock select */ 00448 uint32_t USBSRC : 1; /*!< [18] USB clock source select */ 00449 uint32_t RMIISRC : 1; /*!< [19] RMII clock source select */ 00450 uint32_t TIMESRC : 2; /*!< [21:20] IEEE 1588 timestamp clock source 00451 * select */ 00452 uint32_t RESERVED3 : 6; /*!< [27:22] */ 00453 uint32_t SDHCSRC : 2; /*!< [29:28] SDHC clock source select */ 00454 uint32_t RESERVED4 : 2; /*!< [31:30] */ 00455 } B; 00456 } hw_sim_sopt2_t; 00457 00458 /*! 00459 * @name Constants and macros for entire SIM_SOPT2 register 00460 */ 00461 /*@{*/ 00462 #define HW_SIM_SOPT2_ADDR(x) ((x) + 0x1004U) 00463 00464 #define HW_SIM_SOPT2(x) (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR(x)) 00465 #define HW_SIM_SOPT2_RD(x) (ADDRESS_READ(hw_sim_sopt2_t, HW_SIM_SOPT2_ADDR(x))) 00466 #define HW_SIM_SOPT2_WR(x, v) (ADDRESS_WRITE(hw_sim_sopt2_t, HW_SIM_SOPT2_ADDR(x), v)) 00467 #define HW_SIM_SOPT2_SET(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) | (v))) 00468 #define HW_SIM_SOPT2_CLR(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) & ~(v))) 00469 #define HW_SIM_SOPT2_TOG(x, v) (HW_SIM_SOPT2_WR(x, HW_SIM_SOPT2_RD(x) ^ (v))) 00470 /*@}*/ 00471 00472 /* 00473 * Constants & macros for individual SIM_SOPT2 bitfields 00474 */ 00475 00476 /*! 00477 * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW) 00478 * 00479 * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the 00480 * RTC_CLKOUT pin. 00481 * 00482 * Values: 00483 * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin. 00484 * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin. 00485 */ 00486 /*@{*/ 00487 #define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) /*!< Bit position for SIM_SOPT2_RTCCLKOUTSEL. */ 00488 #define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) /*!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL. */ 00489 #define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL. */ 00490 00491 /*! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field. */ 00492 #define BR_SIM_SOPT2_RTCCLKOUTSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL))) 00493 00494 /*! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL. */ 00495 #define BF_SIM_SOPT2_RTCCLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RTCCLKOUTSEL) & BM_SIM_SOPT2_RTCCLKOUTSEL) 00496 00497 /*! @brief Set the RTCCLKOUTSEL field to a new value. */ 00498 #define BW_SIM_SOPT2_RTCCLKOUTSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RTCCLKOUTSEL), v)) 00499 /*@}*/ 00500 00501 /*! 00502 * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW) 00503 * 00504 * Selects the clock to output on the CLKOUT pin. 00505 * 00506 * Values: 00507 * - 000 - FlexBus CLKOUT 00508 * - 001 - Reserved 00509 * - 010 - Flash clock 00510 * - 011 - LPO clock (1 kHz) 00511 * - 100 - MCGIRCLK 00512 * - 101 - RTC 32.768kHz clock 00513 * - 110 - OSCERCLK0 00514 * - 111 - IRC 48 MHz clock 00515 */ 00516 /*@{*/ 00517 #define BP_SIM_SOPT2_CLKOUTSEL (5U) /*!< Bit position for SIM_SOPT2_CLKOUTSEL. */ 00518 #define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) /*!< Bit mask for SIM_SOPT2_CLKOUTSEL. */ 00519 #define BS_SIM_SOPT2_CLKOUTSEL (3U) /*!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL. */ 00520 00521 /*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */ 00522 #define BR_SIM_SOPT2_CLKOUTSEL(x) (UNION_READ(hw_sim_sopt2_t, HW_SIM_SOPT2_ADDR(x), U, B.CLKOUTSEL)) 00523 00524 /*! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL. */ 00525 #define BF_SIM_SOPT2_CLKOUTSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_CLKOUTSEL) & BM_SIM_SOPT2_CLKOUTSEL) 00526 00527 /*! @brief Set the CLKOUTSEL field to a new value. */ 00528 #define BW_SIM_SOPT2_CLKOUTSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v))) 00529 /*@}*/ 00530 00531 /*! 00532 * @name Register SIM_SOPT2, field FBSL[9:8] (RW) 00533 * 00534 * If flash security is enabled, then this field affects what CPU operations can 00535 * access off-chip via the FlexBus interface. This field has no effect if flash 00536 * security is not enabled. 00537 * 00538 * Values: 00539 * - 00 - All off-chip accesses (instruction and data) via the FlexBus are 00540 * disallowed. 00541 * - 01 - All off-chip accesses (instruction and data) via the FlexBus are 00542 * disallowed. 00543 * - 10 - Off-chip instruction accesses are disallowed. Data accesses are 00544 * allowed. 00545 * - 11 - Off-chip instruction accesses and data accesses are allowed. 00546 */ 00547 /*@{*/ 00548 #define BP_SIM_SOPT2_FBSL (8U) /*!< Bit position for SIM_SOPT2_FBSL. */ 00549 #define BM_SIM_SOPT2_FBSL (0x00000300U) /*!< Bit mask for SIM_SOPT2_FBSL. */ 00550 #define BS_SIM_SOPT2_FBSL (2U) /*!< Bit field size in bits for SIM_SOPT2_FBSL. */ 00551 00552 /*! @brief Read current value of the SIM_SOPT2_FBSL field. */ 00553 #define BR_SIM_SOPT2_FBSL(x) (UNION_READ(hw_sim_sopt2_t, HW_SIM_SOPT2_ADDR(x), U, B.FBSL)) 00554 00555 /*! @brief Format value for bitfield SIM_SOPT2_FBSL. */ 00556 #define BF_SIM_SOPT2_FBSL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_FBSL) & BM_SIM_SOPT2_FBSL) 00557 00558 /*! @brief Set the FBSL field to a new value. */ 00559 #define BW_SIM_SOPT2_FBSL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v))) 00560 /*@}*/ 00561 00562 /*! 00563 * @name Register SIM_SOPT2, field PTD7PAD[11] (RW) 00564 * 00565 * Controls the output drive strength of the PTD7 pin by selecting either one or 00566 * two pads to drive it. 00567 * 00568 * Values: 00569 * - 0 - Single-pad drive strength for PTD7. 00570 * - 1 - Double pad drive strength for PTD7. 00571 */ 00572 /*@{*/ 00573 #define BP_SIM_SOPT2_PTD7PAD (11U) /*!< Bit position for SIM_SOPT2_PTD7PAD. */ 00574 #define BM_SIM_SOPT2_PTD7PAD (0x00000800U) /*!< Bit mask for SIM_SOPT2_PTD7PAD. */ 00575 #define BS_SIM_SOPT2_PTD7PAD (1U) /*!< Bit field size in bits for SIM_SOPT2_PTD7PAD. */ 00576 00577 /*! @brief Read current value of the SIM_SOPT2_PTD7PAD field. */ 00578 #define BR_SIM_SOPT2_PTD7PAD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD))) 00579 00580 /*! @brief Format value for bitfield SIM_SOPT2_PTD7PAD. */ 00581 #define BF_SIM_SOPT2_PTD7PAD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PTD7PAD) & BM_SIM_SOPT2_PTD7PAD) 00582 00583 /*! @brief Set the PTD7PAD field to a new value. */ 00584 #define BW_SIM_SOPT2_PTD7PAD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_PTD7PAD), v)) 00585 /*@}*/ 00586 00587 /*! 00588 * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW) 00589 * 00590 * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace 00591 * clock source. 00592 * 00593 * Values: 00594 * - 0 - MCGOUTCLK 00595 * - 1 - Core/system clock 00596 */ 00597 /*@{*/ 00598 #define BP_SIM_SOPT2_TRACECLKSEL (12U) /*!< Bit position for SIM_SOPT2_TRACECLKSEL. */ 00599 #define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) /*!< Bit mask for SIM_SOPT2_TRACECLKSEL. */ 00600 #define BS_SIM_SOPT2_TRACECLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL. */ 00601 00602 /*! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field. */ 00603 #define BR_SIM_SOPT2_TRACECLKSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL))) 00604 00605 /*! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL. */ 00606 #define BF_SIM_SOPT2_TRACECLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TRACECLKSEL) & BM_SIM_SOPT2_TRACECLKSEL) 00607 00608 /*! @brief Set the TRACECLKSEL field to a new value. */ 00609 #define BW_SIM_SOPT2_TRACECLKSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_TRACECLKSEL), v)) 00610 /*@}*/ 00611 00612 /*! 00613 * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW) 00614 * 00615 * Selects the high frequency clock for various peripheral clocking options. 00616 * 00617 * Values: 00618 * - 00 - MCGFLLCLK clock 00619 * - 01 - MCGPLLCLK clock 00620 * - 10 - Reserved 00621 * - 11 - IRC48 MHz clock 00622 */ 00623 /*@{*/ 00624 #define BP_SIM_SOPT2_PLLFLLSEL (16U) /*!< Bit position for SIM_SOPT2_PLLFLLSEL. */ 00625 #define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) /*!< Bit mask for SIM_SOPT2_PLLFLLSEL. */ 00626 #define BS_SIM_SOPT2_PLLFLLSEL (2U) /*!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL. */ 00627 00628 /*! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field. */ 00629 #define BR_SIM_SOPT2_PLLFLLSEL(x) (UNION_READ(hw_sim_sopt2_t, HW_SIM_SOPT2_ADDR(x), U, B.PLLFLLSEL)) 00630 00631 /*! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL. */ 00632 #define BF_SIM_SOPT2_PLLFLLSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_PLLFLLSEL) & BM_SIM_SOPT2_PLLFLLSEL) 00633 00634 /*! @brief Set the PLLFLLSEL field to a new value. */ 00635 #define BW_SIM_SOPT2_PLLFLLSEL(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v))) 00636 /*@}*/ 00637 00638 /*! 00639 * @name Register SIM_SOPT2, field USBSRC[18] (RW) 00640 * 00641 * Selects the clock source for the USB 48 MHz clock. 00642 * 00643 * Values: 00644 * - 0 - External bypass clock (USB_CLKIN). 00645 * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by 00646 * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by 00647 * SIM_CLKDIV2[USBFRAC, USBDIV]. 00648 */ 00649 /*@{*/ 00650 #define BP_SIM_SOPT2_USBSRC (18U) /*!< Bit position for SIM_SOPT2_USBSRC. */ 00651 #define BM_SIM_SOPT2_USBSRC (0x00040000U) /*!< Bit mask for SIM_SOPT2_USBSRC. */ 00652 #define BS_SIM_SOPT2_USBSRC (1U) /*!< Bit field size in bits for SIM_SOPT2_USBSRC. */ 00653 00654 /*! @brief Read current value of the SIM_SOPT2_USBSRC field. */ 00655 #define BR_SIM_SOPT2_USBSRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC))) 00656 00657 /*! @brief Format value for bitfield SIM_SOPT2_USBSRC. */ 00658 #define BF_SIM_SOPT2_USBSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_USBSRC) & BM_SIM_SOPT2_USBSRC) 00659 00660 /*! @brief Set the USBSRC field to a new value. */ 00661 #define BW_SIM_SOPT2_USBSRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_USBSRC), v)) 00662 /*@}*/ 00663 00664 /*! 00665 * @name Register SIM_SOPT2, field RMIISRC[19] (RW) 00666 * 00667 * Selects the clock source for the Ethernet RMII interface 00668 * 00669 * Values: 00670 * - 0 - EXTAL clock 00671 * - 1 - External bypass clock (ENET_1588_CLKIN). 00672 */ 00673 /*@{*/ 00674 #define BP_SIM_SOPT2_RMIISRC (19U) /*!< Bit position for SIM_SOPT2_RMIISRC. */ 00675 #define BM_SIM_SOPT2_RMIISRC (0x00080000U) /*!< Bit mask for SIM_SOPT2_RMIISRC. */ 00676 #define BS_SIM_SOPT2_RMIISRC (1U) /*!< Bit field size in bits for SIM_SOPT2_RMIISRC. */ 00677 00678 /*! @brief Read current value of the SIM_SOPT2_RMIISRC field. */ 00679 #define BR_SIM_SOPT2_RMIISRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC))) 00680 00681 /*! @brief Format value for bitfield SIM_SOPT2_RMIISRC. */ 00682 #define BF_SIM_SOPT2_RMIISRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_RMIISRC) & BM_SIM_SOPT2_RMIISRC) 00683 00684 /*! @brief Set the RMIISRC field to a new value. */ 00685 #define BW_SIM_SOPT2_RMIISRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT2_ADDR(x), BP_SIM_SOPT2_RMIISRC), v)) 00686 /*@}*/ 00687 00688 /*! 00689 * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW) 00690 * 00691 * Selects the clock source for the Ethernet timestamp clock. 00692 * 00693 * Values: 00694 * - 00 - Core/system clock. 00695 * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by 00696 * SOPT2[PLLFLLSEL]. 00697 * - 10 - OSCERCLK clock 00698 * - 11 - External bypass clock (ENET_1588_CLKIN). 00699 */ 00700 /*@{*/ 00701 #define BP_SIM_SOPT2_TIMESRC (20U) /*!< Bit position for SIM_SOPT2_TIMESRC. */ 00702 #define BM_SIM_SOPT2_TIMESRC (0x00300000U) /*!< Bit mask for SIM_SOPT2_TIMESRC. */ 00703 #define BS_SIM_SOPT2_TIMESRC (2U) /*!< Bit field size in bits for SIM_SOPT2_TIMESRC. */ 00704 00705 /*! @brief Read current value of the SIM_SOPT2_TIMESRC field. */ 00706 #define BR_SIM_SOPT2_TIMESRC(x) (UNION_READ(hw_sim_sopt2_t, HW_SIM_SOPT2_ADDR(x), U, B.TIMESRC)) 00707 00708 /*! @brief Format value for bitfield SIM_SOPT2_TIMESRC. */ 00709 #define BF_SIM_SOPT2_TIMESRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_TIMESRC) & BM_SIM_SOPT2_TIMESRC) 00710 00711 /*! @brief Set the TIMESRC field to a new value. */ 00712 #define BW_SIM_SOPT2_TIMESRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v))) 00713 /*@}*/ 00714 00715 /*! 00716 * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW) 00717 * 00718 * Selects the clock source for the SDHC clock . 00719 * 00720 * Values: 00721 * - 00 - Core/system clock. 00722 * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by 00723 * SOPT2[PLLFLLSEL]. 00724 * - 10 - OSCERCLK clock 00725 * - 11 - External bypass clock (SDHC0_CLKIN) 00726 */ 00727 /*@{*/ 00728 #define BP_SIM_SOPT2_SDHCSRC (28U) /*!< Bit position for SIM_SOPT2_SDHCSRC. */ 00729 #define BM_SIM_SOPT2_SDHCSRC (0x30000000U) /*!< Bit mask for SIM_SOPT2_SDHCSRC. */ 00730 #define BS_SIM_SOPT2_SDHCSRC (2U) /*!< Bit field size in bits for SIM_SOPT2_SDHCSRC. */ 00731 00732 /*! @brief Read current value of the SIM_SOPT2_SDHCSRC field. */ 00733 #define BR_SIM_SOPT2_SDHCSRC(x) (UNION_READ(hw_sim_sopt2_t, HW_SIM_SOPT2_ADDR(x), U, B.SDHCSRC)) 00734 00735 /*! @brief Format value for bitfield SIM_SOPT2_SDHCSRC. */ 00736 #define BF_SIM_SOPT2_SDHCSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT2_SDHCSRC) & BM_SIM_SOPT2_SDHCSRC) 00737 00738 /*! @brief Set the SDHCSRC field to a new value. */ 00739 #define BW_SIM_SOPT2_SDHCSRC(x, v) (HW_SIM_SOPT2_WR(x, (HW_SIM_SOPT2_RD(x) & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v))) 00740 /*@}*/ 00741 00742 /******************************************************************************* 00743 * HW_SIM_SOPT4 - System Options Register 4 00744 ******************************************************************************/ 00745 00746 /*! 00747 * @brief HW_SIM_SOPT4 - System Options Register 4 (RW) 00748 * 00749 * Reset value: 0x00000000U 00750 */ 00751 typedef union _hw_sim_sopt4 00752 { 00753 uint32_t U; 00754 struct _hw_sim_sopt4_bitfields 00755 { 00756 uint32_t FTM0FLT0 : 1; /*!< [0] FTM0 Fault 0 Select */ 00757 uint32_t FTM0FLT1 : 1; /*!< [1] FTM0 Fault 1 Select */ 00758 uint32_t FTM0FLT2 : 1; /*!< [2] FTM0 Fault 2 Select */ 00759 uint32_t RESERVED0 : 1; /*!< [3] */ 00760 uint32_t FTM1FLT0 : 1; /*!< [4] FTM1 Fault 0 Select */ 00761 uint32_t RESERVED1 : 3; /*!< [7:5] */ 00762 uint32_t FTM2FLT0 : 1; /*!< [8] FTM2 Fault 0 Select */ 00763 uint32_t RESERVED2 : 3; /*!< [11:9] */ 00764 uint32_t FTM3FLT0 : 1; /*!< [12] FTM3 Fault 0 Select */ 00765 uint32_t RESERVED3 : 5; /*!< [17:13] */ 00766 uint32_t FTM1CH0SRC : 2; /*!< [19:18] FTM1 channel 0 input capture 00767 * source select */ 00768 uint32_t FTM2CH0SRC : 2; /*!< [21:20] FTM2 channel 0 input capture 00769 * source select */ 00770 uint32_t RESERVED4 : 2; /*!< [23:22] */ 00771 uint32_t FTM0CLKSEL : 1; /*!< [24] FlexTimer 0 External Clock Pin 00772 * Select */ 00773 uint32_t FTM1CLKSEL : 1; /*!< [25] FTM1 External Clock Pin Select */ 00774 uint32_t FTM2CLKSEL : 1; /*!< [26] FlexTimer 2 External Clock Pin 00775 * Select */ 00776 uint32_t FTM3CLKSEL : 1; /*!< [27] FlexTimer 3 External Clock Pin 00777 * Select */ 00778 uint32_t FTM0TRG0SRC : 1; /*!< [28] FlexTimer 0 Hardware Trigger 0 00779 * Source Select */ 00780 uint32_t FTM0TRG1SRC : 1; /*!< [29] FlexTimer 0 Hardware Trigger 1 00781 * Source Select */ 00782 uint32_t FTM3TRG0SRC : 1; /*!< [30] FlexTimer 3 Hardware Trigger 0 00783 * Source Select */ 00784 uint32_t FTM3TRG1SRC : 1; /*!< [31] FlexTimer 3 Hardware Trigger 1 00785 * Source Select */ 00786 } B; 00787 } hw_sim_sopt4_t; 00788 00789 /*! 00790 * @name Constants and macros for entire SIM_SOPT4 register 00791 */ 00792 /*@{*/ 00793 #define HW_SIM_SOPT4_ADDR(x) ((x) + 0x100CU) 00794 00795 #define HW_SIM_SOPT4(x) (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR(x)) 00796 #define HW_SIM_SOPT4_RD(x) (ADDRESS_READ(hw_sim_sopt4_t, HW_SIM_SOPT4_ADDR(x))) 00797 #define HW_SIM_SOPT4_WR(x, v) (ADDRESS_WRITE(hw_sim_sopt4_t, HW_SIM_SOPT4_ADDR(x), v)) 00798 #define HW_SIM_SOPT4_SET(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) | (v))) 00799 #define HW_SIM_SOPT4_CLR(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) & ~(v))) 00800 #define HW_SIM_SOPT4_TOG(x, v) (HW_SIM_SOPT4_WR(x, HW_SIM_SOPT4_RD(x) ^ (v))) 00801 /*@}*/ 00802 00803 /* 00804 * Constants & macros for individual SIM_SOPT4 bitfields 00805 */ 00806 00807 /*! 00808 * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW) 00809 * 00810 * Selects the source of FTM0 fault 0. The pin source for fault 0 must be 00811 * configured for the FTM module fault function through the appropriate pin control 00812 * register in the port control module. 00813 * 00814 * Values: 00815 * - 0 - FTM0_FLT0 pin 00816 * - 1 - CMP0 out 00817 */ 00818 /*@{*/ 00819 #define BP_SIM_SOPT4_FTM0FLT0 (0U) /*!< Bit position for SIM_SOPT4_FTM0FLT0. */ 00820 #define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) /*!< Bit mask for SIM_SOPT4_FTM0FLT0. */ 00821 #define BS_SIM_SOPT4_FTM0FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT0. */ 00822 00823 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field. */ 00824 #define BR_SIM_SOPT4_FTM0FLT0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0))) 00825 00826 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0. */ 00827 #define BF_SIM_SOPT4_FTM0FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT0) & BM_SIM_SOPT4_FTM0FLT0) 00828 00829 /*! @brief Set the FTM0FLT0 field to a new value. */ 00830 #define BW_SIM_SOPT4_FTM0FLT0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT0), v)) 00831 /*@}*/ 00832 00833 /*! 00834 * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW) 00835 * 00836 * Selects the source of FTM0 fault 1. The pin source for fault 1 must be 00837 * configured for the FTM module fault function through the appropriate pin control 00838 * register in the port control module. 00839 * 00840 * Values: 00841 * - 0 - FTM0_FLT1 pin 00842 * - 1 - CMP1 out 00843 */ 00844 /*@{*/ 00845 #define BP_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit position for SIM_SOPT4_FTM0FLT1. */ 00846 #define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) /*!< Bit mask for SIM_SOPT4_FTM0FLT1. */ 00847 #define BS_SIM_SOPT4_FTM0FLT1 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT1. */ 00848 00849 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field. */ 00850 #define BR_SIM_SOPT4_FTM0FLT1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1))) 00851 00852 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1. */ 00853 #define BF_SIM_SOPT4_FTM0FLT1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT1) & BM_SIM_SOPT4_FTM0FLT1) 00854 00855 /*! @brief Set the FTM0FLT1 field to a new value. */ 00856 #define BW_SIM_SOPT4_FTM0FLT1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT1), v)) 00857 /*@}*/ 00858 00859 /*! 00860 * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW) 00861 * 00862 * Selects the source of FTM0 fault 2. The pin source for fault 2 must be 00863 * configured for the FTM module fault function through the appropriate pin control 00864 * register in the port control module. 00865 * 00866 * Values: 00867 * - 0 - FTM0_FLT2 pin 00868 * - 1 - CMP2 out 00869 */ 00870 /*@{*/ 00871 #define BP_SIM_SOPT4_FTM0FLT2 (2U) /*!< Bit position for SIM_SOPT4_FTM0FLT2. */ 00872 #define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) /*!< Bit mask for SIM_SOPT4_FTM0FLT2. */ 00873 #define BS_SIM_SOPT4_FTM0FLT2 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0FLT2. */ 00874 00875 /*! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field. */ 00876 #define BR_SIM_SOPT4_FTM0FLT2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2))) 00877 00878 /*! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2. */ 00879 #define BF_SIM_SOPT4_FTM0FLT2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0FLT2) & BM_SIM_SOPT4_FTM0FLT2) 00880 00881 /*! @brief Set the FTM0FLT2 field to a new value. */ 00882 #define BW_SIM_SOPT4_FTM0FLT2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0FLT2), v)) 00883 /*@}*/ 00884 00885 /*! 00886 * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW) 00887 * 00888 * Selects the source of FTM1 fault 0. The pin source for fault 0 must be 00889 * configured for the FTM module fault function through the appropriate pin control 00890 * register in the port control module. 00891 * 00892 * Values: 00893 * - 0 - FTM1_FLT0 pin 00894 * - 1 - CMP0 out 00895 */ 00896 /*@{*/ 00897 #define BP_SIM_SOPT4_FTM1FLT0 (4U) /*!< Bit position for SIM_SOPT4_FTM1FLT0. */ 00898 #define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) /*!< Bit mask for SIM_SOPT4_FTM1FLT0. */ 00899 #define BS_SIM_SOPT4_FTM1FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1FLT0. */ 00900 00901 /*! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field. */ 00902 #define BR_SIM_SOPT4_FTM1FLT0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0))) 00903 00904 /*! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0. */ 00905 #define BF_SIM_SOPT4_FTM1FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1FLT0) & BM_SIM_SOPT4_FTM1FLT0) 00906 00907 /*! @brief Set the FTM1FLT0 field to a new value. */ 00908 #define BW_SIM_SOPT4_FTM1FLT0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1FLT0), v)) 00909 /*@}*/ 00910 00911 /*! 00912 * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW) 00913 * 00914 * Selects the source of FTM2 fault 0. The pin source for fault 0 must be 00915 * configured for the FTM module fault function through the appropriate PORTx pin 00916 * control register. 00917 * 00918 * Values: 00919 * - 0 - FTM2_FLT0 pin 00920 * - 1 - CMP0 out 00921 */ 00922 /*@{*/ 00923 #define BP_SIM_SOPT4_FTM2FLT0 (8U) /*!< Bit position for SIM_SOPT4_FTM2FLT0. */ 00924 #define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) /*!< Bit mask for SIM_SOPT4_FTM2FLT0. */ 00925 #define BS_SIM_SOPT4_FTM2FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2FLT0. */ 00926 00927 /*! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field. */ 00928 #define BR_SIM_SOPT4_FTM2FLT0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0))) 00929 00930 /*! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0. */ 00931 #define BF_SIM_SOPT4_FTM2FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2FLT0) & BM_SIM_SOPT4_FTM2FLT0) 00932 00933 /*! @brief Set the FTM2FLT0 field to a new value. */ 00934 #define BW_SIM_SOPT4_FTM2FLT0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2FLT0), v)) 00935 /*@}*/ 00936 00937 /*! 00938 * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW) 00939 * 00940 * Selects the source of FTM3 fault 0. The pin source for fault 0 must be 00941 * configured for the FTM module fault function through the appropriate PORTx pin 00942 * control register. 00943 * 00944 * Values: 00945 * - 0 - FTM3_FLT0 pin 00946 * - 1 - CMP0 out 00947 */ 00948 /*@{*/ 00949 #define BP_SIM_SOPT4_FTM3FLT0 (12U) /*!< Bit position for SIM_SOPT4_FTM3FLT0. */ 00950 #define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) /*!< Bit mask for SIM_SOPT4_FTM3FLT0. */ 00951 #define BS_SIM_SOPT4_FTM3FLT0 (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3FLT0. */ 00952 00953 /*! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field. */ 00954 #define BR_SIM_SOPT4_FTM3FLT0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0))) 00955 00956 /*! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0. */ 00957 #define BF_SIM_SOPT4_FTM3FLT0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3FLT0) & BM_SIM_SOPT4_FTM3FLT0) 00958 00959 /*! @brief Set the FTM3FLT0 field to a new value. */ 00960 #define BW_SIM_SOPT4_FTM3FLT0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3FLT0), v)) 00961 /*@}*/ 00962 00963 /*! 00964 * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW) 00965 * 00966 * Selects the source for FTM1 channel 0 input capture. When the FTM is not in 00967 * input capture mode, clear this field. 00968 * 00969 * Values: 00970 * - 00 - FTM1_CH0 signal 00971 * - 01 - CMP0 output 00972 * - 10 - CMP1 output 00973 * - 11 - USB start of frame pulse 00974 */ 00975 /*@{*/ 00976 #define BP_SIM_SOPT4_FTM1CH0SRC (18U) /*!< Bit position for SIM_SOPT4_FTM1CH0SRC. */ 00977 #define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) /*!< Bit mask for SIM_SOPT4_FTM1CH0SRC. */ 00978 #define BS_SIM_SOPT4_FTM1CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC. */ 00979 00980 /*! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field. */ 00981 #define BR_SIM_SOPT4_FTM1CH0SRC(x) (UNION_READ(hw_sim_sopt4_t, HW_SIM_SOPT4_ADDR(x), U, B.FTM1CH0SRC)) 00982 00983 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC. */ 00984 #define BF_SIM_SOPT4_FTM1CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CH0SRC) & BM_SIM_SOPT4_FTM1CH0SRC) 00985 00986 /*! @brief Set the FTM1CH0SRC field to a new value. */ 00987 #define BW_SIM_SOPT4_FTM1CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v))) 00988 /*@}*/ 00989 00990 /*! 00991 * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW) 00992 * 00993 * Selects the source for FTM2 channel 0 input capture. When the FTM is not in 00994 * input capture mode, clear this field. 00995 * 00996 * Values: 00997 * - 00 - FTM2_CH0 signal 00998 * - 01 - CMP0 output 00999 * - 10 - CMP1 output 01000 * - 11 - Reserved 01001 */ 01002 /*@{*/ 01003 #define BP_SIM_SOPT4_FTM2CH0SRC (20U) /*!< Bit position for SIM_SOPT4_FTM2CH0SRC. */ 01004 #define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) /*!< Bit mask for SIM_SOPT4_FTM2CH0SRC. */ 01005 #define BS_SIM_SOPT4_FTM2CH0SRC (2U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC. */ 01006 01007 /*! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field. */ 01008 #define BR_SIM_SOPT4_FTM2CH0SRC(x) (UNION_READ(hw_sim_sopt4_t, HW_SIM_SOPT4_ADDR(x), U, B.FTM2CH0SRC)) 01009 01010 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC. */ 01011 #define BF_SIM_SOPT4_FTM2CH0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CH0SRC) & BM_SIM_SOPT4_FTM2CH0SRC) 01012 01013 /*! @brief Set the FTM2CH0SRC field to a new value. */ 01014 #define BW_SIM_SOPT4_FTM2CH0SRC(x, v) (HW_SIM_SOPT4_WR(x, (HW_SIM_SOPT4_RD(x) & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v))) 01015 /*@}*/ 01016 01017 /*! 01018 * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW) 01019 * 01020 * Selects the external pin used to drive the clock to the FTM0 module. The 01021 * selected pin must also be configured for the FTM external clock function through 01022 * the appropriate pin control register in the port control module. 01023 * 01024 * Values: 01025 * - 0 - FTM_CLK0 pin 01026 * - 1 - FTM_CLK1 pin 01027 */ 01028 /*@{*/ 01029 #define BP_SIM_SOPT4_FTM0CLKSEL (24U) /*!< Bit position for SIM_SOPT4_FTM0CLKSEL. */ 01030 #define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) /*!< Bit mask for SIM_SOPT4_FTM0CLKSEL. */ 01031 #define BS_SIM_SOPT4_FTM0CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL. */ 01032 01033 /*! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field. */ 01034 #define BR_SIM_SOPT4_FTM0CLKSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL))) 01035 01036 /*! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL. */ 01037 #define BF_SIM_SOPT4_FTM0CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0CLKSEL) & BM_SIM_SOPT4_FTM0CLKSEL) 01038 01039 /*! @brief Set the FTM0CLKSEL field to a new value. */ 01040 #define BW_SIM_SOPT4_FTM0CLKSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0CLKSEL), v)) 01041 /*@}*/ 01042 01043 /*! 01044 * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW) 01045 * 01046 * Selects the external pin used to drive the clock to the FTM1 module. The 01047 * selected pin must also be configured for the FTM external clock function through 01048 * the appropriate pin control register in the port control module. 01049 * 01050 * Values: 01051 * - 0 - FTM_CLK0 pin 01052 * - 1 - FTM_CLK1 pin 01053 */ 01054 /*@{*/ 01055 #define BP_SIM_SOPT4_FTM1CLKSEL (25U) /*!< Bit position for SIM_SOPT4_FTM1CLKSEL. */ 01056 #define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) /*!< Bit mask for SIM_SOPT4_FTM1CLKSEL. */ 01057 #define BS_SIM_SOPT4_FTM1CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL. */ 01058 01059 /*! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field. */ 01060 #define BR_SIM_SOPT4_FTM1CLKSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL))) 01061 01062 /*! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL. */ 01063 #define BF_SIM_SOPT4_FTM1CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM1CLKSEL) & BM_SIM_SOPT4_FTM1CLKSEL) 01064 01065 /*! @brief Set the FTM1CLKSEL field to a new value. */ 01066 #define BW_SIM_SOPT4_FTM1CLKSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM1CLKSEL), v)) 01067 /*@}*/ 01068 01069 /*! 01070 * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW) 01071 * 01072 * Selects the external pin used to drive the clock to the FTM2 module. The 01073 * selected pin must also be configured for the FTM2 module external clock function 01074 * through the appropriate pin control register in the port control module. 01075 * 01076 * Values: 01077 * - 0 - FTM2 external clock driven by FTM_CLK0 pin. 01078 * - 1 - FTM2 external clock driven by FTM_CLK1 pin. 01079 */ 01080 /*@{*/ 01081 #define BP_SIM_SOPT4_FTM2CLKSEL (26U) /*!< Bit position for SIM_SOPT4_FTM2CLKSEL. */ 01082 #define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) /*!< Bit mask for SIM_SOPT4_FTM2CLKSEL. */ 01083 #define BS_SIM_SOPT4_FTM2CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL. */ 01084 01085 /*! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field. */ 01086 #define BR_SIM_SOPT4_FTM2CLKSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL))) 01087 01088 /*! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL. */ 01089 #define BF_SIM_SOPT4_FTM2CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM2CLKSEL) & BM_SIM_SOPT4_FTM2CLKSEL) 01090 01091 /*! @brief Set the FTM2CLKSEL field to a new value. */ 01092 #define BW_SIM_SOPT4_FTM2CLKSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM2CLKSEL), v)) 01093 /*@}*/ 01094 01095 /*! 01096 * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW) 01097 * 01098 * Selects the external pin used to drive the clock to the FTM3 module. The 01099 * selected pin must also be configured for the FTM3 module external clock function 01100 * through the appropriate pin control register in the port control module. 01101 * 01102 * Values: 01103 * - 0 - FTM3 external clock driven by FTM_CLK0 pin. 01104 * - 1 - FTM3 external clock driven by FTM_CLK1 pin. 01105 */ 01106 /*@{*/ 01107 #define BP_SIM_SOPT4_FTM3CLKSEL (27U) /*!< Bit position for SIM_SOPT4_FTM3CLKSEL. */ 01108 #define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) /*!< Bit mask for SIM_SOPT4_FTM3CLKSEL. */ 01109 #define BS_SIM_SOPT4_FTM3CLKSEL (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL. */ 01110 01111 /*! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field. */ 01112 #define BR_SIM_SOPT4_FTM3CLKSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL))) 01113 01114 /*! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL. */ 01115 #define BF_SIM_SOPT4_FTM3CLKSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3CLKSEL) & BM_SIM_SOPT4_FTM3CLKSEL) 01116 01117 /*! @brief Set the FTM3CLKSEL field to a new value. */ 01118 #define BW_SIM_SOPT4_FTM3CLKSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3CLKSEL), v)) 01119 /*@}*/ 01120 01121 /*! 01122 * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW) 01123 * 01124 * Selects the source of FTM0 hardware trigger 0. 01125 * 01126 * Values: 01127 * - 0 - HSCMP0 output drives FTM0 hardware trigger 0 01128 * - 1 - FTM1 channel match drives FTM0 hardware trigger 0 01129 */ 01130 /*@{*/ 01131 #define BP_SIM_SOPT4_FTM0TRG0SRC (28U) /*!< Bit position for SIM_SOPT4_FTM0TRG0SRC. */ 01132 #define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG0SRC. */ 01133 #define BS_SIM_SOPT4_FTM0TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC. */ 01134 01135 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field. */ 01136 #define BR_SIM_SOPT4_FTM0TRG0SRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC))) 01137 01138 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC. */ 01139 #define BF_SIM_SOPT4_FTM0TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG0SRC) & BM_SIM_SOPT4_FTM0TRG0SRC) 01140 01141 /*! @brief Set the FTM0TRG0SRC field to a new value. */ 01142 #define BW_SIM_SOPT4_FTM0TRG0SRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG0SRC), v)) 01143 /*@}*/ 01144 01145 /*! 01146 * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW) 01147 * 01148 * Selects the source of FTM0 hardware trigger 1. 01149 * 01150 * Values: 01151 * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1 01152 * - 1 - FTM2 channel match drives FTM0 hardware trigger 1 01153 */ 01154 /*@{*/ 01155 #define BP_SIM_SOPT4_FTM0TRG1SRC (29U) /*!< Bit position for SIM_SOPT4_FTM0TRG1SRC. */ 01156 #define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) /*!< Bit mask for SIM_SOPT4_FTM0TRG1SRC. */ 01157 #define BS_SIM_SOPT4_FTM0TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC. */ 01158 01159 /*! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field. */ 01160 #define BR_SIM_SOPT4_FTM0TRG1SRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC))) 01161 01162 /*! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC. */ 01163 #define BF_SIM_SOPT4_FTM0TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM0TRG1SRC) & BM_SIM_SOPT4_FTM0TRG1SRC) 01164 01165 /*! @brief Set the FTM0TRG1SRC field to a new value. */ 01166 #define BW_SIM_SOPT4_FTM0TRG1SRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM0TRG1SRC), v)) 01167 /*@}*/ 01168 01169 /*! 01170 * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW) 01171 * 01172 * Selects the source of FTM3 hardware trigger 0. 01173 * 01174 * Values: 01175 * - 0 - Reserved 01176 * - 1 - FTM1 channel match drives FTM3 hardware trigger 0 01177 */ 01178 /*@{*/ 01179 #define BP_SIM_SOPT4_FTM3TRG0SRC (30U) /*!< Bit position for SIM_SOPT4_FTM3TRG0SRC. */ 01180 #define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG0SRC. */ 01181 #define BS_SIM_SOPT4_FTM3TRG0SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC. */ 01182 01183 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field. */ 01184 #define BR_SIM_SOPT4_FTM3TRG0SRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC))) 01185 01186 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC. */ 01187 #define BF_SIM_SOPT4_FTM3TRG0SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG0SRC) & BM_SIM_SOPT4_FTM3TRG0SRC) 01188 01189 /*! @brief Set the FTM3TRG0SRC field to a new value. */ 01190 #define BW_SIM_SOPT4_FTM3TRG0SRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG0SRC), v)) 01191 /*@}*/ 01192 01193 /*! 01194 * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW) 01195 * 01196 * Selects the source of FTM3 hardware trigger 1. 01197 * 01198 * Values: 01199 * - 0 - Reserved 01200 * - 1 - FTM2 channel match drives FTM3 hardware trigger 1 01201 */ 01202 /*@{*/ 01203 #define BP_SIM_SOPT4_FTM3TRG1SRC (31U) /*!< Bit position for SIM_SOPT4_FTM3TRG1SRC. */ 01204 #define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) /*!< Bit mask for SIM_SOPT4_FTM3TRG1SRC. */ 01205 #define BS_SIM_SOPT4_FTM3TRG1SRC (1U) /*!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC. */ 01206 01207 /*! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field. */ 01208 #define BR_SIM_SOPT4_FTM3TRG1SRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC))) 01209 01210 /*! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC. */ 01211 #define BF_SIM_SOPT4_FTM3TRG1SRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT4_FTM3TRG1SRC) & BM_SIM_SOPT4_FTM3TRG1SRC) 01212 01213 /*! @brief Set the FTM3TRG1SRC field to a new value. */ 01214 #define BW_SIM_SOPT4_FTM3TRG1SRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT4_ADDR(x), BP_SIM_SOPT4_FTM3TRG1SRC), v)) 01215 /*@}*/ 01216 01217 /******************************************************************************* 01218 * HW_SIM_SOPT5 - System Options Register 5 01219 ******************************************************************************/ 01220 01221 /*! 01222 * @brief HW_SIM_SOPT5 - System Options Register 5 (RW) 01223 * 01224 * Reset value: 0x00000000U 01225 */ 01226 typedef union _hw_sim_sopt5 01227 { 01228 uint32_t U; 01229 struct _hw_sim_sopt5_bitfields 01230 { 01231 uint32_t UART0TXSRC : 2; /*!< [1:0] UART 0 transmit data source 01232 * select */ 01233 uint32_t UART0RXSRC : 2; /*!< [3:2] UART 0 receive data source select 01234 * */ 01235 uint32_t UART1TXSRC : 2; /*!< [5:4] UART 1 transmit data source 01236 * select */ 01237 uint32_t UART1RXSRC : 2; /*!< [7:6] UART 1 receive data source select 01238 * */ 01239 uint32_t RESERVED0 : 24; /*!< [31:8] */ 01240 } B; 01241 } hw_sim_sopt5_t; 01242 01243 /*! 01244 * @name Constants and macros for entire SIM_SOPT5 register 01245 */ 01246 /*@{*/ 01247 #define HW_SIM_SOPT5_ADDR(x) ((x) + 0x1010U) 01248 01249 #define HW_SIM_SOPT5(x) (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR(x)) 01250 #define HW_SIM_SOPT5_RD(x) (ADDRESS_READ(hw_sim_sopt5_t, HW_SIM_SOPT5_ADDR(x))) 01251 #define HW_SIM_SOPT5_WR(x, v) (ADDRESS_WRITE(hw_sim_sopt5_t, HW_SIM_SOPT5_ADDR(x), v)) 01252 #define HW_SIM_SOPT5_SET(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) | (v))) 01253 #define HW_SIM_SOPT5_CLR(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) & ~(v))) 01254 #define HW_SIM_SOPT5_TOG(x, v) (HW_SIM_SOPT5_WR(x, HW_SIM_SOPT5_RD(x) ^ (v))) 01255 /*@}*/ 01256 01257 /* 01258 * Constants & macros for individual SIM_SOPT5 bitfields 01259 */ 01260 01261 /*! 01262 * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW) 01263 * 01264 * Selects the source for the UART 0 transmit data. 01265 * 01266 * Values: 01267 * - 00 - UART0_TX pin 01268 * - 01 - UART0_TX pin modulated with FTM1 channel 0 output 01269 * - 10 - UART0_TX pin modulated with FTM2 channel 0 output 01270 * - 11 - Reserved 01271 */ 01272 /*@{*/ 01273 #define BP_SIM_SOPT5_UART0TXSRC (0U) /*!< Bit position for SIM_SOPT5_UART0TXSRC. */ 01274 #define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) /*!< Bit mask for SIM_SOPT5_UART0TXSRC. */ 01275 #define BS_SIM_SOPT5_UART0TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0TXSRC. */ 01276 01277 /*! @brief Read current value of the SIM_SOPT5_UART0TXSRC field. */ 01278 #define BR_SIM_SOPT5_UART0TXSRC(x) (UNION_READ(hw_sim_sopt5_t, HW_SIM_SOPT5_ADDR(x), U, B.UART0TXSRC)) 01279 01280 /*! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC. */ 01281 #define BF_SIM_SOPT5_UART0TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0TXSRC) & BM_SIM_SOPT5_UART0TXSRC) 01282 01283 /*! @brief Set the UART0TXSRC field to a new value. */ 01284 #define BW_SIM_SOPT5_UART0TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v))) 01285 /*@}*/ 01286 01287 /*! 01288 * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW) 01289 * 01290 * Selects the source for the UART 0 receive data. 01291 * 01292 * Values: 01293 * - 00 - UART0_RX pin 01294 * - 01 - CMP0 01295 * - 10 - CMP1 01296 * - 11 - Reserved 01297 */ 01298 /*@{*/ 01299 #define BP_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit position for SIM_SOPT5_UART0RXSRC. */ 01300 #define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) /*!< Bit mask for SIM_SOPT5_UART0RXSRC. */ 01301 #define BS_SIM_SOPT5_UART0RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART0RXSRC. */ 01302 01303 /*! @brief Read current value of the SIM_SOPT5_UART0RXSRC field. */ 01304 #define BR_SIM_SOPT5_UART0RXSRC(x) (UNION_READ(hw_sim_sopt5_t, HW_SIM_SOPT5_ADDR(x), U, B.UART0RXSRC)) 01305 01306 /*! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC. */ 01307 #define BF_SIM_SOPT5_UART0RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART0RXSRC) & BM_SIM_SOPT5_UART0RXSRC) 01308 01309 /*! @brief Set the UART0RXSRC field to a new value. */ 01310 #define BW_SIM_SOPT5_UART0RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v))) 01311 /*@}*/ 01312 01313 /*! 01314 * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW) 01315 * 01316 * Selects the source for the UART 1 transmit data. 01317 * 01318 * Values: 01319 * - 00 - UART1_TX pin 01320 * - 01 - UART1_TX pin modulated with FTM1 channel 0 output 01321 * - 10 - UART1_TX pin modulated with FTM2 channel 0 output 01322 * - 11 - Reserved 01323 */ 01324 /*@{*/ 01325 #define BP_SIM_SOPT5_UART1TXSRC (4U) /*!< Bit position for SIM_SOPT5_UART1TXSRC. */ 01326 #define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) /*!< Bit mask for SIM_SOPT5_UART1TXSRC. */ 01327 #define BS_SIM_SOPT5_UART1TXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1TXSRC. */ 01328 01329 /*! @brief Read current value of the SIM_SOPT5_UART1TXSRC field. */ 01330 #define BR_SIM_SOPT5_UART1TXSRC(x) (UNION_READ(hw_sim_sopt5_t, HW_SIM_SOPT5_ADDR(x), U, B.UART1TXSRC)) 01331 01332 /*! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC. */ 01333 #define BF_SIM_SOPT5_UART1TXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1TXSRC) & BM_SIM_SOPT5_UART1TXSRC) 01334 01335 /*! @brief Set the UART1TXSRC field to a new value. */ 01336 #define BW_SIM_SOPT5_UART1TXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v))) 01337 /*@}*/ 01338 01339 /*! 01340 * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW) 01341 * 01342 * Selects the source for the UART 1 receive data. 01343 * 01344 * Values: 01345 * - 00 - UART1_RX pin 01346 * - 01 - CMP0 01347 * - 10 - CMP1 01348 * - 11 - Reserved 01349 */ 01350 /*@{*/ 01351 #define BP_SIM_SOPT5_UART1RXSRC (6U) /*!< Bit position for SIM_SOPT5_UART1RXSRC. */ 01352 #define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) /*!< Bit mask for SIM_SOPT5_UART1RXSRC. */ 01353 #define BS_SIM_SOPT5_UART1RXSRC (2U) /*!< Bit field size in bits for SIM_SOPT5_UART1RXSRC. */ 01354 01355 /*! @brief Read current value of the SIM_SOPT5_UART1RXSRC field. */ 01356 #define BR_SIM_SOPT5_UART1RXSRC(x) (UNION_READ(hw_sim_sopt5_t, HW_SIM_SOPT5_ADDR(x), U, B.UART1RXSRC)) 01357 01358 /*! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC. */ 01359 #define BF_SIM_SOPT5_UART1RXSRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT5_UART1RXSRC) & BM_SIM_SOPT5_UART1RXSRC) 01360 01361 /*! @brief Set the UART1RXSRC field to a new value. */ 01362 #define BW_SIM_SOPT5_UART1RXSRC(x, v) (HW_SIM_SOPT5_WR(x, (HW_SIM_SOPT5_RD(x) & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v))) 01363 /*@}*/ 01364 01365 /******************************************************************************* 01366 * HW_SIM_SOPT7 - System Options Register 7 01367 ******************************************************************************/ 01368 01369 /*! 01370 * @brief HW_SIM_SOPT7 - System Options Register 7 (RW) 01371 * 01372 * Reset value: 0x00000000U 01373 */ 01374 typedef union _hw_sim_sopt7 01375 { 01376 uint32_t U; 01377 struct _hw_sim_sopt7_bitfields 01378 { 01379 uint32_t ADC0TRGSEL : 4; /*!< [3:0] ADC0 trigger select */ 01380 uint32_t ADC0PRETRGSEL : 1; /*!< [4] ADC0 pretrigger select */ 01381 uint32_t RESERVED0 : 2; /*!< [6:5] */ 01382 uint32_t ADC0ALTTRGEN : 1; /*!< [7] ADC0 alternate trigger enable */ 01383 uint32_t ADC1TRGSEL : 4; /*!< [11:8] ADC1 trigger select */ 01384 uint32_t ADC1PRETRGSEL : 1; /*!< [12] ADC1 pre-trigger select */ 01385 uint32_t RESERVED1 : 2; /*!< [14:13] */ 01386 uint32_t ADC1ALTTRGEN : 1; /*!< [15] ADC1 alternate trigger enable */ 01387 uint32_t RESERVED2 : 16; /*!< [31:16] */ 01388 } B; 01389 } hw_sim_sopt7_t; 01390 01391 /*! 01392 * @name Constants and macros for entire SIM_SOPT7 register 01393 */ 01394 /*@{*/ 01395 #define HW_SIM_SOPT7_ADDR(x) ((x) + 0x1018U) 01396 01397 #define HW_SIM_SOPT7(x) (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR(x)) 01398 #define HW_SIM_SOPT7_RD(x) (ADDRESS_READ(hw_sim_sopt7_t, HW_SIM_SOPT7_ADDR(x))) 01399 #define HW_SIM_SOPT7_WR(x, v) (ADDRESS_WRITE(hw_sim_sopt7_t, HW_SIM_SOPT7_ADDR(x), v)) 01400 #define HW_SIM_SOPT7_SET(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) | (v))) 01401 #define HW_SIM_SOPT7_CLR(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) & ~(v))) 01402 #define HW_SIM_SOPT7_TOG(x, v) (HW_SIM_SOPT7_WR(x, HW_SIM_SOPT7_RD(x) ^ (v))) 01403 /*@}*/ 01404 01405 /* 01406 * Constants & macros for individual SIM_SOPT7 bitfields 01407 */ 01408 01409 /*! 01410 * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW) 01411 * 01412 * Selects the ADC0 trigger source when alternative triggers are functional in 01413 * stop and VLPS modes. . 01414 * 01415 * Values: 01416 * - 0000 - PDB external trigger pin input (PDB0_EXTRG) 01417 * - 0001 - High speed comparator 0 output 01418 * - 0010 - High speed comparator 1 output 01419 * - 0011 - High speed comparator 2 output 01420 * - 0100 - PIT trigger 0 01421 * - 0101 - PIT trigger 1 01422 * - 0110 - PIT trigger 2 01423 * - 0111 - PIT trigger 3 01424 * - 1000 - FTM0 trigger 01425 * - 1001 - FTM1 trigger 01426 * - 1010 - FTM2 trigger 01427 * - 1011 - FTM3 trigger 01428 * - 1100 - RTC alarm 01429 * - 1101 - RTC seconds 01430 * - 1110 - Low-power timer (LPTMR) trigger 01431 * - 1111 - Reserved 01432 */ 01433 /*@{*/ 01434 #define BP_SIM_SOPT7_ADC0TRGSEL (0U) /*!< Bit position for SIM_SOPT7_ADC0TRGSEL. */ 01435 #define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) /*!< Bit mask for SIM_SOPT7_ADC0TRGSEL. */ 01436 #define BS_SIM_SOPT7_ADC0TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL. */ 01437 01438 /*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */ 01439 #define BR_SIM_SOPT7_ADC0TRGSEL(x) (UNION_READ(hw_sim_sopt7_t, HW_SIM_SOPT7_ADDR(x), U, B.ADC0TRGSEL)) 01440 01441 /*! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL. */ 01442 #define BF_SIM_SOPT7_ADC0TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0TRGSEL) & BM_SIM_SOPT7_ADC0TRGSEL) 01443 01444 /*! @brief Set the ADC0TRGSEL field to a new value. */ 01445 #define BW_SIM_SOPT7_ADC0TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v))) 01446 /*@}*/ 01447 01448 /*! 01449 * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW) 01450 * 01451 * Selects the ADC0 pre-trigger source when alternative triggers are enabled 01452 * through ADC0ALTTRGEN. 01453 * 01454 * Values: 01455 * - 0 - Pre-trigger A 01456 * - 1 - Pre-trigger B 01457 */ 01458 /*@{*/ 01459 #define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) /*!< Bit position for SIM_SOPT7_ADC0PRETRGSEL. */ 01460 #define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) /*!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL. */ 01461 #define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL. */ 01462 01463 /*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */ 01464 #define BR_SIM_SOPT7_ADC0PRETRGSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL))) 01465 01466 /*! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL. */ 01467 #define BF_SIM_SOPT7_ADC0PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0PRETRGSEL) & BM_SIM_SOPT7_ADC0PRETRGSEL) 01468 01469 /*! @brief Set the ADC0PRETRGSEL field to a new value. */ 01470 #define BW_SIM_SOPT7_ADC0PRETRGSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0PRETRGSEL), v)) 01471 /*@}*/ 01472 01473 /*! 01474 * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW) 01475 * 01476 * Enable alternative conversion triggers for ADC0. 01477 * 01478 * Values: 01479 * - 0 - PDB trigger selected for ADC0. 01480 * - 1 - Alternate trigger selected for ADC0. 01481 */ 01482 /*@{*/ 01483 #define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) /*!< Bit position for SIM_SOPT7_ADC0ALTTRGEN. */ 01484 #define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) /*!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN. */ 01485 #define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN. */ 01486 01487 /*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */ 01488 #define BR_SIM_SOPT7_ADC0ALTTRGEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN))) 01489 01490 /*! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN. */ 01491 #define BF_SIM_SOPT7_ADC0ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC0ALTTRGEN) & BM_SIM_SOPT7_ADC0ALTTRGEN) 01492 01493 /*! @brief Set the ADC0ALTTRGEN field to a new value. */ 01494 #define BW_SIM_SOPT7_ADC0ALTTRGEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC0ALTTRGEN), v)) 01495 /*@}*/ 01496 01497 /*! 01498 * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW) 01499 * 01500 * Selects the ADC1 trigger source when alternative triggers are functional in 01501 * stop and VLPS modes. 01502 * 01503 * Values: 01504 * - 0000 - PDB external trigger pin input (PDB0_EXTRG) 01505 * - 0001 - High speed comparator 0 output 01506 * - 0010 - High speed comparator 1 output 01507 * - 0011 - High speed comparator 2 output 01508 * - 0100 - PIT trigger 0 01509 * - 0101 - PIT trigger 1 01510 * - 0110 - PIT trigger 2 01511 * - 0111 - PIT trigger 3 01512 * - 1000 - FTM0 trigger 01513 * - 1001 - FTM1 trigger 01514 * - 1010 - FTM2 trigger 01515 * - 1011 - FTM3 trigger 01516 * - 1100 - RTC alarm 01517 * - 1101 - RTC seconds 01518 * - 1110 - Low-power timer (LPTMR) trigger 01519 * - 1111 - Reserved 01520 */ 01521 /*@{*/ 01522 #define BP_SIM_SOPT7_ADC1TRGSEL (8U) /*!< Bit position for SIM_SOPT7_ADC1TRGSEL. */ 01523 #define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) /*!< Bit mask for SIM_SOPT7_ADC1TRGSEL. */ 01524 #define BS_SIM_SOPT7_ADC1TRGSEL (4U) /*!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL. */ 01525 01526 /*! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field. */ 01527 #define BR_SIM_SOPT7_ADC1TRGSEL(x) (UNION_READ(hw_sim_sopt7_t, HW_SIM_SOPT7_ADDR(x), U, B.ADC1TRGSEL)) 01528 01529 /*! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL. */ 01530 #define BF_SIM_SOPT7_ADC1TRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1TRGSEL) & BM_SIM_SOPT7_ADC1TRGSEL) 01531 01532 /*! @brief Set the ADC1TRGSEL field to a new value. */ 01533 #define BW_SIM_SOPT7_ADC1TRGSEL(x, v) (HW_SIM_SOPT7_WR(x, (HW_SIM_SOPT7_RD(x) & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v))) 01534 /*@}*/ 01535 01536 /*! 01537 * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW) 01538 * 01539 * Selects the ADC1 pre-trigger source when alternative triggers are enabled 01540 * through ADC1ALTTRGEN. 01541 * 01542 * Values: 01543 * - 0 - Pre-trigger A selected for ADC1. 01544 * - 1 - Pre-trigger B selected for ADC1. 01545 */ 01546 /*@{*/ 01547 #define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) /*!< Bit position for SIM_SOPT7_ADC1PRETRGSEL. */ 01548 #define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) /*!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL. */ 01549 #define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL. */ 01550 01551 /*! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field. */ 01552 #define BR_SIM_SOPT7_ADC1PRETRGSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL))) 01553 01554 /*! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL. */ 01555 #define BF_SIM_SOPT7_ADC1PRETRGSEL(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1PRETRGSEL) & BM_SIM_SOPT7_ADC1PRETRGSEL) 01556 01557 /*! @brief Set the ADC1PRETRGSEL field to a new value. */ 01558 #define BW_SIM_SOPT7_ADC1PRETRGSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1PRETRGSEL), v)) 01559 /*@}*/ 01560 01561 /*! 01562 * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW) 01563 * 01564 * Enable alternative conversion triggers for ADC1. 01565 * 01566 * Values: 01567 * - 0 - PDB trigger selected for ADC1 01568 * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. 01569 */ 01570 /*@{*/ 01571 #define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) /*!< Bit position for SIM_SOPT7_ADC1ALTTRGEN. */ 01572 #define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) /*!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN. */ 01573 #define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) /*!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN. */ 01574 01575 /*! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field. */ 01576 #define BR_SIM_SOPT7_ADC1ALTTRGEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN))) 01577 01578 /*! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN. */ 01579 #define BF_SIM_SOPT7_ADC1ALTTRGEN(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SOPT7_ADC1ALTTRGEN) & BM_SIM_SOPT7_ADC1ALTTRGEN) 01580 01581 /*! @brief Set the ADC1ALTTRGEN field to a new value. */ 01582 #define BW_SIM_SOPT7_ADC1ALTTRGEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SOPT7_ADDR(x), BP_SIM_SOPT7_ADC1ALTTRGEN), v)) 01583 /*@}*/ 01584 01585 /******************************************************************************* 01586 * HW_SIM_SDID - System Device Identification Register 01587 ******************************************************************************/ 01588 01589 /*! 01590 * @brief HW_SIM_SDID - System Device Identification Register (RO) 01591 * 01592 * Reset value: 0x00000380U 01593 */ 01594 typedef union _hw_sim_sdid 01595 { 01596 uint32_t U; 01597 struct _hw_sim_sdid_bitfields 01598 { 01599 uint32_t PINID : 4; /*!< [3:0] Pincount identification */ 01600 uint32_t FAMID : 3; /*!< [6:4] Kinetis family identification */ 01601 uint32_t DIEID : 5; /*!< [11:7] Device Die ID */ 01602 uint32_t REVID : 4; /*!< [15:12] Device revision number */ 01603 uint32_t RESERVED0 : 4; /*!< [19:16] */ 01604 uint32_t SERIESID : 4; /*!< [23:20] Kinetis Series ID */ 01605 uint32_t SUBFAMID : 4; /*!< [27:24] Kinetis Sub-Family ID */ 01606 uint32_t FAMILYID : 4; /*!< [31:28] Kinetis Family ID */ 01607 } B; 01608 } hw_sim_sdid_t; 01609 01610 /*! 01611 * @name Constants and macros for entire SIM_SDID register 01612 */ 01613 /*@{*/ 01614 #define HW_SIM_SDID_ADDR(x) ((x) + 0x1024U) 01615 01616 #define HW_SIM_SDID(x) (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR(x)) 01617 #define HW_SIM_SDID_RD(x) (ADDRESS_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x))) 01618 /*@}*/ 01619 01620 /* 01621 * Constants & macros for individual SIM_SDID bitfields 01622 */ 01623 01624 /*! 01625 * @name Register SIM_SDID, field PINID[3:0] (RO) 01626 * 01627 * Specifies the pincount of the device. 01628 * 01629 * Values: 01630 * - 0000 - Reserved 01631 * - 0001 - Reserved 01632 * - 0010 - 32-pin 01633 * - 0011 - Reserved 01634 * - 0100 - 48-pin 01635 * - 0101 - 64-pin 01636 * - 0110 - 80-pin 01637 * - 0111 - 81-pin or 121-pin 01638 * - 1000 - 100-pin 01639 * - 1001 - 121-pin 01640 * - 1010 - 144-pin 01641 * - 1011 - Custom pinout (WLCSP) 01642 * - 1100 - 169-pin 01643 * - 1101 - Reserved 01644 * - 1110 - 256-pin 01645 * - 1111 - Reserved 01646 */ 01647 /*@{*/ 01648 #define BP_SIM_SDID_PINID (0U) /*!< Bit position for SIM_SDID_PINID. */ 01649 #define BM_SIM_SDID_PINID (0x0000000FU) /*!< Bit mask for SIM_SDID_PINID. */ 01650 #define BS_SIM_SDID_PINID (4U) /*!< Bit field size in bits for SIM_SDID_PINID. */ 01651 01652 /*! @brief Read current value of the SIM_SDID_PINID field. */ 01653 #define BR_SIM_SDID_PINID(x) (UNION_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x), U, B.PINID)) 01654 /*@}*/ 01655 01656 /*! 01657 * @name Register SIM_SDID, field FAMID[6:4] (RO) 01658 * 01659 * This field is maintained for compatibility only, but has been superceded by 01660 * the SERIESID, FAMILYID and SUBFAMID fields in this register. 01661 * 01662 * Values: 01663 * - 000 - K1x Family (without tamper) 01664 * - 001 - K2x Family (without tamper) 01665 * - 010 - K3x Family or K1x/K6x Family (with tamper) 01666 * - 011 - K4x Family or K2x Family (with tamper) 01667 * - 100 - K6x Family (without tamper) 01668 * - 101 - K7x Family 01669 * - 110 - Reserved 01670 * - 111 - Reserved 01671 */ 01672 /*@{*/ 01673 #define BP_SIM_SDID_FAMID (4U) /*!< Bit position for SIM_SDID_FAMID. */ 01674 #define BM_SIM_SDID_FAMID (0x00000070U) /*!< Bit mask for SIM_SDID_FAMID. */ 01675 #define BS_SIM_SDID_FAMID (3U) /*!< Bit field size in bits for SIM_SDID_FAMID. */ 01676 01677 /*! @brief Read current value of the SIM_SDID_FAMID field. */ 01678 #define BR_SIM_SDID_FAMID(x) (UNION_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x), U, B.FAMID)) 01679 /*@}*/ 01680 01681 /*! 01682 * @name Register SIM_SDID, field DIEID[11:7] (RO) 01683 * 01684 * Specifies the silicon feature set identication number for the device. 01685 */ 01686 /*@{*/ 01687 #define BP_SIM_SDID_DIEID (7U) /*!< Bit position for SIM_SDID_DIEID. */ 01688 #define BM_SIM_SDID_DIEID (0x00000F80U) /*!< Bit mask for SIM_SDID_DIEID. */ 01689 #define BS_SIM_SDID_DIEID (5U) /*!< Bit field size in bits for SIM_SDID_DIEID. */ 01690 01691 /*! @brief Read current value of the SIM_SDID_DIEID field. */ 01692 #define BR_SIM_SDID_DIEID(x) (UNION_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x), U, B.DIEID)) 01693 /*@}*/ 01694 01695 /*! 01696 * @name Register SIM_SDID, field REVID[15:12] (RO) 01697 * 01698 * Specifies the silicon implementation number for the device. 01699 */ 01700 /*@{*/ 01701 #define BP_SIM_SDID_REVID (12U) /*!< Bit position for SIM_SDID_REVID. */ 01702 #define BM_SIM_SDID_REVID (0x0000F000U) /*!< Bit mask for SIM_SDID_REVID. */ 01703 #define BS_SIM_SDID_REVID (4U) /*!< Bit field size in bits for SIM_SDID_REVID. */ 01704 01705 /*! @brief Read current value of the SIM_SDID_REVID field. */ 01706 #define BR_SIM_SDID_REVID(x) (UNION_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x), U, B.REVID)) 01707 /*@}*/ 01708 01709 /*! 01710 * @name Register SIM_SDID, field SERIESID[23:20] (RO) 01711 * 01712 * Specifies the Kinetis series of the device. 01713 * 01714 * Values: 01715 * - 0000 - Kinetis K series 01716 * - 0001 - Kinetis L series 01717 * - 0101 - Kinetis W series 01718 * - 0110 - Kinetis V series 01719 */ 01720 /*@{*/ 01721 #define BP_SIM_SDID_SERIESID (20U) /*!< Bit position for SIM_SDID_SERIESID. */ 01722 #define BM_SIM_SDID_SERIESID (0x00F00000U) /*!< Bit mask for SIM_SDID_SERIESID. */ 01723 #define BS_SIM_SDID_SERIESID (4U) /*!< Bit field size in bits for SIM_SDID_SERIESID. */ 01724 01725 /*! @brief Read current value of the SIM_SDID_SERIESID field. */ 01726 #define BR_SIM_SDID_SERIESID(x) (UNION_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x), U, B.SERIESID)) 01727 /*@}*/ 01728 01729 /*! 01730 * @name Register SIM_SDID, field SUBFAMID[27:24] (RO) 01731 * 01732 * Specifies the Kinetis sub-family of the device. 01733 * 01734 * Values: 01735 * - 0000 - Kx0 Subfamily 01736 * - 0001 - Kx1 Subfamily (tamper detect) 01737 * - 0010 - Kx2 Subfamily 01738 * - 0011 - Kx3 Subfamily (tamper detect) 01739 * - 0100 - Kx4 Subfamily 01740 * - 0101 - Kx5 Subfamily (tamper detect) 01741 * - 0110 - Kx6 Subfamily 01742 */ 01743 /*@{*/ 01744 #define BP_SIM_SDID_SUBFAMID (24U) /*!< Bit position for SIM_SDID_SUBFAMID. */ 01745 #define BM_SIM_SDID_SUBFAMID (0x0F000000U) /*!< Bit mask for SIM_SDID_SUBFAMID. */ 01746 #define BS_SIM_SDID_SUBFAMID (4U) /*!< Bit field size in bits for SIM_SDID_SUBFAMID. */ 01747 01748 /*! @brief Read current value of the SIM_SDID_SUBFAMID field. */ 01749 #define BR_SIM_SDID_SUBFAMID(x) (UNION_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x), U, B.SUBFAMID)) 01750 /*@}*/ 01751 01752 /*! 01753 * @name Register SIM_SDID, field FAMILYID[31:28] (RO) 01754 * 01755 * Specifies the Kinetis family of the device. 01756 * 01757 * Values: 01758 * - 0001 - K1x Family 01759 * - 0010 - K2x Family 01760 * - 0011 - K3x Family 01761 * - 0100 - K4x Family 01762 * - 0110 - K6x Family 01763 * - 0111 - K7x Family 01764 */ 01765 /*@{*/ 01766 #define BP_SIM_SDID_FAMILYID (28U) /*!< Bit position for SIM_SDID_FAMILYID. */ 01767 #define BM_SIM_SDID_FAMILYID (0xF0000000U) /*!< Bit mask for SIM_SDID_FAMILYID. */ 01768 #define BS_SIM_SDID_FAMILYID (4U) /*!< Bit field size in bits for SIM_SDID_FAMILYID. */ 01769 01770 /*! @brief Read current value of the SIM_SDID_FAMILYID field. */ 01771 #define BR_SIM_SDID_FAMILYID(x) (UNION_READ(hw_sim_sdid_t, HW_SIM_SDID_ADDR(x), U, B.FAMILYID)) 01772 /*@}*/ 01773 01774 /******************************************************************************* 01775 * HW_SIM_SCGC1 - System Clock Gating Control Register 1 01776 ******************************************************************************/ 01777 01778 /*! 01779 * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW) 01780 * 01781 * Reset value: 0x00000000U 01782 */ 01783 typedef union _hw_sim_scgc1 01784 { 01785 uint32_t U; 01786 struct _hw_sim_scgc1_bitfields 01787 { 01788 uint32_t RESERVED0 : 6; /*!< [5:0] */ 01789 uint32_t I2C2b : 1; /*!< [6] I2C2 Clock Gate Control */ 01790 uint32_t RESERVED1 : 3; /*!< [9:7] */ 01791 uint32_t UART4b : 1; /*!< [10] UART4 Clock Gate Control */ 01792 uint32_t UART5b : 1; /*!< [11] UART5 Clock Gate Control */ 01793 uint32_t RESERVED2 : 20; /*!< [31:12] */ 01794 } B; 01795 } hw_sim_scgc1_t; 01796 01797 /*! 01798 * @name Constants and macros for entire SIM_SCGC1 register 01799 */ 01800 /*@{*/ 01801 #define HW_SIM_SCGC1_ADDR(x) ((x) + 0x1028U) 01802 01803 #define HW_SIM_SCGC1(x) (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR(x)) 01804 #define HW_SIM_SCGC1_RD(x) (ADDRESS_READ(hw_sim_scgc1_t, HW_SIM_SCGC1_ADDR(x))) 01805 #define HW_SIM_SCGC1_WR(x, v) (ADDRESS_WRITE(hw_sim_scgc1_t, HW_SIM_SCGC1_ADDR(x), v)) 01806 #define HW_SIM_SCGC1_SET(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) | (v))) 01807 #define HW_SIM_SCGC1_CLR(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) & ~(v))) 01808 #define HW_SIM_SCGC1_TOG(x, v) (HW_SIM_SCGC1_WR(x, HW_SIM_SCGC1_RD(x) ^ (v))) 01809 /*@}*/ 01810 01811 /* 01812 * Constants & macros for individual SIM_SCGC1 bitfields 01813 */ 01814 01815 /*! 01816 * @name Register SIM_SCGC1, field I2C2[6] (RW) 01817 * 01818 * This bit controls the clock gate to the I2C2 module. 01819 * 01820 * Values: 01821 * - 0 - Clock disabled 01822 * - 1 - Clock enabled 01823 */ 01824 /*@{*/ 01825 #define BP_SIM_SCGC1_I2C2 (6U) /*!< Bit position for SIM_SCGC1_I2C2. */ 01826 #define BM_SIM_SCGC1_I2C2 (0x00000040U) /*!< Bit mask for SIM_SCGC1_I2C2. */ 01827 #define BS_SIM_SCGC1_I2C2 (1U) /*!< Bit field size in bits for SIM_SCGC1_I2C2. */ 01828 01829 /*! @brief Read current value of the SIM_SCGC1_I2C2 field. */ 01830 #define BR_SIM_SCGC1_I2C2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2))) 01831 01832 /*! @brief Format value for bitfield SIM_SCGC1_I2C2. */ 01833 #define BF_SIM_SCGC1_I2C2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_I2C2) & BM_SIM_SCGC1_I2C2) 01834 01835 /*! @brief Set the I2C2 field to a new value. */ 01836 #define BW_SIM_SCGC1_I2C2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_I2C2), v)) 01837 /*@}*/ 01838 01839 /*! 01840 * @name Register SIM_SCGC1, field UART4[10] (RW) 01841 * 01842 * This bit controls the clock gate to the UART4 module. 01843 * 01844 * Values: 01845 * - 0 - Clock disabled 01846 * - 1 - Clock enabled 01847 */ 01848 /*@{*/ 01849 #define BP_SIM_SCGC1_UART4 (10U) /*!< Bit position for SIM_SCGC1_UART4. */ 01850 #define BM_SIM_SCGC1_UART4 (0x00000400U) /*!< Bit mask for SIM_SCGC1_UART4. */ 01851 #define BS_SIM_SCGC1_UART4 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART4. */ 01852 01853 /*! @brief Read current value of the SIM_SCGC1_UART4 field. */ 01854 #define BR_SIM_SCGC1_UART4(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4))) 01855 01856 /*! @brief Format value for bitfield SIM_SCGC1_UART4. */ 01857 #define BF_SIM_SCGC1_UART4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART4) & BM_SIM_SCGC1_UART4) 01858 01859 /*! @brief Set the UART4 field to a new value. */ 01860 #define BW_SIM_SCGC1_UART4(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART4), v)) 01861 /*@}*/ 01862 01863 /*! 01864 * @name Register SIM_SCGC1, field UART5[11] (RW) 01865 * 01866 * This bit controls the clock gate to the UART5 module. 01867 * 01868 * Values: 01869 * - 0 - Clock disabled 01870 * - 1 - Clock enabled 01871 */ 01872 /*@{*/ 01873 #define BP_SIM_SCGC1_UART5 (11U) /*!< Bit position for SIM_SCGC1_UART5. */ 01874 #define BM_SIM_SCGC1_UART5 (0x00000800U) /*!< Bit mask for SIM_SCGC1_UART5. */ 01875 #define BS_SIM_SCGC1_UART5 (1U) /*!< Bit field size in bits for SIM_SCGC1_UART5. */ 01876 01877 /*! @brief Read current value of the SIM_SCGC1_UART5 field. */ 01878 #define BR_SIM_SCGC1_UART5(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5))) 01879 01880 /*! @brief Format value for bitfield SIM_SCGC1_UART5. */ 01881 #define BF_SIM_SCGC1_UART5(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC1_UART5) & BM_SIM_SCGC1_UART5) 01882 01883 /*! @brief Set the UART5 field to a new value. */ 01884 #define BW_SIM_SCGC1_UART5(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC1_ADDR(x), BP_SIM_SCGC1_UART5), v)) 01885 /*@}*/ 01886 01887 /******************************************************************************* 01888 * HW_SIM_SCGC2 - System Clock Gating Control Register 2 01889 ******************************************************************************/ 01890 01891 /*! 01892 * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW) 01893 * 01894 * Reset value: 0x00000000U 01895 * 01896 * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through 01897 * AIPS1, define the clock gate control bits in the SCGC2. When accessing through 01898 * AIPS0, define the clock gate control bits in SCGC6. 01899 */ 01900 typedef union _hw_sim_scgc2 01901 { 01902 uint32_t U; 01903 struct _hw_sim_scgc2_bitfields 01904 { 01905 uint32_t ENETb : 1; /*!< [0] ENET Clock Gate Control */ 01906 uint32_t RESERVED0 : 11; /*!< [11:1] */ 01907 uint32_t DAC0b : 1; /*!< [12] DAC0 Clock Gate Control */ 01908 uint32_t DAC1b : 1; /*!< [13] DAC1 Clock Gate Control */ 01909 uint32_t RESERVED1 : 18; /*!< [31:14] */ 01910 } B; 01911 } hw_sim_scgc2_t; 01912 01913 /*! 01914 * @name Constants and macros for entire SIM_SCGC2 register 01915 */ 01916 /*@{*/ 01917 #define HW_SIM_SCGC2_ADDR(x) ((x) + 0x102CU) 01918 01919 #define HW_SIM_SCGC2(x) (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR(x)) 01920 #define HW_SIM_SCGC2_RD(x) (ADDRESS_READ(hw_sim_scgc2_t, HW_SIM_SCGC2_ADDR(x))) 01921 #define HW_SIM_SCGC2_WR(x, v) (ADDRESS_WRITE(hw_sim_scgc2_t, HW_SIM_SCGC2_ADDR(x), v)) 01922 #define HW_SIM_SCGC2_SET(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) | (v))) 01923 #define HW_SIM_SCGC2_CLR(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) & ~(v))) 01924 #define HW_SIM_SCGC2_TOG(x, v) (HW_SIM_SCGC2_WR(x, HW_SIM_SCGC2_RD(x) ^ (v))) 01925 /*@}*/ 01926 01927 /* 01928 * Constants & macros for individual SIM_SCGC2 bitfields 01929 */ 01930 01931 /*! 01932 * @name Register SIM_SCGC2, field ENET[0] (RW) 01933 * 01934 * This bit controls the clock gate to the ENET module. 01935 * 01936 * Values: 01937 * - 0 - Clock disabled 01938 * - 1 - Clock enabled 01939 */ 01940 /*@{*/ 01941 #define BP_SIM_SCGC2_ENET (0U) /*!< Bit position for SIM_SCGC2_ENET. */ 01942 #define BM_SIM_SCGC2_ENET (0x00000001U) /*!< Bit mask for SIM_SCGC2_ENET. */ 01943 #define BS_SIM_SCGC2_ENET (1U) /*!< Bit field size in bits for SIM_SCGC2_ENET. */ 01944 01945 /*! @brief Read current value of the SIM_SCGC2_ENET field. */ 01946 #define BR_SIM_SCGC2_ENET(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET))) 01947 01948 /*! @brief Format value for bitfield SIM_SCGC2_ENET. */ 01949 #define BF_SIM_SCGC2_ENET(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_ENET) & BM_SIM_SCGC2_ENET) 01950 01951 /*! @brief Set the ENET field to a new value. */ 01952 #define BW_SIM_SCGC2_ENET(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_ENET), v)) 01953 /*@}*/ 01954 01955 /*! 01956 * @name Register SIM_SCGC2, field DAC0[12] (RW) 01957 * 01958 * This bit controls the clock gate to the DAC0 module. 01959 * 01960 * Values: 01961 * - 0 - Clock disabled 01962 * - 1 - Clock enabled 01963 */ 01964 /*@{*/ 01965 #define BP_SIM_SCGC2_DAC0 (12U) /*!< Bit position for SIM_SCGC2_DAC0. */ 01966 #define BM_SIM_SCGC2_DAC0 (0x00001000U) /*!< Bit mask for SIM_SCGC2_DAC0. */ 01967 #define BS_SIM_SCGC2_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC0. */ 01968 01969 /*! @brief Read current value of the SIM_SCGC2_DAC0 field. */ 01970 #define BR_SIM_SCGC2_DAC0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0))) 01971 01972 /*! @brief Format value for bitfield SIM_SCGC2_DAC0. */ 01973 #define BF_SIM_SCGC2_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC0) & BM_SIM_SCGC2_DAC0) 01974 01975 /*! @brief Set the DAC0 field to a new value. */ 01976 #define BW_SIM_SCGC2_DAC0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC0), v)) 01977 /*@}*/ 01978 01979 /*! 01980 * @name Register SIM_SCGC2, field DAC1[13] (RW) 01981 * 01982 * This bit controls the clock gate to the DAC1 module. 01983 * 01984 * Values: 01985 * - 0 - Clock disabled 01986 * - 1 - Clock enabled 01987 */ 01988 /*@{*/ 01989 #define BP_SIM_SCGC2_DAC1 (13U) /*!< Bit position for SIM_SCGC2_DAC1. */ 01990 #define BM_SIM_SCGC2_DAC1 (0x00002000U) /*!< Bit mask for SIM_SCGC2_DAC1. */ 01991 #define BS_SIM_SCGC2_DAC1 (1U) /*!< Bit field size in bits for SIM_SCGC2_DAC1. */ 01992 01993 /*! @brief Read current value of the SIM_SCGC2_DAC1 field. */ 01994 #define BR_SIM_SCGC2_DAC1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1))) 01995 01996 /*! @brief Format value for bitfield SIM_SCGC2_DAC1. */ 01997 #define BF_SIM_SCGC2_DAC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC2_DAC1) & BM_SIM_SCGC2_DAC1) 01998 01999 /*! @brief Set the DAC1 field to a new value. */ 02000 #define BW_SIM_SCGC2_DAC1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC2_ADDR(x), BP_SIM_SCGC2_DAC1), v)) 02001 /*@}*/ 02002 02003 /******************************************************************************* 02004 * HW_SIM_SCGC3 - System Clock Gating Control Register 3 02005 ******************************************************************************/ 02006 02007 /*! 02008 * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW) 02009 * 02010 * Reset value: 0x00000000U 02011 * 02012 * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing 02013 * through AIPS1, define the clock gate control bits in the SCGC3. When accessing 02014 * through AIPS0, define the clock gate control bits in SCGC6. 02015 */ 02016 typedef union _hw_sim_scgc3 02017 { 02018 uint32_t U; 02019 struct _hw_sim_scgc3_bitfields 02020 { 02021 uint32_t RNGA : 1; /*!< [0] RNGA Clock Gate Control */ 02022 uint32_t RESERVED0 : 11; /*!< [11:1] */ 02023 uint32_t SPI2b : 1; /*!< [12] SPI2 Clock Gate Control */ 02024 uint32_t RESERVED1 : 4; /*!< [16:13] */ 02025 uint32_t SDHCb : 1; /*!< [17] SDHC Clock Gate Control */ 02026 uint32_t RESERVED2 : 6; /*!< [23:18] */ 02027 uint32_t FTM2b : 1; /*!< [24] FTM2 Clock Gate Control */ 02028 uint32_t FTM3b : 1; /*!< [25] FTM3 Clock Gate Control */ 02029 uint32_t RESERVED3 : 1; /*!< [26] */ 02030 uint32_t ADC1b : 1; /*!< [27] ADC1 Clock Gate Control */ 02031 uint32_t RESERVED4 : 4; /*!< [31:28] */ 02032 } B; 02033 } hw_sim_scgc3_t; 02034 02035 /*! 02036 * @name Constants and macros for entire SIM_SCGC3 register 02037 */ 02038 /*@{*/ 02039 #define HW_SIM_SCGC3_ADDR(x) ((x) + 0x1030U) 02040 02041 #define HW_SIM_SCGC3(x) (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR(x)) 02042 #define HW_SIM_SCGC3_RD(x) (ADDRESS_READ(hw_sim_scgc3_t, HW_SIM_SCGC3_ADDR(x))) 02043 #define HW_SIM_SCGC3_WR(x, v) (ADDRESS_WRITE(hw_sim_scgc3_t, HW_SIM_SCGC3_ADDR(x), v)) 02044 #define HW_SIM_SCGC3_SET(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) | (v))) 02045 #define HW_SIM_SCGC3_CLR(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) & ~(v))) 02046 #define HW_SIM_SCGC3_TOG(x, v) (HW_SIM_SCGC3_WR(x, HW_SIM_SCGC3_RD(x) ^ (v))) 02047 /*@}*/ 02048 02049 /* 02050 * Constants & macros for individual SIM_SCGC3 bitfields 02051 */ 02052 02053 /*! 02054 * @name Register SIM_SCGC3, field RNGA[0] (RW) 02055 * 02056 * This bit controls the clock gate to the RNGA module. 02057 * 02058 * Values: 02059 * - 0 - Clock disabled 02060 * - 1 - Clock enabled 02061 */ 02062 /*@{*/ 02063 #define BP_SIM_SCGC3_RNGA (0U) /*!< Bit position for SIM_SCGC3_RNGA. */ 02064 #define BM_SIM_SCGC3_RNGA (0x00000001U) /*!< Bit mask for SIM_SCGC3_RNGA. */ 02065 #define BS_SIM_SCGC3_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC3_RNGA. */ 02066 02067 /*! @brief Read current value of the SIM_SCGC3_RNGA field. */ 02068 #define BR_SIM_SCGC3_RNGA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA))) 02069 02070 /*! @brief Format value for bitfield SIM_SCGC3_RNGA. */ 02071 #define BF_SIM_SCGC3_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_RNGA) & BM_SIM_SCGC3_RNGA) 02072 02073 /*! @brief Set the RNGA field to a new value. */ 02074 #define BW_SIM_SCGC3_RNGA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_RNGA), v)) 02075 /*@}*/ 02076 02077 /*! 02078 * @name Register SIM_SCGC3, field SPI2[12] (RW) 02079 * 02080 * This bit controls the clock gate to the SPI2 module. 02081 * 02082 * Values: 02083 * - 0 - Clock disabled 02084 * - 1 - Clock enabled 02085 */ 02086 /*@{*/ 02087 #define BP_SIM_SCGC3_SPI2 (12U) /*!< Bit position for SIM_SCGC3_SPI2. */ 02088 #define BM_SIM_SCGC3_SPI2 (0x00001000U) /*!< Bit mask for SIM_SCGC3_SPI2. */ 02089 #define BS_SIM_SCGC3_SPI2 (1U) /*!< Bit field size in bits for SIM_SCGC3_SPI2. */ 02090 02091 /*! @brief Read current value of the SIM_SCGC3_SPI2 field. */ 02092 #define BR_SIM_SCGC3_SPI2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2))) 02093 02094 /*! @brief Format value for bitfield SIM_SCGC3_SPI2. */ 02095 #define BF_SIM_SCGC3_SPI2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SPI2) & BM_SIM_SCGC3_SPI2) 02096 02097 /*! @brief Set the SPI2 field to a new value. */ 02098 #define BW_SIM_SCGC3_SPI2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SPI2), v)) 02099 /*@}*/ 02100 02101 /*! 02102 * @name Register SIM_SCGC3, field SDHC[17] (RW) 02103 * 02104 * This bit controls the clock gate to the SDHC module. 02105 * 02106 * Values: 02107 * - 0 - Clock disabled 02108 * - 1 - Clock enabled 02109 */ 02110 /*@{*/ 02111 #define BP_SIM_SCGC3_SDHC (17U) /*!< Bit position for SIM_SCGC3_SDHC. */ 02112 #define BM_SIM_SCGC3_SDHC (0x00020000U) /*!< Bit mask for SIM_SCGC3_SDHC. */ 02113 #define BS_SIM_SCGC3_SDHC (1U) /*!< Bit field size in bits for SIM_SCGC3_SDHC. */ 02114 02115 /*! @brief Read current value of the SIM_SCGC3_SDHC field. */ 02116 #define BR_SIM_SCGC3_SDHC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC))) 02117 02118 /*! @brief Format value for bitfield SIM_SCGC3_SDHC. */ 02119 #define BF_SIM_SCGC3_SDHC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_SDHC) & BM_SIM_SCGC3_SDHC) 02120 02121 /*! @brief Set the SDHC field to a new value. */ 02122 #define BW_SIM_SCGC3_SDHC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_SDHC), v)) 02123 /*@}*/ 02124 02125 /*! 02126 * @name Register SIM_SCGC3, field FTM2[24] (RW) 02127 * 02128 * This bit controls the clock gate to the FTM2 module. 02129 * 02130 * Values: 02131 * - 0 - Clock disabled 02132 * - 1 - Clock enabled 02133 */ 02134 /*@{*/ 02135 #define BP_SIM_SCGC3_FTM2 (24U) /*!< Bit position for SIM_SCGC3_FTM2. */ 02136 #define BM_SIM_SCGC3_FTM2 (0x01000000U) /*!< Bit mask for SIM_SCGC3_FTM2. */ 02137 #define BS_SIM_SCGC3_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM2. */ 02138 02139 /*! @brief Read current value of the SIM_SCGC3_FTM2 field. */ 02140 #define BR_SIM_SCGC3_FTM2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2))) 02141 02142 /*! @brief Format value for bitfield SIM_SCGC3_FTM2. */ 02143 #define BF_SIM_SCGC3_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM2) & BM_SIM_SCGC3_FTM2) 02144 02145 /*! @brief Set the FTM2 field to a new value. */ 02146 #define BW_SIM_SCGC3_FTM2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM2), v)) 02147 /*@}*/ 02148 02149 /*! 02150 * @name Register SIM_SCGC3, field FTM3[25] (RW) 02151 * 02152 * This bit controls the clock gate to the FTM3 module. 02153 * 02154 * Values: 02155 * - 0 - Clock disabled 02156 * - 1 - Clock enabled 02157 */ 02158 /*@{*/ 02159 #define BP_SIM_SCGC3_FTM3 (25U) /*!< Bit position for SIM_SCGC3_FTM3. */ 02160 #define BM_SIM_SCGC3_FTM3 (0x02000000U) /*!< Bit mask for SIM_SCGC3_FTM3. */ 02161 #define BS_SIM_SCGC3_FTM3 (1U) /*!< Bit field size in bits for SIM_SCGC3_FTM3. */ 02162 02163 /*! @brief Read current value of the SIM_SCGC3_FTM3 field. */ 02164 #define BR_SIM_SCGC3_FTM3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3))) 02165 02166 /*! @brief Format value for bitfield SIM_SCGC3_FTM3. */ 02167 #define BF_SIM_SCGC3_FTM3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_FTM3) & BM_SIM_SCGC3_FTM3) 02168 02169 /*! @brief Set the FTM3 field to a new value. */ 02170 #define BW_SIM_SCGC3_FTM3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_FTM3), v)) 02171 /*@}*/ 02172 02173 /*! 02174 * @name Register SIM_SCGC3, field ADC1[27] (RW) 02175 * 02176 * This bit controls the clock gate to the ADC1 module. 02177 * 02178 * Values: 02179 * - 0 - Clock disabled 02180 * - 1 - Clock enabled 02181 */ 02182 /*@{*/ 02183 #define BP_SIM_SCGC3_ADC1 (27U) /*!< Bit position for SIM_SCGC3_ADC1. */ 02184 #define BM_SIM_SCGC3_ADC1 (0x08000000U) /*!< Bit mask for SIM_SCGC3_ADC1. */ 02185 #define BS_SIM_SCGC3_ADC1 (1U) /*!< Bit field size in bits for SIM_SCGC3_ADC1. */ 02186 02187 /*! @brief Read current value of the SIM_SCGC3_ADC1 field. */ 02188 #define BR_SIM_SCGC3_ADC1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1))) 02189 02190 /*! @brief Format value for bitfield SIM_SCGC3_ADC1. */ 02191 #define BF_SIM_SCGC3_ADC1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC3_ADC1) & BM_SIM_SCGC3_ADC1) 02192 02193 /*! @brief Set the ADC1 field to a new value. */ 02194 #define BW_SIM_SCGC3_ADC1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC3_ADDR(x), BP_SIM_SCGC3_ADC1), v)) 02195 /*@}*/ 02196 02197 /******************************************************************************* 02198 * HW_SIM_SCGC4 - System Clock Gating Control Register 4 02199 ******************************************************************************/ 02200 02201 /*! 02202 * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW) 02203 * 02204 * Reset value: 0xF0100030U 02205 */ 02206 typedef union _hw_sim_scgc4 02207 { 02208 uint32_t U; 02209 struct _hw_sim_scgc4_bitfields 02210 { 02211 uint32_t RESERVED0 : 1; /*!< [0] */ 02212 uint32_t EWMb : 1; /*!< [1] EWM Clock Gate Control */ 02213 uint32_t CMTb : 1; /*!< [2] CMT Clock Gate Control */ 02214 uint32_t RESERVED1 : 3; /*!< [5:3] */ 02215 uint32_t I2C0b : 1; /*!< [6] I2C0 Clock Gate Control */ 02216 uint32_t I2C1b : 1; /*!< [7] I2C1 Clock Gate Control */ 02217 uint32_t RESERVED2 : 2; /*!< [9:8] */ 02218 uint32_t UART0b : 1; /*!< [10] UART0 Clock Gate Control */ 02219 uint32_t UART1b : 1; /*!< [11] UART1 Clock Gate Control */ 02220 uint32_t UART2b : 1; /*!< [12] UART2 Clock Gate Control */ 02221 uint32_t UART3b : 1; /*!< [13] UART3 Clock Gate Control */ 02222 uint32_t RESERVED3 : 4; /*!< [17:14] */ 02223 uint32_t USBOTG : 1; /*!< [18] USB Clock Gate Control */ 02224 uint32_t CMP : 1; /*!< [19] Comparator Clock Gate Control */ 02225 uint32_t VREFb : 1; /*!< [20] VREF Clock Gate Control */ 02226 uint32_t RESERVED4 : 11; /*!< [31:21] */ 02227 } B; 02228 } hw_sim_scgc4_t; 02229 02230 /*! 02231 * @name Constants and macros for entire SIM_SCGC4 register 02232 */ 02233 /*@{*/ 02234 #define HW_SIM_SCGC4_ADDR(x) ((x) + 0x1034U) 02235 02236 #define HW_SIM_SCGC4(x) (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR(x)) 02237 #define HW_SIM_SCGC4_RD(x) (ADDRESS_READ(hw_sim_scgc4_t, HW_SIM_SCGC4_ADDR(x))) 02238 #define HW_SIM_SCGC4_WR(x, v) (ADDRESS_WRITE(hw_sim_scgc4_t, HW_SIM_SCGC4_ADDR(x), v)) 02239 #define HW_SIM_SCGC4_SET(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) | (v))) 02240 #define HW_SIM_SCGC4_CLR(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) & ~(v))) 02241 #define HW_SIM_SCGC4_TOG(x, v) (HW_SIM_SCGC4_WR(x, HW_SIM_SCGC4_RD(x) ^ (v))) 02242 /*@}*/ 02243 02244 /* 02245 * Constants & macros for individual SIM_SCGC4 bitfields 02246 */ 02247 02248 /*! 02249 * @name Register SIM_SCGC4, field EWM[1] (RW) 02250 * 02251 * This bit controls the clock gate to the EWM module. 02252 * 02253 * Values: 02254 * - 0 - Clock disabled 02255 * - 1 - Clock enabled 02256 */ 02257 /*@{*/ 02258 #define BP_SIM_SCGC4_EWM (1U) /*!< Bit position for SIM_SCGC4_EWM. */ 02259 #define BM_SIM_SCGC4_EWM (0x00000002U) /*!< Bit mask for SIM_SCGC4_EWM. */ 02260 #define BS_SIM_SCGC4_EWM (1U) /*!< Bit field size in bits for SIM_SCGC4_EWM. */ 02261 02262 /*! @brief Read current value of the SIM_SCGC4_EWM field. */ 02263 #define BR_SIM_SCGC4_EWM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM))) 02264 02265 /*! @brief Format value for bitfield SIM_SCGC4_EWM. */ 02266 #define BF_SIM_SCGC4_EWM(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_EWM) & BM_SIM_SCGC4_EWM) 02267 02268 /*! @brief Set the EWM field to a new value. */ 02269 #define BW_SIM_SCGC4_EWM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_EWM), v)) 02270 /*@}*/ 02271 02272 /*! 02273 * @name Register SIM_SCGC4, field CMT[2] (RW) 02274 * 02275 * This bit controls the clock gate to the CMT module. 02276 * 02277 * Values: 02278 * - 0 - Clock disabled 02279 * - 1 - Clock enabled 02280 */ 02281 /*@{*/ 02282 #define BP_SIM_SCGC4_CMT (2U) /*!< Bit position for SIM_SCGC4_CMT. */ 02283 #define BM_SIM_SCGC4_CMT (0x00000004U) /*!< Bit mask for SIM_SCGC4_CMT. */ 02284 #define BS_SIM_SCGC4_CMT (1U) /*!< Bit field size in bits for SIM_SCGC4_CMT. */ 02285 02286 /*! @brief Read current value of the SIM_SCGC4_CMT field. */ 02287 #define BR_SIM_SCGC4_CMT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT))) 02288 02289 /*! @brief Format value for bitfield SIM_SCGC4_CMT. */ 02290 #define BF_SIM_SCGC4_CMT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMT) & BM_SIM_SCGC4_CMT) 02291 02292 /*! @brief Set the CMT field to a new value. */ 02293 #define BW_SIM_SCGC4_CMT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMT), v)) 02294 /*@}*/ 02295 02296 /*! 02297 * @name Register SIM_SCGC4, field I2C0[6] (RW) 02298 * 02299 * This bit controls the clock gate to the I 2 C0 module. 02300 * 02301 * Values: 02302 * - 0 - Clock disabled 02303 * - 1 - Clock enabled 02304 */ 02305 /*@{*/ 02306 #define BP_SIM_SCGC4_I2C0 (6U) /*!< Bit position for SIM_SCGC4_I2C0. */ 02307 #define BM_SIM_SCGC4_I2C0 (0x00000040U) /*!< Bit mask for SIM_SCGC4_I2C0. */ 02308 #define BS_SIM_SCGC4_I2C0 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C0. */ 02309 02310 /*! @brief Read current value of the SIM_SCGC4_I2C0 field. */ 02311 #define BR_SIM_SCGC4_I2C0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0))) 02312 02313 /*! @brief Format value for bitfield SIM_SCGC4_I2C0. */ 02314 #define BF_SIM_SCGC4_I2C0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C0) & BM_SIM_SCGC4_I2C0) 02315 02316 /*! @brief Set the I2C0 field to a new value. */ 02317 #define BW_SIM_SCGC4_I2C0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C0), v)) 02318 /*@}*/ 02319 02320 /*! 02321 * @name Register SIM_SCGC4, field I2C1[7] (RW) 02322 * 02323 * This bit controls the clock gate to the I 2 C1 module. 02324 * 02325 * Values: 02326 * - 0 - Clock disabled 02327 * - 1 - Clock enabled 02328 */ 02329 /*@{*/ 02330 #define BP_SIM_SCGC4_I2C1 (7U) /*!< Bit position for SIM_SCGC4_I2C1. */ 02331 #define BM_SIM_SCGC4_I2C1 (0x00000080U) /*!< Bit mask for SIM_SCGC4_I2C1. */ 02332 #define BS_SIM_SCGC4_I2C1 (1U) /*!< Bit field size in bits for SIM_SCGC4_I2C1. */ 02333 02334 /*! @brief Read current value of the SIM_SCGC4_I2C1 field. */ 02335 #define BR_SIM_SCGC4_I2C1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1))) 02336 02337 /*! @brief Format value for bitfield SIM_SCGC4_I2C1. */ 02338 #define BF_SIM_SCGC4_I2C1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_I2C1) & BM_SIM_SCGC4_I2C1) 02339 02340 /*! @brief Set the I2C1 field to a new value. */ 02341 #define BW_SIM_SCGC4_I2C1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_I2C1), v)) 02342 /*@}*/ 02343 02344 /*! 02345 * @name Register SIM_SCGC4, field UART0[10] (RW) 02346 * 02347 * This bit controls the clock gate to the UART0 module. 02348 * 02349 * Values: 02350 * - 0 - Clock disabled 02351 * - 1 - Clock enabled 02352 */ 02353 /*@{*/ 02354 #define BP_SIM_SCGC4_UART0 (10U) /*!< Bit position for SIM_SCGC4_UART0. */ 02355 #define BM_SIM_SCGC4_UART0 (0x00000400U) /*!< Bit mask for SIM_SCGC4_UART0. */ 02356 #define BS_SIM_SCGC4_UART0 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART0. */ 02357 02358 /*! @brief Read current value of the SIM_SCGC4_UART0 field. */ 02359 #define BR_SIM_SCGC4_UART0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0))) 02360 02361 /*! @brief Format value for bitfield SIM_SCGC4_UART0. */ 02362 #define BF_SIM_SCGC4_UART0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART0) & BM_SIM_SCGC4_UART0) 02363 02364 /*! @brief Set the UART0 field to a new value. */ 02365 #define BW_SIM_SCGC4_UART0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART0), v)) 02366 /*@}*/ 02367 02368 /*! 02369 * @name Register SIM_SCGC4, field UART1[11] (RW) 02370 * 02371 * This bit controls the clock gate to the UART1 module. 02372 * 02373 * Values: 02374 * - 0 - Clock disabled 02375 * - 1 - Clock enabled 02376 */ 02377 /*@{*/ 02378 #define BP_SIM_SCGC4_UART1 (11U) /*!< Bit position for SIM_SCGC4_UART1. */ 02379 #define BM_SIM_SCGC4_UART1 (0x00000800U) /*!< Bit mask for SIM_SCGC4_UART1. */ 02380 #define BS_SIM_SCGC4_UART1 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART1. */ 02381 02382 /*! @brief Read current value of the SIM_SCGC4_UART1 field. */ 02383 #define BR_SIM_SCGC4_UART1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1))) 02384 02385 /*! @brief Format value for bitfield SIM_SCGC4_UART1. */ 02386 #define BF_SIM_SCGC4_UART1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART1) & BM_SIM_SCGC4_UART1) 02387 02388 /*! @brief Set the UART1 field to a new value. */ 02389 #define BW_SIM_SCGC4_UART1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART1), v)) 02390 /*@}*/ 02391 02392 /*! 02393 * @name Register SIM_SCGC4, field UART2[12] (RW) 02394 * 02395 * This bit controls the clock gate to the UART2 module. 02396 * 02397 * Values: 02398 * - 0 - Clock disabled 02399 * - 1 - Clock enabled 02400 */ 02401 /*@{*/ 02402 #define BP_SIM_SCGC4_UART2 (12U) /*!< Bit position for SIM_SCGC4_UART2. */ 02403 #define BM_SIM_SCGC4_UART2 (0x00001000U) /*!< Bit mask for SIM_SCGC4_UART2. */ 02404 #define BS_SIM_SCGC4_UART2 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART2. */ 02405 02406 /*! @brief Read current value of the SIM_SCGC4_UART2 field. */ 02407 #define BR_SIM_SCGC4_UART2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2))) 02408 02409 /*! @brief Format value for bitfield SIM_SCGC4_UART2. */ 02410 #define BF_SIM_SCGC4_UART2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART2) & BM_SIM_SCGC4_UART2) 02411 02412 /*! @brief Set the UART2 field to a new value. */ 02413 #define BW_SIM_SCGC4_UART2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART2), v)) 02414 /*@}*/ 02415 02416 /*! 02417 * @name Register SIM_SCGC4, field UART3[13] (RW) 02418 * 02419 * This bit controls the clock gate to the UART3 module. 02420 * 02421 * Values: 02422 * - 0 - Clock disabled 02423 * - 1 - Clock enabled 02424 */ 02425 /*@{*/ 02426 #define BP_SIM_SCGC4_UART3 (13U) /*!< Bit position for SIM_SCGC4_UART3. */ 02427 #define BM_SIM_SCGC4_UART3 (0x00002000U) /*!< Bit mask for SIM_SCGC4_UART3. */ 02428 #define BS_SIM_SCGC4_UART3 (1U) /*!< Bit field size in bits for SIM_SCGC4_UART3. */ 02429 02430 /*! @brief Read current value of the SIM_SCGC4_UART3 field. */ 02431 #define BR_SIM_SCGC4_UART3(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3))) 02432 02433 /*! @brief Format value for bitfield SIM_SCGC4_UART3. */ 02434 #define BF_SIM_SCGC4_UART3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_UART3) & BM_SIM_SCGC4_UART3) 02435 02436 /*! @brief Set the UART3 field to a new value. */ 02437 #define BW_SIM_SCGC4_UART3(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_UART3), v)) 02438 /*@}*/ 02439 02440 /*! 02441 * @name Register SIM_SCGC4, field USBOTG[18] (RW) 02442 * 02443 * This bit controls the clock gate to the USB module. 02444 * 02445 * Values: 02446 * - 0 - Clock disabled 02447 * - 1 - Clock enabled 02448 */ 02449 /*@{*/ 02450 #define BP_SIM_SCGC4_USBOTG (18U) /*!< Bit position for SIM_SCGC4_USBOTG. */ 02451 #define BM_SIM_SCGC4_USBOTG (0x00040000U) /*!< Bit mask for SIM_SCGC4_USBOTG. */ 02452 #define BS_SIM_SCGC4_USBOTG (1U) /*!< Bit field size in bits for SIM_SCGC4_USBOTG. */ 02453 02454 /*! @brief Read current value of the SIM_SCGC4_USBOTG field. */ 02455 #define BR_SIM_SCGC4_USBOTG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG))) 02456 02457 /*! @brief Format value for bitfield SIM_SCGC4_USBOTG. */ 02458 #define BF_SIM_SCGC4_USBOTG(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_USBOTG) & BM_SIM_SCGC4_USBOTG) 02459 02460 /*! @brief Set the USBOTG field to a new value. */ 02461 #define BW_SIM_SCGC4_USBOTG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_USBOTG), v)) 02462 /*@}*/ 02463 02464 /*! 02465 * @name Register SIM_SCGC4, field CMP[19] (RW) 02466 * 02467 * This bit controls the clock gate to the comparator module. 02468 * 02469 * Values: 02470 * - 0 - Clock disabled 02471 * - 1 - Clock enabled 02472 */ 02473 /*@{*/ 02474 #define BP_SIM_SCGC4_CMP (19U) /*!< Bit position for SIM_SCGC4_CMP. */ 02475 #define BM_SIM_SCGC4_CMP (0x00080000U) /*!< Bit mask for SIM_SCGC4_CMP. */ 02476 #define BS_SIM_SCGC4_CMP (1U) /*!< Bit field size in bits for SIM_SCGC4_CMP. */ 02477 02478 /*! @brief Read current value of the SIM_SCGC4_CMP field. */ 02479 #define BR_SIM_SCGC4_CMP(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP))) 02480 02481 /*! @brief Format value for bitfield SIM_SCGC4_CMP. */ 02482 #define BF_SIM_SCGC4_CMP(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_CMP) & BM_SIM_SCGC4_CMP) 02483 02484 /*! @brief Set the CMP field to a new value. */ 02485 #define BW_SIM_SCGC4_CMP(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_CMP), v)) 02486 /*@}*/ 02487 02488 /*! 02489 * @name Register SIM_SCGC4, field VREF[20] (RW) 02490 * 02491 * This bit controls the clock gate to the VREF module. 02492 * 02493 * Values: 02494 * - 0 - Clock disabled 02495 * - 1 - Clock enabled 02496 */ 02497 /*@{*/ 02498 #define BP_SIM_SCGC4_VREF (20U) /*!< Bit position for SIM_SCGC4_VREF. */ 02499 #define BM_SIM_SCGC4_VREF (0x00100000U) /*!< Bit mask for SIM_SCGC4_VREF. */ 02500 #define BS_SIM_SCGC4_VREF (1U) /*!< Bit field size in bits for SIM_SCGC4_VREF. */ 02501 02502 /*! @brief Read current value of the SIM_SCGC4_VREF field. */ 02503 #define BR_SIM_SCGC4_VREF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF))) 02504 02505 /*! @brief Format value for bitfield SIM_SCGC4_VREF. */ 02506 #define BF_SIM_SCGC4_VREF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC4_VREF) & BM_SIM_SCGC4_VREF) 02507 02508 /*! @brief Set the VREF field to a new value. */ 02509 #define BW_SIM_SCGC4_VREF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC4_ADDR(x), BP_SIM_SCGC4_VREF), v)) 02510 /*@}*/ 02511 02512 /******************************************************************************* 02513 * HW_SIM_SCGC5 - System Clock Gating Control Register 5 02514 ******************************************************************************/ 02515 02516 /*! 02517 * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW) 02518 * 02519 * Reset value: 0x00040182U 02520 */ 02521 typedef union _hw_sim_scgc5 02522 { 02523 uint32_t U; 02524 struct _hw_sim_scgc5_bitfields 02525 { 02526 uint32_t LPTMR : 1; /*!< [0] Low Power Timer Access Control */ 02527 uint32_t RESERVED0 : 8; /*!< [8:1] */ 02528 uint32_t PORTAb : 1; /*!< [9] Port A Clock Gate Control */ 02529 uint32_t PORTBb : 1; /*!< [10] Port B Clock Gate Control */ 02530 uint32_t PORTCb : 1; /*!< [11] Port C Clock Gate Control */ 02531 uint32_t PORTDb : 1; /*!< [12] Port D Clock Gate Control */ 02532 uint32_t PORTEb : 1; /*!< [13] Port E Clock Gate Control */ 02533 uint32_t RESERVED1 : 18; /*!< [31:14] */ 02534 } B; 02535 } hw_sim_scgc5_t; 02536 02537 /*! 02538 * @name Constants and macros for entire SIM_SCGC5 register 02539 */ 02540 /*@{*/ 02541 #define HW_SIM_SCGC5_ADDR(x) ((x) + 0x1038U) 02542 02543 #define HW_SIM_SCGC5(x) (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR(x)) 02544 #define HW_SIM_SCGC5_RD(x) (ADDRESS_READ(hw_sim_scgc5_t, HW_SIM_SCGC5_ADDR(x))) 02545 #define HW_SIM_SCGC5_WR(x, v) (ADDRESS_WRITE(hw_sim_scgc5_t, HW_SIM_SCGC5_ADDR(x), v)) 02546 #define HW_SIM_SCGC5_SET(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) | (v))) 02547 #define HW_SIM_SCGC5_CLR(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) & ~(v))) 02548 #define HW_SIM_SCGC5_TOG(x, v) (HW_SIM_SCGC5_WR(x, HW_SIM_SCGC5_RD(x) ^ (v))) 02549 /*@}*/ 02550 02551 /* 02552 * Constants & macros for individual SIM_SCGC5 bitfields 02553 */ 02554 02555 /*! 02556 * @name Register SIM_SCGC5, field LPTMR[0] (RW) 02557 * 02558 * This bit controls software access to the Low Power Timer module. 02559 * 02560 * Values: 02561 * - 0 - Access disabled 02562 * - 1 - Access enabled 02563 */ 02564 /*@{*/ 02565 #define BP_SIM_SCGC5_LPTMR (0U) /*!< Bit position for SIM_SCGC5_LPTMR. */ 02566 #define BM_SIM_SCGC5_LPTMR (0x00000001U) /*!< Bit mask for SIM_SCGC5_LPTMR. */ 02567 #define BS_SIM_SCGC5_LPTMR (1U) /*!< Bit field size in bits for SIM_SCGC5_LPTMR. */ 02568 02569 /*! @brief Read current value of the SIM_SCGC5_LPTMR field. */ 02570 #define BR_SIM_SCGC5_LPTMR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR))) 02571 02572 /*! @brief Format value for bitfield SIM_SCGC5_LPTMR. */ 02573 #define BF_SIM_SCGC5_LPTMR(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_LPTMR) & BM_SIM_SCGC5_LPTMR) 02574 02575 /*! @brief Set the LPTMR field to a new value. */ 02576 #define BW_SIM_SCGC5_LPTMR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_LPTMR), v)) 02577 /*@}*/ 02578 02579 /*! 02580 * @name Register SIM_SCGC5, field PORTA[9] (RW) 02581 * 02582 * This bit controls the clock gate to the Port A module. 02583 * 02584 * Values: 02585 * - 0 - Clock disabled 02586 * - 1 - Clock enabled 02587 */ 02588 /*@{*/ 02589 #define BP_SIM_SCGC5_PORTA (9U) /*!< Bit position for SIM_SCGC5_PORTA. */ 02590 #define BM_SIM_SCGC5_PORTA (0x00000200U) /*!< Bit mask for SIM_SCGC5_PORTA. */ 02591 #define BS_SIM_SCGC5_PORTA (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTA. */ 02592 02593 /*! @brief Read current value of the SIM_SCGC5_PORTA field. */ 02594 #define BR_SIM_SCGC5_PORTA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA))) 02595 02596 /*! @brief Format value for bitfield SIM_SCGC5_PORTA. */ 02597 #define BF_SIM_SCGC5_PORTA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTA) & BM_SIM_SCGC5_PORTA) 02598 02599 /*! @brief Set the PORTA field to a new value. */ 02600 #define BW_SIM_SCGC5_PORTA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTA), v)) 02601 /*@}*/ 02602 02603 /*! 02604 * @name Register SIM_SCGC5, field PORTB[10] (RW) 02605 * 02606 * This bit controls the clock gate to the Port B module. 02607 * 02608 * Values: 02609 * - 0 - Clock disabled 02610 * - 1 - Clock enabled 02611 */ 02612 /*@{*/ 02613 #define BP_SIM_SCGC5_PORTB (10U) /*!< Bit position for SIM_SCGC5_PORTB. */ 02614 #define BM_SIM_SCGC5_PORTB (0x00000400U) /*!< Bit mask for SIM_SCGC5_PORTB. */ 02615 #define BS_SIM_SCGC5_PORTB (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTB. */ 02616 02617 /*! @brief Read current value of the SIM_SCGC5_PORTB field. */ 02618 #define BR_SIM_SCGC5_PORTB(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB))) 02619 02620 /*! @brief Format value for bitfield SIM_SCGC5_PORTB. */ 02621 #define BF_SIM_SCGC5_PORTB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTB) & BM_SIM_SCGC5_PORTB) 02622 02623 /*! @brief Set the PORTB field to a new value. */ 02624 #define BW_SIM_SCGC5_PORTB(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTB), v)) 02625 /*@}*/ 02626 02627 /*! 02628 * @name Register SIM_SCGC5, field PORTC[11] (RW) 02629 * 02630 * This bit controls the clock gate to the Port C module. 02631 * 02632 * Values: 02633 * - 0 - Clock disabled 02634 * - 1 - Clock enabled 02635 */ 02636 /*@{*/ 02637 #define BP_SIM_SCGC5_PORTC (11U) /*!< Bit position for SIM_SCGC5_PORTC. */ 02638 #define BM_SIM_SCGC5_PORTC (0x00000800U) /*!< Bit mask for SIM_SCGC5_PORTC. */ 02639 #define BS_SIM_SCGC5_PORTC (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTC. */ 02640 02641 /*! @brief Read current value of the SIM_SCGC5_PORTC field. */ 02642 #define BR_SIM_SCGC5_PORTC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC))) 02643 02644 /*! @brief Format value for bitfield SIM_SCGC5_PORTC. */ 02645 #define BF_SIM_SCGC5_PORTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTC) & BM_SIM_SCGC5_PORTC) 02646 02647 /*! @brief Set the PORTC field to a new value. */ 02648 #define BW_SIM_SCGC5_PORTC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTC), v)) 02649 /*@}*/ 02650 02651 /*! 02652 * @name Register SIM_SCGC5, field PORTD[12] (RW) 02653 * 02654 * This bit controls the clock gate to the Port D module. 02655 * 02656 * Values: 02657 * - 0 - Clock disabled 02658 * - 1 - Clock enabled 02659 */ 02660 /*@{*/ 02661 #define BP_SIM_SCGC5_PORTD (12U) /*!< Bit position for SIM_SCGC5_PORTD. */ 02662 #define BM_SIM_SCGC5_PORTD (0x00001000U) /*!< Bit mask for SIM_SCGC5_PORTD. */ 02663 #define BS_SIM_SCGC5_PORTD (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTD. */ 02664 02665 /*! @brief Read current value of the SIM_SCGC5_PORTD field. */ 02666 #define BR_SIM_SCGC5_PORTD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD))) 02667 02668 /*! @brief Format value for bitfield SIM_SCGC5_PORTD. */ 02669 #define BF_SIM_SCGC5_PORTD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTD) & BM_SIM_SCGC5_PORTD) 02670 02671 /*! @brief Set the PORTD field to a new value. */ 02672 #define BW_SIM_SCGC5_PORTD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTD), v)) 02673 /*@}*/ 02674 02675 /*! 02676 * @name Register SIM_SCGC5, field PORTE[13] (RW) 02677 * 02678 * This bit controls the clock gate to the Port E module. 02679 * 02680 * Values: 02681 * - 0 - Clock disabled 02682 * - 1 - Clock enabled 02683 */ 02684 /*@{*/ 02685 #define BP_SIM_SCGC5_PORTE (13U) /*!< Bit position for SIM_SCGC5_PORTE. */ 02686 #define BM_SIM_SCGC5_PORTE (0x00002000U) /*!< Bit mask for SIM_SCGC5_PORTE. */ 02687 #define BS_SIM_SCGC5_PORTE (1U) /*!< Bit field size in bits for SIM_SCGC5_PORTE. */ 02688 02689 /*! @brief Read current value of the SIM_SCGC5_PORTE field. */ 02690 #define BR_SIM_SCGC5_PORTE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE))) 02691 02692 /*! @brief Format value for bitfield SIM_SCGC5_PORTE. */ 02693 #define BF_SIM_SCGC5_PORTE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC5_PORTE) & BM_SIM_SCGC5_PORTE) 02694 02695 /*! @brief Set the PORTE field to a new value. */ 02696 #define BW_SIM_SCGC5_PORTE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC5_ADDR(x), BP_SIM_SCGC5_PORTE), v)) 02697 /*@}*/ 02698 02699 /******************************************************************************* 02700 * HW_SIM_SCGC6 - System Clock Gating Control Register 6 02701 ******************************************************************************/ 02702 02703 /*! 02704 * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW) 02705 * 02706 * Reset value: 0x40000001U 02707 * 02708 * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When 02709 * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3. 02710 * When accessing through AIPS0, define the clock gate control bits in SCGC6. 02711 */ 02712 typedef union _hw_sim_scgc6 02713 { 02714 uint32_t U; 02715 struct _hw_sim_scgc6_bitfields 02716 { 02717 uint32_t FTF : 1; /*!< [0] Flash Memory Clock Gate Control */ 02718 uint32_t DMAMUXb : 1; /*!< [1] DMA Mux Clock Gate Control */ 02719 uint32_t RESERVED0 : 2; /*!< [3:2] */ 02720 uint32_t FLEXCAN0 : 1; /*!< [4] FlexCAN0 Clock Gate Control */ 02721 uint32_t RESERVED1 : 4; /*!< [8:5] */ 02722 uint32_t RNGA : 1; /*!< [9] RNGA Clock Gate Control */ 02723 uint32_t RESERVED2 : 2; /*!< [11:10] */ 02724 uint32_t SPI0b : 1; /*!< [12] SPI0 Clock Gate Control */ 02725 uint32_t SPI1b : 1; /*!< [13] SPI1 Clock Gate Control */ 02726 uint32_t RESERVED3 : 1; /*!< [14] */ 02727 uint32_t I2S : 1; /*!< [15] I2S Clock Gate Control */ 02728 uint32_t RESERVED4 : 2; /*!< [17:16] */ 02729 uint32_t CRC : 1; /*!< [18] CRC Clock Gate Control */ 02730 uint32_t RESERVED5 : 2; /*!< [20:19] */ 02731 uint32_t USBDCDb : 1; /*!< [21] USB DCD Clock Gate Control */ 02732 uint32_t PDB : 1; /*!< [22] PDB Clock Gate Control */ 02733 uint32_t PITb : 1; /*!< [23] PIT Clock Gate Control */ 02734 uint32_t FTM0b : 1; /*!< [24] FTM0 Clock Gate Control */ 02735 uint32_t FTM1b : 1; /*!< [25] FTM1 Clock Gate Control */ 02736 uint32_t FTM2b : 1; /*!< [26] FTM2 Clock Gate Control */ 02737 uint32_t ADC0b : 1; /*!< [27] ADC0 Clock Gate Control */ 02738 uint32_t RESERVED6 : 1; /*!< [28] */ 02739 uint32_t RTCb : 1; /*!< [29] RTC Access Control */ 02740 uint32_t RESERVED7 : 1; /*!< [30] */ 02741 uint32_t DAC0b : 1; /*!< [31] DAC0 Clock Gate Control */ 02742 } B; 02743 } hw_sim_scgc6_t; 02744 02745 /*! 02746 * @name Constants and macros for entire SIM_SCGC6 register 02747 */ 02748 /*@{*/ 02749 #define HW_SIM_SCGC6_ADDR(x) ((x) + 0x103CU) 02750 02751 #define HW_SIM_SCGC6(x) (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR(x)) 02752 #define HW_SIM_SCGC6_RD(x) (ADDRESS_READ(hw_sim_scgc6_t, HW_SIM_SCGC6_ADDR(x))) 02753 #define HW_SIM_SCGC6_WR(x, v) (ADDRESS_WRITE(hw_sim_scgc6_t, HW_SIM_SCGC6_ADDR(x), v)) 02754 #define HW_SIM_SCGC6_SET(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) | (v))) 02755 #define HW_SIM_SCGC6_CLR(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) & ~(v))) 02756 #define HW_SIM_SCGC6_TOG(x, v) (HW_SIM_SCGC6_WR(x, HW_SIM_SCGC6_RD(x) ^ (v))) 02757 /*@}*/ 02758 02759 /* 02760 * Constants & macros for individual SIM_SCGC6 bitfields 02761 */ 02762 02763 /*! 02764 * @name Register SIM_SCGC6, field FTF[0] (RW) 02765 * 02766 * This bit controls the clock gate to the flash memory. Flash reads are still 02767 * supported while the flash memory is clock gated, but entry into low power modes 02768 * is blocked. 02769 * 02770 * Values: 02771 * - 0 - Clock disabled 02772 * - 1 - Clock enabled 02773 */ 02774 /*@{*/ 02775 #define BP_SIM_SCGC6_FTF (0U) /*!< Bit position for SIM_SCGC6_FTF. */ 02776 #define BM_SIM_SCGC6_FTF (0x00000001U) /*!< Bit mask for SIM_SCGC6_FTF. */ 02777 #define BS_SIM_SCGC6_FTF (1U) /*!< Bit field size in bits for SIM_SCGC6_FTF. */ 02778 02779 /*! @brief Read current value of the SIM_SCGC6_FTF field. */ 02780 #define BR_SIM_SCGC6_FTF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF))) 02781 02782 /*! @brief Format value for bitfield SIM_SCGC6_FTF. */ 02783 #define BF_SIM_SCGC6_FTF(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTF) & BM_SIM_SCGC6_FTF) 02784 02785 /*! @brief Set the FTF field to a new value. */ 02786 #define BW_SIM_SCGC6_FTF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTF), v)) 02787 /*@}*/ 02788 02789 /*! 02790 * @name Register SIM_SCGC6, field DMAMUX[1] (RW) 02791 * 02792 * This bit controls the clock gate to the DMA Mux module. 02793 * 02794 * Values: 02795 * - 0 - Clock disabled 02796 * - 1 - Clock enabled 02797 */ 02798 /*@{*/ 02799 #define BP_SIM_SCGC6_DMAMUX (1U) /*!< Bit position for SIM_SCGC6_DMAMUX. */ 02800 #define BM_SIM_SCGC6_DMAMUX (0x00000002U) /*!< Bit mask for SIM_SCGC6_DMAMUX. */ 02801 #define BS_SIM_SCGC6_DMAMUX (1U) /*!< Bit field size in bits for SIM_SCGC6_DMAMUX. */ 02802 02803 /*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */ 02804 #define BR_SIM_SCGC6_DMAMUX(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX))) 02805 02806 /*! @brief Format value for bitfield SIM_SCGC6_DMAMUX. */ 02807 #define BF_SIM_SCGC6_DMAMUX(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DMAMUX) & BM_SIM_SCGC6_DMAMUX) 02808 02809 /*! @brief Set the DMAMUX field to a new value. */ 02810 #define BW_SIM_SCGC6_DMAMUX(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DMAMUX), v)) 02811 /*@}*/ 02812 02813 /*! 02814 * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW) 02815 * 02816 * This bit controls the clock gate to the FlexCAN0 module. 02817 * 02818 * Values: 02819 * - 0 - Clock disabled 02820 * - 1 - Clock enabled 02821 */ 02822 /*@{*/ 02823 #define BP_SIM_SCGC6_FLEXCAN0 (4U) /*!< Bit position for SIM_SCGC6_FLEXCAN0. */ 02824 #define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) /*!< Bit mask for SIM_SCGC6_FLEXCAN0. */ 02825 #define BS_SIM_SCGC6_FLEXCAN0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FLEXCAN0. */ 02826 02827 /*! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field. */ 02828 #define BR_SIM_SCGC6_FLEXCAN0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0))) 02829 02830 /*! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0. */ 02831 #define BF_SIM_SCGC6_FLEXCAN0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FLEXCAN0) & BM_SIM_SCGC6_FLEXCAN0) 02832 02833 /*! @brief Set the FLEXCAN0 field to a new value. */ 02834 #define BW_SIM_SCGC6_FLEXCAN0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FLEXCAN0), v)) 02835 /*@}*/ 02836 02837 /*! 02838 * @name Register SIM_SCGC6, field RNGA[9] (RW) 02839 * 02840 * This bit controls the clock gate to the RNGA module. 02841 */ 02842 /*@{*/ 02843 #define BP_SIM_SCGC6_RNGA (9U) /*!< Bit position for SIM_SCGC6_RNGA. */ 02844 #define BM_SIM_SCGC6_RNGA (0x00000200U) /*!< Bit mask for SIM_SCGC6_RNGA. */ 02845 #define BS_SIM_SCGC6_RNGA (1U) /*!< Bit field size in bits for SIM_SCGC6_RNGA. */ 02846 02847 /*! @brief Read current value of the SIM_SCGC6_RNGA field. */ 02848 #define BR_SIM_SCGC6_RNGA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA))) 02849 02850 /*! @brief Format value for bitfield SIM_SCGC6_RNGA. */ 02851 #define BF_SIM_SCGC6_RNGA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RNGA) & BM_SIM_SCGC6_RNGA) 02852 02853 /*! @brief Set the RNGA field to a new value. */ 02854 #define BW_SIM_SCGC6_RNGA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RNGA), v)) 02855 /*@}*/ 02856 02857 /*! 02858 * @name Register SIM_SCGC6, field SPI0[12] (RW) 02859 * 02860 * This bit controls the clock gate to the SPI0 module. 02861 * 02862 * Values: 02863 * - 0 - Clock disabled 02864 * - 1 - Clock enabled 02865 */ 02866 /*@{*/ 02867 #define BP_SIM_SCGC6_SPI0 (12U) /*!< Bit position for SIM_SCGC6_SPI0. */ 02868 #define BM_SIM_SCGC6_SPI0 (0x00001000U) /*!< Bit mask for SIM_SCGC6_SPI0. */ 02869 #define BS_SIM_SCGC6_SPI0 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI0. */ 02870 02871 /*! @brief Read current value of the SIM_SCGC6_SPI0 field. */ 02872 #define BR_SIM_SCGC6_SPI0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0))) 02873 02874 /*! @brief Format value for bitfield SIM_SCGC6_SPI0. */ 02875 #define BF_SIM_SCGC6_SPI0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI0) & BM_SIM_SCGC6_SPI0) 02876 02877 /*! @brief Set the SPI0 field to a new value. */ 02878 #define BW_SIM_SCGC6_SPI0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI0), v)) 02879 /*@}*/ 02880 02881 /*! 02882 * @name Register SIM_SCGC6, field SPI1[13] (RW) 02883 * 02884 * This bit controls the clock gate to the SPI1 module. 02885 * 02886 * Values: 02887 * - 0 - Clock disabled 02888 * - 1 - Clock enabled 02889 */ 02890 /*@{*/ 02891 #define BP_SIM_SCGC6_SPI1 (13U) /*!< Bit position for SIM_SCGC6_SPI1. */ 02892 #define BM_SIM_SCGC6_SPI1 (0x00002000U) /*!< Bit mask for SIM_SCGC6_SPI1. */ 02893 #define BS_SIM_SCGC6_SPI1 (1U) /*!< Bit field size in bits for SIM_SCGC6_SPI1. */ 02894 02895 /*! @brief Read current value of the SIM_SCGC6_SPI1 field. */ 02896 #define BR_SIM_SCGC6_SPI1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1))) 02897 02898 /*! @brief Format value for bitfield SIM_SCGC6_SPI1. */ 02899 #define BF_SIM_SCGC6_SPI1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_SPI1) & BM_SIM_SCGC6_SPI1) 02900 02901 /*! @brief Set the SPI1 field to a new value. */ 02902 #define BW_SIM_SCGC6_SPI1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_SPI1), v)) 02903 /*@}*/ 02904 02905 /*! 02906 * @name Register SIM_SCGC6, field I2S[15] (RW) 02907 * 02908 * This bit controls the clock gate to the I 2 S module. 02909 * 02910 * Values: 02911 * - 0 - Clock disabled 02912 * - 1 - Clock enabled 02913 */ 02914 /*@{*/ 02915 #define BP_SIM_SCGC6_I2S (15U) /*!< Bit position for SIM_SCGC6_I2S. */ 02916 #define BM_SIM_SCGC6_I2S (0x00008000U) /*!< Bit mask for SIM_SCGC6_I2S. */ 02917 #define BS_SIM_SCGC6_I2S (1U) /*!< Bit field size in bits for SIM_SCGC6_I2S. */ 02918 02919 /*! @brief Read current value of the SIM_SCGC6_I2S field. */ 02920 #define BR_SIM_SCGC6_I2S(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S))) 02921 02922 /*! @brief Format value for bitfield SIM_SCGC6_I2S. */ 02923 #define BF_SIM_SCGC6_I2S(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_I2S) & BM_SIM_SCGC6_I2S) 02924 02925 /*! @brief Set the I2S field to a new value. */ 02926 #define BW_SIM_SCGC6_I2S(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_I2S), v)) 02927 /*@}*/ 02928 02929 /*! 02930 * @name Register SIM_SCGC6, field CRC[18] (RW) 02931 * 02932 * This bit controls the clock gate to the CRC module. 02933 * 02934 * Values: 02935 * - 0 - Clock disabled 02936 * - 1 - Clock enabled 02937 */ 02938 /*@{*/ 02939 #define BP_SIM_SCGC6_CRC (18U) /*!< Bit position for SIM_SCGC6_CRC. */ 02940 #define BM_SIM_SCGC6_CRC (0x00040000U) /*!< Bit mask for SIM_SCGC6_CRC. */ 02941 #define BS_SIM_SCGC6_CRC (1U) /*!< Bit field size in bits for SIM_SCGC6_CRC. */ 02942 02943 /*! @brief Read current value of the SIM_SCGC6_CRC field. */ 02944 #define BR_SIM_SCGC6_CRC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC))) 02945 02946 /*! @brief Format value for bitfield SIM_SCGC6_CRC. */ 02947 #define BF_SIM_SCGC6_CRC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_CRC) & BM_SIM_SCGC6_CRC) 02948 02949 /*! @brief Set the CRC field to a new value. */ 02950 #define BW_SIM_SCGC6_CRC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_CRC), v)) 02951 /*@}*/ 02952 02953 /*! 02954 * @name Register SIM_SCGC6, field USBDCD[21] (RW) 02955 * 02956 * This bit controls the clock gate to the USB DCD module. 02957 * 02958 * Values: 02959 * - 0 - Clock disabled 02960 * - 1 - Clock enabled 02961 */ 02962 /*@{*/ 02963 #define BP_SIM_SCGC6_USBDCD (21U) /*!< Bit position for SIM_SCGC6_USBDCD. */ 02964 #define BM_SIM_SCGC6_USBDCD (0x00200000U) /*!< Bit mask for SIM_SCGC6_USBDCD. */ 02965 #define BS_SIM_SCGC6_USBDCD (1U) /*!< Bit field size in bits for SIM_SCGC6_USBDCD. */ 02966 02967 /*! @brief Read current value of the SIM_SCGC6_USBDCD field. */ 02968 #define BR_SIM_SCGC6_USBDCD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD))) 02969 02970 /*! @brief Format value for bitfield SIM_SCGC6_USBDCD. */ 02971 #define BF_SIM_SCGC6_USBDCD(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_USBDCD) & BM_SIM_SCGC6_USBDCD) 02972 02973 /*! @brief Set the USBDCD field to a new value. */ 02974 #define BW_SIM_SCGC6_USBDCD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_USBDCD), v)) 02975 /*@}*/ 02976 02977 /*! 02978 * @name Register SIM_SCGC6, field PDB[22] (RW) 02979 * 02980 * This bit controls the clock gate to the PDB module. 02981 * 02982 * Values: 02983 * - 0 - Clock disabled 02984 * - 1 - Clock enabled 02985 */ 02986 /*@{*/ 02987 #define BP_SIM_SCGC6_PDB (22U) /*!< Bit position for SIM_SCGC6_PDB. */ 02988 #define BM_SIM_SCGC6_PDB (0x00400000U) /*!< Bit mask for SIM_SCGC6_PDB. */ 02989 #define BS_SIM_SCGC6_PDB (1U) /*!< Bit field size in bits for SIM_SCGC6_PDB. */ 02990 02991 /*! @brief Read current value of the SIM_SCGC6_PDB field. */ 02992 #define BR_SIM_SCGC6_PDB(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB))) 02993 02994 /*! @brief Format value for bitfield SIM_SCGC6_PDB. */ 02995 #define BF_SIM_SCGC6_PDB(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PDB) & BM_SIM_SCGC6_PDB) 02996 02997 /*! @brief Set the PDB field to a new value. */ 02998 #define BW_SIM_SCGC6_PDB(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PDB), v)) 02999 /*@}*/ 03000 03001 /*! 03002 * @name Register SIM_SCGC6, field PIT[23] (RW) 03003 * 03004 * This bit controls the clock gate to the PIT module. 03005 * 03006 * Values: 03007 * - 0 - Clock disabled 03008 * - 1 - Clock enabled 03009 */ 03010 /*@{*/ 03011 #define BP_SIM_SCGC6_PIT (23U) /*!< Bit position for SIM_SCGC6_PIT. */ 03012 #define BM_SIM_SCGC6_PIT (0x00800000U) /*!< Bit mask for SIM_SCGC6_PIT. */ 03013 #define BS_SIM_SCGC6_PIT (1U) /*!< Bit field size in bits for SIM_SCGC6_PIT. */ 03014 03015 /*! @brief Read current value of the SIM_SCGC6_PIT field. */ 03016 #define BR_SIM_SCGC6_PIT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT))) 03017 03018 /*! @brief Format value for bitfield SIM_SCGC6_PIT. */ 03019 #define BF_SIM_SCGC6_PIT(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_PIT) & BM_SIM_SCGC6_PIT) 03020 03021 /*! @brief Set the PIT field to a new value. */ 03022 #define BW_SIM_SCGC6_PIT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_PIT), v)) 03023 /*@}*/ 03024 03025 /*! 03026 * @name Register SIM_SCGC6, field FTM0[24] (RW) 03027 * 03028 * This bit controls the clock gate to the FTM0 module. 03029 * 03030 * Values: 03031 * - 0 - Clock disabled 03032 * - 1 - Clock enabled 03033 */ 03034 /*@{*/ 03035 #define BP_SIM_SCGC6_FTM0 (24U) /*!< Bit position for SIM_SCGC6_FTM0. */ 03036 #define BM_SIM_SCGC6_FTM0 (0x01000000U) /*!< Bit mask for SIM_SCGC6_FTM0. */ 03037 #define BS_SIM_SCGC6_FTM0 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM0. */ 03038 03039 /*! @brief Read current value of the SIM_SCGC6_FTM0 field. */ 03040 #define BR_SIM_SCGC6_FTM0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0))) 03041 03042 /*! @brief Format value for bitfield SIM_SCGC6_FTM0. */ 03043 #define BF_SIM_SCGC6_FTM0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM0) & BM_SIM_SCGC6_FTM0) 03044 03045 /*! @brief Set the FTM0 field to a new value. */ 03046 #define BW_SIM_SCGC6_FTM0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM0), v)) 03047 /*@}*/ 03048 03049 /*! 03050 * @name Register SIM_SCGC6, field FTM1[25] (RW) 03051 * 03052 * This bit controls the clock gate to the FTM1 module. 03053 * 03054 * Values: 03055 * - 0 - Clock disabled 03056 * - 1 - Clock enabled 03057 */ 03058 /*@{*/ 03059 #define BP_SIM_SCGC6_FTM1 (25U) /*!< Bit position for SIM_SCGC6_FTM1. */ 03060 #define BM_SIM_SCGC6_FTM1 (0x02000000U) /*!< Bit mask for SIM_SCGC6_FTM1. */ 03061 #define BS_SIM_SCGC6_FTM1 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM1. */ 03062 03063 /*! @brief Read current value of the SIM_SCGC6_FTM1 field. */ 03064 #define BR_SIM_SCGC6_FTM1(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1))) 03065 03066 /*! @brief Format value for bitfield SIM_SCGC6_FTM1. */ 03067 #define BF_SIM_SCGC6_FTM1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM1) & BM_SIM_SCGC6_FTM1) 03068 03069 /*! @brief Set the FTM1 field to a new value. */ 03070 #define BW_SIM_SCGC6_FTM1(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM1), v)) 03071 /*@}*/ 03072 03073 /*! 03074 * @name Register SIM_SCGC6, field FTM2[26] (RW) 03075 * 03076 * This bit controls the clock gate to the FTM2 module. 03077 * 03078 * Values: 03079 * - 0 - Clock disabled 03080 * - 1 - Clock enabled 03081 */ 03082 /*@{*/ 03083 #define BP_SIM_SCGC6_FTM2 (26U) /*!< Bit position for SIM_SCGC6_FTM2. */ 03084 #define BM_SIM_SCGC6_FTM2 (0x04000000U) /*!< Bit mask for SIM_SCGC6_FTM2. */ 03085 #define BS_SIM_SCGC6_FTM2 (1U) /*!< Bit field size in bits for SIM_SCGC6_FTM2. */ 03086 03087 /*! @brief Read current value of the SIM_SCGC6_FTM2 field. */ 03088 #define BR_SIM_SCGC6_FTM2(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2))) 03089 03090 /*! @brief Format value for bitfield SIM_SCGC6_FTM2. */ 03091 #define BF_SIM_SCGC6_FTM2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_FTM2) & BM_SIM_SCGC6_FTM2) 03092 03093 /*! @brief Set the FTM2 field to a new value. */ 03094 #define BW_SIM_SCGC6_FTM2(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_FTM2), v)) 03095 /*@}*/ 03096 03097 /*! 03098 * @name Register SIM_SCGC6, field ADC0[27] (RW) 03099 * 03100 * This bit controls the clock gate to the ADC0 module. 03101 * 03102 * Values: 03103 * - 0 - Clock disabled 03104 * - 1 - Clock enabled 03105 */ 03106 /*@{*/ 03107 #define BP_SIM_SCGC6_ADC0 (27U) /*!< Bit position for SIM_SCGC6_ADC0. */ 03108 #define BM_SIM_SCGC6_ADC0 (0x08000000U) /*!< Bit mask for SIM_SCGC6_ADC0. */ 03109 #define BS_SIM_SCGC6_ADC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_ADC0. */ 03110 03111 /*! @brief Read current value of the SIM_SCGC6_ADC0 field. */ 03112 #define BR_SIM_SCGC6_ADC0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0))) 03113 03114 /*! @brief Format value for bitfield SIM_SCGC6_ADC0. */ 03115 #define BF_SIM_SCGC6_ADC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_ADC0) & BM_SIM_SCGC6_ADC0) 03116 03117 /*! @brief Set the ADC0 field to a new value. */ 03118 #define BW_SIM_SCGC6_ADC0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_ADC0), v)) 03119 /*@}*/ 03120 03121 /*! 03122 * @name Register SIM_SCGC6, field RTC[29] (RW) 03123 * 03124 * This bit controls software access and interrupts to the RTC module. 03125 * 03126 * Values: 03127 * - 0 - Access and interrupts disabled 03128 * - 1 - Access and interrupts enabled 03129 */ 03130 /*@{*/ 03131 #define BP_SIM_SCGC6_RTC (29U) /*!< Bit position for SIM_SCGC6_RTC. */ 03132 #define BM_SIM_SCGC6_RTC (0x20000000U) /*!< Bit mask for SIM_SCGC6_RTC. */ 03133 #define BS_SIM_SCGC6_RTC (1U) /*!< Bit field size in bits for SIM_SCGC6_RTC. */ 03134 03135 /*! @brief Read current value of the SIM_SCGC6_RTC field. */ 03136 #define BR_SIM_SCGC6_RTC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC))) 03137 03138 /*! @brief Format value for bitfield SIM_SCGC6_RTC. */ 03139 #define BF_SIM_SCGC6_RTC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_RTC) & BM_SIM_SCGC6_RTC) 03140 03141 /*! @brief Set the RTC field to a new value. */ 03142 #define BW_SIM_SCGC6_RTC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_RTC), v)) 03143 /*@}*/ 03144 03145 /*! 03146 * @name Register SIM_SCGC6, field DAC0[31] (RW) 03147 * 03148 * This bit controls the clock gate to the DAC0 module. 03149 * 03150 * Values: 03151 * - 0 - Clock disabled 03152 * - 1 - Clock enabled 03153 */ 03154 /*@{*/ 03155 #define BP_SIM_SCGC6_DAC0 (31U) /*!< Bit position for SIM_SCGC6_DAC0. */ 03156 #define BM_SIM_SCGC6_DAC0 (0x80000000U) /*!< Bit mask for SIM_SCGC6_DAC0. */ 03157 #define BS_SIM_SCGC6_DAC0 (1U) /*!< Bit field size in bits for SIM_SCGC6_DAC0. */ 03158 03159 /*! @brief Read current value of the SIM_SCGC6_DAC0 field. */ 03160 #define BR_SIM_SCGC6_DAC0(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0))) 03161 03162 /*! @brief Format value for bitfield SIM_SCGC6_DAC0. */ 03163 #define BF_SIM_SCGC6_DAC0(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC6_DAC0) & BM_SIM_SCGC6_DAC0) 03164 03165 /*! @brief Set the DAC0 field to a new value. */ 03166 #define BW_SIM_SCGC6_DAC0(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC6_ADDR(x), BP_SIM_SCGC6_DAC0), v)) 03167 /*@}*/ 03168 03169 /******************************************************************************* 03170 * HW_SIM_SCGC7 - System Clock Gating Control Register 7 03171 ******************************************************************************/ 03172 03173 /*! 03174 * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW) 03175 * 03176 * Reset value: 0x00000006U 03177 */ 03178 typedef union _hw_sim_scgc7 03179 { 03180 uint32_t U; 03181 struct _hw_sim_scgc7_bitfields 03182 { 03183 uint32_t FLEXBUS : 1; /*!< [0] FlexBus Clock Gate Control */ 03184 uint32_t DMA : 1; /*!< [1] DMA Clock Gate Control */ 03185 uint32_t MPUb : 1; /*!< [2] MPU Clock Gate Control */ 03186 uint32_t RESERVED0 : 29; /*!< [31:3] */ 03187 } B; 03188 } hw_sim_scgc7_t; 03189 03190 /*! 03191 * @name Constants and macros for entire SIM_SCGC7 register 03192 */ 03193 /*@{*/ 03194 #define HW_SIM_SCGC7_ADDR(x) ((x) + 0x1040U) 03195 03196 #define HW_SIM_SCGC7(x) (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR(x)) 03197 #define HW_SIM_SCGC7_RD(x) (ADDRESS_READ(hw_sim_scgc7_t, HW_SIM_SCGC7_ADDR(x))) 03198 #define HW_SIM_SCGC7_WR(x, v) (ADDRESS_WRITE(hw_sim_scgc7_t, HW_SIM_SCGC7_ADDR(x), v)) 03199 #define HW_SIM_SCGC7_SET(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) | (v))) 03200 #define HW_SIM_SCGC7_CLR(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) & ~(v))) 03201 #define HW_SIM_SCGC7_TOG(x, v) (HW_SIM_SCGC7_WR(x, HW_SIM_SCGC7_RD(x) ^ (v))) 03202 /*@}*/ 03203 03204 /* 03205 * Constants & macros for individual SIM_SCGC7 bitfields 03206 */ 03207 03208 /*! 03209 * @name Register SIM_SCGC7, field FLEXBUS[0] (RW) 03210 * 03211 * This bit controls the clock gate to the FlexBus module. 03212 * 03213 * Values: 03214 * - 0 - Clock disabled 03215 * - 1 - Clock enabled 03216 */ 03217 /*@{*/ 03218 #define BP_SIM_SCGC7_FLEXBUS (0U) /*!< Bit position for SIM_SCGC7_FLEXBUS. */ 03219 #define BM_SIM_SCGC7_FLEXBUS (0x00000001U) /*!< Bit mask for SIM_SCGC7_FLEXBUS. */ 03220 #define BS_SIM_SCGC7_FLEXBUS (1U) /*!< Bit field size in bits for SIM_SCGC7_FLEXBUS. */ 03221 03222 /*! @brief Read current value of the SIM_SCGC7_FLEXBUS field. */ 03223 #define BR_SIM_SCGC7_FLEXBUS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS))) 03224 03225 /*! @brief Format value for bitfield SIM_SCGC7_FLEXBUS. */ 03226 #define BF_SIM_SCGC7_FLEXBUS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_FLEXBUS) & BM_SIM_SCGC7_FLEXBUS) 03227 03228 /*! @brief Set the FLEXBUS field to a new value. */ 03229 #define BW_SIM_SCGC7_FLEXBUS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_FLEXBUS), v)) 03230 /*@}*/ 03231 03232 /*! 03233 * @name Register SIM_SCGC7, field DMA[1] (RW) 03234 * 03235 * This bit controls the clock gate to the DMA module. 03236 * 03237 * Values: 03238 * - 0 - Clock disabled 03239 * - 1 - Clock enabled 03240 */ 03241 /*@{*/ 03242 #define BP_SIM_SCGC7_DMA (1U) /*!< Bit position for SIM_SCGC7_DMA. */ 03243 #define BM_SIM_SCGC7_DMA (0x00000002U) /*!< Bit mask for SIM_SCGC7_DMA. */ 03244 #define BS_SIM_SCGC7_DMA (1U) /*!< Bit field size in bits for SIM_SCGC7_DMA. */ 03245 03246 /*! @brief Read current value of the SIM_SCGC7_DMA field. */ 03247 #define BR_SIM_SCGC7_DMA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA))) 03248 03249 /*! @brief Format value for bitfield SIM_SCGC7_DMA. */ 03250 #define BF_SIM_SCGC7_DMA(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_DMA) & BM_SIM_SCGC7_DMA) 03251 03252 /*! @brief Set the DMA field to a new value. */ 03253 #define BW_SIM_SCGC7_DMA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_DMA), v)) 03254 /*@}*/ 03255 03256 /*! 03257 * @name Register SIM_SCGC7, field MPU[2] (RW) 03258 * 03259 * This bit controls the clock gate to the MPU module. 03260 * 03261 * Values: 03262 * - 0 - Clock disabled 03263 * - 1 - Clock enabled 03264 */ 03265 /*@{*/ 03266 #define BP_SIM_SCGC7_MPU (2U) /*!< Bit position for SIM_SCGC7_MPU. */ 03267 #define BM_SIM_SCGC7_MPU (0x00000004U) /*!< Bit mask for SIM_SCGC7_MPU. */ 03268 #define BS_SIM_SCGC7_MPU (1U) /*!< Bit field size in bits for SIM_SCGC7_MPU. */ 03269 03270 /*! @brief Read current value of the SIM_SCGC7_MPU field. */ 03271 #define BR_SIM_SCGC7_MPU(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU))) 03272 03273 /*! @brief Format value for bitfield SIM_SCGC7_MPU. */ 03274 #define BF_SIM_SCGC7_MPU(v) ((uint32_t)((uint32_t)(v) << BP_SIM_SCGC7_MPU) & BM_SIM_SCGC7_MPU) 03275 03276 /*! @brief Set the MPU field to a new value. */ 03277 #define BW_SIM_SCGC7_MPU(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_SCGC7_ADDR(x), BP_SIM_SCGC7_MPU), v)) 03278 /*@}*/ 03279 03280 /******************************************************************************* 03281 * HW_SIM_CLKDIV1 - System Clock Divider Register 1 03282 ******************************************************************************/ 03283 03284 /*! 03285 * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW) 03286 * 03287 * Reset value: 0x00010000U 03288 * 03289 * When updating CLKDIV1, update all fields using the one write command. 03290 * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the 03291 * write to be ignored. The maximum divide ratio that can be programmed between 03292 * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals 03293 * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide 03294 * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR 03295 * mode. 03296 */ 03297 typedef union _hw_sim_clkdiv1 03298 { 03299 uint32_t U; 03300 struct _hw_sim_clkdiv1_bitfields 03301 { 03302 uint32_t RESERVED0 : 16; /*!< [15:0] */ 03303 uint32_t OUTDIV4 : 4; /*!< [19:16] Clock 4 output divider value */ 03304 uint32_t OUTDIV3 : 4; /*!< [23:20] Clock 3 output divider value */ 03305 uint32_t OUTDIV2 : 4; /*!< [27:24] Clock 2 output divider value */ 03306 uint32_t OUTDIV1 : 4; /*!< [31:28] Clock 1 output divider value */ 03307 } B; 03308 } hw_sim_clkdiv1_t; 03309 03310 /*! 03311 * @name Constants and macros for entire SIM_CLKDIV1 register 03312 */ 03313 /*@{*/ 03314 #define HW_SIM_CLKDIV1_ADDR(x) ((x) + 0x1044U) 03315 03316 #define HW_SIM_CLKDIV1(x) (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR(x)) 03317 #define HW_SIM_CLKDIV1_RD(x) (ADDRESS_READ(hw_sim_clkdiv1_t, HW_SIM_CLKDIV1_ADDR(x))) 03318 #define HW_SIM_CLKDIV1_WR(x, v) (ADDRESS_WRITE(hw_sim_clkdiv1_t, HW_SIM_CLKDIV1_ADDR(x), v)) 03319 #define HW_SIM_CLKDIV1_SET(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) | (v))) 03320 #define HW_SIM_CLKDIV1_CLR(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) & ~(v))) 03321 #define HW_SIM_CLKDIV1_TOG(x, v) (HW_SIM_CLKDIV1_WR(x, HW_SIM_CLKDIV1_RD(x) ^ (v))) 03322 /*@}*/ 03323 03324 /* 03325 * Constants & macros for individual SIM_CLKDIV1 bitfields 03326 */ 03327 03328 /*! 03329 * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW) 03330 * 03331 * This field sets the divide value for the flash clock from MCGOUTCLK. At the 03332 * end of reset, it is loaded with either 0001 or 1111 depending on 03333 * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock 03334 * frequency. 03335 * 03336 * Values: 03337 * - 0000 - Divide-by-1. 03338 * - 0001 - Divide-by-2. 03339 * - 0010 - Divide-by-3. 03340 * - 0011 - Divide-by-4. 03341 * - 0100 - Divide-by-5. 03342 * - 0101 - Divide-by-6. 03343 * - 0110 - Divide-by-7. 03344 * - 0111 - Divide-by-8. 03345 * - 1000 - Divide-by-9. 03346 * - 1001 - Divide-by-10. 03347 * - 1010 - Divide-by-11. 03348 * - 1011 - Divide-by-12. 03349 * - 1100 - Divide-by-13. 03350 * - 1101 - Divide-by-14. 03351 * - 1110 - Divide-by-15. 03352 * - 1111 - Divide-by-16. 03353 */ 03354 /*@{*/ 03355 #define BP_SIM_CLKDIV1_OUTDIV4 (16U) /*!< Bit position for SIM_CLKDIV1_OUTDIV4. */ 03356 #define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV4. */ 03357 #define BS_SIM_CLKDIV1_OUTDIV4 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4. */ 03358 03359 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */ 03360 #define BR_SIM_CLKDIV1_OUTDIV4(x) (UNION_READ(hw_sim_clkdiv1_t, HW_SIM_CLKDIV1_ADDR(x), U, B.OUTDIV4)) 03361 03362 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4. */ 03363 #define BF_SIM_CLKDIV1_OUTDIV4(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV4) & BM_SIM_CLKDIV1_OUTDIV4) 03364 03365 /*! @brief Set the OUTDIV4 field to a new value. */ 03366 #define BW_SIM_CLKDIV1_OUTDIV4(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v))) 03367 /*@}*/ 03368 03369 /*! 03370 * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW) 03371 * 03372 * This field sets the divide value for the FlexBus clock (external pin FB_CLK) 03373 * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111 03374 * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer 03375 * divide of the system clock frequency. 03376 * 03377 * Values: 03378 * - 0000 - Divide-by-1. 03379 * - 0001 - Divide-by-2. 03380 * - 0010 - Divide-by-3. 03381 * - 0011 - Divide-by-4. 03382 * - 0100 - Divide-by-5. 03383 * - 0101 - Divide-by-6. 03384 * - 0110 - Divide-by-7. 03385 * - 0111 - Divide-by-8. 03386 * - 1000 - Divide-by-9. 03387 * - 1001 - Divide-by-10. 03388 * - 1010 - Divide-by-11. 03389 * - 1011 - Divide-by-12. 03390 * - 1100 - Divide-by-13. 03391 * - 1101 - Divide-by-14. 03392 * - 1110 - Divide-by-15. 03393 * - 1111 - Divide-by-16. 03394 */ 03395 /*@{*/ 03396 #define BP_SIM_CLKDIV1_OUTDIV3 (20U) /*!< Bit position for SIM_CLKDIV1_OUTDIV3. */ 03397 #define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV3. */ 03398 #define BS_SIM_CLKDIV1_OUTDIV3 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3. */ 03399 03400 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field. */ 03401 #define BR_SIM_CLKDIV1_OUTDIV3(x) (UNION_READ(hw_sim_clkdiv1_t, HW_SIM_CLKDIV1_ADDR(x), U, B.OUTDIV3)) 03402 03403 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3. */ 03404 #define BF_SIM_CLKDIV1_OUTDIV3(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV3) & BM_SIM_CLKDIV1_OUTDIV3) 03405 03406 /*! @brief Set the OUTDIV3 field to a new value. */ 03407 #define BW_SIM_CLKDIV1_OUTDIV3(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v))) 03408 /*@}*/ 03409 03410 /*! 03411 * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW) 03412 * 03413 * This field sets the divide value for the bus clock from MCGOUTCLK. At the end 03414 * of reset, it is loaded with either 0000 or 0111 depending on 03415 * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock 03416 * frequency. 03417 * 03418 * Values: 03419 * - 0000 - Divide-by-1. 03420 * - 0001 - Divide-by-2. 03421 * - 0010 - Divide-by-3. 03422 * - 0011 - Divide-by-4. 03423 * - 0100 - Divide-by-5. 03424 * - 0101 - Divide-by-6. 03425 * - 0110 - Divide-by-7. 03426 * - 0111 - Divide-by-8. 03427 * - 1000 - Divide-by-9. 03428 * - 1001 - Divide-by-10. 03429 * - 1010 - Divide-by-11. 03430 * - 1011 - Divide-by-12. 03431 * - 1100 - Divide-by-13. 03432 * - 1101 - Divide-by-14. 03433 * - 1110 - Divide-by-15. 03434 * - 1111 - Divide-by-16. 03435 */ 03436 /*@{*/ 03437 #define BP_SIM_CLKDIV1_OUTDIV2 (24U) /*!< Bit position for SIM_CLKDIV1_OUTDIV2. */ 03438 #define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV2. */ 03439 #define BS_SIM_CLKDIV1_OUTDIV2 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2. */ 03440 03441 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field. */ 03442 #define BR_SIM_CLKDIV1_OUTDIV2(x) (UNION_READ(hw_sim_clkdiv1_t, HW_SIM_CLKDIV1_ADDR(x), U, B.OUTDIV2)) 03443 03444 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2. */ 03445 #define BF_SIM_CLKDIV1_OUTDIV2(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV2) & BM_SIM_CLKDIV1_OUTDIV2) 03446 03447 /*! @brief Set the OUTDIV2 field to a new value. */ 03448 #define BW_SIM_CLKDIV1_OUTDIV2(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v))) 03449 /*@}*/ 03450 03451 /*! 03452 * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW) 03453 * 03454 * This field sets the divide value for the core/system clock from MCGOUTCLK. At 03455 * the end of reset, it is loaded with either 0000 or 0111 depending on 03456 * FTF_FOPT[LPBOOT]. 03457 * 03458 * Values: 03459 * - 0000 - Divide-by-1. 03460 * - 0001 - Divide-by-2. 03461 * - 0010 - Divide-by-3. 03462 * - 0011 - Divide-by-4. 03463 * - 0100 - Divide-by-5. 03464 * - 0101 - Divide-by-6. 03465 * - 0110 - Divide-by-7. 03466 * - 0111 - Divide-by-8. 03467 * - 1000 - Divide-by-9. 03468 * - 1001 - Divide-by-10. 03469 * - 1010 - Divide-by-11. 03470 * - 1011 - Divide-by-12. 03471 * - 1100 - Divide-by-13. 03472 * - 1101 - Divide-by-14. 03473 * - 1110 - Divide-by-15. 03474 * - 1111 - Divide-by-16. 03475 */ 03476 /*@{*/ 03477 #define BP_SIM_CLKDIV1_OUTDIV1 (28U) /*!< Bit position for SIM_CLKDIV1_OUTDIV1. */ 03478 #define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) /*!< Bit mask for SIM_CLKDIV1_OUTDIV1. */ 03479 #define BS_SIM_CLKDIV1_OUTDIV1 (4U) /*!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1. */ 03480 03481 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */ 03482 #define BR_SIM_CLKDIV1_OUTDIV1(x) (UNION_READ(hw_sim_clkdiv1_t, HW_SIM_CLKDIV1_ADDR(x), U, B.OUTDIV1)) 03483 03484 /*! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1. */ 03485 #define BF_SIM_CLKDIV1_OUTDIV1(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV1_OUTDIV1) & BM_SIM_CLKDIV1_OUTDIV1) 03486 03487 /*! @brief Set the OUTDIV1 field to a new value. */ 03488 #define BW_SIM_CLKDIV1_OUTDIV1(x, v) (HW_SIM_CLKDIV1_WR(x, (HW_SIM_CLKDIV1_RD(x) & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v))) 03489 /*@}*/ 03490 03491 /******************************************************************************* 03492 * HW_SIM_CLKDIV2 - System Clock Divider Register 2 03493 ******************************************************************************/ 03494 03495 /*! 03496 * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW) 03497 * 03498 * Reset value: 0x00000000U 03499 */ 03500 typedef union _hw_sim_clkdiv2 03501 { 03502 uint32_t U; 03503 struct _hw_sim_clkdiv2_bitfields 03504 { 03505 uint32_t USBFRAC : 1; /*!< [0] USB clock divider fraction */ 03506 uint32_t USBDIV : 3; /*!< [3:1] USB clock divider divisor */ 03507 uint32_t RESERVED0 : 28; /*!< [31:4] */ 03508 } B; 03509 } hw_sim_clkdiv2_t; 03510 03511 /*! 03512 * @name Constants and macros for entire SIM_CLKDIV2 register 03513 */ 03514 /*@{*/ 03515 #define HW_SIM_CLKDIV2_ADDR(x) ((x) + 0x1048U) 03516 03517 #define HW_SIM_CLKDIV2(x) (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR(x)) 03518 #define HW_SIM_CLKDIV2_RD(x) (ADDRESS_READ(hw_sim_clkdiv2_t, HW_SIM_CLKDIV2_ADDR(x))) 03519 #define HW_SIM_CLKDIV2_WR(x, v) (ADDRESS_WRITE(hw_sim_clkdiv2_t, HW_SIM_CLKDIV2_ADDR(x), v)) 03520 #define HW_SIM_CLKDIV2_SET(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) | (v))) 03521 #define HW_SIM_CLKDIV2_CLR(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) & ~(v))) 03522 #define HW_SIM_CLKDIV2_TOG(x, v) (HW_SIM_CLKDIV2_WR(x, HW_SIM_CLKDIV2_RD(x) ^ (v))) 03523 /*@}*/ 03524 03525 /* 03526 * Constants & macros for individual SIM_CLKDIV2 bitfields 03527 */ 03528 03529 /*! 03530 * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW) 03531 * 03532 * This field sets the fraction multiply value for the fractional clock divider 03533 * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 03534 * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] 03535 */ 03536 /*@{*/ 03537 #define BP_SIM_CLKDIV2_USBFRAC (0U) /*!< Bit position for SIM_CLKDIV2_USBFRAC. */ 03538 #define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) /*!< Bit mask for SIM_CLKDIV2_USBFRAC. */ 03539 #define BS_SIM_CLKDIV2_USBFRAC (1U) /*!< Bit field size in bits for SIM_CLKDIV2_USBFRAC. */ 03540 03541 /*! @brief Read current value of the SIM_CLKDIV2_USBFRAC field. */ 03542 #define BR_SIM_CLKDIV2_USBFRAC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC))) 03543 03544 /*! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC. */ 03545 #define BF_SIM_CLKDIV2_USBFRAC(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBFRAC) & BM_SIM_CLKDIV2_USBFRAC) 03546 03547 /*! @brief Set the USBFRAC field to a new value. */ 03548 #define BW_SIM_CLKDIV2_USBFRAC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_CLKDIV2_ADDR(x), BP_SIM_CLKDIV2_USBFRAC), v)) 03549 /*@}*/ 03550 03551 /*! 03552 * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW) 03553 * 03554 * This field sets the divide value for the fractional clock divider when the 03555 * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider 03556 * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ] 03557 */ 03558 /*@{*/ 03559 #define BP_SIM_CLKDIV2_USBDIV (1U) /*!< Bit position for SIM_CLKDIV2_USBDIV. */ 03560 #define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) /*!< Bit mask for SIM_CLKDIV2_USBDIV. */ 03561 #define BS_SIM_CLKDIV2_USBDIV (3U) /*!< Bit field size in bits for SIM_CLKDIV2_USBDIV. */ 03562 03563 /*! @brief Read current value of the SIM_CLKDIV2_USBDIV field. */ 03564 #define BR_SIM_CLKDIV2_USBDIV(x) (UNION_READ(hw_sim_clkdiv2_t, HW_SIM_CLKDIV2_ADDR(x), U, B.USBDIV)) 03565 03566 /*! @brief Format value for bitfield SIM_CLKDIV2_USBDIV. */ 03567 #define BF_SIM_CLKDIV2_USBDIV(v) ((uint32_t)((uint32_t)(v) << BP_SIM_CLKDIV2_USBDIV) & BM_SIM_CLKDIV2_USBDIV) 03568 03569 /*! @brief Set the USBDIV field to a new value. */ 03570 #define BW_SIM_CLKDIV2_USBDIV(x, v) (HW_SIM_CLKDIV2_WR(x, (HW_SIM_CLKDIV2_RD(x) & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v))) 03571 /*@}*/ 03572 03573 /******************************************************************************* 03574 * HW_SIM_FCFG1 - Flash Configuration Register 1 03575 ******************************************************************************/ 03576 03577 /*! 03578 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW) 03579 * 03580 * Reset value: 0xFF0F0F00U 03581 * 03582 * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on 03583 * user programming in user IFR via the PGMPART flash command. For devices with 03584 * program flash only: 03585 */ 03586 typedef union _hw_sim_fcfg1 03587 { 03588 uint32_t U; 03589 struct _hw_sim_fcfg1_bitfields 03590 { 03591 uint32_t FLASHDIS : 1; /*!< [0] Flash Disable */ 03592 uint32_t FLASHDOZE : 1; /*!< [1] Flash Doze */ 03593 uint32_t RESERVED0 : 6; /*!< [7:2] */ 03594 uint32_t DEPART : 4; /*!< [11:8] FlexNVM partition */ 03595 uint32_t RESERVED1 : 4; /*!< [15:12] */ 03596 uint32_t EESIZE : 4; /*!< [19:16] EEPROM size */ 03597 uint32_t RESERVED2 : 4; /*!< [23:20] */ 03598 uint32_t PFSIZE : 4; /*!< [27:24] Program flash size */ 03599 uint32_t NVMSIZE : 4; /*!< [31:28] FlexNVM size */ 03600 } B; 03601 } hw_sim_fcfg1_t; 03602 03603 /*! 03604 * @name Constants and macros for entire SIM_FCFG1 register 03605 */ 03606 /*@{*/ 03607 #define HW_SIM_FCFG1_ADDR(x) ((x) + 0x104CU) 03608 03609 #define HW_SIM_FCFG1(x) (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR(x)) 03610 #define HW_SIM_FCFG1_RD(x) (ADDRESS_READ(hw_sim_fcfg1_t, HW_SIM_FCFG1_ADDR(x))) 03611 #define HW_SIM_FCFG1_WR(x, v) (ADDRESS_WRITE(hw_sim_fcfg1_t, HW_SIM_FCFG1_ADDR(x), v)) 03612 #define HW_SIM_FCFG1_SET(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) | (v))) 03613 #define HW_SIM_FCFG1_CLR(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) & ~(v))) 03614 #define HW_SIM_FCFG1_TOG(x, v) (HW_SIM_FCFG1_WR(x, HW_SIM_FCFG1_RD(x) ^ (v))) 03615 /*@}*/ 03616 03617 /* 03618 * Constants & macros for individual SIM_FCFG1 bitfields 03619 */ 03620 03621 /*! 03622 * @name Register SIM_FCFG1, field FLASHDIS[0] (RW) 03623 * 03624 * Flash accesses are disabled (and generate a bus error) and the Flash memory 03625 * is placed in a low power state. This bit should not be changed during VLP 03626 * modes. Relocate the interrupt vectors out of Flash memory before disabling the 03627 * Flash. 03628 * 03629 * Values: 03630 * - 0 - Flash is enabled 03631 * - 1 - Flash is disabled 03632 */ 03633 /*@{*/ 03634 #define BP_SIM_FCFG1_FLASHDIS (0U) /*!< Bit position for SIM_FCFG1_FLASHDIS. */ 03635 #define BM_SIM_FCFG1_FLASHDIS (0x00000001U) /*!< Bit mask for SIM_FCFG1_FLASHDIS. */ 03636 #define BS_SIM_FCFG1_FLASHDIS (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDIS. */ 03637 03638 /*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */ 03639 #define BR_SIM_FCFG1_FLASHDIS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS))) 03640 03641 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDIS. */ 03642 #define BF_SIM_FCFG1_FLASHDIS(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDIS) & BM_SIM_FCFG1_FLASHDIS) 03643 03644 /*! @brief Set the FLASHDIS field to a new value. */ 03645 #define BW_SIM_FCFG1_FLASHDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDIS), v)) 03646 /*@}*/ 03647 03648 /*! 03649 * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW) 03650 * 03651 * When set, Flash memory is disabled for the duration of Wait mode. An attempt 03652 * by the DMA or other bus master to access the Flash when the Flash is disabled 03653 * will result in a bus error. This bit should be clear during VLP modes. The 03654 * Flash will be automatically enabled again at the end of Wait mode so interrupt 03655 * vectors do not need to be relocated out of Flash memory. The wakeup time from 03656 * Wait mode is extended when this bit is set. 03657 * 03658 * Values: 03659 * - 0 - Flash remains enabled during Wait mode 03660 * - 1 - Flash is disabled for the duration of Wait mode 03661 */ 03662 /*@{*/ 03663 #define BP_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit position for SIM_FCFG1_FLASHDOZE. */ 03664 #define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) /*!< Bit mask for SIM_FCFG1_FLASHDOZE. */ 03665 #define BS_SIM_FCFG1_FLASHDOZE (1U) /*!< Bit field size in bits for SIM_FCFG1_FLASHDOZE. */ 03666 03667 /*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */ 03668 #define BR_SIM_FCFG1_FLASHDOZE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE))) 03669 03670 /*! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE. */ 03671 #define BF_SIM_FCFG1_FLASHDOZE(v) ((uint32_t)((uint32_t)(v) << BP_SIM_FCFG1_FLASHDOZE) & BM_SIM_FCFG1_FLASHDOZE) 03672 03673 /*! @brief Set the FLASHDOZE field to a new value. */ 03674 #define BW_SIM_FCFG1_FLASHDOZE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SIM_FCFG1_ADDR(x), BP_SIM_FCFG1_FLASHDOZE), v)) 03675 /*@}*/ 03676 03677 /*! 03678 * @name Register SIM_FCFG1, field DEPART[11:8] (RO) 03679 * 03680 * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit 03681 * description in FTFE chapter. For devices without FlexNVM: Reserved 03682 */ 03683 /*@{*/ 03684 #define BP_SIM_FCFG1_DEPART (8U) /*!< Bit position for SIM_FCFG1_DEPART. */ 03685 #define BM_SIM_FCFG1_DEPART (0x00000F00U) /*!< Bit mask for SIM_FCFG1_DEPART. */ 03686 #define BS_SIM_FCFG1_DEPART (4U) /*!< Bit field size in bits for SIM_FCFG1_DEPART. */ 03687 03688 /*! @brief Read current value of the SIM_FCFG1_DEPART field. */ 03689 #define BR_SIM_FCFG1_DEPART(x) (UNION_READ(hw_sim_fcfg1_t, HW_SIM_FCFG1_ADDR(x), U, B.DEPART)) 03690 /*@}*/ 03691 03692 /*! 03693 * @name Register SIM_FCFG1, field EESIZE[19:16] (RO) 03694 * 03695 * EEPROM data size . 03696 * 03697 * Values: 03698 * - 0000 - 16 KB 03699 * - 0001 - 8 KB 03700 * - 0010 - 4 KB 03701 * - 0011 - 2 KB 03702 * - 0100 - 1 KB 03703 * - 0101 - 512 Bytes 03704 * - 0110 - 256 Bytes 03705 * - 0111 - 128 Bytes 03706 * - 1000 - 64 Bytes 03707 * - 1001 - 32 Bytes 03708 * - 1111 - 0 Bytes 03709 */ 03710 /*@{*/ 03711 #define BP_SIM_FCFG1_EESIZE (16U) /*!< Bit position for SIM_FCFG1_EESIZE. */ 03712 #define BM_SIM_FCFG1_EESIZE (0x000F0000U) /*!< Bit mask for SIM_FCFG1_EESIZE. */ 03713 #define BS_SIM_FCFG1_EESIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_EESIZE. */ 03714 03715 /*! @brief Read current value of the SIM_FCFG1_EESIZE field. */ 03716 #define BR_SIM_FCFG1_EESIZE(x) (UNION_READ(hw_sim_fcfg1_t, HW_SIM_FCFG1_ADDR(x), U, B.EESIZE)) 03717 /*@}*/ 03718 03719 /*! 03720 * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO) 03721 * 03722 * This field specifies the amount of program flash memory available on the 03723 * device . Undefined values are reserved. 03724 * 03725 * Values: 03726 * - 0011 - 32 KB of program flash memory 03727 * - 0101 - 64 KB of program flash memory 03728 * - 0111 - 128 KB of program flash memory 03729 * - 1001 - 256 KB of program flash memory 03730 * - 1011 - 512 KB of program flash memory 03731 * - 1101 - 1024 KB of program flash memory 03732 * - 1111 - 1024 KB of program flash memory 03733 */ 03734 /*@{*/ 03735 #define BP_SIM_FCFG1_PFSIZE (24U) /*!< Bit position for SIM_FCFG1_PFSIZE. */ 03736 #define BM_SIM_FCFG1_PFSIZE (0x0F000000U) /*!< Bit mask for SIM_FCFG1_PFSIZE. */ 03737 #define BS_SIM_FCFG1_PFSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_PFSIZE. */ 03738 03739 /*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */ 03740 #define BR_SIM_FCFG1_PFSIZE(x) (UNION_READ(hw_sim_fcfg1_t, HW_SIM_FCFG1_ADDR(x), U, B.PFSIZE)) 03741 /*@}*/ 03742 03743 /*! 03744 * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO) 03745 * 03746 * This field specifies the amount of FlexNVM memory available on the device . 03747 * Undefined values are reserved. 03748 * 03749 * Values: 03750 * - 0000 - 0 KB of FlexNVM 03751 * - 0011 - 32 KB of FlexNVM 03752 * - 0101 - 64 KB of FlexNVM 03753 * - 0111 - 128 KB of FlexNVM 03754 * - 1001 - 256 KB of FlexNVM 03755 * - 1011 - 512 KB of FlexNVM 03756 * - 1111 - 512 KB of FlexNVM 03757 */ 03758 /*@{*/ 03759 #define BP_SIM_FCFG1_NVMSIZE (28U) /*!< Bit position for SIM_FCFG1_NVMSIZE. */ 03760 #define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) /*!< Bit mask for SIM_FCFG1_NVMSIZE. */ 03761 #define BS_SIM_FCFG1_NVMSIZE (4U) /*!< Bit field size in bits for SIM_FCFG1_NVMSIZE. */ 03762 03763 /*! @brief Read current value of the SIM_FCFG1_NVMSIZE field. */ 03764 #define BR_SIM_FCFG1_NVMSIZE(x) (UNION_READ(hw_sim_fcfg1_t, HW_SIM_FCFG1_ADDR(x), U, B.NVMSIZE)) 03765 /*@}*/ 03766 03767 /******************************************************************************* 03768 * HW_SIM_FCFG2 - Flash Configuration Register 2 03769 ******************************************************************************/ 03770 03771 /*! 03772 * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO) 03773 * 03774 * Reset value: 0x7F7F0000U 03775 */ 03776 typedef union _hw_sim_fcfg2 03777 { 03778 uint32_t U; 03779 struct _hw_sim_fcfg2_bitfields 03780 { 03781 uint32_t RESERVED0 : 16; /*!< [15:0] */ 03782 uint32_t MAXADDR1 : 7; /*!< [22:16] Max address block 1 */ 03783 uint32_t PFLSH : 1; /*!< [23] Program flash only */ 03784 uint32_t MAXADDR0 : 7; /*!< [30:24] Max address block 0 */ 03785 uint32_t RESERVED1 : 1; /*!< [31] */ 03786 } B; 03787 } hw_sim_fcfg2_t; 03788 03789 /*! 03790 * @name Constants and macros for entire SIM_FCFG2 register 03791 */ 03792 /*@{*/ 03793 #define HW_SIM_FCFG2_ADDR(x) ((x) + 0x1050U) 03794 03795 #define HW_SIM_FCFG2(x) (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR(x)) 03796 #define HW_SIM_FCFG2_RD(x) (ADDRESS_READ(hw_sim_fcfg2_t, HW_SIM_FCFG2_ADDR(x))) 03797 /*@}*/ 03798 03799 /* 03800 * Constants & macros for individual SIM_FCFG2 bitfields 03801 */ 03802 03803 /*! 03804 * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO) 03805 * 03806 * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus 03807 * the FlexNVM base address indicates the first invalid address of the FlexNVM 03808 * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of 03809 * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value 03810 * for a device with 256 KB FlexNVM. For devices with program flash only: This 03811 * field equals zero if there is only one program flash block, otherwise it equals 03812 * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20 03813 * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be 03814 * the MAXADDR1 value for a device with 512 KB program flash memory across two 03815 * flash blocks and no FlexNVM. 03816 */ 03817 /*@{*/ 03818 #define BP_SIM_FCFG2_MAXADDR1 (16U) /*!< Bit position for SIM_FCFG2_MAXADDR1. */ 03819 #define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) /*!< Bit mask for SIM_FCFG2_MAXADDR1. */ 03820 #define BS_SIM_FCFG2_MAXADDR1 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR1. */ 03821 03822 /*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */ 03823 #define BR_SIM_FCFG2_MAXADDR1(x) (UNION_READ(hw_sim_fcfg2_t, HW_SIM_FCFG2_ADDR(x), U, B.MAXADDR1)) 03824 /*@}*/ 03825 03826 /*! 03827 * @name Register SIM_FCFG2, field PFLSH[23] (RO) 03828 * 03829 * For devices with FlexNVM, this bit is always clear. For devices without 03830 * FlexNVM, this bit is always set. 03831 * 03832 * Values: 03833 * - 0 - Device supports FlexNVM 03834 * - 1 - Program Flash only, device does not support FlexNVM 03835 */ 03836 /*@{*/ 03837 #define BP_SIM_FCFG2_PFLSH (23U) /*!< Bit position for SIM_FCFG2_PFLSH. */ 03838 #define BM_SIM_FCFG2_PFLSH (0x00800000U) /*!< Bit mask for SIM_FCFG2_PFLSH. */ 03839 #define BS_SIM_FCFG2_PFLSH (1U) /*!< Bit field size in bits for SIM_FCFG2_PFLSH. */ 03840 03841 /*! @brief Read current value of the SIM_FCFG2_PFLSH field. */ 03842 #define BR_SIM_FCFG2_PFLSH(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SIM_FCFG2_ADDR(x), BP_SIM_FCFG2_PFLSH))) 03843 /*@}*/ 03844 03845 /*! 03846 * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO) 03847 * 03848 * This field concatenated with 13 trailing zeros indicates the first invalid 03849 * address of each program flash block. For example, if MAXADDR0 = 0x20 the first 03850 * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0 03851 * value for a device with 256 KB program flash in flash block 0. 03852 */ 03853 /*@{*/ 03854 #define BP_SIM_FCFG2_MAXADDR0 (24U) /*!< Bit position for SIM_FCFG2_MAXADDR0. */ 03855 #define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) /*!< Bit mask for SIM_FCFG2_MAXADDR0. */ 03856 #define BS_SIM_FCFG2_MAXADDR0 (7U) /*!< Bit field size in bits for SIM_FCFG2_MAXADDR0. */ 03857 03858 /*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */ 03859 #define BR_SIM_FCFG2_MAXADDR0(x) (UNION_READ(hw_sim_fcfg2_t, HW_SIM_FCFG2_ADDR(x), U, B.MAXADDR0)) 03860 /*@}*/ 03861 03862 /******************************************************************************* 03863 * HW_SIM_UIDH - Unique Identification Register High 03864 ******************************************************************************/ 03865 03866 /*! 03867 * @brief HW_SIM_UIDH - Unique Identification Register High (RO) 03868 * 03869 * Reset value: 0x00000000U 03870 */ 03871 typedef union _hw_sim_uidh 03872 { 03873 uint32_t U; 03874 struct _hw_sim_uidh_bitfields 03875 { 03876 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 03877 } B; 03878 } hw_sim_uidh_t; 03879 03880 /*! 03881 * @name Constants and macros for entire SIM_UIDH register 03882 */ 03883 /*@{*/ 03884 #define HW_SIM_UIDH_ADDR(x) ((x) + 0x1054U) 03885 03886 #define HW_SIM_UIDH(x) (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR(x)) 03887 #define HW_SIM_UIDH_RD(x) (ADDRESS_READ(hw_sim_uidh_t, HW_SIM_UIDH_ADDR(x))) 03888 /*@}*/ 03889 03890 /* 03891 * Constants & macros for individual SIM_UIDH bitfields 03892 */ 03893 03894 /*! 03895 * @name Register SIM_UIDH, field UID[31:0] (RO) 03896 * 03897 * Unique identification for the device. 03898 */ 03899 /*@{*/ 03900 #define BP_SIM_UIDH_UID (0U) /*!< Bit position for SIM_UIDH_UID. */ 03901 #define BM_SIM_UIDH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDH_UID. */ 03902 #define BS_SIM_UIDH_UID (32U) /*!< Bit field size in bits for SIM_UIDH_UID. */ 03903 03904 /*! @brief Read current value of the SIM_UIDH_UID field. */ 03905 #define BR_SIM_UIDH_UID(x) (HW_SIM_UIDH(x).U) 03906 /*@}*/ 03907 03908 /******************************************************************************* 03909 * HW_SIM_UIDMH - Unique Identification Register Mid-High 03910 ******************************************************************************/ 03911 03912 /*! 03913 * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO) 03914 * 03915 * Reset value: 0x00000000U 03916 */ 03917 typedef union _hw_sim_uidmh 03918 { 03919 uint32_t U; 03920 struct _hw_sim_uidmh_bitfields 03921 { 03922 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 03923 } B; 03924 } hw_sim_uidmh_t; 03925 03926 /*! 03927 * @name Constants and macros for entire SIM_UIDMH register 03928 */ 03929 /*@{*/ 03930 #define HW_SIM_UIDMH_ADDR(x) ((x) + 0x1058U) 03931 03932 #define HW_SIM_UIDMH(x) (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR(x)) 03933 #define HW_SIM_UIDMH_RD(x) (ADDRESS_READ(hw_sim_uidmh_t, HW_SIM_UIDMH_ADDR(x))) 03934 /*@}*/ 03935 03936 /* 03937 * Constants & macros for individual SIM_UIDMH bitfields 03938 */ 03939 03940 /*! 03941 * @name Register SIM_UIDMH, field UID[31:0] (RO) 03942 * 03943 * Unique identification for the device. 03944 */ 03945 /*@{*/ 03946 #define BP_SIM_UIDMH_UID (0U) /*!< Bit position for SIM_UIDMH_UID. */ 03947 #define BM_SIM_UIDMH_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDMH_UID. */ 03948 #define BS_SIM_UIDMH_UID (32U) /*!< Bit field size in bits for SIM_UIDMH_UID. */ 03949 03950 /*! @brief Read current value of the SIM_UIDMH_UID field. */ 03951 #define BR_SIM_UIDMH_UID(x) (HW_SIM_UIDMH(x).U) 03952 /*@}*/ 03953 03954 /******************************************************************************* 03955 * HW_SIM_UIDML - Unique Identification Register Mid Low 03956 ******************************************************************************/ 03957 03958 /*! 03959 * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO) 03960 * 03961 * Reset value: 0x00000000U 03962 */ 03963 typedef union _hw_sim_uidml 03964 { 03965 uint32_t U; 03966 struct _hw_sim_uidml_bitfields 03967 { 03968 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 03969 } B; 03970 } hw_sim_uidml_t; 03971 03972 /*! 03973 * @name Constants and macros for entire SIM_UIDML register 03974 */ 03975 /*@{*/ 03976 #define HW_SIM_UIDML_ADDR(x) ((x) + 0x105CU) 03977 03978 #define HW_SIM_UIDML(x) (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR(x)) 03979 #define HW_SIM_UIDML_RD(x) (ADDRESS_READ(hw_sim_uidml_t, HW_SIM_UIDML_ADDR(x))) 03980 /*@}*/ 03981 03982 /* 03983 * Constants & macros for individual SIM_UIDML bitfields 03984 */ 03985 03986 /*! 03987 * @name Register SIM_UIDML, field UID[31:0] (RO) 03988 * 03989 * Unique identification for the device. 03990 */ 03991 /*@{*/ 03992 #define BP_SIM_UIDML_UID (0U) /*!< Bit position for SIM_UIDML_UID. */ 03993 #define BM_SIM_UIDML_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDML_UID. */ 03994 #define BS_SIM_UIDML_UID (32U) /*!< Bit field size in bits for SIM_UIDML_UID. */ 03995 03996 /*! @brief Read current value of the SIM_UIDML_UID field. */ 03997 #define BR_SIM_UIDML_UID(x) (HW_SIM_UIDML(x).U) 03998 /*@}*/ 03999 04000 /******************************************************************************* 04001 * HW_SIM_UIDL - Unique Identification Register Low 04002 ******************************************************************************/ 04003 04004 /*! 04005 * @brief HW_SIM_UIDL - Unique Identification Register Low (RO) 04006 * 04007 * Reset value: 0x00000000U 04008 */ 04009 typedef union _hw_sim_uidl 04010 { 04011 uint32_t U; 04012 struct _hw_sim_uidl_bitfields 04013 { 04014 uint32_t UID : 32; /*!< [31:0] Unique Identification */ 04015 } B; 04016 } hw_sim_uidl_t; 04017 04018 /*! 04019 * @name Constants and macros for entire SIM_UIDL register 04020 */ 04021 /*@{*/ 04022 #define HW_SIM_UIDL_ADDR(x) ((x) + 0x1060U) 04023 04024 #define HW_SIM_UIDL(x) (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR(x)) 04025 #define HW_SIM_UIDL_RD(x) (ADDRESS_READ(hw_sim_uidl_t, HW_SIM_UIDL_ADDR(x))) 04026 /*@}*/ 04027 04028 /* 04029 * Constants & macros for individual SIM_UIDL bitfields 04030 */ 04031 04032 /*! 04033 * @name Register SIM_UIDL, field UID[31:0] (RO) 04034 * 04035 * Unique identification for the device. 04036 */ 04037 /*@{*/ 04038 #define BP_SIM_UIDL_UID (0U) /*!< Bit position for SIM_UIDL_UID. */ 04039 #define BM_SIM_UIDL_UID (0xFFFFFFFFU) /*!< Bit mask for SIM_UIDL_UID. */ 04040 #define BS_SIM_UIDL_UID (32U) /*!< Bit field size in bits for SIM_UIDL_UID. */ 04041 04042 /*! @brief Read current value of the SIM_UIDL_UID field. */ 04043 #define BR_SIM_UIDL_UID(x) (HW_SIM_UIDL(x).U) 04044 /*@}*/ 04045 04046 /******************************************************************************* 04047 * hw_sim_t - module struct 04048 ******************************************************************************/ 04049 /*! 04050 * @brief All SIM module registers. 04051 */ 04052 #pragma pack(1) 04053 typedef struct _hw_sim 04054 { 04055 __IO hw_sim_sopt1_t SOPT1 ; /*!< [0x0] System Options Register 1 */ 04056 __IO hw_sim_sopt1cfg_t SOPT1CFG ; /*!< [0x4] SOPT1 Configuration Register */ 04057 uint8_t _reserved0[4092]; 04058 __IO hw_sim_sopt2_t SOPT2 ; /*!< [0x1004] System Options Register 2 */ 04059 uint8_t _reserved1[4]; 04060 __IO hw_sim_sopt4_t SOPT4 ; /*!< [0x100C] System Options Register 4 */ 04061 __IO hw_sim_sopt5_t SOPT5 ; /*!< [0x1010] System Options Register 5 */ 04062 uint8_t _reserved2[4]; 04063 __IO hw_sim_sopt7_t SOPT7 ; /*!< [0x1018] System Options Register 7 */ 04064 uint8_t _reserved3[8]; 04065 __I hw_sim_sdid_t SDID ; /*!< [0x1024] System Device Identification Register */ 04066 __IO hw_sim_scgc1_t SCGC1 ; /*!< [0x1028] System Clock Gating Control Register 1 */ 04067 __IO hw_sim_scgc2_t SCGC2 ; /*!< [0x102C] System Clock Gating Control Register 2 */ 04068 __IO hw_sim_scgc3_t SCGC3 ; /*!< [0x1030] System Clock Gating Control Register 3 */ 04069 __IO hw_sim_scgc4_t SCGC4 ; /*!< [0x1034] System Clock Gating Control Register 4 */ 04070 __IO hw_sim_scgc5_t SCGC5 ; /*!< [0x1038] System Clock Gating Control Register 5 */ 04071 __IO hw_sim_scgc6_t SCGC6 ; /*!< [0x103C] System Clock Gating Control Register 6 */ 04072 __IO hw_sim_scgc7_t SCGC7 ; /*!< [0x1040] System Clock Gating Control Register 7 */ 04073 __IO hw_sim_clkdiv1_t CLKDIV1 ; /*!< [0x1044] System Clock Divider Register 1 */ 04074 __IO hw_sim_clkdiv2_t CLKDIV2 ; /*!< [0x1048] System Clock Divider Register 2 */ 04075 __IO hw_sim_fcfg1_t FCFG1 ; /*!< [0x104C] Flash Configuration Register 1 */ 04076 __I hw_sim_fcfg2_t FCFG2 ; /*!< [0x1050] Flash Configuration Register 2 */ 04077 __I hw_sim_uidh_t UIDH ; /*!< [0x1054] Unique Identification Register High */ 04078 __I hw_sim_uidmh_t UIDMH ; /*!< [0x1058] Unique Identification Register Mid-High */ 04079 __I hw_sim_uidml_t UIDML ; /*!< [0x105C] Unique Identification Register Mid Low */ 04080 __I hw_sim_uidl_t UIDL ; /*!< [0x1060] Unique Identification Register Low */ 04081 } hw_sim_t; 04082 #pragma pack() 04083 04084 /*! @brief Macro to access all SIM registers. */ 04085 /*! @param x SIM module instance base address. */ 04086 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, 04087 * use the '&' operator, like <code>&HW_SIM(SIM_BASE)</code>. */ 04088 #define HW_SIM(x) (*(hw_sim_t *)(x)) 04089 04090 #endif /* __HW_SIM_REGISTERS_H__ */ 04091 /* EOF */
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