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_hw_sim_scgc3 Union Reference
HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW) More...
#include <MK64F12_sim.h>
Detailed Description
HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
Reset value: 0x00000000U
FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing through AIPS1, define the clock gate control bits in the SCGC3. When accessing through AIPS0, define the clock gate control bits in SCGC6.
Definition at line 2016 of file MK64F12_sim.h.
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