MK64F12_sdhc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_SDHC_REGISTERS_H__
00088 #define __HW_SDHC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 SDHC
00095  *
00096  * Secured Digital Host Controller
00097  *
00098  * Registers defined in this header file:
00099  * - HW_SDHC_DSADDR - DMA System Address register
00100  * - HW_SDHC_BLKATTR - Block Attributes register
00101  * - HW_SDHC_CMDARG - Command Argument register
00102  * - HW_SDHC_XFERTYP - Transfer Type register
00103  * - HW_SDHC_CMDRSP0 - Command Response 0
00104  * - HW_SDHC_CMDRSP1 - Command Response 1
00105  * - HW_SDHC_CMDRSP2 - Command Response 2
00106  * - HW_SDHC_CMDRSP3 - Command Response 3
00107  * - HW_SDHC_DATPORT - Buffer Data Port register
00108  * - HW_SDHC_PRSSTAT - Present State register
00109  * - HW_SDHC_PROCTL - Protocol Control register
00110  * - HW_SDHC_SYSCTL - System Control register
00111  * - HW_SDHC_IRQSTAT - Interrupt Status register
00112  * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register
00113  * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
00114  * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
00115  * - HW_SDHC_HTCAPBLT - Host Controller Capabilities
00116  * - HW_SDHC_WML - Watermark Level Register
00117  * - HW_SDHC_FEVT - Force Event register
00118  * - HW_SDHC_ADMAES - ADMA Error Status register
00119  * - HW_SDHC_ADSADDR - ADMA System Addressregister
00120  * - HW_SDHC_VENDOR - Vendor Specific register
00121  * - HW_SDHC_MMCBOOT - MMC Boot register
00122  * - HW_SDHC_HOSTVER - Host Controller Version
00123  *
00124  * - hw_sdhc_t - Struct containing all module registers.
00125  */
00126 
00127 #define HW_SDHC_INSTANCE_COUNT (1U) /*!< Number of instances of the SDHC module. */
00128 
00129 /*******************************************************************************
00130  * HW_SDHC_DSADDR - DMA System Address register
00131  ******************************************************************************/
00132 
00133 /*!
00134  * @brief HW_SDHC_DSADDR - DMA System Address register (RW)
00135  *
00136  * Reset value: 0x00000000U
00137  *
00138  * This register contains the physical system memory address used for DMA
00139  * transfers.
00140  */
00141 typedef union _hw_sdhc_dsaddr
00142 {
00143     uint32_t U;
00144     struct _hw_sdhc_dsaddr_bitfields
00145     {
00146         uint32_t RESERVED0 : 2;        /*!< [1:0]  */
00147         uint32_t DSADDR : 30;          /*!< [31:2] DMA System Address */
00148     } B;
00149 } hw_sdhc_dsaddr_t;
00150 
00151 /*!
00152  * @name Constants and macros for entire SDHC_DSADDR register
00153  */
00154 /*@{*/
00155 #define HW_SDHC_DSADDR_ADDR(x)   ((x) + 0x0U)
00156 
00157 #define HW_SDHC_DSADDR(x)        (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR(x))
00158 #define HW_SDHC_DSADDR_RD(x)     (ADDRESS_READ(hw_sdhc_dsaddr_t, HW_SDHC_DSADDR_ADDR(x)))
00159 #define HW_SDHC_DSADDR_WR(x, v)  (ADDRESS_WRITE(hw_sdhc_dsaddr_t, HW_SDHC_DSADDR_ADDR(x), v))
00160 #define HW_SDHC_DSADDR_SET(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) |  (v)))
00161 #define HW_SDHC_DSADDR_CLR(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) & ~(v)))
00162 #define HW_SDHC_DSADDR_TOG(x, v) (HW_SDHC_DSADDR_WR(x, HW_SDHC_DSADDR_RD(x) ^  (v)))
00163 /*@}*/
00164 
00165 /*
00166  * Constants & macros for individual SDHC_DSADDR bitfields
00167  */
00168 
00169 /*!
00170  * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
00171  *
00172  * Contains the 32-bit system memory address for a DMA transfer. Because the
00173  * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
00174  * When the SDHC stops a DMA transfer, this register points to the system address
00175  * of the next contiguous data position. It can be accessed only when no
00176  * transaction is executing, that is, after a transaction has stopped. Read operation
00177  * during transfers may return an invalid value. The host driver shall initialize
00178  * this register before starting a DMA transaction. After DMA has stopped, the
00179  * system address of the next contiguous data position can be read from this register.
00180  * This register is protected during a data transfer. When data lines are
00181  * active, write to this register is ignored. The host driver shall wait, until
00182  * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
00183  * not support a virtual memory system. It supports only continuous physical
00184  * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
00185  * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
00186  * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
00187  * automatically alters the value of internal address counter, so SW cannot
00188  * change this register when IRQSTAT[TC] is set.
00189  */
00190 /*@{*/
00191 #define BP_SDHC_DSADDR_DSADDR (2U)         /*!< Bit position for SDHC_DSADDR_DSADDR. */
00192 #define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) /*!< Bit mask for SDHC_DSADDR_DSADDR. */
00193 #define BS_SDHC_DSADDR_DSADDR (30U)        /*!< Bit field size in bits for SDHC_DSADDR_DSADDR. */
00194 
00195 /*! @brief Read current value of the SDHC_DSADDR_DSADDR field. */
00196 #define BR_SDHC_DSADDR_DSADDR(x) (UNION_READ(hw_sdhc_dsaddr_t, HW_SDHC_DSADDR_ADDR(x), U, B.DSADDR))
00197 
00198 /*! @brief Format value for bitfield SDHC_DSADDR_DSADDR. */
00199 #define BF_SDHC_DSADDR_DSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DSADDR_DSADDR) & BM_SDHC_DSADDR_DSADDR)
00200 
00201 /*! @brief Set the DSADDR field to a new value. */
00202 #define BW_SDHC_DSADDR_DSADDR(x, v) (HW_SDHC_DSADDR_WR(x, (HW_SDHC_DSADDR_RD(x) & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v)))
00203 /*@}*/
00204 
00205 /*******************************************************************************
00206  * HW_SDHC_BLKATTR - Block Attributes register
00207  ******************************************************************************/
00208 
00209 /*!
00210  * @brief HW_SDHC_BLKATTR - Block Attributes register (RW)
00211  *
00212  * Reset value: 0x00000000U
00213  *
00214  * This register is used to configure the number of data blocks and the number
00215  * of bytes in each block.
00216  */
00217 typedef union _hw_sdhc_blkattr
00218 {
00219     uint32_t U;
00220     struct _hw_sdhc_blkattr_bitfields
00221     {
00222         uint32_t BLKSIZE : 13;         /*!< [12:0] Transfer Block Size */
00223         uint32_t RESERVED0 : 3;        /*!< [15:13]  */
00224         uint32_t BLKCNT : 16;          /*!< [31:16] Blocks Count For Current Transfer
00225                                         * */
00226     } B;
00227 } hw_sdhc_blkattr_t;
00228 
00229 /*!
00230  * @name Constants and macros for entire SDHC_BLKATTR register
00231  */
00232 /*@{*/
00233 #define HW_SDHC_BLKATTR_ADDR(x)  ((x) + 0x4U)
00234 
00235 #define HW_SDHC_BLKATTR(x)       (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR(x))
00236 #define HW_SDHC_BLKATTR_RD(x)    (ADDRESS_READ(hw_sdhc_blkattr_t, HW_SDHC_BLKATTR_ADDR(x)))
00237 #define HW_SDHC_BLKATTR_WR(x, v) (ADDRESS_WRITE(hw_sdhc_blkattr_t, HW_SDHC_BLKATTR_ADDR(x), v))
00238 #define HW_SDHC_BLKATTR_SET(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) |  (v)))
00239 #define HW_SDHC_BLKATTR_CLR(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) & ~(v)))
00240 #define HW_SDHC_BLKATTR_TOG(x, v) (HW_SDHC_BLKATTR_WR(x, HW_SDHC_BLKATTR_RD(x) ^  (v)))
00241 /*@}*/
00242 
00243 /*
00244  * Constants & macros for individual SDHC_BLKATTR bitfields
00245  */
00246 
00247 /*!
00248  * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
00249  *
00250  * Specifies the block size for block data transfers. Values ranging from 1 byte
00251  * up to the maximum buffer size can be set. It can be accessed only when no
00252  * transaction is executing, that is, after a transaction has stopped. Read
00253  * operations during transfers may return an invalid value, and write operations will be
00254  * ignored.
00255  *
00256  * Values:
00257  * - 0 - No data transfer.
00258  * - 1 - 1 Byte
00259  * - 10 - 2 Bytes
00260  * - 11 - 3 Bytes
00261  * - 100 - 4 Bytes
00262  * - 111111111 - 511 Bytes
00263  * - 1000000000 - 512 Bytes
00264  * - 100000000000 - 2048 Bytes
00265  * - 1000000000000 - 4096 Bytes
00266  */
00267 /*@{*/
00268 #define BP_SDHC_BLKATTR_BLKSIZE (0U)       /*!< Bit position for SDHC_BLKATTR_BLKSIZE. */
00269 #define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) /*!< Bit mask for SDHC_BLKATTR_BLKSIZE. */
00270 #define BS_SDHC_BLKATTR_BLKSIZE (13U)      /*!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE. */
00271 
00272 /*! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field. */
00273 #define BR_SDHC_BLKATTR_BLKSIZE(x) (UNION_READ(hw_sdhc_blkattr_t, HW_SDHC_BLKATTR_ADDR(x), U, B.BLKSIZE))
00274 
00275 /*! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE. */
00276 #define BF_SDHC_BLKATTR_BLKSIZE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKSIZE) & BM_SDHC_BLKATTR_BLKSIZE)
00277 
00278 /*! @brief Set the BLKSIZE field to a new value. */
00279 #define BW_SDHC_BLKATTR_BLKSIZE(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v)))
00280 /*@}*/
00281 
00282 /*!
00283  * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
00284  *
00285  * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
00286  * multiple block transfers. For single block transfer, this register will
00287  * always read as 1. The host driver shall set this register to a value between 1 and
00288  * the maximum block count. The SDHC decrements the block count after each block
00289  * transfer and stops when the count reaches zero. Setting the block count to 0
00290  * results in no data blocks being transferred. This register must be accessed
00291  * only when no transaction is executing, that is, after transactions are stopped.
00292  * During data transfer, read operations on this register may return an invalid
00293  * value and write operations are ignored. When saving transfer content as a result
00294  * of a suspend command, the number of blocks yet to be transferred can be
00295  * determined by reading this register. The reading of this register must be applied
00296  * after transfer is paused by stop at block gap operation and before sending the
00297  * command marked as suspend. This is because when suspend command is sent out,
00298  * SDHC will regard the current transfer as aborted and change BLKCNT back to its
00299  * original value instead of keeping the dynamical indicator of remained block
00300  * count. When restoring transfer content prior to issuing a resume command, the
00301  * host driver shall restore the previously saved block count. Although the BLKCNT
00302  * field is 0 after reset, the read of reset value is 0x1. This is because when
00303  * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
00304  * BLKCNT is always 1.
00305  *
00306  * Values:
00307  * - 0 - Stop count.
00308  * - 1 - 1 block
00309  * - 10 - 2 blocks
00310  * - 1111111111111111 - 65535 blocks
00311  */
00312 /*@{*/
00313 #define BP_SDHC_BLKATTR_BLKCNT (16U)       /*!< Bit position for SDHC_BLKATTR_BLKCNT. */
00314 #define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) /*!< Bit mask for SDHC_BLKATTR_BLKCNT. */
00315 #define BS_SDHC_BLKATTR_BLKCNT (16U)       /*!< Bit field size in bits for SDHC_BLKATTR_BLKCNT. */
00316 
00317 /*! @brief Read current value of the SDHC_BLKATTR_BLKCNT field. */
00318 #define BR_SDHC_BLKATTR_BLKCNT(x) (UNION_READ(hw_sdhc_blkattr_t, HW_SDHC_BLKATTR_ADDR(x), U, B.BLKCNT))
00319 
00320 /*! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT. */
00321 #define BF_SDHC_BLKATTR_BLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_BLKATTR_BLKCNT) & BM_SDHC_BLKATTR_BLKCNT)
00322 
00323 /*! @brief Set the BLKCNT field to a new value. */
00324 #define BW_SDHC_BLKATTR_BLKCNT(x, v) (HW_SDHC_BLKATTR_WR(x, (HW_SDHC_BLKATTR_RD(x) & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v)))
00325 /*@}*/
00326 
00327 /*******************************************************************************
00328  * HW_SDHC_CMDARG - Command Argument register
00329  ******************************************************************************/
00330 
00331 /*!
00332  * @brief HW_SDHC_CMDARG - Command Argument register (RW)
00333  *
00334  * Reset value: 0x00000000U
00335  *
00336  * This register contains the SD/MMC command argument.
00337  */
00338 typedef union _hw_sdhc_cmdarg
00339 {
00340     uint32_t U;
00341     struct _hw_sdhc_cmdarg_bitfields
00342     {
00343         uint32_t CMDARG : 32;          /*!< [31:0] Command Argument */
00344     } B;
00345 } hw_sdhc_cmdarg_t;
00346 
00347 /*!
00348  * @name Constants and macros for entire SDHC_CMDARG register
00349  */
00350 /*@{*/
00351 #define HW_SDHC_CMDARG_ADDR(x)   ((x) + 0x8U)
00352 
00353 #define HW_SDHC_CMDARG(x)        (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR(x))
00354 #define HW_SDHC_CMDARG_RD(x)     (ADDRESS_READ(hw_sdhc_cmdarg_t, HW_SDHC_CMDARG_ADDR(x)))
00355 #define HW_SDHC_CMDARG_WR(x, v)  (ADDRESS_WRITE(hw_sdhc_cmdarg_t, HW_SDHC_CMDARG_ADDR(x), v))
00356 #define HW_SDHC_CMDARG_SET(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) |  (v)))
00357 #define HW_SDHC_CMDARG_CLR(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) & ~(v)))
00358 #define HW_SDHC_CMDARG_TOG(x, v) (HW_SDHC_CMDARG_WR(x, HW_SDHC_CMDARG_RD(x) ^  (v)))
00359 /*@}*/
00360 
00361 /*
00362  * Constants & macros for individual SDHC_CMDARG bitfields
00363  */
00364 
00365 /*!
00366  * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW)
00367  *
00368  * The SD/MMC command argument is specified as bits 39-8 of the command format
00369  * in the SD or MMC specification. This register is write protected when
00370  * PRSSTAT[CDIHB0] is set.
00371  */
00372 /*@{*/
00373 #define BP_SDHC_CMDARG_CMDARG (0U)         /*!< Bit position for SDHC_CMDARG_CMDARG. */
00374 #define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDARG_CMDARG. */
00375 #define BS_SDHC_CMDARG_CMDARG (32U)        /*!< Bit field size in bits for SDHC_CMDARG_CMDARG. */
00376 
00377 /*! @brief Read current value of the SDHC_CMDARG_CMDARG field. */
00378 #define BR_SDHC_CMDARG_CMDARG(x) (HW_SDHC_CMDARG(x).U)
00379 
00380 /*! @brief Format value for bitfield SDHC_CMDARG_CMDARG. */
00381 #define BF_SDHC_CMDARG_CMDARG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_CMDARG_CMDARG) & BM_SDHC_CMDARG_CMDARG)
00382 
00383 /*! @brief Set the CMDARG field to a new value. */
00384 #define BW_SDHC_CMDARG_CMDARG(x, v) (HW_SDHC_CMDARG_WR(x, v))
00385 /*@}*/
00386 
00387 /*******************************************************************************
00388  * HW_SDHC_XFERTYP - Transfer Type register
00389  ******************************************************************************/
00390 
00391 /*!
00392  * @brief HW_SDHC_XFERTYP - Transfer Type register (RW)
00393  *
00394  * Reset value: 0x00000000U
00395  *
00396  * This register is used to control the operation of data transfers. The host
00397  * driver shall set this register before issuing a command followed by a data
00398  * transfer, or before issuing a resume command. To prevent data loss, the SDHC
00399  * prevents writing to the bits that are involved in the data transfer of this
00400  * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
00401  * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
00402  * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
00403  * send a command with data by writing to this register is ignored; when
00404  * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
00405  * data transfer involved, it is mandatory that the block size is nonzero.
00406  * Besides, block count must also be nonzero, or indicated as single block transfer
00407  * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
00408  * this register is 0 when written), otherwise SDHC will ignore the sending of
00409  * this command and do nothing. For write command, with all above restrictions, it
00410  * is also mandatory that the write protect switch is not active (WPSPL bit of
00411  * Present State Register is 1), otherwise SDHC will also ignore the command. If
00412  * the commands with data transfer does not receive the response in 64 clock
00413  * cycles, that is, response time-out, SDHC will regard the external device does not
00414  * accept the command and abort the data transfer. In this scenario, the driver
00415  * must issue the command again to retry the transfer. It is also possible that,
00416  * for some reason, the card responds to the command but SDHC does not receive the
00417  * response, and if it is internal DMA (either simple DMA or ADMA) read
00418  * operation, the external system memory is over-written by the internal DMA with data
00419  * sent back from the card. The following table shows the summary of how register
00420  * settings determine the type of data transfer. Transfer Type register setting for
00421  * various transfer types Multi/Single block select Block count enable Block
00422  * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
00423  * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
00424  * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
00425  * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
00426  * Relationship between parameters and the name of the response type Response type
00427  * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
00428  * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
00429  * the SDIO specification, response type notation for R5b is not defined. R5
00430  * includes R5b in the SDIO specification. But R5b is defined in this specification
00431  * to specify that the SDHC will check the busy status after receiving a
00432  * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
00433  * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
00434  * The CRC check shall be disabled for these response types.
00435  */
00436 typedef union _hw_sdhc_xfertyp
00437 {
00438     uint32_t U;
00439     struct _hw_sdhc_xfertyp_bitfields
00440     {
00441         uint32_t DMAEN : 1;            /*!< [0] DMA Enable */
00442         uint32_t BCEN : 1;             /*!< [1] Block Count Enable */
00443         uint32_t AC12EN : 1;           /*!< [2] Auto CMD12 Enable */
00444         uint32_t RESERVED0 : 1;        /*!< [3]  */
00445         uint32_t DTDSEL : 1;           /*!< [4] Data Transfer Direction Select */
00446         uint32_t MSBSEL : 1;           /*!< [5] Multi/Single Block Select */
00447         uint32_t RESERVED1 : 10;       /*!< [15:6]  */
00448         uint32_t RSPTYP : 2;           /*!< [17:16] Response Type Select */
00449         uint32_t RESERVED2 : 1;        /*!< [18]  */
00450         uint32_t CCCEN : 1;            /*!< [19] Command CRC Check Enable */
00451         uint32_t CICEN : 1;            /*!< [20] Command Index Check Enable */
00452         uint32_t DPSEL : 1;            /*!< [21] Data Present Select */
00453         uint32_t CMDTYP : 2;           /*!< [23:22] Command Type */
00454         uint32_t CMDINX : 6;           /*!< [29:24] Command Index */
00455         uint32_t RESERVED3 : 2;        /*!< [31:30]  */
00456     } B;
00457 } hw_sdhc_xfertyp_t;
00458 
00459 /*!
00460  * @name Constants and macros for entire SDHC_XFERTYP register
00461  */
00462 /*@{*/
00463 #define HW_SDHC_XFERTYP_ADDR(x)  ((x) + 0xCU)
00464 
00465 #define HW_SDHC_XFERTYP(x)       (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR(x))
00466 #define HW_SDHC_XFERTYP_RD(x)    (ADDRESS_READ(hw_sdhc_xfertyp_t, HW_SDHC_XFERTYP_ADDR(x)))
00467 #define HW_SDHC_XFERTYP_WR(x, v) (ADDRESS_WRITE(hw_sdhc_xfertyp_t, HW_SDHC_XFERTYP_ADDR(x), v))
00468 #define HW_SDHC_XFERTYP_SET(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) |  (v)))
00469 #define HW_SDHC_XFERTYP_CLR(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) & ~(v)))
00470 #define HW_SDHC_XFERTYP_TOG(x, v) (HW_SDHC_XFERTYP_WR(x, HW_SDHC_XFERTYP_RD(x) ^  (v)))
00471 /*@}*/
00472 
00473 /*
00474  * Constants & macros for individual SDHC_XFERTYP bitfields
00475  */
00476 
00477 /*!
00478  * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
00479  *
00480  * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
00481  * begin when the host driver sets the DPSEL bit of this register. Whether the
00482  * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
00483  *
00484  * Values:
00485  * - 0 - Disable
00486  * - 1 - Enable
00487  */
00488 /*@{*/
00489 #define BP_SDHC_XFERTYP_DMAEN (0U)         /*!< Bit position for SDHC_XFERTYP_DMAEN. */
00490 #define BM_SDHC_XFERTYP_DMAEN (0x00000001U) /*!< Bit mask for SDHC_XFERTYP_DMAEN. */
00491 #define BS_SDHC_XFERTYP_DMAEN (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_DMAEN. */
00492 
00493 /*! @brief Read current value of the SDHC_XFERTYP_DMAEN field. */
00494 #define BR_SDHC_XFERTYP_DMAEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN)))
00495 
00496 /*! @brief Format value for bitfield SDHC_XFERTYP_DMAEN. */
00497 #define BF_SDHC_XFERTYP_DMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DMAEN) & BM_SDHC_XFERTYP_DMAEN)
00498 
00499 /*! @brief Set the DMAEN field to a new value. */
00500 #define BW_SDHC_XFERTYP_DMAEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DMAEN), v))
00501 /*@}*/
00502 
00503 /*!
00504  * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
00505  *
00506  * Used to enable the Block Count register, which is only relevant for multiple
00507  * block transfers. When this bit is 0, the internal counter for block is
00508  * disabled, which is useful in executing an infinite transfer.
00509  *
00510  * Values:
00511  * - 0 - Disable
00512  * - 1 - Enable
00513  */
00514 /*@{*/
00515 #define BP_SDHC_XFERTYP_BCEN (1U)          /*!< Bit position for SDHC_XFERTYP_BCEN. */
00516 #define BM_SDHC_XFERTYP_BCEN (0x00000002U) /*!< Bit mask for SDHC_XFERTYP_BCEN. */
00517 #define BS_SDHC_XFERTYP_BCEN (1U)          /*!< Bit field size in bits for SDHC_XFERTYP_BCEN. */
00518 
00519 /*! @brief Read current value of the SDHC_XFERTYP_BCEN field. */
00520 #define BR_SDHC_XFERTYP_BCEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN)))
00521 
00522 /*! @brief Format value for bitfield SDHC_XFERTYP_BCEN. */
00523 #define BF_SDHC_XFERTYP_BCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_BCEN) & BM_SDHC_XFERTYP_BCEN)
00524 
00525 /*! @brief Set the BCEN field to a new value. */
00526 #define BW_SDHC_XFERTYP_BCEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_BCEN), v))
00527 /*@}*/
00528 
00529 /*!
00530  * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
00531  *
00532  * Multiple block transfers for memory require a CMD12 to stop the transaction.
00533  * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
00534  * last block transfer has completed. The host driver shall not set this bit to
00535  * issue commands that do not require CMD12 to stop a multiple block data
00536  * transfer. In particular, secure commands defined in File Security Specification (see
00537  * reference list) do not require CMD12. In single block transfer, the SDHC will
00538  * ignore this bit whether it is set or not.
00539  *
00540  * Values:
00541  * - 0 - Disable
00542  * - 1 - Enable
00543  */
00544 /*@{*/
00545 #define BP_SDHC_XFERTYP_AC12EN (2U)        /*!< Bit position for SDHC_XFERTYP_AC12EN. */
00546 #define BM_SDHC_XFERTYP_AC12EN (0x00000004U) /*!< Bit mask for SDHC_XFERTYP_AC12EN. */
00547 #define BS_SDHC_XFERTYP_AC12EN (1U)        /*!< Bit field size in bits for SDHC_XFERTYP_AC12EN. */
00548 
00549 /*! @brief Read current value of the SDHC_XFERTYP_AC12EN field. */
00550 #define BR_SDHC_XFERTYP_AC12EN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN)))
00551 
00552 /*! @brief Format value for bitfield SDHC_XFERTYP_AC12EN. */
00553 #define BF_SDHC_XFERTYP_AC12EN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_AC12EN) & BM_SDHC_XFERTYP_AC12EN)
00554 
00555 /*! @brief Set the AC12EN field to a new value. */
00556 #define BW_SDHC_XFERTYP_AC12EN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_AC12EN), v))
00557 /*@}*/
00558 
00559 /*!
00560  * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
00561  *
00562  * Defines the direction of DAT line data transfers. The bit is set to 1 by the
00563  * host driver to transfer data from the SD card to the SDHC and is set to 0 for
00564  * all other commands.
00565  *
00566  * Values:
00567  * - 0 - Write host to card.
00568  * - 1 - Read card to host.
00569  */
00570 /*@{*/
00571 #define BP_SDHC_XFERTYP_DTDSEL (4U)        /*!< Bit position for SDHC_XFERTYP_DTDSEL. */
00572 #define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) /*!< Bit mask for SDHC_XFERTYP_DTDSEL. */
00573 #define BS_SDHC_XFERTYP_DTDSEL (1U)        /*!< Bit field size in bits for SDHC_XFERTYP_DTDSEL. */
00574 
00575 /*! @brief Read current value of the SDHC_XFERTYP_DTDSEL field. */
00576 #define BR_SDHC_XFERTYP_DTDSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL)))
00577 
00578 /*! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL. */
00579 #define BF_SDHC_XFERTYP_DTDSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DTDSEL) & BM_SDHC_XFERTYP_DTDSEL)
00580 
00581 /*! @brief Set the DTDSEL field to a new value. */
00582 #define BW_SDHC_XFERTYP_DTDSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DTDSEL), v))
00583 /*@}*/
00584 
00585 /*!
00586  * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
00587  *
00588  * Enables multiple block DAT line data transfers. For any other commands, this
00589  * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
00590  * count register.
00591  *
00592  * Values:
00593  * - 0 - Single block.
00594  * - 1 - Multiple blocks.
00595  */
00596 /*@{*/
00597 #define BP_SDHC_XFERTYP_MSBSEL (5U)        /*!< Bit position for SDHC_XFERTYP_MSBSEL. */
00598 #define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) /*!< Bit mask for SDHC_XFERTYP_MSBSEL. */
00599 #define BS_SDHC_XFERTYP_MSBSEL (1U)        /*!< Bit field size in bits for SDHC_XFERTYP_MSBSEL. */
00600 
00601 /*! @brief Read current value of the SDHC_XFERTYP_MSBSEL field. */
00602 #define BR_SDHC_XFERTYP_MSBSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL)))
00603 
00604 /*! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL. */
00605 #define BF_SDHC_XFERTYP_MSBSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_MSBSEL) & BM_SDHC_XFERTYP_MSBSEL)
00606 
00607 /*! @brief Set the MSBSEL field to a new value. */
00608 #define BW_SDHC_XFERTYP_MSBSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_MSBSEL), v))
00609 /*@}*/
00610 
00611 /*!
00612  * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
00613  *
00614  * Values:
00615  * - 00 - No response.
00616  * - 01 - Response length 136.
00617  * - 10 - Response length 48.
00618  * - 11 - Response length 48, check busy after response.
00619  */
00620 /*@{*/
00621 #define BP_SDHC_XFERTYP_RSPTYP (16U)       /*!< Bit position for SDHC_XFERTYP_RSPTYP. */
00622 #define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) /*!< Bit mask for SDHC_XFERTYP_RSPTYP. */
00623 #define BS_SDHC_XFERTYP_RSPTYP (2U)        /*!< Bit field size in bits for SDHC_XFERTYP_RSPTYP. */
00624 
00625 /*! @brief Read current value of the SDHC_XFERTYP_RSPTYP field. */
00626 #define BR_SDHC_XFERTYP_RSPTYP(x) (UNION_READ(hw_sdhc_xfertyp_t, HW_SDHC_XFERTYP_ADDR(x), U, B.RSPTYP))
00627 
00628 /*! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP. */
00629 #define BF_SDHC_XFERTYP_RSPTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_RSPTYP) & BM_SDHC_XFERTYP_RSPTYP)
00630 
00631 /*! @brief Set the RSPTYP field to a new value. */
00632 #define BW_SDHC_XFERTYP_RSPTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v)))
00633 /*@}*/
00634 
00635 /*!
00636  * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
00637  *
00638  * If this bit is set to 1, the SDHC shall check the CRC field in the response.
00639  * If an error is detected, it is reported as a Command CRC Error. If this bit is
00640  * set to 0, the CRC field is not checked. The number of bits checked by the CRC
00641  * field value changes according to the length of the response.
00642  *
00643  * Values:
00644  * - 0 - Disable
00645  * - 1 - Enable
00646  */
00647 /*@{*/
00648 #define BP_SDHC_XFERTYP_CCCEN (19U)        /*!< Bit position for SDHC_XFERTYP_CCCEN. */
00649 #define BM_SDHC_XFERTYP_CCCEN (0x00080000U) /*!< Bit mask for SDHC_XFERTYP_CCCEN. */
00650 #define BS_SDHC_XFERTYP_CCCEN (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_CCCEN. */
00651 
00652 /*! @brief Read current value of the SDHC_XFERTYP_CCCEN field. */
00653 #define BR_SDHC_XFERTYP_CCCEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN)))
00654 
00655 /*! @brief Format value for bitfield SDHC_XFERTYP_CCCEN. */
00656 #define BF_SDHC_XFERTYP_CCCEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CCCEN) & BM_SDHC_XFERTYP_CCCEN)
00657 
00658 /*! @brief Set the CCCEN field to a new value. */
00659 #define BW_SDHC_XFERTYP_CCCEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CCCEN), v))
00660 /*@}*/
00661 
00662 /*!
00663  * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
00664  *
00665  * If this bit is set to 1, the SDHC will check the index field in the response
00666  * to see if it has the same value as the command index. If it is not, it is
00667  * reported as a command index error. If this bit is set to 0, the index field is not
00668  * checked.
00669  *
00670  * Values:
00671  * - 0 - Disable
00672  * - 1 - Enable
00673  */
00674 /*@{*/
00675 #define BP_SDHC_XFERTYP_CICEN (20U)        /*!< Bit position for SDHC_XFERTYP_CICEN. */
00676 #define BM_SDHC_XFERTYP_CICEN (0x00100000U) /*!< Bit mask for SDHC_XFERTYP_CICEN. */
00677 #define BS_SDHC_XFERTYP_CICEN (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_CICEN. */
00678 
00679 /*! @brief Read current value of the SDHC_XFERTYP_CICEN field. */
00680 #define BR_SDHC_XFERTYP_CICEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN)))
00681 
00682 /*! @brief Format value for bitfield SDHC_XFERTYP_CICEN. */
00683 #define BF_SDHC_XFERTYP_CICEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CICEN) & BM_SDHC_XFERTYP_CICEN)
00684 
00685 /*! @brief Set the CICEN field to a new value. */
00686 #define BW_SDHC_XFERTYP_CICEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_CICEN), v))
00687 /*@}*/
00688 
00689 /*!
00690  * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
00691  *
00692  * This bit is set to 1 to indicate that data is present and shall be
00693  * transferred using the DAT line. It is set to 0 for the following: Commands using only
00694  * the CMD line, for example: CMD52. Commands with no data transfer, but using the
00695  * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
00696  * this bit shall be set, and other bits in this register shall be set the same
00697  * as when the transfer was initially launched. When the Write Protect switch is
00698  * on, that is, the WPSPL bit is active as 0, any command with a write operation
00699  * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
00700  * 0, writes to the register Transfer Type are ignored.
00701  *
00702  * Values:
00703  * - 0 - No data present.
00704  * - 1 - Data present.
00705  */
00706 /*@{*/
00707 #define BP_SDHC_XFERTYP_DPSEL (21U)        /*!< Bit position for SDHC_XFERTYP_DPSEL. */
00708 #define BM_SDHC_XFERTYP_DPSEL (0x00200000U) /*!< Bit mask for SDHC_XFERTYP_DPSEL. */
00709 #define BS_SDHC_XFERTYP_DPSEL (1U)         /*!< Bit field size in bits for SDHC_XFERTYP_DPSEL. */
00710 
00711 /*! @brief Read current value of the SDHC_XFERTYP_DPSEL field. */
00712 #define BR_SDHC_XFERTYP_DPSEL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL)))
00713 
00714 /*! @brief Format value for bitfield SDHC_XFERTYP_DPSEL. */
00715 #define BF_SDHC_XFERTYP_DPSEL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_DPSEL) & BM_SDHC_XFERTYP_DPSEL)
00716 
00717 /*! @brief Set the DPSEL field to a new value. */
00718 #define BW_SDHC_XFERTYP_DPSEL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_XFERTYP_ADDR(x), BP_SDHC_XFERTYP_DPSEL), v))
00719 /*@}*/
00720 
00721 /*!
00722  * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
00723  *
00724  * There are three types of special commands: suspend, resume, and abort. These
00725  * bits shall be set to 00b for all other commands. Suspend command: If the
00726  * suspend command succeeds, the SDHC shall assume that the card bus has been released
00727  * and that it is possible to issue the next command which uses the DAT line.
00728  * Because the SDHC does not monitor the content of command response, it does not
00729  * know if the suspend command succeeded or not. It is the host driver's
00730  * responsibility to check the status of the suspend command and send another command
00731  * marked as suspend to inform the SDHC that a suspend command was successfully
00732  * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
00733  * transactions and stops checking busy for write transactions. In 4-bit mode,
00734  * the interrupt cycle starts. If the suspend command fails, the SDHC will
00735  * maintain its current state, and the host driver shall restart the transfer by setting
00736  * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
00737  * restoring the registers saved before sending the suspend command and then sends
00738  * the resume command. The SDHC will check for a pending busy state before
00739  * starting write transfers. Abort command: If this command is set when executing a
00740  * read transfer, the SDHC will stop reads to the buffer. If this command is set
00741  * when executing a write transfer, the SDHC will stop driving the DAT line. After
00742  * issuing the abort command, the host driver must issue a software reset (abort
00743  * transaction).
00744  *
00745  * Values:
00746  * - 00 - Normal other commands.
00747  * - 01 - Suspend CMD52 for writing bus suspend in CCCR.
00748  * - 10 - Resume CMD52 for writing function select in CCCR.
00749  * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
00750  */
00751 /*@{*/
00752 #define BP_SDHC_XFERTYP_CMDTYP (22U)       /*!< Bit position for SDHC_XFERTYP_CMDTYP. */
00753 #define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) /*!< Bit mask for SDHC_XFERTYP_CMDTYP. */
00754 #define BS_SDHC_XFERTYP_CMDTYP (2U)        /*!< Bit field size in bits for SDHC_XFERTYP_CMDTYP. */
00755 
00756 /*! @brief Read current value of the SDHC_XFERTYP_CMDTYP field. */
00757 #define BR_SDHC_XFERTYP_CMDTYP(x) (UNION_READ(hw_sdhc_xfertyp_t, HW_SDHC_XFERTYP_ADDR(x), U, B.CMDTYP))
00758 
00759 /*! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP. */
00760 #define BF_SDHC_XFERTYP_CMDTYP(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDTYP) & BM_SDHC_XFERTYP_CMDTYP)
00761 
00762 /*! @brief Set the CMDTYP field to a new value. */
00763 #define BW_SDHC_XFERTYP_CMDTYP(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v)))
00764 /*@}*/
00765 
00766 /*!
00767  * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
00768  *
00769  * These bits shall be set to the command number that is specified in bits 45-40
00770  * of the command-format in the SD Memory Card Physical Layer Specification and
00771  * SDIO Card Specification.
00772  */
00773 /*@{*/
00774 #define BP_SDHC_XFERTYP_CMDINX (24U)       /*!< Bit position for SDHC_XFERTYP_CMDINX. */
00775 #define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) /*!< Bit mask for SDHC_XFERTYP_CMDINX. */
00776 #define BS_SDHC_XFERTYP_CMDINX (6U)        /*!< Bit field size in bits for SDHC_XFERTYP_CMDINX. */
00777 
00778 /*! @brief Read current value of the SDHC_XFERTYP_CMDINX field. */
00779 #define BR_SDHC_XFERTYP_CMDINX(x) (UNION_READ(hw_sdhc_xfertyp_t, HW_SDHC_XFERTYP_ADDR(x), U, B.CMDINX))
00780 
00781 /*! @brief Format value for bitfield SDHC_XFERTYP_CMDINX. */
00782 #define BF_SDHC_XFERTYP_CMDINX(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_XFERTYP_CMDINX) & BM_SDHC_XFERTYP_CMDINX)
00783 
00784 /*! @brief Set the CMDINX field to a new value. */
00785 #define BW_SDHC_XFERTYP_CMDINX(x, v) (HW_SDHC_XFERTYP_WR(x, (HW_SDHC_XFERTYP_RD(x) & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v)))
00786 /*@}*/
00787 
00788 /*******************************************************************************
00789  * HW_SDHC_CMDRSP0 - Command Response 0
00790  ******************************************************************************/
00791 
00792 /*!
00793  * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO)
00794  *
00795  * Reset value: 0x00000000U
00796  *
00797  * This register is used to store part 0 of the response bits from the card.
00798  */
00799 typedef union _hw_sdhc_cmdrsp0
00800 {
00801     uint32_t U;
00802     struct _hw_sdhc_cmdrsp0_bitfields
00803     {
00804         uint32_t CMDRSP0 : 32;         /*!< [31:0] Command Response 0 */
00805     } B;
00806 } hw_sdhc_cmdrsp0_t;
00807 
00808 /*!
00809  * @name Constants and macros for entire SDHC_CMDRSP0 register
00810  */
00811 /*@{*/
00812 #define HW_SDHC_CMDRSP0_ADDR(x)  ((x) + 0x10U)
00813 
00814 #define HW_SDHC_CMDRSP0(x)       (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR(x))
00815 #define HW_SDHC_CMDRSP0_RD(x)    (ADDRESS_READ(hw_sdhc_cmdrsp0_t, HW_SDHC_CMDRSP0_ADDR(x)))
00816 /*@}*/
00817 
00818 /*
00819  * Constants & macros for individual SDHC_CMDRSP0 bitfields
00820  */
00821 
00822 /*!
00823  * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO)
00824  */
00825 /*@{*/
00826 #define BP_SDHC_CMDRSP0_CMDRSP0 (0U)       /*!< Bit position for SDHC_CMDRSP0_CMDRSP0. */
00827 #define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP0_CMDRSP0. */
00828 #define BS_SDHC_CMDRSP0_CMDRSP0 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0. */
00829 
00830 /*! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field. */
00831 #define BR_SDHC_CMDRSP0_CMDRSP0(x) (HW_SDHC_CMDRSP0(x).U)
00832 /*@}*/
00833 
00834 /*******************************************************************************
00835  * HW_SDHC_CMDRSP1 - Command Response 1
00836  ******************************************************************************/
00837 
00838 /*!
00839  * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO)
00840  *
00841  * Reset value: 0x00000000U
00842  *
00843  * This register is used to store part 1 of the response bits from the card.
00844  */
00845 typedef union _hw_sdhc_cmdrsp1
00846 {
00847     uint32_t U;
00848     struct _hw_sdhc_cmdrsp1_bitfields
00849     {
00850         uint32_t CMDRSP1 : 32;         /*!< [31:0] Command Response 1 */
00851     } B;
00852 } hw_sdhc_cmdrsp1_t;
00853 
00854 /*!
00855  * @name Constants and macros for entire SDHC_CMDRSP1 register
00856  */
00857 /*@{*/
00858 #define HW_SDHC_CMDRSP1_ADDR(x)  ((x) + 0x14U)
00859 
00860 #define HW_SDHC_CMDRSP1(x)       (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR(x))
00861 #define HW_SDHC_CMDRSP1_RD(x)    (ADDRESS_READ(hw_sdhc_cmdrsp1_t, HW_SDHC_CMDRSP1_ADDR(x)))
00862 /*@}*/
00863 
00864 /*
00865  * Constants & macros for individual SDHC_CMDRSP1 bitfields
00866  */
00867 
00868 /*!
00869  * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO)
00870  */
00871 /*@{*/
00872 #define BP_SDHC_CMDRSP1_CMDRSP1 (0U)       /*!< Bit position for SDHC_CMDRSP1_CMDRSP1. */
00873 #define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP1_CMDRSP1. */
00874 #define BS_SDHC_CMDRSP1_CMDRSP1 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1. */
00875 
00876 /*! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field. */
00877 #define BR_SDHC_CMDRSP1_CMDRSP1(x) (HW_SDHC_CMDRSP1(x).U)
00878 /*@}*/
00879 
00880 /*******************************************************************************
00881  * HW_SDHC_CMDRSP2 - Command Response 2
00882  ******************************************************************************/
00883 
00884 /*!
00885  * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO)
00886  *
00887  * Reset value: 0x00000000U
00888  *
00889  * This register is used to store part 2 of the response bits from the card.
00890  */
00891 typedef union _hw_sdhc_cmdrsp2
00892 {
00893     uint32_t U;
00894     struct _hw_sdhc_cmdrsp2_bitfields
00895     {
00896         uint32_t CMDRSP2 : 32;         /*!< [31:0] Command Response 2 */
00897     } B;
00898 } hw_sdhc_cmdrsp2_t;
00899 
00900 /*!
00901  * @name Constants and macros for entire SDHC_CMDRSP2 register
00902  */
00903 /*@{*/
00904 #define HW_SDHC_CMDRSP2_ADDR(x)  ((x) + 0x18U)
00905 
00906 #define HW_SDHC_CMDRSP2(x)       (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR(x))
00907 #define HW_SDHC_CMDRSP2_RD(x)    (ADDRESS_READ(hw_sdhc_cmdrsp2_t, HW_SDHC_CMDRSP2_ADDR(x)))
00908 /*@}*/
00909 
00910 /*
00911  * Constants & macros for individual SDHC_CMDRSP2 bitfields
00912  */
00913 
00914 /*!
00915  * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO)
00916  */
00917 /*@{*/
00918 #define BP_SDHC_CMDRSP2_CMDRSP2 (0U)       /*!< Bit position for SDHC_CMDRSP2_CMDRSP2. */
00919 #define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP2_CMDRSP2. */
00920 #define BS_SDHC_CMDRSP2_CMDRSP2 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2. */
00921 
00922 /*! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field. */
00923 #define BR_SDHC_CMDRSP2_CMDRSP2(x) (HW_SDHC_CMDRSP2(x).U)
00924 /*@}*/
00925 
00926 /*******************************************************************************
00927  * HW_SDHC_CMDRSP3 - Command Response 3
00928  ******************************************************************************/
00929 
00930 /*!
00931  * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO)
00932  *
00933  * Reset value: 0x00000000U
00934  *
00935  * This register is used to store part 3 of the response bits from the card. The
00936  * following table describes the mapping of command responses from the SD bus to
00937  * command response registers for each response type. In the table, R[ ] refers
00938  * to a bit range within the response data as transmitted on the SD bus. Response
00939  * bit definition for each response type Response type Meaning of response
00940  * Response field Response register R1,R1b (normal response) Card status R[39:8]
00941  * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2
00942  * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2,
00943  * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4
00944  * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response
00945  * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card
00946  * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48
00947  * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0
00948  * register. Responses of type R1b (auto CMD12 responses) have response data bits
00949  * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have
00950  * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3
00951  * registers. To be able to read the response status efficiently, the SDHC stores
00952  * only a part of the response data in the command response registers. This
00953  * enables the host driver to efficiently read 32-bit of response data in one read
00954  * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC,
00955  * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN],
00956  * and generate an error interrupt if any error is detected. The bit range for the
00957  * CRC check depends on the response length. If the response length is 48, the
00958  * SDHC will check R[47:1], and if the response length is 136 the SDHC will check
00959  * R[119:1]. Because the SDHC may have a multiple block data transfer executing
00960  * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response
00961  * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This
00962  * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT
00963  * and vice versa. When the SDHC modifies part of the command response
00964  * registers, as shown in the table above, it preserves the unmodified bits.
00965  */
00966 typedef union _hw_sdhc_cmdrsp3
00967 {
00968     uint32_t U;
00969     struct _hw_sdhc_cmdrsp3_bitfields
00970     {
00971         uint32_t CMDRSP3 : 32;         /*!< [31:0] Command Response 3 */
00972     } B;
00973 } hw_sdhc_cmdrsp3_t;
00974 
00975 /*!
00976  * @name Constants and macros for entire SDHC_CMDRSP3 register
00977  */
00978 /*@{*/
00979 #define HW_SDHC_CMDRSP3_ADDR(x)  ((x) + 0x1CU)
00980 
00981 #define HW_SDHC_CMDRSP3(x)       (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR(x))
00982 #define HW_SDHC_CMDRSP3_RD(x)    (ADDRESS_READ(hw_sdhc_cmdrsp3_t, HW_SDHC_CMDRSP3_ADDR(x)))
00983 /*@}*/
00984 
00985 /*
00986  * Constants & macros for individual SDHC_CMDRSP3 bitfields
00987  */
00988 
00989 /*!
00990  * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO)
00991  */
00992 /*@{*/
00993 #define BP_SDHC_CMDRSP3_CMDRSP3 (0U)       /*!< Bit position for SDHC_CMDRSP3_CMDRSP3. */
00994 #define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) /*!< Bit mask for SDHC_CMDRSP3_CMDRSP3. */
00995 #define BS_SDHC_CMDRSP3_CMDRSP3 (32U)      /*!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3. */
00996 
00997 /*! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field. */
00998 #define BR_SDHC_CMDRSP3_CMDRSP3(x) (HW_SDHC_CMDRSP3(x).U)
00999 /*@}*/
01000 
01001 /*******************************************************************************
01002  * HW_SDHC_DATPORT - Buffer Data Port register
01003  ******************************************************************************/
01004 
01005 /*!
01006  * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW)
01007  *
01008  * Reset value: 0x00000000U
01009  *
01010  * This is a 32-bit data port register used to access the internal buffer and it
01011  * cannot be updated in Idle mode.
01012  */
01013 typedef union _hw_sdhc_datport
01014 {
01015     uint32_t U;
01016     struct _hw_sdhc_datport_bitfields
01017     {
01018         uint32_t DATCONT : 32;         /*!< [31:0] Data Content */
01019     } B;
01020 } hw_sdhc_datport_t;
01021 
01022 /*!
01023  * @name Constants and macros for entire SDHC_DATPORT register
01024  */
01025 /*@{*/
01026 #define HW_SDHC_DATPORT_ADDR(x)  ((x) + 0x20U)
01027 
01028 #define HW_SDHC_DATPORT(x)       (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR(x))
01029 #define HW_SDHC_DATPORT_RD(x)    (ADDRESS_READ(hw_sdhc_datport_t, HW_SDHC_DATPORT_ADDR(x)))
01030 #define HW_SDHC_DATPORT_WR(x, v) (ADDRESS_WRITE(hw_sdhc_datport_t, HW_SDHC_DATPORT_ADDR(x), v))
01031 #define HW_SDHC_DATPORT_SET(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) |  (v)))
01032 #define HW_SDHC_DATPORT_CLR(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) & ~(v)))
01033 #define HW_SDHC_DATPORT_TOG(x, v) (HW_SDHC_DATPORT_WR(x, HW_SDHC_DATPORT_RD(x) ^  (v)))
01034 /*@}*/
01035 
01036 /*
01037  * Constants & macros for individual SDHC_DATPORT bitfields
01038  */
01039 
01040 /*!
01041  * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW)
01042  *
01043  * The Buffer Data Port register is for 32-bit data access by the CPU or the
01044  * external DMA. When the internal DMA is enabled, any write to this register is
01045  * ignored, and any read from this register will always yield 0s.
01046  */
01047 /*@{*/
01048 #define BP_SDHC_DATPORT_DATCONT (0U)       /*!< Bit position for SDHC_DATPORT_DATCONT. */
01049 #define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) /*!< Bit mask for SDHC_DATPORT_DATCONT. */
01050 #define BS_SDHC_DATPORT_DATCONT (32U)      /*!< Bit field size in bits for SDHC_DATPORT_DATCONT. */
01051 
01052 /*! @brief Read current value of the SDHC_DATPORT_DATCONT field. */
01053 #define BR_SDHC_DATPORT_DATCONT(x) (HW_SDHC_DATPORT(x).U)
01054 
01055 /*! @brief Format value for bitfield SDHC_DATPORT_DATCONT. */
01056 #define BF_SDHC_DATPORT_DATCONT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_DATPORT_DATCONT) & BM_SDHC_DATPORT_DATCONT)
01057 
01058 /*! @brief Set the DATCONT field to a new value. */
01059 #define BW_SDHC_DATPORT_DATCONT(x, v) (HW_SDHC_DATPORT_WR(x, v))
01060 /*@}*/
01061 
01062 /*******************************************************************************
01063  * HW_SDHC_PRSSTAT - Present State register
01064  ******************************************************************************/
01065 
01066 /*!
01067  * @brief HW_SDHC_PRSSTAT - Present State register (RO)
01068  *
01069  * Reset value: 0x00000000U
01070  *
01071  * The host driver can get status of the SDHC from this 32-bit read-only
01072  * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
01073  * SDIO) when the DAT lines are busy during a data transfer. These commands can be
01074  * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
01075  * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
01076  * Physical Specification may add other commands to this list in the future.
01077  */
01078 typedef union _hw_sdhc_prsstat
01079 {
01080     uint32_t U;
01081     struct _hw_sdhc_prsstat_bitfields
01082     {
01083         uint32_t CIHB : 1;             /*!< [0] Command Inhibit (CMD) */
01084         uint32_t CDIHB : 1;            /*!< [1] Command Inhibit (DAT) */
01085         uint32_t DLA : 1;              /*!< [2] Data Line Active */
01086         uint32_t SDSTB : 1;            /*!< [3] SD Clock Stable */
01087         uint32_t IPGOFF : 1;           /*!< [4] Bus Clock Gated Off Internally */
01088         uint32_t HCKOFF : 1;           /*!< [5] System Clock Gated Off Internally */
01089         uint32_t PEROFF : 1;           /*!< [6] SDHC clock Gated Off Internally */
01090         uint32_t SDOFF : 1;            /*!< [7] SD Clock Gated Off Internally */
01091         uint32_t WTA : 1;              /*!< [8] Write Transfer Active */
01092         uint32_t RTA : 1;              /*!< [9] Read Transfer Active */
01093         uint32_t BWEN : 1;             /*!< [10] Buffer Write Enable */
01094         uint32_t BREN : 1;             /*!< [11] Buffer Read Enable */
01095         uint32_t RESERVED0 : 4;        /*!< [15:12]  */
01096         uint32_t CINS : 1;             /*!< [16] Card Inserted */
01097         uint32_t RESERVED1 : 6;        /*!< [22:17]  */
01098         uint32_t CLSL : 1;             /*!< [23] CMD Line Signal Level */
01099         uint32_t DLSL : 8;             /*!< [31:24] DAT Line Signal Level */
01100     } B;
01101 } hw_sdhc_prsstat_t;
01102 
01103 /*!
01104  * @name Constants and macros for entire SDHC_PRSSTAT register
01105  */
01106 /*@{*/
01107 #define HW_SDHC_PRSSTAT_ADDR(x)  ((x) + 0x24U)
01108 
01109 #define HW_SDHC_PRSSTAT(x)       (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR(x))
01110 #define HW_SDHC_PRSSTAT_RD(x)    (ADDRESS_READ(hw_sdhc_prsstat_t, HW_SDHC_PRSSTAT_ADDR(x)))
01111 /*@}*/
01112 
01113 /*
01114  * Constants & macros for individual SDHC_PRSSTAT bitfields
01115  */
01116 
01117 /*!
01118  * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
01119  *
01120  * If this status bit is 0, it indicates that the CMD line is not in use and the
01121  * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
01122  * immediately after the Transfer Type register is written. This bit is cleared when
01123  * the command response is received. Even if the CDIHB bit is set to 1, Commands
01124  * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
01125  * generates a command complete interrupt in the interrupt status register. If the
01126  * SDHC cannot issue the command because of a command conflict error (see
01127  * command CRC error) or because of a command not issued by auto CMD12 error, this bit
01128  * will remain 1 and the command complete is not set. The status of issuing an
01129  * auto CMD12 does not show on this bit.
01130  *
01131  * Values:
01132  * - 0 - Can issue command using only CMD line.
01133  * - 1 - Cannot issue command.
01134  */
01135 /*@{*/
01136 #define BP_SDHC_PRSSTAT_CIHB (0U)          /*!< Bit position for SDHC_PRSSTAT_CIHB. */
01137 #define BM_SDHC_PRSSTAT_CIHB (0x00000001U) /*!< Bit mask for SDHC_PRSSTAT_CIHB. */
01138 #define BS_SDHC_PRSSTAT_CIHB (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_CIHB. */
01139 
01140 /*! @brief Read current value of the SDHC_PRSSTAT_CIHB field. */
01141 #define BR_SDHC_PRSSTAT_CIHB(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CIHB)))
01142 /*@}*/
01143 
01144 /*!
01145  * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
01146  *
01147  * This status bit is generated if either the DLA or the RTA is set to 1. If
01148  * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
01149  * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
01150  * the case when the command busy is finished, changing from 1 to 0 generates a
01151  * transfer complete interrupt in the Interrupt Status register. The SD host
01152  * driver can save registers for a suspend transaction after this bit has changed
01153  * from 1 to 0.
01154  *
01155  * Values:
01156  * - 0 - Can issue command which uses the DAT line.
01157  * - 1 - Cannot issue command which uses the DAT line.
01158  */
01159 /*@{*/
01160 #define BP_SDHC_PRSSTAT_CDIHB (1U)         /*!< Bit position for SDHC_PRSSTAT_CDIHB. */
01161 #define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) /*!< Bit mask for SDHC_PRSSTAT_CDIHB. */
01162 #define BS_SDHC_PRSSTAT_CDIHB (1U)         /*!< Bit field size in bits for SDHC_PRSSTAT_CDIHB. */
01163 
01164 /*! @brief Read current value of the SDHC_PRSSTAT_CDIHB field. */
01165 #define BR_SDHC_PRSSTAT_CDIHB(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CDIHB)))
01166 /*@}*/
01167 
01168 /*!
01169  * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
01170  *
01171  * Indicates whether one of the DAT lines on the SD bus is in use. In the case
01172  * of read transactions: This status indicates whether a read transfer is
01173  * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
01174  * generates a block gap event interrupt in the Interrupt Status register. This bit
01175  * will be set in either of the following cases: After the end bit of the read
01176  * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
01177  * will be cleared in either of the following cases: When the end bit of the last
01178  * data block is sent from the SD bus to the SDHC. When the read wait state is
01179  * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
01180  * the next block gap by driving read wait at the start of the interrupt cycle.
01181  * If the read wait signal is already driven (data buffer cannot receive data),
01182  * the SDHC can wait for a current block gap by continuing to drive the read wait
01183  * signal. It is necessary to support read wait to use the suspend / resume
01184  * function. This bit will remain 1 during read wait. In the case of write
01185  * transactions: This status indicates that a write transfer is executing on the SD bus.
01186  * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
01187  * interrupt status register. This bit will be set in either of the following
01188  * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
01189  * continue a write transfer. This bit will be cleared in either of the
01190  * following cases: When the SD card releases write busy of the last data block, the SDHC
01191  * will also detect if the output is not busy. If the SD card does not drive the
01192  * busy signal after the CRC status is received, the SDHC shall assume the card
01193  * drive "Not busy". When the SD card releases write busy, prior to waiting for
01194  * write transfer, and as a result of a stop at block gap request. In the case of
01195  * command with busy pending: This status indicates that a busy state follows the
01196  * command and the data line is in use. This bit will be cleared when the DAT0
01197  * line is released.
01198  *
01199  * Values:
01200  * - 0 - DAT line inactive.
01201  * - 1 - DAT line active.
01202  */
01203 /*@{*/
01204 #define BP_SDHC_PRSSTAT_DLA  (2U)          /*!< Bit position for SDHC_PRSSTAT_DLA. */
01205 #define BM_SDHC_PRSSTAT_DLA  (0x00000004U) /*!< Bit mask for SDHC_PRSSTAT_DLA. */
01206 #define BS_SDHC_PRSSTAT_DLA  (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_DLA. */
01207 
01208 /*! @brief Read current value of the SDHC_PRSSTAT_DLA field. */
01209 #define BR_SDHC_PRSSTAT_DLA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_DLA)))
01210 /*@}*/
01211 
01212 /*!
01213  * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
01214  *
01215  * Indicates that the internal card clock is stable. This bit is for the host
01216  * driver to poll clock status when changing the clock frequency. It is recommended
01217  * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
01218  * frequency is changing.
01219  *
01220  * Values:
01221  * - 0 - Clock is changing frequency and not stable.
01222  * - 1 - Clock is stable.
01223  */
01224 /*@{*/
01225 #define BP_SDHC_PRSSTAT_SDSTB (3U)         /*!< Bit position for SDHC_PRSSTAT_SDSTB. */
01226 #define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) /*!< Bit mask for SDHC_PRSSTAT_SDSTB. */
01227 #define BS_SDHC_PRSSTAT_SDSTB (1U)         /*!< Bit field size in bits for SDHC_PRSSTAT_SDSTB. */
01228 
01229 /*! @brief Read current value of the SDHC_PRSSTAT_SDSTB field. */
01230 #define BR_SDHC_PRSSTAT_SDSTB(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDSTB)))
01231 /*@}*/
01232 
01233 /*!
01234  * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
01235  *
01236  * Indicates that the bus clock is internally gated off. This bit is for the
01237  * host driver to debug.
01238  *
01239  * Values:
01240  * - 0 - Bus clock is active.
01241  * - 1 - Bus clock is gated off.
01242  */
01243 /*@{*/
01244 #define BP_SDHC_PRSSTAT_IPGOFF (4U)        /*!< Bit position for SDHC_PRSSTAT_IPGOFF. */
01245 #define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) /*!< Bit mask for SDHC_PRSSTAT_IPGOFF. */
01246 #define BS_SDHC_PRSSTAT_IPGOFF (1U)        /*!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF. */
01247 
01248 /*! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field. */
01249 #define BR_SDHC_PRSSTAT_IPGOFF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_IPGOFF)))
01250 /*@}*/
01251 
01252 /*!
01253  * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
01254  *
01255  * Indicates that the system clock is internally gated off. This bit is for the
01256  * host driver to debug during a data transfer.
01257  *
01258  * Values:
01259  * - 0 - System clock is active.
01260  * - 1 - System clock is gated off.
01261  */
01262 /*@{*/
01263 #define BP_SDHC_PRSSTAT_HCKOFF (5U)        /*!< Bit position for SDHC_PRSSTAT_HCKOFF. */
01264 #define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) /*!< Bit mask for SDHC_PRSSTAT_HCKOFF. */
01265 #define BS_SDHC_PRSSTAT_HCKOFF (1U)        /*!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF. */
01266 
01267 /*! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field. */
01268 #define BR_SDHC_PRSSTAT_HCKOFF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_HCKOFF)))
01269 /*@}*/
01270 
01271 /*!
01272  * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
01273  *
01274  * Indicates that the is internally gated off. This bit is for the host driver
01275  * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
01276  * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
01277  * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
01278  * clock SDHC clock bus clock
01279  *
01280  * Values:
01281  * - 0 - SDHC clock is active.
01282  * - 1 - SDHC clock is gated off.
01283  */
01284 /*@{*/
01285 #define BP_SDHC_PRSSTAT_PEROFF (6U)        /*!< Bit position for SDHC_PRSSTAT_PEROFF. */
01286 #define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) /*!< Bit mask for SDHC_PRSSTAT_PEROFF. */
01287 #define BS_SDHC_PRSSTAT_PEROFF (1U)        /*!< Bit field size in bits for SDHC_PRSSTAT_PEROFF. */
01288 
01289 /*! @brief Read current value of the SDHC_PRSSTAT_PEROFF field. */
01290 #define BR_SDHC_PRSSTAT_PEROFF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_PEROFF)))
01291 /*@}*/
01292 
01293 /*!
01294  * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
01295  *
01296  * Indicates that the SD clock is internally gated off, because of buffer
01297  * over/under-run or read pause without read wait assertion, or the driver has cleared
01298  * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
01299  * data transaction on the SD bus.
01300  *
01301  * Values:
01302  * - 0 - SD clock is active.
01303  * - 1 - SD clock is gated off.
01304  */
01305 /*@{*/
01306 #define BP_SDHC_PRSSTAT_SDOFF (7U)         /*!< Bit position for SDHC_PRSSTAT_SDOFF. */
01307 #define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) /*!< Bit mask for SDHC_PRSSTAT_SDOFF. */
01308 #define BS_SDHC_PRSSTAT_SDOFF (1U)         /*!< Bit field size in bits for SDHC_PRSSTAT_SDOFF. */
01309 
01310 /*! @brief Read current value of the SDHC_PRSSTAT_SDOFF field. */
01311 #define BR_SDHC_PRSSTAT_SDOFF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_SDOFF)))
01312 /*@}*/
01313 
01314 /*!
01315  * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
01316  *
01317  * Indicates that a write transfer is active. If this bit is 0, it means no
01318  * valid write data exists in the SDHC. This bit is set in either of the following
01319  * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
01320  * restart a write transfer. This bit is cleared in either of the following
01321  * cases: After getting the CRC status of the last data block as specified by the
01322  * transfer count (single and multiple). After getting the CRC status of any block
01323  * where data transmission is about to be stopped by a stop at block gap request.
01324  * During a write transaction, a block gap event interrupt is generated when this
01325  * bit is changed to 0, as result of the stop at block gap request being set.
01326  * This status is useful for the host driver in determining when to issue commands
01327  * during write busy state.
01328  *
01329  * Values:
01330  * - 0 - No valid data.
01331  * - 1 - Transferring data.
01332  */
01333 /*@{*/
01334 #define BP_SDHC_PRSSTAT_WTA  (8U)          /*!< Bit position for SDHC_PRSSTAT_WTA. */
01335 #define BM_SDHC_PRSSTAT_WTA  (0x00000100U) /*!< Bit mask for SDHC_PRSSTAT_WTA. */
01336 #define BS_SDHC_PRSSTAT_WTA  (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_WTA. */
01337 
01338 /*! @brief Read current value of the SDHC_PRSSTAT_WTA field. */
01339 #define BR_SDHC_PRSSTAT_WTA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_WTA)))
01340 /*@}*/
01341 
01342 /*!
01343  * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
01344  *
01345  * Used for detecting completion of a read transfer. This bit is set for either
01346  * of the following conditions: After the end bit of the read command. When
01347  * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
01348  * interrupt is generated when this bit changes to 0. This bit is cleared for either of
01349  * the following conditions: When the last data block as specified by block
01350  * length is transferred to the system, that is, all data are read away from SDHC
01351  * internal buffer. When all valid data blocks have been transferred from SDHC
01352  * internal buffer to the system and no current block transfers are being sent as a
01353  * result of the stop at block gap request being set to 1.
01354  *
01355  * Values:
01356  * - 0 - No valid data.
01357  * - 1 - Transferring data.
01358  */
01359 /*@{*/
01360 #define BP_SDHC_PRSSTAT_RTA  (9U)          /*!< Bit position for SDHC_PRSSTAT_RTA. */
01361 #define BM_SDHC_PRSSTAT_RTA  (0x00000200U) /*!< Bit mask for SDHC_PRSSTAT_RTA. */
01362 #define BS_SDHC_PRSSTAT_RTA  (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_RTA. */
01363 
01364 /*! @brief Read current value of the SDHC_PRSSTAT_RTA field. */
01365 #define BR_SDHC_PRSSTAT_RTA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_RTA)))
01366 /*@}*/
01367 
01368 /*!
01369  * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
01370  *
01371  * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
01372  * transfer data efficiently. This read-only flag indicates whether space is
01373  * available for write data. If this bit is 1, valid data greater than the watermark
01374  * level can be written to the buffer. This read-only flag indicates whether
01375  * space is available for write data.
01376  *
01377  * Values:
01378  * - 0 - Write disable, the buffer can hold valid data less than the write
01379  *     watermark level.
01380  * - 1 - Write enable, the buffer can hold valid data greater than the write
01381  *     watermark level.
01382  */
01383 /*@{*/
01384 #define BP_SDHC_PRSSTAT_BWEN (10U)         /*!< Bit position for SDHC_PRSSTAT_BWEN. */
01385 #define BM_SDHC_PRSSTAT_BWEN (0x00000400U) /*!< Bit mask for SDHC_PRSSTAT_BWEN. */
01386 #define BS_SDHC_PRSSTAT_BWEN (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_BWEN. */
01387 
01388 /*! @brief Read current value of the SDHC_PRSSTAT_BWEN field. */
01389 #define BR_SDHC_PRSSTAT_BWEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BWEN)))
01390 /*@}*/
01391 
01392 /*!
01393  * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
01394  *
01395  * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
01396  * transfer data efficiently. This read-only flag indicates that valid data exists
01397  * in the host side buffer. If this bit is high, valid data greater than the
01398  * watermark level exist in the buffer. This read-only flag indicates that valid
01399  * data exists in the host side buffer.
01400  *
01401  * Values:
01402  * - 0 - Read disable, valid data less than the watermark level exist in the
01403  *     buffer.
01404  * - 1 - Read enable, valid data greater than the watermark level exist in the
01405  *     buffer.
01406  */
01407 /*@{*/
01408 #define BP_SDHC_PRSSTAT_BREN (11U)         /*!< Bit position for SDHC_PRSSTAT_BREN. */
01409 #define BM_SDHC_PRSSTAT_BREN (0x00000800U) /*!< Bit mask for SDHC_PRSSTAT_BREN. */
01410 #define BS_SDHC_PRSSTAT_BREN (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_BREN. */
01411 
01412 /*! @brief Read current value of the SDHC_PRSSTAT_BREN field. */
01413 #define BR_SDHC_PRSSTAT_BREN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_BREN)))
01414 /*@}*/
01415 
01416 /*!
01417  * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
01418  *
01419  * Indicates whether a card has been inserted. The SDHC debounces this signal so
01420  * that the host driver will not need to wait for it to stabilize. Changing from
01421  * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
01422  * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
01423  * Status register. A write to the force event register does not effect this bit.
01424  * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
01425  * bit.
01426  *
01427  * Values:
01428  * - 0 - Power on reset or no card.
01429  * - 1 - Card inserted.
01430  */
01431 /*@{*/
01432 #define BP_SDHC_PRSSTAT_CINS (16U)         /*!< Bit position for SDHC_PRSSTAT_CINS. */
01433 #define BM_SDHC_PRSSTAT_CINS (0x00010000U) /*!< Bit mask for SDHC_PRSSTAT_CINS. */
01434 #define BS_SDHC_PRSSTAT_CINS (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_CINS. */
01435 
01436 /*! @brief Read current value of the SDHC_PRSSTAT_CINS field. */
01437 #define BR_SDHC_PRSSTAT_CINS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CINS)))
01438 /*@}*/
01439 
01440 /*!
01441  * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
01442  *
01443  * Used to check the CMD line level to recover from errors, and for debugging.
01444  * The reset value is effected by the external pullup/pulldown resistor, by
01445  * default, the read value of this bit after reset is 1b, when the command line is
01446  * pulled up.
01447  */
01448 /*@{*/
01449 #define BP_SDHC_PRSSTAT_CLSL (23U)         /*!< Bit position for SDHC_PRSSTAT_CLSL. */
01450 #define BM_SDHC_PRSSTAT_CLSL (0x00800000U) /*!< Bit mask for SDHC_PRSSTAT_CLSL. */
01451 #define BS_SDHC_PRSSTAT_CLSL (1U)          /*!< Bit field size in bits for SDHC_PRSSTAT_CLSL. */
01452 
01453 /*! @brief Read current value of the SDHC_PRSSTAT_CLSL field. */
01454 #define BR_SDHC_PRSSTAT_CLSL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PRSSTAT_ADDR(x), BP_SDHC_PRSSTAT_CLSL)))
01455 /*@}*/
01456 
01457 /*!
01458  * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
01459  *
01460  * Used to check the DAT line level to recover from errors, and for debugging.
01461  * This is especially useful in detecting the busy signal level from DAT[0]. The
01462  * reset value is effected by the external pullup/pulldown resistors. By default,
01463  * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
01464  * down and the other lines are pulled up.
01465  */
01466 /*@{*/
01467 #define BP_SDHC_PRSSTAT_DLSL (24U)         /*!< Bit position for SDHC_PRSSTAT_DLSL. */
01468 #define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) /*!< Bit mask for SDHC_PRSSTAT_DLSL. */
01469 #define BS_SDHC_PRSSTAT_DLSL (8U)          /*!< Bit field size in bits for SDHC_PRSSTAT_DLSL. */
01470 
01471 /*! @brief Read current value of the SDHC_PRSSTAT_DLSL field. */
01472 #define BR_SDHC_PRSSTAT_DLSL(x) (UNION_READ(hw_sdhc_prsstat_t, HW_SDHC_PRSSTAT_ADDR(x), U, B.DLSL))
01473 /*@}*/
01474 
01475 /*******************************************************************************
01476  * HW_SDHC_PROCTL - Protocol Control register
01477  ******************************************************************************/
01478 
01479 /*!
01480  * @brief HW_SDHC_PROCTL - Protocol Control register (RW)
01481  *
01482  * Reset value: 0x00000020U
01483  *
01484  * There are three cases to restart the transfer after stop at the block gap.
01485  * Which case is appropriate depends on whether the SDHC issues a suspend command
01486  * or the SD card accepts the suspend command: If the host driver does not issue a
01487  * suspend command, the continue request shall be used to restart the transfer.
01488  * If the host driver issues a suspend command and the SD card accepts it, a
01489  * resume command shall be used to restart the transfer. If the host driver issues a
01490  * suspend command and the SD card does not accept it, the continue request shall
01491  * be used to restart the transfer. Any time stop at block gap request stops the
01492  * data transfer, the host driver shall wait for a transfer complete (in the
01493  * interrupt status register), before attempting to restart the transfer. When
01494  * restarting the data transfer by continue request, the host driver shall clear the
01495  * stop at block gap request before or simultaneously.
01496  */
01497 typedef union _hw_sdhc_proctl
01498 {
01499     uint32_t U;
01500     struct _hw_sdhc_proctl_bitfields
01501     {
01502         uint32_t LCTL : 1;             /*!< [0] LED Control */
01503         uint32_t DTW : 2;              /*!< [2:1] Data Transfer Width */
01504         uint32_t D3CD : 1;             /*!< [3] DAT3 As Card Detection Pin */
01505         uint32_t EMODE : 2;            /*!< [5:4] Endian Mode */
01506         uint32_t CDTL : 1;             /*!< [6] Card Detect Test Level */
01507         uint32_t CDSS : 1;             /*!< [7] Card Detect Signal Selection */
01508         uint32_t DMAS : 2;             /*!< [9:8] DMA Select */
01509         uint32_t RESERVED0 : 6;        /*!< [15:10]  */
01510         uint32_t SABGREQ : 1;          /*!< [16] Stop At Block Gap Request */
01511         uint32_t CREQ : 1;             /*!< [17] Continue Request */
01512         uint32_t RWCTL : 1;            /*!< [18] Read Wait Control */
01513         uint32_t IABG : 1;             /*!< [19] Interrupt At Block Gap */
01514         uint32_t RESERVED1 : 4;        /*!< [23:20]  */
01515         uint32_t WECINT : 1;           /*!< [24] Wakeup Event Enable On Card Interrupt
01516                                         * */
01517         uint32_t WECINS : 1;           /*!< [25] Wakeup Event Enable On SD Card
01518                                         * Insertion */
01519         uint32_t WECRM : 1;            /*!< [26] Wakeup Event Enable On SD Card Removal
01520                                         * */
01521         uint32_t RESERVED2 : 5;        /*!< [31:27]  */
01522     } B;
01523 } hw_sdhc_proctl_t;
01524 
01525 /*!
01526  * @name Constants and macros for entire SDHC_PROCTL register
01527  */
01528 /*@{*/
01529 #define HW_SDHC_PROCTL_ADDR(x)   ((x) + 0x28U)
01530 
01531 #define HW_SDHC_PROCTL(x)        (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR(x))
01532 #define HW_SDHC_PROCTL_RD(x)     (ADDRESS_READ(hw_sdhc_proctl_t, HW_SDHC_PROCTL_ADDR(x)))
01533 #define HW_SDHC_PROCTL_WR(x, v)  (ADDRESS_WRITE(hw_sdhc_proctl_t, HW_SDHC_PROCTL_ADDR(x), v))
01534 #define HW_SDHC_PROCTL_SET(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) |  (v)))
01535 #define HW_SDHC_PROCTL_CLR(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) & ~(v)))
01536 #define HW_SDHC_PROCTL_TOG(x, v) (HW_SDHC_PROCTL_WR(x, HW_SDHC_PROCTL_RD(x) ^  (v)))
01537 /*@}*/
01538 
01539 /*
01540  * Constants & macros for individual SDHC_PROCTL bitfields
01541  */
01542 
01543 /*!
01544  * @name Register SDHC_PROCTL, field LCTL[0] (RW)
01545  *
01546  * This bit, fully controlled by the host driver, is used to caution the user
01547  * not to remove the card while the card is being accessed. If the software is
01548  * going to issue multiple SD commands, this bit can be set during all these
01549  * transactions. It is not necessary to change for each transaction. When the software
01550  * issues multiple SD commands, setting the bit once before the first command is
01551  * sufficient: it is not necessary to reset the bit between commands.
01552  *
01553  * Values:
01554  * - 0 - LED off.
01555  * - 1 - LED on.
01556  */
01557 /*@{*/
01558 #define BP_SDHC_PROCTL_LCTL  (0U)          /*!< Bit position for SDHC_PROCTL_LCTL. */
01559 #define BM_SDHC_PROCTL_LCTL  (0x00000001U) /*!< Bit mask for SDHC_PROCTL_LCTL. */
01560 #define BS_SDHC_PROCTL_LCTL  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_LCTL. */
01561 
01562 /*! @brief Read current value of the SDHC_PROCTL_LCTL field. */
01563 #define BR_SDHC_PROCTL_LCTL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL)))
01564 
01565 /*! @brief Format value for bitfield SDHC_PROCTL_LCTL. */
01566 #define BF_SDHC_PROCTL_LCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_LCTL) & BM_SDHC_PROCTL_LCTL)
01567 
01568 /*! @brief Set the LCTL field to a new value. */
01569 #define BW_SDHC_PROCTL_LCTL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_LCTL), v))
01570 /*@}*/
01571 
01572 /*!
01573  * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
01574  *
01575  * Selects the data width of the SD bus for a data transfer. The host driver
01576  * shall set it to match the data width of the card. Possible data transfer width is
01577  * 1-bit, 4-bits or 8-bits.
01578  *
01579  * Values:
01580  * - 00 - 1-bit mode
01581  * - 01 - 4-bit mode
01582  * - 10 - 8-bit mode
01583  * - 11 - Reserved
01584  */
01585 /*@{*/
01586 #define BP_SDHC_PROCTL_DTW   (1U)          /*!< Bit position for SDHC_PROCTL_DTW. */
01587 #define BM_SDHC_PROCTL_DTW   (0x00000006U) /*!< Bit mask for SDHC_PROCTL_DTW. */
01588 #define BS_SDHC_PROCTL_DTW   (2U)          /*!< Bit field size in bits for SDHC_PROCTL_DTW. */
01589 
01590 /*! @brief Read current value of the SDHC_PROCTL_DTW field. */
01591 #define BR_SDHC_PROCTL_DTW(x) (UNION_READ(hw_sdhc_proctl_t, HW_SDHC_PROCTL_ADDR(x), U, B.DTW))
01592 
01593 /*! @brief Format value for bitfield SDHC_PROCTL_DTW. */
01594 #define BF_SDHC_PROCTL_DTW(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DTW) & BM_SDHC_PROCTL_DTW)
01595 
01596 /*! @brief Set the DTW field to a new value. */
01597 #define BW_SDHC_PROCTL_DTW(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v)))
01598 /*@}*/
01599 
01600 /*!
01601  * @name Register SDHC_PROCTL, field D3CD[3] (RW)
01602  *
01603  * If this bit is set, DAT3 should be pulled down to act as a card detection
01604  * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
01605  * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
01606  * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
01607  * is used.
01608  *
01609  * Values:
01610  * - 0 - DAT3 does not monitor card Insertion.
01611  * - 1 - DAT3 as card detection pin.
01612  */
01613 /*@{*/
01614 #define BP_SDHC_PROCTL_D3CD  (3U)          /*!< Bit position for SDHC_PROCTL_D3CD. */
01615 #define BM_SDHC_PROCTL_D3CD  (0x00000008U) /*!< Bit mask for SDHC_PROCTL_D3CD. */
01616 #define BS_SDHC_PROCTL_D3CD  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_D3CD. */
01617 
01618 /*! @brief Read current value of the SDHC_PROCTL_D3CD field. */
01619 #define BR_SDHC_PROCTL_D3CD(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD)))
01620 
01621 /*! @brief Format value for bitfield SDHC_PROCTL_D3CD. */
01622 #define BF_SDHC_PROCTL_D3CD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_D3CD) & BM_SDHC_PROCTL_D3CD)
01623 
01624 /*! @brief Set the D3CD field to a new value. */
01625 #define BW_SDHC_PROCTL_D3CD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_D3CD), v))
01626 /*@}*/
01627 
01628 /*!
01629  * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
01630  *
01631  * The SDHC supports all four endian modes in data transfer.
01632  *
01633  * Values:
01634  * - 00 - Big endian mode
01635  * - 01 - Half word big endian mode
01636  * - 10 - Little endian mode
01637  * - 11 - Reserved
01638  */
01639 /*@{*/
01640 #define BP_SDHC_PROCTL_EMODE (4U)          /*!< Bit position for SDHC_PROCTL_EMODE. */
01641 #define BM_SDHC_PROCTL_EMODE (0x00000030U) /*!< Bit mask for SDHC_PROCTL_EMODE. */
01642 #define BS_SDHC_PROCTL_EMODE (2U)          /*!< Bit field size in bits for SDHC_PROCTL_EMODE. */
01643 
01644 /*! @brief Read current value of the SDHC_PROCTL_EMODE field. */
01645 #define BR_SDHC_PROCTL_EMODE(x) (UNION_READ(hw_sdhc_proctl_t, HW_SDHC_PROCTL_ADDR(x), U, B.EMODE))
01646 
01647 /*! @brief Format value for bitfield SDHC_PROCTL_EMODE. */
01648 #define BF_SDHC_PROCTL_EMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_EMODE) & BM_SDHC_PROCTL_EMODE)
01649 
01650 /*! @brief Set the EMODE field to a new value. */
01651 #define BW_SDHC_PROCTL_EMODE(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v)))
01652 /*@}*/
01653 
01654 /*!
01655  * @name Register SDHC_PROCTL, field CDTL[6] (RW)
01656  *
01657  * Enabled while the CDSS is set to 1 and it indicates card insertion.
01658  *
01659  * Values:
01660  * - 0 - Card detect test level is 0, no card inserted.
01661  * - 1 - Card detect test level is 1, card inserted.
01662  */
01663 /*@{*/
01664 #define BP_SDHC_PROCTL_CDTL  (6U)          /*!< Bit position for SDHC_PROCTL_CDTL. */
01665 #define BM_SDHC_PROCTL_CDTL  (0x00000040U) /*!< Bit mask for SDHC_PROCTL_CDTL. */
01666 #define BS_SDHC_PROCTL_CDTL  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_CDTL. */
01667 
01668 /*! @brief Read current value of the SDHC_PROCTL_CDTL field. */
01669 #define BR_SDHC_PROCTL_CDTL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL)))
01670 
01671 /*! @brief Format value for bitfield SDHC_PROCTL_CDTL. */
01672 #define BF_SDHC_PROCTL_CDTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDTL) & BM_SDHC_PROCTL_CDTL)
01673 
01674 /*! @brief Set the CDTL field to a new value. */
01675 #define BW_SDHC_PROCTL_CDTL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDTL), v))
01676 /*@}*/
01677 
01678 /*!
01679  * @name Register SDHC_PROCTL, field CDSS[7] (RW)
01680  *
01681  * Selects the source for the card detection.
01682  *
01683  * Values:
01684  * - 0 - Card detection level is selected for normal purpose.
01685  * - 1 - Card detection test level is selected for test purpose.
01686  */
01687 /*@{*/
01688 #define BP_SDHC_PROCTL_CDSS  (7U)          /*!< Bit position for SDHC_PROCTL_CDSS. */
01689 #define BM_SDHC_PROCTL_CDSS  (0x00000080U) /*!< Bit mask for SDHC_PROCTL_CDSS. */
01690 #define BS_SDHC_PROCTL_CDSS  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_CDSS. */
01691 
01692 /*! @brief Read current value of the SDHC_PROCTL_CDSS field. */
01693 #define BR_SDHC_PROCTL_CDSS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS)))
01694 
01695 /*! @brief Format value for bitfield SDHC_PROCTL_CDSS. */
01696 #define BF_SDHC_PROCTL_CDSS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CDSS) & BM_SDHC_PROCTL_CDSS)
01697 
01698 /*! @brief Set the CDSS field to a new value. */
01699 #define BW_SDHC_PROCTL_CDSS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CDSS), v))
01700 /*@}*/
01701 
01702 /*!
01703  * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
01704  *
01705  * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
01706  * operation.
01707  *
01708  * Values:
01709  * - 00 - No DMA or simple DMA is selected.
01710  * - 01 - ADMA1 is selected.
01711  * - 10 - ADMA2 is selected.
01712  * - 11 - Reserved
01713  */
01714 /*@{*/
01715 #define BP_SDHC_PROCTL_DMAS  (8U)          /*!< Bit position for SDHC_PROCTL_DMAS. */
01716 #define BM_SDHC_PROCTL_DMAS  (0x00000300U) /*!< Bit mask for SDHC_PROCTL_DMAS. */
01717 #define BS_SDHC_PROCTL_DMAS  (2U)          /*!< Bit field size in bits for SDHC_PROCTL_DMAS. */
01718 
01719 /*! @brief Read current value of the SDHC_PROCTL_DMAS field. */
01720 #define BR_SDHC_PROCTL_DMAS(x) (UNION_READ(hw_sdhc_proctl_t, HW_SDHC_PROCTL_ADDR(x), U, B.DMAS))
01721 
01722 /*! @brief Format value for bitfield SDHC_PROCTL_DMAS. */
01723 #define BF_SDHC_PROCTL_DMAS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_DMAS) & BM_SDHC_PROCTL_DMAS)
01724 
01725 /*! @brief Set the DMAS field to a new value. */
01726 #define BW_SDHC_PROCTL_DMAS(x, v) (HW_SDHC_PROCTL_WR(x, (HW_SDHC_PROCTL_RD(x) & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v)))
01727 /*@}*/
01728 
01729 /*!
01730  * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
01731  *
01732  * Used to stop executing a transaction at the next block gap for both DMA and
01733  * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
01734  * transfer completion, the host driver shall leave this bit set to 1. Clearing both
01735  * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
01736  * Wait is used to stop the read transaction at the block gap. The SDHC will
01737  * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
01738  * that SDIO card support read wait. Therefore, the host driver shall not set
01739  * this bit during read transfers unless the SDIO card supports read wait and has
01740  * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
01741  * the read operation during block gap. In the case of write transfers in which
01742  * the host driver writes data to the data port register, the host driver shall set
01743  * this bit after all block data is written. If this bit is set to 1, the host
01744  * driver shall not write data to the Data Port register after a block is sent.
01745  * Once this bit is set, the host driver shall not clear this bit before
01746  * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
01747  * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
01748  *
01749  * Values:
01750  * - 0 - Transfer
01751  * - 1 - Stop
01752  */
01753 /*@{*/
01754 #define BP_SDHC_PROCTL_SABGREQ (16U)       /*!< Bit position for SDHC_PROCTL_SABGREQ. */
01755 #define BM_SDHC_PROCTL_SABGREQ (0x00010000U) /*!< Bit mask for SDHC_PROCTL_SABGREQ. */
01756 #define BS_SDHC_PROCTL_SABGREQ (1U)        /*!< Bit field size in bits for SDHC_PROCTL_SABGREQ. */
01757 
01758 /*! @brief Read current value of the SDHC_PROCTL_SABGREQ field. */
01759 #define BR_SDHC_PROCTL_SABGREQ(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ)))
01760 
01761 /*! @brief Format value for bitfield SDHC_PROCTL_SABGREQ. */
01762 #define BF_SDHC_PROCTL_SABGREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_SABGREQ) & BM_SDHC_PROCTL_SABGREQ)
01763 
01764 /*! @brief Set the SABGREQ field to a new value. */
01765 #define BW_SDHC_PROCTL_SABGREQ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_SABGREQ), v))
01766 /*@}*/
01767 
01768 /*!
01769  * @name Register SDHC_PROCTL, field CREQ[17] (RW)
01770  *
01771  * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
01772  * When a suspend operation is not accepted by the card, it is also by setting this
01773  * bit to restart the paused transfer. To cancel stop at the block gap, set
01774  * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
01775  * automatically clears this bit, therefore it is not necessary for the host driver to
01776  * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
01777  * request is ignored.
01778  *
01779  * Values:
01780  * - 0 - No effect.
01781  * - 1 - Restart
01782  */
01783 /*@{*/
01784 #define BP_SDHC_PROCTL_CREQ  (17U)         /*!< Bit position for SDHC_PROCTL_CREQ. */
01785 #define BM_SDHC_PROCTL_CREQ  (0x00020000U) /*!< Bit mask for SDHC_PROCTL_CREQ. */
01786 #define BS_SDHC_PROCTL_CREQ  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_CREQ. */
01787 
01788 /*! @brief Read current value of the SDHC_PROCTL_CREQ field. */
01789 #define BR_SDHC_PROCTL_CREQ(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ)))
01790 
01791 /*! @brief Format value for bitfield SDHC_PROCTL_CREQ. */
01792 #define BF_SDHC_PROCTL_CREQ(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_CREQ) & BM_SDHC_PROCTL_CREQ)
01793 
01794 /*! @brief Set the CREQ field to a new value. */
01795 #define BW_SDHC_PROCTL_CREQ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_CREQ), v))
01796 /*@}*/
01797 
01798 /*!
01799  * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
01800  *
01801  * The read wait function is optional for SDIO cards. If the card supports read
01802  * wait, set this bit to enable use of the read wait protocol to stop read data
01803  * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
01804  * read data, which restricts commands generation. When the host driver detects an
01805  * SDIO card insertion, it shall set this bit according to the CCCR of the card.
01806  * If the card does not support read wait, this bit shall never be set to 1,
01807  * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
01808  * during read operation is also supported, but the SDHC will stop the SD Clock
01809  * to pause reading operation.
01810  *
01811  * Values:
01812  * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ
01813  *     is set.
01814  * - 1 - Enable read wait control, and assert read wait without stopping SD
01815  *     clock at block gap when SABGREQ bit is set.
01816  */
01817 /*@{*/
01818 #define BP_SDHC_PROCTL_RWCTL (18U)         /*!< Bit position for SDHC_PROCTL_RWCTL. */
01819 #define BM_SDHC_PROCTL_RWCTL (0x00040000U) /*!< Bit mask for SDHC_PROCTL_RWCTL. */
01820 #define BS_SDHC_PROCTL_RWCTL (1U)          /*!< Bit field size in bits for SDHC_PROCTL_RWCTL. */
01821 
01822 /*! @brief Read current value of the SDHC_PROCTL_RWCTL field. */
01823 #define BR_SDHC_PROCTL_RWCTL(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL)))
01824 
01825 /*! @brief Format value for bitfield SDHC_PROCTL_RWCTL. */
01826 #define BF_SDHC_PROCTL_RWCTL(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_RWCTL) & BM_SDHC_PROCTL_RWCTL)
01827 
01828 /*! @brief Set the RWCTL field to a new value. */
01829 #define BW_SDHC_PROCTL_RWCTL(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_RWCTL), v))
01830 /*@}*/
01831 
01832 /*!
01833  * @name Register SDHC_PROCTL, field IABG[19] (RW)
01834  *
01835  * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
01836  * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
01837  * for a multiple block transfer. Setting to 0 disables interrupt detection during
01838  * a multiple block transfer. If the SDIO card can't signal an interrupt during a
01839  * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
01840  * interrupt. When the host driver detects an SDIO card insertion, it shall set
01841  * this bit according to the CCCR of the card.
01842  *
01843  * Values:
01844  * - 0 - Disabled
01845  * - 1 - Enabled
01846  */
01847 /*@{*/
01848 #define BP_SDHC_PROCTL_IABG  (19U)         /*!< Bit position for SDHC_PROCTL_IABG. */
01849 #define BM_SDHC_PROCTL_IABG  (0x00080000U) /*!< Bit mask for SDHC_PROCTL_IABG. */
01850 #define BS_SDHC_PROCTL_IABG  (1U)          /*!< Bit field size in bits for SDHC_PROCTL_IABG. */
01851 
01852 /*! @brief Read current value of the SDHC_PROCTL_IABG field. */
01853 #define BR_SDHC_PROCTL_IABG(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG)))
01854 
01855 /*! @brief Format value for bitfield SDHC_PROCTL_IABG. */
01856 #define BF_SDHC_PROCTL_IABG(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_IABG) & BM_SDHC_PROCTL_IABG)
01857 
01858 /*! @brief Set the IABG field to a new value. */
01859 #define BW_SDHC_PROCTL_IABG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_IABG), v))
01860 /*@}*/
01861 
01862 /*!
01863  * @name Register SDHC_PROCTL, field WECINT[24] (RW)
01864  *
01865  * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
01866  * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
01867  * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
01868  * the wakeup feature is not enabled, the SD_CLK must be active to assert the
01869  * card interrupt status and the SDHC interrupt.
01870  *
01871  * Values:
01872  * - 0 - Disabled
01873  * - 1 - Enabled
01874  */
01875 /*@{*/
01876 #define BP_SDHC_PROCTL_WECINT (24U)        /*!< Bit position for SDHC_PROCTL_WECINT. */
01877 #define BM_SDHC_PROCTL_WECINT (0x01000000U) /*!< Bit mask for SDHC_PROCTL_WECINT. */
01878 #define BS_SDHC_PROCTL_WECINT (1U)         /*!< Bit field size in bits for SDHC_PROCTL_WECINT. */
01879 
01880 /*! @brief Read current value of the SDHC_PROCTL_WECINT field. */
01881 #define BR_SDHC_PROCTL_WECINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT)))
01882 
01883 /*! @brief Format value for bitfield SDHC_PROCTL_WECINT. */
01884 #define BF_SDHC_PROCTL_WECINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINT) & BM_SDHC_PROCTL_WECINT)
01885 
01886 /*! @brief Set the WECINT field to a new value. */
01887 #define BW_SDHC_PROCTL_WECINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINT), v))
01888 /*@}*/
01889 
01890 /*!
01891  * @name Register SDHC_PROCTL, field WECINS[25] (RW)
01892  *
01893  * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
01894  * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
01895  * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
01896  * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
01897  * interrupt.
01898  *
01899  * Values:
01900  * - 0 - Disabled
01901  * - 1 - Enabled
01902  */
01903 /*@{*/
01904 #define BP_SDHC_PROCTL_WECINS (25U)        /*!< Bit position for SDHC_PROCTL_WECINS. */
01905 #define BM_SDHC_PROCTL_WECINS (0x02000000U) /*!< Bit mask for SDHC_PROCTL_WECINS. */
01906 #define BS_SDHC_PROCTL_WECINS (1U)         /*!< Bit field size in bits for SDHC_PROCTL_WECINS. */
01907 
01908 /*! @brief Read current value of the SDHC_PROCTL_WECINS field. */
01909 #define BR_SDHC_PROCTL_WECINS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS)))
01910 
01911 /*! @brief Format value for bitfield SDHC_PROCTL_WECINS. */
01912 #define BF_SDHC_PROCTL_WECINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECINS) & BM_SDHC_PROCTL_WECINS)
01913 
01914 /*! @brief Set the WECINS field to a new value. */
01915 #define BW_SDHC_PROCTL_WECINS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECINS), v))
01916 /*@}*/
01917 
01918 /*!
01919  * @name Register SDHC_PROCTL, field WECRM[26] (RW)
01920  *
01921  * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
01922  * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
01923  * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
01924  * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
01925  *
01926  * Values:
01927  * - 0 - Disabled
01928  * - 1 - Enabled
01929  */
01930 /*@{*/
01931 #define BP_SDHC_PROCTL_WECRM (26U)         /*!< Bit position for SDHC_PROCTL_WECRM. */
01932 #define BM_SDHC_PROCTL_WECRM (0x04000000U) /*!< Bit mask for SDHC_PROCTL_WECRM. */
01933 #define BS_SDHC_PROCTL_WECRM (1U)          /*!< Bit field size in bits for SDHC_PROCTL_WECRM. */
01934 
01935 /*! @brief Read current value of the SDHC_PROCTL_WECRM field. */
01936 #define BR_SDHC_PROCTL_WECRM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM)))
01937 
01938 /*! @brief Format value for bitfield SDHC_PROCTL_WECRM. */
01939 #define BF_SDHC_PROCTL_WECRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_PROCTL_WECRM) & BM_SDHC_PROCTL_WECRM)
01940 
01941 /*! @brief Set the WECRM field to a new value. */
01942 #define BW_SDHC_PROCTL_WECRM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_PROCTL_ADDR(x), BP_SDHC_PROCTL_WECRM), v))
01943 /*@}*/
01944 
01945 /*******************************************************************************
01946  * HW_SDHC_SYSCTL - System Control register
01947  ******************************************************************************/
01948 
01949 /*!
01950  * @brief HW_SDHC_SYSCTL - System Control register (RW)
01951  *
01952  * Reset value: 0x00008008U
01953  */
01954 typedef union _hw_sdhc_sysctl
01955 {
01956     uint32_t U;
01957     struct _hw_sdhc_sysctl_bitfields
01958     {
01959         uint32_t IPGEN : 1;            /*!< [0] IPG Clock Enable */
01960         uint32_t HCKEN : 1;            /*!< [1] System Clock Enable */
01961         uint32_t PEREN : 1;            /*!< [2] Peripheral Clock Enable */
01962         uint32_t SDCLKEN : 1;          /*!< [3] SD Clock Enable */
01963         uint32_t DVS : 4;              /*!< [7:4] Divisor */
01964         uint32_t SDCLKFS : 8;          /*!< [15:8] SDCLK Frequency Select */
01965         uint32_t DTOCV : 4;            /*!< [19:16] Data Timeout Counter Value */
01966         uint32_t RESERVED0 : 4;        /*!< [23:20]  */
01967         uint32_t RSTA : 1;             /*!< [24] Software Reset For ALL */
01968         uint32_t RSTC : 1;             /*!< [25] Software Reset For CMD Line */
01969         uint32_t RSTD : 1;             /*!< [26] Software Reset For DAT Line */
01970         uint32_t INITA : 1;            /*!< [27] Initialization Active */
01971         uint32_t RESERVED1 : 4;        /*!< [31:28]  */
01972     } B;
01973 } hw_sdhc_sysctl_t;
01974 
01975 /*!
01976  * @name Constants and macros for entire SDHC_SYSCTL register
01977  */
01978 /*@{*/
01979 #define HW_SDHC_SYSCTL_ADDR(x)   ((x) + 0x2CU)
01980 
01981 #define HW_SDHC_SYSCTL(x)        (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR(x))
01982 #define HW_SDHC_SYSCTL_RD(x)     (ADDRESS_READ(hw_sdhc_sysctl_t, HW_SDHC_SYSCTL_ADDR(x)))
01983 #define HW_SDHC_SYSCTL_WR(x, v)  (ADDRESS_WRITE(hw_sdhc_sysctl_t, HW_SDHC_SYSCTL_ADDR(x), v))
01984 #define HW_SDHC_SYSCTL_SET(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) |  (v)))
01985 #define HW_SDHC_SYSCTL_CLR(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) & ~(v)))
01986 #define HW_SDHC_SYSCTL_TOG(x, v) (HW_SDHC_SYSCTL_WR(x, HW_SDHC_SYSCTL_RD(x) ^  (v)))
01987 /*@}*/
01988 
01989 /*
01990  * Constants & macros for individual SDHC_SYSCTL bitfields
01991  */
01992 
01993 /*!
01994  * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
01995  *
01996  * If this bit is set, bus clock will always be active and no automatic gating
01997  * is applied. The bus clock will be internally gated off, if none of the
01998  * following factors are met: The cmd part is reset, or Data part is reset, or Soft
01999  * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
02000  * request is just set, or This bit is set, or Card insertion is detected, or Card
02001  * removal is detected, or Card external interrupt is detected, or The SDHC
02002  * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
02003  * is not gated off. So clearing only this bit has no effect unless the PEREN bit
02004  * is also cleared.
02005  *
02006  * Values:
02007  * - 0 - Bus clock will be internally gated off.
02008  * - 1 - Bus clock will not be automatically gated off.
02009  */
02010 /*@{*/
02011 #define BP_SDHC_SYSCTL_IPGEN (0U)          /*!< Bit position for SDHC_SYSCTL_IPGEN. */
02012 #define BM_SDHC_SYSCTL_IPGEN (0x00000001U) /*!< Bit mask for SDHC_SYSCTL_IPGEN. */
02013 #define BS_SDHC_SYSCTL_IPGEN (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_IPGEN. */
02014 
02015 /*! @brief Read current value of the SDHC_SYSCTL_IPGEN field. */
02016 #define BR_SDHC_SYSCTL_IPGEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN)))
02017 
02018 /*! @brief Format value for bitfield SDHC_SYSCTL_IPGEN. */
02019 #define BF_SDHC_SYSCTL_IPGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_IPGEN) & BM_SDHC_SYSCTL_IPGEN)
02020 
02021 /*! @brief Set the IPGEN field to a new value. */
02022 #define BW_SDHC_SYSCTL_IPGEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_IPGEN), v))
02023 /*@}*/
02024 
02025 /*!
02026  * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
02027  *
02028  * If this bit is set, system clock will always be active and no automatic
02029  * gating is applied. When this bit is cleared, system clock will be automatically off
02030  * when no data transfer is on the SD bus.
02031  *
02032  * Values:
02033  * - 0 - System clock will be internally gated off.
02034  * - 1 - System clock will not be automatically gated off.
02035  */
02036 /*@{*/
02037 #define BP_SDHC_SYSCTL_HCKEN (1U)          /*!< Bit position for SDHC_SYSCTL_HCKEN. */
02038 #define BM_SDHC_SYSCTL_HCKEN (0x00000002U) /*!< Bit mask for SDHC_SYSCTL_HCKEN. */
02039 #define BS_SDHC_SYSCTL_HCKEN (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_HCKEN. */
02040 
02041 /*! @brief Read current value of the SDHC_SYSCTL_HCKEN field. */
02042 #define BR_SDHC_SYSCTL_HCKEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN)))
02043 
02044 /*! @brief Format value for bitfield SDHC_SYSCTL_HCKEN. */
02045 #define BF_SDHC_SYSCTL_HCKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_HCKEN) & BM_SDHC_SYSCTL_HCKEN)
02046 
02047 /*! @brief Set the HCKEN field to a new value. */
02048 #define BW_SDHC_SYSCTL_HCKEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_HCKEN), v))
02049 /*@}*/
02050 
02051 /*!
02052  * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
02053  *
02054  * If this bit is set, SDHC clock will always be active and no automatic gating
02055  * is applied. Thus the SDCLK is active except for when auto gating-off during
02056  * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
02057  * the SDHC clock will be automatically off whenever there is no transaction on
02058  * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
02059  * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
02060  * if none of the following factors are met: The cmd part is reset, or Data part
02061  * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
02062  * just updated, or Continue request is just set, or This bit is set, or Card
02063  * insertion is detected, or Card removal is detected, or Card external interrupt is
02064  * detected, or 80 clocks for initialization phase is ongoing
02065  *
02066  * Values:
02067  * - 0 - SDHC clock will be internally gated off.
02068  * - 1 - SDHC clock will not be automatically gated off.
02069  */
02070 /*@{*/
02071 #define BP_SDHC_SYSCTL_PEREN (2U)          /*!< Bit position for SDHC_SYSCTL_PEREN. */
02072 #define BM_SDHC_SYSCTL_PEREN (0x00000004U) /*!< Bit mask for SDHC_SYSCTL_PEREN. */
02073 #define BS_SDHC_SYSCTL_PEREN (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_PEREN. */
02074 
02075 /*! @brief Read current value of the SDHC_SYSCTL_PEREN field. */
02076 #define BR_SDHC_SYSCTL_PEREN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN)))
02077 
02078 /*! @brief Format value for bitfield SDHC_SYSCTL_PEREN. */
02079 #define BF_SDHC_SYSCTL_PEREN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_PEREN) & BM_SDHC_SYSCTL_PEREN)
02080 
02081 /*! @brief Set the PEREN field to a new value. */
02082 #define BW_SDHC_SYSCTL_PEREN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_PEREN), v))
02083 /*@}*/
02084 
02085 /*!
02086  * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
02087  *
02088  * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
02089  * frequency can be changed when this bit is 0. Then, the host controller shall
02090  * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
02091  * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
02092  * power.
02093  */
02094 /*@{*/
02095 #define BP_SDHC_SYSCTL_SDCLKEN (3U)        /*!< Bit position for SDHC_SYSCTL_SDCLKEN. */
02096 #define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) /*!< Bit mask for SDHC_SYSCTL_SDCLKEN. */
02097 #define BS_SDHC_SYSCTL_SDCLKEN (1U)        /*!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN. */
02098 
02099 /*! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field. */
02100 #define BR_SDHC_SYSCTL_SDCLKEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN)))
02101 
02102 /*! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN. */
02103 #define BF_SDHC_SYSCTL_SDCLKEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKEN) & BM_SDHC_SYSCTL_SDCLKEN)
02104 
02105 /*! @brief Set the SDCLKEN field to a new value. */
02106 #define BW_SDHC_SYSCTL_SDCLKEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_SDCLKEN), v))
02107 /*@}*/
02108 
02109 /*!
02110  * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
02111  *
02112  * Used to provide a more exact divisor to generate the desired SD clock
02113  * frequency. Note the divider can even support odd divisor without deterioration of
02114  * duty cycle. The setting are as following:
02115  *
02116  * Values:
02117  * - 0 - Divisor by 1.
02118  * - 1 - Divisor by 2.
02119  * - 1110 - Divisor by 15.
02120  * - 1111 - Divisor by 16.
02121  */
02122 /*@{*/
02123 #define BP_SDHC_SYSCTL_DVS   (4U)          /*!< Bit position for SDHC_SYSCTL_DVS. */
02124 #define BM_SDHC_SYSCTL_DVS   (0x000000F0U) /*!< Bit mask for SDHC_SYSCTL_DVS. */
02125 #define BS_SDHC_SYSCTL_DVS   (4U)          /*!< Bit field size in bits for SDHC_SYSCTL_DVS. */
02126 
02127 /*! @brief Read current value of the SDHC_SYSCTL_DVS field. */
02128 #define BR_SDHC_SYSCTL_DVS(x) (UNION_READ(hw_sdhc_sysctl_t, HW_SDHC_SYSCTL_ADDR(x), U, B.DVS))
02129 
02130 /*! @brief Format value for bitfield SDHC_SYSCTL_DVS. */
02131 #define BF_SDHC_SYSCTL_DVS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DVS) & BM_SDHC_SYSCTL_DVS)
02132 
02133 /*! @brief Set the DVS field to a new value. */
02134 #define BW_SDHC_SYSCTL_DVS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v)))
02135 /*@}*/
02136 
02137 /*!
02138  * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
02139  *
02140  * Used to select the frequency of the SDCLK pin. The frequency is not
02141  * programmed directly. Rather this register holds the prescaler (this register) and
02142  * divisor (next register) of the base clock frequency register. Setting 00h bypasses
02143  * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
02144  * behavior of this prescaler is undefined. The two default divider values can
02145  * be calculated by the frequency of SDHC clock and the following divisor bits.
02146  * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
02147  * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
02148  * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
02149  * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
02150  * less than or equal to the target. Similarly, to approach a clock value of 400
02151  * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
02152  * value of 400 kHz. The reset value of this field is 80h, so if the input base
02153  * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
02154  * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
02155  * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
02156  * never exceed this limit. Only the following settings are allowed:
02157  *
02158  * Values:
02159  * - 1 - Base clock divided by 2.
02160  * - 10 - Base clock divided by 4.
02161  * - 100 - Base clock divided by 8.
02162  * - 1000 - Base clock divided by 16.
02163  * - 10000 - Base clock divided by 32.
02164  * - 100000 - Base clock divided by 64.
02165  * - 1000000 - Base clock divided by 128.
02166  * - 10000000 - Base clock divided by 256.
02167  */
02168 /*@{*/
02169 #define BP_SDHC_SYSCTL_SDCLKFS (8U)        /*!< Bit position for SDHC_SYSCTL_SDCLKFS. */
02170 #define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) /*!< Bit mask for SDHC_SYSCTL_SDCLKFS. */
02171 #define BS_SDHC_SYSCTL_SDCLKFS (8U)        /*!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS. */
02172 
02173 /*! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field. */
02174 #define BR_SDHC_SYSCTL_SDCLKFS(x) (UNION_READ(hw_sdhc_sysctl_t, HW_SDHC_SYSCTL_ADDR(x), U, B.SDCLKFS))
02175 
02176 /*! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS. */
02177 #define BF_SDHC_SYSCTL_SDCLKFS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_SDCLKFS) & BM_SDHC_SYSCTL_SDCLKFS)
02178 
02179 /*! @brief Set the SDCLKFS field to a new value. */
02180 #define BW_SDHC_SYSCTL_SDCLKFS(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v)))
02181 /*@}*/
02182 
02183 /*!
02184  * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
02185  *
02186  * Determines the interval by which DAT line timeouts are detected. See
02187  * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
02188  * clock frequency will be generated by dividing the base clock SDCLK value by this
02189  * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
02190  * time-out events.
02191  *
02192  * Values:
02193  * - 0000 - SDCLK x 2 13
02194  * - 0001 - SDCLK x 2 14
02195  * - 1110 - SDCLK x 2 27
02196  * - 1111 - Reserved
02197  */
02198 /*@{*/
02199 #define BP_SDHC_SYSCTL_DTOCV (16U)         /*!< Bit position for SDHC_SYSCTL_DTOCV. */
02200 #define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) /*!< Bit mask for SDHC_SYSCTL_DTOCV. */
02201 #define BS_SDHC_SYSCTL_DTOCV (4U)          /*!< Bit field size in bits for SDHC_SYSCTL_DTOCV. */
02202 
02203 /*! @brief Read current value of the SDHC_SYSCTL_DTOCV field. */
02204 #define BR_SDHC_SYSCTL_DTOCV(x) (UNION_READ(hw_sdhc_sysctl_t, HW_SDHC_SYSCTL_ADDR(x), U, B.DTOCV))
02205 
02206 /*! @brief Format value for bitfield SDHC_SYSCTL_DTOCV. */
02207 #define BF_SDHC_SYSCTL_DTOCV(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_DTOCV) & BM_SDHC_SYSCTL_DTOCV)
02208 
02209 /*! @brief Set the DTOCV field to a new value. */
02210 #define BW_SDHC_SYSCTL_DTOCV(x, v) (HW_SDHC_SYSCTL_WR(x, (HW_SDHC_SYSCTL_RD(x) & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v)))
02211 /*@}*/
02212 
02213 /*!
02214  * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
02215  *
02216  * Effects the entire host controller except for the card detection circuit.
02217  * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
02218  * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
02219  * reset this bit to 0 when the capabilities registers are valid and the host driver
02220  * can read them. Additional use of software reset for all does not affect the
02221  * value of the capabilities registers. After this bit is set, it is recommended
02222  * that the host driver reset the external card and reinitialize it.
02223  *
02224  * Values:
02225  * - 0 - No reset.
02226  * - 1 - Reset.
02227  */
02228 /*@{*/
02229 #define BP_SDHC_SYSCTL_RSTA  (24U)         /*!< Bit position for SDHC_SYSCTL_RSTA. */
02230 #define BM_SDHC_SYSCTL_RSTA  (0x01000000U) /*!< Bit mask for SDHC_SYSCTL_RSTA. */
02231 #define BS_SDHC_SYSCTL_RSTA  (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_RSTA. */
02232 
02233 /*! @brief Format value for bitfield SDHC_SYSCTL_RSTA. */
02234 #define BF_SDHC_SYSCTL_RSTA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTA) & BM_SDHC_SYSCTL_RSTA)
02235 
02236 /*! @brief Set the RSTA field to a new value. */
02237 #define BW_SDHC_SYSCTL_RSTA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTA), v))
02238 /*@}*/
02239 
02240 /*!
02241  * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
02242  *
02243  * Only part of the command circuit is reset. The following registers and bits
02244  * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
02245  *
02246  * Values:
02247  * - 0 - No reset.
02248  * - 1 - Reset.
02249  */
02250 /*@{*/
02251 #define BP_SDHC_SYSCTL_RSTC  (25U)         /*!< Bit position for SDHC_SYSCTL_RSTC. */
02252 #define BM_SDHC_SYSCTL_RSTC  (0x02000000U) /*!< Bit mask for SDHC_SYSCTL_RSTC. */
02253 #define BS_SDHC_SYSCTL_RSTC  (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_RSTC. */
02254 
02255 /*! @brief Format value for bitfield SDHC_SYSCTL_RSTC. */
02256 #define BF_SDHC_SYSCTL_RSTC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTC) & BM_SDHC_SYSCTL_RSTC)
02257 
02258 /*! @brief Set the RSTC field to a new value. */
02259 #define BW_SDHC_SYSCTL_RSTC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTC), v))
02260 /*@}*/
02261 
02262 /*!
02263  * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
02264  *
02265  * Only part of the data circuit is reset. DMA circuit is also reset. The
02266  * following registers and bits are cleared by this bit: Data Port register Buffer Is
02267  * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
02268  * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
02269  * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
02270  * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
02271  * Block Gap Event Transfer Complete
02272  *
02273  * Values:
02274  * - 0 - No reset.
02275  * - 1 - Reset.
02276  */
02277 /*@{*/
02278 #define BP_SDHC_SYSCTL_RSTD  (26U)         /*!< Bit position for SDHC_SYSCTL_RSTD. */
02279 #define BM_SDHC_SYSCTL_RSTD  (0x04000000U) /*!< Bit mask for SDHC_SYSCTL_RSTD. */
02280 #define BS_SDHC_SYSCTL_RSTD  (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_RSTD. */
02281 
02282 /*! @brief Format value for bitfield SDHC_SYSCTL_RSTD. */
02283 #define BF_SDHC_SYSCTL_RSTD(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_RSTD) & BM_SDHC_SYSCTL_RSTD)
02284 
02285 /*! @brief Set the RSTD field to a new value. */
02286 #define BW_SDHC_SYSCTL_RSTD(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_RSTD), v))
02287 /*@}*/
02288 
02289 /*!
02290  * @name Register SDHC_SYSCTL, field INITA[27] (RW)
02291  *
02292  * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
02293  * are sent, this bit is self-cleared. This bit is very useful during the card
02294  * power-up period when 74 SD-clocks are needed and the clock auto gating feature
02295  * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
02296  * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
02297  * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
02298  * when command line or data lines are active, write to this bit is not allowed.
02299  * On the otherhand, when this bit is set, that is, during intialization active
02300  * period, it is allowed to issue command, and the command bit stream will appear
02301  * on the CMD pad after all 80 clock cycles are done. So when this command ends,
02302  * the driver can make sure the 80 clock cycles are sent out. This is very useful
02303  * when the driver needs send 80 cycles to the card and does not want to wait
02304  * till this bit is self-cleared.
02305  */
02306 /*@{*/
02307 #define BP_SDHC_SYSCTL_INITA (27U)         /*!< Bit position for SDHC_SYSCTL_INITA. */
02308 #define BM_SDHC_SYSCTL_INITA (0x08000000U) /*!< Bit mask for SDHC_SYSCTL_INITA. */
02309 #define BS_SDHC_SYSCTL_INITA (1U)          /*!< Bit field size in bits for SDHC_SYSCTL_INITA. */
02310 
02311 /*! @brief Read current value of the SDHC_SYSCTL_INITA field. */
02312 #define BR_SDHC_SYSCTL_INITA(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA)))
02313 
02314 /*! @brief Format value for bitfield SDHC_SYSCTL_INITA. */
02315 #define BF_SDHC_SYSCTL_INITA(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_SYSCTL_INITA) & BM_SDHC_SYSCTL_INITA)
02316 
02317 /*! @brief Set the INITA field to a new value. */
02318 #define BW_SDHC_SYSCTL_INITA(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_SYSCTL_ADDR(x), BP_SDHC_SYSCTL_INITA), v))
02319 /*@}*/
02320 
02321 /*******************************************************************************
02322  * HW_SDHC_IRQSTAT - Interrupt Status register
02323  ******************************************************************************/
02324 
02325 /*!
02326  * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW)
02327  *
02328  * Reset value: 0x00000000U
02329  *
02330  * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
02331  * and at least one of the status bits is set to 1. For all bits, writing 1 to a
02332  * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
02333  * be cleared with a single register write. For Card Interrupt, before writing 1
02334  * to clear, it is required that the card stops asserting the interrupt, meaning
02335  * that when the Card Driver services the interrupt condition, otherwise the CINT
02336  * bit will be asserted again. The table below shows the relationship between
02337  * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
02338  * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
02339  * received within 64 SDCLK cycles 1 0 Response received The table below shows the
02340  * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
02341  * for data timeout error/transfer complete bit combinations Transfer complete
02342  * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
02343  * transfer 1 X Data transfer complete The table below shows the relationship between
02344  * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
02345  * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
02346  * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
02347  * CMD line conflict
02348  */
02349 typedef union _hw_sdhc_irqstat
02350 {
02351     uint32_t U;
02352     struct _hw_sdhc_irqstat_bitfields
02353     {
02354         uint32_t CC : 1;               /*!< [0] Command Complete */
02355         uint32_t TC : 1;               /*!< [1] Transfer Complete */
02356         uint32_t BGE : 1;              /*!< [2] Block Gap Event */
02357         uint32_t DINT : 1;             /*!< [3] DMA Interrupt */
02358         uint32_t BWR : 1;              /*!< [4] Buffer Write Ready */
02359         uint32_t BRR : 1;              /*!< [5] Buffer Read Ready */
02360         uint32_t CINS : 1;             /*!< [6] Card Insertion */
02361         uint32_t CRM : 1;              /*!< [7] Card Removal */
02362         uint32_t CINT : 1;             /*!< [8] Card Interrupt */
02363         uint32_t RESERVED0 : 7;        /*!< [15:9]  */
02364         uint32_t CTOE : 1;             /*!< [16] Command Timeout Error */
02365         uint32_t CCE : 1;              /*!< [17] Command CRC Error */
02366         uint32_t CEBE : 1;             /*!< [18] Command End Bit Error */
02367         uint32_t CIE : 1;              /*!< [19] Command Index Error */
02368         uint32_t DTOE : 1;             /*!< [20] Data Timeout Error */
02369         uint32_t DCE : 1;              /*!< [21] Data CRC Error */
02370         uint32_t DEBE : 1;             /*!< [22] Data End Bit Error */
02371         uint32_t RESERVED1 : 1;        /*!< [23]  */
02372         uint32_t AC12E : 1;            /*!< [24] Auto CMD12 Error */
02373         uint32_t RESERVED2 : 3;        /*!< [27:25]  */
02374         uint32_t DMAE : 1;             /*!< [28] DMA Error */
02375         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
02376     } B;
02377 } hw_sdhc_irqstat_t;
02378 
02379 /*!
02380  * @name Constants and macros for entire SDHC_IRQSTAT register
02381  */
02382 /*@{*/
02383 #define HW_SDHC_IRQSTAT_ADDR(x)  ((x) + 0x30U)
02384 
02385 #define HW_SDHC_IRQSTAT(x)       (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR(x))
02386 #define HW_SDHC_IRQSTAT_RD(x)    (ADDRESS_READ(hw_sdhc_irqstat_t, HW_SDHC_IRQSTAT_ADDR(x)))
02387 #define HW_SDHC_IRQSTAT_WR(x, v) (ADDRESS_WRITE(hw_sdhc_irqstat_t, HW_SDHC_IRQSTAT_ADDR(x), v))
02388 #define HW_SDHC_IRQSTAT_SET(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) |  (v)))
02389 #define HW_SDHC_IRQSTAT_CLR(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) & ~(v)))
02390 #define HW_SDHC_IRQSTAT_TOG(x, v) (HW_SDHC_IRQSTAT_WR(x, HW_SDHC_IRQSTAT_RD(x) ^  (v)))
02391 /*@}*/
02392 
02393 /*
02394  * Constants & macros for individual SDHC_IRQSTAT bitfields
02395  */
02396 
02397 /*!
02398  * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
02399  *
02400  * This bit is set when you receive the end bit of the command response, except
02401  * Auto CMD12. See PRSSTAT[CIHB].
02402  *
02403  * Values:
02404  * - 0 - Command not complete.
02405  * - 1 - Command complete.
02406  */
02407 /*@{*/
02408 #define BP_SDHC_IRQSTAT_CC   (0U)          /*!< Bit position for SDHC_IRQSTAT_CC. */
02409 #define BM_SDHC_IRQSTAT_CC   (0x00000001U) /*!< Bit mask for SDHC_IRQSTAT_CC. */
02410 #define BS_SDHC_IRQSTAT_CC   (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CC. */
02411 
02412 /*! @brief Read current value of the SDHC_IRQSTAT_CC field. */
02413 #define BR_SDHC_IRQSTAT_CC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC)))
02414 
02415 /*! @brief Format value for bitfield SDHC_IRQSTAT_CC. */
02416 #define BF_SDHC_IRQSTAT_CC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CC) & BM_SDHC_IRQSTAT_CC)
02417 
02418 /*! @brief Set the CC field to a new value. */
02419 #define BW_SDHC_IRQSTAT_CC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CC), v))
02420 /*@}*/
02421 
02422 /*!
02423  * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
02424  *
02425  * This bit is set when a read or write transfer is completed. In the case of a
02426  * read transaction: This bit is set at the falling edge of the read transfer
02427  * active status. There are two cases in which this interrupt is generated. The
02428  * first is when a data transfer is completed as specified by the data length, after
02429  * the last data has been read to the host system. The second is when data has
02430  * stopped at the block gap and completed the data transfer by setting
02431  * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
02432  * transaction: This bit is set at the falling edge of the DAT line active
02433  * status. There are two cases in which this interrupt is generated. The first is when
02434  * the last data is written to the SD card as specified by the data length and
02435  * the busy signal is released. The second is when data transfers are stopped at
02436  * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
02437  * completed,after valid data is written to the SD card and the busy signal released.
02438  *
02439  * Values:
02440  * - 0 - Transfer not complete.
02441  * - 1 - Transfer complete.
02442  */
02443 /*@{*/
02444 #define BP_SDHC_IRQSTAT_TC   (1U)          /*!< Bit position for SDHC_IRQSTAT_TC. */
02445 #define BM_SDHC_IRQSTAT_TC   (0x00000002U) /*!< Bit mask for SDHC_IRQSTAT_TC. */
02446 #define BS_SDHC_IRQSTAT_TC   (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_TC. */
02447 
02448 /*! @brief Read current value of the SDHC_IRQSTAT_TC field. */
02449 #define BR_SDHC_IRQSTAT_TC(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC)))
02450 
02451 /*! @brief Format value for bitfield SDHC_IRQSTAT_TC. */
02452 #define BF_SDHC_IRQSTAT_TC(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_TC) & BM_SDHC_IRQSTAT_TC)
02453 
02454 /*! @brief Set the TC field to a new value. */
02455 #define BW_SDHC_IRQSTAT_TC(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_TC), v))
02456 /*@}*/
02457 
02458 /*!
02459  * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
02460  *
02461  * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
02462  * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
02463  * set to 1. In the case of a read transaction: This bit is set at the falling
02464  * edge of the DAT line active status, when the transaction is stopped at SD Bus
02465  * timing. The read wait must be supported in order to use this function. In the
02466  * case of write transaction: This bit is set at the falling edge of write transfer
02467  * active status, after getting CRC status at SD bus timing.
02468  *
02469  * Values:
02470  * - 0 - No block gap event.
02471  * - 1 - Transaction stopped at block gap.
02472  */
02473 /*@{*/
02474 #define BP_SDHC_IRQSTAT_BGE  (2U)          /*!< Bit position for SDHC_IRQSTAT_BGE. */
02475 #define BM_SDHC_IRQSTAT_BGE  (0x00000004U) /*!< Bit mask for SDHC_IRQSTAT_BGE. */
02476 #define BS_SDHC_IRQSTAT_BGE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_BGE. */
02477 
02478 /*! @brief Read current value of the SDHC_IRQSTAT_BGE field. */
02479 #define BR_SDHC_IRQSTAT_BGE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE)))
02480 
02481 /*! @brief Format value for bitfield SDHC_IRQSTAT_BGE. */
02482 #define BF_SDHC_IRQSTAT_BGE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BGE) & BM_SDHC_IRQSTAT_BGE)
02483 
02484 /*! @brief Set the BGE field to a new value. */
02485 #define BW_SDHC_IRQSTAT_BGE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BGE), v))
02486 /*@}*/
02487 
02488 /*!
02489  * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
02490  *
02491  * Occurs only when the internal DMA finishes the data transfer successfully.
02492  * Whenever errors occur during data transfer, this bit will not be set. Instead,
02493  * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
02494  * this bit will be set.
02495  *
02496  * Values:
02497  * - 0 - No DMA Interrupt.
02498  * - 1 - DMA Interrupt is generated.
02499  */
02500 /*@{*/
02501 #define BP_SDHC_IRQSTAT_DINT (3U)          /*!< Bit position for SDHC_IRQSTAT_DINT. */
02502 #define BM_SDHC_IRQSTAT_DINT (0x00000008U) /*!< Bit mask for SDHC_IRQSTAT_DINT. */
02503 #define BS_SDHC_IRQSTAT_DINT (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DINT. */
02504 
02505 /*! @brief Read current value of the SDHC_IRQSTAT_DINT field. */
02506 #define BR_SDHC_IRQSTAT_DINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT)))
02507 
02508 /*! @brief Format value for bitfield SDHC_IRQSTAT_DINT. */
02509 #define BF_SDHC_IRQSTAT_DINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DINT) & BM_SDHC_IRQSTAT_DINT)
02510 
02511 /*! @brief Set the DINT field to a new value. */
02512 #define BW_SDHC_IRQSTAT_DINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DINT), v))
02513 /*@}*/
02514 
02515 /*!
02516  * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
02517  *
02518  * This status bit is set if the Buffer Write Enable bit, in the Present State
02519  * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
02520  * State register for additional information.
02521  *
02522  * Values:
02523  * - 0 - Not ready to write buffer.
02524  * - 1 - Ready to write buffer.
02525  */
02526 /*@{*/
02527 #define BP_SDHC_IRQSTAT_BWR  (4U)          /*!< Bit position for SDHC_IRQSTAT_BWR. */
02528 #define BM_SDHC_IRQSTAT_BWR  (0x00000010U) /*!< Bit mask for SDHC_IRQSTAT_BWR. */
02529 #define BS_SDHC_IRQSTAT_BWR  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_BWR. */
02530 
02531 /*! @brief Read current value of the SDHC_IRQSTAT_BWR field. */
02532 #define BR_SDHC_IRQSTAT_BWR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR)))
02533 
02534 /*! @brief Format value for bitfield SDHC_IRQSTAT_BWR. */
02535 #define BF_SDHC_IRQSTAT_BWR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BWR) & BM_SDHC_IRQSTAT_BWR)
02536 
02537 /*! @brief Set the BWR field to a new value. */
02538 #define BW_SDHC_IRQSTAT_BWR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BWR), v))
02539 /*@}*/
02540 
02541 /*!
02542  * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
02543  *
02544  * This status bit is set if the Buffer Read Enable bit, in the Present State
02545  * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
02546  * State register for additional information.
02547  *
02548  * Values:
02549  * - 0 - Not ready to read buffer.
02550  * - 1 - Ready to read buffer.
02551  */
02552 /*@{*/
02553 #define BP_SDHC_IRQSTAT_BRR  (5U)          /*!< Bit position for SDHC_IRQSTAT_BRR. */
02554 #define BM_SDHC_IRQSTAT_BRR  (0x00000020U) /*!< Bit mask for SDHC_IRQSTAT_BRR. */
02555 #define BS_SDHC_IRQSTAT_BRR  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_BRR. */
02556 
02557 /*! @brief Read current value of the SDHC_IRQSTAT_BRR field. */
02558 #define BR_SDHC_IRQSTAT_BRR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR)))
02559 
02560 /*! @brief Format value for bitfield SDHC_IRQSTAT_BRR. */
02561 #define BF_SDHC_IRQSTAT_BRR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_BRR) & BM_SDHC_IRQSTAT_BRR)
02562 
02563 /*! @brief Set the BRR field to a new value. */
02564 #define BW_SDHC_IRQSTAT_BRR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_BRR), v))
02565 /*@}*/
02566 
02567 /*!
02568  * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
02569  *
02570  * This status bit is set if the Card Inserted bit in the Present State register
02571  * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
02572  * status, the status of the Card Inserted in the Present State register must be
02573  * confirmed. Because the card state may possibly be changed when the host driver
02574  * clears this bit and the interrupt event may not be generated. When this bit
02575  * is cleared, it will be set again if a card is inserted. To leave it cleared,
02576  * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
02577  *
02578  * Values:
02579  * - 0 - Card state unstable or removed.
02580  * - 1 - Card inserted.
02581  */
02582 /*@{*/
02583 #define BP_SDHC_IRQSTAT_CINS (6U)          /*!< Bit position for SDHC_IRQSTAT_CINS. */
02584 #define BM_SDHC_IRQSTAT_CINS (0x00000040U) /*!< Bit mask for SDHC_IRQSTAT_CINS. */
02585 #define BS_SDHC_IRQSTAT_CINS (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CINS. */
02586 
02587 /*! @brief Read current value of the SDHC_IRQSTAT_CINS field. */
02588 #define BR_SDHC_IRQSTAT_CINS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS)))
02589 
02590 /*! @brief Format value for bitfield SDHC_IRQSTAT_CINS. */
02591 #define BF_SDHC_IRQSTAT_CINS(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINS) & BM_SDHC_IRQSTAT_CINS)
02592 
02593 /*! @brief Set the CINS field to a new value. */
02594 #define BW_SDHC_IRQSTAT_CINS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINS), v))
02595 /*@}*/
02596 
02597 /*!
02598  * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
02599  *
02600  * This status bit is set if the Card Inserted bit in the Present State register
02601  * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
02602  * status, the status of the Card Inserted in the Present State register must be
02603  * confirmed. Because the card state may possibly be changed when the host driver
02604  * clears this bit and the interrupt event may not be generated. When this bit
02605  * is cleared, it will be set again if no card is inserted. To leave it cleared,
02606  * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
02607  *
02608  * Values:
02609  * - 0 - Card state unstable or inserted.
02610  * - 1 - Card removed.
02611  */
02612 /*@{*/
02613 #define BP_SDHC_IRQSTAT_CRM  (7U)          /*!< Bit position for SDHC_IRQSTAT_CRM. */
02614 #define BM_SDHC_IRQSTAT_CRM  (0x00000080U) /*!< Bit mask for SDHC_IRQSTAT_CRM. */
02615 #define BS_SDHC_IRQSTAT_CRM  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CRM. */
02616 
02617 /*! @brief Read current value of the SDHC_IRQSTAT_CRM field. */
02618 #define BR_SDHC_IRQSTAT_CRM(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM)))
02619 
02620 /*! @brief Format value for bitfield SDHC_IRQSTAT_CRM. */
02621 #define BF_SDHC_IRQSTAT_CRM(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CRM) & BM_SDHC_IRQSTAT_CRM)
02622 
02623 /*! @brief Set the CRM field to a new value. */
02624 #define BW_SDHC_IRQSTAT_CRM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CRM), v))
02625 /*@}*/
02626 
02627 /*!
02628  * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
02629  *
02630  * This status bit is set when an interrupt signal is detected from the external
02631  * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
02632  * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
02633  * during the interrupt cycle, so the interrupt from card can only be sampled
02634  * during interrupt cycle, introducing some delay between the interrupt signal from
02635  * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
02636  * clear this bit, but as the interrupt factor from the SDIO card does not clear,
02637  * this bit is set again. To clear this bit, it is required to reset the interrupt
02638  * factor from the external card followed by a writing 1 to this bit. When this
02639  * status has been set, and the host driver needs to service this interrupt, the
02640  * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
02641  * 0 to stop driving the interrupt signal to the host system. After completion
02642  * of the card interrupt service (it must reset the interrupt factors in the SDIO
02643  * card and the interrupt signal may not be asserted), write 1 to clear this bit,
02644  * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
02645  * signal again.
02646  *
02647  * Values:
02648  * - 0 - No Card Interrupt.
02649  * - 1 - Generate Card Interrupt.
02650  */
02651 /*@{*/
02652 #define BP_SDHC_IRQSTAT_CINT (8U)          /*!< Bit position for SDHC_IRQSTAT_CINT. */
02653 #define BM_SDHC_IRQSTAT_CINT (0x00000100U) /*!< Bit mask for SDHC_IRQSTAT_CINT. */
02654 #define BS_SDHC_IRQSTAT_CINT (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CINT. */
02655 
02656 /*! @brief Read current value of the SDHC_IRQSTAT_CINT field. */
02657 #define BR_SDHC_IRQSTAT_CINT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT)))
02658 
02659 /*! @brief Format value for bitfield SDHC_IRQSTAT_CINT. */
02660 #define BF_SDHC_IRQSTAT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CINT) & BM_SDHC_IRQSTAT_CINT)
02661 
02662 /*! @brief Set the CINT field to a new value. */
02663 #define BW_SDHC_IRQSTAT_CINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CINT), v))
02664 /*@}*/
02665 
02666 /*!
02667  * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
02668  *
02669  * Occurs only if no response is returned within 64 SDCLK cycles from the end
02670  * bit of the command. If the SDHC detects a CMD line conflict, in which case a
02671  * Command CRC Error shall also be set, this bit shall be set without waiting for 64
02672  * SDCLK cycles. This is because the command will be aborted by the SDHC.
02673  *
02674  * Values:
02675  * - 0 - No error.
02676  * - 1 - Time out.
02677  */
02678 /*@{*/
02679 #define BP_SDHC_IRQSTAT_CTOE (16U)         /*!< Bit position for SDHC_IRQSTAT_CTOE. */
02680 #define BM_SDHC_IRQSTAT_CTOE (0x00010000U) /*!< Bit mask for SDHC_IRQSTAT_CTOE. */
02681 #define BS_SDHC_IRQSTAT_CTOE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CTOE. */
02682 
02683 /*! @brief Read current value of the SDHC_IRQSTAT_CTOE field. */
02684 #define BR_SDHC_IRQSTAT_CTOE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE)))
02685 
02686 /*! @brief Format value for bitfield SDHC_IRQSTAT_CTOE. */
02687 #define BF_SDHC_IRQSTAT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CTOE) & BM_SDHC_IRQSTAT_CTOE)
02688 
02689 /*! @brief Set the CTOE field to a new value. */
02690 #define BW_SDHC_IRQSTAT_CTOE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CTOE), v))
02691 /*@}*/
02692 
02693 /*!
02694  * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
02695  *
02696  * Command CRC Error is generated in two cases. If a response is returned and
02697  * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
02698  * when detecting a CRC error in the command response. The SDHC detects a CMD line
02699  * conflict by monitoring the CMD line when a command is issued. If the SDHC
02700  * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
02701  * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
02702  * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
02703  * conflict.
02704  *
02705  * Values:
02706  * - 0 - No error.
02707  * - 1 - CRC Error generated.
02708  */
02709 /*@{*/
02710 #define BP_SDHC_IRQSTAT_CCE  (17U)         /*!< Bit position for SDHC_IRQSTAT_CCE. */
02711 #define BM_SDHC_IRQSTAT_CCE  (0x00020000U) /*!< Bit mask for SDHC_IRQSTAT_CCE. */
02712 #define BS_SDHC_IRQSTAT_CCE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CCE. */
02713 
02714 /*! @brief Read current value of the SDHC_IRQSTAT_CCE field. */
02715 #define BR_SDHC_IRQSTAT_CCE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE)))
02716 
02717 /*! @brief Format value for bitfield SDHC_IRQSTAT_CCE. */
02718 #define BF_SDHC_IRQSTAT_CCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CCE) & BM_SDHC_IRQSTAT_CCE)
02719 
02720 /*! @brief Set the CCE field to a new value. */
02721 #define BW_SDHC_IRQSTAT_CCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CCE), v))
02722 /*@}*/
02723 
02724 /*!
02725  * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
02726  *
02727  * Occurs when detecting that the end bit of a command response is 0.
02728  *
02729  * Values:
02730  * - 0 - No error.
02731  * - 1 - End Bit Error generated.
02732  */
02733 /*@{*/
02734 #define BP_SDHC_IRQSTAT_CEBE (18U)         /*!< Bit position for SDHC_IRQSTAT_CEBE. */
02735 #define BM_SDHC_IRQSTAT_CEBE (0x00040000U) /*!< Bit mask for SDHC_IRQSTAT_CEBE. */
02736 #define BS_SDHC_IRQSTAT_CEBE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CEBE. */
02737 
02738 /*! @brief Read current value of the SDHC_IRQSTAT_CEBE field. */
02739 #define BR_SDHC_IRQSTAT_CEBE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE)))
02740 
02741 /*! @brief Format value for bitfield SDHC_IRQSTAT_CEBE. */
02742 #define BF_SDHC_IRQSTAT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CEBE) & BM_SDHC_IRQSTAT_CEBE)
02743 
02744 /*! @brief Set the CEBE field to a new value. */
02745 #define BW_SDHC_IRQSTAT_CEBE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CEBE), v))
02746 /*@}*/
02747 
02748 /*!
02749  * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
02750  *
02751  * Occurs if a Command Index error occurs in the command response.
02752  *
02753  * Values:
02754  * - 0 - No error.
02755  * - 1 - Error.
02756  */
02757 /*@{*/
02758 #define BP_SDHC_IRQSTAT_CIE  (19U)         /*!< Bit position for SDHC_IRQSTAT_CIE. */
02759 #define BM_SDHC_IRQSTAT_CIE  (0x00080000U) /*!< Bit mask for SDHC_IRQSTAT_CIE. */
02760 #define BS_SDHC_IRQSTAT_CIE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_CIE. */
02761 
02762 /*! @brief Read current value of the SDHC_IRQSTAT_CIE field. */
02763 #define BR_SDHC_IRQSTAT_CIE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE)))
02764 
02765 /*! @brief Format value for bitfield SDHC_IRQSTAT_CIE. */
02766 #define BF_SDHC_IRQSTAT_CIE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_CIE) & BM_SDHC_IRQSTAT_CIE)
02767 
02768 /*! @brief Set the CIE field to a new value. */
02769 #define BW_SDHC_IRQSTAT_CIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_CIE), v))
02770 /*@}*/
02771 
02772 /*!
02773  * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
02774  *
02775  * Occurs when detecting one of following time-out conditions. Busy time-out for
02776  * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
02777  *
02778  * Values:
02779  * - 0 - No error.
02780  * - 1 - Time out.
02781  */
02782 /*@{*/
02783 #define BP_SDHC_IRQSTAT_DTOE (20U)         /*!< Bit position for SDHC_IRQSTAT_DTOE. */
02784 #define BM_SDHC_IRQSTAT_DTOE (0x00100000U) /*!< Bit mask for SDHC_IRQSTAT_DTOE. */
02785 #define BS_SDHC_IRQSTAT_DTOE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DTOE. */
02786 
02787 /*! @brief Read current value of the SDHC_IRQSTAT_DTOE field. */
02788 #define BR_SDHC_IRQSTAT_DTOE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE)))
02789 
02790 /*! @brief Format value for bitfield SDHC_IRQSTAT_DTOE. */
02791 #define BF_SDHC_IRQSTAT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DTOE) & BM_SDHC_IRQSTAT_DTOE)
02792 
02793 /*! @brief Set the DTOE field to a new value. */
02794 #define BW_SDHC_IRQSTAT_DTOE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DTOE), v))
02795 /*@}*/
02796 
02797 /*!
02798  * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
02799  *
02800  * Occurs when detecting a CRC error when transferring read data, which uses the
02801  * DAT line, or when detecting the Write CRC status having a value other than
02802  * 010.
02803  *
02804  * Values:
02805  * - 0 - No error.
02806  * - 1 - Error.
02807  */
02808 /*@{*/
02809 #define BP_SDHC_IRQSTAT_DCE  (21U)         /*!< Bit position for SDHC_IRQSTAT_DCE. */
02810 #define BM_SDHC_IRQSTAT_DCE  (0x00200000U) /*!< Bit mask for SDHC_IRQSTAT_DCE. */
02811 #define BS_SDHC_IRQSTAT_DCE  (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DCE. */
02812 
02813 /*! @brief Read current value of the SDHC_IRQSTAT_DCE field. */
02814 #define BR_SDHC_IRQSTAT_DCE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE)))
02815 
02816 /*! @brief Format value for bitfield SDHC_IRQSTAT_DCE. */
02817 #define BF_SDHC_IRQSTAT_DCE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DCE) & BM_SDHC_IRQSTAT_DCE)
02818 
02819 /*! @brief Set the DCE field to a new value. */
02820 #define BW_SDHC_IRQSTAT_DCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DCE), v))
02821 /*@}*/
02822 
02823 /*!
02824  * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
02825  *
02826  * Occurs either when detecting 0 at the end bit position of read data, which
02827  * uses the DAT line, or at the end bit position of the CRC.
02828  *
02829  * Values:
02830  * - 0 - No error.
02831  * - 1 - Error.
02832  */
02833 /*@{*/
02834 #define BP_SDHC_IRQSTAT_DEBE (22U)         /*!< Bit position for SDHC_IRQSTAT_DEBE. */
02835 #define BM_SDHC_IRQSTAT_DEBE (0x00400000U) /*!< Bit mask for SDHC_IRQSTAT_DEBE. */
02836 #define BS_SDHC_IRQSTAT_DEBE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DEBE. */
02837 
02838 /*! @brief Read current value of the SDHC_IRQSTAT_DEBE field. */
02839 #define BR_SDHC_IRQSTAT_DEBE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE)))
02840 
02841 /*! @brief Format value for bitfield SDHC_IRQSTAT_DEBE. */
02842 #define BF_SDHC_IRQSTAT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DEBE) & BM_SDHC_IRQSTAT_DEBE)
02843 
02844 /*! @brief Set the DEBE field to a new value. */
02845 #define BW_SDHC_IRQSTAT_DEBE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DEBE), v))
02846 /*@}*/
02847 
02848 /*!
02849  * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
02850  *
02851  * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
02852  * register has changed from 0 to 1. This bit is set to 1, not only when the errors
02853  * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
02854  * previous command error.
02855  *
02856  * Values:
02857  * - 0 - No error.
02858  * - 1 - Error.
02859  */
02860 /*@{*/
02861 #define BP_SDHC_IRQSTAT_AC12E (24U)        /*!< Bit position for SDHC_IRQSTAT_AC12E. */
02862 #define BM_SDHC_IRQSTAT_AC12E (0x01000000U) /*!< Bit mask for SDHC_IRQSTAT_AC12E. */
02863 #define BS_SDHC_IRQSTAT_AC12E (1U)         /*!< Bit field size in bits for SDHC_IRQSTAT_AC12E. */
02864 
02865 /*! @brief Read current value of the SDHC_IRQSTAT_AC12E field. */
02866 #define BR_SDHC_IRQSTAT_AC12E(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E)))
02867 
02868 /*! @brief Format value for bitfield SDHC_IRQSTAT_AC12E. */
02869 #define BF_SDHC_IRQSTAT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_AC12E) & BM_SDHC_IRQSTAT_AC12E)
02870 
02871 /*! @brief Set the AC12E field to a new value. */
02872 #define BW_SDHC_IRQSTAT_AC12E(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_AC12E), v))
02873 /*@}*/
02874 
02875 /*!
02876  * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
02877  *
02878  * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
02879  * some error occurs in the data transfer. This error can be caused by either
02880  * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
02881  * Address register is the next fetch address where the error occurs. Because any
02882  * error corrupts the whole data block, the host driver shall restart the transfer
02883  * from the corrupted block boundary. The address of the block boundary can be
02884  * calculated either from the current DSADDR value or from the remaining number of
02885  * blocks and the block size.
02886  *
02887  * Values:
02888  * - 0 - No error.
02889  * - 1 - Error.
02890  */
02891 /*@{*/
02892 #define BP_SDHC_IRQSTAT_DMAE (28U)         /*!< Bit position for SDHC_IRQSTAT_DMAE. */
02893 #define BM_SDHC_IRQSTAT_DMAE (0x10000000U) /*!< Bit mask for SDHC_IRQSTAT_DMAE. */
02894 #define BS_SDHC_IRQSTAT_DMAE (1U)          /*!< Bit field size in bits for SDHC_IRQSTAT_DMAE. */
02895 
02896 /*! @brief Read current value of the SDHC_IRQSTAT_DMAE field. */
02897 #define BR_SDHC_IRQSTAT_DMAE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE)))
02898 
02899 /*! @brief Format value for bitfield SDHC_IRQSTAT_DMAE. */
02900 #define BF_SDHC_IRQSTAT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTAT_DMAE) & BM_SDHC_IRQSTAT_DMAE)
02901 
02902 /*! @brief Set the DMAE field to a new value. */
02903 #define BW_SDHC_IRQSTAT_DMAE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTAT_ADDR(x), BP_SDHC_IRQSTAT_DMAE), v))
02904 /*@}*/
02905 
02906 /*******************************************************************************
02907  * HW_SDHC_IRQSTATEN - Interrupt Status Enable register
02908  ******************************************************************************/
02909 
02910 /*!
02911  * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
02912  *
02913  * Reset value: 0x117F013FU
02914  *
02915  * Setting the bits in this register to 1 enables the corresponding interrupt
02916  * status to be set by the specified event. If any bit is cleared, the
02917  * corresponding interrupt status bit is also cleared, that is, when the bit in this register
02918  * is cleared, the corresponding bit in interrupt status register is always 0.
02919  * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
02920  * card interrupt signal during the interrupt period and hold its value in the
02921  * flip-flop. There will be some delays on the card interrupt, asserted from the card,
02922  * to the time the host system is informed. To detect a CMD line conflict, the
02923  * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
02924  */
02925 typedef union _hw_sdhc_irqstaten
02926 {
02927     uint32_t U;
02928     struct _hw_sdhc_irqstaten_bitfields
02929     {
02930         uint32_t CCSEN : 1;            /*!< [0] Command Complete Status Enable */
02931         uint32_t TCSEN : 1;            /*!< [1] Transfer Complete Status Enable */
02932         uint32_t BGESEN : 1;           /*!< [2] Block Gap Event Status Enable */
02933         uint32_t DINTSEN : 1;          /*!< [3] DMA Interrupt Status Enable */
02934         uint32_t BWRSEN : 1;           /*!< [4] Buffer Write Ready Status Enable */
02935         uint32_t BRRSEN : 1;           /*!< [5] Buffer Read Ready Status Enable */
02936         uint32_t CINSEN : 1;           /*!< [6] Card Insertion Status Enable */
02937         uint32_t CRMSEN : 1;           /*!< [7] Card Removal Status Enable */
02938         uint32_t CINTSEN : 1;          /*!< [8] Card Interrupt Status Enable */
02939         uint32_t RESERVED0 : 7;        /*!< [15:9]  */
02940         uint32_t CTOESEN : 1;          /*!< [16] Command Timeout Error Status Enable */
02941         uint32_t CCESEN : 1;           /*!< [17] Command CRC Error Status Enable */
02942         uint32_t CEBESEN : 1;          /*!< [18] Command End Bit Error Status Enable */
02943         uint32_t CIESEN : 1;           /*!< [19] Command Index Error Status Enable */
02944         uint32_t DTOESEN : 1;          /*!< [20] Data Timeout Error Status Enable */
02945         uint32_t DCESEN : 1;           /*!< [21] Data CRC Error Status Enable */
02946         uint32_t DEBESEN : 1;          /*!< [22] Data End Bit Error Status Enable */
02947         uint32_t RESERVED1 : 1;        /*!< [23]  */
02948         uint32_t AC12ESEN : 1;         /*!< [24] Auto CMD12 Error Status Enable */
02949         uint32_t RESERVED2 : 3;        /*!< [27:25]  */
02950         uint32_t DMAESEN : 1;          /*!< [28] DMA Error Status Enable */
02951         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
02952     } B;
02953 } hw_sdhc_irqstaten_t;
02954 
02955 /*!
02956  * @name Constants and macros for entire SDHC_IRQSTATEN register
02957  */
02958 /*@{*/
02959 #define HW_SDHC_IRQSTATEN_ADDR(x) ((x) + 0x34U)
02960 
02961 #define HW_SDHC_IRQSTATEN(x)     (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR(x))
02962 #define HW_SDHC_IRQSTATEN_RD(x)  (ADDRESS_READ(hw_sdhc_irqstaten_t, HW_SDHC_IRQSTATEN_ADDR(x)))
02963 #define HW_SDHC_IRQSTATEN_WR(x, v) (ADDRESS_WRITE(hw_sdhc_irqstaten_t, HW_SDHC_IRQSTATEN_ADDR(x), v))
02964 #define HW_SDHC_IRQSTATEN_SET(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) |  (v)))
02965 #define HW_SDHC_IRQSTATEN_CLR(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) & ~(v)))
02966 #define HW_SDHC_IRQSTATEN_TOG(x, v) (HW_SDHC_IRQSTATEN_WR(x, HW_SDHC_IRQSTATEN_RD(x) ^  (v)))
02967 /*@}*/
02968 
02969 /*
02970  * Constants & macros for individual SDHC_IRQSTATEN bitfields
02971  */
02972 
02973 /*!
02974  * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
02975  *
02976  * Values:
02977  * - 0 - Masked
02978  * - 1 - Enabled
02979  */
02980 /*@{*/
02981 #define BP_SDHC_IRQSTATEN_CCSEN (0U)       /*!< Bit position for SDHC_IRQSTATEN_CCSEN. */
02982 #define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) /*!< Bit mask for SDHC_IRQSTATEN_CCSEN. */
02983 #define BS_SDHC_IRQSTATEN_CCSEN (1U)       /*!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN. */
02984 
02985 /*! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field. */
02986 #define BR_SDHC_IRQSTATEN_CCSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN)))
02987 
02988 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN. */
02989 #define BF_SDHC_IRQSTATEN_CCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCSEN) & BM_SDHC_IRQSTATEN_CCSEN)
02990 
02991 /*! @brief Set the CCSEN field to a new value. */
02992 #define BW_SDHC_IRQSTATEN_CCSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCSEN), v))
02993 /*@}*/
02994 
02995 /*!
02996  * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
02997  *
02998  * Values:
02999  * - 0 - Masked
03000  * - 1 - Enabled
03001  */
03002 /*@{*/
03003 #define BP_SDHC_IRQSTATEN_TCSEN (1U)       /*!< Bit position for SDHC_IRQSTATEN_TCSEN. */
03004 #define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) /*!< Bit mask for SDHC_IRQSTATEN_TCSEN. */
03005 #define BS_SDHC_IRQSTATEN_TCSEN (1U)       /*!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN. */
03006 
03007 /*! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field. */
03008 #define BR_SDHC_IRQSTATEN_TCSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN)))
03009 
03010 /*! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN. */
03011 #define BF_SDHC_IRQSTATEN_TCSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_TCSEN) & BM_SDHC_IRQSTATEN_TCSEN)
03012 
03013 /*! @brief Set the TCSEN field to a new value. */
03014 #define BW_SDHC_IRQSTATEN_TCSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_TCSEN), v))
03015 /*@}*/
03016 
03017 /*!
03018  * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
03019  *
03020  * Values:
03021  * - 0 - Masked
03022  * - 1 - Enabled
03023  */
03024 /*@{*/
03025 #define BP_SDHC_IRQSTATEN_BGESEN (2U)      /*!< Bit position for SDHC_IRQSTATEN_BGESEN. */
03026 #define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) /*!< Bit mask for SDHC_IRQSTATEN_BGESEN. */
03027 #define BS_SDHC_IRQSTATEN_BGESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN. */
03028 
03029 /*! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field. */
03030 #define BR_SDHC_IRQSTATEN_BGESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN)))
03031 
03032 /*! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN. */
03033 #define BF_SDHC_IRQSTATEN_BGESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BGESEN) & BM_SDHC_IRQSTATEN_BGESEN)
03034 
03035 /*! @brief Set the BGESEN field to a new value. */
03036 #define BW_SDHC_IRQSTATEN_BGESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BGESEN), v))
03037 /*@}*/
03038 
03039 /*!
03040  * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
03041  *
03042  * Values:
03043  * - 0 - Masked
03044  * - 1 - Enabled
03045  */
03046 /*@{*/
03047 #define BP_SDHC_IRQSTATEN_DINTSEN (3U)     /*!< Bit position for SDHC_IRQSTATEN_DINTSEN. */
03048 #define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) /*!< Bit mask for SDHC_IRQSTATEN_DINTSEN. */
03049 #define BS_SDHC_IRQSTATEN_DINTSEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN. */
03050 
03051 /*! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field. */
03052 #define BR_SDHC_IRQSTATEN_DINTSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN)))
03053 
03054 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN. */
03055 #define BF_SDHC_IRQSTATEN_DINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DINTSEN) & BM_SDHC_IRQSTATEN_DINTSEN)
03056 
03057 /*! @brief Set the DINTSEN field to a new value. */
03058 #define BW_SDHC_IRQSTATEN_DINTSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DINTSEN), v))
03059 /*@}*/
03060 
03061 /*!
03062  * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
03063  *
03064  * Values:
03065  * - 0 - Masked
03066  * - 1 - Enabled
03067  */
03068 /*@{*/
03069 #define BP_SDHC_IRQSTATEN_BWRSEN (4U)      /*!< Bit position for SDHC_IRQSTATEN_BWRSEN. */
03070 #define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) /*!< Bit mask for SDHC_IRQSTATEN_BWRSEN. */
03071 #define BS_SDHC_IRQSTATEN_BWRSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN. */
03072 
03073 /*! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field. */
03074 #define BR_SDHC_IRQSTATEN_BWRSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN)))
03075 
03076 /*! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN. */
03077 #define BF_SDHC_IRQSTATEN_BWRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BWRSEN) & BM_SDHC_IRQSTATEN_BWRSEN)
03078 
03079 /*! @brief Set the BWRSEN field to a new value. */
03080 #define BW_SDHC_IRQSTATEN_BWRSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BWRSEN), v))
03081 /*@}*/
03082 
03083 /*!
03084  * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
03085  *
03086  * Values:
03087  * - 0 - Masked
03088  * - 1 - Enabled
03089  */
03090 /*@{*/
03091 #define BP_SDHC_IRQSTATEN_BRRSEN (5U)      /*!< Bit position for SDHC_IRQSTATEN_BRRSEN. */
03092 #define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) /*!< Bit mask for SDHC_IRQSTATEN_BRRSEN. */
03093 #define BS_SDHC_IRQSTATEN_BRRSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN. */
03094 
03095 /*! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field. */
03096 #define BR_SDHC_IRQSTATEN_BRRSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN)))
03097 
03098 /*! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN. */
03099 #define BF_SDHC_IRQSTATEN_BRRSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_BRRSEN) & BM_SDHC_IRQSTATEN_BRRSEN)
03100 
03101 /*! @brief Set the BRRSEN field to a new value. */
03102 #define BW_SDHC_IRQSTATEN_BRRSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_BRRSEN), v))
03103 /*@}*/
03104 
03105 /*!
03106  * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
03107  *
03108  * Values:
03109  * - 0 - Masked
03110  * - 1 - Enabled
03111  */
03112 /*@{*/
03113 #define BP_SDHC_IRQSTATEN_CINSEN (6U)      /*!< Bit position for SDHC_IRQSTATEN_CINSEN. */
03114 #define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) /*!< Bit mask for SDHC_IRQSTATEN_CINSEN. */
03115 #define BS_SDHC_IRQSTATEN_CINSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN. */
03116 
03117 /*! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field. */
03118 #define BR_SDHC_IRQSTATEN_CINSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN)))
03119 
03120 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN. */
03121 #define BF_SDHC_IRQSTATEN_CINSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINSEN) & BM_SDHC_IRQSTATEN_CINSEN)
03122 
03123 /*! @brief Set the CINSEN field to a new value. */
03124 #define BW_SDHC_IRQSTATEN_CINSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINSEN), v))
03125 /*@}*/
03126 
03127 /*!
03128  * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
03129  *
03130  * Values:
03131  * - 0 - Masked
03132  * - 1 - Enabled
03133  */
03134 /*@{*/
03135 #define BP_SDHC_IRQSTATEN_CRMSEN (7U)      /*!< Bit position for SDHC_IRQSTATEN_CRMSEN. */
03136 #define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) /*!< Bit mask for SDHC_IRQSTATEN_CRMSEN. */
03137 #define BS_SDHC_IRQSTATEN_CRMSEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN. */
03138 
03139 /*! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field. */
03140 #define BR_SDHC_IRQSTATEN_CRMSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN)))
03141 
03142 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN. */
03143 #define BF_SDHC_IRQSTATEN_CRMSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CRMSEN) & BM_SDHC_IRQSTATEN_CRMSEN)
03144 
03145 /*! @brief Set the CRMSEN field to a new value. */
03146 #define BW_SDHC_IRQSTATEN_CRMSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CRMSEN), v))
03147 /*@}*/
03148 
03149 /*!
03150  * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
03151  *
03152  * If this bit is set to 0, the SDHC will clear the interrupt request to the
03153  * system. The card interrupt detection is stopped when this bit is cleared and
03154  * restarted when this bit is set to 1. The host driver must clear the this bit
03155  * before servicing the card interrupt and must set this bit again after all interrupt
03156  * requests from the card are cleared to prevent inadvertent interrupts.
03157  *
03158  * Values:
03159  * - 0 - Masked
03160  * - 1 - Enabled
03161  */
03162 /*@{*/
03163 #define BP_SDHC_IRQSTATEN_CINTSEN (8U)     /*!< Bit position for SDHC_IRQSTATEN_CINTSEN. */
03164 #define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) /*!< Bit mask for SDHC_IRQSTATEN_CINTSEN. */
03165 #define BS_SDHC_IRQSTATEN_CINTSEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN. */
03166 
03167 /*! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field. */
03168 #define BR_SDHC_IRQSTATEN_CINTSEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN)))
03169 
03170 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN. */
03171 #define BF_SDHC_IRQSTATEN_CINTSEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CINTSEN) & BM_SDHC_IRQSTATEN_CINTSEN)
03172 
03173 /*! @brief Set the CINTSEN field to a new value. */
03174 #define BW_SDHC_IRQSTATEN_CINTSEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CINTSEN), v))
03175 /*@}*/
03176 
03177 /*!
03178  * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
03179  *
03180  * Values:
03181  * - 0 - Masked
03182  * - 1 - Enabled
03183  */
03184 /*@{*/
03185 #define BP_SDHC_IRQSTATEN_CTOESEN (16U)    /*!< Bit position for SDHC_IRQSTATEN_CTOESEN. */
03186 #define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) /*!< Bit mask for SDHC_IRQSTATEN_CTOESEN. */
03187 #define BS_SDHC_IRQSTATEN_CTOESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN. */
03188 
03189 /*! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field. */
03190 #define BR_SDHC_IRQSTATEN_CTOESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN)))
03191 
03192 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN. */
03193 #define BF_SDHC_IRQSTATEN_CTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CTOESEN) & BM_SDHC_IRQSTATEN_CTOESEN)
03194 
03195 /*! @brief Set the CTOESEN field to a new value. */
03196 #define BW_SDHC_IRQSTATEN_CTOESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CTOESEN), v))
03197 /*@}*/
03198 
03199 /*!
03200  * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
03201  *
03202  * Values:
03203  * - 0 - Masked
03204  * - 1 - Enabled
03205  */
03206 /*@{*/
03207 #define BP_SDHC_IRQSTATEN_CCESEN (17U)     /*!< Bit position for SDHC_IRQSTATEN_CCESEN. */
03208 #define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) /*!< Bit mask for SDHC_IRQSTATEN_CCESEN. */
03209 #define BS_SDHC_IRQSTATEN_CCESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN. */
03210 
03211 /*! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field. */
03212 #define BR_SDHC_IRQSTATEN_CCESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN)))
03213 
03214 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN. */
03215 #define BF_SDHC_IRQSTATEN_CCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CCESEN) & BM_SDHC_IRQSTATEN_CCESEN)
03216 
03217 /*! @brief Set the CCESEN field to a new value. */
03218 #define BW_SDHC_IRQSTATEN_CCESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CCESEN), v))
03219 /*@}*/
03220 
03221 /*!
03222  * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
03223  *
03224  * Values:
03225  * - 0 - Masked
03226  * - 1 - Enabled
03227  */
03228 /*@{*/
03229 #define BP_SDHC_IRQSTATEN_CEBESEN (18U)    /*!< Bit position for SDHC_IRQSTATEN_CEBESEN. */
03230 #define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) /*!< Bit mask for SDHC_IRQSTATEN_CEBESEN. */
03231 #define BS_SDHC_IRQSTATEN_CEBESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN. */
03232 
03233 /*! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field. */
03234 #define BR_SDHC_IRQSTATEN_CEBESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN)))
03235 
03236 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN. */
03237 #define BF_SDHC_IRQSTATEN_CEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CEBESEN) & BM_SDHC_IRQSTATEN_CEBESEN)
03238 
03239 /*! @brief Set the CEBESEN field to a new value. */
03240 #define BW_SDHC_IRQSTATEN_CEBESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CEBESEN), v))
03241 /*@}*/
03242 
03243 /*!
03244  * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
03245  *
03246  * Values:
03247  * - 0 - Masked
03248  * - 1 - Enabled
03249  */
03250 /*@{*/
03251 #define BP_SDHC_IRQSTATEN_CIESEN (19U)     /*!< Bit position for SDHC_IRQSTATEN_CIESEN. */
03252 #define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) /*!< Bit mask for SDHC_IRQSTATEN_CIESEN. */
03253 #define BS_SDHC_IRQSTATEN_CIESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN. */
03254 
03255 /*! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field. */
03256 #define BR_SDHC_IRQSTATEN_CIESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN)))
03257 
03258 /*! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN. */
03259 #define BF_SDHC_IRQSTATEN_CIESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_CIESEN) & BM_SDHC_IRQSTATEN_CIESEN)
03260 
03261 /*! @brief Set the CIESEN field to a new value. */
03262 #define BW_SDHC_IRQSTATEN_CIESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_CIESEN), v))
03263 /*@}*/
03264 
03265 /*!
03266  * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
03267  *
03268  * Values:
03269  * - 0 - Masked
03270  * - 1 - Enabled
03271  */
03272 /*@{*/
03273 #define BP_SDHC_IRQSTATEN_DTOESEN (20U)    /*!< Bit position for SDHC_IRQSTATEN_DTOESEN. */
03274 #define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) /*!< Bit mask for SDHC_IRQSTATEN_DTOESEN. */
03275 #define BS_SDHC_IRQSTATEN_DTOESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN. */
03276 
03277 /*! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field. */
03278 #define BR_SDHC_IRQSTATEN_DTOESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN)))
03279 
03280 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN. */
03281 #define BF_SDHC_IRQSTATEN_DTOESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DTOESEN) & BM_SDHC_IRQSTATEN_DTOESEN)
03282 
03283 /*! @brief Set the DTOESEN field to a new value. */
03284 #define BW_SDHC_IRQSTATEN_DTOESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DTOESEN), v))
03285 /*@}*/
03286 
03287 /*!
03288  * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
03289  *
03290  * Values:
03291  * - 0 - Masked
03292  * - 1 - Enabled
03293  */
03294 /*@{*/
03295 #define BP_SDHC_IRQSTATEN_DCESEN (21U)     /*!< Bit position for SDHC_IRQSTATEN_DCESEN. */
03296 #define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) /*!< Bit mask for SDHC_IRQSTATEN_DCESEN. */
03297 #define BS_SDHC_IRQSTATEN_DCESEN (1U)      /*!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN. */
03298 
03299 /*! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field. */
03300 #define BR_SDHC_IRQSTATEN_DCESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN)))
03301 
03302 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN. */
03303 #define BF_SDHC_IRQSTATEN_DCESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DCESEN) & BM_SDHC_IRQSTATEN_DCESEN)
03304 
03305 /*! @brief Set the DCESEN field to a new value. */
03306 #define BW_SDHC_IRQSTATEN_DCESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DCESEN), v))
03307 /*@}*/
03308 
03309 /*!
03310  * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
03311  *
03312  * Values:
03313  * - 0 - Masked
03314  * - 1 - Enabled
03315  */
03316 /*@{*/
03317 #define BP_SDHC_IRQSTATEN_DEBESEN (22U)    /*!< Bit position for SDHC_IRQSTATEN_DEBESEN. */
03318 #define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) /*!< Bit mask for SDHC_IRQSTATEN_DEBESEN. */
03319 #define BS_SDHC_IRQSTATEN_DEBESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN. */
03320 
03321 /*! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field. */
03322 #define BR_SDHC_IRQSTATEN_DEBESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN)))
03323 
03324 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN. */
03325 #define BF_SDHC_IRQSTATEN_DEBESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DEBESEN) & BM_SDHC_IRQSTATEN_DEBESEN)
03326 
03327 /*! @brief Set the DEBESEN field to a new value. */
03328 #define BW_SDHC_IRQSTATEN_DEBESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DEBESEN), v))
03329 /*@}*/
03330 
03331 /*!
03332  * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
03333  *
03334  * Values:
03335  * - 0 - Masked
03336  * - 1 - Enabled
03337  */
03338 /*@{*/
03339 #define BP_SDHC_IRQSTATEN_AC12ESEN (24U)   /*!< Bit position for SDHC_IRQSTATEN_AC12ESEN. */
03340 #define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) /*!< Bit mask for SDHC_IRQSTATEN_AC12ESEN. */
03341 #define BS_SDHC_IRQSTATEN_AC12ESEN (1U)    /*!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN. */
03342 
03343 /*! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field. */
03344 #define BR_SDHC_IRQSTATEN_AC12ESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN)))
03345 
03346 /*! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN. */
03347 #define BF_SDHC_IRQSTATEN_AC12ESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_AC12ESEN) & BM_SDHC_IRQSTATEN_AC12ESEN)
03348 
03349 /*! @brief Set the AC12ESEN field to a new value. */
03350 #define BW_SDHC_IRQSTATEN_AC12ESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_AC12ESEN), v))
03351 /*@}*/
03352 
03353 /*!
03354  * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
03355  *
03356  * Values:
03357  * - 0 - Masked
03358  * - 1 - Enabled
03359  */
03360 /*@{*/
03361 #define BP_SDHC_IRQSTATEN_DMAESEN (28U)    /*!< Bit position for SDHC_IRQSTATEN_DMAESEN. */
03362 #define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) /*!< Bit mask for SDHC_IRQSTATEN_DMAESEN. */
03363 #define BS_SDHC_IRQSTATEN_DMAESEN (1U)     /*!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN. */
03364 
03365 /*! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field. */
03366 #define BR_SDHC_IRQSTATEN_DMAESEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN)))
03367 
03368 /*! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN. */
03369 #define BF_SDHC_IRQSTATEN_DMAESEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSTATEN_DMAESEN) & BM_SDHC_IRQSTATEN_DMAESEN)
03370 
03371 /*! @brief Set the DMAESEN field to a new value. */
03372 #define BW_SDHC_IRQSTATEN_DMAESEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSTATEN_ADDR(x), BP_SDHC_IRQSTATEN_DMAESEN), v))
03373 /*@}*/
03374 
03375 /*******************************************************************************
03376  * HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
03377  ******************************************************************************/
03378 
03379 /*!
03380  * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
03381  *
03382  * Reset value: 0x00000000U
03383  *
03384  * This register is used to select which interrupt status is indicated to the
03385  * host system as the interrupt. All of these status bits share the same interrupt
03386  * line. Setting any of these bits to 1 enables interrupt generation. The
03387  * corresponding status register bit will generate an interrupt when the corresponding
03388  * interrupt signal enable bit is set.
03389  */
03390 typedef union _hw_sdhc_irqsigen
03391 {
03392     uint32_t U;
03393     struct _hw_sdhc_irqsigen_bitfields
03394     {
03395         uint32_t CCIEN : 1;            /*!< [0] Command Complete Interrupt Enable */
03396         uint32_t TCIEN : 1;            /*!< [1] Transfer Complete Interrupt Enable */
03397         uint32_t BGEIEN : 1;           /*!< [2] Block Gap Event Interrupt Enable */
03398         uint32_t DINTIEN : 1;          /*!< [3] DMA Interrupt Enable */
03399         uint32_t BWRIEN : 1;           /*!< [4] Buffer Write Ready Interrupt Enable */
03400         uint32_t BRRIEN : 1;           /*!< [5] Buffer Read Ready Interrupt Enable */
03401         uint32_t CINSIEN : 1;          /*!< [6] Card Insertion Interrupt Enable */
03402         uint32_t CRMIEN : 1;           /*!< [7] Card Removal Interrupt Enable */
03403         uint32_t CINTIEN : 1;          /*!< [8] Card Interrupt Enable */
03404         uint32_t RESERVED0 : 7;        /*!< [15:9]  */
03405         uint32_t CTOEIEN : 1;          /*!< [16] Command Timeout Error Interrupt
03406                                         * Enable */
03407         uint32_t CCEIEN : 1;           /*!< [17] Command CRC Error Interrupt Enable */
03408         uint32_t CEBEIEN : 1;          /*!< [18] Command End Bit Error Interrupt
03409                                         * Enable */
03410         uint32_t CIEIEN : 1;           /*!< [19] Command Index Error Interrupt Enable */
03411         uint32_t DTOEIEN : 1;          /*!< [20] Data Timeout Error Interrupt Enable */
03412         uint32_t DCEIEN : 1;           /*!< [21] Data CRC Error Interrupt Enable */
03413         uint32_t DEBEIEN : 1;          /*!< [22] Data End Bit Error Interrupt Enable */
03414         uint32_t RESERVED1 : 1;        /*!< [23]  */
03415         uint32_t AC12EIEN : 1;         /*!< [24] Auto CMD12 Error Interrupt Enable */
03416         uint32_t RESERVED2 : 3;        /*!< [27:25]  */
03417         uint32_t DMAEIEN : 1;          /*!< [28] DMA Error Interrupt Enable */
03418         uint32_t RESERVED3 : 3;        /*!< [31:29]  */
03419     } B;
03420 } hw_sdhc_irqsigen_t;
03421 
03422 /*!
03423  * @name Constants and macros for entire SDHC_IRQSIGEN register
03424  */
03425 /*@{*/
03426 #define HW_SDHC_IRQSIGEN_ADDR(x) ((x) + 0x38U)
03427 
03428 #define HW_SDHC_IRQSIGEN(x)      (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR(x))
03429 #define HW_SDHC_IRQSIGEN_RD(x)   (ADDRESS_READ(hw_sdhc_irqsigen_t, HW_SDHC_IRQSIGEN_ADDR(x)))
03430 #define HW_SDHC_IRQSIGEN_WR(x, v) (ADDRESS_WRITE(hw_sdhc_irqsigen_t, HW_SDHC_IRQSIGEN_ADDR(x), v))
03431 #define HW_SDHC_IRQSIGEN_SET(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) |  (v)))
03432 #define HW_SDHC_IRQSIGEN_CLR(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) & ~(v)))
03433 #define HW_SDHC_IRQSIGEN_TOG(x, v) (HW_SDHC_IRQSIGEN_WR(x, HW_SDHC_IRQSIGEN_RD(x) ^  (v)))
03434 /*@}*/
03435 
03436 /*
03437  * Constants & macros for individual SDHC_IRQSIGEN bitfields
03438  */
03439 
03440 /*!
03441  * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
03442  *
03443  * Values:
03444  * - 0 - Masked
03445  * - 1 - Enabled
03446  */
03447 /*@{*/
03448 #define BP_SDHC_IRQSIGEN_CCIEN (0U)        /*!< Bit position for SDHC_IRQSIGEN_CCIEN. */
03449 #define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) /*!< Bit mask for SDHC_IRQSIGEN_CCIEN. */
03450 #define BS_SDHC_IRQSIGEN_CCIEN (1U)        /*!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN. */
03451 
03452 /*! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field. */
03453 #define BR_SDHC_IRQSIGEN_CCIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN)))
03454 
03455 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN. */
03456 #define BF_SDHC_IRQSIGEN_CCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCIEN) & BM_SDHC_IRQSIGEN_CCIEN)
03457 
03458 /*! @brief Set the CCIEN field to a new value. */
03459 #define BW_SDHC_IRQSIGEN_CCIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCIEN), v))
03460 /*@}*/
03461 
03462 /*!
03463  * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
03464  *
03465  * Values:
03466  * - 0 - Masked
03467  * - 1 - Enabled
03468  */
03469 /*@{*/
03470 #define BP_SDHC_IRQSIGEN_TCIEN (1U)        /*!< Bit position for SDHC_IRQSIGEN_TCIEN. */
03471 #define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) /*!< Bit mask for SDHC_IRQSIGEN_TCIEN. */
03472 #define BS_SDHC_IRQSIGEN_TCIEN (1U)        /*!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN. */
03473 
03474 /*! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field. */
03475 #define BR_SDHC_IRQSIGEN_TCIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN)))
03476 
03477 /*! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN. */
03478 #define BF_SDHC_IRQSIGEN_TCIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_TCIEN) & BM_SDHC_IRQSIGEN_TCIEN)
03479 
03480 /*! @brief Set the TCIEN field to a new value. */
03481 #define BW_SDHC_IRQSIGEN_TCIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_TCIEN), v))
03482 /*@}*/
03483 
03484 /*!
03485  * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
03486  *
03487  * Values:
03488  * - 0 - Masked
03489  * - 1 - Enabled
03490  */
03491 /*@{*/
03492 #define BP_SDHC_IRQSIGEN_BGEIEN (2U)       /*!< Bit position for SDHC_IRQSIGEN_BGEIEN. */
03493 #define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) /*!< Bit mask for SDHC_IRQSIGEN_BGEIEN. */
03494 #define BS_SDHC_IRQSIGEN_BGEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN. */
03495 
03496 /*! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field. */
03497 #define BR_SDHC_IRQSIGEN_BGEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN)))
03498 
03499 /*! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN. */
03500 #define BF_SDHC_IRQSIGEN_BGEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BGEIEN) & BM_SDHC_IRQSIGEN_BGEIEN)
03501 
03502 /*! @brief Set the BGEIEN field to a new value. */
03503 #define BW_SDHC_IRQSIGEN_BGEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BGEIEN), v))
03504 /*@}*/
03505 
03506 /*!
03507  * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
03508  *
03509  * Values:
03510  * - 0 - Masked
03511  * - 1 - Enabled
03512  */
03513 /*@{*/
03514 #define BP_SDHC_IRQSIGEN_DINTIEN (3U)      /*!< Bit position for SDHC_IRQSIGEN_DINTIEN. */
03515 #define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) /*!< Bit mask for SDHC_IRQSIGEN_DINTIEN. */
03516 #define BS_SDHC_IRQSIGEN_DINTIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN. */
03517 
03518 /*! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field. */
03519 #define BR_SDHC_IRQSIGEN_DINTIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN)))
03520 
03521 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN. */
03522 #define BF_SDHC_IRQSIGEN_DINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DINTIEN) & BM_SDHC_IRQSIGEN_DINTIEN)
03523 
03524 /*! @brief Set the DINTIEN field to a new value. */
03525 #define BW_SDHC_IRQSIGEN_DINTIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DINTIEN), v))
03526 /*@}*/
03527 
03528 /*!
03529  * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
03530  *
03531  * Values:
03532  * - 0 - Masked
03533  * - 1 - Enabled
03534  */
03535 /*@{*/
03536 #define BP_SDHC_IRQSIGEN_BWRIEN (4U)       /*!< Bit position for SDHC_IRQSIGEN_BWRIEN. */
03537 #define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) /*!< Bit mask for SDHC_IRQSIGEN_BWRIEN. */
03538 #define BS_SDHC_IRQSIGEN_BWRIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN. */
03539 
03540 /*! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field. */
03541 #define BR_SDHC_IRQSIGEN_BWRIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN)))
03542 
03543 /*! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN. */
03544 #define BF_SDHC_IRQSIGEN_BWRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BWRIEN) & BM_SDHC_IRQSIGEN_BWRIEN)
03545 
03546 /*! @brief Set the BWRIEN field to a new value. */
03547 #define BW_SDHC_IRQSIGEN_BWRIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BWRIEN), v))
03548 /*@}*/
03549 
03550 /*!
03551  * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
03552  *
03553  * Values:
03554  * - 0 - Masked
03555  * - 1 - Enabled
03556  */
03557 /*@{*/
03558 #define BP_SDHC_IRQSIGEN_BRRIEN (5U)       /*!< Bit position for SDHC_IRQSIGEN_BRRIEN. */
03559 #define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) /*!< Bit mask for SDHC_IRQSIGEN_BRRIEN. */
03560 #define BS_SDHC_IRQSIGEN_BRRIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN. */
03561 
03562 /*! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field. */
03563 #define BR_SDHC_IRQSIGEN_BRRIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN)))
03564 
03565 /*! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN. */
03566 #define BF_SDHC_IRQSIGEN_BRRIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_BRRIEN) & BM_SDHC_IRQSIGEN_BRRIEN)
03567 
03568 /*! @brief Set the BRRIEN field to a new value. */
03569 #define BW_SDHC_IRQSIGEN_BRRIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_BRRIEN), v))
03570 /*@}*/
03571 
03572 /*!
03573  * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
03574  *
03575  * Values:
03576  * - 0 - Masked
03577  * - 1 - Enabled
03578  */
03579 /*@{*/
03580 #define BP_SDHC_IRQSIGEN_CINSIEN (6U)      /*!< Bit position for SDHC_IRQSIGEN_CINSIEN. */
03581 #define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) /*!< Bit mask for SDHC_IRQSIGEN_CINSIEN. */
03582 #define BS_SDHC_IRQSIGEN_CINSIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN. */
03583 
03584 /*! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field. */
03585 #define BR_SDHC_IRQSIGEN_CINSIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN)))
03586 
03587 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN. */
03588 #define BF_SDHC_IRQSIGEN_CINSIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINSIEN) & BM_SDHC_IRQSIGEN_CINSIEN)
03589 
03590 /*! @brief Set the CINSIEN field to a new value. */
03591 #define BW_SDHC_IRQSIGEN_CINSIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINSIEN), v))
03592 /*@}*/
03593 
03594 /*!
03595  * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
03596  *
03597  * Values:
03598  * - 0 - Masked
03599  * - 1 - Enabled
03600  */
03601 /*@{*/
03602 #define BP_SDHC_IRQSIGEN_CRMIEN (7U)       /*!< Bit position for SDHC_IRQSIGEN_CRMIEN. */
03603 #define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) /*!< Bit mask for SDHC_IRQSIGEN_CRMIEN. */
03604 #define BS_SDHC_IRQSIGEN_CRMIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN. */
03605 
03606 /*! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field. */
03607 #define BR_SDHC_IRQSIGEN_CRMIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN)))
03608 
03609 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN. */
03610 #define BF_SDHC_IRQSIGEN_CRMIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CRMIEN) & BM_SDHC_IRQSIGEN_CRMIEN)
03611 
03612 /*! @brief Set the CRMIEN field to a new value. */
03613 #define BW_SDHC_IRQSIGEN_CRMIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CRMIEN), v))
03614 /*@}*/
03615 
03616 /*!
03617  * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
03618  *
03619  * Values:
03620  * - 0 - Masked
03621  * - 1 - Enabled
03622  */
03623 /*@{*/
03624 #define BP_SDHC_IRQSIGEN_CINTIEN (8U)      /*!< Bit position for SDHC_IRQSIGEN_CINTIEN. */
03625 #define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) /*!< Bit mask for SDHC_IRQSIGEN_CINTIEN. */
03626 #define BS_SDHC_IRQSIGEN_CINTIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN. */
03627 
03628 /*! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field. */
03629 #define BR_SDHC_IRQSIGEN_CINTIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN)))
03630 
03631 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN. */
03632 #define BF_SDHC_IRQSIGEN_CINTIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CINTIEN) & BM_SDHC_IRQSIGEN_CINTIEN)
03633 
03634 /*! @brief Set the CINTIEN field to a new value. */
03635 #define BW_SDHC_IRQSIGEN_CINTIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CINTIEN), v))
03636 /*@}*/
03637 
03638 /*!
03639  * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
03640  *
03641  * Values:
03642  * - 0 - Masked
03643  * - 1 - Enabled
03644  */
03645 /*@{*/
03646 #define BP_SDHC_IRQSIGEN_CTOEIEN (16U)     /*!< Bit position for SDHC_IRQSIGEN_CTOEIEN. */
03647 #define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) /*!< Bit mask for SDHC_IRQSIGEN_CTOEIEN. */
03648 #define BS_SDHC_IRQSIGEN_CTOEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN. */
03649 
03650 /*! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field. */
03651 #define BR_SDHC_IRQSIGEN_CTOEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN)))
03652 
03653 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN. */
03654 #define BF_SDHC_IRQSIGEN_CTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CTOEIEN) & BM_SDHC_IRQSIGEN_CTOEIEN)
03655 
03656 /*! @brief Set the CTOEIEN field to a new value. */
03657 #define BW_SDHC_IRQSIGEN_CTOEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CTOEIEN), v))
03658 /*@}*/
03659 
03660 /*!
03661  * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
03662  *
03663  * Values:
03664  * - 0 - Masked
03665  * - 1 - Enabled
03666  */
03667 /*@{*/
03668 #define BP_SDHC_IRQSIGEN_CCEIEN (17U)      /*!< Bit position for SDHC_IRQSIGEN_CCEIEN. */
03669 #define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) /*!< Bit mask for SDHC_IRQSIGEN_CCEIEN. */
03670 #define BS_SDHC_IRQSIGEN_CCEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN. */
03671 
03672 /*! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field. */
03673 #define BR_SDHC_IRQSIGEN_CCEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN)))
03674 
03675 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN. */
03676 #define BF_SDHC_IRQSIGEN_CCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CCEIEN) & BM_SDHC_IRQSIGEN_CCEIEN)
03677 
03678 /*! @brief Set the CCEIEN field to a new value. */
03679 #define BW_SDHC_IRQSIGEN_CCEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CCEIEN), v))
03680 /*@}*/
03681 
03682 /*!
03683  * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
03684  *
03685  * Values:
03686  * - 0 - Masked
03687  * - 1 - Enabled
03688  */
03689 /*@{*/
03690 #define BP_SDHC_IRQSIGEN_CEBEIEN (18U)     /*!< Bit position for SDHC_IRQSIGEN_CEBEIEN. */
03691 #define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) /*!< Bit mask for SDHC_IRQSIGEN_CEBEIEN. */
03692 #define BS_SDHC_IRQSIGEN_CEBEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN. */
03693 
03694 /*! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field. */
03695 #define BR_SDHC_IRQSIGEN_CEBEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN)))
03696 
03697 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN. */
03698 #define BF_SDHC_IRQSIGEN_CEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CEBEIEN) & BM_SDHC_IRQSIGEN_CEBEIEN)
03699 
03700 /*! @brief Set the CEBEIEN field to a new value. */
03701 #define BW_SDHC_IRQSIGEN_CEBEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CEBEIEN), v))
03702 /*@}*/
03703 
03704 /*!
03705  * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
03706  *
03707  * Values:
03708  * - 0 - Masked
03709  * - 1 - Enabled
03710  */
03711 /*@{*/
03712 #define BP_SDHC_IRQSIGEN_CIEIEN (19U)      /*!< Bit position for SDHC_IRQSIGEN_CIEIEN. */
03713 #define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) /*!< Bit mask for SDHC_IRQSIGEN_CIEIEN. */
03714 #define BS_SDHC_IRQSIGEN_CIEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN. */
03715 
03716 /*! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field. */
03717 #define BR_SDHC_IRQSIGEN_CIEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN)))
03718 
03719 /*! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN. */
03720 #define BF_SDHC_IRQSIGEN_CIEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_CIEIEN) & BM_SDHC_IRQSIGEN_CIEIEN)
03721 
03722 /*! @brief Set the CIEIEN field to a new value. */
03723 #define BW_SDHC_IRQSIGEN_CIEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_CIEIEN), v))
03724 /*@}*/
03725 
03726 /*!
03727  * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
03728  *
03729  * Values:
03730  * - 0 - Masked
03731  * - 1 - Enabled
03732  */
03733 /*@{*/
03734 #define BP_SDHC_IRQSIGEN_DTOEIEN (20U)     /*!< Bit position for SDHC_IRQSIGEN_DTOEIEN. */
03735 #define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) /*!< Bit mask for SDHC_IRQSIGEN_DTOEIEN. */
03736 #define BS_SDHC_IRQSIGEN_DTOEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN. */
03737 
03738 /*! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field. */
03739 #define BR_SDHC_IRQSIGEN_DTOEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN)))
03740 
03741 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN. */
03742 #define BF_SDHC_IRQSIGEN_DTOEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DTOEIEN) & BM_SDHC_IRQSIGEN_DTOEIEN)
03743 
03744 /*! @brief Set the DTOEIEN field to a new value. */
03745 #define BW_SDHC_IRQSIGEN_DTOEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DTOEIEN), v))
03746 /*@}*/
03747 
03748 /*!
03749  * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
03750  *
03751  * Values:
03752  * - 0 - Masked
03753  * - 1 - Enabled
03754  */
03755 /*@{*/
03756 #define BP_SDHC_IRQSIGEN_DCEIEN (21U)      /*!< Bit position for SDHC_IRQSIGEN_DCEIEN. */
03757 #define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) /*!< Bit mask for SDHC_IRQSIGEN_DCEIEN. */
03758 #define BS_SDHC_IRQSIGEN_DCEIEN (1U)       /*!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN. */
03759 
03760 /*! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field. */
03761 #define BR_SDHC_IRQSIGEN_DCEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN)))
03762 
03763 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN. */
03764 #define BF_SDHC_IRQSIGEN_DCEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DCEIEN) & BM_SDHC_IRQSIGEN_DCEIEN)
03765 
03766 /*! @brief Set the DCEIEN field to a new value. */
03767 #define BW_SDHC_IRQSIGEN_DCEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DCEIEN), v))
03768 /*@}*/
03769 
03770 /*!
03771  * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
03772  *
03773  * Values:
03774  * - 0 - Masked
03775  * - 1 - Enabled
03776  */
03777 /*@{*/
03778 #define BP_SDHC_IRQSIGEN_DEBEIEN (22U)     /*!< Bit position for SDHC_IRQSIGEN_DEBEIEN. */
03779 #define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) /*!< Bit mask for SDHC_IRQSIGEN_DEBEIEN. */
03780 #define BS_SDHC_IRQSIGEN_DEBEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN. */
03781 
03782 /*! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field. */
03783 #define BR_SDHC_IRQSIGEN_DEBEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN)))
03784 
03785 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN. */
03786 #define BF_SDHC_IRQSIGEN_DEBEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DEBEIEN) & BM_SDHC_IRQSIGEN_DEBEIEN)
03787 
03788 /*! @brief Set the DEBEIEN field to a new value. */
03789 #define BW_SDHC_IRQSIGEN_DEBEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DEBEIEN), v))
03790 /*@}*/
03791 
03792 /*!
03793  * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
03794  *
03795  * Values:
03796  * - 0 - Masked
03797  * - 1 - Enabled
03798  */
03799 /*@{*/
03800 #define BP_SDHC_IRQSIGEN_AC12EIEN (24U)    /*!< Bit position for SDHC_IRQSIGEN_AC12EIEN. */
03801 #define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) /*!< Bit mask for SDHC_IRQSIGEN_AC12EIEN. */
03802 #define BS_SDHC_IRQSIGEN_AC12EIEN (1U)     /*!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN. */
03803 
03804 /*! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field. */
03805 #define BR_SDHC_IRQSIGEN_AC12EIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN)))
03806 
03807 /*! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN. */
03808 #define BF_SDHC_IRQSIGEN_AC12EIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_AC12EIEN) & BM_SDHC_IRQSIGEN_AC12EIEN)
03809 
03810 /*! @brief Set the AC12EIEN field to a new value. */
03811 #define BW_SDHC_IRQSIGEN_AC12EIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_AC12EIEN), v))
03812 /*@}*/
03813 
03814 /*!
03815  * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
03816  *
03817  * Values:
03818  * - 0 - Masked
03819  * - 1 - Enabled
03820  */
03821 /*@{*/
03822 #define BP_SDHC_IRQSIGEN_DMAEIEN (28U)     /*!< Bit position for SDHC_IRQSIGEN_DMAEIEN. */
03823 #define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) /*!< Bit mask for SDHC_IRQSIGEN_DMAEIEN. */
03824 #define BS_SDHC_IRQSIGEN_DMAEIEN (1U)      /*!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN. */
03825 
03826 /*! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field. */
03827 #define BR_SDHC_IRQSIGEN_DMAEIEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN)))
03828 
03829 /*! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN. */
03830 #define BF_SDHC_IRQSIGEN_DMAEIEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_IRQSIGEN_DMAEIEN) & BM_SDHC_IRQSIGEN_DMAEIEN)
03831 
03832 /*! @brief Set the DMAEIEN field to a new value. */
03833 #define BW_SDHC_IRQSIGEN_DMAEIEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_IRQSIGEN_ADDR(x), BP_SDHC_IRQSIGEN_DMAEIEN), v))
03834 /*@}*/
03835 
03836 /*******************************************************************************
03837  * HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
03838  ******************************************************************************/
03839 
03840 /*!
03841  * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
03842  *
03843  * Reset value: 0x00000000U
03844  *
03845  * When the AC12ESEN bit in the Status register is set, the host driver shall
03846  * check this register to identify what kind of error the Auto CMD12 indicated.
03847  * This register is valid only when the Auto CMD12 Error status bit is set. The
03848  * following table shows the relationship between the Auto CMGD12 CRC error and the
03849  * Auto CMD12 command timeout error. Relationship between Command CRC Error and
03850  * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
03851  * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
03852  * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
03853  * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
03854  * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
03855  * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
03856  * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
03857  * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
03858  * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
03859  * command that can't be issued. Clear bit 7 if there is no command to issue. The
03860  * timing for generating the auto CMD12 error and writing to the command register
03861  * are asynchronous. After that, bit 7 shall be sampled when the driver is not
03862  * writing to the command register. So it is suggested to read this register only
03863  * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
03864  * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
03865  * error does not generate an interrupt.
03866  */
03867 typedef union _hw_sdhc_ac12err
03868 {
03869     uint32_t U;
03870     struct _hw_sdhc_ac12err_bitfields
03871     {
03872         uint32_t AC12NE : 1;           /*!< [0] Auto CMD12 Not Executed */
03873         uint32_t AC12TOE : 1;          /*!< [1] Auto CMD12 Timeout Error */
03874         uint32_t AC12EBE : 1;          /*!< [2] Auto CMD12 End Bit Error */
03875         uint32_t AC12CE : 1;           /*!< [3] Auto CMD12 CRC Error */
03876         uint32_t AC12IE : 1;           /*!< [4] Auto CMD12 Index Error */
03877         uint32_t RESERVED0 : 2;        /*!< [6:5]  */
03878         uint32_t CNIBAC12E : 1;        /*!< [7] Command Not Issued By Auto CMD12
03879                                         * Error */
03880         uint32_t RESERVED1 : 24;       /*!< [31:8]  */
03881     } B;
03882 } hw_sdhc_ac12err_t;
03883 
03884 /*!
03885  * @name Constants and macros for entire SDHC_AC12ERR register
03886  */
03887 /*@{*/
03888 #define HW_SDHC_AC12ERR_ADDR(x)  ((x) + 0x3CU)
03889 
03890 #define HW_SDHC_AC12ERR(x)       (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR(x))
03891 #define HW_SDHC_AC12ERR_RD(x)    (ADDRESS_READ(hw_sdhc_ac12err_t, HW_SDHC_AC12ERR_ADDR(x)))
03892 /*@}*/
03893 
03894 /*
03895  * Constants & macros for individual SDHC_AC12ERR bitfields
03896  */
03897 
03898 /*!
03899  * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
03900  *
03901  * If memory multiple block data transfer is not started, due to a command
03902  * error, this bit is not set because it is not necessary to issue an auto CMD12.
03903  * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
03904  * multiple block data transfer due to some error. If this bit is set to 1, other
03905  * error status bits (1-4) have no meaning.
03906  *
03907  * Values:
03908  * - 0 - Executed.
03909  * - 1 - Not executed.
03910  */
03911 /*@{*/
03912 #define BP_SDHC_AC12ERR_AC12NE (0U)        /*!< Bit position for SDHC_AC12ERR_AC12NE. */
03913 #define BM_SDHC_AC12ERR_AC12NE (0x00000001U) /*!< Bit mask for SDHC_AC12ERR_AC12NE. */
03914 #define BS_SDHC_AC12ERR_AC12NE (1U)        /*!< Bit field size in bits for SDHC_AC12ERR_AC12NE. */
03915 
03916 /*! @brief Read current value of the SDHC_AC12ERR_AC12NE field. */
03917 #define BR_SDHC_AC12ERR_AC12NE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12NE)))
03918 /*@}*/
03919 
03920 /*!
03921  * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
03922  *
03923  * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
03924  * the command. If this bit is set to 1, the other error status bits (2-4) have
03925  * no meaning.
03926  *
03927  * Values:
03928  * - 0 - No error.
03929  * - 1 - Time out.
03930  */
03931 /*@{*/
03932 #define BP_SDHC_AC12ERR_AC12TOE (1U)       /*!< Bit position for SDHC_AC12ERR_AC12TOE. */
03933 #define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) /*!< Bit mask for SDHC_AC12ERR_AC12TOE. */
03934 #define BS_SDHC_AC12ERR_AC12TOE (1U)       /*!< Bit field size in bits for SDHC_AC12ERR_AC12TOE. */
03935 
03936 /*! @brief Read current value of the SDHC_AC12ERR_AC12TOE field. */
03937 #define BR_SDHC_AC12ERR_AC12TOE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12TOE)))
03938 /*@}*/
03939 
03940 /*!
03941  * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
03942  *
03943  * Occurs when detecting that the end bit of command response is 0 which must be
03944  * 1.
03945  *
03946  * Values:
03947  * - 0 - No error.
03948  * - 1 - End bit error generated.
03949  */
03950 /*@{*/
03951 #define BP_SDHC_AC12ERR_AC12EBE (2U)       /*!< Bit position for SDHC_AC12ERR_AC12EBE. */
03952 #define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) /*!< Bit mask for SDHC_AC12ERR_AC12EBE. */
03953 #define BS_SDHC_AC12ERR_AC12EBE (1U)       /*!< Bit field size in bits for SDHC_AC12ERR_AC12EBE. */
03954 
03955 /*! @brief Read current value of the SDHC_AC12ERR_AC12EBE field. */
03956 #define BR_SDHC_AC12ERR_AC12EBE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12EBE)))
03957 /*@}*/
03958 
03959 /*!
03960  * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
03961  *
03962  * Occurs when detecting a CRC error in the command response.
03963  *
03964  * Values:
03965  * - 0 - No CRC error.
03966  * - 1 - CRC error met in Auto CMD12 response.
03967  */
03968 /*@{*/
03969 #define BP_SDHC_AC12ERR_AC12CE (3U)        /*!< Bit position for SDHC_AC12ERR_AC12CE. */
03970 #define BM_SDHC_AC12ERR_AC12CE (0x00000008U) /*!< Bit mask for SDHC_AC12ERR_AC12CE. */
03971 #define BS_SDHC_AC12ERR_AC12CE (1U)        /*!< Bit field size in bits for SDHC_AC12ERR_AC12CE. */
03972 
03973 /*! @brief Read current value of the SDHC_AC12ERR_AC12CE field. */
03974 #define BR_SDHC_AC12ERR_AC12CE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12CE)))
03975 /*@}*/
03976 
03977 /*!
03978  * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
03979  *
03980  * Occurs if the command index error occurs in response to a command.
03981  *
03982  * Values:
03983  * - 0 - No error.
03984  * - 1 - Error, the CMD index in response is not CMD12.
03985  */
03986 /*@{*/
03987 #define BP_SDHC_AC12ERR_AC12IE (4U)        /*!< Bit position for SDHC_AC12ERR_AC12IE. */
03988 #define BM_SDHC_AC12ERR_AC12IE (0x00000010U) /*!< Bit mask for SDHC_AC12ERR_AC12IE. */
03989 #define BS_SDHC_AC12ERR_AC12IE (1U)        /*!< Bit field size in bits for SDHC_AC12ERR_AC12IE. */
03990 
03991 /*! @brief Read current value of the SDHC_AC12ERR_AC12IE field. */
03992 #define BR_SDHC_AC12ERR_AC12IE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_AC12IE)))
03993 /*@}*/
03994 
03995 /*!
03996  * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
03997  *
03998  * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
03999  * error (D04-D01) in this register.
04000  *
04001  * Values:
04002  * - 0 - No error.
04003  * - 1 - Not issued.
04004  */
04005 /*@{*/
04006 #define BP_SDHC_AC12ERR_CNIBAC12E (7U)     /*!< Bit position for SDHC_AC12ERR_CNIBAC12E. */
04007 #define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) /*!< Bit mask for SDHC_AC12ERR_CNIBAC12E. */
04008 #define BS_SDHC_AC12ERR_CNIBAC12E (1U)     /*!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E. */
04009 
04010 /*! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field. */
04011 #define BR_SDHC_AC12ERR_CNIBAC12E(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_AC12ERR_ADDR(x), BP_SDHC_AC12ERR_CNIBAC12E)))
04012 /*@}*/
04013 
04014 /*******************************************************************************
04015  * HW_SDHC_HTCAPBLT - Host Controller Capabilities
04016  ******************************************************************************/
04017 
04018 /*!
04019  * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO)
04020  *
04021  * Reset value: 0x07F30000U
04022  *
04023  * This register provides the host driver with information specific to the SDHC
04024  * implementation. The value in this register is the power-on-reset value, and
04025  * does not change with a software reset. Any write to this register is ignored.
04026  */
04027 typedef union _hw_sdhc_htcapblt
04028 {
04029     uint32_t U;
04030     struct _hw_sdhc_htcapblt_bitfields
04031     {
04032         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
04033         uint32_t MBL : 3;              /*!< [18:16] Max Block Length */
04034         uint32_t RESERVED1 : 1;        /*!< [19]  */
04035         uint32_t ADMAS : 1;            /*!< [20] ADMA Support */
04036         uint32_t HSS : 1;              /*!< [21] High Speed Support */
04037         uint32_t DMAS : 1;             /*!< [22] DMA Support */
04038         uint32_t SRS : 1;              /*!< [23] Suspend/Resume Support */
04039         uint32_t VS33 : 1;             /*!< [24] Voltage Support 3.3 V */
04040         uint32_t RESERVED2 : 7;        /*!< [31:25]  */
04041     } B;
04042 } hw_sdhc_htcapblt_t;
04043 
04044 /*!
04045  * @name Constants and macros for entire SDHC_HTCAPBLT register
04046  */
04047 /*@{*/
04048 #define HW_SDHC_HTCAPBLT_ADDR(x) ((x) + 0x40U)
04049 
04050 #define HW_SDHC_HTCAPBLT(x)      (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR(x))
04051 #define HW_SDHC_HTCAPBLT_RD(x)   (ADDRESS_READ(hw_sdhc_htcapblt_t, HW_SDHC_HTCAPBLT_ADDR(x)))
04052 /*@}*/
04053 
04054 /*
04055  * Constants & macros for individual SDHC_HTCAPBLT bitfields
04056  */
04057 
04058 /*!
04059  * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
04060  *
04061  * This value indicates the maximum block size that the host driver can read and
04062  * write to the buffer in the SDHC. The buffer shall transfer block size without
04063  * wait cycles.
04064  *
04065  * Values:
04066  * - 000 - 512 bytes
04067  * - 001 - 1024 bytes
04068  * - 010 - 2048 bytes
04069  * - 011 - 4096 bytes
04070  */
04071 /*@{*/
04072 #define BP_SDHC_HTCAPBLT_MBL (16U)         /*!< Bit position for SDHC_HTCAPBLT_MBL. */
04073 #define BM_SDHC_HTCAPBLT_MBL (0x00070000U) /*!< Bit mask for SDHC_HTCAPBLT_MBL. */
04074 #define BS_SDHC_HTCAPBLT_MBL (3U)          /*!< Bit field size in bits for SDHC_HTCAPBLT_MBL. */
04075 
04076 /*! @brief Read current value of the SDHC_HTCAPBLT_MBL field. */
04077 #define BR_SDHC_HTCAPBLT_MBL(x) (UNION_READ(hw_sdhc_htcapblt_t, HW_SDHC_HTCAPBLT_ADDR(x), U, B.MBL))
04078 /*@}*/
04079 
04080 /*!
04081  * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
04082  *
04083  * This bit indicates whether the SDHC supports the ADMA feature.
04084  *
04085  * Values:
04086  * - 0 - Advanced DMA not supported.
04087  * - 1 - Advanced DMA supported.
04088  */
04089 /*@{*/
04090 #define BP_SDHC_HTCAPBLT_ADMAS (20U)       /*!< Bit position for SDHC_HTCAPBLT_ADMAS. */
04091 #define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) /*!< Bit mask for SDHC_HTCAPBLT_ADMAS. */
04092 #define BS_SDHC_HTCAPBLT_ADMAS (1U)        /*!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS. */
04093 
04094 /*! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field. */
04095 #define BR_SDHC_HTCAPBLT_ADMAS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_ADMAS)))
04096 /*@}*/
04097 
04098 /*!
04099  * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
04100  *
04101  * This bit indicates whether the SDHC supports high speed mode and the host
04102  * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
04103  *
04104  * Values:
04105  * - 0 - High speed not supported.
04106  * - 1 - High speed supported.
04107  */
04108 /*@{*/
04109 #define BP_SDHC_HTCAPBLT_HSS (21U)         /*!< Bit position for SDHC_HTCAPBLT_HSS. */
04110 #define BM_SDHC_HTCAPBLT_HSS (0x00200000U) /*!< Bit mask for SDHC_HTCAPBLT_HSS. */
04111 #define BS_SDHC_HTCAPBLT_HSS (1U)          /*!< Bit field size in bits for SDHC_HTCAPBLT_HSS. */
04112 
04113 /*! @brief Read current value of the SDHC_HTCAPBLT_HSS field. */
04114 #define BR_SDHC_HTCAPBLT_HSS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_HSS)))
04115 /*@}*/
04116 
04117 /*!
04118  * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
04119  *
04120  * This bit indicates whether the SDHC is capable of using the internal DMA to
04121  * transfer data between system memory and the data buffer directly.
04122  *
04123  * Values:
04124  * - 0 - DMA not supported.
04125  * - 1 - DMA supported.
04126  */
04127 /*@{*/
04128 #define BP_SDHC_HTCAPBLT_DMAS (22U)        /*!< Bit position for SDHC_HTCAPBLT_DMAS. */
04129 #define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) /*!< Bit mask for SDHC_HTCAPBLT_DMAS. */
04130 #define BS_SDHC_HTCAPBLT_DMAS (1U)         /*!< Bit field size in bits for SDHC_HTCAPBLT_DMAS. */
04131 
04132 /*! @brief Read current value of the SDHC_HTCAPBLT_DMAS field. */
04133 #define BR_SDHC_HTCAPBLT_DMAS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_DMAS)))
04134 /*@}*/
04135 
04136 /*!
04137  * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
04138  *
04139  * This bit indicates whether the SDHC supports suspend / resume functionality.
04140  * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
04141  * are not supported, and the host driver shall not issue either suspend or
04142  * resume commands.
04143  *
04144  * Values:
04145  * - 0 - Not supported.
04146  * - 1 - Supported.
04147  */
04148 /*@{*/
04149 #define BP_SDHC_HTCAPBLT_SRS (23U)         /*!< Bit position for SDHC_HTCAPBLT_SRS. */
04150 #define BM_SDHC_HTCAPBLT_SRS (0x00800000U) /*!< Bit mask for SDHC_HTCAPBLT_SRS. */
04151 #define BS_SDHC_HTCAPBLT_SRS (1U)          /*!< Bit field size in bits for SDHC_HTCAPBLT_SRS. */
04152 
04153 /*! @brief Read current value of the SDHC_HTCAPBLT_SRS field. */
04154 #define BR_SDHC_HTCAPBLT_SRS(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_SRS)))
04155 /*@}*/
04156 
04157 /*!
04158  * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
04159  *
04160  * This bit shall depend on the host system ability.
04161  *
04162  * Values:
04163  * - 0 - 3.3 V not supported.
04164  * - 1 - 3.3 V supported.
04165  */
04166 /*@{*/
04167 #define BP_SDHC_HTCAPBLT_VS33 (24U)        /*!< Bit position for SDHC_HTCAPBLT_VS33. */
04168 #define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) /*!< Bit mask for SDHC_HTCAPBLT_VS33. */
04169 #define BS_SDHC_HTCAPBLT_VS33 (1U)         /*!< Bit field size in bits for SDHC_HTCAPBLT_VS33. */
04170 
04171 /*! @brief Read current value of the SDHC_HTCAPBLT_VS33 field. */
04172 #define BR_SDHC_HTCAPBLT_VS33(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_HTCAPBLT_ADDR(x), BP_SDHC_HTCAPBLT_VS33)))
04173 /*@}*/
04174 
04175 /*******************************************************************************
04176  * HW_SDHC_WML - Watermark Level Register
04177  ******************************************************************************/
04178 
04179 /*!
04180  * @brief HW_SDHC_WML - Watermark Level Register (RW)
04181  *
04182  * Reset value: 0x00100010U
04183  *
04184  * Both write and read watermark levels (FIFO threshold) are configurable. There
04185  * value can range from 1 to 128 words. Both write and read burst lengths are
04186  * also configurable. There value can range from 1 to 31 words.
04187  */
04188 typedef union _hw_sdhc_wml
04189 {
04190     uint32_t U;
04191     struct _hw_sdhc_wml_bitfields
04192     {
04193         uint32_t RDWML : 8;            /*!< [7:0] Read Watermark Level */
04194         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
04195         uint32_t WRWML : 8;            /*!< [23:16] Write Watermark Level */
04196         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
04197     } B;
04198 } hw_sdhc_wml_t;
04199 
04200 /*!
04201  * @name Constants and macros for entire SDHC_WML register
04202  */
04203 /*@{*/
04204 #define HW_SDHC_WML_ADDR(x)      ((x) + 0x44U)
04205 
04206 #define HW_SDHC_WML(x)           (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR(x))
04207 #define HW_SDHC_WML_RD(x)        (ADDRESS_READ(hw_sdhc_wml_t, HW_SDHC_WML_ADDR(x)))
04208 #define HW_SDHC_WML_WR(x, v)     (ADDRESS_WRITE(hw_sdhc_wml_t, HW_SDHC_WML_ADDR(x), v))
04209 #define HW_SDHC_WML_SET(x, v)    (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) |  (v)))
04210 #define HW_SDHC_WML_CLR(x, v)    (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) & ~(v)))
04211 #define HW_SDHC_WML_TOG(x, v)    (HW_SDHC_WML_WR(x, HW_SDHC_WML_RD(x) ^  (v)))
04212 /*@}*/
04213 
04214 /*
04215  * Constants & macros for individual SDHC_WML bitfields
04216  */
04217 
04218 /*!
04219  * @name Register SDHC_WML, field RDWML[7:0] (RW)
04220  *
04221  * The number of words used as the watermark level (FIFO threshold) in a DMA
04222  * read operation. Also the number of words as a sequence of read bursts in
04223  * back-to-back mode. The maximum legal value for the read water mark level is 128.
04224  */
04225 /*@{*/
04226 #define BP_SDHC_WML_RDWML    (0U)          /*!< Bit position for SDHC_WML_RDWML. */
04227 #define BM_SDHC_WML_RDWML    (0x000000FFU) /*!< Bit mask for SDHC_WML_RDWML. */
04228 #define BS_SDHC_WML_RDWML    (8U)          /*!< Bit field size in bits for SDHC_WML_RDWML. */
04229 
04230 /*! @brief Read current value of the SDHC_WML_RDWML field. */
04231 #define BR_SDHC_WML_RDWML(x) (UNION_READ(hw_sdhc_wml_t, HW_SDHC_WML_ADDR(x), U, B.RDWML))
04232 
04233 /*! @brief Format value for bitfield SDHC_WML_RDWML. */
04234 #define BF_SDHC_WML_RDWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_RDWML) & BM_SDHC_WML_RDWML)
04235 
04236 /*! @brief Set the RDWML field to a new value. */
04237 #define BW_SDHC_WML_RDWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v)))
04238 /*@}*/
04239 
04240 /*!
04241  * @name Register SDHC_WML, field WRWML[23:16] (RW)
04242  *
04243  * The number of words used as the watermark level (FIFO threshold) in a DMA
04244  * write operation. Also the number of words as a sequence of write bursts in
04245  * back-to-back mode. The maximum legal value for the write watermark level is 128.
04246  */
04247 /*@{*/
04248 #define BP_SDHC_WML_WRWML    (16U)         /*!< Bit position for SDHC_WML_WRWML. */
04249 #define BM_SDHC_WML_WRWML    (0x00FF0000U) /*!< Bit mask for SDHC_WML_WRWML. */
04250 #define BS_SDHC_WML_WRWML    (8U)          /*!< Bit field size in bits for SDHC_WML_WRWML. */
04251 
04252 /*! @brief Read current value of the SDHC_WML_WRWML field. */
04253 #define BR_SDHC_WML_WRWML(x) (UNION_READ(hw_sdhc_wml_t, HW_SDHC_WML_ADDR(x), U, B.WRWML))
04254 
04255 /*! @brief Format value for bitfield SDHC_WML_WRWML. */
04256 #define BF_SDHC_WML_WRWML(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_WML_WRWML) & BM_SDHC_WML_WRWML)
04257 
04258 /*! @brief Set the WRWML field to a new value. */
04259 #define BW_SDHC_WML_WRWML(x, v) (HW_SDHC_WML_WR(x, (HW_SDHC_WML_RD(x) & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v)))
04260 /*@}*/
04261 
04262 /*******************************************************************************
04263  * HW_SDHC_FEVT - Force Event register
04264  ******************************************************************************/
04265 
04266 /*!
04267  * @brief HW_SDHC_FEVT - Force Event register (WO)
04268  *
04269  * Reset value: 0x00000000U
04270  *
04271  * The Force Event (FEVT) register is not a physically implemented register.
04272  * Rather, it is an address at which the Interrupt Status register can be written if
04273  * the corresponding bit of the Interrupt Status Enable register is set. This
04274  * register is a write only register and writing 0 to it has no effect. Writing 1
04275  * to this register actually sets the corresponding bit of Interrupt Status
04276  * register. A read from this register always results in 0's. To change the
04277  * corresponding status bits in the interrupt status register, make sure to set
04278  * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
04279  * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
04280  * normal interrupt. The interrupt service routine may skip polling the card
04281  * interrupt factor as the interrupt is selfcleared.
04282  */
04283 typedef union _hw_sdhc_fevt
04284 {
04285     uint32_t U;
04286     struct _hw_sdhc_fevt_bitfields
04287     {
04288         uint32_t AC12NE : 1;           /*!< [0] Force Event Auto Command 12 Not
04289                                         * Executed */
04290         uint32_t AC12TOE : 1;          /*!< [1] Force Event Auto Command 12 Time Out
04291                                         * Error */
04292         uint32_t AC12CE : 1;           /*!< [2] Force Event Auto Command 12 CRC Error */
04293         uint32_t AC12EBE : 1;          /*!< [3] Force Event Auto Command 12 End Bit
04294                                         * Error */
04295         uint32_t AC12IE : 1;           /*!< [4] Force Event Auto Command 12 Index Error
04296                                         * */
04297         uint32_t RESERVED0 : 2;        /*!< [6:5]  */
04298         uint32_t CNIBAC12E : 1;        /*!< [7] Force Event Command Not Executed By
04299                                         * Auto Command 12 Error */
04300         uint32_t RESERVED1 : 8;        /*!< [15:8]  */
04301         uint32_t CTOE : 1;             /*!< [16] Force Event Command Time Out Error */
04302         uint32_t CCE : 1;              /*!< [17] Force Event Command CRC Error */
04303         uint32_t CEBE : 1;             /*!< [18] Force Event Command End Bit Error */
04304         uint32_t CIE : 1;              /*!< [19] Force Event Command Index Error */
04305         uint32_t DTOE : 1;             /*!< [20] Force Event Data Time Out Error */
04306         uint32_t DCE : 1;              /*!< [21] Force Event Data CRC Error */
04307         uint32_t DEBE : 1;             /*!< [22] Force Event Data End Bit Error */
04308         uint32_t RESERVED2 : 1;        /*!< [23]  */
04309         uint32_t AC12E : 1;            /*!< [24] Force Event Auto Command 12 Error */
04310         uint32_t RESERVED3 : 3;        /*!< [27:25]  */
04311         uint32_t DMAE : 1;             /*!< [28] Force Event DMA Error */
04312         uint32_t RESERVED4 : 2;        /*!< [30:29]  */
04313         uint32_t CINT : 1;             /*!< [31] Force Event Card Interrupt */
04314     } B;
04315 } hw_sdhc_fevt_t;
04316 
04317 /*!
04318  * @name Constants and macros for entire SDHC_FEVT register
04319  */
04320 /*@{*/
04321 #define HW_SDHC_FEVT_ADDR(x)     ((x) + 0x50U)
04322 
04323 #define HW_SDHC_FEVT(x)          (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR(x))
04324 #define HW_SDHC_FEVT_RD(x)       (ADDRESS_READ(hw_sdhc_fevt_t, HW_SDHC_FEVT_ADDR(x)))
04325 #define HW_SDHC_FEVT_WR(x, v)    (ADDRESS_WRITE(hw_sdhc_fevt_t, HW_SDHC_FEVT_ADDR(x), v))
04326 /*@}*/
04327 
04328 /*
04329  * Constants & macros for individual SDHC_FEVT bitfields
04330  */
04331 
04332 /*!
04333  * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
04334  *
04335  * Forces AC12ERR[AC12NE] to be set.
04336  */
04337 /*@{*/
04338 #define BP_SDHC_FEVT_AC12NE  (0U)          /*!< Bit position for SDHC_FEVT_AC12NE. */
04339 #define BM_SDHC_FEVT_AC12NE  (0x00000001U) /*!< Bit mask for SDHC_FEVT_AC12NE. */
04340 #define BS_SDHC_FEVT_AC12NE  (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12NE. */
04341 
04342 /*! @brief Format value for bitfield SDHC_FEVT_AC12NE. */
04343 #define BF_SDHC_FEVT_AC12NE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12NE) & BM_SDHC_FEVT_AC12NE)
04344 
04345 /*! @brief Set the AC12NE field to a new value. */
04346 #define BW_SDHC_FEVT_AC12NE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12NE), v))
04347 /*@}*/
04348 
04349 /*!
04350  * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
04351  *
04352  * Forces AC12ERR[AC12TOE] to be set.
04353  */
04354 /*@{*/
04355 #define BP_SDHC_FEVT_AC12TOE (1U)          /*!< Bit position for SDHC_FEVT_AC12TOE. */
04356 #define BM_SDHC_FEVT_AC12TOE (0x00000002U) /*!< Bit mask for SDHC_FEVT_AC12TOE. */
04357 #define BS_SDHC_FEVT_AC12TOE (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12TOE. */
04358 
04359 /*! @brief Format value for bitfield SDHC_FEVT_AC12TOE. */
04360 #define BF_SDHC_FEVT_AC12TOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12TOE) & BM_SDHC_FEVT_AC12TOE)
04361 
04362 /*! @brief Set the AC12TOE field to a new value. */
04363 #define BW_SDHC_FEVT_AC12TOE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12TOE), v))
04364 /*@}*/
04365 
04366 /*!
04367  * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
04368  *
04369  * Forces AC12ERR[AC12CE] to be set.
04370  */
04371 /*@{*/
04372 #define BP_SDHC_FEVT_AC12CE  (2U)          /*!< Bit position for SDHC_FEVT_AC12CE. */
04373 #define BM_SDHC_FEVT_AC12CE  (0x00000004U) /*!< Bit mask for SDHC_FEVT_AC12CE. */
04374 #define BS_SDHC_FEVT_AC12CE  (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12CE. */
04375 
04376 /*! @brief Format value for bitfield SDHC_FEVT_AC12CE. */
04377 #define BF_SDHC_FEVT_AC12CE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12CE) & BM_SDHC_FEVT_AC12CE)
04378 
04379 /*! @brief Set the AC12CE field to a new value. */
04380 #define BW_SDHC_FEVT_AC12CE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12CE), v))
04381 /*@}*/
04382 
04383 /*!
04384  * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
04385  *
04386  * Forces AC12ERR[AC12EBE] to be set.
04387  */
04388 /*@{*/
04389 #define BP_SDHC_FEVT_AC12EBE (3U)          /*!< Bit position for SDHC_FEVT_AC12EBE. */
04390 #define BM_SDHC_FEVT_AC12EBE (0x00000008U) /*!< Bit mask for SDHC_FEVT_AC12EBE. */
04391 #define BS_SDHC_FEVT_AC12EBE (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12EBE. */
04392 
04393 /*! @brief Format value for bitfield SDHC_FEVT_AC12EBE. */
04394 #define BF_SDHC_FEVT_AC12EBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12EBE) & BM_SDHC_FEVT_AC12EBE)
04395 
04396 /*! @brief Set the AC12EBE field to a new value. */
04397 #define BW_SDHC_FEVT_AC12EBE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12EBE), v))
04398 /*@}*/
04399 
04400 /*!
04401  * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
04402  *
04403  * Forces AC12ERR[AC12IE] to be set.
04404  */
04405 /*@{*/
04406 #define BP_SDHC_FEVT_AC12IE  (4U)          /*!< Bit position for SDHC_FEVT_AC12IE. */
04407 #define BM_SDHC_FEVT_AC12IE  (0x00000010U) /*!< Bit mask for SDHC_FEVT_AC12IE. */
04408 #define BS_SDHC_FEVT_AC12IE  (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12IE. */
04409 
04410 /*! @brief Format value for bitfield SDHC_FEVT_AC12IE. */
04411 #define BF_SDHC_FEVT_AC12IE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12IE) & BM_SDHC_FEVT_AC12IE)
04412 
04413 /*! @brief Set the AC12IE field to a new value. */
04414 #define BW_SDHC_FEVT_AC12IE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12IE), v))
04415 /*@}*/
04416 
04417 /*!
04418  * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
04419  *
04420  * Forces AC12ERR[CNIBAC12E] to be set.
04421  */
04422 /*@{*/
04423 #define BP_SDHC_FEVT_CNIBAC12E (7U)        /*!< Bit position for SDHC_FEVT_CNIBAC12E. */
04424 #define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) /*!< Bit mask for SDHC_FEVT_CNIBAC12E. */
04425 #define BS_SDHC_FEVT_CNIBAC12E (1U)        /*!< Bit field size in bits for SDHC_FEVT_CNIBAC12E. */
04426 
04427 /*! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E. */
04428 #define BF_SDHC_FEVT_CNIBAC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CNIBAC12E) & BM_SDHC_FEVT_CNIBAC12E)
04429 
04430 /*! @brief Set the CNIBAC12E field to a new value. */
04431 #define BW_SDHC_FEVT_CNIBAC12E(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CNIBAC12E), v))
04432 /*@}*/
04433 
04434 /*!
04435  * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
04436  *
04437  * Forces IRQSTAT[CTOE] to be set.
04438  */
04439 /*@{*/
04440 #define BP_SDHC_FEVT_CTOE    (16U)         /*!< Bit position for SDHC_FEVT_CTOE. */
04441 #define BM_SDHC_FEVT_CTOE    (0x00010000U) /*!< Bit mask for SDHC_FEVT_CTOE. */
04442 #define BS_SDHC_FEVT_CTOE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_CTOE. */
04443 
04444 /*! @brief Format value for bitfield SDHC_FEVT_CTOE. */
04445 #define BF_SDHC_FEVT_CTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CTOE) & BM_SDHC_FEVT_CTOE)
04446 
04447 /*! @brief Set the CTOE field to a new value. */
04448 #define BW_SDHC_FEVT_CTOE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CTOE), v))
04449 /*@}*/
04450 
04451 /*!
04452  * @name Register SDHC_FEVT, field CCE[17] (WORZ)
04453  *
04454  * Forces IRQSTAT[CCE] to be set.
04455  */
04456 /*@{*/
04457 #define BP_SDHC_FEVT_CCE     (17U)         /*!< Bit position for SDHC_FEVT_CCE. */
04458 #define BM_SDHC_FEVT_CCE     (0x00020000U) /*!< Bit mask for SDHC_FEVT_CCE. */
04459 #define BS_SDHC_FEVT_CCE     (1U)          /*!< Bit field size in bits for SDHC_FEVT_CCE. */
04460 
04461 /*! @brief Format value for bitfield SDHC_FEVT_CCE. */
04462 #define BF_SDHC_FEVT_CCE(v)  ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CCE) & BM_SDHC_FEVT_CCE)
04463 
04464 /*! @brief Set the CCE field to a new value. */
04465 #define BW_SDHC_FEVT_CCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CCE), v))
04466 /*@}*/
04467 
04468 /*!
04469  * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
04470  *
04471  * Forces IRQSTAT[CEBE] to be set.
04472  */
04473 /*@{*/
04474 #define BP_SDHC_FEVT_CEBE    (18U)         /*!< Bit position for SDHC_FEVT_CEBE. */
04475 #define BM_SDHC_FEVT_CEBE    (0x00040000U) /*!< Bit mask for SDHC_FEVT_CEBE. */
04476 #define BS_SDHC_FEVT_CEBE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_CEBE. */
04477 
04478 /*! @brief Format value for bitfield SDHC_FEVT_CEBE. */
04479 #define BF_SDHC_FEVT_CEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CEBE) & BM_SDHC_FEVT_CEBE)
04480 
04481 /*! @brief Set the CEBE field to a new value. */
04482 #define BW_SDHC_FEVT_CEBE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CEBE), v))
04483 /*@}*/
04484 
04485 /*!
04486  * @name Register SDHC_FEVT, field CIE[19] (WORZ)
04487  *
04488  * Forces IRQSTAT[CCE] to be set.
04489  */
04490 /*@{*/
04491 #define BP_SDHC_FEVT_CIE     (19U)         /*!< Bit position for SDHC_FEVT_CIE. */
04492 #define BM_SDHC_FEVT_CIE     (0x00080000U) /*!< Bit mask for SDHC_FEVT_CIE. */
04493 #define BS_SDHC_FEVT_CIE     (1U)          /*!< Bit field size in bits for SDHC_FEVT_CIE. */
04494 
04495 /*! @brief Format value for bitfield SDHC_FEVT_CIE. */
04496 #define BF_SDHC_FEVT_CIE(v)  ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CIE) & BM_SDHC_FEVT_CIE)
04497 
04498 /*! @brief Set the CIE field to a new value. */
04499 #define BW_SDHC_FEVT_CIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CIE), v))
04500 /*@}*/
04501 
04502 /*!
04503  * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
04504  *
04505  * Forces IRQSTAT[DTOE] to be set.
04506  */
04507 /*@{*/
04508 #define BP_SDHC_FEVT_DTOE    (20U)         /*!< Bit position for SDHC_FEVT_DTOE. */
04509 #define BM_SDHC_FEVT_DTOE    (0x00100000U) /*!< Bit mask for SDHC_FEVT_DTOE. */
04510 #define BS_SDHC_FEVT_DTOE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_DTOE. */
04511 
04512 /*! @brief Format value for bitfield SDHC_FEVT_DTOE. */
04513 #define BF_SDHC_FEVT_DTOE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DTOE) & BM_SDHC_FEVT_DTOE)
04514 
04515 /*! @brief Set the DTOE field to a new value. */
04516 #define BW_SDHC_FEVT_DTOE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DTOE), v))
04517 /*@}*/
04518 
04519 /*!
04520  * @name Register SDHC_FEVT, field DCE[21] (WORZ)
04521  *
04522  * Forces IRQSTAT[DCE] to be set.
04523  */
04524 /*@{*/
04525 #define BP_SDHC_FEVT_DCE     (21U)         /*!< Bit position for SDHC_FEVT_DCE. */
04526 #define BM_SDHC_FEVT_DCE     (0x00200000U) /*!< Bit mask for SDHC_FEVT_DCE. */
04527 #define BS_SDHC_FEVT_DCE     (1U)          /*!< Bit field size in bits for SDHC_FEVT_DCE. */
04528 
04529 /*! @brief Format value for bitfield SDHC_FEVT_DCE. */
04530 #define BF_SDHC_FEVT_DCE(v)  ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DCE) & BM_SDHC_FEVT_DCE)
04531 
04532 /*! @brief Set the DCE field to a new value. */
04533 #define BW_SDHC_FEVT_DCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DCE), v))
04534 /*@}*/
04535 
04536 /*!
04537  * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
04538  *
04539  * Forces IRQSTAT[DEBE] to be set.
04540  */
04541 /*@{*/
04542 #define BP_SDHC_FEVT_DEBE    (22U)         /*!< Bit position for SDHC_FEVT_DEBE. */
04543 #define BM_SDHC_FEVT_DEBE    (0x00400000U) /*!< Bit mask for SDHC_FEVT_DEBE. */
04544 #define BS_SDHC_FEVT_DEBE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_DEBE. */
04545 
04546 /*! @brief Format value for bitfield SDHC_FEVT_DEBE. */
04547 #define BF_SDHC_FEVT_DEBE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DEBE) & BM_SDHC_FEVT_DEBE)
04548 
04549 /*! @brief Set the DEBE field to a new value. */
04550 #define BW_SDHC_FEVT_DEBE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DEBE), v))
04551 /*@}*/
04552 
04553 /*!
04554  * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
04555  *
04556  * Forces IRQSTAT[AC12E] to be set.
04557  */
04558 /*@{*/
04559 #define BP_SDHC_FEVT_AC12E   (24U)         /*!< Bit position for SDHC_FEVT_AC12E. */
04560 #define BM_SDHC_FEVT_AC12E   (0x01000000U) /*!< Bit mask for SDHC_FEVT_AC12E. */
04561 #define BS_SDHC_FEVT_AC12E   (1U)          /*!< Bit field size in bits for SDHC_FEVT_AC12E. */
04562 
04563 /*! @brief Format value for bitfield SDHC_FEVT_AC12E. */
04564 #define BF_SDHC_FEVT_AC12E(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_AC12E) & BM_SDHC_FEVT_AC12E)
04565 
04566 /*! @brief Set the AC12E field to a new value. */
04567 #define BW_SDHC_FEVT_AC12E(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_AC12E), v))
04568 /*@}*/
04569 
04570 /*!
04571  * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
04572  *
04573  * Forces the DMAE bit of Interrupt Status Register to be set.
04574  */
04575 /*@{*/
04576 #define BP_SDHC_FEVT_DMAE    (28U)         /*!< Bit position for SDHC_FEVT_DMAE. */
04577 #define BM_SDHC_FEVT_DMAE    (0x10000000U) /*!< Bit mask for SDHC_FEVT_DMAE. */
04578 #define BS_SDHC_FEVT_DMAE    (1U)          /*!< Bit field size in bits for SDHC_FEVT_DMAE. */
04579 
04580 /*! @brief Format value for bitfield SDHC_FEVT_DMAE. */
04581 #define BF_SDHC_FEVT_DMAE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_DMAE) & BM_SDHC_FEVT_DMAE)
04582 
04583 /*! @brief Set the DMAE field to a new value. */
04584 #define BW_SDHC_FEVT_DMAE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_DMAE), v))
04585 /*@}*/
04586 
04587 /*!
04588  * @name Register SDHC_FEVT, field CINT[31] (WORZ)
04589  *
04590  * Writing 1 to this bit generates a short low-level pulse on the internal
04591  * DAT[1] line, as if a self-clearing interrupt was received from the external card.
04592  * If enabled, the CINT bit will be set and the interrupt service routine may
04593  * treat this interrupt as a normal interrupt from the external card.
04594  */
04595 /*@{*/
04596 #define BP_SDHC_FEVT_CINT    (31U)         /*!< Bit position for SDHC_FEVT_CINT. */
04597 #define BM_SDHC_FEVT_CINT    (0x80000000U) /*!< Bit mask for SDHC_FEVT_CINT. */
04598 #define BS_SDHC_FEVT_CINT    (1U)          /*!< Bit field size in bits for SDHC_FEVT_CINT. */
04599 
04600 /*! @brief Format value for bitfield SDHC_FEVT_CINT. */
04601 #define BF_SDHC_FEVT_CINT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_FEVT_CINT) & BM_SDHC_FEVT_CINT)
04602 
04603 /*! @brief Set the CINT field to a new value. */
04604 #define BW_SDHC_FEVT_CINT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_FEVT_ADDR(x), BP_SDHC_FEVT_CINT), v))
04605 /*@}*/
04606 
04607 /*******************************************************************************
04608  * HW_SDHC_ADMAES - ADMA Error Status register
04609  ******************************************************************************/
04610 
04611 /*!
04612  * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO)
04613  *
04614  * Reset value: 0x00000000U
04615  *
04616  * When an ADMA error interrupt has occurred, the ADMA Error States field in
04617  * this register holds the ADMA state and the ADMA System Address register holds the
04618  * address around the error descriptor. For recovering from this error, the host
04619  * driver requires the ADMA state to identify the error descriptor address as
04620  * follows: ST_STOP: Previous location set in the ADMA System Address register is
04621  * the error descriptor address. ST_FDS: Current location set in the ADMA System
04622  * Address register is the error descriptor address. ST_CADR: This state is never
04623  * set because it only increments the descriptor pointer and doesn't generate an
04624  * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
04625  * is the error descriptor address. In case of a write operation, the host driver
04626  * must use the ACMD22 to get the number of the written block, rather than using
04627  * this information, because unwritten data may exist in the host controller.
04628  * The host controller generates the ADMA error interrupt when it detects invalid
04629  * descriptor data (valid = 0) in the ST_FDS state. The host driver can
04630  * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
04631  * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
04632  * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
04633  * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
04634  * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
04635  * (Transfer Data) Holds the address of the next executable descriptor command
04636  */
04637 typedef union _hw_sdhc_admaes
04638 {
04639     uint32_t U;
04640     struct _hw_sdhc_admaes_bitfields
04641     {
04642         uint32_t ADMAES : 2;           /*!< [1:0] ADMA Error State (When ADMA Error Is
04643                                         * Occurred.) */
04644         uint32_t ADMALME : 1;          /*!< [2] ADMA Length Mismatch Error */
04645         uint32_t ADMADCE : 1;          /*!< [3] ADMA Descriptor Error */
04646         uint32_t RESERVED0 : 28;       /*!< [31:4]  */
04647     } B;
04648 } hw_sdhc_admaes_t;
04649 
04650 /*!
04651  * @name Constants and macros for entire SDHC_ADMAES register
04652  */
04653 /*@{*/
04654 #define HW_SDHC_ADMAES_ADDR(x)   ((x) + 0x54U)
04655 
04656 #define HW_SDHC_ADMAES(x)        (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR(x))
04657 #define HW_SDHC_ADMAES_RD(x)     (ADDRESS_READ(hw_sdhc_admaes_t, HW_SDHC_ADMAES_ADDR(x)))
04658 /*@}*/
04659 
04660 /*
04661  * Constants & macros for individual SDHC_ADMAES bitfields
04662  */
04663 
04664 /*!
04665  * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
04666  *
04667  * Indicates the state of the ADMA when an error has occurred during an ADMA
04668  * data transfer.
04669  */
04670 /*@{*/
04671 #define BP_SDHC_ADMAES_ADMAES (0U)         /*!< Bit position for SDHC_ADMAES_ADMAES. */
04672 #define BM_SDHC_ADMAES_ADMAES (0x00000003U) /*!< Bit mask for SDHC_ADMAES_ADMAES. */
04673 #define BS_SDHC_ADMAES_ADMAES (2U)         /*!< Bit field size in bits for SDHC_ADMAES_ADMAES. */
04674 
04675 /*! @brief Read current value of the SDHC_ADMAES_ADMAES field. */
04676 #define BR_SDHC_ADMAES_ADMAES(x) (UNION_READ(hw_sdhc_admaes_t, HW_SDHC_ADMAES_ADDR(x), U, B.ADMAES))
04677 /*@}*/
04678 
04679 /*!
04680  * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
04681  *
04682  * This error occurs in the following 2 cases: While the block count enable is
04683  * being set, the total data length specified by the descriptor table is different
04684  * from that specified by the block count and block length. Total data length
04685  * can not be divided by the block length.
04686  *
04687  * Values:
04688  * - 0 - No error.
04689  * - 1 - Error.
04690  */
04691 /*@{*/
04692 #define BP_SDHC_ADMAES_ADMALME (2U)        /*!< Bit position for SDHC_ADMAES_ADMALME. */
04693 #define BM_SDHC_ADMAES_ADMALME (0x00000004U) /*!< Bit mask for SDHC_ADMAES_ADMALME. */
04694 #define BS_SDHC_ADMAES_ADMALME (1U)        /*!< Bit field size in bits for SDHC_ADMAES_ADMALME. */
04695 
04696 /*! @brief Read current value of the SDHC_ADMAES_ADMALME field. */
04697 #define BR_SDHC_ADMAES_ADMALME(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMALME)))
04698 /*@}*/
04699 
04700 /*!
04701  * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
04702  *
04703  * This error occurs when an invalid descriptor is fetched by ADMA.
04704  *
04705  * Values:
04706  * - 0 - No error.
04707  * - 1 - Error.
04708  */
04709 /*@{*/
04710 #define BP_SDHC_ADMAES_ADMADCE (3U)        /*!< Bit position for SDHC_ADMAES_ADMADCE. */
04711 #define BM_SDHC_ADMAES_ADMADCE (0x00000008U) /*!< Bit mask for SDHC_ADMAES_ADMADCE. */
04712 #define BS_SDHC_ADMAES_ADMADCE (1U)        /*!< Bit field size in bits for SDHC_ADMAES_ADMADCE. */
04713 
04714 /*! @brief Read current value of the SDHC_ADMAES_ADMADCE field. */
04715 #define BR_SDHC_ADMAES_ADMADCE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_ADMAES_ADDR(x), BP_SDHC_ADMAES_ADMADCE)))
04716 /*@}*/
04717 
04718 /*******************************************************************************
04719  * HW_SDHC_ADSADDR - ADMA System Addressregister
04720  ******************************************************************************/
04721 
04722 /*!
04723  * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW)
04724  *
04725  * Reset value: 0x00000000U
04726  *
04727  * This register contains the physical system memory address used for ADMA
04728  * transfers.
04729  */
04730 typedef union _hw_sdhc_adsaddr
04731 {
04732     uint32_t U;
04733     struct _hw_sdhc_adsaddr_bitfields
04734     {
04735         uint32_t RESERVED0 : 2;        /*!< [1:0]  */
04736         uint32_t ADSADDR : 30;         /*!< [31:2] ADMA System Address */
04737     } B;
04738 } hw_sdhc_adsaddr_t;
04739 
04740 /*!
04741  * @name Constants and macros for entire SDHC_ADSADDR register
04742  */
04743 /*@{*/
04744 #define HW_SDHC_ADSADDR_ADDR(x)  ((x) + 0x58U)
04745 
04746 #define HW_SDHC_ADSADDR(x)       (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR(x))
04747 #define HW_SDHC_ADSADDR_RD(x)    (ADDRESS_READ(hw_sdhc_adsaddr_t, HW_SDHC_ADSADDR_ADDR(x)))
04748 #define HW_SDHC_ADSADDR_WR(x, v) (ADDRESS_WRITE(hw_sdhc_adsaddr_t, HW_SDHC_ADSADDR_ADDR(x), v))
04749 #define HW_SDHC_ADSADDR_SET(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) |  (v)))
04750 #define HW_SDHC_ADSADDR_CLR(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) & ~(v)))
04751 #define HW_SDHC_ADSADDR_TOG(x, v) (HW_SDHC_ADSADDR_WR(x, HW_SDHC_ADSADDR_RD(x) ^  (v)))
04752 /*@}*/
04753 
04754 /*
04755  * Constants & macros for individual SDHC_ADSADDR bitfields
04756  */
04757 
04758 /*!
04759  * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
04760  *
04761  * Holds the word address of the executing command in the descriptor table. At
04762  * the start of ADMA, the host driver shall set the start address of the
04763  * Descriptor table. The ADMA engine increments this register address whenever fetching a
04764  * descriptor command. When the ADMA is stopped at the block gap, this register
04765  * indicates the address of the next executable descriptor command. When the ADMA
04766  * error interrupt is generated, this register shall hold the valid descriptor
04767  * address depending on the ADMA state. The lower 2 bits of this register is tied
04768  * to '0' so the ADMA address is always word-aligned. Because this register
04769  * supports dynamic address reflecting, when TC bit is set, it automatically alters the
04770  * value of internal address counter, so SW cannot change this register when TC
04771  * bit is set.
04772  */
04773 /*@{*/
04774 #define BP_SDHC_ADSADDR_ADSADDR (2U)       /*!< Bit position for SDHC_ADSADDR_ADSADDR. */
04775 #define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) /*!< Bit mask for SDHC_ADSADDR_ADSADDR. */
04776 #define BS_SDHC_ADSADDR_ADSADDR (30U)      /*!< Bit field size in bits for SDHC_ADSADDR_ADSADDR. */
04777 
04778 /*! @brief Read current value of the SDHC_ADSADDR_ADSADDR field. */
04779 #define BR_SDHC_ADSADDR_ADSADDR(x) (UNION_READ(hw_sdhc_adsaddr_t, HW_SDHC_ADSADDR_ADDR(x), U, B.ADSADDR))
04780 
04781 /*! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR. */
04782 #define BF_SDHC_ADSADDR_ADSADDR(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_ADSADDR_ADSADDR) & BM_SDHC_ADSADDR_ADSADDR)
04783 
04784 /*! @brief Set the ADSADDR field to a new value. */
04785 #define BW_SDHC_ADSADDR_ADSADDR(x, v) (HW_SDHC_ADSADDR_WR(x, (HW_SDHC_ADSADDR_RD(x) & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v)))
04786 /*@}*/
04787 
04788 /*******************************************************************************
04789  * HW_SDHC_VENDOR - Vendor Specific register
04790  ******************************************************************************/
04791 
04792 /*!
04793  * @brief HW_SDHC_VENDOR - Vendor Specific register (RW)
04794  *
04795  * Reset value: 0x00000001U
04796  *
04797  * This register contains the vendor-specific control/status register.
04798  */
04799 typedef union _hw_sdhc_vendor
04800 {
04801     uint32_t U;
04802     struct _hw_sdhc_vendor_bitfields
04803     {
04804         uint32_t EXTDMAEN : 1;         /*!< [0] External DMA Request Enable */
04805         uint32_t EXBLKNU : 1;          /*!< [1] Exact Block Number Block Read Enable
04806                                         * For SDIO CMD53 */
04807         uint32_t RESERVED0 : 14;       /*!< [15:2]  */
04808         uint32_t INTSTVAL : 8;         /*!< [23:16] Internal State Value */
04809         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
04810     } B;
04811 } hw_sdhc_vendor_t;
04812 
04813 /*!
04814  * @name Constants and macros for entire SDHC_VENDOR register
04815  */
04816 /*@{*/
04817 #define HW_SDHC_VENDOR_ADDR(x)   ((x) + 0xC0U)
04818 
04819 #define HW_SDHC_VENDOR(x)        (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR(x))
04820 #define HW_SDHC_VENDOR_RD(x)     (ADDRESS_READ(hw_sdhc_vendor_t, HW_SDHC_VENDOR_ADDR(x)))
04821 #define HW_SDHC_VENDOR_WR(x, v)  (ADDRESS_WRITE(hw_sdhc_vendor_t, HW_SDHC_VENDOR_ADDR(x), v))
04822 #define HW_SDHC_VENDOR_SET(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) |  (v)))
04823 #define HW_SDHC_VENDOR_CLR(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) & ~(v)))
04824 #define HW_SDHC_VENDOR_TOG(x, v) (HW_SDHC_VENDOR_WR(x, HW_SDHC_VENDOR_RD(x) ^  (v)))
04825 /*@}*/
04826 
04827 /*
04828  * Constants & macros for individual SDHC_VENDOR bitfields
04829  */
04830 
04831 /*!
04832  * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
04833  *
04834  * Enables the request to external DMA. When the internal DMA (either simple DMA
04835  * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
04836  * request when the internal buffer is ready. This bit is particularly useful when
04837  * transferring data by CPU polling mode, and it is not allowed to send out the
04838  * external DMA request. By default, this bit is set.
04839  *
04840  * Values:
04841  * - 0 - In any scenario, SDHC does not send out the external DMA request.
04842  * - 1 - When internal DMA is not active, the external DMA request will be sent
04843  *     out.
04844  */
04845 /*@{*/
04846 #define BP_SDHC_VENDOR_EXTDMAEN (0U)       /*!< Bit position for SDHC_VENDOR_EXTDMAEN. */
04847 #define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) /*!< Bit mask for SDHC_VENDOR_EXTDMAEN. */
04848 #define BS_SDHC_VENDOR_EXTDMAEN (1U)       /*!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN. */
04849 
04850 /*! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field. */
04851 #define BR_SDHC_VENDOR_EXTDMAEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN)))
04852 
04853 /*! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN. */
04854 #define BF_SDHC_VENDOR_EXTDMAEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXTDMAEN) & BM_SDHC_VENDOR_EXTDMAEN)
04855 
04856 /*! @brief Set the EXTDMAEN field to a new value. */
04857 #define BW_SDHC_VENDOR_EXTDMAEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXTDMAEN), v))
04858 /*@}*/
04859 
04860 /*!
04861  * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
04862  *
04863  * This bit must be set before S/W issues CMD53 multi-block read with exact
04864  * block number. This bit must not be set if the CMD53 multi-block read is not exact
04865  * block number.
04866  *
04867  * Values:
04868  * - 0 - None exact block read.
04869  * - 1 - Exact block read for SDIO CMD53.
04870  */
04871 /*@{*/
04872 #define BP_SDHC_VENDOR_EXBLKNU (1U)        /*!< Bit position for SDHC_VENDOR_EXBLKNU. */
04873 #define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) /*!< Bit mask for SDHC_VENDOR_EXBLKNU. */
04874 #define BS_SDHC_VENDOR_EXBLKNU (1U)        /*!< Bit field size in bits for SDHC_VENDOR_EXBLKNU. */
04875 
04876 /*! @brief Read current value of the SDHC_VENDOR_EXBLKNU field. */
04877 #define BR_SDHC_VENDOR_EXBLKNU(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU)))
04878 
04879 /*! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU. */
04880 #define BF_SDHC_VENDOR_EXBLKNU(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_VENDOR_EXBLKNU) & BM_SDHC_VENDOR_EXBLKNU)
04881 
04882 /*! @brief Set the EXBLKNU field to a new value. */
04883 #define BW_SDHC_VENDOR_EXBLKNU(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_VENDOR_ADDR(x), BP_SDHC_VENDOR_EXBLKNU), v))
04884 /*@}*/
04885 
04886 /*!
04887  * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
04888  *
04889  * Internal state value, reflecting the corresponding state value selected by
04890  * Debug Select field. This field is read-only and write to this field does not
04891  * have effect.
04892  */
04893 /*@{*/
04894 #define BP_SDHC_VENDOR_INTSTVAL (16U)      /*!< Bit position for SDHC_VENDOR_INTSTVAL. */
04895 #define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) /*!< Bit mask for SDHC_VENDOR_INTSTVAL. */
04896 #define BS_SDHC_VENDOR_INTSTVAL (8U)       /*!< Bit field size in bits for SDHC_VENDOR_INTSTVAL. */
04897 
04898 /*! @brief Read current value of the SDHC_VENDOR_INTSTVAL field. */
04899 #define BR_SDHC_VENDOR_INTSTVAL(x) (UNION_READ(hw_sdhc_vendor_t, HW_SDHC_VENDOR_ADDR(x), U, B.INTSTVAL))
04900 /*@}*/
04901 
04902 /*******************************************************************************
04903  * HW_SDHC_MMCBOOT - MMC Boot register
04904  ******************************************************************************/
04905 
04906 /*!
04907  * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW)
04908  *
04909  * Reset value: 0x00000000U
04910  *
04911  * This register contains the MMC fast boot control register.
04912  */
04913 typedef union _hw_sdhc_mmcboot
04914 {
04915     uint32_t U;
04916     struct _hw_sdhc_mmcboot_bitfields
04917     {
04918         uint32_t DTOCVACK : 4;         /*!< [3:0] Boot ACK Time Out Counter Value */
04919         uint32_t BOOTACK : 1;          /*!< [4] Boot Ack Mode Select */
04920         uint32_t BOOTMODE : 1;         /*!< [5] Boot Mode Select */
04921         uint32_t BOOTEN : 1;           /*!< [6] Boot Mode Enable */
04922         uint32_t AUTOSABGEN : 1;       /*!< [7]  */
04923         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
04924         uint32_t BOOTBLKCNT : 16;      /*!< [31:16]  */
04925     } B;
04926 } hw_sdhc_mmcboot_t;
04927 
04928 /*!
04929  * @name Constants and macros for entire SDHC_MMCBOOT register
04930  */
04931 /*@{*/
04932 #define HW_SDHC_MMCBOOT_ADDR(x)  ((x) + 0xC4U)
04933 
04934 #define HW_SDHC_MMCBOOT(x)       (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR(x))
04935 #define HW_SDHC_MMCBOOT_RD(x)    (ADDRESS_READ(hw_sdhc_mmcboot_t, HW_SDHC_MMCBOOT_ADDR(x)))
04936 #define HW_SDHC_MMCBOOT_WR(x, v) (ADDRESS_WRITE(hw_sdhc_mmcboot_t, HW_SDHC_MMCBOOT_ADDR(x), v))
04937 #define HW_SDHC_MMCBOOT_SET(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) |  (v)))
04938 #define HW_SDHC_MMCBOOT_CLR(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) & ~(v)))
04939 #define HW_SDHC_MMCBOOT_TOG(x, v) (HW_SDHC_MMCBOOT_WR(x, HW_SDHC_MMCBOOT_RD(x) ^  (v)))
04940 /*@}*/
04941 
04942 /*
04943  * Constants & macros for individual SDHC_MMCBOOT bitfields
04944  */
04945 
04946 /*!
04947  * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
04948  *
04949  * Values:
04950  * - 0000 - SDCLK x 2^8
04951  * - 0001 - SDCLK x 2^9
04952  * - 0010 - SDCLK x 2^10
04953  * - 0011 - SDCLK x 2^11
04954  * - 0100 - SDCLK x 2^12
04955  * - 0101 - SDCLK x 2^13
04956  * - 0110 - SDCLK x 2^14
04957  * - 0111 - SDCLK x 2^15
04958  * - 1110 - SDCLK x 2^22
04959  * - 1111 - Reserved
04960  */
04961 /*@{*/
04962 #define BP_SDHC_MMCBOOT_DTOCVACK (0U)      /*!< Bit position for SDHC_MMCBOOT_DTOCVACK. */
04963 #define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) /*!< Bit mask for SDHC_MMCBOOT_DTOCVACK. */
04964 #define BS_SDHC_MMCBOOT_DTOCVACK (4U)      /*!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK. */
04965 
04966 /*! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field. */
04967 #define BR_SDHC_MMCBOOT_DTOCVACK(x) (UNION_READ(hw_sdhc_mmcboot_t, HW_SDHC_MMCBOOT_ADDR(x), U, B.DTOCVACK))
04968 
04969 /*! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK. */
04970 #define BF_SDHC_MMCBOOT_DTOCVACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_DTOCVACK) & BM_SDHC_MMCBOOT_DTOCVACK)
04971 
04972 /*! @brief Set the DTOCVACK field to a new value. */
04973 #define BW_SDHC_MMCBOOT_DTOCVACK(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v)))
04974 /*@}*/
04975 
04976 /*!
04977  * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
04978  *
04979  * Values:
04980  * - 0 - No ack.
04981  * - 1 - Ack.
04982  */
04983 /*@{*/
04984 #define BP_SDHC_MMCBOOT_BOOTACK (4U)       /*!< Bit position for SDHC_MMCBOOT_BOOTACK. */
04985 #define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) /*!< Bit mask for SDHC_MMCBOOT_BOOTACK. */
04986 #define BS_SDHC_MMCBOOT_BOOTACK (1U)       /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK. */
04987 
04988 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field. */
04989 #define BR_SDHC_MMCBOOT_BOOTACK(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK)))
04990 
04991 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK. */
04992 #define BF_SDHC_MMCBOOT_BOOTACK(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTACK) & BM_SDHC_MMCBOOT_BOOTACK)
04993 
04994 /*! @brief Set the BOOTACK field to a new value. */
04995 #define BW_SDHC_MMCBOOT_BOOTACK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTACK), v))
04996 /*@}*/
04997 
04998 /*!
04999  * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
05000  *
05001  * Values:
05002  * - 0 - Normal boot.
05003  * - 1 - Alternative boot.
05004  */
05005 /*@{*/
05006 #define BP_SDHC_MMCBOOT_BOOTMODE (5U)      /*!< Bit position for SDHC_MMCBOOT_BOOTMODE. */
05007 #define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) /*!< Bit mask for SDHC_MMCBOOT_BOOTMODE. */
05008 #define BS_SDHC_MMCBOOT_BOOTMODE (1U)      /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE. */
05009 
05010 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field. */
05011 #define BR_SDHC_MMCBOOT_BOOTMODE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE)))
05012 
05013 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE. */
05014 #define BF_SDHC_MMCBOOT_BOOTMODE(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTMODE) & BM_SDHC_MMCBOOT_BOOTMODE)
05015 
05016 /*! @brief Set the BOOTMODE field to a new value. */
05017 #define BW_SDHC_MMCBOOT_BOOTMODE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTMODE), v))
05018 /*@}*/
05019 
05020 /*!
05021  * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
05022  *
05023  * Values:
05024  * - 0 - Fast boot disable.
05025  * - 1 - Fast boot enable.
05026  */
05027 /*@{*/
05028 #define BP_SDHC_MMCBOOT_BOOTEN (6U)        /*!< Bit position for SDHC_MMCBOOT_BOOTEN. */
05029 #define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) /*!< Bit mask for SDHC_MMCBOOT_BOOTEN. */
05030 #define BS_SDHC_MMCBOOT_BOOTEN (1U)        /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN. */
05031 
05032 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field. */
05033 #define BR_SDHC_MMCBOOT_BOOTEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN)))
05034 
05035 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN. */
05036 #define BF_SDHC_MMCBOOT_BOOTEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTEN) & BM_SDHC_MMCBOOT_BOOTEN)
05037 
05038 /*! @brief Set the BOOTEN field to a new value. */
05039 #define BW_SDHC_MMCBOOT_BOOTEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_BOOTEN), v))
05040 /*@}*/
05041 
05042 /*!
05043  * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
05044  *
05045  * When boot, enable auto stop at block gap function. This function will be
05046  * triggered, and host will stop at block gap when received card block cnt is equal
05047  * to BOOTBLKCNT.
05048  */
05049 /*@{*/
05050 #define BP_SDHC_MMCBOOT_AUTOSABGEN (7U)    /*!< Bit position for SDHC_MMCBOOT_AUTOSABGEN. */
05051 #define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) /*!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN. */
05052 #define BS_SDHC_MMCBOOT_AUTOSABGEN (1U)    /*!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN. */
05053 
05054 /*! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field. */
05055 #define BR_SDHC_MMCBOOT_AUTOSABGEN(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN)))
05056 
05057 /*! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN. */
05058 #define BF_SDHC_MMCBOOT_AUTOSABGEN(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_AUTOSABGEN) & BM_SDHC_MMCBOOT_AUTOSABGEN)
05059 
05060 /*! @brief Set the AUTOSABGEN field to a new value. */
05061 #define BW_SDHC_MMCBOOT_AUTOSABGEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_SDHC_MMCBOOT_ADDR(x), BP_SDHC_MMCBOOT_AUTOSABGEN), v))
05062 /*@}*/
05063 
05064 /*!
05065  * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
05066  *
05067  * Defines the stop at block gap value of automatic mode. When received card
05068  * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
05069  */
05070 /*@{*/
05071 #define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U)   /*!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT. */
05072 #define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) /*!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT. */
05073 #define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U)   /*!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT. */
05074 
05075 /*! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field. */
05076 #define BR_SDHC_MMCBOOT_BOOTBLKCNT(x) (UNION_READ(hw_sdhc_mmcboot_t, HW_SDHC_MMCBOOT_ADDR(x), U, B.BOOTBLKCNT))
05077 
05078 /*! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT. */
05079 #define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) ((uint32_t)((uint32_t)(v) << BP_SDHC_MMCBOOT_BOOTBLKCNT) & BM_SDHC_MMCBOOT_BOOTBLKCNT)
05080 
05081 /*! @brief Set the BOOTBLKCNT field to a new value. */
05082 #define BW_SDHC_MMCBOOT_BOOTBLKCNT(x, v) (HW_SDHC_MMCBOOT_WR(x, (HW_SDHC_MMCBOOT_RD(x) & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v)))
05083 /*@}*/
05084 
05085 /*******************************************************************************
05086  * HW_SDHC_HOSTVER - Host Controller Version
05087  ******************************************************************************/
05088 
05089 /*!
05090  * @brief HW_SDHC_HOSTVER - Host Controller Version (RO)
05091  *
05092  * Reset value: 0x00001201U
05093  *
05094  * This register contains the vendor host controller version information. All
05095  * bits are read only and will read the same as the power-reset value.
05096  */
05097 typedef union _hw_sdhc_hostver
05098 {
05099     uint32_t U;
05100     struct _hw_sdhc_hostver_bitfields
05101     {
05102         uint32_t SVN : 8;              /*!< [7:0] Specification Version Number */
05103         uint32_t VVN : 8;              /*!< [15:8] Vendor Version Number */
05104         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
05105     } B;
05106 } hw_sdhc_hostver_t;
05107 
05108 /*!
05109  * @name Constants and macros for entire SDHC_HOSTVER register
05110  */
05111 /*@{*/
05112 #define HW_SDHC_HOSTVER_ADDR(x)  ((x) + 0xFCU)
05113 
05114 #define HW_SDHC_HOSTVER(x)       (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR(x))
05115 #define HW_SDHC_HOSTVER_RD(x)    (ADDRESS_READ(hw_sdhc_hostver_t, HW_SDHC_HOSTVER_ADDR(x)))
05116 /*@}*/
05117 
05118 /*
05119  * Constants & macros for individual SDHC_HOSTVER bitfields
05120  */
05121 
05122 /*!
05123  * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
05124  *
05125  * These status bits indicate the host controller specification version.
05126  *
05127  * Values:
05128  * - 1 - SD host specification version 2.0, supports test event register and
05129  *     ADMA.
05130  */
05131 /*@{*/
05132 #define BP_SDHC_HOSTVER_SVN  (0U)          /*!< Bit position for SDHC_HOSTVER_SVN. */
05133 #define BM_SDHC_HOSTVER_SVN  (0x000000FFU) /*!< Bit mask for SDHC_HOSTVER_SVN. */
05134 #define BS_SDHC_HOSTVER_SVN  (8U)          /*!< Bit field size in bits for SDHC_HOSTVER_SVN. */
05135 
05136 /*! @brief Read current value of the SDHC_HOSTVER_SVN field. */
05137 #define BR_SDHC_HOSTVER_SVN(x) (UNION_READ(hw_sdhc_hostver_t, HW_SDHC_HOSTVER_ADDR(x), U, B.SVN))
05138 /*@}*/
05139 
05140 /*!
05141  * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
05142  *
05143  * These status bits are reserved for the vendor version number. The host driver
05144  * shall not use this status.
05145  *
05146  * Values:
05147  * - 0 - Freescale SDHC version 1.0
05148  * - 10000 - Freescale SDHC version 2.0
05149  * - 10001 - Freescale SDHC version 2.1
05150  * - 10010 - Freescale SDHC version 2.2
05151  */
05152 /*@{*/
05153 #define BP_SDHC_HOSTVER_VVN  (8U)          /*!< Bit position for SDHC_HOSTVER_VVN. */
05154 #define BM_SDHC_HOSTVER_VVN  (0x0000FF00U) /*!< Bit mask for SDHC_HOSTVER_VVN. */
05155 #define BS_SDHC_HOSTVER_VVN  (8U)          /*!< Bit field size in bits for SDHC_HOSTVER_VVN. */
05156 
05157 /*! @brief Read current value of the SDHC_HOSTVER_VVN field. */
05158 #define BR_SDHC_HOSTVER_VVN(x) (UNION_READ(hw_sdhc_hostver_t, HW_SDHC_HOSTVER_ADDR(x), U, B.VVN))
05159 /*@}*/
05160 
05161 /*******************************************************************************
05162  * hw_sdhc_t - module struct
05163  ******************************************************************************/
05164 /*!
05165  * @brief All SDHC module registers.
05166  */
05167 #pragma pack(1)
05168 typedef struct _hw_sdhc
05169 {
05170     __IO hw_sdhc_dsaddr_t DSADDR ;          /*!< [0x0] DMA System Address register */
05171     __IO hw_sdhc_blkattr_t BLKATTR ;        /*!< [0x4] Block Attributes register */
05172     __IO hw_sdhc_cmdarg_t CMDARG ;          /*!< [0x8] Command Argument register */
05173     __IO hw_sdhc_xfertyp_t XFERTYP ;        /*!< [0xC] Transfer Type register */
05174     __I hw_sdhc_cmdrsp0_t CMDRSP0 ;         /*!< [0x10] Command Response 0 */
05175     __I hw_sdhc_cmdrsp1_t CMDRSP1 ;         /*!< [0x14] Command Response 1 */
05176     __I hw_sdhc_cmdrsp2_t CMDRSP2 ;         /*!< [0x18] Command Response 2 */
05177     __I hw_sdhc_cmdrsp3_t CMDRSP3 ;         /*!< [0x1C] Command Response 3 */
05178     __IO hw_sdhc_datport_t DATPORT ;        /*!< [0x20] Buffer Data Port register */
05179     __I hw_sdhc_prsstat_t PRSSTAT ;         /*!< [0x24] Present State register */
05180     __IO hw_sdhc_proctl_t PROCTL ;          /*!< [0x28] Protocol Control register */
05181     __IO hw_sdhc_sysctl_t SYSCTL ;          /*!< [0x2C] System Control register */
05182     __IO hw_sdhc_irqstat_t IRQSTAT ;        /*!< [0x30] Interrupt Status register */
05183     __IO hw_sdhc_irqstaten_t IRQSTATEN ;    /*!< [0x34] Interrupt Status Enable register */
05184     __IO hw_sdhc_irqsigen_t IRQSIGEN ;      /*!< [0x38] Interrupt Signal Enable register */
05185     __I hw_sdhc_ac12err_t AC12ERR ;         /*!< [0x3C] Auto CMD12 Error Status Register */
05186     __I hw_sdhc_htcapblt_t HTCAPBLT ;       /*!< [0x40] Host Controller Capabilities */
05187     __IO hw_sdhc_wml_t WML ;                /*!< [0x44] Watermark Level Register */
05188     uint8_t _reserved0[8];
05189     __O hw_sdhc_fevt_t FEVT ;               /*!< [0x50] Force Event register */
05190     __I hw_sdhc_admaes_t ADMAES ;           /*!< [0x54] ADMA Error Status register */
05191     __IO hw_sdhc_adsaddr_t ADSADDR ;        /*!< [0x58] ADMA System Addressregister */
05192     uint8_t _reserved1[100];
05193     __IO hw_sdhc_vendor_t VENDOR ;          /*!< [0xC0] Vendor Specific register */
05194     __IO hw_sdhc_mmcboot_t MMCBOOT ;        /*!< [0xC4] MMC Boot register */
05195     uint8_t _reserved2[52];
05196     __I hw_sdhc_hostver_t HOSTVER ;         /*!< [0xFC] Host Controller Version */
05197 } hw_sdhc_t;
05198 #pragma pack()
05199 
05200 /*! @brief Macro to access all SDHC registers. */
05201 /*! @param x SDHC module instance base address. */
05202 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
05203  *     use the '&' operator, like <code>&HW_SDHC(SDHC_BASE)</code>. */
05204 #define HW_SDHC(x)     (*(hw_sdhc_t *)(x))
05205 
05206 #endif /* __HW_SDHC_REGISTERS_H__ */
05207 /* EOF */