_hw_sdhc_irqstat Union Reference

HW_SDHC_IRQSTAT - Interrupt Status register (RW) More...

#include <MK64F12_sdhc.h>

Detailed Description

HW_SDHC_IRQSTAT - Interrupt Status register (RW)

Reset value: 0x00000000U

An interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1. For all bits, writing 1 to a bit clears it; writing to 0 keeps the bit unchanged. More than one status can be cleared with a single register write. For Card Interrupt, before writing 1 to clear, it is required that the card stops asserting the interrupt, meaning that when the Card Driver services the interrupt condition, otherwise the CINT bit will be asserted again. The table below shows the relationship between the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command complete Command timeout error Meaning of the status 0 0 X X 1 Response not received within 64 SDCLK cycles 1 0 Response received The table below shows the relationship between the Transfer Complete and the Data Timeout Error. SDHC status for data timeout error/transfer complete bit combinations Transfer complete Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during transfer 1 X Data transfer complete The table below shows the relationship between the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1 CMD line conflict

Definition at line 2349 of file MK64F12_sdhc.h.