_hw_sdhc_xfertyp Union Reference

HW_SDHC_XFERTYP - Transfer Type register (RW) More...

#include <MK64F12_sdhc.h>

Detailed Description

HW_SDHC_XFERTYP - Transfer Type register (RW)

Reset value: 0x00000000U

This register is used to control the operation of data transfers. The host driver shall set this register before issuing a command followed by a data transfer, or before issuing a resume command. To prevent data loss, the SDHC prevents writing to the bits that are involved in the data transfer of this register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN, BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB] before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to send a command with data by writing to this register is ignored; when PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with data transfer involved, it is mandatory that the block size is nonzero. Besides, block count must also be nonzero, or indicated as single block transfer (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of this register is 0 when written), otherwise SDHC will ignore the sending of this command and do nothing. For write command, with all above restrictions, it is also mandatory that the write protect switch is not active (WPSPL bit of Present State Register is 1), otherwise SDHC will also ignore the command. If the commands with data transfer does not receive the response in 64 clock cycles, that is, response time-out, SDHC will regard the external device does not accept the command and abort the data transfer. In this scenario, the driver must issue the command again to retry the transfer. It is also possible that, for some reason, the card responds to the command but SDHC does not receive the response, and if it is internal DMA (either simple DMA or ADMA) read operation, the external system memory is over-written by the internal DMA with data sent back from the card. The following table shows the summary of how register settings determine the type of data transfer. Transfer Type register setting for various transfer types Multi/Single block select Block count enable Block count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN], in regards to XFERTYP[RSPTYP] as well as the name of the response type. Relationship between parameters and the name of the response type Response type (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In the SDIO specification, response type notation for R5b is not defined. R5 includes R5b in the SDIO specification. But R5b is defined in this specification to specify that the SDHC will check the busy status after receiving a response. For example, usually CMD52 is used with R5, but the I/O abort command shall be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits. The CRC check shall be disabled for these response types.

Definition at line 436 of file MK64F12_sdhc.h.